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1 5 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
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////  Versatile library, memories                                 ////
4
////                                                              ////
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////  Description                                                 ////
6
////  memories                                                    ////
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////                                                              ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - add more memory types                                    ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
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////        ORSoC AB                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
17
////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
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////                                                              ////
37
//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
42
 
43 40 unneback
`ifdef ROM_INIT
44 5 unneback
/// ROM
45 40 unneback
`define MODULE rom_init
46
module `BASE`MODULE ( adr, q, clk);
47
`undef MODULE
48 5 unneback
 
49 7 unneback
   parameter data_width = 32;
50
   parameter addr_width = 8;
51
   input [(addr_width-1):0]       adr;
52
   output reg [(data_width-1):0] q;
53
   input                         clk;
54
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
55
   parameter memory_file = "vl_rom.vmem";
56
   initial
57
     begin
58
        $readmemh(memory_file, rom);
59
     end
60
 
61
   always @ (posedge clk)
62
     q <= rom[adr];
63 5 unneback
 
64 7 unneback
endmodule
65 40 unneback
`endif
66 7 unneback
 
67 14 unneback
/*
68 7 unneback
module vl_rom ( adr, q, clk);
69
 
70 5 unneback
parameter data_width = 32;
71
parameter addr_width = 4;
72
 
73
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
74
    {32'h18000000},
75
    {32'hA8200000},
76
    {32'hA8200000},
77
    {32'hA8200000},
78
    {32'h44003000},
79
    {32'h15000000},
80
    {32'h15000000},
81
    {32'h15000000},
82
    {32'h15000000},
83
    {32'h15000000},
84
    {32'h15000000},
85
    {32'h15000000},
86
    {32'h15000000},
87
    {32'h15000000},
88
    {32'h15000000},
89
    {32'h15000000}};
90
 
91 7 unneback
input [addr_width-1:0] adr;
92 5 unneback
output reg [data_width-1:0] q;
93
input clk;
94
 
95
always @ (posedge clk)
96 7 unneback
    q <= data[adr];
97 5 unneback
 
98
endmodule
99 14 unneback
*/
100 40 unneback
 
101
`ifdef RAM
102
`define MODULE ram
103 5 unneback
// Single port RAM
104 40 unneback
module `BASE`MODULE ( d, adr, we, q, clk);
105
`undef MODULE
106 5 unneback
 
107
   parameter data_width = 32;
108
   parameter addr_width = 8;
109
   input [(data_width-1):0]      d;
110
   input [(addr_width-1):0]       adr;
111
   input                         we;
112 7 unneback
   output reg [(data_width-1):0] q;
113 5 unneback
   input                         clk;
114
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
115 7 unneback
   parameter init = 0;
116
   parameter memory_file = "vl_ram.vmem";
117
   generate if (init) begin : init_mem
118
   initial
119
     begin
120
        $readmemh(memory_file, ram);
121
     end
122
   end
123
   endgenerate
124
 
125 5 unneback
   always @ (posedge clk)
126
   begin
127
   if (we)
128
     ram[adr] <= d;
129
   q <= ram[adr];
130
   end
131
 
132
endmodule
133 40 unneback
`endif
134 5 unneback
 
135 40 unneback
`ifdef RAM_BE
136
`define MODULE ram_be
137
module `BASE`MODULE ( d, adr, be, we, q, clk);
138
`undef MODULE
139
 
140 7 unneback
   parameter data_width = 32;
141
   parameter addr_width = 8;
142
   input [(data_width-1):0]      d;
143
   input [(addr_width-1):0]       adr;
144
   input [(addr_width/4)-1:0]    be;
145
   input                         we;
146
   output reg [(data_width-1):0] q;
147
   input                         clk;
148
 
149
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
150
 
151
   parameter init = 0;
152
   parameter memory_file = "vl_ram.vmem";
153
   generate if (init) begin : init_mem
154
   initial
155
     begin
156
        $readmemh(memory_file, ram);
157
     end
158
   end
159
   endgenerate
160
 
161
   genvar i;
162
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
163
      always @ (posedge clk)
164
      if (we & be[i])
165
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
166
   end
167
   endgenerate
168
 
169
   always @ (posedge clk)
170
      q <= ram[adr];
171
 
172
endmodule
173 40 unneback
`endif
174 7 unneback
 
175 5 unneback
// Dual port RAM
176
 
177
// ACTEL FPGA should not use logic to handle rw collision
178
`ifdef ACTEL
179
        `define SYN /*synthesis syn_ramstyle = "no_rw_check"*/
180
`else
181
        `define SYN
182
`endif
183
 
184 40 unneback
`ifdef DPRAM_1R1W
185
`define MODULE dpram_1r1w
186
module `BASE`MODULE ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
187
`undef MODULE
188 5 unneback
   parameter data_width = 32;
189
   parameter addr_width = 8;
190
   input [(data_width-1):0]      d_a;
191
   input [(addr_width-1):0]       adr_a;
192
   input [(addr_width-1):0]       adr_b;
193
   input                         we_a;
194
   output [(data_width-1):0]      q_b;
195
   input                         clk_a, clk_b;
196
   reg [(addr_width-1):0]         adr_b_reg;
197
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
198 7 unneback
 
199
   parameter init = 0;
200
   parameter memory_file = "vl_ram.vmem";
201
   generate if (init) begin : init_mem
202
   initial
203
     begin
204
        $readmemh(memory_file, ram);
205
     end
206
   end
207
   endgenerate
208
 
209 5 unneback
   always @ (posedge clk_a)
210
   if (we_a)
211
     ram[adr_a] <= d_a;
212
   always @ (posedge clk_b)
213
   adr_b_reg <= adr_b;
214
   assign q_b = ram[adr_b_reg];
215 40 unneback
 
216 5 unneback
endmodule
217 40 unneback
`endif
218 5 unneback
 
219 40 unneback
`ifdef DPRAM_2R1W
220
`define MODULE dpram_2r1w
221
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
222
`undef MODULE
223
 
224 5 unneback
   parameter data_width = 32;
225
   parameter addr_width = 8;
226
   input [(data_width-1):0]      d_a;
227
   input [(addr_width-1):0]       adr_a;
228
   input [(addr_width-1):0]       adr_b;
229
   input                         we_a;
230
   output [(data_width-1):0]      q_b;
231
   output reg [(data_width-1):0] q_a;
232
   input                         clk_a, clk_b;
233
   reg [(data_width-1):0]         q_b;
234
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
235 7 unneback
 
236
   parameter init = 0;
237
   parameter memory_file = "vl_ram.vmem";
238
   generate if (init) begin : init_mem
239
   initial
240
     begin
241
        $readmemh(memory_file, ram);
242
     end
243
   end
244
   endgenerate
245
 
246 5 unneback
   always @ (posedge clk_a)
247
     begin
248
        q_a <= ram[adr_a];
249
        if (we_a)
250
             ram[adr_a] <= d_a;
251
     end
252
   always @ (posedge clk_b)
253
          q_b <= ram[adr_b];
254
endmodule
255 40 unneback
`endif
256 5 unneback
 
257 40 unneback
`ifdef DPRAM_2R2W
258
`define MODULE dpram_2r2w
259
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
260
`undef MODULE
261
 
262 5 unneback
   parameter data_width = 32;
263
   parameter addr_width = 8;
264
   input [(data_width-1):0]      d_a;
265
   input [(addr_width-1):0]       adr_a;
266
   input [(addr_width-1):0]       adr_b;
267
   input                         we_a;
268
   output [(data_width-1):0]      q_b;
269
   input [(data_width-1):0]       d_b;
270
   output reg [(data_width-1):0] q_a;
271
   input                         we_b;
272
   input                         clk_a, clk_b;
273
   reg [(data_width-1):0]         q_b;
274
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
275 7 unneback
 
276
   parameter init = 0;
277
   parameter memory_file = "vl_ram.vmem";
278
   generate if (init) begin : init_mem
279
   initial
280
     begin
281
        $readmemh(memory_file, ram);
282
     end
283
   end
284
   endgenerate
285
 
286 5 unneback
   always @ (posedge clk_a)
287
     begin
288
        q_a <= ram[adr_a];
289
        if (we_a)
290
             ram[adr_a] <= d_a;
291
     end
292
   always @ (posedge clk_b)
293
     begin
294
        q_b <= ram[adr_b];
295
        if (we_b)
296
          ram[adr_b] <= d_b;
297
     end
298
endmodule
299 40 unneback
`endif
300 5 unneback
 
301
// Content addresable memory, CAM
302
 
303 40 unneback
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
304 5 unneback
// FIFO
305 40 unneback
`define MODULE fifo_1r1w_fill_level_sync
306
module `BASE`MODULE (
307
`undef MODULE
308 25 unneback
    d, wr, fifo_full,
309
    q, rd, fifo_empty,
310
    fill_level,
311
    clk, rst
312
    );
313
 
314
parameter data_width = 18;
315
parameter addr_width = 4;
316 5 unneback
 
317 25 unneback
// write side
318
input  [data_width-1:0] d;
319
input                   wr;
320
output                  fifo_full;
321
// read side
322
output [data_width-1:0] q;
323
input                   rd;
324
output                  fifo_empty;
325
// common
326
output [addr_width:0]   fill_level;
327
input rst, clk;
328
 
329
wire [addr_width:1] wadr, radr;
330
 
331 40 unneback
`define MODULE cnt_bin_ce
332
`BASE`MODULE
333 25 unneback
    # ( .length(addr_width))
334
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
335 40 unneback
`BASE`MODULE
336 25 unneback
    # (.length(addr_width))
337
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
338 40 unneback
`undef MODULE
339 25 unneback
 
340 40 unneback
`define MODULE dpram_1r1w
341
`BASE`MODULE
342 25 unneback
    # (.data_width(data_width), .addr_width(addr_width))
343
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
344 40 unneback
`undef MODULE
345 25 unneback
 
346 40 unneback
`define MODULE cnt_bin_ce_rew_q_zq_l1
347
`BASE`MODULE
348 27 unneback
    # (.length(addr_width+1), .level1_value(1<<addr_width))
349 25 unneback
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
350 40 unneback
`undef MODULE
351 25 unneback
endmodule
352 40 unneback
`endif
353 25 unneback
 
354 40 unneback
`ifdef FIFO_2R2W_SYNC_SIMPLEX
355 27 unneback
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
356
// RAM is supposed to be larger than the two FIFOs
357
// LFSR counters used adr pointers
358 40 unneback
`define MODULE fifo_2r2w_sync_simplex
359
module `BASE`MODULE (
360
`undef MODULE
361 27 unneback
    // a side
362
    a_d, a_wr, a_fifo_full,
363
    a_q, a_rd, a_fifo_empty,
364
    a_fill_level,
365
    // b side
366
    b_d, b_wr, b_fifo_full,
367
    b_q, b_rd, b_fifo_empty,
368
    b_fill_level,
369
    // common
370
    clk, rst
371
    );
372
parameter data_width = 8;
373
parameter addr_width = 5;
374
parameter fifo_full_level = (1<<addr_width)-1;
375
 
376
// a side
377
input  [data_width-1:0] a_d;
378
input                   a_wr;
379
output                  a_fifo_full;
380
output [data_width-1:0] a_q;
381
input                   a_rd;
382
output                  a_fifo_empty;
383
output [addr_width-1:0] a_fill_level;
384
 
385
// b side
386
input  [data_width-1:0] b_d;
387
input                   b_wr;
388
output                  b_fifo_full;
389
output [data_width-1:0] b_q;
390
input                   b_rd;
391
output                  b_fifo_empty;
392
output [addr_width-1:0] b_fill_level;
393
 
394
input                   clk;
395
input                   rst;
396
 
397
// adr_gen
398
wire [addr_width:1] a_wadr, a_radr;
399
wire [addr_width:1] b_wadr, b_radr;
400
// dpram
401
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
402
 
403 40 unneback
`define MODULE cnt_lfsr_ce
404
`BASE`MODULE
405 27 unneback
    # ( .length(addr_width))
406
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
407
 
408 40 unneback
`BASE`MODULE
409 27 unneback
    # (.length(addr_width))
410
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
411
 
412 40 unneback
`BASE`MODULE
413 27 unneback
    # ( .length(addr_width))
414
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
415
 
416 40 unneback
`BASE`MODULE
417 27 unneback
    # (.length(addr_width))
418
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
419 40 unneback
`undef MODULE
420 27 unneback
 
421
// mux read or write adr to DPRAM
422
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
423
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
424
 
425 40 unneback
`define MODULE dpram_2r2w
426
`BASE`MODULE
427 27 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
428
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
429
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
430 40 unneback
`undef MODULE
431
 
432
`define MODULE cnt_bin_ce_rew_zq_l1
433
`BASE`MODULE
434 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
435 27 unneback
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
436
 
437 40 unneback
`BASE`MODULE
438 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
439 27 unneback
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
440 40 unneback
`undef MODULE
441 27 unneback
 
442
endmodule
443 40 unneback
`endif
444 27 unneback
 
445 40 unneback
`ifdef FIFO_CMP_ASYNC
446
`define MODULE fifo_cmp_async
447
module `BASE`MODULE ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
448
`undef MODULE
449 5 unneback
 
450 11 unneback
   parameter addr_width = 4;
451
   parameter N = addr_width-1;
452 5 unneback
 
453
   parameter Q1 = 2'b00;
454
   parameter Q2 = 2'b01;
455
   parameter Q3 = 2'b11;
456
   parameter Q4 = 2'b10;
457
 
458
   parameter going_empty = 1'b0;
459
   parameter going_full  = 1'b1;
460
 
461
   input [N:0]  wptr, rptr;
462 14 unneback
   output       fifo_empty;
463 5 unneback
   output       fifo_full;
464
   input        wclk, rclk, rst;
465
 
466
`ifndef GENERATE_DIRECTION_AS_LATCH
467
   wire direction;
468
`endif
469
`ifdef GENERATE_DIRECTION_AS_LATCH
470
   reg direction;
471
`endif
472
   reg  direction_set, direction_clr;
473
 
474
   wire async_empty, async_full;
475
   wire fifo_full2;
476 14 unneback
   wire fifo_empty2;
477 5 unneback
 
478
   // direction_set
479
   always @ (wptr[N:N-1] or rptr[N:N-1])
480
     case ({wptr[N:N-1],rptr[N:N-1]})
481
       {Q1,Q2} : direction_set <= 1'b1;
482
       {Q2,Q3} : direction_set <= 1'b1;
483
       {Q3,Q4} : direction_set <= 1'b1;
484
       {Q4,Q1} : direction_set <= 1'b1;
485
       default : direction_set <= 1'b0;
486
     endcase
487
 
488
   // direction_clear
489
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
490
     if (rst)
491
       direction_clr <= 1'b1;
492
     else
493
       case ({wptr[N:N-1],rptr[N:N-1]})
494
         {Q2,Q1} : direction_clr <= 1'b1;
495
         {Q3,Q2} : direction_clr <= 1'b1;
496
         {Q4,Q3} : direction_clr <= 1'b1;
497
         {Q1,Q4} : direction_clr <= 1'b1;
498
         default : direction_clr <= 1'b0;
499
       endcase
500
 
501 40 unneback
`define MODULE dff_sr
502 5 unneback
`ifndef GENERATE_DIRECTION_AS_LATCH
503 40 unneback
    `BASE`MODULE dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
504 5 unneback
`endif
505
 
506
`ifdef GENERATE_DIRECTION_AS_LATCH
507
   always @ (posedge direction_set or posedge direction_clr)
508
     if (direction_clr)
509
       direction <= going_empty;
510
     else
511
       direction <= going_full;
512
`endif
513
 
514
   assign async_empty = (wptr == rptr) && (direction==going_empty);
515
   assign async_full  = (wptr == rptr) && (direction==going_full);
516
 
517 40 unneback
    `BASE`MODULE dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
518
    `BASE`MODULE dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
519
`undef MODULE
520 5 unneback
 
521
/*
522
   always @ (posedge wclk or posedge rst or posedge async_full)
523
     if (rst)
524
       {fifo_full, fifo_full2} <= 2'b00;
525
     else if (async_full)
526
       {fifo_full, fifo_full2} <= 2'b11;
527
     else
528
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
529
*/
530 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
531 5 unneback
     if (async_empty)
532
       {fifo_empty, fifo_empty2} <= 2'b11;
533
     else
534 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
535 40 unneback
`define MODULE dff
536
    `BASE`MODULE # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
537
    `BASE`MODULE # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
538
`undef MODULE
539 25 unneback
endmodule // async_compb
540 40 unneback
`endif
541 5 unneback
 
542 40 unneback
`ifdef FIFO_1R1W_ASYNC
543
`define MODULE fifo_1r1w_async
544
module `BASE`MODULE (
545
`undef MODULE
546 5 unneback
    d, wr, fifo_full, wr_clk, wr_rst,
547
    q, rd, fifo_empty, rd_clk, rd_rst
548
    );
549
 
550
parameter data_width = 18;
551
parameter addr_width = 4;
552
 
553
// write side
554
input  [data_width-1:0] d;
555
input                   wr;
556
output                  fifo_full;
557
input                   wr_clk;
558
input                   wr_rst;
559
// read side
560
output [data_width-1:0] q;
561
input                   rd;
562
output                  fifo_empty;
563
input                   rd_clk;
564
input                   rd_rst;
565
 
566
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
567 23 unneback
 
568 40 unneback
`define MODULE cnt_gray_ce_bin
569
`BASE`MODULE
570 5 unneback
    # ( .length(addr_width))
571
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
572
 
573 40 unneback
`BASE`MODULE
574 5 unneback
    # (.length(addr_width))
575 23 unneback
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
576 40 unneback
`undef MODULE
577 5 unneback
 
578 40 unneback
`define MODULE dpram_1r1w
579
`BASE`MODULE
580 5 unneback
    # (.data_width(data_width), .addr_width(addr_width))
581
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
582 40 unneback
`undef MODULE
583 5 unneback
 
584 40 unneback
`define MODULE fifo_cmp_async
585
`BASE`MODULE
586 5 unneback
    # (.addr_width(addr_width))
587
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
588 40 unneback
`undef MODULE
589 5 unneback
 
590
endmodule
591 40 unneback
`endif
592 5 unneback
 
593 40 unneback
`ifdef FIFO_2R2W_ASYNC
594
`define MODULE fifo_2r2w_async
595
module `BASE`MODULE (
596
`undef MODULE
597 5 unneback
    // a side
598
    a_d, a_wr, a_fifo_full,
599
    a_q, a_rd, a_fifo_empty,
600
    a_clk, a_rst,
601
    // b side
602
    b_d, b_wr, b_fifo_full,
603
    b_q, b_rd, b_fifo_empty,
604
    b_clk, b_rst
605
    );
606
 
607
parameter data_width = 18;
608
parameter addr_width = 4;
609
 
610
// a side
611
input  [data_width-1:0] a_d;
612
input                   a_wr;
613
output                  a_fifo_full;
614
output [data_width-1:0] a_q;
615
input                   a_rd;
616
output                  a_fifo_empty;
617
input                   a_clk;
618
input                   a_rst;
619
 
620
// b side
621
input  [data_width-1:0] b_d;
622
input                   b_wr;
623
output                  b_fifo_full;
624
output [data_width-1:0] b_q;
625
input                   b_rd;
626
output                  b_fifo_empty;
627
input                   b_clk;
628
input                   b_rst;
629
 
630 40 unneback
`define MODULE fifo_1r1w_async
631
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
632 5 unneback
vl_fifo_1r1w_async_a (
633
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
634
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
635
    );
636
 
637 40 unneback
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
638 5 unneback
vl_fifo_1r1w_async_b (
639
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
640
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
641
    );
642 40 unneback
`undef MODULE
643
 
644 5 unneback
endmodule
645 40 unneback
`endif
646 5 unneback
 
647 40 unneback
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
648
`define MODULE fifo_2r2w_async_simplex
649
module `BASE`MODULE (
650
`undef MODULE
651 5 unneback
    // a side
652
    a_d, a_wr, a_fifo_full,
653
    a_q, a_rd, a_fifo_empty,
654
    a_clk, a_rst,
655
    // b side
656
    b_d, b_wr, b_fifo_full,
657
    b_q, b_rd, b_fifo_empty,
658
    b_clk, b_rst
659
    );
660
 
661
parameter data_width = 18;
662
parameter addr_width = 4;
663
 
664
// a side
665
input  [data_width-1:0] a_d;
666
input                   a_wr;
667
output                  a_fifo_full;
668
output [data_width-1:0] a_q;
669
input                   a_rd;
670
output                  a_fifo_empty;
671
input                   a_clk;
672
input                   a_rst;
673
 
674
// b side
675
input  [data_width-1:0] b_d;
676
input                   b_wr;
677
output                  b_fifo_full;
678
output [data_width-1:0] b_q;
679
input                   b_rd;
680
output                  b_fifo_empty;
681
input                   b_clk;
682
input                   b_rst;
683
 
684
// adr_gen
685
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
686
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
687
// dpram
688
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
689
 
690 40 unneback
`define MODULE cnt_gray_ce_bin
691
`BASE`MODULE
692 5 unneback
    # ( .length(addr_width))
693
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
694
 
695 40 unneback
`BASE`MODULE
696 5 unneback
    # (.length(addr_width))
697
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
698
 
699 40 unneback
`BASE`MODULE
700 5 unneback
    # ( .length(addr_width))
701
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
702
 
703 40 unneback
`BASE`MODULE
704 5 unneback
    # (.length(addr_width))
705
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
706 40 unneback
`undef MODULE
707 5 unneback
 
708
// mux read or write adr to DPRAM
709
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
710
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
711
 
712 40 unneback
`define MODULE dpram_2r2w
713
`BASE`MODULE
714 5 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
715
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
716
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
717 40 unneback
`undef MODULE
718 5 unneback
 
719 40 unneback
`define MODULE fifo_cmp_async
720
`BASE`MODULE
721 5 unneback
    # (.addr_width(addr_width))
722
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
723
 
724 40 unneback
`BASE`MODULE
725 5 unneback
    # (.addr_width(addr_width))
726
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
727 40 unneback
`undef MODULE
728 5 unneback
 
729
endmodule
730 40 unneback
`endif

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