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1 5 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
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////  Versatile library, memories                                 ////
4
////                                                              ////
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////  Description                                                 ////
6
////  memories                                                    ////
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////                                                              ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - add more memory types                                    ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
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////        ORSoC AB                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
42
 
43 40 unneback
`ifdef ROM_INIT
44 5 unneback
/// ROM
45 40 unneback
`define MODULE rom_init
46
module `BASE`MODULE ( adr, q, clk);
47
`undef MODULE
48 5 unneback
 
49 7 unneback
   parameter data_width = 32;
50
   parameter addr_width = 8;
51
   input [(addr_width-1):0]       adr;
52
   output reg [(data_width-1):0] q;
53
   input                         clk;
54
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
55
   parameter memory_file = "vl_rom.vmem";
56
   initial
57
     begin
58
        $readmemh(memory_file, rom);
59
     end
60
 
61
   always @ (posedge clk)
62
     q <= rom[adr];
63 5 unneback
 
64 7 unneback
endmodule
65 40 unneback
`endif
66 7 unneback
 
67 40 unneback
`ifdef RAM
68
`define MODULE ram
69 5 unneback
// Single port RAM
70 40 unneback
module `BASE`MODULE ( d, adr, we, q, clk);
71
`undef MODULE
72 5 unneback
 
73
   parameter data_width = 32;
74
   parameter addr_width = 8;
75
   input [(data_width-1):0]      d;
76
   input [(addr_width-1):0]       adr;
77
   input                         we;
78 7 unneback
   output reg [(data_width-1):0] q;
79 5 unneback
   input                         clk;
80
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
81 7 unneback
   parameter init = 0;
82
   parameter memory_file = "vl_ram.vmem";
83
   generate if (init) begin : init_mem
84
   initial
85
     begin
86
        $readmemh(memory_file, ram);
87
     end
88
   end
89
   endgenerate
90
 
91 5 unneback
   always @ (posedge clk)
92
   begin
93
   if (we)
94
     ram[adr] <= d;
95
   q <= ram[adr];
96
   end
97
 
98
endmodule
99 40 unneback
`endif
100 5 unneback
 
101 40 unneback
`ifdef RAM_BE
102
`define MODULE ram_be
103
module `BASE`MODULE ( d, adr, be, we, q, clk);
104
`undef MODULE
105
 
106 7 unneback
   parameter data_width = 32;
107
   parameter addr_width = 8;
108
   input [(data_width-1):0]      d;
109
   input [(addr_width-1):0]       adr;
110
   input [(addr_width/4)-1:0]    be;
111
   input                         we;
112
   output reg [(data_width-1):0] q;
113
   input                         clk;
114
 
115
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
116
 
117
   parameter init = 0;
118
   parameter memory_file = "vl_ram.vmem";
119
   generate if (init) begin : init_mem
120
   initial
121
     begin
122
        $readmemh(memory_file, ram);
123
     end
124
   end
125
   endgenerate
126
 
127
   genvar i;
128
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
129
      always @ (posedge clk)
130
      if (we & be[i])
131
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
132
   end
133
   endgenerate
134
 
135
   always @ (posedge clk)
136
      q <= ram[adr];
137
 
138
endmodule
139 40 unneback
`endif
140 7 unneback
 
141 5 unneback
`ifdef ACTEL
142 48 unneback
        // ACTEL FPGA should not use logic to handle rw collision
143 5 unneback
        `define SYN /*synthesis syn_ramstyle = "no_rw_check"*/
144
`else
145
        `define SYN
146
`endif
147
 
148 40 unneback
`ifdef DPRAM_1R1W
149
`define MODULE dpram_1r1w
150
module `BASE`MODULE ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
151
`undef MODULE
152 5 unneback
   parameter data_width = 32;
153
   parameter addr_width = 8;
154
   input [(data_width-1):0]      d_a;
155
   input [(addr_width-1):0]       adr_a;
156
   input [(addr_width-1):0]       adr_b;
157
   input                         we_a;
158
   output [(data_width-1):0]      q_b;
159
   input                         clk_a, clk_b;
160
   reg [(addr_width-1):0]         adr_b_reg;
161
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
162 7 unneback
 
163
   parameter init = 0;
164
   parameter memory_file = "vl_ram.vmem";
165
   generate if (init) begin : init_mem
166
   initial
167
     begin
168
        $readmemh(memory_file, ram);
169
     end
170
   end
171
   endgenerate
172
 
173 5 unneback
   always @ (posedge clk_a)
174
   if (we_a)
175
     ram[adr_a] <= d_a;
176
   always @ (posedge clk_b)
177
   adr_b_reg <= adr_b;
178
   assign q_b = ram[adr_b_reg];
179 40 unneback
 
180 5 unneback
endmodule
181 40 unneback
`endif
182 5 unneback
 
183 40 unneback
`ifdef DPRAM_2R1W
184
`define MODULE dpram_2r1w
185
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
186
`undef MODULE
187
 
188 5 unneback
   parameter data_width = 32;
189
   parameter addr_width = 8;
190
   input [(data_width-1):0]      d_a;
191
   input [(addr_width-1):0]       adr_a;
192
   input [(addr_width-1):0]       adr_b;
193
   input                         we_a;
194
   output [(data_width-1):0]      q_b;
195
   output reg [(data_width-1):0] q_a;
196
   input                         clk_a, clk_b;
197
   reg [(data_width-1):0]         q_b;
198
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
199 7 unneback
 
200
   parameter init = 0;
201
   parameter memory_file = "vl_ram.vmem";
202
   generate if (init) begin : init_mem
203
   initial
204
     begin
205
        $readmemh(memory_file, ram);
206
     end
207
   end
208
   endgenerate
209
 
210 5 unneback
   always @ (posedge clk_a)
211
     begin
212
        q_a <= ram[adr_a];
213
        if (we_a)
214
             ram[adr_a] <= d_a;
215
     end
216
   always @ (posedge clk_b)
217
          q_b <= ram[adr_b];
218
endmodule
219 40 unneback
`endif
220 5 unneback
 
221 40 unneback
`ifdef DPRAM_2R2W
222
`define MODULE dpram_2r2w
223
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
224
`undef MODULE
225
 
226 5 unneback
   parameter data_width = 32;
227
   parameter addr_width = 8;
228
   input [(data_width-1):0]      d_a;
229
   input [(addr_width-1):0]       adr_a;
230
   input [(addr_width-1):0]       adr_b;
231
   input                         we_a;
232
   output [(data_width-1):0]      q_b;
233
   input [(data_width-1):0]       d_b;
234
   output reg [(data_width-1):0] q_a;
235
   input                         we_b;
236
   input                         clk_a, clk_b;
237
   reg [(data_width-1):0]         q_b;
238
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
239 7 unneback
 
240
   parameter init = 0;
241
   parameter memory_file = "vl_ram.vmem";
242
   generate if (init) begin : init_mem
243
   initial
244
     begin
245
        $readmemh(memory_file, ram);
246
     end
247
   end
248
   endgenerate
249
 
250 5 unneback
   always @ (posedge clk_a)
251
     begin
252
        q_a <= ram[adr_a];
253
        if (we_a)
254
             ram[adr_a] <= d_a;
255
     end
256
   always @ (posedge clk_b)
257
     begin
258
        q_b <= ram[adr_b];
259
        if (we_b)
260
          ram[adr_b] <= d_b;
261
     end
262
endmodule
263 40 unneback
`endif
264 5 unneback
 
265
// Content addresable memory, CAM
266
 
267 40 unneback
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
268 5 unneback
// FIFO
269 40 unneback
`define MODULE fifo_1r1w_fill_level_sync
270
module `BASE`MODULE (
271
`undef MODULE
272 25 unneback
    d, wr, fifo_full,
273
    q, rd, fifo_empty,
274
    fill_level,
275
    clk, rst
276
    );
277
 
278
parameter data_width = 18;
279
parameter addr_width = 4;
280 5 unneback
 
281 25 unneback
// write side
282
input  [data_width-1:0] d;
283
input                   wr;
284
output                  fifo_full;
285
// read side
286
output [data_width-1:0] q;
287
input                   rd;
288
output                  fifo_empty;
289
// common
290
output [addr_width:0]   fill_level;
291
input rst, clk;
292
 
293
wire [addr_width:1] wadr, radr;
294
 
295 40 unneback
`define MODULE cnt_bin_ce
296
`BASE`MODULE
297 25 unneback
    # ( .length(addr_width))
298
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
299 40 unneback
`BASE`MODULE
300 25 unneback
    # (.length(addr_width))
301
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
302 40 unneback
`undef MODULE
303 25 unneback
 
304 40 unneback
`define MODULE dpram_1r1w
305
`BASE`MODULE
306 25 unneback
    # (.data_width(data_width), .addr_width(addr_width))
307
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
308 40 unneback
`undef MODULE
309 25 unneback
 
310 40 unneback
`define MODULE cnt_bin_ce_rew_q_zq_l1
311
`BASE`MODULE
312 27 unneback
    # (.length(addr_width+1), .level1_value(1<<addr_width))
313 25 unneback
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
314 40 unneback
`undef MODULE
315 25 unneback
endmodule
316 40 unneback
`endif
317 25 unneback
 
318 40 unneback
`ifdef FIFO_2R2W_SYNC_SIMPLEX
319 27 unneback
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
320
// RAM is supposed to be larger than the two FIFOs
321
// LFSR counters used adr pointers
322 40 unneback
`define MODULE fifo_2r2w_sync_simplex
323
module `BASE`MODULE (
324
`undef MODULE
325 27 unneback
    // a side
326
    a_d, a_wr, a_fifo_full,
327
    a_q, a_rd, a_fifo_empty,
328
    a_fill_level,
329
    // b side
330
    b_d, b_wr, b_fifo_full,
331
    b_q, b_rd, b_fifo_empty,
332
    b_fill_level,
333
    // common
334
    clk, rst
335
    );
336
parameter data_width = 8;
337
parameter addr_width = 5;
338
parameter fifo_full_level = (1<<addr_width)-1;
339
 
340
// a side
341
input  [data_width-1:0] a_d;
342
input                   a_wr;
343
output                  a_fifo_full;
344
output [data_width-1:0] a_q;
345
input                   a_rd;
346
output                  a_fifo_empty;
347
output [addr_width-1:0] a_fill_level;
348
 
349
// b side
350
input  [data_width-1:0] b_d;
351
input                   b_wr;
352
output                  b_fifo_full;
353
output [data_width-1:0] b_q;
354
input                   b_rd;
355
output                  b_fifo_empty;
356
output [addr_width-1:0] b_fill_level;
357
 
358
input                   clk;
359
input                   rst;
360
 
361
// adr_gen
362
wire [addr_width:1] a_wadr, a_radr;
363
wire [addr_width:1] b_wadr, b_radr;
364
// dpram
365
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
366
 
367 40 unneback
`define MODULE cnt_lfsr_ce
368
`BASE`MODULE
369 27 unneback
    # ( .length(addr_width))
370
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
371
 
372 40 unneback
`BASE`MODULE
373 27 unneback
    # (.length(addr_width))
374
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
375
 
376 40 unneback
`BASE`MODULE
377 27 unneback
    # ( .length(addr_width))
378
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
379
 
380 40 unneback
`BASE`MODULE
381 27 unneback
    # (.length(addr_width))
382
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
383 40 unneback
`undef MODULE
384 27 unneback
 
385
// mux read or write adr to DPRAM
386
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
387
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
388
 
389 40 unneback
`define MODULE dpram_2r2w
390
`BASE`MODULE
391 27 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
392
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
393
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
394 40 unneback
`undef MODULE
395
 
396
`define MODULE cnt_bin_ce_rew_zq_l1
397
`BASE`MODULE
398 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
399 27 unneback
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
400
 
401 40 unneback
`BASE`MODULE
402 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
403 27 unneback
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
404 40 unneback
`undef MODULE
405 27 unneback
 
406
endmodule
407 40 unneback
`endif
408 27 unneback
 
409 40 unneback
`ifdef FIFO_CMP_ASYNC
410
`define MODULE fifo_cmp_async
411
module `BASE`MODULE ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
412
`undef MODULE
413 5 unneback
 
414 11 unneback
   parameter addr_width = 4;
415
   parameter N = addr_width-1;
416 5 unneback
 
417
   parameter Q1 = 2'b00;
418
   parameter Q2 = 2'b01;
419
   parameter Q3 = 2'b11;
420
   parameter Q4 = 2'b10;
421
 
422
   parameter going_empty = 1'b0;
423
   parameter going_full  = 1'b1;
424
 
425
   input [N:0]  wptr, rptr;
426 14 unneback
   output       fifo_empty;
427 5 unneback
   output       fifo_full;
428
   input        wclk, rclk, rst;
429
 
430
`ifndef GENERATE_DIRECTION_AS_LATCH
431
   wire direction;
432
`endif
433
`ifdef GENERATE_DIRECTION_AS_LATCH
434
   reg direction;
435
`endif
436
   reg  direction_set, direction_clr;
437
 
438
   wire async_empty, async_full;
439
   wire fifo_full2;
440 14 unneback
   wire fifo_empty2;
441 5 unneback
 
442
   // direction_set
443
   always @ (wptr[N:N-1] or rptr[N:N-1])
444
     case ({wptr[N:N-1],rptr[N:N-1]})
445
       {Q1,Q2} : direction_set <= 1'b1;
446
       {Q2,Q3} : direction_set <= 1'b1;
447
       {Q3,Q4} : direction_set <= 1'b1;
448
       {Q4,Q1} : direction_set <= 1'b1;
449
       default : direction_set <= 1'b0;
450
     endcase
451
 
452
   // direction_clear
453
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
454
     if (rst)
455
       direction_clr <= 1'b1;
456
     else
457
       case ({wptr[N:N-1],rptr[N:N-1]})
458
         {Q2,Q1} : direction_clr <= 1'b1;
459
         {Q3,Q2} : direction_clr <= 1'b1;
460
         {Q4,Q3} : direction_clr <= 1'b1;
461
         {Q1,Q4} : direction_clr <= 1'b1;
462
         default : direction_clr <= 1'b0;
463
       endcase
464
 
465 40 unneback
`define MODULE dff_sr
466 5 unneback
`ifndef GENERATE_DIRECTION_AS_LATCH
467 40 unneback
    `BASE`MODULE dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
468 5 unneback
`endif
469
 
470
`ifdef GENERATE_DIRECTION_AS_LATCH
471
   always @ (posedge direction_set or posedge direction_clr)
472
     if (direction_clr)
473
       direction <= going_empty;
474
     else
475
       direction <= going_full;
476
`endif
477
 
478
   assign async_empty = (wptr == rptr) && (direction==going_empty);
479
   assign async_full  = (wptr == rptr) && (direction==going_full);
480
 
481 40 unneback
    `BASE`MODULE dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
482
    `BASE`MODULE dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
483
`undef MODULE
484 5 unneback
 
485
/*
486
   always @ (posedge wclk or posedge rst or posedge async_full)
487
     if (rst)
488
       {fifo_full, fifo_full2} <= 2'b00;
489
     else if (async_full)
490
       {fifo_full, fifo_full2} <= 2'b11;
491
     else
492
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
493
*/
494 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
495 5 unneback
     if (async_empty)
496
       {fifo_empty, fifo_empty2} <= 2'b11;
497
     else
498 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
499 40 unneback
`define MODULE dff
500
    `BASE`MODULE # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
501
    `BASE`MODULE # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
502
`undef MODULE
503 25 unneback
endmodule // async_compb
504 40 unneback
`endif
505 5 unneback
 
506 40 unneback
`ifdef FIFO_1R1W_ASYNC
507
`define MODULE fifo_1r1w_async
508
module `BASE`MODULE (
509
`undef MODULE
510 5 unneback
    d, wr, fifo_full, wr_clk, wr_rst,
511
    q, rd, fifo_empty, rd_clk, rd_rst
512
    );
513
 
514
parameter data_width = 18;
515
parameter addr_width = 4;
516
 
517
// write side
518
input  [data_width-1:0] d;
519
input                   wr;
520
output                  fifo_full;
521
input                   wr_clk;
522
input                   wr_rst;
523
// read side
524
output [data_width-1:0] q;
525
input                   rd;
526
output                  fifo_empty;
527
input                   rd_clk;
528
input                   rd_rst;
529
 
530
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
531 23 unneback
 
532 40 unneback
`define MODULE cnt_gray_ce_bin
533
`BASE`MODULE
534 5 unneback
    # ( .length(addr_width))
535
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
536
 
537 40 unneback
`BASE`MODULE
538 5 unneback
    # (.length(addr_width))
539 23 unneback
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
540 40 unneback
`undef MODULE
541 5 unneback
 
542 40 unneback
`define MODULE dpram_1r1w
543
`BASE`MODULE
544 5 unneback
    # (.data_width(data_width), .addr_width(addr_width))
545
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
546 40 unneback
`undef MODULE
547 5 unneback
 
548 40 unneback
`define MODULE fifo_cmp_async
549
`BASE`MODULE
550 5 unneback
    # (.addr_width(addr_width))
551
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
552 40 unneback
`undef MODULE
553 5 unneback
 
554
endmodule
555 40 unneback
`endif
556 5 unneback
 
557 40 unneback
`ifdef FIFO_2R2W_ASYNC
558
`define MODULE fifo_2r2w_async
559
module `BASE`MODULE (
560
`undef MODULE
561 5 unneback
    // a side
562
    a_d, a_wr, a_fifo_full,
563
    a_q, a_rd, a_fifo_empty,
564
    a_clk, a_rst,
565
    // b side
566
    b_d, b_wr, b_fifo_full,
567
    b_q, b_rd, b_fifo_empty,
568
    b_clk, b_rst
569
    );
570
 
571
parameter data_width = 18;
572
parameter addr_width = 4;
573
 
574
// a side
575
input  [data_width-1:0] a_d;
576
input                   a_wr;
577
output                  a_fifo_full;
578
output [data_width-1:0] a_q;
579
input                   a_rd;
580
output                  a_fifo_empty;
581
input                   a_clk;
582
input                   a_rst;
583
 
584
// b side
585
input  [data_width-1:0] b_d;
586
input                   b_wr;
587
output                  b_fifo_full;
588
output [data_width-1:0] b_q;
589
input                   b_rd;
590
output                  b_fifo_empty;
591
input                   b_clk;
592
input                   b_rst;
593
 
594 40 unneback
`define MODULE fifo_1r1w_async
595
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
596 5 unneback
vl_fifo_1r1w_async_a (
597
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
598
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
599
    );
600
 
601 40 unneback
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
602 5 unneback
vl_fifo_1r1w_async_b (
603
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
604
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
605
    );
606 40 unneback
`undef MODULE
607
 
608 5 unneback
endmodule
609 40 unneback
`endif
610 5 unneback
 
611 40 unneback
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
612
`define MODULE fifo_2r2w_async_simplex
613
module `BASE`MODULE (
614
`undef MODULE
615 5 unneback
    // a side
616
    a_d, a_wr, a_fifo_full,
617
    a_q, a_rd, a_fifo_empty,
618
    a_clk, a_rst,
619
    // b side
620
    b_d, b_wr, b_fifo_full,
621
    b_q, b_rd, b_fifo_empty,
622
    b_clk, b_rst
623
    );
624
 
625
parameter data_width = 18;
626
parameter addr_width = 4;
627
 
628
// a side
629
input  [data_width-1:0] a_d;
630
input                   a_wr;
631
output                  a_fifo_full;
632
output [data_width-1:0] a_q;
633
input                   a_rd;
634
output                  a_fifo_empty;
635
input                   a_clk;
636
input                   a_rst;
637
 
638
// b side
639
input  [data_width-1:0] b_d;
640
input                   b_wr;
641
output                  b_fifo_full;
642
output [data_width-1:0] b_q;
643
input                   b_rd;
644
output                  b_fifo_empty;
645
input                   b_clk;
646
input                   b_rst;
647
 
648
// adr_gen
649
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
650
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
651
// dpram
652
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
653
 
654 40 unneback
`define MODULE cnt_gray_ce_bin
655
`BASE`MODULE
656 5 unneback
    # ( .length(addr_width))
657
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
658
 
659 40 unneback
`BASE`MODULE
660 5 unneback
    # (.length(addr_width))
661
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
662
 
663 40 unneback
`BASE`MODULE
664 5 unneback
    # ( .length(addr_width))
665
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
666
 
667 40 unneback
`BASE`MODULE
668 5 unneback
    # (.length(addr_width))
669
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
670 40 unneback
`undef MODULE
671 5 unneback
 
672
// mux read or write adr to DPRAM
673
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
674
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
675
 
676 40 unneback
`define MODULE dpram_2r2w
677
`BASE`MODULE
678 5 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
679
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
680
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
681 40 unneback
`undef MODULE
682 5 unneback
 
683 40 unneback
`define MODULE fifo_cmp_async
684
`BASE`MODULE
685 5 unneback
    # (.addr_width(addr_width))
686
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
687
 
688 40 unneback
`BASE`MODULE
689 5 unneback
    # (.addr_width(addr_width))
690
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
691 40 unneback
`undef MODULE
692 5 unneback
 
693
endmodule
694 40 unneback
`endif
695 48 unneback
 
696
`ifdef REG_FILE
697
`define MODULE reg_file
698
module `BASE`MODULE (
699
`undef MODULE
700
    a1, a2, a3, wd3, we3, rd1, rd2, clk
701
);
702
parameter data_width = 32;
703
parameter addr_width = 5;
704
input [addr_width-1:0] a1, a2, a3;
705
input [data_width-1:0] wd3;
706
input we3;
707
output [data_width-1:0] rd1, rd2;
708
input clk;
709
 
710
`ifdef ACTEL
711
reg [data_width-1:0] wd3_reg;
712
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
713
reg we3_reg;
714
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] `SYN;
715
reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] `SYN;
716
always @ (posedge clk or posedge rst)
717
if (rst)
718
    {wd3_reg, a3_reg, we3_reg} <= {(data_width+addr_width+1){1'b0}};
719
else
720
    {wd3_reg, a3_reg, we3_reg} <= {wd3,a3,wd3};
721
 
722
    always @ (negedge clk)
723
    if (we3_reg)
724
        ram1[a3_reg] <= wd3;
725
    always @ (posedge clk)
726
        a1_reg <= a1;
727
    assign rd1 = ram1[a1_reg];
728
 
729
    always @ (negedge clk)
730
    if (we3_reg)
731
        ram2[a3_reg] <= wd3;
732
    always @ (posedge clk)
733
        a2_reg <= a2;
734
    assign rd2 = ram2[a2_reg];
735
 
736
`else
737
 
738
`define MODULE dpram_1r1w
739
`BASE`MODULE
740
    # ( .data_width(data_width), .addr_width(addr_width))
741
    ram1 (
742
        .d_a(wd3),
743
        .adr_a(a3),
744
        .we_a(we3),
745
        .clk_a(clk),
746
        .q_b(rd1),
747
        .adr_b(a1),
748
        .clk_b(clk) );
749
 
750
`BASE`MODULE
751
    # ( .data_width(data_width), .addr_width(addr_width))
752
    ram2 (
753
        .d_a(wd3),
754
        .adr_a(a3),
755
        .we_a(we3),
756
        .clk_a(clk),
757
        .q_b(rd2),
758
        .adr_b(a2),
759
        .clk_b(clk) );
760
`undef MODULE
761
 
762
`endif
763
 
764
endmodule
765
`endif

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