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1 5 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
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////  Versatile library, memories                                 ////
4
////                                                              ////
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////  Description                                                 ////
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////  memories                                                    ////
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////                                                              ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - add more memory types                                    ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
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////        ORSoC AB                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
42
 
43 40 unneback
`ifdef ROM_INIT
44 5 unneback
/// ROM
45 40 unneback
`define MODULE rom_init
46
module `BASE`MODULE ( adr, q, clk);
47
`undef MODULE
48 5 unneback
 
49 7 unneback
   parameter data_width = 32;
50
   parameter addr_width = 8;
51
   input [(addr_width-1):0]       adr;
52
   output reg [(data_width-1):0] q;
53
   input                         clk;
54
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
55
   parameter memory_file = "vl_rom.vmem";
56
   initial
57
     begin
58
        $readmemh(memory_file, rom);
59
     end
60
 
61
   always @ (posedge clk)
62
     q <= rom[adr];
63 5 unneback
 
64 7 unneback
endmodule
65 40 unneback
`endif
66 7 unneback
 
67 40 unneback
`ifdef RAM
68
`define MODULE ram
69 5 unneback
// Single port RAM
70 40 unneback
module `BASE`MODULE ( d, adr, we, q, clk);
71
`undef MODULE
72 5 unneback
 
73
   parameter data_width = 32;
74
   parameter addr_width = 8;
75
   input [(data_width-1):0]      d;
76
   input [(addr_width-1):0]       adr;
77
   input                         we;
78 7 unneback
   output reg [(data_width-1):0] q;
79 5 unneback
   input                         clk;
80
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
81 7 unneback
   parameter init = 0;
82
   parameter memory_file = "vl_ram.vmem";
83
   generate if (init) begin : init_mem
84
   initial
85
     begin
86
        $readmemh(memory_file, ram);
87
     end
88
   end
89
   endgenerate
90
 
91 5 unneback
   always @ (posedge clk)
92
   begin
93
   if (we)
94
     ram[adr] <= d;
95
   q <= ram[adr];
96
   end
97
 
98
endmodule
99 40 unneback
`endif
100 5 unneback
 
101 40 unneback
`ifdef RAM_BE
102
`define MODULE ram_be
103
module `BASE`MODULE ( d, adr, be, we, q, clk);
104
`undef MODULE
105
 
106 7 unneback
   parameter data_width = 32;
107
   parameter addr_width = 8;
108
   input [(data_width-1):0]      d;
109
   input [(addr_width-1):0]       adr;
110
   input [(addr_width/4)-1:0]    be;
111
   input                         we;
112
   output reg [(data_width-1):0] q;
113
   input                         clk;
114
 
115
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
116
 
117 60 unneback
   parameter memory_init = 0;
118 7 unneback
   parameter memory_file = "vl_ram.vmem";
119 60 unneback
   generate if (memory_init) begin : init_mem
120 7 unneback
   initial
121
     begin
122
        $readmemh(memory_file, ram);
123
     end
124
   end
125
   endgenerate
126
 
127 60 unneback
//E2_ifdef SYSTEMVERILOG
128
// use a multi-dimensional packed array
129
//to model individual bytes within the word
130
 
131
logic [dat_width/8-1:0][7:0] ram[0:1<<(adr_width-2)-1];// # words = 1 << address width
132
always_ff@(posedge clk)
133
begin
134
    if(we) begin // note: we should have a for statement to support any bus width
135
        if(be[3]) ram[adr[adr_size-2:0]][3] <= d[31:24];
136
        if(be[2]) ram[adr[adr_size-2:0]][2] <= d[23:16];
137
        if(be[1]) ram[adr[adr_size-2:0]][1] <= d[15:8];
138
        if(be[0]) ram[adr[adr_size-2:0]][0] <= d[7:0];
139
    end
140
    q <= ram[raddr];
141
end
142
 
143
//E2_else
144
 
145 7 unneback
   genvar i;
146
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
147
      always @ (posedge clk)
148
      if (we & be[i])
149
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
150
   end
151
   endgenerate
152
 
153
   always @ (posedge clk)
154
      q <= ram[adr];
155
 
156 60 unneback
//E2_endif
157
 
158 7 unneback
endmodule
159 40 unneback
`endif
160 7 unneback
 
161 5 unneback
`ifdef ACTEL
162 48 unneback
        // ACTEL FPGA should not use logic to handle rw collision
163 5 unneback
        `define SYN /*synthesis syn_ramstyle = "no_rw_check"*/
164
`else
165
        `define SYN
166
`endif
167
 
168 40 unneback
`ifdef DPRAM_1R1W
169
`define MODULE dpram_1r1w
170
module `BASE`MODULE ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
171
`undef MODULE
172 5 unneback
   parameter data_width = 32;
173
   parameter addr_width = 8;
174
   input [(data_width-1):0]      d_a;
175
   input [(addr_width-1):0]       adr_a;
176
   input [(addr_width-1):0]       adr_b;
177
   input                         we_a;
178
   output [(data_width-1):0]      q_b;
179
   input                         clk_a, clk_b;
180
   reg [(addr_width-1):0]         adr_b_reg;
181
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
182 7 unneback
 
183
   parameter init = 0;
184
   parameter memory_file = "vl_ram.vmem";
185
   generate if (init) begin : init_mem
186
   initial
187
     begin
188
        $readmemh(memory_file, ram);
189
     end
190
   end
191
   endgenerate
192
 
193 5 unneback
   always @ (posedge clk_a)
194
   if (we_a)
195
     ram[adr_a] <= d_a;
196
   always @ (posedge clk_b)
197
   adr_b_reg <= adr_b;
198
   assign q_b = ram[adr_b_reg];
199 40 unneback
 
200 5 unneback
endmodule
201 40 unneback
`endif
202 5 unneback
 
203 40 unneback
`ifdef DPRAM_2R1W
204
`define MODULE dpram_2r1w
205
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
206
`undef MODULE
207
 
208 5 unneback
   parameter data_width = 32;
209
   parameter addr_width = 8;
210
   input [(data_width-1):0]      d_a;
211
   input [(addr_width-1):0]       adr_a;
212
   input [(addr_width-1):0]       adr_b;
213
   input                         we_a;
214
   output [(data_width-1):0]      q_b;
215
   output reg [(data_width-1):0] q_a;
216
   input                         clk_a, clk_b;
217
   reg [(data_width-1):0]         q_b;
218
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
219 7 unneback
 
220
   parameter init = 0;
221
   parameter memory_file = "vl_ram.vmem";
222
   generate if (init) begin : init_mem
223
   initial
224
     begin
225
        $readmemh(memory_file, ram);
226
     end
227
   end
228
   endgenerate
229
 
230 5 unneback
   always @ (posedge clk_a)
231
     begin
232
        q_a <= ram[adr_a];
233
        if (we_a)
234
             ram[adr_a] <= d_a;
235
     end
236
   always @ (posedge clk_b)
237
          q_b <= ram[adr_b];
238
endmodule
239 40 unneback
`endif
240 5 unneback
 
241 40 unneback
`ifdef DPRAM_2R2W
242
`define MODULE dpram_2r2w
243
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
244
`undef MODULE
245
 
246 5 unneback
   parameter data_width = 32;
247
   parameter addr_width = 8;
248
   input [(data_width-1):0]      d_a;
249
   input [(addr_width-1):0]       adr_a;
250
   input [(addr_width-1):0]       adr_b;
251
   input                         we_a;
252
   output [(data_width-1):0]      q_b;
253
   input [(data_width-1):0]       d_b;
254
   output reg [(data_width-1):0] q_a;
255
   input                         we_b;
256
   input                         clk_a, clk_b;
257
   reg [(data_width-1):0]         q_b;
258
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
259 7 unneback
 
260
   parameter init = 0;
261
   parameter memory_file = "vl_ram.vmem";
262
   generate if (init) begin : init_mem
263
   initial
264
     begin
265
        $readmemh(memory_file, ram);
266
     end
267
   end
268
   endgenerate
269
 
270 5 unneback
   always @ (posedge clk_a)
271
     begin
272
        q_a <= ram[adr_a];
273
        if (we_a)
274
             ram[adr_a] <= d_a;
275
     end
276
   always @ (posedge clk_b)
277
     begin
278
        q_b <= ram[adr_b];
279
        if (we_b)
280
          ram[adr_b] <= d_b;
281
     end
282
endmodule
283 40 unneback
`endif
284 5 unneback
 
285
// Content addresable memory, CAM
286
 
287 40 unneback
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
288 5 unneback
// FIFO
289 40 unneback
`define MODULE fifo_1r1w_fill_level_sync
290
module `BASE`MODULE (
291
`undef MODULE
292 25 unneback
    d, wr, fifo_full,
293
    q, rd, fifo_empty,
294
    fill_level,
295
    clk, rst
296
    );
297
 
298
parameter data_width = 18;
299
parameter addr_width = 4;
300 5 unneback
 
301 25 unneback
// write side
302
input  [data_width-1:0] d;
303
input                   wr;
304
output                  fifo_full;
305
// read side
306
output [data_width-1:0] q;
307
input                   rd;
308
output                  fifo_empty;
309
// common
310
output [addr_width:0]   fill_level;
311
input rst, clk;
312
 
313
wire [addr_width:1] wadr, radr;
314
 
315 40 unneback
`define MODULE cnt_bin_ce
316
`BASE`MODULE
317 25 unneback
    # ( .length(addr_width))
318
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
319 40 unneback
`BASE`MODULE
320 25 unneback
    # (.length(addr_width))
321
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
322 40 unneback
`undef MODULE
323 25 unneback
 
324 40 unneback
`define MODULE dpram_1r1w
325
`BASE`MODULE
326 25 unneback
    # (.data_width(data_width), .addr_width(addr_width))
327
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
328 40 unneback
`undef MODULE
329 25 unneback
 
330 40 unneback
`define MODULE cnt_bin_ce_rew_q_zq_l1
331
`BASE`MODULE
332 27 unneback
    # (.length(addr_width+1), .level1_value(1<<addr_width))
333 25 unneback
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
334 40 unneback
`undef MODULE
335 25 unneback
endmodule
336 40 unneback
`endif
337 25 unneback
 
338 40 unneback
`ifdef FIFO_2R2W_SYNC_SIMPLEX
339 27 unneback
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
340
// RAM is supposed to be larger than the two FIFOs
341
// LFSR counters used adr pointers
342 40 unneback
`define MODULE fifo_2r2w_sync_simplex
343
module `BASE`MODULE (
344
`undef MODULE
345 27 unneback
    // a side
346
    a_d, a_wr, a_fifo_full,
347
    a_q, a_rd, a_fifo_empty,
348
    a_fill_level,
349
    // b side
350
    b_d, b_wr, b_fifo_full,
351
    b_q, b_rd, b_fifo_empty,
352
    b_fill_level,
353
    // common
354
    clk, rst
355
    );
356
parameter data_width = 8;
357
parameter addr_width = 5;
358
parameter fifo_full_level = (1<<addr_width)-1;
359
 
360
// a side
361
input  [data_width-1:0] a_d;
362
input                   a_wr;
363
output                  a_fifo_full;
364
output [data_width-1:0] a_q;
365
input                   a_rd;
366
output                  a_fifo_empty;
367
output [addr_width-1:0] a_fill_level;
368
 
369
// b side
370
input  [data_width-1:0] b_d;
371
input                   b_wr;
372
output                  b_fifo_full;
373
output [data_width-1:0] b_q;
374
input                   b_rd;
375
output                  b_fifo_empty;
376
output [addr_width-1:0] b_fill_level;
377
 
378
input                   clk;
379
input                   rst;
380
 
381
// adr_gen
382
wire [addr_width:1] a_wadr, a_radr;
383
wire [addr_width:1] b_wadr, b_radr;
384
// dpram
385
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
386
 
387 40 unneback
`define MODULE cnt_lfsr_ce
388
`BASE`MODULE
389 27 unneback
    # ( .length(addr_width))
390
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
391
 
392 40 unneback
`BASE`MODULE
393 27 unneback
    # (.length(addr_width))
394
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
395
 
396 40 unneback
`BASE`MODULE
397 27 unneback
    # ( .length(addr_width))
398
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
399
 
400 40 unneback
`BASE`MODULE
401 27 unneback
    # (.length(addr_width))
402
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
403 40 unneback
`undef MODULE
404 27 unneback
 
405
// mux read or write adr to DPRAM
406
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
407
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
408
 
409 40 unneback
`define MODULE dpram_2r2w
410
`BASE`MODULE
411 27 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
412
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
413
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
414 40 unneback
`undef MODULE
415
 
416
`define MODULE cnt_bin_ce_rew_zq_l1
417
`BASE`MODULE
418 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
419 27 unneback
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
420
 
421 40 unneback
`BASE`MODULE
422 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
423 27 unneback
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
424 40 unneback
`undef MODULE
425 27 unneback
 
426
endmodule
427 40 unneback
`endif
428 27 unneback
 
429 40 unneback
`ifdef FIFO_CMP_ASYNC
430
`define MODULE fifo_cmp_async
431
module `BASE`MODULE ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
432
`undef MODULE
433 5 unneback
 
434 11 unneback
   parameter addr_width = 4;
435
   parameter N = addr_width-1;
436 5 unneback
 
437
   parameter Q1 = 2'b00;
438
   parameter Q2 = 2'b01;
439
   parameter Q3 = 2'b11;
440
   parameter Q4 = 2'b10;
441
 
442
   parameter going_empty = 1'b0;
443
   parameter going_full  = 1'b1;
444
 
445
   input [N:0]  wptr, rptr;
446 14 unneback
   output       fifo_empty;
447 5 unneback
   output       fifo_full;
448
   input        wclk, rclk, rst;
449
 
450
`ifndef GENERATE_DIRECTION_AS_LATCH
451
   wire direction;
452
`endif
453
`ifdef GENERATE_DIRECTION_AS_LATCH
454
   reg direction;
455
`endif
456
   reg  direction_set, direction_clr;
457
 
458
   wire async_empty, async_full;
459
   wire fifo_full2;
460 14 unneback
   wire fifo_empty2;
461 5 unneback
 
462
   // direction_set
463
   always @ (wptr[N:N-1] or rptr[N:N-1])
464
     case ({wptr[N:N-1],rptr[N:N-1]})
465
       {Q1,Q2} : direction_set <= 1'b1;
466
       {Q2,Q3} : direction_set <= 1'b1;
467
       {Q3,Q4} : direction_set <= 1'b1;
468
       {Q4,Q1} : direction_set <= 1'b1;
469
       default : direction_set <= 1'b0;
470
     endcase
471
 
472
   // direction_clear
473
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
474
     if (rst)
475
       direction_clr <= 1'b1;
476
     else
477
       case ({wptr[N:N-1],rptr[N:N-1]})
478
         {Q2,Q1} : direction_clr <= 1'b1;
479
         {Q3,Q2} : direction_clr <= 1'b1;
480
         {Q4,Q3} : direction_clr <= 1'b1;
481
         {Q1,Q4} : direction_clr <= 1'b1;
482
         default : direction_clr <= 1'b0;
483
       endcase
484
 
485 40 unneback
`define MODULE dff_sr
486 5 unneback
`ifndef GENERATE_DIRECTION_AS_LATCH
487 40 unneback
    `BASE`MODULE dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
488 5 unneback
`endif
489
 
490
`ifdef GENERATE_DIRECTION_AS_LATCH
491
   always @ (posedge direction_set or posedge direction_clr)
492
     if (direction_clr)
493
       direction <= going_empty;
494
     else
495
       direction <= going_full;
496
`endif
497
 
498
   assign async_empty = (wptr == rptr) && (direction==going_empty);
499
   assign async_full  = (wptr == rptr) && (direction==going_full);
500
 
501 40 unneback
    `BASE`MODULE dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
502
    `BASE`MODULE dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
503
`undef MODULE
504 5 unneback
 
505
/*
506
   always @ (posedge wclk or posedge rst or posedge async_full)
507
     if (rst)
508
       {fifo_full, fifo_full2} <= 2'b00;
509
     else if (async_full)
510
       {fifo_full, fifo_full2} <= 2'b11;
511
     else
512
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
513
*/
514 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
515 5 unneback
     if (async_empty)
516
       {fifo_empty, fifo_empty2} <= 2'b11;
517
     else
518 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
519 40 unneback
`define MODULE dff
520
    `BASE`MODULE # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
521
    `BASE`MODULE # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
522
`undef MODULE
523 25 unneback
endmodule // async_compb
524 40 unneback
`endif
525 5 unneback
 
526 40 unneback
`ifdef FIFO_1R1W_ASYNC
527
`define MODULE fifo_1r1w_async
528
module `BASE`MODULE (
529
`undef MODULE
530 5 unneback
    d, wr, fifo_full, wr_clk, wr_rst,
531
    q, rd, fifo_empty, rd_clk, rd_rst
532
    );
533
 
534
parameter data_width = 18;
535
parameter addr_width = 4;
536
 
537
// write side
538
input  [data_width-1:0] d;
539
input                   wr;
540
output                  fifo_full;
541
input                   wr_clk;
542
input                   wr_rst;
543
// read side
544
output [data_width-1:0] q;
545
input                   rd;
546
output                  fifo_empty;
547
input                   rd_clk;
548
input                   rd_rst;
549
 
550
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
551 23 unneback
 
552 40 unneback
`define MODULE cnt_gray_ce_bin
553
`BASE`MODULE
554 5 unneback
    # ( .length(addr_width))
555
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
556
 
557 40 unneback
`BASE`MODULE
558 5 unneback
    # (.length(addr_width))
559 23 unneback
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
560 40 unneback
`undef MODULE
561 5 unneback
 
562 40 unneback
`define MODULE dpram_1r1w
563
`BASE`MODULE
564 5 unneback
    # (.data_width(data_width), .addr_width(addr_width))
565
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
566 40 unneback
`undef MODULE
567 5 unneback
 
568 40 unneback
`define MODULE fifo_cmp_async
569
`BASE`MODULE
570 5 unneback
    # (.addr_width(addr_width))
571
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
572 40 unneback
`undef MODULE
573 5 unneback
 
574
endmodule
575 40 unneback
`endif
576 5 unneback
 
577 40 unneback
`ifdef FIFO_2R2W_ASYNC
578
`define MODULE fifo_2r2w_async
579
module `BASE`MODULE (
580
`undef MODULE
581 5 unneback
    // a side
582
    a_d, a_wr, a_fifo_full,
583
    a_q, a_rd, a_fifo_empty,
584
    a_clk, a_rst,
585
    // b side
586
    b_d, b_wr, b_fifo_full,
587
    b_q, b_rd, b_fifo_empty,
588
    b_clk, b_rst
589
    );
590
 
591
parameter data_width = 18;
592
parameter addr_width = 4;
593
 
594
// a side
595
input  [data_width-1:0] a_d;
596
input                   a_wr;
597
output                  a_fifo_full;
598
output [data_width-1:0] a_q;
599
input                   a_rd;
600
output                  a_fifo_empty;
601
input                   a_clk;
602
input                   a_rst;
603
 
604
// b side
605
input  [data_width-1:0] b_d;
606
input                   b_wr;
607
output                  b_fifo_full;
608
output [data_width-1:0] b_q;
609
input                   b_rd;
610
output                  b_fifo_empty;
611
input                   b_clk;
612
input                   b_rst;
613
 
614 40 unneback
`define MODULE fifo_1r1w_async
615
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
616 5 unneback
vl_fifo_1r1w_async_a (
617
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
618
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
619
    );
620
 
621 40 unneback
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
622 5 unneback
vl_fifo_1r1w_async_b (
623
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
624
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
625
    );
626 40 unneback
`undef MODULE
627
 
628 5 unneback
endmodule
629 40 unneback
`endif
630 5 unneback
 
631 40 unneback
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
632
`define MODULE fifo_2r2w_async_simplex
633
module `BASE`MODULE (
634
`undef MODULE
635 5 unneback
    // a side
636
    a_d, a_wr, a_fifo_full,
637
    a_q, a_rd, a_fifo_empty,
638
    a_clk, a_rst,
639
    // b side
640
    b_d, b_wr, b_fifo_full,
641
    b_q, b_rd, b_fifo_empty,
642
    b_clk, b_rst
643
    );
644
 
645
parameter data_width = 18;
646
parameter addr_width = 4;
647
 
648
// a side
649
input  [data_width-1:0] a_d;
650
input                   a_wr;
651
output                  a_fifo_full;
652
output [data_width-1:0] a_q;
653
input                   a_rd;
654
output                  a_fifo_empty;
655
input                   a_clk;
656
input                   a_rst;
657
 
658
// b side
659
input  [data_width-1:0] b_d;
660
input                   b_wr;
661
output                  b_fifo_full;
662
output [data_width-1:0] b_q;
663
input                   b_rd;
664
output                  b_fifo_empty;
665
input                   b_clk;
666
input                   b_rst;
667
 
668
// adr_gen
669
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
670
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
671
// dpram
672
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
673
 
674 40 unneback
`define MODULE cnt_gray_ce_bin
675
`BASE`MODULE
676 5 unneback
    # ( .length(addr_width))
677
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
678
 
679 40 unneback
`BASE`MODULE
680 5 unneback
    # (.length(addr_width))
681
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
682
 
683 40 unneback
`BASE`MODULE
684 5 unneback
    # ( .length(addr_width))
685
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
686
 
687 40 unneback
`BASE`MODULE
688 5 unneback
    # (.length(addr_width))
689
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
690 40 unneback
`undef MODULE
691 5 unneback
 
692
// mux read or write adr to DPRAM
693
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
694
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
695
 
696 40 unneback
`define MODULE dpram_2r2w
697
`BASE`MODULE
698 5 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
699
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
700
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
701 40 unneback
`undef MODULE
702 5 unneback
 
703 40 unneback
`define MODULE fifo_cmp_async
704
`BASE`MODULE
705 5 unneback
    # (.addr_width(addr_width))
706
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
707
 
708 40 unneback
`BASE`MODULE
709 5 unneback
    # (.addr_width(addr_width))
710
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
711 40 unneback
`undef MODULE
712 5 unneback
 
713
endmodule
714 40 unneback
`endif
715 48 unneback
 
716
`ifdef REG_FILE
717
`define MODULE reg_file
718
module `BASE`MODULE (
719
`undef MODULE
720
    a1, a2, a3, wd3, we3, rd1, rd2, clk
721
);
722
parameter data_width = 32;
723
parameter addr_width = 5;
724
input [addr_width-1:0] a1, a2, a3;
725
input [data_width-1:0] wd3;
726
input we3;
727
output [data_width-1:0] rd1, rd2;
728
input clk;
729
 
730
`ifdef ACTEL
731
reg [data_width-1:0] wd3_reg;
732
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
733
reg we3_reg;
734
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] `SYN;
735
reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] `SYN;
736
always @ (posedge clk or posedge rst)
737
if (rst)
738
    {wd3_reg, a3_reg, we3_reg} <= {(data_width+addr_width+1){1'b0}};
739
else
740
    {wd3_reg, a3_reg, we3_reg} <= {wd3,a3,wd3};
741
 
742
    always @ (negedge clk)
743
    if (we3_reg)
744
        ram1[a3_reg] <= wd3;
745
    always @ (posedge clk)
746
        a1_reg <= a1;
747
    assign rd1 = ram1[a1_reg];
748
 
749
    always @ (negedge clk)
750
    if (we3_reg)
751
        ram2[a3_reg] <= wd3;
752
    always @ (posedge clk)
753
        a2_reg <= a2;
754
    assign rd2 = ram2[a2_reg];
755
 
756
`else
757
 
758
`define MODULE dpram_1r1w
759
`BASE`MODULE
760
    # ( .data_width(data_width), .addr_width(addr_width))
761
    ram1 (
762
        .d_a(wd3),
763
        .adr_a(a3),
764
        .we_a(we3),
765
        .clk_a(clk),
766
        .q_b(rd1),
767
        .adr_b(a1),
768
        .clk_b(clk) );
769
 
770
`BASE`MODULE
771
    # ( .data_width(data_width), .addr_width(addr_width))
772
    ram2 (
773
        .d_a(wd3),
774
        .adr_a(a3),
775
        .we_a(we3),
776
        .clk_a(clk),
777
        .q_b(rd2),
778
        .adr_b(a2),
779
        .clk_b(clk) );
780
`undef MODULE
781
 
782
`endif
783
 
784
endmodule
785
`endif

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