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1 5 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
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////  Versatile library, memories                                 ////
4
////                                                              ////
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////  Description                                                 ////
6
////  memories                                                    ////
7
////                                                              ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - add more memory types                                    ////
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////                                                              ////
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////  Author(s):                                                  ////
13
////      - Michael Unneback, unneback@opencores.org              ////
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////        ORSoC AB                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
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////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
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////                                                              ////
37
//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
42
 
43 40 unneback
`ifdef ROM_INIT
44 5 unneback
/// ROM
45 40 unneback
`define MODULE rom_init
46
module `BASE`MODULE ( adr, q, clk);
47
`undef MODULE
48 5 unneback
 
49 7 unneback
   parameter data_width = 32;
50
   parameter addr_width = 8;
51 75 unneback
   parameter mem_size = 1<<addr_width;
52 7 unneback
   input [(addr_width-1):0]       adr;
53
   output reg [(data_width-1):0] q;
54
   input                         clk;
55 75 unneback
   reg [data_width-1:0] rom [mem_size-1:0];
56 7 unneback
   parameter memory_file = "vl_rom.vmem";
57
   initial
58
     begin
59
        $readmemh(memory_file, rom);
60
     end
61
 
62
   always @ (posedge clk)
63
     q <= rom[adr];
64 5 unneback
 
65 7 unneback
endmodule
66 40 unneback
`endif
67 7 unneback
 
68 40 unneback
`ifdef RAM
69
`define MODULE ram
70 5 unneback
// Single port RAM
71 40 unneback
module `BASE`MODULE ( d, adr, we, q, clk);
72
`undef MODULE
73 5 unneback
 
74
   parameter data_width = 32;
75
   parameter addr_width = 8;
76 75 unneback
   parameter mem_size = 1<<addr_width;
77 5 unneback
   input [(data_width-1):0]      d;
78
   input [(addr_width-1):0]       adr;
79
   input                         we;
80 7 unneback
   output reg [(data_width-1):0] q;
81 5 unneback
   input                         clk;
82 75 unneback
   reg [data_width-1:0] ram [mem_szie-1:0];
83 7 unneback
   parameter init = 0;
84
   parameter memory_file = "vl_ram.vmem";
85
   generate if (init) begin : init_mem
86
   initial
87
     begin
88
        $readmemh(memory_file, ram);
89
     end
90
   end
91
   endgenerate
92
 
93 5 unneback
   always @ (posedge clk)
94
   begin
95
   if (we)
96
     ram[adr] <= d;
97
   q <= ram[adr];
98
   end
99
 
100
endmodule
101 40 unneback
`endif
102 5 unneback
 
103 40 unneback
`ifdef RAM_BE
104
`define MODULE ram_be
105
module `BASE`MODULE ( d, adr, be, we, q, clk);
106
`undef MODULE
107
 
108 7 unneback
   parameter data_width = 32;
109 72 unneback
   parameter addr_width = 6;
110 75 unneback
   parameter mem_size = 1<<addr_width;
111 7 unneback
   input [(data_width-1):0]      d;
112
   input [(addr_width-1):0]       adr;
113 73 unneback
   input [(data_width/8)-1:0]    be;
114 7 unneback
   input                         we;
115
   output reg [(data_width-1):0] q;
116
   input                         clk;
117
 
118 65 unneback
//E2_ifdef SYSTEMVERILOG
119 68 unneback
   logic [data_width/8-1:0][7:0] ram[0:mem_size-1];// # words = 1 << address width
120 65 unneback
//E2_else
121 68 unneback
   reg [data_width-1:0] ram [mem_size-1:0];
122 65 unneback
//E2_endif
123
 
124 60 unneback
   parameter memory_init = 0;
125 7 unneback
   parameter memory_file = "vl_ram.vmem";
126 60 unneback
   generate if (memory_init) begin : init_mem
127 7 unneback
   initial
128
     begin
129
        $readmemh(memory_file, ram);
130
     end
131
   end
132
   endgenerate
133
 
134 60 unneback
//E2_ifdef SYSTEMVERILOG
135
// use a multi-dimensional packed array
136
//to model individual bytes within the word
137
 
138
always_ff@(posedge clk)
139
begin
140
    if(we) begin // note: we should have a for statement to support any bus width
141 65 unneback
        if(be[3]) ram[adr[addr_width-2:0]][3] <= d[31:24];
142
        if(be[2]) ram[adr[addr_width-2:0]][2] <= d[23:16];
143
        if(be[1]) ram[adr[addr_width-2:0]][1] <= d[15:8];
144
        if(be[0]) ram[adr[addr_width-2:0]][0] <= d[7:0];
145 60 unneback
    end
146 65 unneback
    q <= ram[adr];
147 60 unneback
end
148
 
149
//E2_else
150
 
151 7 unneback
   genvar i;
152
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
153
      always @ (posedge clk)
154
      if (we & be[i])
155
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
156
   end
157
   endgenerate
158
 
159
   always @ (posedge clk)
160
      q <= ram[adr];
161
 
162 60 unneback
//E2_endif
163
 
164 7 unneback
endmodule
165 40 unneback
`endif
166 7 unneback
 
167 5 unneback
`ifdef ACTEL
168 48 unneback
        // ACTEL FPGA should not use logic to handle rw collision
169 5 unneback
        `define SYN /*synthesis syn_ramstyle = "no_rw_check"*/
170
`else
171
        `define SYN
172
`endif
173
 
174 40 unneback
`ifdef DPRAM_1R1W
175
`define MODULE dpram_1r1w
176
module `BASE`MODULE ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
177
`undef MODULE
178 5 unneback
   parameter data_width = 32;
179
   parameter addr_width = 8;
180 75 unneback
   parameter mem_size = 1<<addr_width;
181 5 unneback
   input [(data_width-1):0]      d_a;
182
   input [(addr_width-1):0]       adr_a;
183
   input [(addr_width-1):0]       adr_b;
184
   input                         we_a;
185
   output [(data_width-1):0]      q_b;
186
   input                         clk_a, clk_b;
187
   reg [(addr_width-1):0]         adr_b_reg;
188 75 unneback
   reg [data_width-1:0] ram [mem_szie-1:0] `SYN;
189 7 unneback
 
190
   parameter init = 0;
191
   parameter memory_file = "vl_ram.vmem";
192
   generate if (init) begin : init_mem
193
   initial
194
     begin
195
        $readmemh(memory_file, ram);
196
     end
197
   end
198
   endgenerate
199
 
200 5 unneback
   always @ (posedge clk_a)
201
   if (we_a)
202
     ram[adr_a] <= d_a;
203
   always @ (posedge clk_b)
204
   adr_b_reg <= adr_b;
205
   assign q_b = ram[adr_b_reg];
206 40 unneback
 
207 5 unneback
endmodule
208 40 unneback
`endif
209 5 unneback
 
210 40 unneback
`ifdef DPRAM_2R1W
211
`define MODULE dpram_2r1w
212
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
213
`undef MODULE
214
 
215 5 unneback
   parameter data_width = 32;
216
   parameter addr_width = 8;
217 75 unneback
   parameter mem_size = 1<<addr_width;
218 5 unneback
   input [(data_width-1):0]      d_a;
219
   input [(addr_width-1):0]       adr_a;
220
   input [(addr_width-1):0]       adr_b;
221
   input                         we_a;
222
   output [(data_width-1):0]      q_b;
223
   output reg [(data_width-1):0] q_a;
224
   input                         clk_a, clk_b;
225
   reg [(data_width-1):0]         q_b;
226 75 unneback
   reg [data_width-1:0] ram [mem_szie-1:0] `SYN;
227 7 unneback
 
228
   parameter init = 0;
229
   parameter memory_file = "vl_ram.vmem";
230
   generate if (init) begin : init_mem
231
   initial
232
     begin
233
        $readmemh(memory_file, ram);
234
     end
235
   end
236
   endgenerate
237
 
238 5 unneback
   always @ (posedge clk_a)
239
     begin
240
        q_a <= ram[adr_a];
241
        if (we_a)
242
             ram[adr_a] <= d_a;
243
     end
244
   always @ (posedge clk_b)
245
          q_b <= ram[adr_b];
246
endmodule
247 40 unneback
`endif
248 5 unneback
 
249 40 unneback
`ifdef DPRAM_2R2W
250
`define MODULE dpram_2r2w
251
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
252
`undef MODULE
253
 
254 5 unneback
   parameter data_width = 32;
255
   parameter addr_width = 8;
256 75 unneback
   parameter mem_size = 1<<addr_width;
257 5 unneback
   input [(data_width-1):0]      d_a;
258
   input [(addr_width-1):0]       adr_a;
259
   input [(addr_width-1):0]       adr_b;
260
   input                         we_a;
261
   output [(data_width-1):0]      q_b;
262
   input [(data_width-1):0]       d_b;
263
   output reg [(data_width-1):0] q_a;
264
   input                         we_b;
265
   input                         clk_a, clk_b;
266
   reg [(data_width-1):0]         q_b;
267 75 unneback
   reg [data_width-1:0] ram [mem_size-1:0] `SYN;
268 7 unneback
 
269
   parameter init = 0;
270
   parameter memory_file = "vl_ram.vmem";
271
   generate if (init) begin : init_mem
272
   initial
273
     begin
274
        $readmemh(memory_file, ram);
275
     end
276
   end
277
   endgenerate
278
 
279 5 unneback
   always @ (posedge clk_a)
280
     begin
281
        q_a <= ram[adr_a];
282
        if (we_a)
283
             ram[adr_a] <= d_a;
284
     end
285
   always @ (posedge clk_b)
286
     begin
287
        q_b <= ram[adr_b];
288
        if (we_b)
289
          ram[adr_b] <= d_b;
290
     end
291
endmodule
292 40 unneback
`endif
293 5 unneback
 
294 75 unneback
`ifdef DPRAM_BE_2R2W
295
`define MODULE dpram_be_2r2w
296
module `BASE`MODULE ( d_a, q_a, adr_a, be_a, we_a, clk_a, d_b, q_b, adr_b, be_b, we_b, clk_b );
297
`undef MODULE
298
 
299
   parameter a_data_width = 32;
300
   parameter a_addr_width = 8;
301
   parameter b_data_width = 64;
302
   parameter b_addr_width = 7;
303
   //parameter mem_size = (a_addr_width>b_addr_width) ? (1<<a_addr_width) : (1<<b_addr_width);
304
   parameter mem_size = 1024;
305
   input [(a_data_width-1):0]      d_a;
306
   input [(a_addr_width-1):0]     adr_a;
307
   input [(b_addr_width-1):0]     adr_b;
308
   input [(a_data_width/4-1):0]    be_a;
309
   input                         we_a;
310
   output [(b_data_width-1):0]    q_b;
311
   input [(b_data_width-1):0]     d_b;
312
   output reg [(a_data_width-1):0] q_a;
313
   input [(b_data_width/4-1):0]    be_b;
314
   input                         we_b;
315
   input                         clk_a, clk_b;
316
   reg [(b_data_width-1):0]       q_b;
317
 
318
generate
319
if (a_data_width==32 & b_data_width==64) begin : inst32to64
320
 
321 77 unneback
    wire [63:0] tmp;
322 75 unneback
    `define MODULE dpram_2r2w
323
    `BASE`MODULE
324
    # (.data_width(8), .addr_width(b_addr_width-3))
325
    ram0 (
326
        .d_a(d_a[7:0]),
327
        .q_a(tmp[7:0]),
328
        .adr_a(adr_a[a_addr_width-3-1:0]),
329
        .we_a(we_a & be_a[0] & !adr_a[0]),
330
        .clk_a(clk_a),
331
        .d_b(d_b[7:0]),
332
        .q_b(q_b[7:0]),
333
        .adr_b(adr_b[b_addr_width-3-1:0]),
334
        .we_b(we_b),
335
        .clk_b(clk_b) );
336
    `BASE`MODULE
337
    # (.data_width(8), .addr_width(b_addr_width-3))
338
    ram1 (
339
        .d_a(d_a[7:0]),
340
        .q_a(tmp[7:0]),
341
        .adr_a(adr_a[a_addr_width-3-1:0]),
342
        .we_a(we_a),
343
        .clk_a(clk_a),
344
        .d_b(d_b[7:0]),
345
        .q_b(q_b[7:0]),
346
        .adr_b(adr_b[b_addr_width-3-1:0]),
347
        .we_b(we_b),
348
        .clk_b(clk_b) );
349
    `BASE`MODULE
350
    # (.data_width(8), .addr_width(b_addr_width-3))
351
    ram2 (
352
        .d_a(d_a[15:8]),
353
        .q_a(tmp[7:0]),
354
        .adr_a(adr_a[a_addr_width-3-1:0]),
355
        .we_a(we_a),
356
        .clk_a(clk_a),
357
        .d_b(d_b[7:0]),
358
        .q_b(q_b[7:0]),
359
        .adr_b(adr_b[b_addr_width-3-1:0]),
360
        .we_b(we_b),
361
        .clk_b(clk_b) );
362
    `BASE`MODULE
363
    # (.data_width(8), .addr_width(b_addr_width-3))
364
    ram3 (
365
        .d_a(d_a[15:8]),
366
        .q_a(tmp[7:0]),
367
        .adr_a(adr_a[a_addr_width-3-1:0]),
368
        .we_a(we_a),
369
        .clk_a(clk_a),
370
        .d_b(d_b[7:0]),
371
        .q_b(q_b[7:0]),
372
        .adr_b(adr_b[b_addr_width-3-1:0]),
373
        .we_b(we_b),
374
        .clk_b(clk_b) );
375
    `BASE`MODULE
376
    # (.data_width(8), .addr_width(b_addr_width-3))
377
    ram4 (
378
        .d_a(d_a[23:16]),
379
        .q_a(tmp[7:0]),
380
        .adr_a(adr_a[a_addr_width-3-1:0]),
381
        .we_a(we_a),
382
        .clk_a(clk_a),
383
        .d_b(d_b[7:0]),
384
        .q_b(q_b[7:0]),
385
        .adr_b(adr_b[b_addr_width-3-1:0]),
386
        .we_b(we_b),
387
        .clk_b(clk_b) );
388
    `BASE`MODULE
389
    # (.data_width(8), .addr_width(b_addr_width-3))
390
    ram5 (
391
        .d_a(d_a[23:16]),
392
        .q_a(tmp[7:0]),
393
        .adr_a(adr_a[a_addr_width-3-1:0]),
394
        .we_a(we_a),
395
        .clk_a(clk_a),
396
        .d_b(d_b[7:0]),
397
        .q_b(q_b[7:0]),
398
        .adr_b(adr_b[b_addr_width-3-1:0]),
399
        .we_b(we_b),
400
        .clk_b(clk_b) );
401
    `BASE`MODULE
402
    # (.data_width(8), .addr_width(b_addr_width-3))
403
    ram6 (
404
        .d_a(d_a[31:24]),
405
        .q_a(tmp[7:0]),
406
        .adr_a(adr_a[a_addr_width-3-1:0]),
407
        .we_a(we_a),
408
        .clk_a(clk_a),
409
        .d_b(d_b[7:0]),
410
        .q_b(q_b[7:0]),
411
        .adr_b(adr_b[b_addr_width-3-1:0]),
412
        .we_b(we_b),
413
        .clk_b(clk_b) );
414
    `BASE`MODULE
415
    # (.data_width(8), .addr_width(b_addr_width-3))
416
    ram7 (
417
        .d_a(d_a[31:24]),
418
        .q_a(tmp[7:0]),
419
        .adr_a(adr_a[a_addr_width-3-1:0]),
420
        .we_a(we_a),
421
        .clk_a(clk_a),
422
        .d_b(d_b[7:0]),
423
        .q_b(q_b[7:0]),
424
        .adr_b(adr_b[b_addr_width-3-1:0]),
425
        .we_b(we_b),
426
        .clk_b(clk_b) );
427
`undef MODULE
428
/*
429
   reg [7:0] ram0 [mem_size/8-1:0];
430
   wire [7:0] wea, web;
431
   assign wea = we_a & be_a[0];
432
   assign web = we_b & be_b[0];
433
   always @ (posedge clk_a)
434
    if (wea)
435
        ram0[adr_a] <= d_a[7:0];
436
    always @ (posedge clk_a)
437
        q_a[7:0] <= ram0[adr_a];
438
   always @ (posedge clk_a)
439
    if (web)
440
        ram0[adr_b] <= d_b[7:0];
441
    always @ (posedge clk_b)
442
        q_b[7:0] <= ram0[adr_b];
443
*/
444
end
445
endgenerate
446
/*
447
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_rama
448
      always @ (posedge clk_a)
449
      if (we_a & be_a[i])
450
        ram[adr_a][(i+1)*8-1:i*8] <= d_a[(i+1)*8-1:i*8];
451
   end
452
   endgenerate
453
 
454
   always @ (posedge clk_a)
455
      q_a <= ram[adr_a];
456
 
457
   genvar i;
458
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ramb
459
      always @ (posedge clk_a)
460
      if (we_b & be_b[i])
461
        ram[adr_b][(i+1)*8-1:i*8] <= d_b[(i+1)*8-1:i*8];
462
   end
463
   endgenerate
464
 
465
   always @ (posedge clk_b)
466
      q_b <= ram[adr_b];
467
*/
468
/*
469
   always @ (posedge clk_a)
470
     begin
471
        q_a <= ram[adr_a];
472
        if (we_a)
473
             ram[adr_a] <= d_a;
474
     end
475
   always @ (posedge clk_b)
476
     begin
477
        q_b <= ram[adr_b];
478
        if (we_b)
479
          ram[adr_b] <= d_b;
480
     end
481
*/
482
endmodule
483
`endif
484
 
485 5 unneback
// Content addresable memory, CAM
486
 
487 40 unneback
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
488 5 unneback
// FIFO
489 40 unneback
`define MODULE fifo_1r1w_fill_level_sync
490
module `BASE`MODULE (
491
`undef MODULE
492 25 unneback
    d, wr, fifo_full,
493
    q, rd, fifo_empty,
494
    fill_level,
495
    clk, rst
496
    );
497
 
498
parameter data_width = 18;
499
parameter addr_width = 4;
500 5 unneback
 
501 25 unneback
// write side
502
input  [data_width-1:0] d;
503
input                   wr;
504
output                  fifo_full;
505
// read side
506
output [data_width-1:0] q;
507
input                   rd;
508
output                  fifo_empty;
509
// common
510
output [addr_width:0]   fill_level;
511
input rst, clk;
512
 
513
wire [addr_width:1] wadr, radr;
514
 
515 40 unneback
`define MODULE cnt_bin_ce
516
`BASE`MODULE
517 25 unneback
    # ( .length(addr_width))
518
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
519 40 unneback
`BASE`MODULE
520 25 unneback
    # (.length(addr_width))
521
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
522 40 unneback
`undef MODULE
523 25 unneback
 
524 40 unneback
`define MODULE dpram_1r1w
525
`BASE`MODULE
526 25 unneback
    # (.data_width(data_width), .addr_width(addr_width))
527
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
528 40 unneback
`undef MODULE
529 25 unneback
 
530 40 unneback
`define MODULE cnt_bin_ce_rew_q_zq_l1
531
`BASE`MODULE
532 27 unneback
    # (.length(addr_width+1), .level1_value(1<<addr_width))
533 25 unneback
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
534 40 unneback
`undef MODULE
535 25 unneback
endmodule
536 40 unneback
`endif
537 25 unneback
 
538 40 unneback
`ifdef FIFO_2R2W_SYNC_SIMPLEX
539 27 unneback
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
540
// RAM is supposed to be larger than the two FIFOs
541
// LFSR counters used adr pointers
542 40 unneback
`define MODULE fifo_2r2w_sync_simplex
543
module `BASE`MODULE (
544
`undef MODULE
545 27 unneback
    // a side
546
    a_d, a_wr, a_fifo_full,
547
    a_q, a_rd, a_fifo_empty,
548
    a_fill_level,
549
    // b side
550
    b_d, b_wr, b_fifo_full,
551
    b_q, b_rd, b_fifo_empty,
552
    b_fill_level,
553
    // common
554
    clk, rst
555
    );
556
parameter data_width = 8;
557
parameter addr_width = 5;
558
parameter fifo_full_level = (1<<addr_width)-1;
559
 
560
// a side
561
input  [data_width-1:0] a_d;
562
input                   a_wr;
563
output                  a_fifo_full;
564
output [data_width-1:0] a_q;
565
input                   a_rd;
566
output                  a_fifo_empty;
567
output [addr_width-1:0] a_fill_level;
568
 
569
// b side
570
input  [data_width-1:0] b_d;
571
input                   b_wr;
572
output                  b_fifo_full;
573
output [data_width-1:0] b_q;
574
input                   b_rd;
575
output                  b_fifo_empty;
576
output [addr_width-1:0] b_fill_level;
577
 
578
input                   clk;
579
input                   rst;
580
 
581
// adr_gen
582
wire [addr_width:1] a_wadr, a_radr;
583
wire [addr_width:1] b_wadr, b_radr;
584
// dpram
585
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
586
 
587 40 unneback
`define MODULE cnt_lfsr_ce
588
`BASE`MODULE
589 27 unneback
    # ( .length(addr_width))
590
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
591
 
592 40 unneback
`BASE`MODULE
593 27 unneback
    # (.length(addr_width))
594
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
595
 
596 40 unneback
`BASE`MODULE
597 27 unneback
    # ( .length(addr_width))
598
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
599
 
600 40 unneback
`BASE`MODULE
601 27 unneback
    # (.length(addr_width))
602
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
603 40 unneback
`undef MODULE
604 27 unneback
 
605
// mux read or write adr to DPRAM
606
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
607
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
608
 
609 40 unneback
`define MODULE dpram_2r2w
610
`BASE`MODULE
611 27 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
612
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
613
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
614 40 unneback
`undef MODULE
615
 
616
`define MODULE cnt_bin_ce_rew_zq_l1
617
`BASE`MODULE
618 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
619 27 unneback
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
620
 
621 40 unneback
`BASE`MODULE
622 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
623 27 unneback
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
624 40 unneback
`undef MODULE
625 27 unneback
 
626
endmodule
627 40 unneback
`endif
628 27 unneback
 
629 40 unneback
`ifdef FIFO_CMP_ASYNC
630
`define MODULE fifo_cmp_async
631
module `BASE`MODULE ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
632
`undef MODULE
633 5 unneback
 
634 11 unneback
   parameter addr_width = 4;
635
   parameter N = addr_width-1;
636 5 unneback
 
637
   parameter Q1 = 2'b00;
638
   parameter Q2 = 2'b01;
639
   parameter Q3 = 2'b11;
640
   parameter Q4 = 2'b10;
641
 
642
   parameter going_empty = 1'b0;
643
   parameter going_full  = 1'b1;
644
 
645
   input [N:0]  wptr, rptr;
646 14 unneback
   output       fifo_empty;
647 5 unneback
   output       fifo_full;
648
   input        wclk, rclk, rst;
649
 
650
`ifndef GENERATE_DIRECTION_AS_LATCH
651
   wire direction;
652
`endif
653
`ifdef GENERATE_DIRECTION_AS_LATCH
654
   reg direction;
655
`endif
656
   reg  direction_set, direction_clr;
657
 
658
   wire async_empty, async_full;
659
   wire fifo_full2;
660 14 unneback
   wire fifo_empty2;
661 5 unneback
 
662
   // direction_set
663
   always @ (wptr[N:N-1] or rptr[N:N-1])
664
     case ({wptr[N:N-1],rptr[N:N-1]})
665
       {Q1,Q2} : direction_set <= 1'b1;
666
       {Q2,Q3} : direction_set <= 1'b1;
667
       {Q3,Q4} : direction_set <= 1'b1;
668
       {Q4,Q1} : direction_set <= 1'b1;
669
       default : direction_set <= 1'b0;
670
     endcase
671
 
672
   // direction_clear
673
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
674
     if (rst)
675
       direction_clr <= 1'b1;
676
     else
677
       case ({wptr[N:N-1],rptr[N:N-1]})
678
         {Q2,Q1} : direction_clr <= 1'b1;
679
         {Q3,Q2} : direction_clr <= 1'b1;
680
         {Q4,Q3} : direction_clr <= 1'b1;
681
         {Q1,Q4} : direction_clr <= 1'b1;
682
         default : direction_clr <= 1'b0;
683
       endcase
684
 
685 40 unneback
`define MODULE dff_sr
686 5 unneback
`ifndef GENERATE_DIRECTION_AS_LATCH
687 40 unneback
    `BASE`MODULE dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
688 5 unneback
`endif
689
 
690
`ifdef GENERATE_DIRECTION_AS_LATCH
691
   always @ (posedge direction_set or posedge direction_clr)
692
     if (direction_clr)
693
       direction <= going_empty;
694
     else
695
       direction <= going_full;
696
`endif
697
 
698
   assign async_empty = (wptr == rptr) && (direction==going_empty);
699
   assign async_full  = (wptr == rptr) && (direction==going_full);
700
 
701 40 unneback
    `BASE`MODULE dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
702
    `BASE`MODULE dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
703
`undef MODULE
704 5 unneback
 
705
/*
706
   always @ (posedge wclk or posedge rst or posedge async_full)
707
     if (rst)
708
       {fifo_full, fifo_full2} <= 2'b00;
709
     else if (async_full)
710
       {fifo_full, fifo_full2} <= 2'b11;
711
     else
712
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
713
*/
714 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
715 5 unneback
     if (async_empty)
716
       {fifo_empty, fifo_empty2} <= 2'b11;
717
     else
718 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
719 40 unneback
`define MODULE dff
720
    `BASE`MODULE # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
721
    `BASE`MODULE # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
722
`undef MODULE
723 25 unneback
endmodule // async_compb
724 40 unneback
`endif
725 5 unneback
 
726 40 unneback
`ifdef FIFO_1R1W_ASYNC
727
`define MODULE fifo_1r1w_async
728
module `BASE`MODULE (
729
`undef MODULE
730 5 unneback
    d, wr, fifo_full, wr_clk, wr_rst,
731
    q, rd, fifo_empty, rd_clk, rd_rst
732
    );
733
 
734
parameter data_width = 18;
735
parameter addr_width = 4;
736
 
737
// write side
738
input  [data_width-1:0] d;
739
input                   wr;
740
output                  fifo_full;
741
input                   wr_clk;
742
input                   wr_rst;
743
// read side
744
output [data_width-1:0] q;
745
input                   rd;
746
output                  fifo_empty;
747
input                   rd_clk;
748
input                   rd_rst;
749
 
750
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
751 23 unneback
 
752 40 unneback
`define MODULE cnt_gray_ce_bin
753
`BASE`MODULE
754 5 unneback
    # ( .length(addr_width))
755
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
756
 
757 40 unneback
`BASE`MODULE
758 5 unneback
    # (.length(addr_width))
759 23 unneback
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
760 40 unneback
`undef MODULE
761 5 unneback
 
762 40 unneback
`define MODULE dpram_1r1w
763
`BASE`MODULE
764 5 unneback
    # (.data_width(data_width), .addr_width(addr_width))
765
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
766 40 unneback
`undef MODULE
767 5 unneback
 
768 40 unneback
`define MODULE fifo_cmp_async
769
`BASE`MODULE
770 5 unneback
    # (.addr_width(addr_width))
771
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
772 40 unneback
`undef MODULE
773 5 unneback
 
774
endmodule
775 40 unneback
`endif
776 5 unneback
 
777 40 unneback
`ifdef FIFO_2R2W_ASYNC
778
`define MODULE fifo_2r2w_async
779
module `BASE`MODULE (
780
`undef MODULE
781 5 unneback
    // a side
782
    a_d, a_wr, a_fifo_full,
783
    a_q, a_rd, a_fifo_empty,
784
    a_clk, a_rst,
785
    // b side
786
    b_d, b_wr, b_fifo_full,
787
    b_q, b_rd, b_fifo_empty,
788
    b_clk, b_rst
789
    );
790
 
791
parameter data_width = 18;
792
parameter addr_width = 4;
793
 
794
// a side
795
input  [data_width-1:0] a_d;
796
input                   a_wr;
797
output                  a_fifo_full;
798
output [data_width-1:0] a_q;
799
input                   a_rd;
800
output                  a_fifo_empty;
801
input                   a_clk;
802
input                   a_rst;
803
 
804
// b side
805
input  [data_width-1:0] b_d;
806
input                   b_wr;
807
output                  b_fifo_full;
808
output [data_width-1:0] b_q;
809
input                   b_rd;
810
output                  b_fifo_empty;
811
input                   b_clk;
812
input                   b_rst;
813
 
814 40 unneback
`define MODULE fifo_1r1w_async
815
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
816 5 unneback
vl_fifo_1r1w_async_a (
817
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
818
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
819
    );
820
 
821 40 unneback
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
822 5 unneback
vl_fifo_1r1w_async_b (
823
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
824
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
825
    );
826 40 unneback
`undef MODULE
827
 
828 5 unneback
endmodule
829 40 unneback
`endif
830 5 unneback
 
831 40 unneback
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
832
`define MODULE fifo_2r2w_async_simplex
833
module `BASE`MODULE (
834
`undef MODULE
835 5 unneback
    // a side
836
    a_d, a_wr, a_fifo_full,
837
    a_q, a_rd, a_fifo_empty,
838
    a_clk, a_rst,
839
    // b side
840
    b_d, b_wr, b_fifo_full,
841
    b_q, b_rd, b_fifo_empty,
842
    b_clk, b_rst
843
    );
844
 
845
parameter data_width = 18;
846
parameter addr_width = 4;
847
 
848
// a side
849
input  [data_width-1:0] a_d;
850
input                   a_wr;
851
output                  a_fifo_full;
852
output [data_width-1:0] a_q;
853
input                   a_rd;
854
output                  a_fifo_empty;
855
input                   a_clk;
856
input                   a_rst;
857
 
858
// b side
859
input  [data_width-1:0] b_d;
860
input                   b_wr;
861
output                  b_fifo_full;
862
output [data_width-1:0] b_q;
863
input                   b_rd;
864
output                  b_fifo_empty;
865
input                   b_clk;
866
input                   b_rst;
867
 
868
// adr_gen
869
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
870
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
871
// dpram
872
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
873
 
874 40 unneback
`define MODULE cnt_gray_ce_bin
875
`BASE`MODULE
876 5 unneback
    # ( .length(addr_width))
877
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
878
 
879 40 unneback
`BASE`MODULE
880 5 unneback
    # (.length(addr_width))
881
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
882
 
883 40 unneback
`BASE`MODULE
884 5 unneback
    # ( .length(addr_width))
885
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
886
 
887 40 unneback
`BASE`MODULE
888 5 unneback
    # (.length(addr_width))
889
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
890 40 unneback
`undef MODULE
891 5 unneback
 
892
// mux read or write adr to DPRAM
893
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
894
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
895
 
896 40 unneback
`define MODULE dpram_2r2w
897
`BASE`MODULE
898 5 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
899
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
900
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
901 40 unneback
`undef MODULE
902 5 unneback
 
903 40 unneback
`define MODULE fifo_cmp_async
904
`BASE`MODULE
905 5 unneback
    # (.addr_width(addr_width))
906
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
907
 
908 40 unneback
`BASE`MODULE
909 5 unneback
    # (.addr_width(addr_width))
910
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
911 40 unneback
`undef MODULE
912 5 unneback
 
913
endmodule
914 40 unneback
`endif
915 48 unneback
 
916
`ifdef REG_FILE
917
`define MODULE reg_file
918
module `BASE`MODULE (
919
`undef MODULE
920
    a1, a2, a3, wd3, we3, rd1, rd2, clk
921
);
922
parameter data_width = 32;
923
parameter addr_width = 5;
924
input [addr_width-1:0] a1, a2, a3;
925
input [data_width-1:0] wd3;
926
input we3;
927
output [data_width-1:0] rd1, rd2;
928
input clk;
929
 
930
`ifdef ACTEL
931
reg [data_width-1:0] wd3_reg;
932
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
933
reg we3_reg;
934
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] `SYN;
935
reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] `SYN;
936
always @ (posedge clk or posedge rst)
937
if (rst)
938
    {wd3_reg, a3_reg, we3_reg} <= {(data_width+addr_width+1){1'b0}};
939
else
940
    {wd3_reg, a3_reg, we3_reg} <= {wd3,a3,wd3};
941
 
942
    always @ (negedge clk)
943
    if (we3_reg)
944
        ram1[a3_reg] <= wd3;
945
    always @ (posedge clk)
946
        a1_reg <= a1;
947
    assign rd1 = ram1[a1_reg];
948
 
949
    always @ (negedge clk)
950
    if (we3_reg)
951
        ram2[a3_reg] <= wd3;
952
    always @ (posedge clk)
953
        a2_reg <= a2;
954
    assign rd2 = ram2[a2_reg];
955
 
956
`else
957
 
958
`define MODULE dpram_1r1w
959
`BASE`MODULE
960
    # ( .data_width(data_width), .addr_width(addr_width))
961
    ram1 (
962
        .d_a(wd3),
963
        .adr_a(a3),
964
        .we_a(we3),
965
        .clk_a(clk),
966
        .q_b(rd1),
967
        .adr_b(a1),
968
        .clk_b(clk) );
969
 
970
`BASE`MODULE
971
    # ( .data_width(data_width), .addr_width(addr_width))
972
    ram2 (
973
        .d_a(wd3),
974
        .adr_a(a3),
975
        .we_a(we3),
976
        .clk_a(clk),
977
        .q_b(rd2),
978
        .adr_b(a2),
979
        .clk_b(clk) );
980
`undef MODULE
981
 
982
`endif
983
 
984
endmodule
985
`endif

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