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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Versatile library, memories                                 ////
////                                                              ////
////  Description                                                 ////
////  memories                                                    ////
////                                                              ////
////                                                              ////
////  To Do:                                                      ////
////   - add more memory types                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
`ifdef ROM_INIT
/// ROM
`define MODULE rom_init
module `BASE`MODULE ( adr, q, clk);
`undef MODULE
 
   parameter data_width = 32;
   parameter addr_width = 8;
   parameter mem_size = 1<<addr_width;
   input [(addr_width-1):0]       adr;
   output reg [(data_width-1):0] q;
   input                         clk;
   reg [data_width-1:0] rom [mem_size-1:0];
   parameter memory_file = "vl_rom.vmem";
   initial
     begin
        $readmemh(memory_file, rom);
     end
 
   always @ (posedge clk)
     q <= rom[adr];
 
endmodule
`endif
 
`ifdef RAM
`define MODULE ram
// Single port RAM
module `BASE`MODULE ( d, adr, we, q, clk);
`undef MODULE
 
   parameter data_width = 32;
   parameter addr_width = 8;
   parameter mem_size = 1<<addr_width;
   input [(data_width-1):0]      d;
   input [(addr_width-1):0]       adr;
   input                         we;
   output reg [(data_width-1):0] q;
   input                         clk;
   reg [data_width-1:0] ram [mem_szie-1:0];
   parameter init = 0;
   parameter memory_file = "vl_ram.vmem";
   generate if (init) begin : init_mem
   initial
     begin
        $readmemh(memory_file, ram);
     end
   end
   endgenerate
 
   always @ (posedge clk)
   begin
   if (we)
     ram[adr] <= d;
   q <= ram[adr];
   end
 
endmodule
`endif
 
`ifdef RAM_BE
`define MODULE ram_be
module `BASE`MODULE ( d, adr, be, we, q, clk);
`undef MODULE
 
   parameter data_width = 32;
   parameter addr_width = 6;
   parameter mem_size = 1<<addr_width;
   input [(data_width-1):0]      d;
   input [(addr_width-1):0]       adr;
   input [(data_width/8)-1:0]    be;
   input                         we;
   output reg [(data_width-1):0] q;
   input                         clk;
 
 
//E2_ifdef SYSTEMVERILOG
   logic [data_width/8-1:0][7:0] ram[0:mem_size-1];// # words = 1 << address width
//E2_else
    reg [data_width-1:0] ram [mem_size-1:0];
    wire [data_width/8-1:0] cke;
//E2_endif
 
   parameter memory_init = 0;
   parameter memory_file = "vl_ram.vmem";
   generate if (memory_init) begin : init_mem
   initial
     begin
        $readmemh(memory_file, ram);
     end
   end
   endgenerate
 
//E2_ifdef SYSTEMVERILOG
// use a multi-dimensional packed array
//to model individual bytes within the word
 
always_ff@(posedge clk)
begin
    if(we) begin // note: we should have a for statement to support any bus width
        if(be[3]) ram[adr][3] <= d[31:24];
        if(be[2]) ram[adr][2] <= d[23:16];
        if(be[1]) ram[adr][1] <= d[15:8];
        if(be[0]) ram[adr][0] <= d[7:0];
    end
        q <= ram[adr];
end
 
//E2_else
 
assign cke = {data_width/8{we}} & be;
   genvar i;
   generate for (i=0;i<data_width/8;i=i+1) begin : be_ram
      always @ (posedge clk)
      if (cke[i])
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
   end
   endgenerate
 
   always @ (posedge clk)
      q <= ram[adr];
 
//E2_endif
 
   // Function to access RAM (for use by Verilator).
   function [31:0] get_mem;
      // verilator public
      input [addr_width-1:0]             addr;
      get_mem = ram[addr];
   endfunction // get_mem
 
   // Function to write RAM (for use by Verilator).
   function set_mem;
      // verilator public
      input [addr_width-1:0]             addr;
      input [data_width-1:0]             data;
      ram[addr] = data;
   endfunction // set_mem
 
endmodule
`endif
 
`ifdef ACTEL
        // ACTEL FPGA should not use logic to handle rw collision
        `define SYN /*synthesis syn_ramstyle = "no_rw_check"*/
`else
        `define SYN
`endif
 
`ifdef DPRAM_1R1W
`define MODULE dpram_1r1w
module `BASE`MODULE ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
`undef MODULE
   parameter data_width = 32;
   parameter addr_width = 8;
   parameter mem_size = 1<<addr_width;
   input [(data_width-1):0]      d_a;
   input [(addr_width-1):0]       adr_a;
   input [(addr_width-1):0]       adr_b;
   input                         we_a;
   output [(data_width-1):0]      q_b;
   input                         clk_a, clk_b;
   reg [(addr_width-1):0]         adr_b_reg;
   reg [data_width-1:0] ram [mem_szie-1:0] `SYN;
 
   parameter init = 0;
   parameter memory_file = "vl_ram.vmem";
   generate if (init) begin : init_mem
   initial
     begin
        $readmemh(memory_file, ram);
     end
   end
   endgenerate
 
   always @ (posedge clk_a)
   if (we_a)
     ram[adr_a] <= d_a;
   always @ (posedge clk_b)
   adr_b_reg <= adr_b;
   assign q_b = ram[adr_b_reg];
 
endmodule
`endif
 
`ifdef DPRAM_2R1W
`define MODULE dpram_2r1w
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
`undef MODULE
 
   parameter data_width = 32;
   parameter addr_width = 8;
   parameter mem_size = 1<<addr_width;
   input [(data_width-1):0]      d_a;
   input [(addr_width-1):0]       adr_a;
   input [(addr_width-1):0]       adr_b;
   input                         we_a;
   output [(data_width-1):0]      q_b;
   output reg [(data_width-1):0] q_a;
   input                         clk_a, clk_b;
   reg [(data_width-1):0]         q_b;
   reg [data_width-1:0] ram [mem_szie-1:0] `SYN;
 
   parameter init = 0;
   parameter memory_file = "vl_ram.vmem";
   generate if (init) begin : init_mem
   initial
     begin
        $readmemh(memory_file, ram);
     end
   end
   endgenerate
 
   always @ (posedge clk_a)
     begin
        q_a <= ram[adr_a];
        if (we_a)
             ram[adr_a] <= d_a;
     end
   always @ (posedge clk_b)
          q_b <= ram[adr_b];
endmodule
`endif
 
`ifdef DPRAM_2R2W
`define MODULE dpram_2r2w
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
`undef MODULE
 
   parameter data_width = 32;
   parameter addr_width = 8;
   parameter mem_size = 1<<addr_width;
   input [(data_width-1):0]      d_a;
   input [(addr_width-1):0]       adr_a;
   input [(addr_width-1):0]       adr_b;
   input                         we_a;
   output [(data_width-1):0]      q_b;
   input [(data_width-1):0]       d_b;
   output reg [(data_width-1):0] q_a;
   input                         we_b;
   input                         clk_a, clk_b;
   reg [(data_width-1):0]         q_b;
   reg [data_width-1:0] ram [mem_size-1:0] `SYN;
 
   parameter init = 0;
   parameter memory_file = "vl_ram.vmem";
   generate if (init) begin : init_mem
   initial
     begin
        $readmemh(memory_file, ram);
     end
   end
   endgenerate
 
   always @ (posedge clk_a)
     begin
        q_a <= ram[adr_a];
        if (we_a)
             ram[adr_a] <= d_a;
     end
   always @ (posedge clk_b)
     begin
        q_b <= ram[adr_b];
        if (we_b)
          ram[adr_b] <= d_b;
     end
endmodule
`endif
 
 
`ifdef DPRAM_BE_2R2W
`define MODULE dpram_be_2r2w
module `BASE`MODULE ( d_a, q_a, adr_a, be_a, we_a, clk_a, d_b, q_b, adr_b, be_b, we_b, clk_b );
`undef MODULE
 
   parameter a_data_width = 32;
   parameter a_addr_width = 8;
   parameter b_data_width = a_data_width;
   localparam b_addr_width = a_data_width * a_addr_width / b_data_width;
   parameter mem_size = (a_addr_width>b_addr_width) ? (1<<a_addr_width) : (1<<b_addr_width);
 
   input [(a_data_width-1):0]      d_a;
   input [(a_addr_width-1):0]       adr_a;
   input [(a_data_width/8-1):0]    be_a;
   input                           we_a;
   output reg [(a_data_width-1):0] q_a;
   input [(b_data_width-1):0]       d_b;
   input [(b_addr_width-1):0]       adr_b;
   input [(b_data_width/8-1):0]    be_b;
   input                           we_b;
   output reg [(b_data_width-1):0]          q_b;
   input                           clk_a, clk_b;
 
//E2_ifdef SYSTEMVERILOG
// use a multi-dimensional packed array
//to model individual bytes within the word
 
generate
if (a_data_width==32 & b_data_width==32) begin : dpram_3232
 
   logic [3:0][7:0] ram [0:mem_size-1];
 
    always_ff@(posedge clk_a)
    begin
        if(we_a) begin
            if(be_a[3]) ram[adr_a][3] <= d_a[31:24];
            if(be_a[2]) ram[adr_a][2] <= d_a[23:16];
            if(be_a[1]) ram[adr_a][1] <= d_a[15:8];
            if(be_a[0]) ram[adr_a][0] <= d_a[7:0];
        end
    end
 
    always@(posedge clk_a)
        q_a = ram[adr_a];
 
    always_ff@(posedge clk_b)
    begin
        if(we_b) begin
            if(be_b[3]) ram[adr_b][3] <= d_b[31:24];
            if(be_b[2]) ram[adr_b][2] <= d_b[23:16];
            if(be_b[1]) ram[adr_b][1] <= d_b[15:8];
            if(be_b[0]) ram[adr_b][0] <= d_b[7:0];
        end
    end
 
    always@(posedge clk_b)
        q_b = ram[adr_b];
 
end
endgenerate
 
//E2_else
    // This modules requires SystemVerilog
//E2_endif
endmodule
`endif
 
`ifdef CAM
// Content addresable memory, CAM
`endif
 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
// FIFO
`define MODULE fifo_1r1w_fill_level_sync
module `BASE`MODULE (
`undef MODULE
    d, wr, fifo_full,
    q, rd, fifo_empty,
    fill_level,
    clk, rst
    );
 
parameter data_width = 18;
parameter addr_width = 4;
 
// write side
input  [data_width-1:0] d;
input                   wr;
output                  fifo_full;
// read side
output [data_width-1:0] q;
input                   rd;
output                  fifo_empty;
// common
output [addr_width:0]   fill_level;
input rst, clk;
 
wire [addr_width:1] wadr, radr;
 
`define MODULE cnt_bin_ce
`BASE`MODULE
    # ( .length(addr_width))
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
`BASE`MODULE
    # (.length(addr_width))
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
`undef MODULE
 
`define MODULE dpram_1r1w
`BASE`MODULE
    # (.data_width(data_width), .addr_width(addr_width))
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
`undef MODULE
 
`define MODULE cnt_bin_ce_rew_q_zq_l1
`BASE`MODULE
    # (.length(addr_width+1), .level1_value(1<<addr_width))
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
`undef MODULE
endmodule
`endif
 
`ifdef FIFO_2R2W_SYNC_SIMPLEX
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
// RAM is supposed to be larger than the two FIFOs
// LFSR counters used adr pointers
`define MODULE fifo_2r2w_sync_simplex
module `BASE`MODULE (
`undef MODULE
    // a side
    a_d, a_wr, a_fifo_full,
    a_q, a_rd, a_fifo_empty,
    a_fill_level,
    // b side
    b_d, b_wr, b_fifo_full,
    b_q, b_rd, b_fifo_empty,
    b_fill_level,
    // common
    clk, rst
    );
parameter data_width = 8;
parameter addr_width = 5;
parameter fifo_full_level = (1<<addr_width)-1;
 
// a side
input  [data_width-1:0] a_d;
input                   a_wr;
output                  a_fifo_full;
output [data_width-1:0] a_q;
input                   a_rd;
output                  a_fifo_empty;
output [addr_width-1:0] a_fill_level;
 
// b side
input  [data_width-1:0] b_d;
input                   b_wr;
output                  b_fifo_full;
output [data_width-1:0] b_q;
input                   b_rd;
output                  b_fifo_empty;
output [addr_width-1:0] b_fill_level;
 
input                   clk;
input                   rst;
 
// adr_gen
wire [addr_width:1] a_wadr, a_radr;
wire [addr_width:1] b_wadr, b_radr;
// dpram
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
 
`define MODULE cnt_lfsr_ce
`BASE`MODULE
    # ( .length(addr_width))
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
 
`BASE`MODULE
    # (.length(addr_width))
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
 
`BASE`MODULE
    # ( .length(addr_width))
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
 
`BASE`MODULE
    # (.length(addr_width))
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
`undef MODULE
 
// mux read or write adr to DPRAM
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
 
`define MODULE dpram_2r2w
`BASE`MODULE
    # (.data_width(data_width), .addr_width(addr_width+1))
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
`undef MODULE
 
`define MODULE cnt_bin_ce_rew_zq_l1
`BASE`MODULE
    # (.length(addr_width), .level1_value(fifo_full_level))
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
 
`BASE`MODULE
    # (.length(addr_width), .level1_value(fifo_full_level))
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
`undef MODULE
 
endmodule
`endif
 
`ifdef FIFO_CMP_ASYNC
`define MODULE fifo_cmp_async
module `BASE`MODULE ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
`undef MODULE
 
   parameter addr_width = 4;
   parameter N = addr_width-1;
 
   parameter Q1 = 2'b00;
   parameter Q2 = 2'b01;
   parameter Q3 = 2'b11;
   parameter Q4 = 2'b10;
 
   parameter going_empty = 1'b0;
   parameter going_full  = 1'b1;
 
   input [N:0]  wptr, rptr;
   output       fifo_empty;
   output       fifo_full;
   input        wclk, rclk, rst;
 
`ifndef GENERATE_DIRECTION_AS_LATCH
   wire direction;
`endif
`ifdef GENERATE_DIRECTION_AS_LATCH
   reg direction;
`endif
   reg  direction_set, direction_clr;
 
   wire async_empty, async_full;
   wire fifo_full2;
   wire fifo_empty2;
 
   // direction_set
   always @ (wptr[N:N-1] or rptr[N:N-1])
     case ({wptr[N:N-1],rptr[N:N-1]})
       {Q1,Q2} : direction_set <= 1'b1;
       {Q2,Q3} : direction_set <= 1'b1;
       {Q3,Q4} : direction_set <= 1'b1;
       {Q4,Q1} : direction_set <= 1'b1;
       default : direction_set <= 1'b0;
     endcase
 
   // direction_clear
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
     if (rst)
       direction_clr <= 1'b1;
     else
       case ({wptr[N:N-1],rptr[N:N-1]})
         {Q2,Q1} : direction_clr <= 1'b1;
         {Q3,Q2} : direction_clr <= 1'b1;
         {Q4,Q3} : direction_clr <= 1'b1;
         {Q1,Q4} : direction_clr <= 1'b1;
         default : direction_clr <= 1'b0;
       endcase
 
`define MODULE dff_sr
`ifndef GENERATE_DIRECTION_AS_LATCH
    `BASE`MODULE dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
`endif
 
`ifdef GENERATE_DIRECTION_AS_LATCH
   always @ (posedge direction_set or posedge direction_clr)
     if (direction_clr)
       direction <= going_empty;
     else
       direction <= going_full;
`endif
 
   assign async_empty = (wptr == rptr) && (direction==going_empty);
   assign async_full  = (wptr == rptr) && (direction==going_full);
 
    `BASE`MODULE dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
    `BASE`MODULE dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
`undef MODULE
 
/*
   always @ (posedge wclk or posedge rst or posedge async_full)
     if (rst)
       {fifo_full, fifo_full2} <= 2'b00;
     else if (async_full)
       {fifo_full, fifo_full2} <= 2'b11;
     else
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
*/
/*   always @ (posedge rclk or posedge async_empty)
     if (async_empty)
       {fifo_empty, fifo_empty2} <= 2'b11;
     else
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
`define MODULE dff
    `BASE`MODULE # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
    `BASE`MODULE # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
`undef MODULE
endmodule // async_compb
`endif
 
`ifdef FIFO_1R1W_ASYNC
`define MODULE fifo_1r1w_async
module `BASE`MODULE (
`undef MODULE
    d, wr, fifo_full, wr_clk, wr_rst,
    q, rd, fifo_empty, rd_clk, rd_rst
    );
 
parameter data_width = 18;
parameter addr_width = 4;
 
// write side
input  [data_width-1:0] d;
input                   wr;
output                  fifo_full;
input                   wr_clk;
input                   wr_rst;
// read side
output [data_width-1:0] q;
input                   rd;
output                  fifo_empty;
input                   rd_clk;
input                   rd_rst;
 
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
 
`define MODULE cnt_gray_ce_bin
`BASE`MODULE
    # ( .length(addr_width))
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
 
`BASE`MODULE
    # (.length(addr_width))
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
`undef MODULE
 
`define MODULE dpram_1r1w
`BASE`MODULE
    # (.data_width(data_width), .addr_width(addr_width))
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
`undef MODULE
 
`define MODULE fifo_cmp_async
`BASE`MODULE
    # (.addr_width(addr_width))
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
`undef MODULE
 
endmodule
`endif
 
`ifdef FIFO_2R2W_ASYNC
`define MODULE fifo_2r2w_async
module `BASE`MODULE (
`undef MODULE
    // a side
    a_d, a_wr, a_fifo_full,
    a_q, a_rd, a_fifo_empty,
    a_clk, a_rst,
    // b side
    b_d, b_wr, b_fifo_full,
    b_q, b_rd, b_fifo_empty,
    b_clk, b_rst
    );
 
parameter data_width = 18;
parameter addr_width = 4;
 
// a side
input  [data_width-1:0] a_d;
input                   a_wr;
output                  a_fifo_full;
output [data_width-1:0] a_q;
input                   a_rd;
output                  a_fifo_empty;
input                   a_clk;
input                   a_rst;
 
// b side
input  [data_width-1:0] b_d;
input                   b_wr;
output                  b_fifo_full;
output [data_width-1:0] b_q;
input                   b_rd;
output                  b_fifo_empty;
input                   b_clk;
input                   b_rst;
 
`define MODULE fifo_1r1w_async
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
vl_fifo_1r1w_async_a (
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
    );
 
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
vl_fifo_1r1w_async_b (
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
    );
`undef MODULE
 
endmodule
`endif
 
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
`define MODULE fifo_2r2w_async_simplex
module `BASE`MODULE (
`undef MODULE
    // a side
    a_d, a_wr, a_fifo_full,
    a_q, a_rd, a_fifo_empty,
    a_clk, a_rst,
    // b side
    b_d, b_wr, b_fifo_full,
    b_q, b_rd, b_fifo_empty,
    b_clk, b_rst
    );
 
parameter data_width = 18;
parameter addr_width = 4;
 
// a side
input  [data_width-1:0] a_d;
input                   a_wr;
output                  a_fifo_full;
output [data_width-1:0] a_q;
input                   a_rd;
output                  a_fifo_empty;
input                   a_clk;
input                   a_rst;
 
// b side
input  [data_width-1:0] b_d;
input                   b_wr;
output                  b_fifo_full;
output [data_width-1:0] b_q;
input                   b_rd;
output                  b_fifo_empty;
input                   b_clk;
input                   b_rst;
 
// adr_gen
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
// dpram
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
 
`define MODULE cnt_gray_ce_bin
`BASE`MODULE
    # ( .length(addr_width))
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
 
`BASE`MODULE
    # (.length(addr_width))
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
 
`BASE`MODULE
    # ( .length(addr_width))
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
 
`BASE`MODULE
    # (.length(addr_width))
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
`undef MODULE
 
// mux read or write adr to DPRAM
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
 
`define MODULE dpram_2r2w
`BASE`MODULE
    # (.data_width(data_width), .addr_width(addr_width+1))
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
`undef MODULE
 
`define MODULE fifo_cmp_async
`BASE`MODULE
    # (.addr_width(addr_width))
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
 
`BASE`MODULE
    # (.addr_width(addr_width))
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
`undef MODULE
 
endmodule
`endif
 
`ifdef REG_FILE
`define MODULE reg_file
module `BASE`MODULE (
`undef MODULE
    a1, a2, a3, wd3, we3, rd1, rd2, clk
);
parameter data_width = 32;
parameter addr_width = 5;
input [addr_width-1:0] a1, a2, a3;
input [data_width-1:0] wd3;
input we3;
output [data_width-1:0] rd1, rd2;
input clk;
 
`ifdef ACTEL
reg [data_width-1:0] wd3_reg;
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
reg we3_reg;
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] `SYN;
reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] `SYN;
always @ (posedge clk or posedge rst)
if (rst)
    {wd3_reg, a3_reg, we3_reg} <= {(data_width+addr_width+1){1'b0}};
else
    {wd3_reg, a3_reg, we3_reg} <= {wd3,a3,wd3};
 
    always @ (negedge clk)
    if (we3_reg)
        ram1[a3_reg] <= wd3;
    always @ (posedge clk)
        a1_reg <= a1;
    assign rd1 = ram1[a1_reg];
 
    always @ (negedge clk)
    if (we3_reg)
        ram2[a3_reg] <= wd3;
    always @ (posedge clk)
        a2_reg <= a2;
    assign rd2 = ram2[a2_reg];
 
`else
 
`define MODULE dpram_1r1w
`BASE`MODULE
    # ( .data_width(data_width), .addr_width(addr_width))
    ram1 (
        .d_a(wd3),
        .adr_a(a3),
        .we_a(we3),
        .clk_a(clk),
        .q_b(rd1),
        .adr_b(a1),
        .clk_b(clk) );
 
`BASE`MODULE
    # ( .data_width(data_width), .addr_width(addr_width))
    ram2 (
        .d_a(wd3),
        .adr_a(a3),
        .we_a(we3),
        .clk_a(clk),
        .q_b(rd2),
        .adr_b(a2),
        .clk_b(clk) );
`undef MODULE
 
`endif
 
endmodule
`endif

Line No.	Rev	Author	Line
1	5	unneback	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Versatile library, memories ////`
4			`//// ////`
5			`//// Description ////`
6			`//// memories ////`
7			`//// ////`
8			`//// ////`
9			`//// To Do: ////`
10			`//// - add more memory types ////`
11			`//// ////`
12			`//// Author(s): ////`
13			`//// - Michael Unneback, unneback@opencores.org ////`
14			`//// ORSoC AB ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2010 Authors and OPENCORES.ORG ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42
43	40	unneback	`ifdef ROM_INIT
44	5	unneback	`/// ROM`
45	40	unneback	`define MODULE rom_init
46			module `BASE`MODULE ( adr, q, clk);
47			`undef MODULE
48	5	unneback
49	7	unneback	`parameter data_width = 32;`
50			`parameter addr_width = 8;`
51	75	unneback	`parameter mem_size = 1<<addr_width;`
52	7	unneback	`input [(addr_width-1):0] adr;`
53			`output reg [(data_width-1):0] q;`
54			`input clk;`
55	75	unneback	`reg [data_width-1:0] rom [mem_size-1:0];`
56	7	unneback	`parameter memory_file = "vl_rom.vmem";`
57			`initial`
58			`begin`
59			`$readmemh(memory_file, rom);`
60			`end`
61
62			`always @ (posedge clk)`
63			`q <= rom[adr];`
64	5	unneback
65	7	unneback	`endmodule`
66	40	unneback	`endif
67	7	unneback
68	40	unneback	`ifdef RAM
69			`define MODULE ram
70	5	unneback	`// Single port RAM`
71	40	unneback	module `BASE`MODULE ( d, adr, we, q, clk);
72			`undef MODULE
73	5	unneback
74			`parameter data_width = 32;`
75			`parameter addr_width = 8;`
76	75	unneback	`parameter mem_size = 1<<addr_width;`
77	5	unneback	`input [(data_width-1):0] d;`
78			`input [(addr_width-1):0] adr;`
79			`input we;`
80	7	unneback	`output reg [(data_width-1):0] q;`
81	5	unneback	`input clk;`
82	75	unneback	`reg [data_width-1:0] ram [mem_szie-1:0];`
83	7	unneback	`parameter init = 0;`
84			`parameter memory_file = "vl_ram.vmem";`
85			`generate if (init) begin : init_mem`
86			`initial`
87			`begin`
88			`$readmemh(memory_file, ram);`
89			`end`
90			`end`
91			`endgenerate`
92
93	5	unneback	`always @ (posedge clk)`
94			`begin`
95			`if (we)`
96			`ram[adr] <= d;`
97			`q <= ram[adr];`
98			`end`
99
100			`endmodule`
101	40	unneback	`endif
102	5	unneback
103	40	unneback	`ifdef RAM_BE
104			`define MODULE ram_be
105	91	unneback	module `BASE`MODULE ( d, adr, be, we, q, clk);
106	40	unneback	`undef MODULE
107
108	7	unneback	`parameter data_width = 32;`
109	72	unneback	`parameter addr_width = 6;`
110	75	unneback	`parameter mem_size = 1<<addr_width;`
111	7	unneback	`input [(data_width-1):0] d;`
112			`input [(addr_width-1):0] adr;`
113	73	unneback	`input [(data_width/8)-1:0] be;`
114	7	unneback	`input we;`
115			`output reg [(data_width-1):0] q;`
116			`input clk;`
117
118	84	unneback
119	65	unneback	`//E2_ifdef SYSTEMVERILOG`
120	68	unneback	`logic [data_width/8-1:0][7:0] ram[0:mem_size-1];// # words = 1 << address width`
121	65	unneback	`//E2_else`
122	84	unneback	`reg [data_width-1:0] ram [mem_size-1:0];`
123			`wire [data_width/8-1:0] cke;`
124	65	unneback	`//E2_endif`
125
126	60	unneback	`parameter memory_init = 0;`
127	7	unneback	`parameter memory_file = "vl_ram.vmem";`
128	60	unneback	`generate if (memory_init) begin : init_mem`
129	7	unneback	`initial`
130			`begin`
131			`$readmemh(memory_file, ram);`
132			`end`
133			`end`
134			`endgenerate`
135
136	60	unneback	`//E2_ifdef SYSTEMVERILOG`
137			`// use a multi-dimensional packed array`
138			`//to model individual bytes within the word`
139
140			`always_ff@(posedge clk)`
141			`begin`
142			`if(we) begin // note: we should have a for statement to support any bus width`
143	86	unneback	`if(be[3]) ram[adr][3] <= d[31:24];`
144			`if(be[2]) ram[adr][2] <= d[23:16];`
145			`if(be[1]) ram[adr][1] <= d[15:8];`
146			`if(be[0]) ram[adr][0] <= d[7:0];`
147	60	unneback	`end`
148	90	unneback	`q <= ram[adr];`
149	60	unneback	`end`
150
151			`//E2_else`
152
153	84	unneback	`assign cke = {data_width/8{we}} & be;`
154	7	unneback	`genvar i;`
155	84	unneback	`generate for (i=0;i<data_width/8;i=i+1) begin : be_ram`
156	7	unneback	`always @ (posedge clk)`
157	84	unneback	`if (cke[i])`
158	7	unneback	`ram[adr][(i+1)8-1:i8] <= d[(i+1)8-1:i8];`
159			`end`
160			`endgenerate`
161
162			`always @ (posedge clk)`
163			`q <= ram[adr];`
164
165	60	unneback	`//E2_endif`
166
167	84	unneback	`// Function to access RAM (for use by Verilator).`
168			`function [31:0] get_mem;`
169			`// verilator public`
170	90	unneback	`input [addr_width-1:0] addr;`
171	84	unneback	`get_mem = ram[addr];`
172			`endfunction // get_mem`
173
174			`// Function to write RAM (for use by Verilator).`
175			`function set_mem;`
176			`// verilator public`
177	90	unneback	`input [addr_width-1:0] addr;`
178			`input [data_width-1:0] data;`
179	84	unneback	`ram[addr] = data;`
180			`endfunction // set_mem`
181
182	7	unneback	`endmodule`
183	40	unneback	`endif
184	7	unneback
185	5	unneback	`ifdef ACTEL
186	48	unneback	`// ACTEL FPGA should not use logic to handle rw collision`
187	5	unneback	`define SYN /synthesis syn_ramstyle = "no_rw_check"/
188			`else
189			`define SYN
190			`endif
191
192	40	unneback	`ifdef DPRAM_1R1W
193			`define MODULE dpram_1r1w
194			module `BASE`MODULE ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
195			`undef MODULE
196	5	unneback	`parameter data_width = 32;`
197			`parameter addr_width = 8;`
198	75	unneback	`parameter mem_size = 1<<addr_width;`
199	5	unneback	`input [(data_width-1):0] d_a;`
200			`input [(addr_width-1):0] adr_a;`
201			`input [(addr_width-1):0] adr_b;`
202			`input we_a;`
203			`output [(data_width-1):0] q_b;`
204			`input clk_a, clk_b;`
205			`reg [(addr_width-1):0] adr_b_reg;`
206	75	unneback	reg [data_width-1:0] ram [mem_szie-1:0] `SYN;
207	7	unneback
208			`parameter init = 0;`
209			`parameter memory_file = "vl_ram.vmem";`
210			`generate if (init) begin : init_mem`
211			`initial`
212			`begin`
213			`$readmemh(memory_file, ram);`
214			`end`
215			`end`
216			`endgenerate`
217
218	5	unneback	`always @ (posedge clk_a)`
219			`if (we_a)`
220			`ram[adr_a] <= d_a;`
221			`always @ (posedge clk_b)`
222			`adr_b_reg <= adr_b;`
223			`assign q_b = ram[adr_b_reg];`
224	40	unneback
225	5	unneback	`endmodule`
226	40	unneback	`endif
227	5	unneback
228	40	unneback	`ifdef DPRAM_2R1W
229			`define MODULE dpram_2r1w
230			module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
231			`undef MODULE
232
233	5	unneback	`parameter data_width = 32;`
234			`parameter addr_width = 8;`
235	75	unneback	`parameter mem_size = 1<<addr_width;`
236	5	unneback	`input [(data_width-1):0] d_a;`
237			`input [(addr_width-1):0] adr_a;`
238			`input [(addr_width-1):0] adr_b;`
239			`input we_a;`
240			`output [(data_width-1):0] q_b;`
241			`output reg [(data_width-1):0] q_a;`
242			`input clk_a, clk_b;`
243			`reg [(data_width-1):0] q_b;`
244	75	unneback	reg [data_width-1:0] ram [mem_szie-1:0] `SYN;
245	7	unneback
246			`parameter init = 0;`
247			`parameter memory_file = "vl_ram.vmem";`
248			`generate if (init) begin : init_mem`
249			`initial`
250			`begin`
251			`$readmemh(memory_file, ram);`
252			`end`
253			`end`
254			`endgenerate`
255
256	5	unneback	`always @ (posedge clk_a)`
257			`begin`
258			`q_a <= ram[adr_a];`
259			`if (we_a)`
260			`ram[adr_a] <= d_a;`
261			`end`
262			`always @ (posedge clk_b)`
263			`q_b <= ram[adr_b];`
264			`endmodule`
265	40	unneback	`endif
266	5	unneback
267	40	unneback	`ifdef DPRAM_2R2W
268			`define MODULE dpram_2r2w
269			module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
270			`undef MODULE
271
272	5	unneback	`parameter data_width = 32;`
273			`parameter addr_width = 8;`
274	75	unneback	`parameter mem_size = 1<<addr_width;`
275	5	unneback	`input [(data_width-1):0] d_a;`
276			`input [(addr_width-1):0] adr_a;`
277			`input [(addr_width-1):0] adr_b;`
278			`input we_a;`
279			`output [(data_width-1):0] q_b;`
280			`input [(data_width-1):0] d_b;`
281			`output reg [(data_width-1):0] q_a;`
282			`input we_b;`
283			`input clk_a, clk_b;`
284			`reg [(data_width-1):0] q_b;`
285	75	unneback	reg [data_width-1:0] ram [mem_size-1:0] `SYN;
286	7	unneback
287			`parameter init = 0;`
288			`parameter memory_file = "vl_ram.vmem";`
289			`generate if (init) begin : init_mem`
290			`initial`
291			`begin`
292			`$readmemh(memory_file, ram);`
293			`end`
294			`end`
295			`endgenerate`
296
297	5	unneback	`always @ (posedge clk_a)`
298			`begin`
299			`q_a <= ram[adr_a];`
300			`if (we_a)`
301			`ram[adr_a] <= d_a;`
302			`end`
303			`always @ (posedge clk_b)`
304			`begin`
305			`q_b <= ram[adr_b];`
306			`if (we_b)`
307			`ram[adr_b] <= d_b;`
308			`end`
309			`endmodule`
310	40	unneback	`endif
311	5	unneback
312	83	unneback
313	75	unneback	`ifdef DPRAM_BE_2R2W
314			`define MODULE dpram_be_2r2w
315	92	unneback	module `BASE`MODULE ( d_a, q_a, adr_a, be_a, we_a, clk_a, d_b, q_b, adr_b, be_b, we_b, clk_b );
316	75	unneback	`undef MODULE
317
318			`parameter a_data_width = 32;`
319			`parameter a_addr_width = 8;`
320	92	unneback	`parameter b_data_width = a_data_width;`
321	91	unneback	`localparam b_addr_width = a_data_width * a_addr_width / b_data_width;`
322			`parameter mem_size = (a_addr_width>b_addr_width) ? (1<<a_addr_width) : (1<<b_addr_width);`
323
324	75	unneback	`input [(a_data_width-1):0] d_a;`
325	91	unneback	`input [(a_addr_width-1):0] adr_a;`
326			`input [(a_data_width/8-1):0] be_a;`
327			`input we_a;`
328	75	unneback	`output reg [(a_data_width-1):0] q_a;`
329	91	unneback	`input [(b_data_width-1):0] d_b;`
330			`input [(b_addr_width-1):0] adr_b;`
331	92	unneback	`input [(b_data_width/8-1):0] be_b;`
332			`input we_b;`
333			`output reg [(b_data_width-1):0] q_b;`
334	91	unneback	`input clk_a, clk_b;`
335	75	unneback
336	91	unneback	`//E2_ifdef SYSTEMVERILOG`
337			`// use a multi-dimensional packed array`
338			`//to model individual bytes within the word`
339
340	75	unneback	`generate`
341	91	unneback	`if (a_data_width==32 & b_data_width==32) begin : dpram_3232`
342	75	unneback
343	91	unneback	`logic [3:0][7:0] ram [0:mem_size-1];`
344
345			`always_ff@(posedge clk_a)`
346			`begin`
347			`if(we_a) begin`
348			`if(be_a[3]) ram[adr_a][3] <= d_a[31:24];`
349			`if(be_a[2]) ram[adr_a][2] <= d_a[23:16];`
350			`if(be_a[1]) ram[adr_a][1] <= d_a[15:8];`
351			`if(be_a[0]) ram[adr_a][0] <= d_a[7:0];`
352			`end`
353			`end`
354
355	92	unneback	`always@(posedge clk_a)`
356			`q_a = ram[adr_a];`
357	91	unneback
358			`always_ff@(posedge clk_b)`
359	92	unneback	`begin`
360			`if(we_b) begin`
361			`if(be_b[3]) ram[adr_b][3] <= d_b[31:24];`
362			`if(be_b[2]) ram[adr_b][2] <= d_b[23:16];`
363			`if(be_b[1]) ram[adr_b][1] <= d_b[15:8];`
364			`if(be_b[0]) ram[adr_b][0] <= d_b[7:0];`
365			`end`
366			`end`
367	91	unneback
368	92	unneback	`always@(posedge clk_b)`
369			`q_b = ram[adr_b];`
370	91	unneback
371	75	unneback	`end`
372			`endgenerate`
373
374	91	unneback	`//E2_else`
375	92	unneback	`// This modules requires SystemVerilog`
376	91	unneback	`//E2_endif`
377	75	unneback	`endmodule`
378			`endif
379
380	91	unneback	`ifdef CAM
381	5	unneback	`// Content addresable memory, CAM`
382	91	unneback	`endif
383	5	unneback
384	40	unneback	`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
385	5	unneback	`// FIFO`
386	40	unneback	`define MODULE fifo_1r1w_fill_level_sync
387			module `BASE`MODULE (
388			`undef MODULE
389	25	unneback	`d, wr, fifo_full,`
390			`q, rd, fifo_empty,`
391			`fill_level,`
392			`clk, rst`
393			`);`
394
395			`parameter data_width = 18;`
396			`parameter addr_width = 4;`
397	5	unneback
398	25	unneback	`// write side`
399			`input [data_width-1:0] d;`
400			`input wr;`
401			`output fifo_full;`
402			`// read side`
403			`output [data_width-1:0] q;`
404			`input rd;`
405			`output fifo_empty;`
406			`// common`
407			`output [addr_width:0] fill_level;`
408			`input rst, clk;`
409
410			`wire [addr_width:1] wadr, radr;`
411
412	40	unneback	`define MODULE cnt_bin_ce
413			`BASE`MODULE
414	25	unneback	`# ( .length(addr_width))`
415			`fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));`
416	40	unneback	`BASE`MODULE
417	25	unneback	`# (.length(addr_width))`
418			`fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));`
419	40	unneback	`undef MODULE
420	25	unneback
421	40	unneback	`define MODULE dpram_1r1w
422			`BASE`MODULE
423	25	unneback	`# (.data_width(data_width), .addr_width(addr_width))`
424			`dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));`
425	40	unneback	`undef MODULE
426	25	unneback
427	40	unneback	`define MODULE cnt_bin_ce_rew_q_zq_l1
428			`BASE`MODULE
429	27	unneback	`# (.length(addr_width+1), .level1_value(1<<addr_width))`
430	25	unneback	`fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));`
431	40	unneback	`undef MODULE
432	25	unneback	`endmodule`
433	40	unneback	`endif
434	25	unneback
435	40	unneback	`ifdef FIFO_2R2W_SYNC_SIMPLEX
436	27	unneback	`// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource`
437			`// RAM is supposed to be larger than the two FIFOs`
438			`// LFSR counters used adr pointers`
439	40	unneback	`define MODULE fifo_2r2w_sync_simplex
440			module `BASE`MODULE (
441			`undef MODULE
442	27	unneback	`// a side`
443			`a_d, a_wr, a_fifo_full,`
444			`a_q, a_rd, a_fifo_empty,`
445			`a_fill_level,`
446			`// b side`
447			`b_d, b_wr, b_fifo_full,`
448			`b_q, b_rd, b_fifo_empty,`
449			`b_fill_level,`
450			`// common`
451			`clk, rst`
452			`);`
453			`parameter data_width = 8;`
454			`parameter addr_width = 5;`
455			`parameter fifo_full_level = (1<<addr_width)-1;`
456
457			`// a side`
458			`input [data_width-1:0] a_d;`
459			`input a_wr;`
460			`output a_fifo_full;`
461			`output [data_width-1:0] a_q;`
462			`input a_rd;`
463			`output a_fifo_empty;`
464			`output [addr_width-1:0] a_fill_level;`
465
466			`// b side`
467			`input [data_width-1:0] b_d;`
468			`input b_wr;`
469			`output b_fifo_full;`
470			`output [data_width-1:0] b_q;`
471			`input b_rd;`
472			`output b_fifo_empty;`
473			`output [addr_width-1:0] b_fill_level;`
474
475			`input clk;`
476			`input rst;`
477
478			`// adr_gen`
479			`wire [addr_width:1] a_wadr, a_radr;`
480			`wire [addr_width:1] b_wadr, b_radr;`
481			`// dpram`
482			`wire [addr_width:0] a_dpram_adr, b_dpram_adr;`
483
484	40	unneback	`define MODULE cnt_lfsr_ce
485			`BASE`MODULE
486	27	unneback	`# ( .length(addr_width))`
487			`fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));`
488
489	40	unneback	`BASE`MODULE
490	27	unneback	`# (.length(addr_width))`
491			`fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));`
492
493	40	unneback	`BASE`MODULE
494	27	unneback	`# ( .length(addr_width))`
495			`fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));`
496
497	40	unneback	`BASE`MODULE
498	27	unneback	`# (.length(addr_width))`
499			`fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));`
500	40	unneback	`undef MODULE

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