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1 5 unneback
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  Versatile library, memories                                 ////
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////                                                              ////
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////  Description                                                 ////
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////  memories                                                    ////
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////                                                              ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - add more memory types                                    ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
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////        ORSoC AB                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
42
 
43 40 unneback
`ifdef ROM_INIT
44 5 unneback
/// ROM
45 40 unneback
`define MODULE rom_init
46
module `BASE`MODULE ( adr, q, clk);
47
`undef MODULE
48 5 unneback
 
49 7 unneback
   parameter data_width = 32;
50
   parameter addr_width = 8;
51 75 unneback
   parameter mem_size = 1<<addr_width;
52 7 unneback
   input [(addr_width-1):0]       adr;
53
   output reg [(data_width-1):0] q;
54
   input                         clk;
55 75 unneback
   reg [data_width-1:0] rom [mem_size-1:0];
56 7 unneback
   parameter memory_file = "vl_rom.vmem";
57
   initial
58
     begin
59
        $readmemh(memory_file, rom);
60
     end
61
 
62
   always @ (posedge clk)
63
     q <= rom[adr];
64 5 unneback
 
65 7 unneback
endmodule
66 40 unneback
`endif
67 7 unneback
 
68 40 unneback
`ifdef RAM
69
`define MODULE ram
70 5 unneback
// Single port RAM
71 40 unneback
module `BASE`MODULE ( d, adr, we, q, clk);
72
`undef MODULE
73 5 unneback
 
74
   parameter data_width = 32;
75
   parameter addr_width = 8;
76 75 unneback
   parameter mem_size = 1<<addr_width;
77 5 unneback
   input [(data_width-1):0]      d;
78
   input [(addr_width-1):0]       adr;
79
   input                         we;
80 7 unneback
   output reg [(data_width-1):0] q;
81 5 unneback
   input                         clk;
82 75 unneback
   reg [data_width-1:0] ram [mem_szie-1:0];
83 7 unneback
   parameter init = 0;
84
   parameter memory_file = "vl_ram.vmem";
85
   generate if (init) begin : init_mem
86
   initial
87
     begin
88
        $readmemh(memory_file, ram);
89
     end
90
   end
91
   endgenerate
92
 
93 5 unneback
   always @ (posedge clk)
94
   begin
95
   if (we)
96
     ram[adr] <= d;
97
   q <= ram[adr];
98
   end
99
 
100
endmodule
101 40 unneback
`endif
102 5 unneback
 
103 40 unneback
`ifdef RAM_BE
104
`define MODULE ram_be
105 91 unneback
module `BASE`MODULE ( d, adr, be, we, q, clk);
106 40 unneback
`undef MODULE
107
 
108 7 unneback
   parameter data_width = 32;
109 72 unneback
   parameter addr_width = 6;
110 75 unneback
   parameter mem_size = 1<<addr_width;
111 7 unneback
   input [(data_width-1):0]      d;
112
   input [(addr_width-1):0]       adr;
113 73 unneback
   input [(data_width/8)-1:0]    be;
114 7 unneback
   input                         we;
115
   output reg [(data_width-1):0] q;
116
   input                         clk;
117
 
118 84 unneback
 
119 65 unneback
//E2_ifdef SYSTEMVERILOG
120 68 unneback
   logic [data_width/8-1:0][7:0] ram[0:mem_size-1];// # words = 1 << address width
121 65 unneback
//E2_else
122 84 unneback
    reg [data_width-1:0] ram [mem_size-1:0];
123
    wire [data_width/8-1:0] cke;
124 65 unneback
//E2_endif
125
 
126 60 unneback
   parameter memory_init = 0;
127 7 unneback
   parameter memory_file = "vl_ram.vmem";
128 60 unneback
   generate if (memory_init) begin : init_mem
129 7 unneback
   initial
130
     begin
131
        $readmemh(memory_file, ram);
132
     end
133
   end
134
   endgenerate
135
 
136 60 unneback
//E2_ifdef SYSTEMVERILOG
137
// use a multi-dimensional packed array
138
//to model individual bytes within the word
139
 
140
always_ff@(posedge clk)
141
begin
142
    if(we) begin // note: we should have a for statement to support any bus width
143 86 unneback
        if(be[3]) ram[adr][3] <= d[31:24];
144
        if(be[2]) ram[adr][2] <= d[23:16];
145
        if(be[1]) ram[adr][1] <= d[15:8];
146
        if(be[0]) ram[adr][0] <= d[7:0];
147 60 unneback
    end
148 90 unneback
        q <= ram[adr];
149 60 unneback
end
150
 
151
//E2_else
152
 
153 84 unneback
assign cke = {data_width/8{we}} & be;
154 7 unneback
   genvar i;
155 84 unneback
   generate for (i=0;i<data_width/8;i=i+1) begin : be_ram
156 7 unneback
      always @ (posedge clk)
157 84 unneback
      if (cke[i])
158 7 unneback
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
159
   end
160
   endgenerate
161
 
162
   always @ (posedge clk)
163
      q <= ram[adr];
164
 
165 60 unneback
//E2_endif
166
 
167 84 unneback
   // Function to access RAM (for use by Verilator).
168
   function [31:0] get_mem;
169
      // verilator public
170 90 unneback
      input [addr_width-1:0]             addr;
171 84 unneback
      get_mem = ram[addr];
172
   endfunction // get_mem
173
 
174
   // Function to write RAM (for use by Verilator).
175
   function set_mem;
176
      // verilator public
177 90 unneback
      input [addr_width-1:0]             addr;
178
      input [data_width-1:0]             data;
179 84 unneback
      ram[addr] = data;
180
   endfunction // set_mem
181
 
182 7 unneback
endmodule
183 40 unneback
`endif
184 7 unneback
 
185 5 unneback
`ifdef ACTEL
186 48 unneback
        // ACTEL FPGA should not use logic to handle rw collision
187 5 unneback
        `define SYN /*synthesis syn_ramstyle = "no_rw_check"*/
188
`else
189
        `define SYN
190
`endif
191
 
192 40 unneback
`ifdef DPRAM_1R1W
193
`define MODULE dpram_1r1w
194
module `BASE`MODULE ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
195
`undef MODULE
196 5 unneback
   parameter data_width = 32;
197
   parameter addr_width = 8;
198 75 unneback
   parameter mem_size = 1<<addr_width;
199 5 unneback
   input [(data_width-1):0]      d_a;
200
   input [(addr_width-1):0]       adr_a;
201
   input [(addr_width-1):0]       adr_b;
202
   input                         we_a;
203
   output [(data_width-1):0]      q_b;
204
   input                         clk_a, clk_b;
205
   reg [(addr_width-1):0]         adr_b_reg;
206 75 unneback
   reg [data_width-1:0] ram [mem_szie-1:0] `SYN;
207 7 unneback
 
208
   parameter init = 0;
209
   parameter memory_file = "vl_ram.vmem";
210
   generate if (init) begin : init_mem
211
   initial
212
     begin
213
        $readmemh(memory_file, ram);
214
     end
215
   end
216
   endgenerate
217
 
218 5 unneback
   always @ (posedge clk_a)
219
   if (we_a)
220
     ram[adr_a] <= d_a;
221
   always @ (posedge clk_b)
222
   adr_b_reg <= adr_b;
223
   assign q_b = ram[adr_b_reg];
224 40 unneback
 
225 5 unneback
endmodule
226 40 unneback
`endif
227 5 unneback
 
228 40 unneback
`ifdef DPRAM_2R1W
229
`define MODULE dpram_2r1w
230
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
231
`undef MODULE
232
 
233 5 unneback
   parameter data_width = 32;
234
   parameter addr_width = 8;
235 75 unneback
   parameter mem_size = 1<<addr_width;
236 5 unneback
   input [(data_width-1):0]      d_a;
237
   input [(addr_width-1):0]       adr_a;
238
   input [(addr_width-1):0]       adr_b;
239
   input                         we_a;
240
   output [(data_width-1):0]      q_b;
241
   output reg [(data_width-1):0] q_a;
242
   input                         clk_a, clk_b;
243
   reg [(data_width-1):0]         q_b;
244 75 unneback
   reg [data_width-1:0] ram [mem_szie-1:0] `SYN;
245 7 unneback
 
246
   parameter init = 0;
247
   parameter memory_file = "vl_ram.vmem";
248
   generate if (init) begin : init_mem
249
   initial
250
     begin
251
        $readmemh(memory_file, ram);
252
     end
253
   end
254
   endgenerate
255
 
256 5 unneback
   always @ (posedge clk_a)
257
     begin
258
        q_a <= ram[adr_a];
259
        if (we_a)
260
             ram[adr_a] <= d_a;
261
     end
262
   always @ (posedge clk_b)
263
          q_b <= ram[adr_b];
264
endmodule
265 40 unneback
`endif
266 5 unneback
 
267 40 unneback
`ifdef DPRAM_2R2W
268
`define MODULE dpram_2r2w
269
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
270
`undef MODULE
271
 
272 5 unneback
   parameter data_width = 32;
273
   parameter addr_width = 8;
274 75 unneback
   parameter mem_size = 1<<addr_width;
275 5 unneback
   input [(data_width-1):0]      d_a;
276
   input [(addr_width-1):0]       adr_a;
277
   input [(addr_width-1):0]       adr_b;
278
   input                         we_a;
279
   output [(data_width-1):0]      q_b;
280
   input [(data_width-1):0]       d_b;
281
   output reg [(data_width-1):0] q_a;
282
   input                         we_b;
283
   input                         clk_a, clk_b;
284
   reg [(data_width-1):0]         q_b;
285 75 unneback
   reg [data_width-1:0] ram [mem_size-1:0] `SYN;
286 7 unneback
 
287
   parameter init = 0;
288
   parameter memory_file = "vl_ram.vmem";
289
   generate if (init) begin : init_mem
290
   initial
291
     begin
292
        $readmemh(memory_file, ram);
293
     end
294
   end
295
   endgenerate
296
 
297 5 unneback
   always @ (posedge clk_a)
298
     begin
299
        q_a <= ram[adr_a];
300
        if (we_a)
301
             ram[adr_a] <= d_a;
302
     end
303
   always @ (posedge clk_b)
304
     begin
305
        q_b <= ram[adr_b];
306
        if (we_b)
307
          ram[adr_b] <= d_b;
308
     end
309
endmodule
310 40 unneback
`endif
311 5 unneback
 
312 83 unneback
 
313 75 unneback
`ifdef DPRAM_BE_2R2W
314
`define MODULE dpram_be_2r2w
315 92 unneback
module `BASE`MODULE ( d_a, q_a, adr_a, be_a, we_a, clk_a, d_b, q_b, adr_b, be_b, we_b, clk_b );
316 75 unneback
`undef MODULE
317
 
318
   parameter a_data_width = 32;
319
   parameter a_addr_width = 8;
320 92 unneback
   parameter b_data_width = a_data_width;
321 91 unneback
   localparam b_addr_width = a_data_width * a_addr_width / b_data_width;
322
   parameter mem_size = (a_addr_width>b_addr_width) ? (1<<a_addr_width) : (1<<b_addr_width);
323
 
324 75 unneback
   input [(a_data_width-1):0]      d_a;
325 91 unneback
   input [(a_addr_width-1):0]       adr_a;
326
   input [(a_data_width/8-1):0]    be_a;
327
   input                           we_a;
328 75 unneback
   output reg [(a_data_width-1):0] q_a;
329 91 unneback
   input [(b_data_width-1):0]       d_b;
330
   input [(b_addr_width-1):0]       adr_b;
331 92 unneback
   input [(b_data_width/8-1):0]    be_b;
332
   input                           we_b;
333
   output reg [(b_data_width-1):0]          q_b;
334 91 unneback
   input                           clk_a, clk_b;
335 75 unneback
 
336 91 unneback
//E2_ifdef SYSTEMVERILOG
337
// use a multi-dimensional packed array
338
//to model individual bytes within the word
339
 
340 75 unneback
generate
341 91 unneback
if (a_data_width==32 & b_data_width==32) begin : dpram_3232
342 75 unneback
 
343 91 unneback
   logic [3:0][7:0] ram [0:mem_size-1];
344
 
345
    always_ff@(posedge clk_a)
346
    begin
347
        if(we_a) begin
348
            if(be_a[3]) ram[adr_a][3] <= d_a[31:24];
349
            if(be_a[2]) ram[adr_a][2] <= d_a[23:16];
350
            if(be_a[1]) ram[adr_a][1] <= d_a[15:8];
351
            if(be_a[0]) ram[adr_a][0] <= d_a[7:0];
352
        end
353
    end
354
 
355 92 unneback
    always@(posedge clk_a)
356
        q_a = ram[adr_a];
357 91 unneback
 
358
    always_ff@(posedge clk_b)
359 92 unneback
    begin
360
        if(we_b) begin
361
            if(be_b[3]) ram[adr_b][3] <= d_b[31:24];
362
            if(be_b[2]) ram[adr_b][2] <= d_b[23:16];
363
            if(be_b[1]) ram[adr_b][1] <= d_b[15:8];
364
            if(be_b[0]) ram[adr_b][0] <= d_b[7:0];
365
        end
366
    end
367 91 unneback
 
368 92 unneback
    always@(posedge clk_b)
369
        q_b = ram[adr_b];
370 91 unneback
 
371 75 unneback
end
372
endgenerate
373
 
374 91 unneback
//E2_else
375 92 unneback
    // This modules requires SystemVerilog
376 91 unneback
//E2_endif
377 75 unneback
endmodule
378
`endif
379
 
380 91 unneback
`ifdef CAM
381 5 unneback
// Content addresable memory, CAM
382 91 unneback
`endif
383 5 unneback
 
384 40 unneback
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
385 5 unneback
// FIFO
386 40 unneback
`define MODULE fifo_1r1w_fill_level_sync
387
module `BASE`MODULE (
388
`undef MODULE
389 25 unneback
    d, wr, fifo_full,
390
    q, rd, fifo_empty,
391
    fill_level,
392
    clk, rst
393
    );
394
 
395
parameter data_width = 18;
396
parameter addr_width = 4;
397 5 unneback
 
398 25 unneback
// write side
399
input  [data_width-1:0] d;
400
input                   wr;
401
output                  fifo_full;
402
// read side
403
output [data_width-1:0] q;
404
input                   rd;
405
output                  fifo_empty;
406
// common
407
output [addr_width:0]   fill_level;
408
input rst, clk;
409
 
410
wire [addr_width:1] wadr, radr;
411
 
412 40 unneback
`define MODULE cnt_bin_ce
413
`BASE`MODULE
414 25 unneback
    # ( .length(addr_width))
415
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
416 40 unneback
`BASE`MODULE
417 25 unneback
    # (.length(addr_width))
418
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
419 40 unneback
`undef MODULE
420 25 unneback
 
421 40 unneback
`define MODULE dpram_1r1w
422
`BASE`MODULE
423 25 unneback
    # (.data_width(data_width), .addr_width(addr_width))
424
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
425 40 unneback
`undef MODULE
426 25 unneback
 
427 40 unneback
`define MODULE cnt_bin_ce_rew_q_zq_l1
428
`BASE`MODULE
429 27 unneback
    # (.length(addr_width+1), .level1_value(1<<addr_width))
430 25 unneback
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
431 40 unneback
`undef MODULE
432 25 unneback
endmodule
433 40 unneback
`endif
434 25 unneback
 
435 40 unneback
`ifdef FIFO_2R2W_SYNC_SIMPLEX
436 27 unneback
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
437
// RAM is supposed to be larger than the two FIFOs
438
// LFSR counters used adr pointers
439 40 unneback
`define MODULE fifo_2r2w_sync_simplex
440
module `BASE`MODULE (
441
`undef MODULE
442 27 unneback
    // a side
443
    a_d, a_wr, a_fifo_full,
444
    a_q, a_rd, a_fifo_empty,
445
    a_fill_level,
446
    // b side
447
    b_d, b_wr, b_fifo_full,
448
    b_q, b_rd, b_fifo_empty,
449
    b_fill_level,
450
    // common
451
    clk, rst
452
    );
453
parameter data_width = 8;
454
parameter addr_width = 5;
455
parameter fifo_full_level = (1<<addr_width)-1;
456
 
457
// a side
458
input  [data_width-1:0] a_d;
459
input                   a_wr;
460
output                  a_fifo_full;
461
output [data_width-1:0] a_q;
462
input                   a_rd;
463
output                  a_fifo_empty;
464
output [addr_width-1:0] a_fill_level;
465
 
466
// b side
467
input  [data_width-1:0] b_d;
468
input                   b_wr;
469
output                  b_fifo_full;
470
output [data_width-1:0] b_q;
471
input                   b_rd;
472
output                  b_fifo_empty;
473
output [addr_width-1:0] b_fill_level;
474
 
475
input                   clk;
476
input                   rst;
477
 
478
// adr_gen
479
wire [addr_width:1] a_wadr, a_radr;
480
wire [addr_width:1] b_wadr, b_radr;
481
// dpram
482
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
483
 
484 40 unneback
`define MODULE cnt_lfsr_ce
485
`BASE`MODULE
486 27 unneback
    # ( .length(addr_width))
487
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
488
 
489 40 unneback
`BASE`MODULE
490 27 unneback
    # (.length(addr_width))
491
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
492
 
493 40 unneback
`BASE`MODULE
494 27 unneback
    # ( .length(addr_width))
495
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
496
 
497 40 unneback
`BASE`MODULE
498 27 unneback
    # (.length(addr_width))
499
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
500 40 unneback
`undef MODULE
501 27 unneback
 
502
// mux read or write adr to DPRAM
503
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
504
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
505
 
506 40 unneback
`define MODULE dpram_2r2w
507
`BASE`MODULE
508 27 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
509
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
510
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
511 40 unneback
`undef MODULE
512
 
513
`define MODULE cnt_bin_ce_rew_zq_l1
514
`BASE`MODULE
515 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
516 27 unneback
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
517
 
518 40 unneback
`BASE`MODULE
519 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
520 27 unneback
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
521 40 unneback
`undef MODULE
522 27 unneback
 
523
endmodule
524 40 unneback
`endif
525 27 unneback
 
526 40 unneback
`ifdef FIFO_CMP_ASYNC
527
`define MODULE fifo_cmp_async
528
module `BASE`MODULE ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
529
`undef MODULE
530 5 unneback
 
531 11 unneback
   parameter addr_width = 4;
532
   parameter N = addr_width-1;
533 5 unneback
 
534
   parameter Q1 = 2'b00;
535
   parameter Q2 = 2'b01;
536
   parameter Q3 = 2'b11;
537
   parameter Q4 = 2'b10;
538
 
539
   parameter going_empty = 1'b0;
540
   parameter going_full  = 1'b1;
541
 
542
   input [N:0]  wptr, rptr;
543 14 unneback
   output       fifo_empty;
544 5 unneback
   output       fifo_full;
545
   input        wclk, rclk, rst;
546
 
547
`ifndef GENERATE_DIRECTION_AS_LATCH
548
   wire direction;
549
`endif
550
`ifdef GENERATE_DIRECTION_AS_LATCH
551
   reg direction;
552
`endif
553
   reg  direction_set, direction_clr;
554
 
555
   wire async_empty, async_full;
556
   wire fifo_full2;
557 14 unneback
   wire fifo_empty2;
558 5 unneback
 
559
   // direction_set
560
   always @ (wptr[N:N-1] or rptr[N:N-1])
561
     case ({wptr[N:N-1],rptr[N:N-1]})
562
       {Q1,Q2} : direction_set <= 1'b1;
563
       {Q2,Q3} : direction_set <= 1'b1;
564
       {Q3,Q4} : direction_set <= 1'b1;
565
       {Q4,Q1} : direction_set <= 1'b1;
566
       default : direction_set <= 1'b0;
567
     endcase
568
 
569
   // direction_clear
570
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
571
     if (rst)
572
       direction_clr <= 1'b1;
573
     else
574
       case ({wptr[N:N-1],rptr[N:N-1]})
575
         {Q2,Q1} : direction_clr <= 1'b1;
576
         {Q3,Q2} : direction_clr <= 1'b1;
577
         {Q4,Q3} : direction_clr <= 1'b1;
578
         {Q1,Q4} : direction_clr <= 1'b1;
579
         default : direction_clr <= 1'b0;
580
       endcase
581
 
582 40 unneback
`define MODULE dff_sr
583 5 unneback
`ifndef GENERATE_DIRECTION_AS_LATCH
584 40 unneback
    `BASE`MODULE dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
585 5 unneback
`endif
586
 
587
`ifdef GENERATE_DIRECTION_AS_LATCH
588
   always @ (posedge direction_set or posedge direction_clr)
589
     if (direction_clr)
590
       direction <= going_empty;
591
     else
592
       direction <= going_full;
593
`endif
594
 
595
   assign async_empty = (wptr == rptr) && (direction==going_empty);
596
   assign async_full  = (wptr == rptr) && (direction==going_full);
597
 
598 40 unneback
    `BASE`MODULE dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
599
    `BASE`MODULE dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
600
`undef MODULE
601 5 unneback
 
602
/*
603
   always @ (posedge wclk or posedge rst or posedge async_full)
604
     if (rst)
605
       {fifo_full, fifo_full2} <= 2'b00;
606
     else if (async_full)
607
       {fifo_full, fifo_full2} <= 2'b11;
608
     else
609
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
610
*/
611 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
612 5 unneback
     if (async_empty)
613
       {fifo_empty, fifo_empty2} <= 2'b11;
614
     else
615 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
616 40 unneback
`define MODULE dff
617
    `BASE`MODULE # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
618
    `BASE`MODULE # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
619
`undef MODULE
620 25 unneback
endmodule // async_compb
621 40 unneback
`endif
622 5 unneback
 
623 40 unneback
`ifdef FIFO_1R1W_ASYNC
624
`define MODULE fifo_1r1w_async
625
module `BASE`MODULE (
626
`undef MODULE
627 5 unneback
    d, wr, fifo_full, wr_clk, wr_rst,
628
    q, rd, fifo_empty, rd_clk, rd_rst
629
    );
630
 
631
parameter data_width = 18;
632
parameter addr_width = 4;
633
 
634
// write side
635
input  [data_width-1:0] d;
636
input                   wr;
637
output                  fifo_full;
638
input                   wr_clk;
639
input                   wr_rst;
640
// read side
641
output [data_width-1:0] q;
642
input                   rd;
643
output                  fifo_empty;
644
input                   rd_clk;
645
input                   rd_rst;
646
 
647
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
648 23 unneback
 
649 40 unneback
`define MODULE cnt_gray_ce_bin
650
`BASE`MODULE
651 5 unneback
    # ( .length(addr_width))
652
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
653
 
654 40 unneback
`BASE`MODULE
655 5 unneback
    # (.length(addr_width))
656 23 unneback
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
657 40 unneback
`undef MODULE
658 5 unneback
 
659 40 unneback
`define MODULE dpram_1r1w
660
`BASE`MODULE
661 5 unneback
    # (.data_width(data_width), .addr_width(addr_width))
662
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
663 40 unneback
`undef MODULE
664 5 unneback
 
665 40 unneback
`define MODULE fifo_cmp_async
666
`BASE`MODULE
667 5 unneback
    # (.addr_width(addr_width))
668
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
669 40 unneback
`undef MODULE
670 5 unneback
 
671
endmodule
672 40 unneback
`endif
673 5 unneback
 
674 40 unneback
`ifdef FIFO_2R2W_ASYNC
675
`define MODULE fifo_2r2w_async
676
module `BASE`MODULE (
677
`undef MODULE
678 5 unneback
    // a side
679
    a_d, a_wr, a_fifo_full,
680
    a_q, a_rd, a_fifo_empty,
681
    a_clk, a_rst,
682
    // b side
683
    b_d, b_wr, b_fifo_full,
684
    b_q, b_rd, b_fifo_empty,
685
    b_clk, b_rst
686
    );
687
 
688
parameter data_width = 18;
689
parameter addr_width = 4;
690
 
691
// a side
692
input  [data_width-1:0] a_d;
693
input                   a_wr;
694
output                  a_fifo_full;
695
output [data_width-1:0] a_q;
696
input                   a_rd;
697
output                  a_fifo_empty;
698
input                   a_clk;
699
input                   a_rst;
700
 
701
// b side
702
input  [data_width-1:0] b_d;
703
input                   b_wr;
704
output                  b_fifo_full;
705
output [data_width-1:0] b_q;
706
input                   b_rd;
707
output                  b_fifo_empty;
708
input                   b_clk;
709
input                   b_rst;
710
 
711 40 unneback
`define MODULE fifo_1r1w_async
712
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
713 5 unneback
vl_fifo_1r1w_async_a (
714
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
715
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
716
    );
717
 
718 40 unneback
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
719 5 unneback
vl_fifo_1r1w_async_b (
720
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
721
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
722
    );
723 40 unneback
`undef MODULE
724
 
725 5 unneback
endmodule
726 40 unneback
`endif
727 5 unneback
 
728 40 unneback
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
729
`define MODULE fifo_2r2w_async_simplex
730
module `BASE`MODULE (
731
`undef MODULE
732 5 unneback
    // a side
733
    a_d, a_wr, a_fifo_full,
734
    a_q, a_rd, a_fifo_empty,
735
    a_clk, a_rst,
736
    // b side
737
    b_d, b_wr, b_fifo_full,
738
    b_q, b_rd, b_fifo_empty,
739
    b_clk, b_rst
740
    );
741
 
742
parameter data_width = 18;
743
parameter addr_width = 4;
744
 
745
// a side
746
input  [data_width-1:0] a_d;
747
input                   a_wr;
748
output                  a_fifo_full;
749
output [data_width-1:0] a_q;
750
input                   a_rd;
751
output                  a_fifo_empty;
752
input                   a_clk;
753
input                   a_rst;
754
 
755
// b side
756
input  [data_width-1:0] b_d;
757
input                   b_wr;
758
output                  b_fifo_full;
759
output [data_width-1:0] b_q;
760
input                   b_rd;
761
output                  b_fifo_empty;
762
input                   b_clk;
763
input                   b_rst;
764
 
765
// adr_gen
766
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
767
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
768
// dpram
769
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
770
 
771 40 unneback
`define MODULE cnt_gray_ce_bin
772
`BASE`MODULE
773 5 unneback
    # ( .length(addr_width))
774
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
775
 
776 40 unneback
`BASE`MODULE
777 5 unneback
    # (.length(addr_width))
778
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
779
 
780 40 unneback
`BASE`MODULE
781 5 unneback
    # ( .length(addr_width))
782
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
783
 
784 40 unneback
`BASE`MODULE
785 5 unneback
    # (.length(addr_width))
786
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
787 40 unneback
`undef MODULE
788 5 unneback
 
789
// mux read or write adr to DPRAM
790
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
791
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
792
 
793 40 unneback
`define MODULE dpram_2r2w
794
`BASE`MODULE
795 5 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
796
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
797
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
798 40 unneback
`undef MODULE
799 5 unneback
 
800 40 unneback
`define MODULE fifo_cmp_async
801
`BASE`MODULE
802 5 unneback
    # (.addr_width(addr_width))
803
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
804
 
805 40 unneback
`BASE`MODULE
806 5 unneback
    # (.addr_width(addr_width))
807
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
808 40 unneback
`undef MODULE
809 5 unneback
 
810
endmodule
811 40 unneback
`endif
812 48 unneback
 
813
`ifdef REG_FILE
814
`define MODULE reg_file
815
module `BASE`MODULE (
816
`undef MODULE
817
    a1, a2, a3, wd3, we3, rd1, rd2, clk
818
);
819
parameter data_width = 32;
820
parameter addr_width = 5;
821
input [addr_width-1:0] a1, a2, a3;
822
input [data_width-1:0] wd3;
823
input we3;
824
output [data_width-1:0] rd1, rd2;
825
input clk;
826
 
827
`ifdef ACTEL
828
reg [data_width-1:0] wd3_reg;
829
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
830
reg we3_reg;
831
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] `SYN;
832
reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] `SYN;
833
always @ (posedge clk or posedge rst)
834
if (rst)
835
    {wd3_reg, a3_reg, we3_reg} <= {(data_width+addr_width+1){1'b0}};
836
else
837
    {wd3_reg, a3_reg, we3_reg} <= {wd3,a3,wd3};
838
 
839
    always @ (negedge clk)
840
    if (we3_reg)
841
        ram1[a3_reg] <= wd3;
842
    always @ (posedge clk)
843
        a1_reg <= a1;
844
    assign rd1 = ram1[a1_reg];
845
 
846
    always @ (negedge clk)
847
    if (we3_reg)
848
        ram2[a3_reg] <= wd3;
849
    always @ (posedge clk)
850
        a2_reg <= a2;
851
    assign rd2 = ram2[a2_reg];
852
 
853
`else
854
 
855
`define MODULE dpram_1r1w
856
`BASE`MODULE
857
    # ( .data_width(data_width), .addr_width(addr_width))
858
    ram1 (
859
        .d_a(wd3),
860
        .adr_a(a3),
861
        .we_a(we3),
862
        .clk_a(clk),
863
        .q_b(rd1),
864
        .adr_b(a1),
865
        .clk_b(clk) );
866
 
867
`BASE`MODULE
868
    # ( .data_width(data_width), .addr_width(addr_width))
869
    ram2 (
870
        .d_a(wd3),
871
        .adr_a(a3),
872
        .we_a(we3),
873
        .clk_a(clk),
874
        .q_b(rd2),
875
        .adr_b(a2),
876
        .clk_b(clk) );
877
`undef MODULE
878
 
879
`endif
880
 
881
endmodule
882
`endif

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