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1 3 unneback
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  Versatile library, registers                                ////
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////                                                              ////
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////  Description                                                 ////
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////  Different type of registers                                 ////
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////                                                              ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - add more different registers                             ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
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////        ORSoC AB                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
42
 
43 18 unneback
module vl_dff ( d, q, clk, rst);
44 3 unneback
 
45
        parameter width = 1;
46
        parameter reset_value = 0;
47
 
48
        input [width-1:0] d;
49
        input clk, rst;
50
        output reg [width-1:0] q;
51
 
52
        always @ (posedge clk or posedge rst)
53
        if (rst)
54
                q <= reset_value;
55
        else
56
                q <= d;
57
 
58
endmodule
59
 
60 18 unneback
module vl_dff_array ( d, q, clk, rst);
61 5 unneback
 
62
        parameter width = 1;
63
        parameter depth = 2;
64
        parameter reset_value = 1'b0;
65
 
66
        input [width-1:0] d;
67
        input clk, rst;
68
        output [width-1:0] q;
69
        reg  [0:depth-1] q_tmp [width-1:0];
70
        integer i;
71
        always @ (posedge clk or posedge rst)
72
        if (rst) begin
73
            for (i=0;i<depth;i=i+1)
74
                q_tmp[i] <= {width{reset_value}};
75
        end else begin
76
            q_tmp[0] <= d;
77
            for (i=1;i<depth;i=i+1)
78
                q_tmp[i] <= q_tmp[i-1];
79
        end
80
 
81
    assign q = q_tmp[depth-1];
82
 
83
endmodule
84
 
85 18 unneback
module vl_dff_ce ( d, ce, q, clk, rst);
86 3 unneback
 
87
        parameter width = 1;
88
        parameter reset_value = 0;
89
 
90
        input [width-1:0] d;
91
        input ce, clk, rst;
92
        output reg [width-1:0] q;
93
 
94
        always @ (posedge clk or posedge rst)
95
        if (rst)
96
                q <= reset_value;
97
        else
98
                if (ce)
99
                        q <= d;
100
 
101
endmodule
102
 
103 18 unneback
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
104 8 unneback
 
105
        parameter width = 1;
106
        parameter reset_value = 0;
107
 
108
        input [width-1:0] d;
109 10 unneback
        input ce, clear, clk, rst;
110 8 unneback
        output reg [width-1:0] q;
111
 
112
        always @ (posedge clk or posedge rst)
113
        if (rst)
114
            q <= reset_value;
115
        else
116
            if (ce)
117
                if (clear)
118
                    q <= {width{1'b0}};
119
                else
120
                    q <= d;
121
 
122
endmodule
123
 
124 24 unneback
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
125
 
126
        parameter width = 1;
127
        parameter reset_value = 0;
128
 
129
        input [width-1:0] d;
130
        input ce, set, clk, rst;
131
        output reg [width-1:0] q;
132
 
133
        always @ (posedge clk or posedge rst)
134
        if (rst)
135
            q <= reset_value;
136
        else
137
            if (ce)
138
                if (set)
139
                    q <= {width{1'b1}};
140
                else
141
                    q <= d;
142
 
143
endmodule
144
 
145 3 unneback
`ifdef ALTERA
146
// megafunction wizard: %LPM_FF%
147
// GENERATION: STANDARD
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// VERSION: WM1.0
149
// MODULE: lpm_ff 
150
 
151
// ============================================================
152
// File Name: dff_sr.v
153
// Megafunction Name(s):
154
//                      lpm_ff
155
//
156
// Simulation Library Files(s):
157
//                      lpm
158
// ============================================================
159
// ************************************************************
160
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
161
//
162
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
163
// ************************************************************
164
 
165
 
166
//Copyright (C) 1991-2010 Altera Corporation
167
//Your use of Altera Corporation's design tools, logic functions 
168
//and other software and tools, and its AMPP partner logic 
169
//functions, and any output files from any of the foregoing 
170
//(including device programming or simulation files), and any 
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//associated documentation or information are expressly subject 
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//to the terms and conditions of the Altera Program License 
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//Subscription Agreement, Altera MegaCore Function License 
174
//Agreement, or other applicable license agreement, including, 
175
//without limitation, that your use is for the sole purpose of 
176
//programming logic devices manufactured by Altera and sold by 
177
//Altera or its authorized distributors.  Please refer to the 
178
//applicable agreement for further details.
179
 
180
 
181
// synopsys translate_off
182
`timescale 1 ps / 1 ps
183
// synopsys translate_on
184 18 unneback
module vl_dff_sr (
185 3 unneback
        aclr,
186
        aset,
187
        clock,
188
        data,
189
        q);
190
 
191
        input     aclr;
192
        input     aset;
193
        input     clock;
194
        input     data;
195
        output    q;
196
 
197
        wire [0:0] sub_wire0;
198
        wire [0:0] sub_wire1 = sub_wire0[0:0];
199
        wire  q = sub_wire1;
200
        wire  sub_wire2 = data;
201
        wire  sub_wire3 = sub_wire2;
202
 
203
        lpm_ff  lpm_ff_component (
204
                                .aclr (aclr),
205
                                .clock (clock),
206
                                .data (sub_wire3),
207
                                .aset (aset),
208
                                .q (sub_wire0)
209
                                // synopsys translate_off
210
                                ,
211
                                .aload (),
212
                                .enable (),
213
                                .sclr (),
214
                                .sload (),
215
                                .sset ()
216
                                // synopsys translate_on
217
                                );
218
        defparam
219
                lpm_ff_component.lpm_fftype = "DFF",
220
                lpm_ff_component.lpm_type = "LPM_FF",
221
                lpm_ff_component.lpm_width = 1;
222
 
223
 
224
endmodule
225
 
226
// ============================================================
227
// CNX file retrieval info
228
// ============================================================
229
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
230
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
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// Retrieval info: PRIVATE: ASET NUMERIC "1"
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// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
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// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
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// Retrieval info: PRIVATE: DFF NUMERIC "1"
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// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
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// Retrieval info: PRIVATE: SCLR NUMERIC "0"
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// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
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// Retrieval info: PRIVATE: SSET NUMERIC "0"
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// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
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// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
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// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
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// Retrieval info: PRIVATE: nBit NUMERIC "1"
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// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
244
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
245
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
246
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
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// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
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// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
249
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
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// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
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// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
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// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
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// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
254
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
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// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
256
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
257
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
258
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
259
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
262
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
263
// Retrieval info: LIB_FILE: lpm
264
 
265
 
266
`else
267
 
268
 
269 18 unneback
module vl_dff_sr ( aclr, aset, clock, data, q);
270 3 unneback
 
271
    input         aclr;
272
    input         aset;
273
    input         clock;
274
    input         data;
275
    output reg    q;
276
 
277
   always @ (posedge clock or posedge aclr or posedge aset)
278
     if (aclr)
279
       q <= 1'b0;
280
     else if (aset)
281
       q <= 1'b1;
282
     else
283
       q <= data;
284
 
285
endmodule
286
 
287
`endif
288 5 unneback
 
289
// LATCH
290
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
291
`ifdef ALTERA
292 18 unneback
module vl_latch ( d, le, q, clk);
293 5 unneback
input d, le;
294
output q;
295
input clk;
296
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
297
endmodule
298
`else
299
module latch ( d, le, q, clk);
300
input d, le;
301
output q;
302
input clk;/*
303
   always @ (posedge direction_set or posedge direction_clr)
304
     if (direction_clr)
305
       direction <= going_empty;
306
     else
307
       direction <= going_full;*/
308
endmodule
309 15 unneback
`endif
310
 
311 18 unneback
module vl_shreg ( d, q, clk, rst);
312 17 unneback
parameter depth = 10;
313
input d;
314
output q;
315
input clk, rst;
316
 
317
reg [1:depth] dffs;
318
 
319
always @ (posedge clk or posedge rst)
320
if (rst)
321
    dffs <= {depth{1'b0}};
322
else
323
    dffs <= {d,dffs[1:depth-1]};
324
assign q = dffs[depth];
325
endmodule
326
 
327 18 unneback
module vl_shreg_ce ( d, ce, q, clk, rst);
328 17 unneback
parameter depth = 10;
329
input d, ce;
330
output q;
331
input clk, rst;
332
 
333
reg [1:depth] dffs;
334
 
335
always @ (posedge clk or posedge rst)
336
if (rst)
337
    dffs <= {depth{1'b0}};
338
else
339
    if (ce)
340
        dffs <= {d,dffs[1:depth-1]};
341
assign q = dffs[depth];
342
endmodule
343
 
344 18 unneback
module vl_delay ( d, q, clk, rst);
345 15 unneback
parameter depth = 10;
346
input d;
347
output q;
348
input clk, rst;
349
 
350
reg [1:depth] dffs;
351
 
352
always @ (posedge clk or posedge rst)
353
if (rst)
354
    dffs <= {depth{1'b0}};
355
else
356
    dffs <= {d,dffs[1:depth-1]};
357
assign q = dffs[depth];
358 17 unneback
endmodule
359
 
360 18 unneback
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
361 17 unneback
parameter depth = 10;
362
input d;
363
output q, emptyflag;
364
input clk, rst;
365
 
366
reg [1:depth] dffs;
367
 
368
always @ (posedge clk or posedge rst)
369
if (rst)
370
    dffs <= {depth{1'b0}};
371
else
372
    dffs <= {d,dffs[1:depth-1]};
373
assign q = dffs[depth];
374
assign emptyflag = !(|dffs);
375
endmodule

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