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1 3 unneback
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  Versatile library, registers                                ////
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////                                                              ////
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////  Description                                                 ////
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////  Different type of registers                                 ////
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////                                                              ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - add more different registers                             ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
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////        ORSoC AB                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
42
 
43 18 unneback
module vl_dff ( d, q, clk, rst);
44 3 unneback
 
45
        parameter width = 1;
46
        parameter reset_value = 0;
47
 
48
        input [width-1:0] d;
49
        input clk, rst;
50
        output reg [width-1:0] q;
51
 
52
        always @ (posedge clk or posedge rst)
53
        if (rst)
54
                q <= reset_value;
55
        else
56
                q <= d;
57
 
58
endmodule
59
 
60 18 unneback
module vl_dff_array ( d, q, clk, rst);
61 5 unneback
 
62
        parameter width = 1;
63
        parameter depth = 2;
64
        parameter reset_value = 1'b0;
65
 
66
        input [width-1:0] d;
67
        input clk, rst;
68
        output [width-1:0] q;
69
        reg  [0:depth-1] q_tmp [width-1:0];
70
        integer i;
71
        always @ (posedge clk or posedge rst)
72
        if (rst) begin
73
            for (i=0;i<depth;i=i+1)
74
                q_tmp[i] <= {width{reset_value}};
75
        end else begin
76
            q_tmp[0] <= d;
77
            for (i=1;i<depth;i=i+1)
78
                q_tmp[i] <= q_tmp[i-1];
79
        end
80
 
81
    assign q = q_tmp[depth-1];
82
 
83
endmodule
84
 
85 18 unneback
module vl_dff_ce ( d, ce, q, clk, rst);
86 3 unneback
 
87
        parameter width = 1;
88
        parameter reset_value = 0;
89
 
90
        input [width-1:0] d;
91
        input ce, clk, rst;
92
        output reg [width-1:0] q;
93
 
94
        always @ (posedge clk or posedge rst)
95
        if (rst)
96
                q <= reset_value;
97
        else
98
                if (ce)
99
                        q <= d;
100
 
101
endmodule
102
 
103 18 unneback
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
104 8 unneback
 
105
        parameter width = 1;
106
        parameter reset_value = 0;
107
 
108
        input [width-1:0] d;
109 10 unneback
        input ce, clear, clk, rst;
110 8 unneback
        output reg [width-1:0] q;
111
 
112
        always @ (posedge clk or posedge rst)
113
        if (rst)
114
            q <= reset_value;
115
        else
116
            if (ce)
117
                if (clear)
118
                    q <= {width{1'b0}};
119
                else
120
                    q <= d;
121
 
122
endmodule
123
 
124 24 unneback
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
125
 
126
        parameter width = 1;
127
        parameter reset_value = 0;
128
 
129
        input [width-1:0] d;
130
        input ce, set, clk, rst;
131
        output reg [width-1:0] q;
132
 
133
        always @ (posedge clk or posedge rst)
134
        if (rst)
135
            q <= reset_value;
136
        else
137
            if (ce)
138
                if (set)
139
                    q <= {width{1'b1}};
140
                else
141
                    q <= d;
142
 
143
endmodule
144
 
145 29 unneback
module vl_spr ( sp, r, q, clk, rst);
146
 
147
        parameter width = 1;
148
        parameter reset_value = 0;
149
 
150
        input sp, r;
151
        output reg q;
152
        input clk, rst;
153
 
154
        always @ (posedge clk or posedge rst)
155
        if (rst)
156
            q <= reset_value;
157
        else
158
            if (sp)
159
                q <= 1'b1;
160
            else if (r)
161
                q <= 1'b0;
162
 
163
endmodule
164
 
165
module vl_srp ( s, rp, q, clk, rst);
166
 
167
        parameter width = 1;
168
        parameter reset_value = 0;
169
 
170
        input s, rp;
171
        output reg q;
172
        input clk, rst;
173
 
174
        always @ (posedge clk or posedge rst)
175
        if (rst)
176
            q <= reset_value;
177
        else
178
            if (rp)
179
                q <= 1'b0;
180
            else if (s)
181
                q <= 1'b1;
182
 
183
endmodule
184
 
185
 
186 3 unneback
`ifdef ALTERA
187
// megafunction wizard: %LPM_FF%
188
// GENERATION: STANDARD
189
// VERSION: WM1.0
190
// MODULE: lpm_ff 
191
 
192
// ============================================================
193
// File Name: dff_sr.v
194
// Megafunction Name(s):
195
//                      lpm_ff
196
//
197
// Simulation Library Files(s):
198
//                      lpm
199
// ============================================================
200
// ************************************************************
201
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
202
//
203
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
204
// ************************************************************
205
 
206
 
207
//Copyright (C) 1991-2010 Altera Corporation
208
//Your use of Altera Corporation's design tools, logic functions 
209
//and other software and tools, and its AMPP partner logic 
210
//functions, and any output files from any of the foregoing 
211
//(including device programming or simulation files), and any 
212
//associated documentation or information are expressly subject 
213
//to the terms and conditions of the Altera Program License 
214
//Subscription Agreement, Altera MegaCore Function License 
215
//Agreement, or other applicable license agreement, including, 
216
//without limitation, that your use is for the sole purpose of 
217
//programming logic devices manufactured by Altera and sold by 
218
//Altera or its authorized distributors.  Please refer to the 
219
//applicable agreement for further details.
220
 
221
 
222
// synopsys translate_off
223
`timescale 1 ps / 1 ps
224
// synopsys translate_on
225 18 unneback
module vl_dff_sr (
226 3 unneback
        aclr,
227
        aset,
228
        clock,
229
        data,
230
        q);
231
 
232
        input     aclr;
233
        input     aset;
234
        input     clock;
235
        input     data;
236
        output    q;
237
 
238
        wire [0:0] sub_wire0;
239
        wire [0:0] sub_wire1 = sub_wire0[0:0];
240
        wire  q = sub_wire1;
241
        wire  sub_wire2 = data;
242
        wire  sub_wire3 = sub_wire2;
243
 
244
        lpm_ff  lpm_ff_component (
245
                                .aclr (aclr),
246
                                .clock (clock),
247
                                .data (sub_wire3),
248
                                .aset (aset),
249
                                .q (sub_wire0)
250
                                // synopsys translate_off
251
                                ,
252
                                .aload (),
253
                                .enable (),
254
                                .sclr (),
255
                                .sload (),
256
                                .sset ()
257
                                // synopsys translate_on
258
                                );
259
        defparam
260
                lpm_ff_component.lpm_fftype = "DFF",
261
                lpm_ff_component.lpm_type = "LPM_FF",
262
                lpm_ff_component.lpm_width = 1;
263
 
264
 
265
endmodule
266
 
267
// ============================================================
268
// CNX file retrieval info
269
// ============================================================
270
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
271
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
272
// Retrieval info: PRIVATE: ASET NUMERIC "1"
273
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
274
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
275
// Retrieval info: PRIVATE: DFF NUMERIC "1"
276
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
277
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
278
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
279
// Retrieval info: PRIVATE: SSET NUMERIC "0"
280
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
281
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
282
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
283
// Retrieval info: PRIVATE: nBit NUMERIC "1"
284
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
285
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
286
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
287
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
288
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
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// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
290
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
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// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
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// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
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// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
294
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
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// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
296
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
297
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
298
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
299
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
300
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
301
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
302
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
303
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
304
// Retrieval info: LIB_FILE: lpm
305
 
306
 
307
`else
308
 
309
 
310 18 unneback
module vl_dff_sr ( aclr, aset, clock, data, q);
311 3 unneback
 
312
    input         aclr;
313
    input         aset;
314
    input         clock;
315
    input         data;
316
    output reg    q;
317
 
318
   always @ (posedge clock or posedge aclr or posedge aset)
319
     if (aclr)
320
       q <= 1'b0;
321
     else if (aset)
322
       q <= 1'b1;
323
     else
324
       q <= data;
325
 
326
endmodule
327
 
328
`endif
329 5 unneback
 
330
// LATCH
331
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
332
`ifdef ALTERA
333 18 unneback
module vl_latch ( d, le, q, clk);
334 5 unneback
input d, le;
335
output q;
336
input clk;
337
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
338
endmodule
339
`else
340
module latch ( d, le, q, clk);
341
input d, le;
342
output q;
343
input clk;/*
344
   always @ (posedge direction_set or posedge direction_clr)
345
     if (direction_clr)
346
       direction <= going_empty;
347
     else
348
       direction <= going_full;*/
349
endmodule
350 15 unneback
`endif
351
 
352 18 unneback
module vl_shreg ( d, q, clk, rst);
353 17 unneback
parameter depth = 10;
354
input d;
355
output q;
356
input clk, rst;
357
 
358
reg [1:depth] dffs;
359
 
360
always @ (posedge clk or posedge rst)
361
if (rst)
362
    dffs <= {depth{1'b0}};
363
else
364
    dffs <= {d,dffs[1:depth-1]};
365
assign q = dffs[depth];
366
endmodule
367
 
368 18 unneback
module vl_shreg_ce ( d, ce, q, clk, rst);
369 17 unneback
parameter depth = 10;
370
input d, ce;
371
output q;
372
input clk, rst;
373
 
374
reg [1:depth] dffs;
375
 
376
always @ (posedge clk or posedge rst)
377
if (rst)
378
    dffs <= {depth{1'b0}};
379
else
380
    if (ce)
381
        dffs <= {d,dffs[1:depth-1]};
382
assign q = dffs[depth];
383
endmodule
384
 
385 18 unneback
module vl_delay ( d, q, clk, rst);
386 15 unneback
parameter depth = 10;
387
input d;
388
output q;
389
input clk, rst;
390
 
391
reg [1:depth] dffs;
392
 
393
always @ (posedge clk or posedge rst)
394
if (rst)
395
    dffs <= {depth{1'b0}};
396
else
397
    dffs <= {d,dffs[1:depth-1]};
398
assign q = dffs[depth];
399 17 unneback
endmodule
400
 
401 18 unneback
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
402 17 unneback
parameter depth = 10;
403
input d;
404
output q, emptyflag;
405
input clk, rst;
406
 
407
reg [1:depth] dffs;
408
 
409
always @ (posedge clk or posedge rst)
410
if (rst)
411
    dffs <= {depth{1'b0}};
412
else
413
    dffs <= {d,dffs[1:depth-1]};
414
assign q = dffs[depth];
415
assign emptyflag = !(|dffs);
416
endmodule

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