OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [registers.v] - Blame information for rev 5

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 3 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  Versatile library, registers                                ////
4
////                                                              ////
5
////  Description                                                 ////
6
////  Different type of registers                                 ////
7
////                                                              ////
8
////                                                              ////
9
////  To Do:                                                      ////
10
////   - add more different registers                             ////
11
////                                                              ////
12
////  Author(s):                                                  ////
13
////      - Michael Unneback, unneback@opencores.org              ////
14
////        ORSoC AB                                              ////
15
////                                                              ////
16
//////////////////////////////////////////////////////////////////////
17
////                                                              ////
18
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
19
////                                                              ////
20
//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
36
////                                                              ////
37
//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
 
43
module dff ( d, q, clk, rst);
44
 
45
        parameter width = 1;
46
        parameter reset_value = 0;
47
 
48
        input [width-1:0] d;
49
        input clk, rst;
50
        output reg [width-1:0] q;
51
 
52
        always @ (posedge clk or posedge rst)
53
        if (rst)
54
                q <= reset_value;
55
        else
56
                q <= d;
57
 
58
endmodule
59
 
60 5 unneback
module dff_array ( d, q, clk, rst);
61
 
62
        parameter width = 1;
63
        parameter depth = 2;
64
        parameter reset_value = 1'b0;
65
 
66
        input [width-1:0] d;
67
        input clk, rst;
68
        output [width-1:0] q;
69
        reg  [0:depth-1] q_tmp [width-1:0];
70
        integer i;
71
        always @ (posedge clk or posedge rst)
72
        if (rst) begin
73
            for (i=0;i<depth;i=i+1)
74
                q_tmp[i] <= {width{reset_value}};
75
        end else begin
76
            q_tmp[0] <= d;
77
            for (i=1;i<depth;i=i+1)
78
                q_tmp[i] <= q_tmp[i-1];
79
        end
80
 
81
    assign q = q_tmp[depth-1];
82
 
83
endmodule
84
 
85 3 unneback
module dff_ce ( d, ce, q, clk, rst);
86
 
87
        parameter width = 1;
88
        parameter reset_value = 0;
89
 
90
        input [width-1:0] d;
91
        input ce, clk, rst;
92
        output reg [width-1:0] q;
93
 
94
        always @ (posedge clk or posedge rst)
95
        if (rst)
96
                q <= reset_value;
97
        else
98
                if (ce)
99
                        q <= d;
100
 
101
endmodule
102
 
103
`ifdef ALTERA
104
// megafunction wizard: %LPM_FF%
105
// GENERATION: STANDARD
106
// VERSION: WM1.0
107
// MODULE: lpm_ff 
108
 
109
// ============================================================
110
// File Name: dff_sr.v
111
// Megafunction Name(s):
112
//                      lpm_ff
113
//
114
// Simulation Library Files(s):
115
//                      lpm
116
// ============================================================
117
// ************************************************************
118
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
119
//
120
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
121
// ************************************************************
122
 
123
 
124
//Copyright (C) 1991-2010 Altera Corporation
125
//Your use of Altera Corporation's design tools, logic functions 
126
//and other software and tools, and its AMPP partner logic 
127
//functions, and any output files from any of the foregoing 
128
//(including device programming or simulation files), and any 
129
//associated documentation or information are expressly subject 
130
//to the terms and conditions of the Altera Program License 
131
//Subscription Agreement, Altera MegaCore Function License 
132
//Agreement, or other applicable license agreement, including, 
133
//without limitation, that your use is for the sole purpose of 
134
//programming logic devices manufactured by Altera and sold by 
135
//Altera or its authorized distributors.  Please refer to the 
136
//applicable agreement for further details.
137
 
138
 
139
// synopsys translate_off
140
`timescale 1 ps / 1 ps
141
// synopsys translate_on
142
module dff_sr (
143
        aclr,
144
        aset,
145
        clock,
146
        data,
147
        q);
148
 
149
        input     aclr;
150
        input     aset;
151
        input     clock;
152
        input     data;
153
        output    q;
154
 
155
        wire [0:0] sub_wire0;
156
        wire [0:0] sub_wire1 = sub_wire0[0:0];
157
        wire  q = sub_wire1;
158
        wire  sub_wire2 = data;
159
        wire  sub_wire3 = sub_wire2;
160
 
161
        lpm_ff  lpm_ff_component (
162
                                .aclr (aclr),
163
                                .clock (clock),
164
                                .data (sub_wire3),
165
                                .aset (aset),
166
                                .q (sub_wire0)
167
                                // synopsys translate_off
168
                                ,
169
                                .aload (),
170
                                .enable (),
171
                                .sclr (),
172
                                .sload (),
173
                                .sset ()
174
                                // synopsys translate_on
175
                                );
176
        defparam
177
                lpm_ff_component.lpm_fftype = "DFF",
178
                lpm_ff_component.lpm_type = "LPM_FF",
179
                lpm_ff_component.lpm_width = 1;
180
 
181
 
182
endmodule
183
 
184
// ============================================================
185
// CNX file retrieval info
186
// ============================================================
187
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
188
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
189
// Retrieval info: PRIVATE: ASET NUMERIC "1"
190
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
191
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
192
// Retrieval info: PRIVATE: DFF NUMERIC "1"
193
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
194
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
195
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
196
// Retrieval info: PRIVATE: SSET NUMERIC "0"
197
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
198
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
199
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
200
// Retrieval info: PRIVATE: nBit NUMERIC "1"
201
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
202
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
203
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
204
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
205
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
206
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
207
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
208
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
209
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
210
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
211
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
212
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
213
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
214
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
215
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
216
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
217
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
218
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
219
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
220
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
221
// Retrieval info: LIB_FILE: lpm
222
 
223
 
224
`else
225
 
226
 
227
module dff_sr ( aclr, aset, clock, data, q);
228
 
229
    input         aclr;
230
    input         aset;
231
    input         clock;
232
    input         data;
233
    output reg    q;
234
 
235
   always @ (posedge clock or posedge aclr or posedge aset)
236
     if (aclr)
237
       q <= 1'b0;
238
     else if (aset)
239
       q <= 1'b1;
240
     else
241
       q <= data;
242
 
243
endmodule
244
 
245
`endif
246 5 unneback
 
247
// LATCH
248
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
249
`ifdef ALTERA
250
module latch ( d, le, q, clk);
251
input d, le;
252
output q;
253
input clk;
254
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
255
endmodule
256
`else
257
module latch ( d, le, q, clk);
258
input d, le;
259
output q;
260
input clk;/*
261
   always @ (posedge direction_set or posedge direction_clr)
262
     if (direction_clr)
263
       direction <= going_empty;
264
     else
265
       direction <= going_full;*/
266
endmodule
267
`endif

powered by: WebSVN 2.1.0

© copyright 1999-2021 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.