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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Blame information for rev 100

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Line No. Rev Author Line
1 40 unneback 
`ifndef BASE
2 
`define BASE vl_
3 
`endif
4 
 
5 60 unneback 
// default SYN_KEEP definition
6 
`define SYN_KEEP /*synthesis syn_keep = 1*/
7 
 
8 44 unneback 
`ifdef ACTEL
9 60 unneback 
`undef SYN_KEEP
10 44 unneback 
`define SYN_KEEP /*synthesis syn_keep = 1*/
11 
`endif
12 
 
13 98 unneback 
`ifdef ACTEL
14 
    // ACTEL FPGA should not use logic to handle rw collision
15 
    `define SYN_NO_RW_CHECK /*synthesis syn_ramstyle = "no_rw_check"*/
16 
`else
17 
    `define SYN_NO_RW_CHECK
18 
`endif
19 
 
20 40 unneback 
`ifdef ALL
21 
 
22 
`define GBUF
23 
`define SYNC_RST
24 
`define PLL
25 
 
26 
`define MULTS
27 
`define MULTS18X18
28 
`define MULT
29 
`define SHIFT_UNIT_32
30 
`define LOGIC_UNIT
31 
 
32 
`define CNT_SHREG_WRAP
33 
`define CNT_SHREG_CE_WRAP
34 
`define CNT_SHREG_CE_CLEAR
35 
`define CNT_SHREG_CE_CLEAR_WRAP
36 
 
37 
`define MUX_ANDOR
38 
`define MUX2_ANDOR
39 
`define MUX3_ANDOR
40 
`define MUX4_ANDOR
41 
`define MUX5_ANDOR
42 
`define MUX6_ANDOR
43 43 unneback 
`define PARITY
44 40 unneback 
 
45 
`define ROM_INIT
46 
`define RAM
47 
`define RAM_BE
48 
`define DPRAM_1R1W
49 
`define DPRAM_2R1W
50 100 unneback 
`define DPRAM_1R2W
51 40 unneback 
`define DPRAM_2R2W
52 75 unneback 
`define DPRAM_BE_2R2W
53 40 unneback 
`define FIFO_1R1W_FILL_LEVEL_SYNC
54 
`define FIFO_2R2W_SYNC_SIMPLEX
55 
`define FIFO_CMP_ASYNC
56 
`define FIFO_1R1W_ASYNC
57 
`define FIFO_2R2W_ASYNC
58 
`define FIFO_2R2W_ASYNC_SIMPLEX
59 48 unneback 
`define REG_FILE
60 40 unneback 
 
61 
`define DFF
62 
`define DFF_ARRAY
63 
`define DFF_CE
64 
`define DFF_CE_CLEAR
65 
`define DF_CE_SET
66 
`define SPR
67 
`define SRP
68 
`define DFF_SR
69 
`define LATCH
70 
`define SHREG
71 
`define SHREG_CE
72 
`define DELAY
73 
`define DELAY_EMPTYFLAG
74 94 unneback 
`define PULSE2TOGGLE
75 
`define TOGGLE2PULSE
76 
`define SYNCHRONIZER
77 
`define CDC
78 40 unneback 
 
79 75 unneback 
`define WB3AVALON_BRIDGE
80 40 unneback 
`define WB3WB3_BRIDGE
81 
`define WB3_ARBITER_TYPE1
82 83 unneback 
`define WB_ADR_INC
83 59 unneback 
`define WB_B3_RAM_BE
84 49 unneback 
`define WB_B4_RAM_BE
85 48 unneback 
`define WB_B4_ROM
86 40 unneback 
`define WB_BOOT_ROM
87 
`define WB_DPRAM
88 97 unneback 
`define WBB3_WBB4_CACHE
89 40 unneback 
 
90 44 unneback 
`define IO_DFF_OE
91 
`define O_DFF
92 
 
93 40 unneback 
`endif
94 
 
95 
`ifdef PLL
96 
`ifndef SYNC_RST
97 
`define SYNC_RST
98 
`endif
99 
`endif
100 
 
101 
`ifdef SYNC_RST
102 
`ifndef GBUF
103 
`define GBUF
104 
`endif
105 
`endif
106 
 
107 92 unneback 
`ifdef WB_B3_DPRAM
108 
`ifndef WB_ADR_INC
109 
`define WB_ADR_INC
110 40 unneback 
`endif
111 92 unneback 
`ifndef DPRAM_BE_2R2W
112 
`define DPRAM_BE_2R2W
113 40 unneback 
`endif
114 
`endif
115 
 
116 62 unneback 
`ifdef WB_B3_RAM_BE
117 83 unneback 
`ifndef WB_ADR_INC
118 
`define WB_ADR_INC
119 62 unneback 
`endif
120 
`ifndef RAM_BE
121 
`define RAM_BE
122 
`endif
123 
`endif
124 
 
125 40 unneback 
`ifdef WB3_ARBITER_TYPE1
126 42 unneback 
`ifndef SPR
127 
`define SPR
128 
`endif
129 40 unneback 
`ifndef MUX_ANDOR
130 
`define MUX_ANDOR
131 
`endif
132 
`endif
133 
 
134 76 unneback 
`ifdef WB3AVALON_BRIDGE
135 
`ifndef WB3WB3_BRIDGE
136 
`define WB3WB3_BRIDGE
137 
`endif
138 
`endif
139 
 
140 40 unneback 
`ifdef WB3WB3_BRIDGE
141 
`ifndef CNT_SHREG_CE_CLEAR
142 
`define CNT_SHREG_CE_CLEAR
143 
`endif
144 
`ifndef DFF
145 
`define DFF
146 
`endif
147 
`ifndef DFF_CE
148 
`define DFF_CE
149 
`endif
150 
`ifndef CNT_SHREG_CE_CLEAR
151 
`define CNT_SHREG_CE_CLEAR
152 
`endif
153 
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
154 
`define FIFO_2R2W_ASYNC_SIMPLEX
155 
`endif
156 
`endif
157 
 
158 100 unneback 
`ifdef WBB3_WBB4_CACHE
159 
`ifndef RAM
160 
`define RAM
161 
`endif
162 
`ifndef WB_ADR_INC
163 
`define WB_ADR_INC
164 
`endif
165 
`ifndef DPRAM_1R1W
166 
`define DPRAM_1R1W
167 
`endif
168 
`ifndef DPRAM_1R2W
169 
`define DPRAM_1R2W
170 
`endif
171 
`ifndef DPRAM_BE_2R2W
172 
`define DPRAM_BE_2R2W
173 
`endif
174 
`ifndef CDC
175 
`define CDC
176 
`endif
177 
`endif
178 97 unneback 
 
179 40 unneback 
`ifdef MULTS18X18
180 
`ifndef MULTS
181 
`define MULTS
182 
`endif
183 
`endif
184 
 
185 
`ifdef SHIFT_UNIT_32
186 
`ifndef MULTS
187 
`define MULTS
188 
`endif
189 
`endif
190 
 
191 
`ifdef MUX2_ANDOR
192 
`ifndef MUX_ANDOR
193 
`define MUX_ANDOR
194 
`endif
195 
`endif
196 
 
197 
`ifdef MUX3_ANDOR
198 
`ifndef MUX_ANDOR
199 
`define MUX_ANDOR
200 
`endif
201 
`endif
202 
 
203 
`ifdef MUX4_ANDOR
204 
`ifndef MUX_ANDOR
205 
`define MUX_ANDOR
206 
`endif
207 
`endif
208 
 
209 
`ifdef MUX5_ANDOR
210 
`ifndef MUX_ANDOR
211 
`define MUX_ANDOR
212 
`endif
213 
`endif
214 
 
215 
`ifdef MUX6_ANDOR
216 
`ifndef MUX_ANDOR
217 
`define MUX_ANDOR
218 
`endif
219 
`endif
220 
 
221 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
222 
`ifndef CNT_BIN_CE
223 
`define CNT_BIN_CE
224 
`endif
225 
`ifndef DPRAM_1R1W
226 
`define DPRAM_1R1W
227 
`endif
228 
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
229 
`define CNT_BIN_CE_REW_Q_ZQ_L1
230 
`endif
231 
`endif
232 
 
233 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
234 
`ifndef CNT_LFSR_CE
235 
`define CNT_LFSR_CE
236 
`endif
237 
`ifndef DPRAM_2R2W
238 
`define DPRAM_2R2W
239 
`endif
240 
`ifndef CNT_BIN_CE_REW_ZQ_L1
241 
`define CNT_BIN_CE_REW_ZQ_L1
242 
`endif
243 
`endif
244 
 
245 
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
246 
`ifndef CNT_GRAY_CE_BIN
247 
`define CNT_GRAY_CE_BIN
248 
`endif
249 
`ifndef DPRAM_2R2W
250 
`define DPRAM_2R2W
251 
`endif
252 
`ifndef FIFO_CMP_ASYNC
253 
`define FIFO_CMP_ASYNC
254 
`endif
255 
`endif
256 
 
257 
`ifdef FIFO_2R2W_ASYNC
258 
`ifndef FIFO_1R1W_ASYNC
259 
`define FIFO_1R1W_ASYNC
260 
`endif
261 
`endif
262 
 
263 
`ifdef FIFO_1R1W_ASYNC
264 
`ifndef CNT_GRAY_CE_BIN
265 
`define CNT_GRAY_CE_BIN
266 
`endif
267 
`ifndef DPRAM_1R1W
268 
`define DPRAM_1R1W
269 
`endif
270 
`ifndef FIFO_CMP_ASYNC
271 
`define FIFO_CMP_ASYNC
272 
`endif
273 
`endif
274 
 
275 
`ifdef FIFO_CMP_ASYNC
276 
`ifndef DFF_SR
277 
`define DFF_SR
278 
`endif
279 
`ifndef DFF
280 
`define DFF
281 
`endif
282 
`endif
283 48 unneback 
 
284 
`ifdef REG_FILE
285 
`ifndef DPRAM_1R1W
286 
`define DPRAM_1R1W
287 
`endif
288 
`endif
289 97 unneback 
 
290 98 unneback 
`ifdef CDC
291 
`ifndef PULSE2TOGGLE
292 
`define PULSE2TOGGLE
293 
`endif
294 
`ifndef TOGGLE2PULSE
295 
`define TOGGLE2PULSE
296 
`endif
297 
`ifndef SYNCHRONIZER
298 
`define SYNCHRONIZER
299 
`endif
300 
`endif
301 
 
302 97 unneback 
// size to width
303 100 unneback 
`define SIZE2WIDTH_EXPR = (`SIZE2WIDTH==1) ? 0 : (`SIZE2WIDTH==2) ? 1 : (`SIZE2WIDTH==4) ? 2 : (`SIZE2WIDTH==8) ? 3 : (`SIZE2WIDTH==16) ? 4 : (`SIZE2WIDTH==32) ? 5 : (`SIZE2WIDTH==64) ? 6 : (`SIZE2WIDTH==128) ? 7 : 8;
304 62 unneback 
//////////////////////////////////////////////////////////////////////
305 6 unneback 
////                                                              ////
306 
////  Versatile library, clock and reset                          ////
307 
////                                                              ////
308 
////  Description                                                 ////
309 
////  Logic related to clock and reset                            ////
310 
////                                                              ////
311 
////                                                              ////
312 
////  To Do:                                                      ////
313 
////   - add more different registers                             ////
314 
////                                                              ////
315 
////  Author(s):                                                  ////
316 
////      - Michael Unneback, unneback@opencores.org              ////
317 
////        ORSoC AB                                              ////
318 
////                                                              ////
319 
//////////////////////////////////////////////////////////////////////
320 
////                                                              ////
321 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
322 
////                                                              ////
323 
//// This source file may be used and distributed without         ////
324 
//// restriction provided that this copyright statement is not    ////
325 
//// removed from the file and that any derivative work contains  ////
326 
//// the original copyright notice and the associated disclaimer. ////
327 
////                                                              ////
328 
//// This source file is free software; you can redistribute it   ////
329 
//// and/or modify it under the terms of the GNU Lesser General   ////
330 
//// Public License as published by the Free Software Foundation; ////
331 
//// either version 2.1 of the License, or (at your option) any   ////
332 
//// later version.                                               ////
333 
////                                                              ////
334 
//// This source is distributed in the hope that it will be       ////
335 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
336 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
337 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
338 
//// details.                                                     ////
339 
////                                                              ////
340 
//// You should have received a copy of the GNU Lesser General    ////
341 
//// Public License along with this source; if not, download it   ////
342 
//// from http://www.opencores.org/lgpl.shtml                     ////
343 
////                                                              ////
344 
//////////////////////////////////////////////////////////////////////
345 
 
346 48 unneback 
`ifdef ACTEL
347 
`ifdef GBUF
348 
`timescale 1 ns/100 ps
349 6 unneback 
// Global buffer
350 
// usage:
351 
// use to enable global buffers for high fan out signals such as clock and reset
352 
// Version: 8.4 8.4.0.33
353 
module gbuf(GL,CLK);
354 
output GL;
355 
input  CLK;
356 
 
357 
    wire GND;
358 
 
359 
    GND GND_1_net(.Y(GND));
360 
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
361 
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
362 
 
363 
endmodule
364 
`timescale 1 ns/1 ns
365 40 unneback 
`define MODULE gbuf
366 
module `BASE`MODULE ( i, o);
367 
`undef MODULE
368 6 unneback 
input i;
369 
output o;
370 
`ifdef SIM_GBUF
371 
assign o=i;
372 
`else
373 
gbuf gbuf_i0 ( .CLK(i), .GL(o));
374 
`endif
375 
endmodule
376 40 unneback 
`endif
377 33 unneback 
 
378 6 unneback 
`else
379 33 unneback 
 
380 40 unneback 
`ifdef ALTERA
381 
`ifdef GBUF
382 21 unneback 
//altera
383 40 unneback 
`define MODULE gbuf
384 
module `BASE`MODULE ( i, o);
385 
`undef MODULE
386 33 unneback 
input i;
387 
output o;
388 
assign o = i;
389 
endmodule
390 40 unneback 
`endif
391 33 unneback 
 
392 6 unneback 
`else
393 
 
394 40 unneback 
`ifdef GBUF
395 6 unneback 
`timescale 1 ns/100 ps
396 40 unneback 
`define MODULE
397 
module `BASE`MODULE ( i, o);
398 
`undef MODULE
399 6 unneback 
input i;
400 
output o;
401 
assign o = i;
402 
endmodule
403 40 unneback 
`endif
404 6 unneback 
`endif // ALTERA
405 
`endif //ACTEL
406 
 
407 40 unneback 
`ifdef SYNC_RST
408 6 unneback 
// sync reset
409 17 unneback 
// input active lo async reset, normally from external reset generator and/or switch
410 6 unneback 
// output active high global reset sync with two DFFs
411 
`timescale 1 ns/100 ps
412 40 unneback 
`define MODULE sync_rst
413 
module `BASE`MODULE ( rst_n_i, rst_o, clk);
414 
`undef MODULE
415 6 unneback 
input rst_n_i, clk;
416 
output rst_o;
417 18 unneback 
reg [1:0] tmp;
418 6 unneback 
always @ (posedge clk or negedge rst_n_i)
419 
if (!rst_n_i)
420 17 unneback 
        tmp <= 2'b11;
421 6 unneback 
else
422 33 unneback 
        tmp <= {1'b0,tmp[1]};
423 40 unneback 
`define MODULE gbuf
424 
`BASE`MODULE buf_i0( .i(tmp[0]), .o(rst_o));
425 
`undef MODULE
426 6 unneback 
endmodule
427 40 unneback 
`endif
428 6 unneback 
 
429 40 unneback 
`ifdef PLL
430 6 unneback 
// vl_pll
431 
`ifdef ACTEL
432 32 unneback 
///////////////////////////////////////////////////////////////////////////////
433 17 unneback 
`timescale 1 ps/1 ps
434 40 unneback 
`define MODULE pll
435 
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
436 
`undef MODULE
437 6 unneback 
parameter index = 0;
438 
parameter number_of_clk = 1;
439 17 unneback 
parameter period_time_0 = 20000;
440 
parameter period_time_1 = 20000;
441 
parameter period_time_2 = 20000;
442 
parameter lock_delay = 2000000;
443 6 unneback 
input clk_i, rst_n_i;
444 
output lock;
445 
output reg [0:number_of_clk-1] clk_o;
446 
output [0:number_of_clk-1] rst_o;
447 
 
448 
`ifdef SIM_PLL
449 
 
450 
always
451 
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
452 
 
453 
generate if (number_of_clk > 1)
454 
always
455 
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
456 
endgenerate
457 
 
458 
generate if (number_of_clk > 2)
459 
always
460 
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
461 
endgenerate
462 
 
463 
genvar i;
464 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
465 
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
466 
end
467 
endgenerate
468 
 
469 
assign #lock_delay lock = rst_n_i;
470 
 
471 
endmodule
472 
`else
473 
generate if (number_of_clk==1 & index==0) begin
474 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
475 
end
476 
endgenerate // index==0
477 
generate if (number_of_clk==1 & index==1) begin
478 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
479 
end
480 
endgenerate // index==1
481 
generate if (number_of_clk==1 & index==2) begin
482 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
483 
end
484 
endgenerate // index==2
485 
generate if (number_of_clk==1 & index==3) begin
486 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
487 
end
488 
endgenerate // index==0
489 
 
490 
generate if (number_of_clk==2 & index==0) begin
491 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
492 
end
493 
endgenerate // index==0
494 
generate if (number_of_clk==2 & index==1) begin
495 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
496 
end
497 
endgenerate // index==1
498 
generate if (number_of_clk==2 & index==2) begin
499 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
500 
end
501 
endgenerate // index==2
502 
generate if (number_of_clk==2 & index==3) begin
503 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
504 
end
505 
endgenerate // index==0
506 
 
507 
generate if (number_of_clk==3 & index==0) begin
508 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
509 
end
510 
endgenerate // index==0
511 
generate if (number_of_clk==3 & index==1) begin
512 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
513 
end
514 
endgenerate // index==1
515 
generate if (number_of_clk==3 & index==2) begin
516 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
517 
end
518 
endgenerate // index==2
519 
generate if (number_of_clk==3 & index==3) begin
520 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
521 
end
522 
endgenerate // index==0
523 
 
524 
genvar i;
525 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
526 40 unneback 
`define MODULE sync_rst
527 
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
528 
`undef MODULE
529 6 unneback 
end
530 
endgenerate
531 
endmodule
532 
`endif
533 32 unneback 
///////////////////////////////////////////////////////////////////////////////
534 6 unneback 
 
535 
`else
536 
 
537 32 unneback 
///////////////////////////////////////////////////////////////////////////////
538 6 unneback 
`ifdef ALTERA
539 
 
540 32 unneback 
`timescale 1 ps/1 ps
541 40 unneback 
`define MODULE pll
542 
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
543 
`undef MODULE
544 32 unneback 
parameter index = 0;
545 
parameter number_of_clk = 1;
546 
parameter period_time_0 = 20000;
547 
parameter period_time_1 = 20000;
548 
parameter period_time_2 = 20000;
549 
parameter period_time_3 = 20000;
550 
parameter period_time_4 = 20000;
551 
parameter lock_delay = 2000000;
552 
input clk_i, rst_n_i;
553 
output lock;
554 
output reg [0:number_of_clk-1] clk_o;
555 
output [0:number_of_clk-1] rst_o;
556 
 
557 
`ifdef SIM_PLL
558 
 
559 
always
560 
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
561 
 
562 
generate if (number_of_clk > 1)
563 
always
564 
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
565 
endgenerate
566 
 
567 
generate if (number_of_clk > 2)
568 
always
569 
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
570 
endgenerate
571 
 
572 33 unneback 
generate if (number_of_clk > 3)
573 32 unneback 
always
574 
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
575 
endgenerate
576 
 
577 33 unneback 
generate if (number_of_clk > 4)
578 32 unneback 
always
579 
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
580 
endgenerate
581 
 
582 
genvar i;
583 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
584 
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
585 
end
586 
endgenerate
587 
 
588 33 unneback 
//assign #lock_delay lock = rst_n_i;
589 
assign lock = rst_n_i;
590 32 unneback 
 
591 
endmodule
592 6 unneback 
`else
593 
 
594 33 unneback 
`ifdef VL_PLL0
595 
`ifdef VL_PLL0_CLK1
596 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
597 
`endif
598 
`ifdef VL_PLL0_CLK2
599 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
600 
`endif
601 
`ifdef VL_PLL0_CLK3
602 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
603 
`endif
604 
`ifdef VL_PLL0_CLK4
605 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
606 
`endif
607 
`ifdef VL_PLL0_CLK5
608 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
609 
`endif
610 
`endif
611 32 unneback 
 
612 33 unneback 
`ifdef VL_PLL1
613 
`ifdef VL_PLL1_CLK1
614 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
615 
`endif
616 
`ifdef VL_PLL1_CLK2
617 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
618 
`endif
619 
`ifdef VL_PLL1_CLK3
620 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
621 
`endif
622 
`ifdef VL_PLL1_CLK4
623 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
624 
`endif
625 
`ifdef VL_PLL1_CLK5
626 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
627 
`endif
628 
`endif
629 32 unneback 
 
630 33 unneback 
`ifdef VL_PLL2
631 
`ifdef VL_PLL2_CLK1
632 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
633 
`endif
634 
`ifdef VL_PLL2_CLK2
635 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
636 
`endif
637 
`ifdef VL_PLL2_CLK3
638 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
639 
`endif
640 
`ifdef VL_PLL2_CLK4
641 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
642 
`endif
643 
`ifdef VL_PLL2_CLK5
644 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
645 
`endif
646 
`endif
647 32 unneback 
 
648 33 unneback 
`ifdef VL_PLL3
649 
`ifdef VL_PLL3_CLK1
650 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
651 
`endif
652 
`ifdef VL_PLL3_CLK2
653 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
654 
`endif
655 
`ifdef VL_PLL3_CLK3
656 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
657 
`endif
658 
`ifdef VL_PLL3_CLK4
659 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
660 
`endif
661 
`ifdef VL_PLL3_CLK5
662 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
663 
`endif
664 
`endif
665 32 unneback 
 
666 
genvar i;
667 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
668 40 unneback 
`define MODULE sync_rst
669 
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
670 
`undef MODULE
671 32 unneback 
end
672 
endgenerate
673 
endmodule
674 
`endif
675 
///////////////////////////////////////////////////////////////////////////////
676 
 
677 
`else
678 
 
679 6 unneback 
// generic PLL
680 17 unneback 
`timescale 1 ps/1 ps
681 40 unneback 
`define MODULE pll
682 
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
683 
`undef MODULE
684 6 unneback 
parameter index = 0;
685 
parameter number_of_clk = 1;
686 17 unneback 
parameter period_time_0 = 20000;
687 
parameter period_time_1 = 20000;
688 
parameter period_time_2 = 20000;
689 6 unneback 
parameter lock_delay = 2000;
690 
input clk_i, rst_n_i;
691 
output lock;
692 
output reg [0:number_of_clk-1] clk_o;
693 
output [0:number_of_clk-1] rst_o;
694 
 
695 
always
696 
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
697 
 
698 
generate if (number_of_clk > 1)
699 
always
700 
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
701 
endgenerate
702 
 
703 
generate if (number_of_clk > 2)
704 
always
705 
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
706 
endgenerate
707 
 
708 
genvar i;
709 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
710 40 unneback 
`define MODULE sync_rst
711 
     `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
712 
`undef MODULE
713 6 unneback 
end
714 
endgenerate
715 
 
716 
assign #lock_delay lock = rst_n_i;
717 
 
718 
endmodule
719 
 
720 
`endif //altera
721 17 unneback 
`endif //actel
722 40 unneback 
`undef MODULE
723 
`endif//////////////////////////////////////////////////////////////////////
724 6 unneback 
////                                                              ////
725 
////  Versatile library, registers                                ////
726 
////                                                              ////
727 
////  Description                                                 ////
728 
////  Different type of registers                                 ////
729 
////                                                              ////
730 
////                                                              ////
731 
////  To Do:                                                      ////
732 
////   - add more different registers                             ////
733 
////                                                              ////
734 
////  Author(s):                                                  ////
735 
////      - Michael Unneback, unneback@opencores.org              ////
736 
////        ORSoC AB                                              ////
737 
////                                                              ////
738 
//////////////////////////////////////////////////////////////////////
739 
////                                                              ////
740 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
741 
////                                                              ////
742 
//// This source file may be used and distributed without         ////
743 
//// restriction provided that this copyright statement is not    ////
744 
//// removed from the file and that any derivative work contains  ////
745 
//// the original copyright notice and the associated disclaimer. ////
746 
////                                                              ////
747 
//// This source file is free software; you can redistribute it   ////
748 
//// and/or modify it under the terms of the GNU Lesser General   ////
749 
//// Public License as published by the Free Software Foundation; ////
750 
//// either version 2.1 of the License, or (at your option) any   ////
751 
//// later version.                                               ////
752 
////                                                              ////
753 
//// This source is distributed in the hope that it will be       ////
754 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
755 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
756 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
757 
//// details.                                                     ////
758 
////                                                              ////
759 
//// You should have received a copy of the GNU Lesser General    ////
760 
//// Public License along with this source; if not, download it   ////
761 
//// from http://www.opencores.org/lgpl.shtml                     ////
762 
////                                                              ////
763 
//////////////////////////////////////////////////////////////////////
764 
 
765 40 unneback 
`ifdef DFF
766 
`define MODULE dff
767 
module `BASE`MODULE ( d, q, clk, rst);
768 
`undef MODULE
769 6 unneback 
        parameter width = 1;
770 
        parameter reset_value = 0;
771 
 
772 
        input [width-1:0] d;
773 
        input clk, rst;
774 
        output reg [width-1:0] q;
775 
 
776 
        always @ (posedge clk or posedge rst)
777 
        if (rst)
778 
                q <= reset_value;
779 
        else
780 
                q <= d;
781 
 
782 
endmodule
783 40 unneback 
`endif
784 6 unneback 
 
785 40 unneback 
`ifdef DFF_ARRAY
786 
`define MODULE dff_array
787 
module `BASE`MODULE ( d, q, clk, rst);
788 
`undef MODULE
789 6 unneback 
 
790 
        parameter width = 1;
791 
        parameter depth = 2;
792 
        parameter reset_value = 1'b0;
793 
 
794 
        input [width-1:0] d;
795 
        input clk, rst;
796 
        output [width-1:0] q;
797 
        reg  [0:depth-1] q_tmp [width-1:0];
798 
        integer i;
799 
        always @ (posedge clk or posedge rst)
800 
        if (rst) begin
801 
            for (i=0;i<depth;i=i+1)
802 
                q_tmp[i] <= {width{reset_value}};
803 
        end else begin
804 
            q_tmp[0] <= d;
805 
            for (i=1;i<depth;i=i+1)
806 
                q_tmp[i] <= q_tmp[i-1];
807 
        end
808 
 
809 
    assign q = q_tmp[depth-1];
810 
 
811 
endmodule
812 40 unneback 
`endif
813 6 unneback 
 
814 40 unneback 
`ifdef DFF_CE
815 
`define MODULE dff_ce
816 
module `BASE`MODULE ( d, ce, q, clk, rst);
817 
`undef MODULE
818 6 unneback 
 
819 
        parameter width = 1;
820 
        parameter reset_value = 0;
821 
 
822 
        input [width-1:0] d;
823 
        input ce, clk, rst;
824 
        output reg [width-1:0] q;
825 
 
826 
        always @ (posedge clk or posedge rst)
827 
        if (rst)
828 
                q <= reset_value;
829 
        else
830 
                if (ce)
831 
                        q <= d;
832 
 
833 
endmodule
834 40 unneback 
`endif
835 6 unneback 
 
836 40 unneback 
`ifdef DFF_CE_CLEAR
837 
`define MODULE dff_ce_clear
838 
module `BASE`MODULE ( d, ce, clear, q, clk, rst);
839 
`undef MODULE
840 8 unneback 
 
841 
        parameter width = 1;
842 
        parameter reset_value = 0;
843 
 
844 
        input [width-1:0] d;
845 10 unneback 
        input ce, clear, clk, rst;
846 8 unneback 
        output reg [width-1:0] q;
847 
 
848 
        always @ (posedge clk or posedge rst)
849 
        if (rst)
850 
            q <= reset_value;
851 
        else
852 
            if (ce)
853 
                if (clear)
854 
                    q <= {width{1'b0}};
855 
                else
856 
                    q <= d;
857 
 
858 
endmodule
859 40 unneback 
`endif
860 8 unneback 
 
861 40 unneback 
`ifdef DF_CE_SET
862 
`define MODULE dff_ce_set
863 
module `BASE`MODULE ( d, ce, set, q, clk, rst);
864 
`undef MODULE
865 24 unneback 
 
866 
        parameter width = 1;
867 
        parameter reset_value = 0;
868 
 
869 
        input [width-1:0] d;
870 
        input ce, set, clk, rst;
871 
        output reg [width-1:0] q;
872 
 
873 
        always @ (posedge clk or posedge rst)
874 
        if (rst)
875 
            q <= reset_value;
876 
        else
877 
            if (ce)
878 
                if (set)
879 
                    q <= {width{1'b1}};
880 
                else
881 
                    q <= d;
882 
 
883 
endmodule
884 40 unneback 
`endif
885 24 unneback 
 
886 40 unneback 
`ifdef SPR
887 
`define MODULE spr
888 
module `BASE`MODULE ( sp, r, q, clk, rst);
889 
`undef MODULE
890 
 
891 64 unneback 
        //parameter width = 1;
892 
        parameter reset_value = 1'b0;
893 29 unneback 
 
894 
        input sp, r;
895 
        output reg q;
896 
        input clk, rst;
897 
 
898 
        always @ (posedge clk or posedge rst)
899 
        if (rst)
900 
            q <= reset_value;
901 
        else
902 
            if (sp)
903 
                q <= 1'b1;
904 
            else if (r)
905 
                q <= 1'b0;
906 
 
907 
endmodule
908 40 unneback 
`endif
909 29 unneback 
 
910 40 unneback 
`ifdef SRP
911 
`define MODULE srp
912 
module `BASE`MODULE ( s, rp, q, clk, rst);
913 
`undef MODULE
914 
 
915 29 unneback 
        parameter width = 1;
916 
        parameter reset_value = 0;
917 
 
918 
        input s, rp;
919 
        output reg q;
920 
        input clk, rst;
921 
 
922 
        always @ (posedge clk or posedge rst)
923 
        if (rst)
924 
            q <= reset_value;
925 
        else
926 
            if (rp)
927 
                q <= 1'b0;
928 
            else if (s)
929 
                q <= 1'b1;
930 
 
931 
endmodule
932 40 unneback 
`endif
933 29 unneback 
 
934 40 unneback 
`ifdef ALTERA
935 29 unneback 
 
936 40 unneback 
`ifdef DFF_SR
937 6 unneback 
// megafunction wizard: %LPM_FF%
938 
// GENERATION: STANDARD
939 
// VERSION: WM1.0
940 
// MODULE: lpm_ff
941 
 
942 
// ============================================================
943 
// File Name: dff_sr.v
944 
// Megafunction Name(s):
945 
//                      lpm_ff
946 
//
947 
// Simulation Library Files(s):
948 
//                      lpm
949 
// ============================================================
950 
// ************************************************************
951 
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
952 
//
953 
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
954 
// ************************************************************
955 
 
956 
 
957 
//Copyright (C) 1991-2010 Altera Corporation
958 
//Your use of Altera Corporation's design tools, logic functions
959 
//and other software and tools, and its AMPP partner logic
960 
//functions, and any output files from any of the foregoing
961 
//(including device programming or simulation files), and any
962 
//associated documentation or information are expressly subject
963 
//to the terms and conditions of the Altera Program License
964 
//Subscription Agreement, Altera MegaCore Function License
965 
//Agreement, or other applicable license agreement, including,
966 
//without limitation, that your use is for the sole purpose of
967 
//programming logic devices manufactured by Altera and sold by
968 
//Altera or its authorized distributors.  Please refer to the
969 
//applicable agreement for further details.
970 
 
971 
 
972 
// synopsys translate_off
973 
`timescale 1 ps / 1 ps
974 
// synopsys translate_on
975 40 unneback 
`define MODULE dff_sr
976 
module `BASE`MODULE (
977 
`undef MODULE
978 
 
979 6 unneback 
        aclr,
980 
        aset,
981 
        clock,
982 
        data,
983 
        q);
984 
 
985 
        input     aclr;
986 
        input     aset;
987 
        input     clock;
988 
        input     data;
989 
        output    q;
990 
 
991 
        wire [0:0] sub_wire0;
992 
        wire [0:0] sub_wire1 = sub_wire0[0:0];
993 
        wire  q = sub_wire1;
994 
        wire  sub_wire2 = data;
995 
        wire  sub_wire3 = sub_wire2;
996 
 
997 
        lpm_ff  lpm_ff_component (
998 
                                .aclr (aclr),
999 
                                .clock (clock),
1000 
                                .data (sub_wire3),
1001 
                                .aset (aset),
1002 
                                .q (sub_wire0)
1003 
                                // synopsys translate_off
1004 
                                ,
1005 
                                .aload (),
1006 
                                .enable (),
1007 
                                .sclr (),
1008 
                                .sload (),
1009 
                                .sset ()
1010 
                                // synopsys translate_on
1011 
                                );
1012 
        defparam
1013 
                lpm_ff_component.lpm_fftype = "DFF",
1014 
                lpm_ff_component.lpm_type = "LPM_FF",
1015 
                lpm_ff_component.lpm_width = 1;
1016 
 
1017 
 
1018 
endmodule
1019 
 
1020 
// ============================================================
1021 
// CNX file retrieval info
1022 
// ============================================================
1023 
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
1024 
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
1025 
// Retrieval info: PRIVATE: ASET NUMERIC "1"
1026 
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
1027 
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
1028 
// Retrieval info: PRIVATE: DFF NUMERIC "1"
1029 
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
1030 
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
1031 
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
1032 
// Retrieval info: PRIVATE: SSET NUMERIC "0"
1033 
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
1034 
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
1035 
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
1036 
// Retrieval info: PRIVATE: nBit NUMERIC "1"
1037 
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
1038 
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
1039 
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
1040 
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
1041 
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
1042 
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
1043 
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
1044 
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
1045 
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
1046 
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
1047 
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
1048 
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
1049 
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
1050 
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
1051 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
1052 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
1053 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
1054 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
1055 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
1056 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
1057 
// Retrieval info: LIB_FILE: lpm
1058 40 unneback 
`endif
1059 6 unneback 
 
1060 
`else
1061 
 
1062 40 unneback 
`ifdef DFF_SR
1063 
`define MODULE dff_sr
1064 
module `BASE`MODULE ( aclr, aset, clock, data, q);
1065 
`undef MODULE
1066 6 unneback 
 
1067 
    input         aclr;
1068 
    input         aset;
1069 
    input         clock;
1070 
    input         data;
1071 
    output reg    q;
1072 
 
1073 
   always @ (posedge clock or posedge aclr or posedge aset)
1074 
     if (aclr)
1075 
       q <= 1'b0;
1076 
     else if (aset)
1077 
       q <= 1'b1;
1078 
     else
1079 
       q <= data;
1080 
 
1081 
endmodule
1082 40 unneback 
`endif
1083 6 unneback 
 
1084 
`endif
1085 
 
1086 
// LATCH
1087 
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
1088 
`ifdef ALTERA
1089 40 unneback 
 
1090 
`ifdef LATCH
1091 
`define MODULE latch
1092 
module `BASE`MODULE ( d, le, q, clk);
1093 
`undef MODULE
1094 6 unneback 
input d, le;
1095 
output q;
1096 
input clk;
1097 
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
1098 
endmodule
1099 40 unneback 
`endif
1100 
 
1101 6 unneback 
`else
1102 40 unneback 
 
1103 
`ifdef LATCH
1104 
`define MODULE latch
1105 
module `BASE`MODULE ( d, le, q, clk);
1106 
`undef MODULE
1107 6 unneback 
input d, le;
1108 48 unneback 
input clk;
1109 
always @ (le or d)
1110 60 unneback 
if (le)
1111 48 unneback 
    d <= q;
1112 6 unneback 
endmodule
1113 15 unneback 
`endif
1114 
 
1115 40 unneback 
`endif
1116 
 
1117 
`ifdef SHREG
1118 
`define MODULE shreg
1119 
module `BASE`MODULE ( d, q, clk, rst);
1120 
`undef MODULE
1121 
 
1122 17 unneback 
parameter depth = 10;
1123 
input d;
1124 
output q;
1125 
input clk, rst;
1126 
 
1127 
reg [1:depth] dffs;
1128 
 
1129 
always @ (posedge clk or posedge rst)
1130 
if (rst)
1131 
    dffs <= {depth{1'b0}};
1132 
else
1133 
    dffs <= {d,dffs[1:depth-1]};
1134 
assign q = dffs[depth];
1135 
endmodule
1136 40 unneback 
`endif
1137 17 unneback 
 
1138 40 unneback 
`ifdef SHREG_CE
1139 
`define MODULE shreg_ce
1140 
module `BASE`MODULE ( d, ce, q, clk, rst);
1141 
`undef MODULE
1142 17 unneback 
parameter depth = 10;
1143 
input d, ce;
1144 
output q;
1145 
input clk, rst;
1146 
 
1147 
reg [1:depth] dffs;
1148 
 
1149 
always @ (posedge clk or posedge rst)
1150 
if (rst)
1151 
    dffs <= {depth{1'b0}};
1152 
else
1153 
    if (ce)
1154 
        dffs <= {d,dffs[1:depth-1]};
1155 
assign q = dffs[depth];
1156 
endmodule
1157 40 unneback 
`endif
1158 17 unneback 
 
1159 40 unneback 
`ifdef DELAY
1160 
`define MODULE delay
1161 
module `BASE`MODULE ( d, q, clk, rst);
1162 
`undef MODULE
1163 15 unneback 
parameter depth = 10;
1164 
input d;
1165 
output q;
1166 
input clk, rst;
1167 
 
1168 
reg [1:depth] dffs;
1169 
 
1170 
always @ (posedge clk or posedge rst)
1171 
if (rst)
1172 
    dffs <= {depth{1'b0}};
1173 
else
1174 
    dffs <= {d,dffs[1:depth-1]};
1175 
assign q = dffs[depth];
1176 17 unneback 
endmodule
1177 40 unneback 
`endif
1178 17 unneback 
 
1179 40 unneback 
`ifdef DELAY_EMPTYFLAG
1180 
`define MODULE delay_emptyflag
1181 41 unneback 
module `BASE`MODULE ( d, q, emptyflag, clk, rst);
1182 40 unneback 
`undef MODULE
1183 17 unneback 
parameter depth = 10;
1184 
input d;
1185 
output q, emptyflag;
1186 
input clk, rst;
1187 
 
1188 
reg [1:depth] dffs;
1189 
 
1190 
always @ (posedge clk or posedge rst)
1191 
if (rst)
1192 
    dffs <= {depth{1'b0}};
1193 
else
1194 
    dffs <= {d,dffs[1:depth-1]};
1195 
assign q = dffs[depth];
1196 
assign emptyflag = !(|dffs);
1197 
endmodule
1198 40 unneback 
`endif
1199 75 unneback 
 
1200 94 unneback 
`ifdef PULSE2TOGGLE
1201 98 unneback 
`define MODULE pulse2toggle
1202 
module `BASE`MODULE ( pl, q, clk, rst);
1203 75 unneback 
`undef MODULE
1204 94 unneback 
input pl;
1205 98 unneback 
output reg q;
1206 94 unneback 
input clk, rst;
1207 
always @ (posedge clk or posedge rst)
1208 75 unneback 
if (rst)
1209 94 unneback 
    q <= 1'b0;
1210 75 unneback 
else
1211 94 unneback 
    q <= pl ^ q;
1212 
endmodule
1213 
`endif
1214 75 unneback 
 
1215 94 unneback 
`ifdef TOGGLE2PULSE
1216 98 unneback 
`define MODULE toggle2pulse
1217 94 unneback 
module `BASE`MODULE (d, pl, clk, rst);
1218 97 unneback 
`undef MODULE
1219 94 unneback 
input d;
1220 
output pl;
1221 
input clk, rst;
1222 
reg dff;
1223 
always @ (posedge clk or posedge rst)
1224 
if (rst)
1225 
    dff <= 1'b0;
1226 75 unneback 
else
1227 94 unneback 
    dff <= d;
1228 98 unneback 
assign pl = d ^ dff;
1229 94 unneback 
endmodule
1230 
`endif
1231 75 unneback 
 
1232 94 unneback 
`ifdef SYNCHRONIZER
1233 
`define MODULE synchronizer
1234 
module `BASE`MODULE (d, q, clk, rst);
1235 
`undef MODULE
1236 
input d;
1237 
output reg q;
1238 
output clk, rst;
1239 
reg dff;
1240 
always @ (posedge clk or posedge rst)
1241 
if (rst)
1242 100 unneback 
    {q,dff} <= 2'b00;
1243 75 unneback 
else
1244 100 unneback 
    {q,dff} <= {dff,d};
1245 94 unneback 
endmodule
1246 
`endif
1247 75 unneback 
 
1248 94 unneback 
`ifdef CDC
1249 
`define MODULE cdc
1250 97 unneback 
module `BASE`MODULE ( start_pl, take_it_pl, take_it_grant_pl, got_it_pl, clk_src, rst_src, clk_dst, rst_dst);
1251 94 unneback 
`undef MODULE
1252 
input start_pl;
1253 
output take_it_pl;
1254 
input take_it_grant_pl; // note: connect to take_it_pl to generate automatic ack
1255 
output got_it_pl;
1256 
input clk_src, rst_src;
1257 
input clk_dst, rst_dst;
1258 
wire take_it_tg, take_it_tg_sync;
1259 
wire got_it_tg, got_it_tg_sync;
1260 
// src -> dst
1261 
`define MODULE pulse2toggle
1262 
`BASE`MODULE p2t0 (
1263 
`undef MODULE
1264 
    .pl(start_pl),
1265 
    .q(take_it_tg),
1266 
    .clk(clk_src),
1267 
    .rst(rst_src));
1268 75 unneback 
 
1269 94 unneback 
`define MODULE synchronizer
1270 
`BASE`MODULE sync0 (
1271 
`undef MODULE
1272 
    .d(take_it_tg),
1273 
    .q(take_it_tg_sync),
1274 
    .clk(clk_dst),
1275 
    .rst(rst_dst));
1276 
 
1277 
`define MODULE toggle2pulse
1278 
`BASE`MODULE t2p0 (
1279 
`undef MODULE
1280 100 unneback 
    .d(take_it_tg_sync),
1281 94 unneback 
    .pl(take_it_pl),
1282 
    .clk(clk_dst),
1283 
    .rst(rst_dst));
1284 
 
1285 
// dst -> src
1286 
`define MODULE pulse2toggle
1287 98 unneback 
`BASE`MODULE p2t1 (
1288 94 unneback 
`undef MODULE
1289 
    .pl(take_it_grant_pl),
1290 
    .q(got_it_tg),
1291 
    .clk(clk_dst),
1292 
    .rst(rst_dst));
1293 
 
1294 
`define MODULE synchronizer
1295 
`BASE`MODULE sync1 (
1296 
`undef MODULE
1297 
    .d(got_it_tg),
1298 
    .q(got_it_tg_sync),
1299 
    .clk(clk_src),
1300 
    .rst(rst_src));
1301 
 
1302 
`define MODULE toggle2pulse
1303 
`BASE`MODULE t2p1 (
1304 
`undef MODULE
1305 100 unneback 
    .d(got_it_tg_sync),
1306 94 unneback 
    .pl(got_it_pl),
1307 
    .clk(clk_src),
1308 
    .rst(rst_src));
1309 
 
1310 75 unneback 
endmodule
1311 
`endif
1312 17 unneback 
//////////////////////////////////////////////////////////////////////
1313 6 unneback 
////                                                              ////
1314 18 unneback 
////  Logic functions                                             ////
1315 
////                                                              ////
1316 
////  Description                                                 ////
1317 
////  Logic functions such as multiplexers                        ////
1318 
////                                                              ////
1319 
////                                                              ////
1320 
////  To Do:                                                      ////
1321 
////   -                                                          ////
1322 
////                                                              ////
1323 
////  Author(s):                                                  ////
1324 
////      - Michael Unneback, unneback@opencores.org              ////
1325 
////        ORSoC AB                                              ////
1326 
////                                                              ////
1327 
//////////////////////////////////////////////////////////////////////
1328 
////                                                              ////
1329 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1330 
////                                                              ////
1331 
//// This source file may be used and distributed without         ////
1332 
//// restriction provided that this copyright statement is not    ////
1333 
//// removed from the file and that any derivative work contains  ////
1334 
//// the original copyright notice and the associated disclaimer. ////
1335 
////                                                              ////
1336 
//// This source file is free software; you can redistribute it   ////
1337 
//// and/or modify it under the terms of the GNU Lesser General   ////
1338 
//// Public License as published by the Free Software Foundation; ////
1339 
//// either version 2.1 of the License, or (at your option) any   ////
1340 
//// later version.                                               ////
1341 
////                                                              ////
1342 
//// This source is distributed in the hope that it will be       ////
1343 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1344 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1345 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1346 
//// details.                                                     ////
1347 
////                                                              ////
1348 
//// You should have received a copy of the GNU Lesser General    ////
1349 
//// Public License along with this source; if not, download it   ////
1350 
//// from http://www.opencores.org/lgpl.shtml                     ////
1351 
////                                                              ////
1352 
//////////////////////////////////////////////////////////////////////
1353 40 unneback 
`ifdef MUX_ANDOR
1354 
`define MODULE mux_andor
1355 
module `BASE`MODULE ( a, sel, dout);
1356 
`undef MODULE
1357 36 unneback 
 
1358 
parameter width = 32;
1359 
parameter nr_of_ports = 4;
1360 
 
1361 
input [nr_of_ports*width-1:0] a;
1362 
input [nr_of_ports-1:0] sel;
1363 
output reg [width-1:0] dout;
1364 
 
1365 38 unneback 
integer i,j;
1366 
 
1367 36 unneback 
always @ (a, sel)
1368 
begin
1369 
    dout = a[width-1:0] & {width{sel[0]}};
1370 42 unneback 
    for (i=1;i<nr_of_ports;i=i+1)
1371 
        for (j=0;j<width;j=j+1)
1372 
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
1373 36 unneback 
end
1374 
 
1375 
endmodule
1376 40 unneback 
`endif
1377 36 unneback 
 
1378 40 unneback 
`ifdef MUX2_ANDOR
1379 
`define MODULE mux2_andor
1380 
module `BASE`MODULE ( a1, a0, sel, dout);
1381 
`undef MODULE
1382 18 unneback 
 
1383 34 unneback 
parameter width = 32;
1384 35 unneback 
localparam nr_of_ports = 2;
1385 34 unneback 
input [width-1:0] a1, a0;
1386 
input [nr_of_ports-1:0] sel;
1387 
output [width-1:0] dout;
1388 
 
1389 40 unneback 
`define MODULE mux_andor
1390 
`BASE`MODULE
1391 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1392 36 unneback 
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
1393 40 unneback 
`undef MODULE
1394 
 
1395 34 unneback 
endmodule
1396 40 unneback 
`endif
1397 34 unneback 
 
1398 40 unneback 
`ifdef MUX3_ANDOR
1399 
`define MODULE mux3_andor
1400 
module `BASE`MODULE ( a2, a1, a0, sel, dout);
1401 
`undef MODULE
1402 34 unneback 
 
1403 
parameter width = 32;
1404 35 unneback 
localparam nr_of_ports = 3;
1405 34 unneback 
input [width-1:0] a2, a1, a0;
1406 
input [nr_of_ports-1:0] sel;
1407 
output [width-1:0] dout;
1408 
 
1409 40 unneback 
`define MODULE mux_andor
1410 
`BASE`MODULE
1411 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1412 36 unneback 
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
1413 40 unneback 
`undef MODULE
1414 34 unneback 
endmodule
1415 40 unneback 
`endif
1416 34 unneback 
 
1417 40 unneback 
`ifdef MUX4_ANDOR
1418 
`define MODULE mux4_andor
1419 
module `BASE`MODULE ( a3, a2, a1, a0, sel, dout);
1420 
`undef MODULE
1421 18 unneback 
 
1422 
parameter width = 32;
1423 35 unneback 
localparam nr_of_ports = 4;
1424 18 unneback 
input [width-1:0] a3, a2, a1, a0;
1425 
input [nr_of_ports-1:0] sel;
1426 22 unneback 
output [width-1:0] dout;
1427 18 unneback 
 
1428 40 unneback 
`define MODULE mux_andor
1429 
`BASE`MODULE
1430 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1431 36 unneback 
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
1432 40 unneback 
`undef MODULE
1433 18 unneback 
 
1434 
endmodule
1435 40 unneback 
`endif
1436 18 unneback 
 
1437 40 unneback 
`ifdef MUX5_ANDOR
1438 
`define MODULE mux5_andor
1439 
module `BASE`MODULE ( a4, a3, a2, a1, a0, sel, dout);
1440 
`undef MODULE
1441 18 unneback 
 
1442 
parameter width = 32;
1443 35 unneback 
localparam nr_of_ports = 5;
1444 18 unneback 
input [width-1:0] a4, a3, a2, a1, a0;
1445 
input [nr_of_ports-1:0] sel;
1446 22 unneback 
output [width-1:0] dout;
1447 18 unneback 
 
1448 40 unneback 
`define MODULE mux_andor
1449 
`BASE`MODULE
1450 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1451 36 unneback 
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1452 40 unneback 
`undef MODULE
1453 18 unneback 
 
1454 
endmodule
1455 40 unneback 
`endif
1456 18 unneback 
 
1457 40 unneback 
`ifdef MUX6_ANDOR
1458 
`define MODULE mux6_andor
1459 
module `BASE`MODULE ( a5, a4, a3, a2, a1, a0, sel, dout);
1460 
`undef MODULE
1461 18 unneback 
 
1462 
parameter width = 32;
1463 35 unneback 
localparam nr_of_ports = 6;
1464 18 unneback 
input [width-1:0] a5, a4, a3, a2, a1, a0;
1465 
input [nr_of_ports-1:0] sel;
1466 22 unneback 
output [width-1:0] dout;
1467 18 unneback 
 
1468 40 unneback 
`define MODULE mux_andor
1469 
`BASE`MODULE
1470 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1471 36 unneback 
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1472 40 unneback 
`undef MODULE
1473 18 unneback 
 
1474 
endmodule
1475 40 unneback 
`endif
1476 43 unneback 
 
1477 
`ifdef PARITY
1478 
 
1479 
`define MODULE parity_generate
1480 
module `BASE`MODULE (data, parity);
1481 
`undef MODULE
1482 
parameter word_size = 32;
1483 
parameter chunk_size = 8;
1484 
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1485 
input [word_size-1:0] data;
1486 
output reg [word_size/chunk_size-1:0] parity;
1487 
integer i,j;
1488 
always @ (data)
1489 
for (i=0;i<word_size/chunk_size;i=i+1) begin
1490 
    parity[i] = parity_type;
1491 
    for (j=0;j<chunk_size;j=j+1) begin
1492 46 unneback 
        parity[i] = data[i*chunk_size+j] ^ parity[i];
1493 43 unneback 
    end
1494 
end
1495 
endmodule
1496 
 
1497 
`define MODULE parity_check
1498 
module `BASE`MODULE( data, parity, parity_error);
1499 
`undef MODULE
1500 
parameter word_size = 32;
1501 
parameter chunk_size = 8;
1502 
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1503 
input [word_size-1:0] data;
1504 
input [word_size/chunk_size-1:0] parity;
1505 
output parity_error;
1506 44 unneback 
reg [word_size/chunk_size-1:0] error_flag;
1507 43 unneback 
integer i,j;
1508 
always @ (data or parity)
1509 
for (i=0;i<word_size/chunk_size;i=i+1) begin
1510 
    error_flag[i] = parity[i] ^ parity_type;
1511 
    for (j=0;j<chunk_size;j=j+1) begin
1512 46 unneback 
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
1513 43 unneback 
    end
1514 
end
1515 
assign parity_error = |error_flag;
1516 
endmodule
1517 
 
1518 44 unneback 
`endif//////////////////////////////////////////////////////////////////////
1519 
////                                                              ////
1520 
////  IO functions                                                ////
1521 
////                                                              ////
1522 
////  Description                                                 ////
1523 
////  IO functions such as IOB flip-flops                         ////
1524 
////                                                              ////
1525 
////                                                              ////
1526 
////  To Do:                                                      ////
1527 
////   -                                                          ////
1528 
////                                                              ////
1529 
////  Author(s):                                                  ////
1530 
////      - Michael Unneback, unneback@opencores.org              ////
1531 
////        ORSoC AB                                              ////
1532 
////                                                              ////
1533 18 unneback 
//////////////////////////////////////////////////////////////////////
1534 
////                                                              ////
1535 44 unneback 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1536 
////                                                              ////
1537 
//// This source file may be used and distributed without         ////
1538 
//// restriction provided that this copyright statement is not    ////
1539 
//// removed from the file and that any derivative work contains  ////
1540 
//// the original copyright notice and the associated disclaimer. ////
1541 
////                                                              ////
1542 
//// This source file is free software; you can redistribute it   ////
1543 
//// and/or modify it under the terms of the GNU Lesser General   ////
1544 
//// Public License as published by the Free Software Foundation; ////
1545 
//// either version 2.1 of the License, or (at your option) any   ////
1546 
//// later version.                                               ////
1547 
////                                                              ////
1548 
//// This source is distributed in the hope that it will be       ////
1549 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1550 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1551 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1552 
//// details.                                                     ////
1553 
////                                                              ////
1554 
//// You should have received a copy of the GNU Lesser General    ////
1555 
//// Public License along with this source; if not, download it   ////
1556 
//// from http://www.opencores.org/lgpl.shtml                     ////
1557 
////                                                              ////
1558 
//////////////////////////////////////////////////////////////////////
1559 45 unneback 
`timescale 1ns/1ns
1560 44 unneback 
`ifdef O_DFF
1561 
`define MODULE o_dff
1562 
module `BASE`MODULE (d_i, o_pad, clk, rst);
1563 
`undef MODULE
1564 
parameter width = 1;
1565 45 unneback 
parameter reset_value = {width{1'b0}};
1566 
input  [width-1:0]  d_i;
1567 44 unneback 
output [width-1:0] o_pad;
1568 
input clk, rst;
1569 
wire [width-1:0] d_i_int `SYN_KEEP;
1570 45 unneback 
reg  [width-1:0] o_pad_int;
1571 44 unneback 
assign d_i_int = d_i;
1572 
genvar i;
1573 45 unneback 
generate
1574 44 unneback 
for (i=0;i<width;i=i+1) begin
1575 
    always @ (posedge clk or posedge rst)
1576 
    if (rst)
1577 45 unneback 
        o_pad_int[i] <= reset_value[i];
1578 44 unneback 
    else
1579 45 unneback 
        o_pad_int[i] <= d_i_int[i];
1580 
    assign #1 o_pad[i] = o_pad_int[i];
1581 44 unneback 
end
1582 
endgenerate
1583 
endmodule
1584 
`endif
1585 
 
1586 45 unneback 
`timescale 1ns/1ns
1587 44 unneback 
`ifdef IO_DFF_OE
1588 
`define MODULE io_dff_oe
1589 
module `BASE`MODULE ( d_i, d_o, oe, io_pad, clk, rst);
1590 
`undef MODULE
1591 
parameter width = 1;
1592 
input  [width-1:0] d_o;
1593 
output reg [width-1:0] d_i;
1594 
input oe;
1595 
inout [width-1:0] io_pad;
1596 
input clk, rst;
1597 
wire [width-1:0] oe_d `SYN_KEEP;
1598 
reg [width-1:0] oe_q;
1599 
reg [width-1:0] d_o_q;
1600 
assign oe_d = {width{oe}};
1601 
genvar i;
1602 
generate
1603 
for (i=0;i<width;i=i+1) begin
1604 
    always @ (posedge clk or posedge rst)
1605 
    if (rst)
1606 
        oe_q[i] <= 1'b0;
1607 
    else
1608 
        oe_q[i] <= oe_d[i];
1609 
    always @ (posedge clk or posedge rst)
1610 
    if (rst)
1611 
        d_o_q[i] <= 1'b0;
1612 
    else
1613 
        d_o_q[i] <= d_o[i];
1614 
    always @ (posedge clk or posedge rst)
1615 
    if (rst)
1616 
        d_i[i] <= 1'b0;
1617 
    else
1618 
        d_i[i] <= io_pad[i];
1619 45 unneback 
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
1620 44 unneback 
end
1621 
endgenerate
1622 
endmodule
1623 
`endif
1624 
`ifdef CNT_BIN
1625 
//////////////////////////////////////////////////////////////////////
1626 
////                                                              ////
1627 6 unneback 
////  Versatile counter                                           ////
1628 
////                                                              ////
1629 
////  Description                                                 ////
1630 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1631 
////  counter                                                     ////
1632 
////                                                              ////
1633 
////  To Do:                                                      ////
1634 
////   - add LFSR with more taps                                  ////
1635 
////                                                              ////
1636 
////  Author(s):                                                  ////
1637 
////      - Michael Unneback, unneback@opencores.org              ////
1638 
////        ORSoC AB                                              ////
1639 
////                                                              ////
1640 
//////////////////////////////////////////////////////////////////////
1641 
////                                                              ////
1642 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1643 
////                                                              ////
1644 
//// This source file may be used and distributed without         ////
1645 
//// restriction provided that this copyright statement is not    ////
1646 
//// removed from the file and that any derivative work contains  ////
1647 
//// the original copyright notice and the associated disclaimer. ////
1648 
////                                                              ////
1649 
//// This source file is free software; you can redistribute it   ////
1650 
//// and/or modify it under the terms of the GNU Lesser General   ////
1651 
//// Public License as published by the Free Software Foundation; ////
1652 
//// either version 2.1 of the License, or (at your option) any   ////
1653 
//// later version.                                               ////
1654 
////                                                              ////
1655 
//// This source is distributed in the hope that it will be       ////
1656 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1657 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1658 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1659 
//// details.                                                     ////
1660 
////                                                              ////
1661 
//// You should have received a copy of the GNU Lesser General    ////
1662 
//// Public License along with this source; if not, download it   ////
1663 
//// from http://www.opencores.org/lgpl.shtml                     ////
1664 
////                                                              ////
1665 
//////////////////////////////////////////////////////////////////////
1666 
 
1667 
// binary counter
1668 22 unneback 
 
1669 40 unneback 
`define MODULE cnt_bin
1670 
module `BASE`MODULE (
1671 
`undef MODULE
1672 
 q, rst, clk);
1673 
 
1674 22 unneback 
   parameter length = 4;
1675 
   output [length:1] q;
1676 
   input rst;
1677 
   input clk;
1678 
 
1679 
   parameter clear_value = 0;
1680 
   parameter set_value = 1;
1681 
   parameter wrap_value = 0;
1682 
   parameter level1_value = 15;
1683 
 
1684 
   reg  [length:1] qi;
1685 
   wire [length:1] q_next;
1686 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1687 
 
1688 
   always @ (posedge clk or posedge rst)
1689 
     if (rst)
1690 
       qi <= {length{1'b0}};
1691 
     else
1692 
       qi <= q_next;
1693 
 
1694 
   assign q = qi;
1695 
 
1696 
endmodule
1697 40 unneback 
`endif
1698 
`ifdef CNT_BIN_CLEAR
1699 22 unneback 
//////////////////////////////////////////////////////////////////////
1700 
////                                                              ////
1701 
////  Versatile counter                                           ////
1702 
////                                                              ////
1703 
////  Description                                                 ////
1704 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1705 
////  counter                                                     ////
1706 
////                                                              ////
1707 
////  To Do:                                                      ////
1708 
////   - add LFSR with more taps                                  ////
1709 
////                                                              ////
1710 
////  Author(s):                                                  ////
1711 
////      - Michael Unneback, unneback@opencores.org              ////
1712 
////        ORSoC AB                                              ////
1713 
////                                                              ////
1714 
//////////////////////////////////////////////////////////////////////
1715 
////                                                              ////
1716 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1717 
////                                                              ////
1718 
//// This source file may be used and distributed without         ////
1719 
//// restriction provided that this copyright statement is not    ////
1720 
//// removed from the file and that any derivative work contains  ////
1721 
//// the original copyright notice and the associated disclaimer. ////
1722 
////                                                              ////
1723 
//// This source file is free software; you can redistribute it   ////
1724 
//// and/or modify it under the terms of the GNU Lesser General   ////
1725 
//// Public License as published by the Free Software Foundation; ////
1726 
//// either version 2.1 of the License, or (at your option) any   ////
1727 
//// later version.                                               ////
1728 
////                                                              ////
1729 
//// This source is distributed in the hope that it will be       ////
1730 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1731 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1732 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1733 
//// details.                                                     ////
1734 
////                                                              ////
1735 
//// You should have received a copy of the GNU Lesser General    ////
1736 
//// Public License along with this source; if not, download it   ////
1737 
//// from http://www.opencores.org/lgpl.shtml                     ////
1738 
////                                                              ////
1739 
//////////////////////////////////////////////////////////////////////
1740 
 
1741 
// binary counter
1742 
 
1743 40 unneback 
`define MODULE cnt_bin_clear
1744 
module `BASE`MODULE (
1745 
`undef MODULE
1746 
 clear, q, rst, clk);
1747 
 
1748 22 unneback 
   parameter length = 4;
1749 
   input clear;
1750 
   output [length:1] q;
1751 
   input rst;
1752 
   input clk;
1753 
 
1754 
   parameter clear_value = 0;
1755 
   parameter set_value = 1;
1756 
   parameter wrap_value = 0;
1757 
   parameter level1_value = 15;
1758 
 
1759 
   reg  [length:1] qi;
1760 
   wire [length:1] q_next;
1761 
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1762 
 
1763 
   always @ (posedge clk or posedge rst)
1764 
     if (rst)
1765 
       qi <= {length{1'b0}};
1766 
     else
1767 
       qi <= q_next;
1768 
 
1769 
   assign q = qi;
1770 
 
1771 
endmodule
1772 40 unneback 
`endif
1773 
`ifdef CNT_BIN_CE
1774 22 unneback 
//////////////////////////////////////////////////////////////////////
1775 
////                                                              ////
1776 
////  Versatile counter                                           ////
1777 
////                                                              ////
1778 
////  Description                                                 ////
1779 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1780 
////  counter                                                     ////
1781 
////                                                              ////
1782 
////  To Do:                                                      ////
1783 
////   - add LFSR with more taps                                  ////
1784 
////                                                              ////
1785 
////  Author(s):                                                  ////
1786 
////      - Michael Unneback, unneback@opencores.org              ////
1787 
////        ORSoC AB                                              ////
1788 
////                                                              ////
1789 
//////////////////////////////////////////////////////////////////////
1790 
////                                                              ////
1791 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1792 
////                                                              ////
1793 
//// This source file may be used and distributed without         ////
1794 
//// restriction provided that this copyright statement is not    ////
1795 
//// removed from the file and that any derivative work contains  ////
1796 
//// the original copyright notice and the associated disclaimer. ////
1797 
////                                                              ////
1798 
//// This source file is free software; you can redistribute it   ////
1799 
//// and/or modify it under the terms of the GNU Lesser General   ////
1800 
//// Public License as published by the Free Software Foundation; ////
1801 
//// either version 2.1 of the License, or (at your option) any   ////
1802 
//// later version.                                               ////
1803 
////                                                              ////
1804 
//// This source is distributed in the hope that it will be       ////
1805 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1806 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1807 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1808 
//// details.                                                     ////
1809 
////                                                              ////
1810 
//// You should have received a copy of the GNU Lesser General    ////
1811 
//// Public License along with this source; if not, download it   ////
1812 
//// from http://www.opencores.org/lgpl.shtml                     ////
1813 
////                                                              ////
1814 
//////////////////////////////////////////////////////////////////////
1815 
 
1816 
// binary counter
1817 6 unneback 
 
1818 40 unneback 
`define MODULE cnt_bin_ce
1819 
module `BASE`MODULE (
1820 
`undef MODULE
1821 
 cke, q, rst, clk);
1822 
 
1823 6 unneback 
   parameter length = 4;
1824 
   input cke;
1825 
   output [length:1] q;
1826 
   input rst;
1827 
   input clk;
1828 
 
1829 
   parameter clear_value = 0;
1830 
   parameter set_value = 1;
1831 
   parameter wrap_value = 0;
1832 
   parameter level1_value = 15;
1833 
 
1834 
   reg  [length:1] qi;
1835 
   wire [length:1] q_next;
1836 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1837 
 
1838 
   always @ (posedge clk or posedge rst)
1839 
     if (rst)
1840 
       qi <= {length{1'b0}};
1841 
     else
1842 
     if (cke)
1843 
       qi <= q_next;
1844 
 
1845 
   assign q = qi;
1846 
 
1847 
endmodule
1848 40 unneback 
`endif
1849 
`ifdef CNT_BIN_CE_CLEAR
1850 6 unneback 
//////////////////////////////////////////////////////////////////////
1851 
////                                                              ////
1852 
////  Versatile counter                                           ////
1853 
////                                                              ////
1854 
////  Description                                                 ////
1855 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1856 
////  counter                                                     ////
1857 
////                                                              ////
1858 
////  To Do:                                                      ////
1859 
////   - add LFSR with more taps                                  ////
1860 
////                                                              ////
1861 
////  Author(s):                                                  ////
1862 
////      - Michael Unneback, unneback@opencores.org              ////
1863 
////        ORSoC AB                                              ////
1864 
////                                                              ////
1865 
//////////////////////////////////////////////////////////////////////
1866 
////                                                              ////
1867 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1868 
////                                                              ////
1869 
//// This source file may be used and distributed without         ////
1870 
//// restriction provided that this copyright statement is not    ////
1871 
//// removed from the file and that any derivative work contains  ////
1872 
//// the original copyright notice and the associated disclaimer. ////
1873 
////                                                              ////
1874 
//// This source file is free software; you can redistribute it   ////
1875 
//// and/or modify it under the terms of the GNU Lesser General   ////
1876 
//// Public License as published by the Free Software Foundation; ////
1877 
//// either version 2.1 of the License, or (at your option) any   ////
1878 
//// later version.                                               ////
1879 
////                                                              ////
1880 
//// This source is distributed in the hope that it will be       ////
1881 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1882 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1883 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1884 
//// details.                                                     ////
1885 
////                                                              ////
1886 
//// You should have received a copy of the GNU Lesser General    ////
1887 
//// Public License along with this source; if not, download it   ////
1888 
//// from http://www.opencores.org/lgpl.shtml                     ////
1889 
////                                                              ////
1890 
//////////////////////////////////////////////////////////////////////
1891 
 
1892 
// binary counter
1893 
 
1894 40 unneback 
`define MODULE cnt_bin_ce_clear
1895 
module `BASE`MODULE (
1896 
`undef MODULE
1897 
 clear, cke, q, rst, clk);
1898 
 
1899 6 unneback 
   parameter length = 4;
1900 
   input clear;
1901 
   input cke;
1902 
   output [length:1] q;
1903 
   input rst;
1904 
   input clk;
1905 
 
1906 
   parameter clear_value = 0;
1907 
   parameter set_value = 1;
1908 
   parameter wrap_value = 0;
1909 
   parameter level1_value = 15;
1910 
 
1911 
   reg  [length:1] qi;
1912 
   wire [length:1] q_next;
1913 
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1914 
 
1915 
   always @ (posedge clk or posedge rst)
1916 
     if (rst)
1917 
       qi <= {length{1'b0}};
1918 
     else
1919 
     if (cke)
1920 
       qi <= q_next;
1921 
 
1922 
   assign q = qi;
1923 
 
1924 
endmodule
1925 40 unneback 
`endif
1926 
`ifdef CNT_BIN_CE_CLEAR_L1_L2
1927 6 unneback 
//////////////////////////////////////////////////////////////////////
1928 
////                                                              ////
1929 
////  Versatile counter                                           ////
1930 
////                                                              ////
1931 
////  Description                                                 ////
1932 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1933 
////  counter                                                     ////
1934 
////                                                              ////
1935 
////  To Do:                                                      ////
1936 
////   - add LFSR with more taps                                  ////
1937 
////                                                              ////
1938 
////  Author(s):                                                  ////
1939 
////      - Michael Unneback, unneback@opencores.org              ////
1940 
////        ORSoC AB                                              ////
1941 
////                                                              ////
1942 
//////////////////////////////////////////////////////////////////////
1943 
////                                                              ////
1944 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1945 
////                                                              ////
1946 
//// This source file may be used and distributed without         ////
1947 
//// restriction provided that this copyright statement is not    ////
1948 
//// removed from the file and that any derivative work contains  ////
1949 
//// the original copyright notice and the associated disclaimer. ////
1950 
////                                                              ////
1951 
//// This source file is free software; you can redistribute it   ////
1952 
//// and/or modify it under the terms of the GNU Lesser General   ////
1953 
//// Public License as published by the Free Software Foundation; ////
1954 
//// either version 2.1 of the License, or (at your option) any   ////
1955 
//// later version.                                               ////
1956 
////                                                              ////
1957 
//// This source is distributed in the hope that it will be       ////
1958 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1959 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1960 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1961 
//// details.                                                     ////
1962 
////                                                              ////
1963 
//// You should have received a copy of the GNU Lesser General    ////
1964 
//// Public License along with this source; if not, download it   ////
1965 
//// from http://www.opencores.org/lgpl.shtml                     ////
1966 
////                                                              ////
1967 
//////////////////////////////////////////////////////////////////////
1968 
 
1969 
// binary counter
1970 29 unneback 
 
1971 40 unneback 
`define MODULE cnt_bin_ce_clear_l1_l2
1972 
module `BASE`MODULE (
1973 
`undef MODULE
1974 
 clear, cke, q, level1, level2, rst, clk);
1975 
 
1976 29 unneback 
   parameter length = 4;
1977 
   input clear;
1978 
   input cke;
1979 
   output [length:1] q;
1980 
   output reg level1;
1981 
   output reg level2;
1982 
   input rst;
1983 
   input clk;
1984 
 
1985 
   parameter clear_value = 0;
1986 
   parameter set_value = 1;
1987 30 unneback 
   parameter wrap_value = 15;
1988 
   parameter level1_value = 8;
1989 
   parameter level2_value = 15;
1990 29 unneback 
 
1991 
   wire rew;
1992 30 unneback 
   assign rew = 1'b0;
1993 29 unneback 
   reg  [length:1] qi;
1994 
   wire [length:1] q_next;
1995 
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1996 
 
1997 
   always @ (posedge clk or posedge rst)
1998 
     if (rst)
1999 
       qi <= {length{1'b0}};
2000 
     else
2001 
     if (cke)
2002 
       qi <= q_next;
2003 
 
2004 
   assign q = qi;
2005 
 
2006 
 
2007 
    always @ (posedge clk or posedge rst)
2008 
    if (rst)
2009 
        level1 <= 1'b0;
2010 
    else
2011 
    if (cke)
2012 
    if (clear)
2013 
        level1 <= 1'b0;
2014 
    else if (q_next == level1_value)
2015 
        level1 <= 1'b1;
2016 
    else if (qi == level1_value & rew)
2017 
        level1 <= 1'b0;
2018 
 
2019 
    always @ (posedge clk or posedge rst)
2020 
    if (rst)
2021 
        level2 <= 1'b0;
2022 
    else
2023 
    if (cke)
2024 
    if (clear)
2025 
        level2 <= 1'b0;
2026 
    else if (q_next == level2_value)
2027 
        level2 <= 1'b1;
2028 
    else if (qi == level2_value & rew)
2029 
        level2 <= 1'b0;
2030 
endmodule
2031 40 unneback 
`endif
2032 
`ifdef CNT_BIN_CE_CLEAR_SET_REW
2033 29 unneback 
//////////////////////////////////////////////////////////////////////
2034 
////                                                              ////
2035 
////  Versatile counter                                           ////
2036 
////                                                              ////
2037 
////  Description                                                 ////
2038 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2039 
////  counter                                                     ////
2040 
////                                                              ////
2041 
////  To Do:                                                      ////
2042 
////   - add LFSR with more taps                                  ////
2043 
////                                                              ////
2044 
////  Author(s):                                                  ////
2045 
////      - Michael Unneback, unneback@opencores.org              ////
2046 
////        ORSoC AB                                              ////
2047 
////                                                              ////
2048 
//////////////////////////////////////////////////////////////////////
2049 
////                                                              ////
2050 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2051 
////                                                              ////
2052 
//// This source file may be used and distributed without         ////
2053 
//// restriction provided that this copyright statement is not    ////
2054 
//// removed from the file and that any derivative work contains  ////
2055 
//// the original copyright notice and the associated disclaimer. ////
2056 
////                                                              ////
2057 
//// This source file is free software; you can redistribute it   ////
2058 
//// and/or modify it under the terms of the GNU Lesser General   ////
2059 
//// Public License as published by the Free Software Foundation; ////
2060 
//// either version 2.1 of the License, or (at your option) any   ////
2061 
//// later version.                                               ////
2062 
////                                                              ////
2063 
//// This source is distributed in the hope that it will be       ////
2064 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2065 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2066 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2067 
//// details.                                                     ////
2068 
////                                                              ////
2069 
//// You should have received a copy of the GNU Lesser General    ////
2070 
//// Public License along with this source; if not, download it   ////
2071 
//// from http://www.opencores.org/lgpl.shtml                     ////
2072 
////                                                              ////
2073 
//////////////////////////////////////////////////////////////////////
2074 
 
2075 
// binary counter
2076 6 unneback 
 
2077 40 unneback 
`define MODULE cnt_bin_ce_clear_set_rew
2078 
module `BASE`MODULE (
2079 
`undef MODULE
2080 
 clear, set, cke, rew, q, rst, clk);
2081 
 
2082 6 unneback 
   parameter length = 4;
2083 
   input clear;
2084 
   input set;
2085 
   input cke;
2086 
   input rew;
2087 
   output [length:1] q;
2088 
   input rst;
2089 
   input clk;
2090 
 
2091 
   parameter clear_value = 0;
2092 
   parameter set_value = 1;
2093 
   parameter wrap_value = 0;
2094 
   parameter level1_value = 15;
2095 
 
2096 
   reg  [length:1] qi;
2097 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2098 
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
2099 
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
2100 
   assign q_next = rew ? q_next_rew : q_next_fw;
2101 
 
2102 
   always @ (posedge clk or posedge rst)
2103 
     if (rst)
2104 
       qi <= {length{1'b0}};
2105 
     else
2106 
     if (cke)
2107 
       qi <= q_next;
2108 
 
2109 
   assign q = qi;
2110 
 
2111 
endmodule
2112 40 unneback 
`endif
2113 
`ifdef CNT_BIN_CE_REW_L1
2114 6 unneback 
//////////////////////////////////////////////////////////////////////
2115 
////                                                              ////
2116 
////  Versatile counter                                           ////
2117 
////                                                              ////
2118 
////  Description                                                 ////
2119 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2120 
////  counter                                                     ////
2121 
////                                                              ////
2122 
////  To Do:                                                      ////
2123 
////   - add LFSR with more taps                                  ////
2124 
////                                                              ////
2125 
////  Author(s):                                                  ////
2126 
////      - Michael Unneback, unneback@opencores.org              ////
2127 
////        ORSoC AB                                              ////
2128 
////                                                              ////
2129 
//////////////////////////////////////////////////////////////////////
2130 
////                                                              ////
2131 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2132 
////                                                              ////
2133 
//// This source file may be used and distributed without         ////
2134 
//// restriction provided that this copyright statement is not    ////
2135 
//// removed from the file and that any derivative work contains  ////
2136 
//// the original copyright notice and the associated disclaimer. ////
2137 
////                                                              ////
2138 
//// This source file is free software; you can redistribute it   ////
2139 
//// and/or modify it under the terms of the GNU Lesser General   ////
2140 
//// Public License as published by the Free Software Foundation; ////
2141 
//// either version 2.1 of the License, or (at your option) any   ////
2142 
//// later version.                                               ////
2143 
////                                                              ////
2144 
//// This source is distributed in the hope that it will be       ////
2145 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2146 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2147 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2148 
//// details.                                                     ////
2149 
////                                                              ////
2150 
//// You should have received a copy of the GNU Lesser General    ////
2151 
//// Public License along with this source; if not, download it   ////
2152 
//// from http://www.opencores.org/lgpl.shtml                     ////
2153 
////                                                              ////
2154 
//////////////////////////////////////////////////////////////////////
2155 
 
2156 
// binary counter
2157 
 
2158 40 unneback 
`define MODULE cnt_bin_ce_rew_l1
2159 
module `BASE`MODULE (
2160 
`undef MODULE
2161 
 cke, rew, level1, rst, clk);
2162 
 
2163 6 unneback 
   parameter length = 4;
2164 
   input cke;
2165 
   input rew;
2166 
   output reg level1;
2167 
   input rst;
2168 
   input clk;
2169 
 
2170 
   parameter clear_value = 0;
2171 
   parameter set_value = 1;
2172 
   parameter wrap_value = 1;
2173 
   parameter level1_value = 15;
2174 
 
2175 29 unneback 
   wire clear;
2176 30 unneback 
   assign clear = 1'b0;
2177 6 unneback 
   reg  [length:1] qi;
2178 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2179 
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2180 
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2181 
   assign q_next = rew ? q_next_rew : q_next_fw;
2182 
 
2183 
   always @ (posedge clk or posedge rst)
2184 
     if (rst)
2185 
       qi <= {length{1'b0}};
2186 
     else
2187 
     if (cke)
2188 
       qi <= q_next;
2189 
 
2190 
 
2191 
 
2192 
    always @ (posedge clk or posedge rst)
2193 
    if (rst)
2194 
        level1 <= 1'b0;
2195 
    else
2196 
    if (cke)
2197 29 unneback 
    if (clear)
2198 
        level1 <= 1'b0;
2199 
    else if (q_next == level1_value)
2200 6 unneback 
        level1 <= 1'b1;
2201 
    else if (qi == level1_value & rew)
2202 
        level1 <= 1'b0;
2203 
endmodule
2204 40 unneback 
`endif
2205 
`ifdef CNT_BIN_CE_REW_ZQ_L1
2206 6 unneback 
//////////////////////////////////////////////////////////////////////
2207 
////                                                              ////
2208 
////  Versatile counter                                           ////
2209 
////                                                              ////
2210 
////  Description                                                 ////
2211 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2212 
////  counter                                                     ////
2213 
////                                                              ////
2214 
////  To Do:                                                      ////
2215 
////   - add LFSR with more taps                                  ////
2216 
////                                                              ////
2217 
////  Author(s):                                                  ////
2218 
////      - Michael Unneback, unneback@opencores.org              ////
2219 
////        ORSoC AB                                              ////
2220 
////                                                              ////
2221 
//////////////////////////////////////////////////////////////////////
2222 
////                                                              ////
2223 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2224 
////                                                              ////
2225 
//// This source file may be used and distributed without         ////
2226 
//// restriction provided that this copyright statement is not    ////
2227 
//// removed from the file and that any derivative work contains  ////
2228 
//// the original copyright notice and the associated disclaimer. ////
2229 
////                                                              ////
2230 
//// This source file is free software; you can redistribute it   ////
2231 
//// and/or modify it under the terms of the GNU Lesser General   ////
2232 
//// Public License as published by the Free Software Foundation; ////
2233 
//// either version 2.1 of the License, or (at your option) any   ////
2234 
//// later version.                                               ////
2235 
////                                                              ////
2236 
//// This source is distributed in the hope that it will be       ////
2237 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2238 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2239 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2240 
//// details.                                                     ////
2241 
////                                                              ////
2242 
//// You should have received a copy of the GNU Lesser General    ////
2243 
//// Public License along with this source; if not, download it   ////
2244 
//// from http://www.opencores.org/lgpl.shtml                     ////
2245 
////                                                              ////
2246 
//////////////////////////////////////////////////////////////////////
2247 
 
2248 25 unneback 
// binary counter
2249 
 
2250 40 unneback 
`define MODULE cnt_bin_ce_rew_zq_l1
2251 
module `BASE`MODULE (
2252 
`undef MODULE
2253 
 cke, rew, zq, level1, rst, clk);
2254 
 
2255 25 unneback 
   parameter length = 4;
2256 
   input cke;
2257 
   input rew;
2258 
   output reg zq;
2259 
   output reg level1;
2260 
   input rst;
2261 
   input clk;
2262 
 
2263 
   parameter clear_value = 0;
2264 
   parameter set_value = 1;
2265 
   parameter wrap_value = 1;
2266 
   parameter level1_value = 15;
2267 
 
2268 29 unneback 
   wire clear;
2269 30 unneback 
   assign clear = 1'b0;
2270 25 unneback 
   reg  [length:1] qi;
2271 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2272 
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2273 
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2274 
   assign q_next = rew ? q_next_rew : q_next_fw;
2275 
 
2276 
   always @ (posedge clk or posedge rst)
2277 
     if (rst)
2278 
       qi <= {length{1'b0}};
2279 
     else
2280 
     if (cke)
2281 
       qi <= q_next;
2282 
 
2283 
 
2284 
 
2285 
   always @ (posedge clk or posedge rst)
2286 
     if (rst)
2287 
       zq <= 1'b1;
2288 
     else
2289 
     if (cke)
2290 
       zq <= q_next == {length{1'b0}};
2291 
 
2292 
    always @ (posedge clk or posedge rst)
2293 
    if (rst)
2294 
        level1 <= 1'b0;
2295 
    else
2296 
    if (cke)
2297 29 unneback 
    if (clear)
2298 
        level1 <= 1'b0;
2299 
    else if (q_next == level1_value)
2300 25 unneback 
        level1 <= 1'b1;
2301 
    else if (qi == level1_value & rew)
2302 
        level1 <= 1'b0;
2303 
endmodule
2304 40 unneback 
`endif
2305 
`ifdef CNT_BIN_CE_REW_Q_ZQ_L1
2306 25 unneback 
//////////////////////////////////////////////////////////////////////
2307 
////                                                              ////
2308 
////  Versatile counter                                           ////
2309 
////                                                              ////
2310 
////  Description                                                 ////
2311 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2312 
////  counter                                                     ////
2313 
////                                                              ////
2314 
////  To Do:                                                      ////
2315 
////   - add LFSR with more taps                                  ////
2316 
////                                                              ////
2317 
////  Author(s):                                                  ////
2318 
////      - Michael Unneback, unneback@opencores.org              ////
2319 
////        ORSoC AB                                              ////
2320 
////                                                              ////
2321 
//////////////////////////////////////////////////////////////////////
2322 
////                                                              ////
2323 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2324 
////                                                              ////
2325 
//// This source file may be used and distributed without         ////
2326 
//// restriction provided that this copyright statement is not    ////
2327 
//// removed from the file and that any derivative work contains  ////
2328 
//// the original copyright notice and the associated disclaimer. ////
2329 
////                                                              ////
2330 
//// This source file is free software; you can redistribute it   ////
2331 
//// and/or modify it under the terms of the GNU Lesser General   ////
2332 
//// Public License as published by the Free Software Foundation; ////
2333 
//// either version 2.1 of the License, or (at your option) any   ////
2334 
//// later version.                                               ////
2335 
////                                                              ////
2336 
//// This source is distributed in the hope that it will be       ////
2337 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2338 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2339 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2340 
//// details.                                                     ////
2341 
////                                                              ////
2342 
//// You should have received a copy of the GNU Lesser General    ////
2343 
//// Public License along with this source; if not, download it   ////
2344 
//// from http://www.opencores.org/lgpl.shtml                     ////
2345 
////                                                              ////
2346 
//////////////////////////////////////////////////////////////////////
2347 
 
2348 
// binary counter
2349 
 
2350 40 unneback 
`define MODULE cnt_bin_ce_rew_q_zq_l1
2351 
module `BASE`MODULE (
2352 
`undef MODULE
2353 
 cke, rew, q, zq, level1, rst, clk);
2354 
 
2355 25 unneback 
   parameter length = 4;
2356 
   input cke;
2357 
   input rew;
2358 
   output [length:1] q;
2359 
   output reg zq;
2360 
   output reg level1;
2361 
   input rst;
2362 
   input clk;
2363 
 
2364 
   parameter clear_value = 0;
2365 
   parameter set_value = 1;
2366 
   parameter wrap_value = 1;
2367 
   parameter level1_value = 15;
2368 
 
2369 29 unneback 
   wire clear;
2370 30 unneback 
   assign clear = 1'b0;
2371 25 unneback 
   reg  [length:1] qi;
2372 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2373 
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2374 
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2375 
   assign q_next = rew ? q_next_rew : q_next_fw;
2376 
 
2377 
   always @ (posedge clk or posedge rst)
2378 
     if (rst)
2379 
       qi <= {length{1'b0}};
2380 
     else
2381 
     if (cke)
2382 
       qi <= q_next;
2383 
 
2384 
   assign q = qi;
2385 
 
2386 
 
2387 
   always @ (posedge clk or posedge rst)
2388 
     if (rst)
2389 
       zq <= 1'b1;
2390 
     else
2391 
     if (cke)
2392 
       zq <= q_next == {length{1'b0}};
2393 
 
2394 
    always @ (posedge clk or posedge rst)
2395 
    if (rst)
2396 
        level1 <= 1'b0;
2397 
    else
2398 
    if (cke)
2399 29 unneback 
    if (clear)
2400 
        level1 <= 1'b0;
2401 
    else if (q_next == level1_value)
2402 25 unneback 
        level1 <= 1'b1;
2403 
    else if (qi == level1_value & rew)
2404 
        level1 <= 1'b0;
2405 
endmodule
2406 40 unneback 
`endif
2407 
`ifdef CNT_LFSR_ZQ
2408 25 unneback 
//////////////////////////////////////////////////////////////////////
2409 
////                                                              ////
2410 
////  Versatile counter                                           ////
2411 
////                                                              ////
2412 
////  Description                                                 ////
2413 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2414 
////  counter                                                     ////
2415 
////                                                              ////
2416 
////  To Do:                                                      ////
2417 
////   - add LFSR with more taps                                  ////
2418 
////                                                              ////
2419 
////  Author(s):                                                  ////
2420 
////      - Michael Unneback, unneback@opencores.org              ////
2421 
////        ORSoC AB                                              ////
2422 
////                                                              ////
2423 
//////////////////////////////////////////////////////////////////////
2424 
////                                                              ////
2425 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2426 
////                                                              ////
2427 
//// This source file may be used and distributed without         ////
2428 
//// restriction provided that this copyright statement is not    ////
2429 
//// removed from the file and that any derivative work contains  ////
2430 
//// the original copyright notice and the associated disclaimer. ////
2431 
////                                                              ////
2432 
//// This source file is free software; you can redistribute it   ////
2433 
//// and/or modify it under the terms of the GNU Lesser General   ////
2434 
//// Public License as published by the Free Software Foundation; ////
2435 
//// either version 2.1 of the License, or (at your option) any   ////
2436 
//// later version.                                               ////
2437 
////                                                              ////
2438 
//// This source is distributed in the hope that it will be       ////
2439 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2440 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2441 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2442 
//// details.                                                     ////
2443 
////                                                              ////
2444 
//// You should have received a copy of the GNU Lesser General    ////
2445 
//// Public License along with this source; if not, download it   ////
2446 
//// from http://www.opencores.org/lgpl.shtml                     ////
2447 
////                                                              ////
2448 
//////////////////////////////////////////////////////////////////////
2449 
 
2450 6 unneback 
// LFSR counter
2451 
 
2452 40 unneback 
`define MODULE cnt_lfsr_zq
2453 
module `BASE`MODULE (
2454 
`undef MODULE
2455 
 zq, rst, clk);
2456 
 
2457 6 unneback 
   parameter length = 4;
2458 
   output reg zq;
2459 
   input rst;
2460 
   input clk;
2461 
 
2462 
   parameter clear_value = 0;
2463 
   parameter set_value = 1;
2464 
   parameter wrap_value = 8;
2465 
   parameter level1_value = 15;
2466 
 
2467 
   reg  [length:1] qi;
2468 
   reg lfsr_fb;
2469 
   wire [length:1] q_next;
2470 
   reg [32:1] polynom;
2471 
   integer i;
2472 
 
2473 
   always @ (qi)
2474 
   begin
2475 
        case (length)
2476 
         2: polynom = 32'b11;                               // 0x3
2477 
         3: polynom = 32'b110;                              // 0x6
2478 
         4: polynom = 32'b1100;                             // 0xC
2479 
         5: polynom = 32'b10100;                            // 0x14
2480 
         6: polynom = 32'b110000;                           // 0x30
2481 
         7: polynom = 32'b1100000;                          // 0x60
2482 
         8: polynom = 32'b10111000;                         // 0xb8
2483 
         9: polynom = 32'b100010000;                        // 0x110
2484 
        10: polynom = 32'b1001000000;                       // 0x240
2485 
        11: polynom = 32'b10100000000;                      // 0x500
2486 
        12: polynom = 32'b100000101001;                     // 0x829
2487 
        13: polynom = 32'b1000000001100;                    // 0x100C
2488 
        14: polynom = 32'b10000000010101;                   // 0x2015
2489 
        15: polynom = 32'b110000000000000;                  // 0x6000
2490 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2491 
        17: polynom = 32'b10010000000000000;                // 0x12000
2492 
        18: polynom = 32'b100000010000000000;               // 0x20400
2493 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2494 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2495 6 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2496 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2497 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2498 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2499 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2500 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2501 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2502 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2503 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2504 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2505 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2506 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2507 
        default: polynom = 32'b0;
2508 
        endcase
2509 
        lfsr_fb = qi[length];
2510 
        for (i=length-1; i>=1; i=i-1) begin
2511 
            if (polynom[i])
2512 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2513 
        end
2514 
    end
2515 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2516 
 
2517 
   always @ (posedge clk or posedge rst)
2518 
     if (rst)
2519 
       qi <= {length{1'b0}};
2520 
     else
2521 
       qi <= q_next;
2522 
 
2523 
 
2524 
 
2525 
   always @ (posedge clk or posedge rst)
2526 
     if (rst)
2527 
       zq <= 1'b1;
2528 
     else
2529 
       zq <= q_next == {length{1'b0}};
2530 
endmodule
2531 40 unneback 
`endif
2532 75 unneback 
`ifdef CNT_LFSR_CE
2533 
//////////////////////////////////////////////////////////////////////
2534 
////                                                              ////
2535 
////  Versatile counter                                           ////
2536 
////                                                              ////
2537 
////  Description                                                 ////
2538 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2539 
////  counter                                                     ////
2540 
////                                                              ////
2541 
////  To Do:                                                      ////
2542 
////   - add LFSR with more taps                                  ////
2543 
////                                                              ////
2544 
////  Author(s):                                                  ////
2545 
////      - Michael Unneback, unneback@opencores.org              ////
2546 
////        ORSoC AB                                              ////
2547 
////                                                              ////
2548 
//////////////////////////////////////////////////////////////////////
2549 
////                                                              ////
2550 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2551 
////                                                              ////
2552 
//// This source file may be used and distributed without         ////
2553 
//// restriction provided that this copyright statement is not    ////
2554 
//// removed from the file and that any derivative work contains  ////
2555 
//// the original copyright notice and the associated disclaimer. ////
2556 
////                                                              ////
2557 
//// This source file is free software; you can redistribute it   ////
2558 
//// and/or modify it under the terms of the GNU Lesser General   ////
2559 
//// Public License as published by the Free Software Foundation; ////
2560 
//// either version 2.1 of the License, or (at your option) any   ////
2561 
//// later version.                                               ////
2562 
////                                                              ////
2563 
//// This source is distributed in the hope that it will be       ////
2564 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2565 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2566 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2567 
//// details.                                                     ////
2568 
////                                                              ////
2569 
//// You should have received a copy of the GNU Lesser General    ////
2570 
//// Public License along with this source; if not, download it   ////
2571 
//// from http://www.opencores.org/lgpl.shtml                     ////
2572 
////                                                              ////
2573 
//////////////////////////////////////////////////////////////////////
2574 
 
2575 
// LFSR counter
2576 
 
2577 
`define MODULE cnt_lfsr_ce
2578 
module `BASE`MODULE (
2579 
`undef MODULE
2580 
 cke, zq, rst, clk);
2581 
 
2582 
   parameter length = 4;
2583 
   input cke;
2584 
   output reg zq;
2585 
   input rst;
2586 
   input clk;
2587 
 
2588 
   parameter clear_value = 0;
2589 
   parameter set_value = 1;
2590 
   parameter wrap_value = 0;
2591 
   parameter level1_value = 15;
2592 
 
2593 
   reg  [length:1] qi;
2594 
   reg lfsr_fb;
2595 
   wire [length:1] q_next;
2596 
   reg [32:1] polynom;
2597 
   integer i;
2598 
 
2599 
   always @ (qi)
2600 
   begin
2601 
        case (length)
2602 
         2: polynom = 32'b11;                               // 0x3
2603 
         3: polynom = 32'b110;                              // 0x6
2604 
         4: polynom = 32'b1100;                             // 0xC
2605 
         5: polynom = 32'b10100;                            // 0x14
2606 
         6: polynom = 32'b110000;                           // 0x30
2607 
         7: polynom = 32'b1100000;                          // 0x60
2608 
         8: polynom = 32'b10111000;                         // 0xb8
2609 
         9: polynom = 32'b100010000;                        // 0x110
2610 
        10: polynom = 32'b1001000000;                       // 0x240
2611 
        11: polynom = 32'b10100000000;                      // 0x500
2612 
        12: polynom = 32'b100000101001;                     // 0x829
2613 
        13: polynom = 32'b1000000001100;                    // 0x100C
2614 
        14: polynom = 32'b10000000010101;                   // 0x2015
2615 
        15: polynom = 32'b110000000000000;                  // 0x6000
2616 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2617 
        17: polynom = 32'b10010000000000000;                // 0x12000
2618 
        18: polynom = 32'b100000010000000000;               // 0x20400
2619 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2620 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2621 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2622 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2623 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2624 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2625 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2626 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2627 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2628 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2629 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2630 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2631 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2632 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2633 
        default: polynom = 32'b0;
2634 
        endcase
2635 
        lfsr_fb = qi[length];
2636 
        for (i=length-1; i>=1; i=i-1) begin
2637 
            if (polynom[i])
2638 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2639 
        end
2640 
    end
2641 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2642 
 
2643 
   always @ (posedge clk or posedge rst)
2644 
     if (rst)
2645 
       qi <= {length{1'b0}};
2646 
     else
2647 
     if (cke)
2648 
       qi <= q_next;
2649 
 
2650 
 
2651 
 
2652 
   always @ (posedge clk or posedge rst)
2653 
     if (rst)
2654 
       zq <= 1'b1;
2655 
     else
2656 
     if (cke)
2657 
       zq <= q_next == {length{1'b0}};
2658 
endmodule
2659 
`endif
2660 40 unneback 
`ifdef CNT_LFSR_CE_ZQ
2661 6 unneback 
//////////////////////////////////////////////////////////////////////
2662 
////                                                              ////
2663 
////  Versatile counter                                           ////
2664 
////                                                              ////
2665 
////  Description                                                 ////
2666 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2667 
////  counter                                                     ////
2668 
////                                                              ////
2669 
////  To Do:                                                      ////
2670 
////   - add LFSR with more taps                                  ////
2671 
////                                                              ////
2672 
////  Author(s):                                                  ////
2673 
////      - Michael Unneback, unneback@opencores.org              ////
2674 
////        ORSoC AB                                              ////
2675 
////                                                              ////
2676 
//////////////////////////////////////////////////////////////////////
2677 
////                                                              ////
2678 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2679 
////                                                              ////
2680 
//// This source file may be used and distributed without         ////
2681 
//// restriction provided that this copyright statement is not    ////
2682 
//// removed from the file and that any derivative work contains  ////
2683 
//// the original copyright notice and the associated disclaimer. ////
2684 
////                                                              ////
2685 
//// This source file is free software; you can redistribute it   ////
2686 
//// and/or modify it under the terms of the GNU Lesser General   ////
2687 
//// Public License as published by the Free Software Foundation; ////
2688 
//// either version 2.1 of the License, or (at your option) any   ////
2689 
//// later version.                                               ////
2690 
////                                                              ////
2691 
//// This source is distributed in the hope that it will be       ////
2692 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2693 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2694 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2695 
//// details.                                                     ////
2696 
////                                                              ////
2697 
//// You should have received a copy of the GNU Lesser General    ////
2698 
//// Public License along with this source; if not, download it   ////
2699 
//// from http://www.opencores.org/lgpl.shtml                     ////
2700 
////                                                              ////
2701 
//////////////////////////////////////////////////////////////////////
2702 
 
2703 
// LFSR counter
2704 
 
2705 40 unneback 
`define MODULE cnt_lfsr_ce_zq
2706 
module `BASE`MODULE (
2707 
`undef MODULE
2708 
 cke, zq, rst, clk);
2709 
 
2710 6 unneback 
   parameter length = 4;
2711 
   input cke;
2712 
   output reg zq;
2713 
   input rst;
2714 
   input clk;
2715 
 
2716 
   parameter clear_value = 0;
2717 
   parameter set_value = 1;
2718 
   parameter wrap_value = 8;
2719 
   parameter level1_value = 15;
2720 
 
2721 
   reg  [length:1] qi;
2722 
   reg lfsr_fb;
2723 
   wire [length:1] q_next;
2724 
   reg [32:1] polynom;
2725 
   integer i;
2726 
 
2727 
   always @ (qi)
2728 
   begin
2729 
        case (length)
2730 
         2: polynom = 32'b11;                               // 0x3
2731 
         3: polynom = 32'b110;                              // 0x6
2732 
         4: polynom = 32'b1100;                             // 0xC
2733 
         5: polynom = 32'b10100;                            // 0x14
2734 
         6: polynom = 32'b110000;                           // 0x30
2735 
         7: polynom = 32'b1100000;                          // 0x60
2736 
         8: polynom = 32'b10111000;                         // 0xb8
2737 
         9: polynom = 32'b100010000;                        // 0x110
2738 
        10: polynom = 32'b1001000000;                       // 0x240
2739 
        11: polynom = 32'b10100000000;                      // 0x500
2740 
        12: polynom = 32'b100000101001;                     // 0x829
2741 
        13: polynom = 32'b1000000001100;                    // 0x100C
2742 
        14: polynom = 32'b10000000010101;                   // 0x2015
2743 
        15: polynom = 32'b110000000000000;                  // 0x6000
2744 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2745 
        17: polynom = 32'b10010000000000000;                // 0x12000
2746 
        18: polynom = 32'b100000010000000000;               // 0x20400
2747 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2748 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2749 6 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2750 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2751 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2752 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2753 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2754 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2755 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2756 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2757 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2758 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2759 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2760 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2761 
        default: polynom = 32'b0;
2762 
        endcase
2763 
        lfsr_fb = qi[length];
2764 
        for (i=length-1; i>=1; i=i-1) begin
2765 
            if (polynom[i])
2766 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2767 
        end
2768 
    end
2769 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2770 
 
2771 
   always @ (posedge clk or posedge rst)
2772 
     if (rst)
2773 
       qi <= {length{1'b0}};
2774 
     else
2775 
     if (cke)
2776 
       qi <= q_next;
2777 
 
2778 
 
2779 
 
2780 
   always @ (posedge clk or posedge rst)
2781 
     if (rst)
2782 
       zq <= 1'b1;
2783 
     else
2784 
     if (cke)
2785 
       zq <= q_next == {length{1'b0}};
2786 
endmodule
2787 40 unneback 
`endif
2788 
`ifdef CNT_LFSR_CE_Q
2789 6 unneback 
//////////////////////////////////////////////////////////////////////
2790 
////                                                              ////
2791 
////  Versatile counter                                           ////
2792 
////                                                              ////
2793 
////  Description                                                 ////
2794 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2795 
////  counter                                                     ////
2796 
////                                                              ////
2797 
////  To Do:                                                      ////
2798 
////   - add LFSR with more taps                                  ////
2799 
////                                                              ////
2800 
////  Author(s):                                                  ////
2801 
////      - Michael Unneback, unneback@opencores.org              ////
2802 
////        ORSoC AB                                              ////
2803 
////                                                              ////
2804 
//////////////////////////////////////////////////////////////////////
2805 
////                                                              ////
2806 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2807 
////                                                              ////
2808 
//// This source file may be used and distributed without         ////
2809 
//// restriction provided that this copyright statement is not    ////
2810 
//// removed from the file and that any derivative work contains  ////
2811 
//// the original copyright notice and the associated disclaimer. ////
2812 
////                                                              ////
2813 
//// This source file is free software; you can redistribute it   ////
2814 
//// and/or modify it under the terms of the GNU Lesser General   ////
2815 
//// Public License as published by the Free Software Foundation; ////
2816 
//// either version 2.1 of the License, or (at your option) any   ////
2817 
//// later version.                                               ////
2818 
////                                                              ////
2819 
//// This source is distributed in the hope that it will be       ////
2820 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2821 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2822 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2823 
//// details.                                                     ////
2824 
////                                                              ////
2825 
//// You should have received a copy of the GNU Lesser General    ////
2826 
//// Public License along with this source; if not, download it   ////
2827 
//// from http://www.opencores.org/lgpl.shtml                     ////
2828 
////                                                              ////
2829 
//////////////////////////////////////////////////////////////////////
2830 22 unneback 
 
2831 
// LFSR counter
2832 27 unneback 
 
2833 40 unneback 
`define MODULE cnt_lfsr_ce_q
2834 
module `BASE`MODULE (
2835 
`undef MODULE
2836 
 cke, q, rst, clk);
2837 
 
2838 27 unneback 
   parameter length = 4;
2839 
   input cke;
2840 
   output [length:1] q;
2841 
   input rst;
2842 
   input clk;
2843 
 
2844 
   parameter clear_value = 0;
2845 
   parameter set_value = 1;
2846 
   parameter wrap_value = 8;
2847 
   parameter level1_value = 15;
2848 
 
2849 
   reg  [length:1] qi;
2850 
   reg lfsr_fb;
2851 
   wire [length:1] q_next;
2852 
   reg [32:1] polynom;
2853 
   integer i;
2854 
 
2855 
   always @ (qi)
2856 
   begin
2857 
        case (length)
2858 
         2: polynom = 32'b11;                               // 0x3
2859 
         3: polynom = 32'b110;                              // 0x6
2860 
         4: polynom = 32'b1100;                             // 0xC
2861 
         5: polynom = 32'b10100;                            // 0x14
2862 
         6: polynom = 32'b110000;                           // 0x30
2863 
         7: polynom = 32'b1100000;                          // 0x60
2864 
         8: polynom = 32'b10111000;                         // 0xb8
2865 
         9: polynom = 32'b100010000;                        // 0x110
2866 
        10: polynom = 32'b1001000000;                       // 0x240
2867 
        11: polynom = 32'b10100000000;                      // 0x500
2868 
        12: polynom = 32'b100000101001;                     // 0x829
2869 
        13: polynom = 32'b1000000001100;                    // 0x100C
2870 
        14: polynom = 32'b10000000010101;                   // 0x2015
2871 
        15: polynom = 32'b110000000000000;                  // 0x6000
2872 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2873 
        17: polynom = 32'b10010000000000000;                // 0x12000
2874 
        18: polynom = 32'b100000010000000000;               // 0x20400
2875 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2876 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2877 27 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2878 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2879 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2880 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2881 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2882 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2883 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2884 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2885 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2886 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2887 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2888 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2889 
        default: polynom = 32'b0;
2890 
        endcase
2891 
        lfsr_fb = qi[length];
2892 
        for (i=length-1; i>=1; i=i-1) begin
2893 
            if (polynom[i])
2894 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2895 
        end
2896 
    end
2897 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2898 
 
2899 
   always @ (posedge clk or posedge rst)
2900 
     if (rst)
2901 
       qi <= {length{1'b0}};
2902 
     else
2903 
     if (cke)
2904 
       qi <= q_next;
2905 
 
2906 
   assign q = qi;
2907 
 
2908 
endmodule
2909 40 unneback 
`endif
2910 
`ifdef CNT_LFSR_CE_CLEAR_Q
2911 27 unneback 
//////////////////////////////////////////////////////////////////////
2912 
////                                                              ////
2913 
////  Versatile counter                                           ////
2914 
////                                                              ////
2915 
////  Description                                                 ////
2916 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2917 
////  counter                                                     ////
2918 
////                                                              ////
2919 
////  To Do:                                                      ////
2920 
////   - add LFSR with more taps                                  ////
2921 
////                                                              ////
2922 
////  Author(s):                                                  ////
2923 
////      - Michael Unneback, unneback@opencores.org              ////
2924 
////        ORSoC AB                                              ////
2925 
////                                                              ////
2926 
//////////////////////////////////////////////////////////////////////
2927 
////                                                              ////
2928 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2929 
////                                                              ////
2930 
//// This source file may be used and distributed without         ////
2931 
//// restriction provided that this copyright statement is not    ////
2932 
//// removed from the file and that any derivative work contains  ////
2933 
//// the original copyright notice and the associated disclaimer. ////
2934 
////                                                              ////
2935 
//// This source file is free software; you can redistribute it   ////
2936 
//// and/or modify it under the terms of the GNU Lesser General   ////
2937 
//// Public License as published by the Free Software Foundation; ////
2938 
//// either version 2.1 of the License, or (at your option) any   ////
2939 
//// later version.                                               ////
2940 
////                                                              ////
2941 
//// This source is distributed in the hope that it will be       ////
2942 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2943 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2944 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2945 
//// details.                                                     ////
2946 
////                                                              ////
2947 
//// You should have received a copy of the GNU Lesser General    ////
2948 
//// Public License along with this source; if not, download it   ////
2949 
//// from http://www.opencores.org/lgpl.shtml                     ////
2950 
////                                                              ////
2951 
//////////////////////////////////////////////////////////////////////
2952 
 
2953 
// LFSR counter
2954 
 
2955 40 unneback 
`define MODULE cnt_lfsr_ce_clear_q
2956 
module `BASE`MODULE (
2957 
`undef MODULE
2958 
 clear, cke, q, rst, clk);
2959 
 
2960 27 unneback 
   parameter length = 4;
2961 
   input clear;
2962 
   input cke;
2963 
   output [length:1] q;
2964 
   input rst;
2965 
   input clk;
2966 
 
2967 
   parameter clear_value = 0;
2968 
   parameter set_value = 1;
2969 
   parameter wrap_value = 8;
2970 
   parameter level1_value = 15;
2971 
 
2972 
   reg  [length:1] qi;
2973 
   reg lfsr_fb;
2974 
   wire [length:1] q_next;
2975 
   reg [32:1] polynom;
2976 
   integer i;
2977 
 
2978 
   always @ (qi)
2979 
   begin
2980 
        case (length)
2981 
         2: polynom = 32'b11;                               // 0x3
2982 
         3: polynom = 32'b110;                              // 0x6
2983 
         4: polynom = 32'b1100;                             // 0xC
2984 
         5: polynom = 32'b10100;                            // 0x14
2985 
         6: polynom = 32'b110000;                           // 0x30
2986 
         7: polynom = 32'b1100000;                          // 0x60
2987 
         8: polynom = 32'b10111000;                         // 0xb8
2988 
         9: polynom = 32'b100010000;                        // 0x110
2989 
        10: polynom = 32'b1001000000;                       // 0x240
2990 
        11: polynom = 32'b10100000000;                      // 0x500
2991 
        12: polynom = 32'b100000101001;                     // 0x829
2992 
        13: polynom = 32'b1000000001100;                    // 0x100C
2993 
        14: polynom = 32'b10000000010101;                   // 0x2015
2994 
        15: polynom = 32'b110000000000000;                  // 0x6000
2995 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2996 
        17: polynom = 32'b10010000000000000;                // 0x12000
2997 
        18: polynom = 32'b100000010000000000;               // 0x20400
2998 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2999 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
3000 27 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
3001 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
3002 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
3003 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
3004 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
3005 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
3006 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
3007 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
3008 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
3009 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
3010 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
3011 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
3012 
        default: polynom = 32'b0;
3013 
        endcase
3014 
        lfsr_fb = qi[length];
3015 
        for (i=length-1; i>=1; i=i-1) begin
3016 
            if (polynom[i])
3017 
                lfsr_fb = lfsr_fb  ~^ qi[i];
3018 
        end
3019 
    end
3020 
   assign q_next =  clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
3021 
 
3022 
   always @ (posedge clk or posedge rst)
3023 
     if (rst)
3024 
       qi <= {length{1'b0}};
3025 
     else
3026 
     if (cke)
3027 
       qi <= q_next;
3028 
 
3029 
   assign q = qi;
3030 
 
3031 
endmodule
3032 40 unneback 
`endif
3033 
`ifdef CNT_LFSR_CE_Q_ZQ
3034 27 unneback 
//////////////////////////////////////////////////////////////////////
3035 
////                                                              ////
3036 
////  Versatile counter                                           ////
3037 
////                                                              ////
3038 
////  Description                                                 ////
3039 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3040 
////  counter                                                     ////
3041 
////                                                              ////
3042 
////  To Do:                                                      ////
3043 
////   - add LFSR with more taps                                  ////
3044 
////                                                              ////
3045 
////  Author(s):                                                  ////
3046 
////      - Michael Unneback, unneback@opencores.org              ////
3047 
////        ORSoC AB                                              ////
3048 
////                                                              ////
3049 
//////////////////////////////////////////////////////////////////////
3050 
////                                                              ////
3051 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3052 
////                                                              ////
3053 
//// This source file may be used and distributed without         ////
3054 
//// restriction provided that this copyright statement is not    ////
3055 
//// removed from the file and that any derivative work contains  ////
3056 
//// the original copyright notice and the associated disclaimer. ////
3057 
////                                                              ////
3058 
//// This source file is free software; you can redistribute it   ////
3059 
//// and/or modify it under the terms of the GNU Lesser General   ////
3060 
//// Public License as published by the Free Software Foundation; ////
3061 
//// either version 2.1 of the License, or (at your option) any   ////
3062 
//// later version.                                               ////
3063 
////                                                              ////
3064 
//// This source is distributed in the hope that it will be       ////
3065 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3066 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3067 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3068 
//// details.                                                     ////
3069 
////                                                              ////
3070 
//// You should have received a copy of the GNU Lesser General    ////
3071 
//// Public License along with this source; if not, download it   ////
3072 
//// from http://www.opencores.org/lgpl.shtml                     ////
3073 
////                                                              ////
3074 
//////////////////////////////////////////////////////////////////////
3075 
 
3076 
// LFSR counter
3077 22 unneback 
 
3078 40 unneback 
`define MODULE cnt_lfsr_ce_q_zq
3079 
module `BASE`MODULE (
3080 
`undef MODULE
3081 
 cke, q, zq, rst, clk);
3082 
 
3083 22 unneback 
   parameter length = 4;
3084 
   input cke;
3085 
   output [length:1] q;
3086 
   output reg zq;
3087 
   input rst;
3088 
   input clk;
3089 
 
3090 
   parameter clear_value = 0;
3091 
   parameter set_value = 1;
3092 
   parameter wrap_value = 8;
3093 
   parameter level1_value = 15;
3094 
 
3095 
   reg  [length:1] qi;
3096 
   reg lfsr_fb;
3097 
   wire [length:1] q_next;
3098 
   reg [32:1] polynom;
3099 
   integer i;
3100 
 
3101 
   always @ (qi)
3102 
   begin
3103 
        case (length)
3104 
         2: polynom = 32'b11;                               // 0x3
3105 
         3: polynom = 32'b110;                              // 0x6
3106 
         4: polynom = 32'b1100;                             // 0xC
3107 
         5: polynom = 32'b10100;                            // 0x14
3108 
         6: polynom = 32'b110000;                           // 0x30
3109 
         7: polynom = 32'b1100000;                          // 0x60
3110 
         8: polynom = 32'b10111000;                         // 0xb8
3111 
         9: polynom = 32'b100010000;                        // 0x110
3112 
        10: polynom = 32'b1001000000;                       // 0x240
3113 
        11: polynom = 32'b10100000000;                      // 0x500
3114 
        12: polynom = 32'b100000101001;                     // 0x829
3115 
        13: polynom = 32'b1000000001100;                    // 0x100C
3116 
        14: polynom = 32'b10000000010101;                   // 0x2015
3117 
        15: polynom = 32'b110000000000000;                  // 0x6000
3118 
        16: polynom = 32'b1101000000001000;                 // 0xD008
3119 
        17: polynom = 32'b10010000000000000;                // 0x12000
3120 
        18: polynom = 32'b100000010000000000;               // 0x20400
3121 
        19: polynom = 32'b1000000000000100011;              // 0x40023
3122 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
3123 22 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
3124 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
3125 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
3126 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
3127 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
3128 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
3129 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
3130 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
3131 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
3132 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
3133 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
3134 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
3135 
        default: polynom = 32'b0;
3136 
        endcase
3137 
        lfsr_fb = qi[length];
3138 
        for (i=length-1; i>=1; i=i-1) begin
3139 
            if (polynom[i])
3140 
                lfsr_fb = lfsr_fb  ~^ qi[i];
3141 
        end
3142 
    end
3143 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
3144 
 
3145 
   always @ (posedge clk or posedge rst)
3146 
     if (rst)
3147 
       qi <= {length{1'b0}};
3148 
     else
3149 
     if (cke)
3150 
       qi <= q_next;
3151 
 
3152 
   assign q = qi;
3153 
 
3154 
 
3155 
   always @ (posedge clk or posedge rst)
3156 
     if (rst)
3157 
       zq <= 1'b1;
3158 
     else
3159 
     if (cke)
3160 
       zq <= q_next == {length{1'b0}};
3161 
endmodule
3162 40 unneback 
`endif
3163 
`ifdef CNT_LFSR_CE_REW_L1
3164 22 unneback 
//////////////////////////////////////////////////////////////////////
3165 
////                                                              ////
3166 
////  Versatile counter                                           ////
3167 
////                                                              ////
3168 
////  Description                                                 ////
3169 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3170 
////  counter                                                     ////
3171 
////                                                              ////
3172 
////  To Do:                                                      ////
3173 
////   - add LFSR with more taps                                  ////
3174 
////                                                              ////
3175 
////  Author(s):                                                  ////
3176 
////      - Michael Unneback, unneback@opencores.org              ////
3177 
////        ORSoC AB                                              ////
3178 
////                                                              ////
3179 
//////////////////////////////////////////////////////////////////////
3180 
////                                                              ////
3181 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3182 
////                                                              ////
3183 
//// This source file may be used and distributed without         ////
3184 
//// restriction provided that this copyright statement is not    ////
3185 
//// removed from the file and that any derivative work contains  ////
3186 
//// the original copyright notice and the associated disclaimer. ////
3187 
////                                                              ////
3188 
//// This source file is free software; you can redistribute it   ////
3189 
//// and/or modify it under the terms of the GNU Lesser General   ////
3190 
//// Public License as published by the Free Software Foundation; ////
3191 
//// either version 2.1 of the License, or (at your option) any   ////
3192 
//// later version.                                               ////
3193 
////                                                              ////
3194 
//// This source is distributed in the hope that it will be       ////
3195 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3196 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3197 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3198 
//// details.                                                     ////
3199 
////                                                              ////
3200 
//// You should have received a copy of the GNU Lesser General    ////
3201 
//// Public License along with this source; if not, download it   ////
3202 
//// from http://www.opencores.org/lgpl.shtml                     ////
3203 
////                                                              ////
3204 
//////////////////////////////////////////////////////////////////////
3205 6 unneback 
 
3206 
// LFSR counter
3207 
 
3208 40 unneback 
`define MODULE cnt_lfsr_ce_rew_l1
3209 
module `BASE`MODULE (
3210 
`undef MODULE
3211 
 cke, rew, level1, rst, clk);
3212 
 
3213 6 unneback 
   parameter length = 4;
3214 
   input cke;
3215 
   input rew;
3216 
   output reg level1;
3217 
   input rst;
3218 
   input clk;
3219 
 
3220 
   parameter clear_value = 0;
3221 
   parameter set_value = 1;
3222 
   parameter wrap_value = 8;
3223 
   parameter level1_value = 15;
3224 
 
3225 29 unneback 
   wire clear;
3226 30 unneback 
   assign clear = 1'b0;
3227 6 unneback 
   reg  [length:1] qi;
3228 
   reg lfsr_fb, lfsr_fb_rew;
3229 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
3230 
   reg [32:1] polynom_rew;
3231 
   integer j;
3232 
   reg [32:1] polynom;
3233 
   integer i;
3234 
 
3235 
   always @ (qi)
3236 
   begin
3237 
        case (length)
3238 
         2: polynom = 32'b11;                               // 0x3
3239 
         3: polynom = 32'b110;                              // 0x6
3240 
         4: polynom = 32'b1100;                             // 0xC
3241 
         5: polynom = 32'b10100;                            // 0x14
3242 
         6: polynom = 32'b110000;                           // 0x30
3243 
         7: polynom = 32'b1100000;                          // 0x60
3244 
         8: polynom = 32'b10111000;                         // 0xb8
3245 
         9: polynom = 32'b100010000;                        // 0x110
3246 
        10: polynom = 32'b1001000000;                       // 0x240
3247 
        11: polynom = 32'b10100000000;                      // 0x500
3248 
        12: polynom = 32'b100000101001;                     // 0x829
3249 
        13: polynom = 32'b1000000001100;                    // 0x100C
3250 
        14: polynom = 32'b10000000010101;                   // 0x2015
3251 
        15: polynom = 32'b110000000000000;                  // 0x6000
3252 
        16: polynom = 32'b1101000000001000;                 // 0xD008
3253 
        17: polynom = 32'b10010000000000000;                // 0x12000
3254 
        18: polynom = 32'b100000010000000000;               // 0x20400
3255 
        19: polynom = 32'b1000000000000100011;              // 0x40023
3256 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
3257 6 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
3258 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
3259 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
3260 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
3261 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
3262 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
3263 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
3264 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
3265 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
3266 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
3267 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
3268 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
3269 
        default: polynom = 32'b0;
3270 
        endcase
3271 
        lfsr_fb = qi[length];
3272 
        for (i=length-1; i>=1; i=i-1) begin
3273 
            if (polynom[i])
3274 
                lfsr_fb = lfsr_fb  ~^ qi[i];
3275 
        end
3276 
    end
3277 
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
3278 
   always @ (qi)
3279 
   begin
3280 
        case (length)
3281 
         2: polynom_rew = 32'b11;
3282 
         3: polynom_rew = 32'b110;
3283 
         4: polynom_rew = 32'b1100;
3284 
         5: polynom_rew = 32'b10100;
3285 
         6: polynom_rew = 32'b110000;
3286 
         7: polynom_rew = 32'b1100000;
3287 
         8: polynom_rew = 32'b10111000;
3288 
         9: polynom_rew = 32'b100010000;
3289 
        10: polynom_rew = 32'b1001000000;
3290 
        11: polynom_rew = 32'b10100000000;
3291 
        12: polynom_rew = 32'b100000101001;
3292 
        13: polynom_rew = 32'b1000000001100;
3293 
        14: polynom_rew = 32'b10000000010101;
3294 
        15: polynom_rew = 32'b110000000000000;
3295 
        16: polynom_rew = 32'b1101000000001000;
3296 
        17: polynom_rew = 32'b10010000000000000;
3297 
        18: polynom_rew = 32'b100000010000000000;
3298 
        19: polynom_rew = 32'b1000000000000100011;
3299 
        20: polynom_rew = 32'b10000010000000000000;
3300 
        21: polynom_rew = 32'b101000000000000000000;
3301 
        22: polynom_rew = 32'b1100000000000000000000;
3302 
        23: polynom_rew = 32'b10000100000000000000000;
3303 
        24: polynom_rew = 32'b111000010000000000000000;
3304 
        25: polynom_rew = 32'b1001000000000000000000000;
3305 
        26: polynom_rew = 32'b10000000000000000000100011;
3306 
        27: polynom_rew = 32'b100000000000000000000010011;
3307 
        28: polynom_rew = 32'b1100100000000000000000000000;
3308 
        29: polynom_rew = 32'b10100000000000000000000000000;
3309 
        30: polynom_rew = 32'b100000000000000000000000101001;
3310 
        31: polynom_rew = 32'b1001000000000000000000000000000;
3311 
        32: polynom_rew = 32'b10000000001000000000000000000011;
3312 
        default: polynom_rew = 32'b0;
3313 
        endcase
3314 
        // rotate left
3315 
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
3316 
        lfsr_fb_rew = qi[length];
3317 
        for (i=length-1; i>=1; i=i-1) begin
3318 
            if (polynom_rew[i])
3319 
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
3320 
        end
3321 
    end
3322 
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
3323 
   assign q_next = rew ? q_next_rew : q_next_fw;
3324 
 
3325 
   always @ (posedge clk or posedge rst)
3326 
     if (rst)
3327 
       qi <= {length{1'b0}};
3328 
     else
3329 
     if (cke)
3330 
       qi <= q_next;
3331 
 
3332 
 
3333 
 
3334 
    always @ (posedge clk or posedge rst)
3335 
    if (rst)
3336 
        level1 <= 1'b0;
3337 
    else
3338 
    if (cke)
3339 29 unneback 
    if (clear)
3340 
        level1 <= 1'b0;
3341 
    else if (q_next == level1_value)
3342 6 unneback 
        level1 <= 1'b1;
3343 
    else if (qi == level1_value & rew)
3344 
        level1 <= 1'b0;
3345 
endmodule
3346 40 unneback 
`endif
3347 
`ifdef CNT_GRAY
3348 6 unneback 
//////////////////////////////////////////////////////////////////////
3349 
////                                                              ////
3350 
////  Versatile counter                                           ////
3351 
////                                                              ////
3352 
////  Description                                                 ////
3353 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3354 
////  counter                                                     ////
3355 
////                                                              ////
3356 
////  To Do:                                                      ////
3357 
////   - add LFSR with more taps                                  ////
3358 
////                                                              ////
3359 
////  Author(s):                                                  ////
3360 
////      - Michael Unneback, unneback@opencores.org              ////
3361 
////        ORSoC AB                                              ////
3362 
////                                                              ////
3363 
//////////////////////////////////////////////////////////////////////
3364 
////                                                              ////
3365 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3366 
////                                                              ////
3367 
//// This source file may be used and distributed without         ////
3368 
//// restriction provided that this copyright statement is not    ////
3369 
//// removed from the file and that any derivative work contains  ////
3370 
//// the original copyright notice and the associated disclaimer. ////
3371 
////                                                              ////
3372 
//// This source file is free software; you can redistribute it   ////
3373 
//// and/or modify it under the terms of the GNU Lesser General   ////
3374 
//// Public License as published by the Free Software Foundation; ////
3375 
//// either version 2.1 of the License, or (at your option) any   ////
3376 
//// later version.                                               ////
3377 
////                                                              ////
3378 
//// This source is distributed in the hope that it will be       ////
3379 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3380 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3381 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3382 
//// details.                                                     ////
3383 
////                                                              ////
3384 
//// You should have received a copy of the GNU Lesser General    ////
3385 
//// Public License along with this source; if not, download it   ////
3386 
//// from http://www.opencores.org/lgpl.shtml                     ////
3387 
////                                                              ////
3388 
//////////////////////////////////////////////////////////////////////
3389 
 
3390 
// GRAY counter
3391 
 
3392 40 unneback 
`define MODULE cnt_gray
3393 
module `BASE`MODULE (
3394 
`undef MODULE
3395 
 q, rst, clk);
3396 
 
3397 6 unneback 
   parameter length = 4;
3398 
   output reg [length:1] q;
3399 
   input rst;
3400 
   input clk;
3401 
 
3402 
   parameter clear_value = 0;
3403 
   parameter set_value = 1;
3404 
   parameter wrap_value = 8;
3405 
   parameter level1_value = 15;
3406 
 
3407 
   reg  [length:1] qi;
3408 
   wire [length:1] q_next;
3409 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3410 
 
3411 
   always @ (posedge clk or posedge rst)
3412 
     if (rst)
3413 
       qi <= {length{1'b0}};
3414 
     else
3415 
       qi <= q_next;
3416 
 
3417 
   always @ (posedge clk or posedge rst)
3418 
     if (rst)
3419 
       q <= {length{1'b0}};
3420 
     else
3421 
         q <= (q_next>>1) ^ q_next;
3422 
 
3423 
endmodule
3424 40 unneback 
`endif
3425 
`ifdef CNT_GRAY_CE
3426 6 unneback 
//////////////////////////////////////////////////////////////////////
3427 
////                                                              ////
3428 
////  Versatile counter                                           ////
3429 
////                                                              ////
3430 
////  Description                                                 ////
3431 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3432 
////  counter                                                     ////
3433 
////                                                              ////
3434 
////  To Do:                                                      ////
3435 
////   - add LFSR with more taps                                  ////
3436 
////                                                              ////
3437 
////  Author(s):                                                  ////
3438 
////      - Michael Unneback, unneback@opencores.org              ////
3439 
////        ORSoC AB                                              ////
3440 
////                                                              ////
3441 
//////////////////////////////////////////////////////////////////////
3442 
////                                                              ////
3443 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3444 
////                                                              ////
3445 
//// This source file may be used and distributed without         ////
3446 
//// restriction provided that this copyright statement is not    ////
3447 
//// removed from the file and that any derivative work contains  ////
3448 
//// the original copyright notice and the associated disclaimer. ////
3449 
////                                                              ////
3450 
//// This source file is free software; you can redistribute it   ////
3451 
//// and/or modify it under the terms of the GNU Lesser General   ////
3452 
//// Public License as published by the Free Software Foundation; ////
3453 
//// either version 2.1 of the License, or (at your option) any   ////
3454 
//// later version.                                               ////
3455 
////                                                              ////
3456 
//// This source is distributed in the hope that it will be       ////
3457 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3458 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3459 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3460 
//// details.                                                     ////
3461 
////                                                              ////
3462 
//// You should have received a copy of the GNU Lesser General    ////
3463 
//// Public License along with this source; if not, download it   ////
3464 
//// from http://www.opencores.org/lgpl.shtml                     ////
3465 
////                                                              ////
3466 
//////////////////////////////////////////////////////////////////////
3467 
 
3468 
// GRAY counter
3469 
 
3470 40 unneback 
`define MODULE cnt_gray_ce
3471 
module `BASE`MODULE (
3472 
`undef MODULE
3473 
 cke, q, rst, clk);
3474 
 
3475 6 unneback 
   parameter length = 4;
3476 
   input cke;
3477 
   output reg [length:1] q;
3478 
   input rst;
3479 
   input clk;
3480 
 
3481 
   parameter clear_value = 0;
3482 
   parameter set_value = 1;
3483 
   parameter wrap_value = 8;
3484 
   parameter level1_value = 15;
3485 
 
3486 
   reg  [length:1] qi;
3487 
   wire [length:1] q_next;
3488 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3489 
 
3490 
   always @ (posedge clk or posedge rst)
3491 
     if (rst)
3492 
       qi <= {length{1'b0}};
3493 
     else
3494 
     if (cke)
3495 
       qi <= q_next;
3496 
 
3497 
   always @ (posedge clk or posedge rst)
3498 
     if (rst)
3499 
       q <= {length{1'b0}};
3500 
     else
3501 
       if (cke)
3502 
         q <= (q_next>>1) ^ q_next;
3503 
 
3504 
endmodule
3505 40 unneback 
`endif
3506 
`ifdef CNT_GRAY_CE_BIN
3507 6 unneback 
//////////////////////////////////////////////////////////////////////
3508 
////                                                              ////
3509 
////  Versatile counter                                           ////
3510 
////                                                              ////
3511 
////  Description                                                 ////
3512 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3513 
////  counter                                                     ////
3514 
////                                                              ////
3515 
////  To Do:                                                      ////
3516 
////   - add LFSR with more taps                                  ////
3517 
////                                                              ////
3518 
////  Author(s):                                                  ////
3519 
////      - Michael Unneback, unneback@opencores.org              ////
3520 
////        ORSoC AB                                              ////
3521 
////                                                              ////
3522 
//////////////////////////////////////////////////////////////////////
3523 
////                                                              ////
3524 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3525 
////                                                              ////
3526 
//// This source file may be used and distributed without         ////
3527 
//// restriction provided that this copyright statement is not    ////
3528 
//// removed from the file and that any derivative work contains  ////
3529 
//// the original copyright notice and the associated disclaimer. ////
3530 
////                                                              ////
3531 
//// This source file is free software; you can redistribute it   ////
3532 
//// and/or modify it under the terms of the GNU Lesser General   ////
3533 
//// Public License as published by the Free Software Foundation; ////
3534 
//// either version 2.1 of the License, or (at your option) any   ////
3535 
//// later version.                                               ////
3536 
////                                                              ////
3537 
//// This source is distributed in the hope that it will be       ////
3538 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3539 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3540 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3541 
//// details.                                                     ////
3542 
////                                                              ////
3543 
//// You should have received a copy of the GNU Lesser General    ////
3544 
//// Public License along with this source; if not, download it   ////
3545 
//// from http://www.opencores.org/lgpl.shtml                     ////
3546 
////                                                              ////
3547 
//////////////////////////////////////////////////////////////////////
3548 
 
3549 
// GRAY counter
3550 
 
3551 40 unneback 
`define MODULE cnt_gray_ce_bin
3552 
module `BASE`MODULE (
3553 
`undef MODULE
3554 
 cke, q, q_bin, rst, clk);
3555 
 
3556 6 unneback 
   parameter length = 4;
3557 
   input cke;
3558 
   output reg [length:1] q;
3559 
   output [length:1] q_bin;
3560 
   input rst;
3561 
   input clk;
3562 
 
3563 
   parameter clear_value = 0;
3564 
   parameter set_value = 1;
3565 
   parameter wrap_value = 8;
3566 
   parameter level1_value = 15;
3567 
 
3568 
   reg  [length:1] qi;
3569 
   wire [length:1] q_next;
3570 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3571 
 
3572 
   always @ (posedge clk or posedge rst)
3573 
     if (rst)
3574 
       qi <= {length{1'b0}};
3575 
     else
3576 
     if (cke)
3577 
       qi <= q_next;
3578 
 
3579 
   always @ (posedge clk or posedge rst)
3580 
     if (rst)
3581 
       q <= {length{1'b0}};
3582 
     else
3583 
       if (cke)
3584 
         q <= (q_next>>1) ^ q_next;
3585 
 
3586 
   assign q_bin = qi;
3587 
 
3588 
endmodule
3589 40 unneback 
`endif
3590 6 unneback 
//////////////////////////////////////////////////////////////////////
3591 
////                                                              ////
3592 
////  Versatile library, counters                                 ////
3593 
////                                                              ////
3594 
////  Description                                                 ////
3595 
////  counters                                                    ////
3596 
////                                                              ////
3597 
////                                                              ////
3598 
////  To Do:                                                      ////
3599 
////   - add more counters                                        ////
3600 
////                                                              ////
3601 
////  Author(s):                                                  ////
3602 
////      - Michael Unneback, unneback@opencores.org              ////
3603 
////        ORSoC AB                                              ////
3604 
////                                                              ////
3605 
//////////////////////////////////////////////////////////////////////
3606 
////                                                              ////
3607 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
3608 
////                                                              ////
3609 
//// This source file may be used and distributed without         ////
3610 
//// restriction provided that this copyright statement is not    ////
3611 
//// removed from the file and that any derivative work contains  ////
3612 
//// the original copyright notice and the associated disclaimer. ////
3613 
////                                                              ////
3614 
//// This source file is free software; you can redistribute it   ////
3615 
//// and/or modify it under the terms of the GNU Lesser General   ////
3616 
//// Public License as published by the Free Software Foundation; ////
3617 
//// either version 2.1 of the License, or (at your option) any   ////
3618 
//// later version.                                               ////
3619 
////                                                              ////
3620 
//// This source is distributed in the hope that it will be       ////
3621 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3622 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3623 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3624 
//// details.                                                     ////
3625 
////                                                              ////
3626 
//// You should have received a copy of the GNU Lesser General    ////
3627 
//// Public License along with this source; if not, download it   ////
3628 
//// from http://www.opencores.org/lgpl.shtml                     ////
3629 
////                                                              ////
3630 
//////////////////////////////////////////////////////////////////////
3631 
 
3632 40 unneback 
`ifdef CNT_SHREG_WRAP
3633 
`define MODULE cnt_shreg_wrap
3634 
module `BASE`MODULE ( q, rst, clk);
3635 
`undef MODULE
3636 6 unneback 
 
3637 
   parameter length = 4;
3638 
   output reg [0:length-1] q;
3639 
   input rst;
3640 
   input clk;
3641 
 
3642 
    always @ (posedge clk or posedge rst)
3643 
    if (rst)
3644 
        q <= {1'b1,{length-1{1'b0}}};
3645 
    else
3646 
        q <= {q[length-1],q[0:length-2]};
3647 
 
3648 
endmodule
3649 40 unneback 
`endif
3650 6 unneback 
 
3651 40 unneback 
`ifdef CNT_SHREG_CE_WRAP
3652 
`define MODULE cnt_shreg_ce_wrap
3653 
module `BASE`MODULE ( cke, q, rst, clk);
3654 
`undef MODULE
3655 6 unneback 
 
3656 
   parameter length = 4;
3657 
   input cke;
3658 
   output reg [0:length-1] q;
3659 
   input rst;
3660 
   input clk;
3661 
 
3662 
    always @ (posedge clk or posedge rst)
3663 
    if (rst)
3664 
        q <= {1'b1,{length-1{1'b0}}};
3665 
    else
3666 
        if (cke)
3667 
            q <= {q[length-1],q[0:length-2]};
3668 
 
3669 
endmodule
3670 40 unneback 
`endif
3671 6 unneback 
 
3672 40 unneback 
`ifdef CNT_SHREG_CE_CLEAR
3673 
`define MODULE cnt_shreg_ce_clear
3674 
module `BASE`MODULE ( cke, clear, q, rst, clk);
3675 
`undef MODULE
3676 6 unneback 
 
3677 
   parameter length = 4;
3678 
   input cke, clear;
3679 
   output reg [0:length-1] q;
3680 
   input rst;
3681 
   input clk;
3682 
 
3683 
    always @ (posedge clk or posedge rst)
3684 
    if (rst)
3685 
        q <= {1'b1,{length-1{1'b0}}};
3686 
    else
3687 
        if (cke)
3688 
            if (clear)
3689 
                q <= {1'b1,{length-1{1'b0}}};
3690 
            else
3691 
                q <= q >> 1;
3692 
 
3693 
endmodule
3694 40 unneback 
`endif
3695 6 unneback 
 
3696 40 unneback 
`ifdef CNT_SHREG_CE_CLEAR_WRAP
3697 
`define MODULE cnt_shreg_ce_clear_wrap
3698 
module `BASE`MODULE ( cke, clear, q, rst, clk);
3699 
`undef MODULE
3700 6 unneback 
 
3701 
   parameter length = 4;
3702 
   input cke, clear;
3703 
   output reg [0:length-1] q;
3704 
   input rst;
3705 
   input clk;
3706 
 
3707 
    always @ (posedge clk or posedge rst)
3708 
    if (rst)
3709 
        q <= {1'b1,{length-1{1'b0}}};
3710 
    else
3711 
        if (cke)
3712 
            if (clear)
3713 
                q <= {1'b1,{length-1{1'b0}}};
3714 
            else
3715 
            q <= {q[length-1],q[0:length-2]};
3716 
 
3717 
endmodule
3718 40 unneback 
`endif
3719 6 unneback 
//////////////////////////////////////////////////////////////////////
3720 
////                                                              ////
3721 
////  Versatile library, memories                                 ////
3722 
////                                                              ////
3723 
////  Description                                                 ////
3724 
////  memories                                                    ////
3725 
////                                                              ////
3726 
////                                                              ////
3727 
////  To Do:                                                      ////
3728 
////   - add more memory types                                    ////
3729 
////                                                              ////
3730 
////  Author(s):                                                  ////
3731 
////      - Michael Unneback, unneback@opencores.org              ////
3732 
////        ORSoC AB                                              ////
3733 
////                                                              ////
3734 
//////////////////////////////////////////////////////////////////////
3735 
////                                                              ////
3736 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
3737 
////                                                              ////
3738 
//// This source file may be used and distributed without         ////
3739 
//// restriction provided that this copyright statement is not    ////
3740 
//// removed from the file and that any derivative work contains  ////
3741 
//// the original copyright notice and the associated disclaimer. ////
3742 
////                                                              ////
3743 
//// This source file is free software; you can redistribute it   ////
3744 
//// and/or modify it under the terms of the GNU Lesser General   ////
3745 
//// Public License as published by the Free Software Foundation; ////
3746 
//// either version 2.1 of the License, or (at your option) any   ////
3747 
//// later version.                                               ////
3748 
////                                                              ////
3749 
//// This source is distributed in the hope that it will be       ////
3750 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3751 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3752 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3753 
//// details.                                                     ////
3754 
////                                                              ////
3755 
//// You should have received a copy of the GNU Lesser General    ////
3756 
//// Public License along with this source; if not, download it   ////
3757 
//// from http://www.opencores.org/lgpl.shtml                     ////
3758 
////                                                              ////
3759 
//////////////////////////////////////////////////////////////////////
3760 
 
3761 40 unneback 
`ifdef ROM_INIT
3762 6 unneback 
/// ROM
3763 40 unneback 
`define MODULE rom_init
3764 
module `BASE`MODULE ( adr, q, clk);
3765 
`undef MODULE
3766 6 unneback 
 
3767 7 unneback 
   parameter data_width = 32;
3768 
   parameter addr_width = 8;
3769 75 unneback 
   parameter mem_size = 1<<addr_width;
3770 7 unneback 
   input [(addr_width-1):0]       adr;
3771 
   output reg [(data_width-1):0] q;
3772 
   input                         clk;
3773 75 unneback 
   reg [data_width-1:0] rom [mem_size-1:0];
3774 7 unneback 
   parameter memory_file = "vl_rom.vmem";
3775 
   initial
3776 
     begin
3777 
        $readmemh(memory_file, rom);
3778 
     end
3779 
 
3780 
   always @ (posedge clk)
3781 
     q <= rom[adr];
3782 6 unneback 
 
3783 7 unneback 
endmodule
3784 40 unneback 
`endif
3785 7 unneback 
 
3786 40 unneback 
`ifdef RAM
3787 
`define MODULE ram
3788 6 unneback 
// Single port RAM
3789 40 unneback 
module `BASE`MODULE ( d, adr, we, q, clk);
3790 
`undef MODULE
3791 6 unneback 
 
3792 
   parameter data_width = 32;
3793 
   parameter addr_width = 8;
3794 75 unneback 
   parameter mem_size = 1<<addr_width;
3795 100 unneback 
   parameter debug = 0;
3796 6 unneback 
   input [(data_width-1):0]      d;
3797 
   input [(addr_width-1):0]       adr;
3798 
   input                         we;
3799 7 unneback 
   output reg [(data_width-1):0] q;
3800 6 unneback 
   input                         clk;
3801 98 unneback 
   reg [data_width-1:0] ram [mem_size-1:0];
3802 100 unneback 
 
3803 
    parameter memory_init = 0;
3804 
    parameter memory_file = "vl_ram.vmem";
3805 
    generate
3806 
    if (memory_init == 1) begin : init_mem
3807 
        initial
3808 
            $readmemh(memory_file, ram);
3809 
   end else if (memory_init == 2) begin : init_zero
3810 
        integer k;
3811 
        initial
3812 
            for (k = 0; k < mem_size; k = k + 1)
3813 
                ram[k] = 0;
3814 7 unneback 
   end
3815 
   endgenerate
3816 
 
3817 100 unneback 
    generate
3818 
    if (debug==1) begin : debug_we
3819 
        always @ (posedge clk)
3820 
        if (we)
3821 
            $display ("Value %h written at address %h : time %t", d, adr, $time);
3822 
 
3823 
    end
3824 
    endgenerate
3825 
 
3826 6 unneback 
   always @ (posedge clk)
3827 
   begin
3828 
   if (we)
3829 
     ram[adr] <= d;
3830 
   q <= ram[adr];
3831 
   end
3832 
 
3833 
endmodule
3834 40 unneback 
`endif
3835 6 unneback 
 
3836 40 unneback 
`ifdef RAM_BE
3837 
`define MODULE ram_be
3838 91 unneback 
module `BASE`MODULE ( d, adr, be, we, q, clk);
3839 40 unneback 
`undef MODULE
3840 
 
3841 7 unneback 
   parameter data_width = 32;
3842 72 unneback 
   parameter addr_width = 6;
3843 75 unneback 
   parameter mem_size = 1<<addr_width;
3844 7 unneback 
   input [(data_width-1):0]      d;
3845 
   input [(addr_width-1):0]       adr;
3846 73 unneback 
   input [(data_width/8)-1:0]    be;
3847 7 unneback 
   input                         we;
3848 
   output reg [(data_width-1):0] q;
3849 
   input                         clk;
3850 
 
3851 85 unneback 
 
3852 65 unneback 
`ifdef SYSTEMVERILOG
3853 95 unneback 
    // use a multi-dimensional packed array
3854 
    //t o model individual bytes within the word
3855 
    logic [data_width/8-1:0][7:0] ram [0:mem_size-1];// # words = 1 << address width
3856 65 unneback 
`else
3857 85 unneback 
    reg [data_width-1:0] ram [mem_size-1:0];
3858 
    wire [data_width/8-1:0] cke;
3859 65 unneback 
`endif
3860 
 
3861 100 unneback 
    parameter memory_init = 0;
3862 
    parameter memory_file = "vl_ram.vmem";
3863 
    generate
3864 
    if (memory_init == 1) begin : init_mem
3865 
        initial
3866 
            $readmemh(memory_file, ram);
3867 
    end else if (memory_init == 2) begin : init_zero
3868 
        integer k;
3869 
        initial
3870 
            for (k = 0; k < mem_size; k = k + 1)
3871 
                ram[k] = 0;
3872 
    end
3873 7 unneback 
   endgenerate
3874 
 
3875 60 unneback 
`ifdef SYSTEMVERILOG
3876 
 
3877 
always_ff@(posedge clk)
3878 
begin
3879 95 unneback 
    if(we) begin
3880 86 unneback 
        if(be[3]) ram[adr][3] <= d[31:24];
3881 
        if(be[2]) ram[adr][2] <= d[23:16];
3882 
        if(be[1]) ram[adr][1] <= d[15:8];
3883 
        if(be[0]) ram[adr][0] <= d[7:0];
3884 60 unneback 
    end
3885 90 unneback 
        q <= ram[adr];
3886 60 unneback 
end
3887 
 
3888 
`else
3889 
 
3890 85 unneback 
assign cke = {data_width/8{we}} & be;
3891 7 unneback 
   genvar i;
3892 85 unneback 
   generate for (i=0;i<data_width/8;i=i+1) begin : be_ram
3893 7 unneback 
      always @ (posedge clk)
3894 85 unneback 
      if (cke[i])
3895 7 unneback 
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
3896 
   end
3897 
   endgenerate
3898 
 
3899 
   always @ (posedge clk)
3900 
      q <= ram[adr];
3901 
 
3902 60 unneback 
`endif
3903 
 
3904 93 unneback 
`ifdef verilator
3905 85 unneback 
   // Function to access RAM (for use by Verilator).
3906 
   function [31:0] get_mem;
3907 
      // verilator public
3908 90 unneback 
      input [addr_width-1:0]             addr;
3909 85 unneback 
      get_mem = ram[addr];
3910 
   endfunction // get_mem
3911 
 
3912 
   // Function to write RAM (for use by Verilator).
3913 
   function set_mem;
3914 
      // verilator public
3915 90 unneback 
      input [addr_width-1:0]             addr;
3916 
      input [data_width-1:0]             data;
3917 85 unneback 
      ram[addr] = data;
3918 
   endfunction // set_mem
3919 93 unneback 
`endif
3920 85 unneback 
 
3921 7 unneback 
endmodule
3922 40 unneback 
`endif
3923 7 unneback 
 
3924 40 unneback 
`ifdef DPRAM_1R1W
3925 
`define MODULE dpram_1r1w
3926 
module `BASE`MODULE ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
3927 
`undef MODULE
3928 6 unneback 
   parameter data_width = 32;
3929 
   parameter addr_width = 8;
3930 75 unneback 
   parameter mem_size = 1<<addr_width;
3931 6 unneback 
   input [(data_width-1):0]      d_a;
3932 
   input [(addr_width-1):0]       adr_a;
3933 
   input [(addr_width-1):0]       adr_b;
3934 
   input                         we_a;
3935 
   output [(data_width-1):0]      q_b;
3936 
   input                         clk_a, clk_b;
3937 
   reg [(addr_width-1):0]         adr_b_reg;
3938 100 unneback 
   reg [data_width-1:0] ram [mem_size-1:0] `SYN_NO_RW_CHECK;
3939 7 unneback 
 
3940 100 unneback 
    parameter memory_init = 0;
3941 
    parameter memory_file = "vl_ram.vmem";
3942 
    parameter debug = 0;
3943 
 
3944 
    generate
3945 
    if (memory_init == 1) begin : init_mem
3946 
        initial
3947 
            $readmemh(memory_file, ram);
3948 
    end else if (memory_init == 2) begin : init_zero
3949 
        integer k;
3950 
        initial
3951 
            for (k = 0; k < mem_size; k = k + 1)
3952 
                ram[k] = 0;
3953 
    end
3954 7 unneback 
   endgenerate
3955 
 
3956 100 unneback 
    generate
3957 
    if (debug==1) begin : debug_we
3958 
        always @ (posedge clk_a)
3959 
        if (we_a)
3960 
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
3961 
 
3962 
    end
3963 
    endgenerate
3964 
 
3965 6 unneback 
   always @ (posedge clk_a)
3966 
   if (we_a)
3967 
     ram[adr_a] <= d_a;
3968 
   always @ (posedge clk_b)
3969 
   adr_b_reg <= adr_b;
3970 
   assign q_b = ram[adr_b_reg];
3971 40 unneback 
 
3972 6 unneback 
endmodule
3973 40 unneback 
`endif
3974 6 unneback 
 
3975 40 unneback 
`ifdef DPRAM_2R1W
3976 
`define MODULE dpram_2r1w
3977 
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
3978 
`undef MODULE
3979 
 
3980 6 unneback 
   parameter data_width = 32;
3981 
   parameter addr_width = 8;
3982 75 unneback 
   parameter mem_size = 1<<addr_width;
3983 6 unneback 
   input [(data_width-1):0]      d_a;
3984 
   input [(addr_width-1):0]       adr_a;
3985 
   input [(addr_width-1):0]       adr_b;
3986 
   input                         we_a;
3987 
   output [(data_width-1):0]      q_b;
3988 
   output reg [(data_width-1):0] q_a;
3989 
   input                         clk_a, clk_b;
3990 
   reg [(data_width-1):0]         q_b;
3991 98 unneback 
   reg [data_width-1:0] ram [mem_szie-1:0] `SYN_NO_RW_CHECK;
3992 7 unneback 
 
3993 100 unneback 
    parameter memory_init = 0;
3994 
    parameter memory_file = "vl_ram.vmem";
3995 
    parameter debug = 0;
3996 
 
3997 
    generate
3998 
    if (memory_init == 1) begin : init_mem
3999 
        initial
4000 
            $readmemh(memory_file, ram);
4001 
    end else if (memory_init == 2) begin : init_zero
4002 
        integer k;
4003 
        initial
4004 
            for (k = 0; k < mem_size; k = k + 1)
4005 
                ram[k] = 0;
4006 
    end
4007 7 unneback 
   endgenerate
4008 
 
4009 100 unneback 
    generate
4010 
    if (debug==1) begin : debug_we
4011 
        always @ (posedge clk_a)
4012 
        if (we_a)
4013 
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
4014 
 
4015 
    end
4016 
    endgenerate
4017 
 
4018 6 unneback 
   always @ (posedge clk_a)
4019 
     begin
4020 
        q_a <= ram[adr_a];
4021 
        if (we_a)
4022 
             ram[adr_a] <= d_a;
4023 
     end
4024 
   always @ (posedge clk_b)
4025 
          q_b <= ram[adr_b];
4026 
endmodule
4027 40 unneback 
`endif
4028 6 unneback 
 
4029 100 unneback 
`ifdef DPRAM_1R2W
4030 
`define MODULE dpram_1r2w
4031 
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, adr_b, we_b, clk_b );
4032 
`undef MODULE
4033 
 
4034 
   parameter data_width = 32;
4035 
   parameter addr_width = 8;
4036 
   parameter mem_size = 1<<addr_width;
4037 
   input [(data_width-1):0]      d_a;
4038 
   input [(addr_width-1):0]       adr_a;
4039 
   input [(addr_width-1):0]       adr_b;
4040 
   input                         we_a;
4041 
   input [(data_width-1):0]       d_b;
4042 
   output reg [(data_width-1):0] q_a;
4043 
   input                         we_b;
4044 
   input                         clk_a, clk_b;
4045 
   reg [(data_width-1):0]         q_b;
4046 
   reg [data_width-1:0] ram [mem_size-1:0] `SYN_NO_RW_CHECK;
4047 
 
4048 
    parameter memory_init = 0;
4049 
    parameter memory_file = "vl_ram.vmem";
4050 
    parameter debug = 0;
4051 
 
4052 
    generate
4053 
    if (memory_init == 1) begin : init_mem
4054 
        initial
4055 
            $readmemh(memory_file, ram);
4056 
    end else if (memory_init == 2) begin : init_zero
4057 
        integer k;
4058 
        initial
4059 
            for (k = 0; k < mem_size; k = k + 1)
4060 
                ram[k] = 0;
4061 
    end
4062 
   endgenerate
4063 
 
4064 
    generate
4065 
    if (debug==1) begin : debug_we
4066 
        always @ (posedge clk_a)
4067 
        if (we_a)
4068 
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
4069 
        always @ (posedge clk_b)
4070 
        if (we_b)
4071 
            $display ("Debug: Value %h written at address %h : time %t", d_b, adr_b, $time);
4072 
    end
4073 
    endgenerate
4074 
 
4075 
   always @ (posedge clk_a)
4076 
     begin
4077 
        q_a <= ram[adr_a];
4078 
        if (we_a)
4079 
             ram[adr_a] <= d_a;
4080 
     end
4081 
   always @ (posedge clk_b)
4082 
     begin
4083 
        if (we_b)
4084 
          ram[adr_b] <= d_b;
4085 
     end
4086 
endmodule
4087 
`endif
4088 
 
4089 40 unneback 
`ifdef DPRAM_2R2W
4090 
`define MODULE dpram_2r2w
4091 
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
4092 
`undef MODULE
4093 
 
4094 6 unneback 
   parameter data_width = 32;
4095 
   parameter addr_width = 8;
4096 75 unneback 
   parameter mem_size = 1<<addr_width;
4097 6 unneback 
   input [(data_width-1):0]      d_a;
4098 
   input [(addr_width-1):0]       adr_a;
4099 
   input [(addr_width-1):0]       adr_b;
4100 
   input                         we_a;
4101 
   output [(data_width-1):0]      q_b;
4102 
   input [(data_width-1):0]       d_b;
4103 
   output reg [(data_width-1):0] q_a;
4104 
   input                         we_b;
4105 
   input                         clk_a, clk_b;
4106 
   reg [(data_width-1):0]         q_b;
4107 98 unneback 
   reg [data_width-1:0] ram [mem_size-1:0] `SYN_NO_RW_CHECK;
4108 7 unneback 
 
4109 100 unneback 
    parameter memory_init = 0;
4110 
    parameter memory_file = "vl_ram.vmem";
4111 
    parameter debug = 0;
4112 
 
4113 
    generate
4114 
    if (memory_init) begin : init_mem
4115 
        initial
4116 
            $readmemh(memory_file, ram);
4117 
    end else if (memory_init == 2) begin : init_zero
4118 
        integer k;
4119 
        initial
4120 
            for (k = 0; k < mem_size; k = k + 1)
4121 
                ram[k] = 0;
4122 
    end
4123 7 unneback 
   endgenerate
4124 
 
4125 100 unneback 
    generate
4126 
    if (debug==1) begin : debug_we
4127 
        always @ (posedge clk_a)
4128 
        if (we_a)
4129 
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
4130 
        always @ (posedge clk_b)
4131 
        if (we_b)
4132 
            $display ("Debug: Value %h written at address %h : time %t", d_b, adr_b, $time);
4133 
    end
4134 
    endgenerate
4135 
 
4136 6 unneback 
   always @ (posedge clk_a)
4137 
     begin
4138 
        q_a <= ram[adr_a];
4139 
        if (we_a)
4140 
             ram[adr_a] <= d_a;
4141 
     end
4142 
   always @ (posedge clk_b)
4143 
     begin
4144 
        q_b <= ram[adr_b];
4145 
        if (we_b)
4146 
          ram[adr_b] <= d_b;
4147 
     end
4148 
endmodule
4149 40 unneback 
`endif
4150 6 unneback 
 
4151 83 unneback 
 
4152 75 unneback 
`ifdef DPRAM_BE_2R2W
4153 
`define MODULE dpram_be_2r2w
4154 92 unneback 
module `BASE`MODULE ( d_a, q_a, adr_a, be_a, we_a, clk_a, d_b, q_b, adr_b, be_b, we_b, clk_b );
4155 75 unneback 
`undef MODULE
4156 
 
4157 
   parameter a_data_width = 32;
4158 
   parameter a_addr_width = 8;
4159 95 unneback 
   parameter b_data_width = 64; //a_data_width;
4160 91 unneback 
   localparam b_addr_width = a_data_width * a_addr_width / b_data_width;
4161 95 unneback 
   localparam ratio = (a_addr_width>b_addr_width) ? (a_addr_width/b_addr_width) : (b_addr_width/a_addr_width);
4162 
   parameter mem_size = (a_addr_width>b_addr_width) ? (1<<b_addr_width) : (1<<a_addr_width);
4163 91 unneback 
 
4164 100 unneback 
   parameter memory_init = 0;
4165 95 unneback 
   parameter memory_file = "vl_ram.vmem";
4166 100 unneback 
   parameter debug = 0;
4167 95 unneback 
 
4168 75 unneback 
   input [(a_data_width-1):0]      d_a;
4169 91 unneback 
   input [(a_addr_width-1):0]       adr_a;
4170 
   input [(a_data_width/8-1):0]    be_a;
4171 
   input                           we_a;
4172 75 unneback 
   output reg [(a_data_width-1):0] q_a;
4173 91 unneback 
   input [(b_data_width-1):0]       d_b;
4174 
   input [(b_addr_width-1):0]       adr_b;
4175 92 unneback 
   input [(b_data_width/8-1):0]    be_b;
4176 
   input                           we_b;
4177 
   output reg [(b_data_width-1):0]          q_b;
4178 91 unneback 
   input                           clk_a, clk_b;
4179 75 unneback 
 
4180 100 unneback 
    generate
4181 
    if (debug==1) begin : debug_we
4182 
        always @ (posedge clk_a)
4183 
        if (we_a)
4184 
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
4185 
        always @ (posedge clk_b)
4186 
        if (we_b)
4187 
            $display ("Debug: Value %h written at address %h : time %t", d_b, adr_b, $time);
4188 
    end
4189 
    endgenerate
4190 
 
4191 
 
4192 91 unneback 
`ifdef SYSTEMVERILOG
4193 
// use a multi-dimensional packed array
4194 
//to model individual bytes within the word
4195 
 
4196 75 unneback 
generate
4197 91 unneback 
if (a_data_width==32 & b_data_width==32) begin : dpram_3232
4198 75 unneback 
 
4199 98 unneback 
    logic [0:3][7:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
4200 95 unneback 
 
4201 
    initial
4202 100 unneback 
        if (memory_init==1)
4203 95 unneback 
            $readmemh(memory_file, ram);
4204 100 unneback 
 
4205 
    integer k;
4206 
    initial
4207 
        if (memory_init==2)
4208 
            for (k = 0; k < mem_size; k = k + 1)
4209 
                ram[k] = 0;
4210 91 unneback 
 
4211 
    always_ff@(posedge clk_a)
4212 
    begin
4213 
        if(we_a) begin
4214 100 unneback 
            if(be_a[3]) ram[adr_a][0] <= d_a[31:24];
4215 
            if(be_a[2]) ram[adr_a][1] <= d_a[23:16];
4216 
            if(be_a[1]) ram[adr_a][2] <= d_a[15:8];
4217 
            if(be_a[0]) ram[adr_a][3] <= d_a[7:0];
4218 91 unneback 
        end
4219 
    end
4220 
 
4221 92 unneback 
    always@(posedge clk_a)
4222 
        q_a = ram[adr_a];
4223 91 unneback 
 
4224 
    always_ff@(posedge clk_b)
4225 92 unneback 
    begin
4226 
        if(we_b) begin
4227 100 unneback 
            if(be_b[3]) ram[adr_b][0] <= d_b[31:24];
4228 
            if(be_b[2]) ram[adr_b][1] <= d_b[23:16];
4229 
            if(be_b[1]) ram[adr_b][2] <= d_b[15:8];
4230 
            if(be_b[0]) ram[adr_b][3] <= d_b[7:0];
4231 92 unneback 
        end
4232 
    end
4233 91 unneback 
 
4234 92 unneback 
    always@(posedge clk_b)
4235 
        q_b = ram[adr_b];
4236 91 unneback 
 
4237 75 unneback 
end
4238 
endgenerate
4239 
 
4240 95 unneback 
generate
4241 
if (a_data_width==64 & b_data_width==64) begin : dpram_6464
4242 
 
4243 98 unneback 
    logic [0:7][7:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
4244 95 unneback 
 
4245 
    initial
4246 100 unneback 
        if (memory_init==1)
4247 95 unneback 
            $readmemh(memory_file, ram);
4248 100 unneback 
 
4249 
    integer k;
4250 
    initial
4251 
        if (memory_init==2)
4252 
            for (k = 0; k < mem_size; k = k + 1)
4253 
                ram[k] = 0;
4254 95 unneback 
 
4255 
    always_ff@(posedge clk_a)
4256 
    begin
4257 
        if(we_a) begin
4258 
            if(be_a[7]) ram[adr_a][7] <= d_a[63:56];
4259 
            if(be_a[6]) ram[adr_a][6] <= d_a[55:48];
4260 
            if(be_a[5]) ram[adr_a][5] <= d_a[47:40];
4261 
            if(be_a[4]) ram[adr_a][4] <= d_a[39:32];
4262 
            if(be_a[3]) ram[adr_a][3] <= d_a[31:24];
4263 
            if(be_a[2]) ram[adr_a][2] <= d_a[23:16];
4264 
            if(be_a[1]) ram[adr_a][1] <= d_a[15:8];
4265 
            if(be_a[0]) ram[adr_a][0] <= d_a[7:0];
4266 
        end
4267 
    end
4268 
 
4269 
    always@(posedge clk_a)
4270 
        q_a = ram[adr_a];
4271 
 
4272 
    always_ff@(posedge clk_b)
4273 
    begin
4274 
        if(we_b) begin
4275 
            if(be_b[7]) ram[adr_b][7] <= d_b[63:56];
4276 
            if(be_b[6]) ram[adr_b][6] <= d_b[55:48];
4277 
            if(be_b[5]) ram[adr_b][5] <= d_b[47:40];
4278 
            if(be_b[4]) ram[adr_b][4] <= d_b[39:32];
4279 
            if(be_b[3]) ram[adr_b][3] <= d_b[31:24];
4280 
            if(be_b[2]) ram[adr_b][2] <= d_b[23:16];
4281 
            if(be_b[1]) ram[adr_b][1] <= d_b[15:8];
4282 
            if(be_b[0]) ram[adr_b][0] <= d_b[7:0];
4283 
        end
4284 
    end
4285 
 
4286 
    always@(posedge clk_b)
4287 
        q_b = ram[adr_b];
4288 
 
4289 
end
4290 
endgenerate
4291 
 
4292 
generate
4293 
if (a_data_width==32 & b_data_width==16) begin : dpram_3216
4294 
logic [31:0] temp;
4295 
`define MODULE dpram_be_2r2w
4296 100 unneback 
`BASE`MODULE # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .init(memory_init), .memory_file(memory_file))
4297 95 unneback 
`undef MODULE
4298 
dpram6464 (
4299 
    .d_a(d_a),
4300 
    .q_a(q_a),
4301 
    .adr_a(adr_a),
4302 
    .be_a(be_a),
4303 
    .we_a(we_a),
4304 
    .clk_a(clk_a),
4305 
    .d_b({d_b,d_b}),
4306 
    .q_b(temp),
4307 
    .adr_b(adr_b),
4308 
    .be_b({be_b,be_b} & {{2{adr_b[0]}},{2{!adr_b[0]}}}),
4309 
    .we_b(we_b),
4310 
    .clk_b(clk_b)
4311 
);
4312 
 
4313 100 unneback 
always @ (adr_b[0] or temp)
4314 95 unneback 
    if (adr_b[0])
4315 
        q_b = temp[31:16];
4316 
    else
4317 
        q_b = temp[15:0];
4318 
 
4319 
end
4320 
endgenerate
4321 
 
4322 
generate
4323 
if (a_data_width==32 & b_data_width==64) begin : dpram_3264
4324 
logic [63:0] temp;
4325 
`define MODULE dpram_be_2r2w
4326 100 unneback 
`BASE`MODULE # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .init(memory_init), .memory_file(memory_file))
4327 95 unneback 
`undef MODULE
4328 
dpram6464 (
4329 
    .d_a({d_a,d_a}),
4330 
    .q_a(temp),
4331 
    .adr_a(adr_a[a_addr_width-1:1]),
4332 
    .be_a({be_a,be_a} & {{4{adr_a[0]}},{4{!adr_a[0]}}}),
4333 
    .we_a(we_a),
4334 
    .clk_a(clk_a),
4335 
    .d_b(d_b),
4336 
    .q_b(q_b),
4337 
    .adr_b(adr_b),
4338 
    .be_b(be_b),
4339 
    .we_b(we_b),
4340 
    .clk_b(clk_b)
4341 
);
4342 
 
4343 100 unneback 
always @ (adr_a[0] or temp)
4344 95 unneback 
    if (adr_a[0])
4345 
        q_a = temp[63:32];
4346 
    else
4347 
        q_a = temp[31:0];
4348 
 
4349 
end
4350 
endgenerate
4351 
 
4352 91 unneback 
`else
4353 92 unneback 
    // This modules requires SystemVerilog
4354 98 unneback 
    // at this point anyway
4355 91 unneback 
`endif
4356 75 unneback 
endmodule
4357 
`endif
4358 
 
4359 91 unneback 
`ifdef CAM
4360 6 unneback 
// Content addresable memory, CAM
4361 91 unneback 
`endif
4362 6 unneback 
 
4363 40 unneback 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
4364 6 unneback 
// FIFO
4365 40 unneback 
`define MODULE fifo_1r1w_fill_level_sync
4366 
module `BASE`MODULE (
4367 
`undef MODULE
4368 25 unneback 
    d, wr, fifo_full,
4369 
    q, rd, fifo_empty,
4370 
    fill_level,
4371 
    clk, rst
4372 
    );
4373 
 
4374 
parameter data_width = 18;
4375 
parameter addr_width = 4;
4376 6 unneback 
 
4377 25 unneback 
// write side
4378 
input  [data_width-1:0] d;
4379 
input                   wr;
4380 
output                  fifo_full;
4381 
// read side
4382 
output [data_width-1:0] q;
4383 
input                   rd;
4384 
output                  fifo_empty;
4385 
// common
4386 
output [addr_width:0]   fill_level;
4387 
input rst, clk;
4388 
 
4389 
wire [addr_width:1] wadr, radr;
4390 
 
4391 40 unneback 
`define MODULE cnt_bin_ce
4392 
`BASE`MODULE
4393 25 unneback 
    # ( .length(addr_width))
4394 
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
4395 40 unneback 
`BASE`MODULE
4396 25 unneback 
    # (.length(addr_width))
4397 
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
4398 40 unneback 
`undef MODULE
4399 25 unneback 
 
4400 40 unneback 
`define MODULE dpram_1r1w
4401 
`BASE`MODULE
4402 25 unneback 
    # (.data_width(data_width), .addr_width(addr_width))
4403 
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
4404 40 unneback 
`undef MODULE
4405 25 unneback 
 
4406 40 unneback 
`define MODULE cnt_bin_ce_rew_q_zq_l1
4407 
`BASE`MODULE
4408 27 unneback 
    # (.length(addr_width+1), .level1_value(1<<addr_width))
4409 25 unneback 
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
4410 40 unneback 
`undef MODULE
4411 25 unneback 
endmodule
4412 40 unneback 
`endif
4413 25 unneback 
 
4414 40 unneback 
`ifdef FIFO_2R2W_SYNC_SIMPLEX
4415 27 unneback 
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
4416 
// RAM is supposed to be larger than the two FIFOs
4417 
// LFSR counters used adr pointers
4418 40 unneback 
`define MODULE fifo_2r2w_sync_simplex
4419 
module `BASE`MODULE (
4420 
`undef MODULE
4421 27 unneback 
    // a side
4422 
    a_d, a_wr, a_fifo_full,
4423 
    a_q, a_rd, a_fifo_empty,
4424 
    a_fill_level,
4425 
    // b side
4426 
    b_d, b_wr, b_fifo_full,
4427 
    b_q, b_rd, b_fifo_empty,
4428 
    b_fill_level,
4429 
    // common
4430 
    clk, rst
4431 
    );
4432 
parameter data_width = 8;
4433 
parameter addr_width = 5;
4434 
parameter fifo_full_level = (1<<addr_width)-1;
4435 
 
4436 
// a side
4437 
input  [data_width-1:0] a_d;
4438 
input                   a_wr;
4439 
output                  a_fifo_full;
4440 
output [data_width-1:0] a_q;
4441 
input                   a_rd;
4442 
output                  a_fifo_empty;
4443 
output [addr_width-1:0] a_fill_level;
4444 
 
4445 
// b side
4446 
input  [data_width-1:0] b_d;
4447 
input                   b_wr;
4448 
output                  b_fifo_full;
4449 
output [data_width-1:0] b_q;
4450 
input                   b_rd;
4451 
output                  b_fifo_empty;
4452 
output [addr_width-1:0] b_fill_level;
4453 
 
4454 
input                   clk;
4455 
input                   rst;
4456 
 
4457 
// adr_gen
4458 
wire [addr_width:1] a_wadr, a_radr;
4459 
wire [addr_width:1] b_wadr, b_radr;
4460 
// dpram
4461 
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
4462 
 
4463 40 unneback 
`define MODULE cnt_lfsr_ce
4464 
`BASE`MODULE
4465 27 unneback 
    # ( .length(addr_width))
4466 
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
4467 
 
4468 40 unneback 
`BASE`MODULE
4469 27 unneback 
    # (.length(addr_width))
4470 
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
4471 
 
4472 40 unneback 
`BASE`MODULE
4473 27 unneback 
    # ( .length(addr_width))
4474 
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
4475 
 
4476 40 unneback 
`BASE`MODULE
4477 27 unneback 
    # (.length(addr_width))
4478 
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
4479 40 unneback 
`undef MODULE
4480 27 unneback 
 
4481 
// mux read or write adr to DPRAM
4482 
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
4483 
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
4484 
 
4485 40 unneback 
`define MODULE dpram_2r2w
4486 
`BASE`MODULE
4487 27 unneback 
    # (.data_width(data_width), .addr_width(addr_width+1))
4488 
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
4489 
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
4490 40 unneback 
`undef MODULE
4491 
 
4492 
`define MODULE cnt_bin_ce_rew_zq_l1
4493 
`BASE`MODULE
4494 28 unneback 
    # (.length(addr_width), .level1_value(fifo_full_level))
4495 27 unneback 
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
4496 
 
4497 40 unneback 
`BASE`MODULE
4498 28 unneback 
    # (.length(addr_width), .level1_value(fifo_full_level))
4499 27 unneback 
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
4500 40 unneback 
`undef MODULE
4501 27 unneback 
 
4502 
endmodule
4503 40 unneback 
`endif
4504 27 unneback 
 
4505 40 unneback 
`ifdef FIFO_CMP_ASYNC
4506 
`define MODULE fifo_cmp_async
4507 
module `BASE`MODULE ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
4508 
`undef MODULE
4509 6 unneback 
 
4510 11 unneback 
   parameter addr_width = 4;
4511 
   parameter N = addr_width-1;
4512 6 unneback 
 
4513 
   parameter Q1 = 2'b00;
4514 
   parameter Q2 = 2'b01;
4515 
   parameter Q3 = 2'b11;
4516 
   parameter Q4 = 2'b10;
4517 
 
4518 
   parameter going_empty = 1'b0;
4519 
   parameter going_full  = 1'b1;
4520 
 
4521 
   input [N:0]  wptr, rptr;
4522 14 unneback 
   output       fifo_empty;
4523 6 unneback 
   output       fifo_full;
4524 
   input        wclk, rclk, rst;
4525 
 
4526 
`ifndef GENERATE_DIRECTION_AS_LATCH
4527 
   wire direction;
4528 
`endif
4529 
`ifdef GENERATE_DIRECTION_AS_LATCH
4530 
   reg direction;
4531 
`endif
4532 
   reg  direction_set, direction_clr;
4533 
 
4534 
   wire async_empty, async_full;
4535 
   wire fifo_full2;
4536 14 unneback 
   wire fifo_empty2;
4537 6 unneback 
 
4538 
   // direction_set
4539 
   always @ (wptr[N:N-1] or rptr[N:N-1])
4540 
     case ({wptr[N:N-1],rptr[N:N-1]})
4541 
       {Q1,Q2} : direction_set <= 1'b1;
4542 
       {Q2,Q3} : direction_set <= 1'b1;
4543 
       {Q3,Q4} : direction_set <= 1'b1;
4544 
       {Q4,Q1} : direction_set <= 1'b1;
4545 
       default : direction_set <= 1'b0;
4546 
     endcase
4547 
 
4548 
   // direction_clear
4549 
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
4550 
     if (rst)
4551 
       direction_clr <= 1'b1;
4552 
     else
4553 
       case ({wptr[N:N-1],rptr[N:N-1]})
4554 
         {Q2,Q1} : direction_clr <= 1'b1;
4555 
         {Q3,Q2} : direction_clr <= 1'b1;
4556 
         {Q4,Q3} : direction_clr <= 1'b1;
4557 
         {Q1,Q4} : direction_clr <= 1'b1;
4558 
         default : direction_clr <= 1'b0;
4559 
       endcase
4560 
 
4561 40 unneback 
`define MODULE dff_sr
4562 6 unneback 
`ifndef GENERATE_DIRECTION_AS_LATCH
4563 40 unneback 
    `BASE`MODULE dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
4564 6 unneback 
`endif
4565 
 
4566 
`ifdef GENERATE_DIRECTION_AS_LATCH
4567 
   always @ (posedge direction_set or posedge direction_clr)
4568 
     if (direction_clr)
4569 
       direction <= going_empty;
4570 
     else
4571 
       direction <= going_full;
4572 
`endif
4573 
 
4574 
   assign async_empty = (wptr == rptr) && (direction==going_empty);
4575 
   assign async_full  = (wptr == rptr) && (direction==going_full);
4576 
 
4577 40 unneback 
    `BASE`MODULE dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
4578 
    `BASE`MODULE dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
4579 
`undef MODULE
4580 6 unneback 
 
4581 
/*
4582 
   always @ (posedge wclk or posedge rst or posedge async_full)
4583 
     if (rst)
4584 
       {fifo_full, fifo_full2} <= 2'b00;
4585 
     else if (async_full)
4586 
       {fifo_full, fifo_full2} <= 2'b11;
4587 
     else
4588 
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
4589 
*/
4590 14 unneback 
/*   always @ (posedge rclk or posedge async_empty)
4591 6 unneback 
     if (async_empty)
4592 
       {fifo_empty, fifo_empty2} <= 2'b11;
4593 
     else
4594 14 unneback 
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
4595 40 unneback 
`define MODULE dff
4596 
    `BASE`MODULE # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
4597 
    `BASE`MODULE # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
4598 
`undef MODULE
4599 27 unneback 
endmodule // async_compb
4600 40 unneback 
`endif
4601 6 unneback 
 
4602 40 unneback 
`ifdef FIFO_1R1W_ASYNC
4603 
`define MODULE fifo_1r1w_async
4604 
module `BASE`MODULE (
4605 
`undef MODULE
4606 6 unneback 
    d, wr, fifo_full, wr_clk, wr_rst,
4607 
    q, rd, fifo_empty, rd_clk, rd_rst
4608 
    );
4609 
 
4610 
parameter data_width = 18;
4611 
parameter addr_width = 4;
4612 
 
4613 
// write side
4614 
input  [data_width-1:0] d;
4615 
input                   wr;
4616 
output                  fifo_full;
4617 
input                   wr_clk;
4618 
input                   wr_rst;
4619 
// read side
4620 
output [data_width-1:0] q;
4621 
input                   rd;
4622 
output                  fifo_empty;
4623 
input                   rd_clk;
4624 
input                   rd_rst;
4625 
 
4626 
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
4627 23 unneback 
 
4628 40 unneback 
`define MODULE cnt_gray_ce_bin
4629 
`BASE`MODULE
4630 6 unneback 
    # ( .length(addr_width))
4631 
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
4632 
 
4633 40 unneback 
`BASE`MODULE
4634 6 unneback 
    # (.length(addr_width))
4635 23 unneback 
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
4636 40 unneback 
`undef MODULE
4637 6 unneback 
 
4638 40 unneback 
`define MODULE dpram_1r1w
4639 
`BASE`MODULE
4640 6 unneback 
    # (.data_width(data_width), .addr_width(addr_width))
4641 
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
4642 40 unneback 
`undef MODULE
4643 6 unneback 
 
4644 40 unneback 
`define MODULE fifo_cmp_async
4645 
`BASE`MODULE
4646 6 unneback 
    # (.addr_width(addr_width))
4647 
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
4648 40 unneback 
`undef MODULE
4649 6 unneback 
 
4650 
endmodule
4651 40 unneback 
`endif
4652 6 unneback 
 
4653 40 unneback 
`ifdef FIFO_2R2W_ASYNC
4654 
`define MODULE fifo_2r2w_async
4655 
module `BASE`MODULE (
4656 
`undef MODULE
4657 6 unneback 
    // a side
4658 
    a_d, a_wr, a_fifo_full,
4659 
    a_q, a_rd, a_fifo_empty,
4660 
    a_clk, a_rst,
4661 
    // b side
4662 
    b_d, b_wr, b_fifo_full,
4663 
    b_q, b_rd, b_fifo_empty,
4664 
    b_clk, b_rst
4665 
    );
4666 
 
4667 
parameter data_width = 18;
4668 
parameter addr_width = 4;
4669 
 
4670 
// a side
4671 
input  [data_width-1:0] a_d;
4672 
input                   a_wr;
4673 
output                  a_fifo_full;
4674 
output [data_width-1:0] a_q;
4675 
input                   a_rd;
4676 
output                  a_fifo_empty;
4677 
input                   a_clk;
4678 
input                   a_rst;
4679 
 
4680 
// b side
4681 
input  [data_width-1:0] b_d;
4682 
input                   b_wr;
4683 
output                  b_fifo_full;
4684 
output [data_width-1:0] b_q;
4685 
input                   b_rd;
4686 
output                  b_fifo_empty;
4687 
input                   b_clk;
4688 
input                   b_rst;
4689 
 
4690 40 unneback 
`define MODULE fifo_1r1w_async
4691 
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
4692 6 unneback 
vl_fifo_1r1w_async_a (
4693 
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
4694 
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
4695 
    );
4696 
 
4697 40 unneback 
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
4698 6 unneback 
vl_fifo_1r1w_async_b (
4699 
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
4700 
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
4701 
    );
4702 40 unneback 
`undef MODULE
4703 
 
4704 6 unneback 
endmodule
4705 40 unneback 
`endif
4706 6 unneback 
 
4707 40 unneback 
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
4708 
`define MODULE fifo_2r2w_async_simplex
4709 
module `BASE`MODULE (
4710 
`undef MODULE
4711 6 unneback 
    // a side
4712 
    a_d, a_wr, a_fifo_full,
4713 
    a_q, a_rd, a_fifo_empty,
4714 
    a_clk, a_rst,
4715 
    // b side
4716 
    b_d, b_wr, b_fifo_full,
4717 
    b_q, b_rd, b_fifo_empty,
4718 
    b_clk, b_rst
4719 
    );
4720 
 
4721 
parameter data_width = 18;
4722 
parameter addr_width = 4;
4723 
 
4724 
// a side
4725 
input  [data_width-1:0] a_d;
4726 
input                   a_wr;
4727 
output                  a_fifo_full;
4728 
output [data_width-1:0] a_q;
4729 
input                   a_rd;
4730 
output                  a_fifo_empty;
4731 
input                   a_clk;
4732 
input                   a_rst;
4733 
 
4734 
// b side
4735 
input  [data_width-1:0] b_d;
4736 
input                   b_wr;
4737 
output                  b_fifo_full;
4738 
output [data_width-1:0] b_q;
4739 
input                   b_rd;
4740 
output                  b_fifo_empty;
4741 
input                   b_clk;
4742 
input                   b_rst;
4743 
 
4744 
// adr_gen
4745 
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
4746 
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
4747 
// dpram
4748 
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
4749 
 
4750 40 unneback 
`define MODULE cnt_gray_ce_bin
4751 
`BASE`MODULE
4752 6 unneback 
    # ( .length(addr_width))
4753 
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
4754 
 
4755 40 unneback 
`BASE`MODULE
4756 6 unneback 
    # (.length(addr_width))
4757 
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
4758 
 
4759 40 unneback 
`BASE`MODULE
4760 6 unneback 
    # ( .length(addr_width))
4761 
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
4762 
 
4763 40 unneback 
`BASE`MODULE
4764 6 unneback 
    # (.length(addr_width))
4765 
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
4766 40 unneback 
`undef MODULE
4767 6 unneback 
 
4768 
// mux read or write adr to DPRAM
4769 
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
4770 
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
4771 
 
4772 40 unneback 
`define MODULE dpram_2r2w
4773 
`BASE`MODULE
4774 6 unneback 
    # (.data_width(data_width), .addr_width(addr_width+1))
4775 
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
4776 
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
4777 40 unneback 
`undef MODULE
4778 6 unneback 
 
4779 40 unneback 
`define MODULE fifo_cmp_async
4780 
`BASE`MODULE
4781 6 unneback 
    # (.addr_width(addr_width))
4782 
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
4783 
 
4784 40 unneback 
`BASE`MODULE
4785 6 unneback 
    # (.addr_width(addr_width))
4786 
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
4787 40 unneback 
`undef MODULE
4788 6 unneback 
 
4789 
endmodule
4790 40 unneback 
`endif
4791 48 unneback 
 
4792 
`ifdef REG_FILE
4793 
`define MODULE reg_file
4794 
module `BASE`MODULE (
4795 
`undef MODULE
4796 
    a1, a2, a3, wd3, we3, rd1, rd2, clk
4797 
);
4798 
parameter data_width = 32;
4799 
parameter addr_width = 5;
4800 
input [addr_width-1:0] a1, a2, a3;
4801 
input [data_width-1:0] wd3;
4802 
input we3;
4803 
output [data_width-1:0] rd1, rd2;
4804 
input clk;
4805 
 
4806 
`ifdef ACTEL
4807 
reg [data_width-1:0] wd3_reg;
4808 
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
4809 
reg we3_reg;
4810 98 unneback 
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] `SYN_NO_RW_CHECK;
4811 
reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] `SYN_NO_RW_CHECK;
4812 48 unneback 
always @ (posedge clk or posedge rst)
4813 
if (rst)
4814 
    {wd3_reg, a3_reg, we3_reg} <= {(data_width+addr_width+1){1'b0}};
4815 
else
4816 
    {wd3_reg, a3_reg, we3_reg} <= {wd3,a3,wd3};
4817 
 
4818 
    always @ (negedge clk)
4819 
    if (we3_reg)
4820 
        ram1[a3_reg] <= wd3;
4821 
    always @ (posedge clk)
4822 
        a1_reg <= a1;
4823 
    assign rd1 = ram1[a1_reg];
4824 
 
4825 
    always @ (negedge clk)
4826 
    if (we3_reg)
4827 
        ram2[a3_reg] <= wd3;
4828 
    always @ (posedge clk)
4829 
        a2_reg <= a2;
4830 
    assign rd2 = ram2[a2_reg];
4831 
 
4832 
`else
4833 
 
4834 
`define MODULE dpram_1r1w
4835 
`BASE`MODULE
4836 
    # ( .data_width(data_width), .addr_width(addr_width))
4837 
    ram1 (
4838 
        .d_a(wd3),
4839 
        .adr_a(a3),
4840 
        .we_a(we3),
4841 
        .clk_a(clk),
4842 
        .q_b(rd1),
4843 
        .adr_b(a1),
4844 
        .clk_b(clk) );
4845 
 
4846 
`BASE`MODULE
4847 
    # ( .data_width(data_width), .addr_width(addr_width))
4848 
    ram2 (
4849 
        .d_a(wd3),
4850 
        .adr_a(a3),
4851 
        .we_a(we3),
4852 
        .clk_a(clk),
4853 
        .q_b(rd2),
4854 
        .adr_b(a2),
4855 
        .clk_b(clk) );
4856 
`undef MODULE
4857 
 
4858 
`endif
4859 
 
4860 
endmodule
4861 
`endif
4862 12 unneback 
//////////////////////////////////////////////////////////////////////
4863 
////                                                              ////
4864 
////  Versatile library, wishbone stuff                           ////
4865 
////                                                              ////
4866 
////  Description                                                 ////
4867 
////  Wishbone compliant modules                                  ////
4868 
////                                                              ////
4869 
////                                                              ////
4870 
////  To Do:                                                      ////
4871 
////   -                                                          ////
4872 
////                                                              ////
4873 
////  Author(s):                                                  ////
4874 
////      - Michael Unneback, unneback@opencores.org              ////
4875 
////        ORSoC AB                                              ////
4876 
////                                                              ////
4877 
//////////////////////////////////////////////////////////////////////
4878 
////                                                              ////
4879 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
4880 
////                                                              ////
4881 
//// This source file may be used and distributed without         ////
4882 
//// restriction provided that this copyright statement is not    ////
4883 
//// removed from the file and that any derivative work contains  ////
4884 
//// the original copyright notice and the associated disclaimer. ////
4885 
////                                                              ////
4886 
//// This source file is free software; you can redistribute it   ////
4887 
//// and/or modify it under the terms of the GNU Lesser General   ////
4888 
//// Public License as published by the Free Software Foundation; ////
4889 
//// either version 2.1 of the License, or (at your option) any   ////
4890 
//// later version.                                               ////
4891 
////                                                              ////
4892 
//// This source is distributed in the hope that it will be       ////
4893 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
4894 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
4895 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
4896 
//// details.                                                     ////
4897 
////                                                              ////
4898 
//// You should have received a copy of the GNU Lesser General    ////
4899 
//// Public License along with this source; if not, download it   ////
4900 
//// from http://www.opencores.org/lgpl.shtml                     ////
4901 
////                                                              ////
4902 
//////////////////////////////////////////////////////////////////////
4903 
 
4904 75 unneback 
`ifdef WB_ADR_INC
4905 
// async wb3 - wb3 bridge
4906 
`timescale 1ns/1ns
4907 
`define MODULE wb_adr_inc
4908 85 unneback 
module `BASE`MODULE ( cyc_i, stb_i, cti_i, bte_i, adr_i, we_i, ack_o, adr_o, clk, rst);
4909 75 unneback 
`undef MODULE
4910 83 unneback 
parameter adr_width = 10;
4911 
parameter max_burst_width = 4;
4912 85 unneback 
input cyc_i, stb_i, we_i;
4913 83 unneback 
input [2:0] cti_i;
4914 
input [1:0] bte_i;
4915 
input [adr_width-1:0] adr_i;
4916 
output [adr_width-1:0] adr_o;
4917 
output ack_o;
4918 
input clk, rst;
4919 75 unneback 
 
4920 83 unneback 
reg [adr_width-1:0] adr;
4921 90 unneback 
wire [max_burst_width-1:0] to_adr;
4922 91 unneback 
reg [max_burst_width-1:0] last_adr;
4923 92 unneback 
reg last_cycle;
4924 
localparam idle_or_eoc = 1'b0;
4925 
localparam cyc_or_ws   = 1'b1;
4926 90 unneback 
 
4927 91 unneback 
always @ (posedge clk or posedge rst)
4928 
if (rst)
4929 
    last_adr <= {max_burst_width{1'b0}};
4930 
else
4931 
    if (stb_i)
4932 92 unneback 
        last_adr <=adr_o[max_burst_width-1:0];
4933 91 unneback 
 
4934 83 unneback 
generate
4935 
if (max_burst_width==0) begin : inst_0
4936 97 unneback 
 
4937 
        reg ack_o;
4938 
        assign adr_o = adr_i;
4939 
        always @ (posedge clk or posedge rst)
4940 
        if (rst)
4941 
            ack_o <= 1'b0;
4942 
        else
4943 
            ack_o <= cyc_i & stb_i & !ack_o;
4944 
 
4945 83 unneback 
end else begin
4946 
 
4947 
    always @ (posedge clk or posedge rst)
4948 
    if (rst)
4949 92 unneback 
        last_cycle <= idle_or_eoc;
4950 83 unneback 
    else
4951 92 unneback 
        last_cycle <= (!cyc_i) ? idle_or_eoc : //idle
4952 
                      (cyc_i & ack_o & (cti_i==3'b000 | cti_i==3'b111)) ? idle_or_eoc : // eoc
4953 
                      (cyc_i & !stb_i) ? cyc_or_ws : //ws
4954 
                      cyc_or_ws; // cyc
4955 
    assign to_adr = (last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
4956 85 unneback 
    assign adr_o[max_burst_width-1:0] = (we_i) ? adr_i[max_burst_width-1:0] :
4957 91 unneback 
                                        (!stb_i) ? last_adr :
4958 92 unneback 
                                        (last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] :
4959 85 unneback 
                                        adr[max_burst_width-1:0];
4960 92 unneback 
    assign ack_o = (last_cycle==cyc_or_ws) & stb_i;
4961 97 unneback 
 
4962 83 unneback 
end
4963 
endgenerate
4964 
 
4965 
generate
4966 
if (max_burst_width==2) begin : inst_2
4967 
    always @ (posedge clk or posedge rst)
4968 
    if (rst)
4969 
        adr <= 2'h0;
4970 
    else
4971 
        if (cyc_i & stb_i)
4972 
            adr[1:0] <= to_adr[1:0] + 2'd1;
4973 75 unneback 
        else
4974 83 unneback 
            adr <= to_adr[1:0];
4975 
end
4976 
endgenerate
4977 
 
4978 
generate
4979 
if (max_burst_width==3) begin : inst_3
4980 
    always @ (posedge clk or posedge rst)
4981 
    if (rst)
4982 
        adr <= 3'h0;
4983 
    else
4984 
        if (cyc_i & stb_i)
4985 
            case (bte_i)
4986 
            2'b01: adr[2:0] <= {to_adr[2],to_adr[1:0] + 2'd1};
4987 
            default: adr[3:0] <= to_adr[2:0] + 3'd1;
4988 75 unneback 
            endcase
4989 83 unneback 
        else
4990 
            adr <= to_adr[2:0];
4991 
end
4992 
endgenerate
4993 
 
4994 
generate
4995 
if (max_burst_width==4) begin : inst_4
4996 
    always @ (posedge clk or posedge rst)
4997 
    if (rst)
4998 
        adr <= 4'h0;
4999 
    else
5000 91 unneback 
        if (stb_i) // | (!stb_i & last_cycle!=ws)) // for !stb_i restart with adr_i +1, only inc once
5001 83 unneback 
            case (bte_i)
5002 
            2'b01: adr[3:0] <= {to_adr[3:2],to_adr[1:0] + 2'd1};
5003 
            2'b10: adr[3:0] <= {to_adr[3],to_adr[2:0] + 3'd1};
5004 
            default: adr[3:0] <= to_adr + 4'd1;
5005 
            endcase
5006 
        else
5007 
            adr <= to_adr[3:0];
5008 
end
5009 
endgenerate
5010 
 
5011 
generate
5012 
if (adr_width > max_burst_width) begin : pass_through
5013 
    assign adr_o[adr_width-1:max_burst_width] = adr_i[adr_width-1:max_burst_width];
5014 
end
5015 
endgenerate
5016 
 
5017 
endmodule
5018 75 unneback 
`endif
5019 
 
5020 40 unneback 
`ifdef WB3WB3_BRIDGE
5021 12 unneback 
// async wb3 - wb3 bridge
5022 
`timescale 1ns/1ns
5023 40 unneback 
`define MODULE wb3wb3_bridge
5024 
module `BASE`MODULE (
5025 
`undef MODULE
5026 12 unneback 
        // wishbone slave side
5027 
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
5028 
        // wishbone master side
5029 
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
5030 
 
5031 95 unneback 
parameter style = "FIFO"; // valid: simple, FIFO
5032 
parameter addr_width = 4;
5033 
 
5034 12 unneback 
input [31:0] wbs_dat_i;
5035 
input [31:2] wbs_adr_i;
5036 
input [3:0]  wbs_sel_i;
5037 
input [1:0]  wbs_bte_i;
5038 
input [2:0]  wbs_cti_i;
5039 
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
5040 
output [31:0] wbs_dat_o;
5041 14 unneback 
output wbs_ack_o;
5042 12 unneback 
input wbs_clk, wbs_rst;
5043 
 
5044 
output [31:0] wbm_dat_o;
5045 
output reg [31:2] wbm_adr_o;
5046 
output [3:0]  wbm_sel_o;
5047 
output reg [1:0]  wbm_bte_o;
5048 
output reg [2:0]  wbm_cti_o;
5049 14 unneback 
output reg wbm_we_o;
5050 
output wbm_cyc_o;
5051 12 unneback 
output wbm_stb_o;
5052 
input [31:0]  wbm_dat_i;
5053 
input wbm_ack_i;
5054 
input wbm_clk, wbm_rst;
5055 
 
5056 
// bte
5057 
parameter linear       = 2'b00;
5058 
parameter wrap4        = 2'b01;
5059 
parameter wrap8        = 2'b10;
5060 
parameter wrap16       = 2'b11;
5061 
// cti
5062 
parameter classic      = 3'b000;
5063 
parameter incburst     = 3'b010;
5064 
parameter endofburst   = 3'b111;
5065 
 
5066 95 unneback 
localparam wbs_adr  = 1'b0;
5067 
localparam wbs_data = 1'b1;
5068 12 unneback 
 
5069 95 unneback 
localparam wbm_adr0      = 2'b00;
5070 
localparam wbm_adr1      = 2'b01;
5071 
localparam wbm_data      = 2'b10;
5072 
localparam wbm_data_wait = 2'b11;
5073 12 unneback 
 
5074 
reg [1:0] wbs_bte_reg;
5075 
reg wbs;
5076 
wire wbs_eoc_alert, wbm_eoc_alert;
5077 
reg wbs_eoc, wbm_eoc;
5078 
reg [1:0] wbm;
5079 
 
5080 14 unneback 
wire [1:16] wbs_count, wbm_count;
5081 12 unneback 
 
5082 
wire [35:0] a_d, a_q, b_d, b_q;
5083 
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
5084 
reg a_rd_reg;
5085 
wire b_rd_adr, b_rd_data;
5086 14 unneback 
wire b_rd_data_reg;
5087 
wire [35:0] temp;
5088 12 unneback 
 
5089 
`define WE 5
5090 
`define BTE 4:3
5091 
`define CTI 2:0
5092 
 
5093 
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
5094 
always @ (posedge wbs_clk or posedge wbs_rst)
5095 
if (wbs_rst)
5096 
        wbs_eoc <= 1'b0;
5097 
else
5098 
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
5099 78 unneback 
                wbs_eoc <= (wbs_bte_i==linear) | (wbs_cti_i==3'b111);
5100 12 unneback 
        else if (wbs_eoc_alert & (a_rd | a_wr))
5101 
                wbs_eoc <= 1'b1;
5102 
 
5103 40 unneback 
`define MODULE cnt_shreg_ce_clear
5104 
`BASE`MODULE # ( .length(16))
5105 
`undef MODULE
5106 12 unneback 
    cnt0 (
5107 
        .cke(wbs_ack_o),
5108 
        .clear(wbs_eoc),
5109 
        .q(wbs_count),
5110 
        .rst(wbs_rst),
5111 
        .clk(wbs_clk));
5112 
 
5113 
always @ (posedge wbs_clk or posedge wbs_rst)
5114 
if (wbs_rst)
5115 
        wbs <= wbs_adr;
5116 
else
5117 75 unneback 
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & a_fifo_empty)
5118 12 unneback 
                wbs <= wbs_data;
5119 
        else if (wbs_eoc & wbs_ack_o)
5120 
                wbs <= wbs_adr;
5121 
 
5122 
// wbs FIFO
5123 75 unneback 
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,((wbs_cti_i==3'b111) ? {2'b00,3'b000} : {wbs_bte_i,wbs_cti_i})} : {wbs_dat_i,wbs_sel_i};
5124 
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & a_fifo_empty :
5125 12 unneback 
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
5126 
              1'b0;
5127 
assign a_rd = !a_fifo_empty;
5128 
always @ (posedge wbs_clk or posedge wbs_rst)
5129 
if (wbs_rst)
5130 
        a_rd_reg <= 1'b0;
5131 
else
5132 
        a_rd_reg <= a_rd;
5133 
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
5134 
 
5135 
assign wbs_dat_o = a_q[35:4];
5136 
 
5137 
always @ (posedge wbs_clk or posedge wbs_rst)
5138 
if (wbs_rst)
5139 13 unneback 
        wbs_bte_reg <= 2'b00;
5140 12 unneback 
else
5141 13 unneback 
        wbs_bte_reg <= wbs_bte_i;
5142 12 unneback 
 
5143 
// wbm FIFO
5144 
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
5145 
always @ (posedge wbm_clk or posedge wbm_rst)
5146 
if (wbm_rst)
5147 
        wbm_eoc <= 1'b0;
5148 
else
5149 
        if (wbm==wbm_adr0 & !b_fifo_empty)
5150 
                wbm_eoc <= b_q[`BTE] == linear;
5151 
        else if (wbm_eoc_alert & wbm_ack_i)
5152 
                wbm_eoc <= 1'b1;
5153 
 
5154 
always @ (posedge wbm_clk or posedge wbm_rst)
5155 
if (wbm_rst)
5156 
        wbm <= wbm_adr0;
5157 
else
5158 33 unneback 
/*
5159 12 unneback 
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
5160 
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
5161 
        (wbm==wbm_adr1 & !wbm_we_o) |
5162 
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
5163 
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
5164 33 unneback 
*/
5165 
    case (wbm)
5166 
    wbm_adr0:
5167 
        if (!b_fifo_empty)
5168 
            wbm <= wbm_adr1;
5169 
    wbm_adr1:
5170 
        if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
5171 
            wbm <= wbm_data;
5172 
    wbm_data:
5173 
        if (wbm_ack_i & wbm_eoc)
5174 
            wbm <= wbm_adr0;
5175 
        else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
5176 
            wbm <= wbm_data_wait;
5177 
    wbm_data_wait:
5178 
        if (!b_fifo_empty)
5179 
            wbm <= wbm_data;
5180 
    endcase
5181 12 unneback 
 
5182 
assign b_d = {wbm_dat_i,4'b1111};
5183 
assign b_wr = !wbm_we_o & wbm_ack_i;
5184 
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
5185 
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
5186 
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
5187 33 unneback 
                   (wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
5188 12 unneback 
                   1'b0;
5189 
assign b_rd = b_rd_adr | b_rd_data;
5190 
 
5191 40 unneback 
`define MODULE dff
5192 
`BASE`MODULE dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
5193 
`undef MODULE
5194 
`define MODULE dff_ce
5195 
`BASE`MODULE # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
5196 
`undef MODULE
5197 12 unneback 
 
5198 
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
5199 
 
5200 40 unneback 
`define MODULE cnt_shreg_ce_clear
5201 42 unneback 
`BASE`MODULE # ( .length(16))
5202 40 unneback 
`undef MODULE
5203 12 unneback 
    cnt1 (
5204 
        .cke(wbm_ack_i),
5205 
        .clear(wbm_eoc),
5206 
        .q(wbm_count),
5207 
        .rst(wbm_rst),
5208 
        .clk(wbm_clk));
5209 
 
5210 33 unneback 
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
5211 
assign wbm_stb_o = (wbm==wbm_data);
5212 12 unneback 
 
5213 
always @ (posedge wbm_clk or posedge wbm_rst)
5214 
if (wbm_rst)
5215 
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
5216 
else begin
5217 
        if (wbm==wbm_adr0 & !b_fifo_empty)
5218 
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
5219 
        else if (wbm_eoc_alert & wbm_ack_i)
5220 
                wbm_cti_o <= endofburst;
5221 
end
5222 
 
5223 
//async_fifo_dw_simplex_top
5224 40 unneback 
`define MODULE fifo_2r2w_async_simplex
5225 
`BASE`MODULE
5226 
`undef MODULE
5227 12 unneback 
# ( .data_width(36), .addr_width(addr_width))
5228 
fifo (
5229 
    // a side
5230 
    .a_d(a_d),
5231 
    .a_wr(a_wr),
5232 
    .a_fifo_full(a_fifo_full),
5233 
    .a_q(a_q),
5234 
    .a_rd(a_rd),
5235 
    .a_fifo_empty(a_fifo_empty),
5236 
    .a_clk(wbs_clk),
5237 
    .a_rst(wbs_rst),
5238 
    // b side
5239 
    .b_d(b_d),
5240 
    .b_wr(b_wr),
5241 
    .b_fifo_full(b_fifo_full),
5242 
    .b_q(b_q),
5243 
    .b_rd(b_rd),
5244 
    .b_fifo_empty(b_fifo_empty),
5245 
    .b_clk(wbm_clk),
5246 
    .b_rst(wbm_rst)
5247 
    );
5248 
 
5249 
endmodule
5250 40 unneback 
`undef WE
5251 
`undef BTE
5252 
`undef CTI
5253 
`endif
5254 17 unneback 
 
5255 75 unneback 
`ifdef WB3AVALON_BRIDGE
5256 
`define MODULE wb3avalon_bridge
5257 
module `BASE`MODULE (
5258 
`undef MODULE
5259 
        // wishbone slave side
5260 
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
5261 77 unneback 
        // avalon master side
5262 75 unneback 
        readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst);
5263 
 
5264 85 unneback 
parameter linewrapburst = 1'b0;
5265 
 
5266 75 unneback 
input [31:0] wbs_dat_i;
5267 
input [31:2] wbs_adr_i;
5268 
input [3:0]  wbs_sel_i;
5269 
input [1:0]  wbs_bte_i;
5270 
input [2:0]  wbs_cti_i;
5271 83 unneback 
input wbs_we_i;
5272 
input wbs_cyc_i;
5273 
input wbs_stb_i;
5274 75 unneback 
output [31:0] wbs_dat_o;
5275 
output wbs_ack_o;
5276 
input wbs_clk, wbs_rst;
5277 
 
5278 
input [31:0] readdata;
5279 
output [31:0] writedata;
5280 
output [31:2] address;
5281 
output [3:0]  be;
5282 
output write;
5283 81 unneback 
output read;
5284 75 unneback 
output beginbursttransfer;
5285 
output [3:0] burstcount;
5286 
input readdatavalid;
5287 
input waitrequest;
5288 
input clk;
5289 
input rst;
5290 
 
5291 
wire [1:0] wbm_bte_o;
5292 
wire [2:0] wbm_cti_o;
5293 
wire wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_ack_i;
5294 
reg last_cyc;
5295 79 unneback 
reg [3:0] counter;
5296 82 unneback 
reg read_busy;
5297 75 unneback 
 
5298 
always @ (posedge clk or posedge rst)
5299 
if (rst)
5300 
    last_cyc <= 1'b0;
5301 
else
5302 
    last_cyc <= wbm_cyc_o;
5303 
 
5304 79 unneback 
always @ (posedge clk or posedge rst)
5305 
if (rst)
5306 82 unneback 
    read_busy <= 1'b0;
5307 79 unneback 
else
5308 82 unneback 
    if (read & !waitrequest)
5309 
        read_busy <= 1'b1;
5310 
    else if (wbm_ack_i & wbm_cti_o!=3'b010)
5311 
        read_busy <= 1'b0;
5312 
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o & !read_busy;
5313 81 unneback 
 
5314 75 unneback 
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010;
5315 
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 :
5316 
                    (wbm_bte_o==2'b10) ? 4'd8 :
5317 78 unneback 
                    (wbm_bte_o==2'b11) ? 4'd16:
5318 
                    4'd1;
5319 82 unneback 
assign wbm_ack_i = (readdatavalid) | (write & !waitrequest);
5320 75 unneback 
 
5321 79 unneback 
always @ (posedge clk or posedge rst)
5322 
if (rst) begin
5323 
    counter <= 4'd0;
5324 
end else
5325 80 unneback 
    if (wbm_we_o) begin
5326 
        if (!waitrequest & !last_cyc & wbm_cyc_o) begin
5327 85 unneback 
            counter <= burstcount -4'd1;
5328 80 unneback 
        end else if (waitrequest & !last_cyc & wbm_cyc_o) begin
5329 
            counter <= burstcount;
5330 
        end else if (!waitrequest & wbm_stb_o) begin
5331 
            counter <= counter - 4'd1;
5332 
        end
5333 82 unneback 
    end
5334 81 unneback 
assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o & counter!=4'd0;
5335 79 unneback 
 
5336 75 unneback 
`define MODULE wb3wb3_bridge
5337 77 unneback 
`BASE`MODULE wbwb3inst (
5338 75 unneback 
`undef MODULE
5339 
    // wishbone slave side
5340 
    .wbs_dat_i(wbs_dat_i),
5341 
    .wbs_adr_i(wbs_adr_i),
5342 
    .wbs_sel_i(wbs_sel_i),
5343 
    .wbs_bte_i(wbs_bte_i),
5344 
    .wbs_cti_i(wbs_cti_i),
5345 
    .wbs_we_i(wbs_we_i),
5346 
    .wbs_cyc_i(wbs_cyc_i),
5347 
    .wbs_stb_i(wbs_stb_i),
5348 
    .wbs_dat_o(wbs_dat_o),
5349 
    .wbs_ack_o(wbs_ack_o),
5350 
    .wbs_clk(wbs_clk),
5351 
    .wbs_rst(wbs_rst),
5352 
    // wishbone master side
5353 
    .wbm_dat_o(writedata),
5354 78 unneback 
    .wbm_adr_o(address),
5355 75 unneback 
    .wbm_sel_o(be),
5356 
    .wbm_bte_o(wbm_bte_o),
5357 
    .wbm_cti_o(wbm_cti_o),
5358 
    .wbm_we_o(wbm_we_o),
5359 
    .wbm_cyc_o(wbm_cyc_o),
5360 
    .wbm_stb_o(wbm_stb_o),
5361 
    .wbm_dat_i(readdata),
5362 
    .wbm_ack_i(wbm_ack_i),
5363 
    .wbm_clk(clk),
5364 
    .wbm_rst(rst));
5365 
 
5366 
 
5367 
endmodule
5368 
`endif
5369 
 
5370 40 unneback 
`ifdef WB3_ARBITER_TYPE1
5371 
`define MODULE wb3_arbiter_type1
5372 42 unneback 
module `BASE`MODULE (
5373 40 unneback 
`undef MODULE
5374 39 unneback 
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
5375 
    wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
5376 
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
5377 
    wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
5378 
    wb_clk, wb_rst
5379 
);
5380 
 
5381 
parameter nr_of_ports = 3;
5382 
parameter adr_size = 26;
5383 
parameter adr_lo   = 2;
5384 
parameter dat_size = 32;
5385 
parameter sel_size = dat_size/8;
5386 
 
5387 
localparam aw = (adr_size - adr_lo) * nr_of_ports;
5388 
localparam dw = dat_size * nr_of_ports;
5389 
localparam sw = sel_size * nr_of_ports;
5390 
localparam cw = 3 * nr_of_ports;
5391 
localparam bw = 2 * nr_of_ports;
5392 
 
5393 
input  [dw-1:0] wbm_dat_o;
5394 
input  [aw-1:0] wbm_adr_o;
5395 
input  [sw-1:0] wbm_sel_o;
5396 
input  [cw-1:0] wbm_cti_o;
5397 
input  [bw-1:0] wbm_bte_o;
5398 
input  [nr_of_ports-1:0] wbm_we_o, wbm_stb_o, wbm_cyc_o;
5399 
output [dw-1:0] wbm_dat_i;
5400 
output [nr_of_ports-1:0] wbm_ack_i, wbm_err_i, wbm_rty_i;
5401 
 
5402 
output [dat_size-1:0] wbs_dat_i;
5403 
output [adr_size-1:adr_lo] wbs_adr_i;
5404 
output [sel_size-1:0] wbs_sel_i;
5405 
output [2:0] wbs_cti_i;
5406 
output [1:0] wbs_bte_i;
5407 
output wbs_we_i, wbs_stb_i, wbs_cyc_i;
5408 
input  [dat_size-1:0] wbs_dat_o;
5409 
input  wbs_ack_o, wbs_err_o, wbs_rty_o;
5410 
 
5411 
input wb_clk, wb_rst;
5412 
 
5413 44 unneback 
reg  [nr_of_ports-1:0] select;
5414 39 unneback 
wire [nr_of_ports-1:0] state;
5415 
wire [nr_of_ports-1:0] eoc; // end-of-cycle
5416 
wire [nr_of_ports-1:0] sel;
5417 
wire idle;
5418 
 
5419 
genvar i;
5420 
 
5421 
assign idle = !(|state);
5422 
 
5423 
generate
5424 
if (nr_of_ports == 2) begin
5425 
 
5426 
    wire [2:0] wbm1_cti_o, wbm0_cti_o;
5427 
 
5428 
    assign {wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5429 
 
5430 44 unneback 
    //assign select = (idle) ? {wbm_cyc_o[1],!wbm_cyc_o[1] & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5431 
 
5432 
    always @ (idle or wbm_cyc_o)
5433 
    if (idle)
5434 
        casex (wbm_cyc_o)
5435 
        2'b1x : select = 2'b10;
5436 
        2'b01 : select = 2'b01;
5437 
        default : select = {nr_of_ports{1'b0}};
5438 
        endcase
5439 
    else
5440 
        select = {nr_of_ports{1'b0}};
5441 
 
5442 39 unneback 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5443 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5444 
 
5445 
end
5446 
endgenerate
5447 
 
5448 
generate
5449 
if (nr_of_ports == 3) begin
5450 
 
5451 
    wire [2:0] wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5452 
 
5453 
    assign {wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5454 
 
5455 44 unneback 
    always @ (idle or wbm_cyc_o)
5456 
    if (idle)
5457 
        casex (wbm_cyc_o)
5458 
        3'b1xx : select = 3'b100;
5459 
        3'b01x : select = 3'b010;
5460 
        3'b001 : select = 3'b001;
5461 
        default : select = {nr_of_ports{1'b0}};
5462 
        endcase
5463 
    else
5464 
        select = {nr_of_ports{1'b0}};
5465 
 
5466 
//    assign select = (idle) ? {wbm_cyc_o[2],!wbm_cyc_o[2] & wbm_cyc_o[1],wbm_cyc_o[2:1]==2'b00 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5467 39 unneback 
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5468 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5469 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5470 
 
5471 
end
5472 
endgenerate
5473 
 
5474 
generate
5475 44 unneback 
if (nr_of_ports == 4) begin
5476 
 
5477 
    wire [2:0] wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5478 
 
5479 
    assign {wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5480 
 
5481 
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5482 
 
5483 
    always @ (idle or wbm_cyc_o)
5484 
    if (idle)
5485 
        casex (wbm_cyc_o)
5486 
        4'b1xxx : select = 4'b1000;
5487 
        4'b01xx : select = 4'b0100;
5488 
        4'b001x : select = 4'b0010;
5489 
        4'b0001 : select = 4'b0001;
5490 
        default : select = {nr_of_ports{1'b0}};
5491 
        endcase
5492 
    else
5493 
        select = {nr_of_ports{1'b0}};
5494 
 
5495 
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5496 
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5497 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5498 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5499 
 
5500 
end
5501 
endgenerate
5502 
 
5503 
generate
5504 
if (nr_of_ports == 5) begin
5505 
 
5506 
    wire [2:0] wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5507 
 
5508 
    assign {wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5509 
 
5510 
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5511 
 
5512 
    always @ (idle or wbm_cyc_o)
5513 
    if (idle)
5514 
        casex (wbm_cyc_o)
5515 
        5'b1xxxx : select = 5'b10000;
5516 
        5'b01xxx : select = 5'b01000;
5517 
        5'b001xx : select = 5'b00100;
5518 
        5'b0001x : select = 5'b00010;
5519 
        5'b00001 : select = 5'b00001;
5520 
        default : select = {nr_of_ports{1'b0}};
5521 
        endcase
5522 
    else
5523 
        select = {nr_of_ports{1'b0}};
5524 
 
5525 
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
5526 
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5527 
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5528 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5529 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5530 
 
5531 
end
5532 
endgenerate
5533 
 
5534 
generate
5535 67 unneback 
if (nr_of_ports == 6) begin
5536 
 
5537 
    wire [2:0] wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5538 
 
5539 
    assign {wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5540 
 
5541 
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5542 
 
5543 
    always @ (idle or wbm_cyc_o)
5544 
    if (idle)
5545 
        casex (wbm_cyc_o)
5546 
        6'b1xxxxx : select = 6'b100000;
5547 
        6'b01xxxx : select = 6'b010000;
5548 
        6'b001xxx : select = 6'b001000;
5549 
        6'b0001xx : select = 6'b000100;
5550 
        6'b00001x : select = 6'b000010;
5551 
        6'b000001 : select = 6'b000001;
5552 
        default : select = {nr_of_ports{1'b0}};
5553 
        endcase
5554 
    else
5555 
        select = {nr_of_ports{1'b0}};
5556 
 
5557 
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
5558 
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
5559 
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5560 
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5561 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5562 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5563 
 
5564 
end
5565 
endgenerate
5566 
 
5567 
generate
5568 
if (nr_of_ports == 7) begin
5569 
 
5570 
    wire [2:0] wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5571 
 
5572 
    assign {wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5573 
 
5574 
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5575 
 
5576 
    always @ (idle or wbm_cyc_o)
5577 
    if (idle)
5578 
        casex (wbm_cyc_o)
5579 
        7'b1xxxxxx : select = 7'b1000000;
5580 
        7'b01xxxxx : select = 7'b0100000;
5581 
        7'b001xxxx : select = 7'b0010000;
5582 
        7'b0001xxx : select = 7'b0001000;
5583 
        7'b00001xx : select = 7'b0000100;
5584 
        7'b000001x : select = 7'b0000010;
5585 
        7'b0000001 : select = 7'b0000001;
5586 
        default : select = {nr_of_ports{1'b0}};
5587 
        endcase
5588 
    else
5589 
        select = {nr_of_ports{1'b0}};
5590 
 
5591 
    assign eoc[6] = (wbm_ack_i[6] & (wbm6_cti_o == 3'b000 | wbm6_cti_o == 3'b111)) | !wbm_cyc_o[6];
5592 
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
5593 
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
5594 
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5595 
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5596 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5597 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5598 
 
5599 
end
5600 
endgenerate
5601 
 
5602 
generate
5603 
if (nr_of_ports == 8) begin
5604 
 
5605 
    wire [2:0] wbm7_cti_o, wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5606 
 
5607 
    assign {wbm7_cti_o, wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5608 
 
5609 
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5610 
 
5611 
    always @ (idle or wbm_cyc_o)
5612 
    if (idle)
5613 
        casex (wbm_cyc_o)
5614 
        8'b1xxxxxxx : select = 8'b10000000;
5615 
        8'b01xxxxxx : select = 8'b01000000;
5616 
        8'b001xxxxx : select = 8'b00100000;
5617 
        8'b0001xxxx : select = 8'b00010000;
5618 
        8'b00001xxx : select = 8'b00001000;
5619 
        8'b000001xx : select = 8'b00000100;
5620 
        8'b0000001x : select = 8'b00000010;
5621 
        8'b00000001 : select = 8'b00000001;
5622 
        default : select = {nr_of_ports{1'b0}};
5623 
        endcase
5624 
    else
5625 
        select = {nr_of_ports{1'b0}};
5626 
 
5627 
    assign eoc[7] = (wbm_ack_i[7] & (wbm7_cti_o == 3'b000 | wbm7_cti_o == 3'b111)) | !wbm_cyc_o[7];
5628 
    assign eoc[6] = (wbm_ack_i[6] & (wbm6_cti_o == 3'b000 | wbm6_cti_o == 3'b111)) | !wbm_cyc_o[6];
5629 
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
5630 
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
5631 
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5632 
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5633 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5634 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5635 
 
5636 
end
5637 
endgenerate
5638 
 
5639 
generate
5640 63 unneback 
for (i=0;i<nr_of_ports;i=i+1) begin : spr0
5641 42 unneback 
`define MODULE spr
5642 
    `BASE`MODULE sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));
5643 
`undef MODULE
5644 39 unneback 
end
5645 
endgenerate
5646 
 
5647 
    assign sel = select | state;
5648 
 
5649 40 unneback 
`define MODULE mux_andor
5650 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i));
5651 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(adr_size-adr_lo)) mux1 ( .a(wbm_adr_o), .sel(sel), .dout(wbs_adr_i));
5652 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(sel_size)) mux2 ( .a(wbm_sel_o), .sel(sel), .dout(wbs_sel_i));
5653 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(3)) mux3 ( .a(wbm_cti_o), .sel(sel), .dout(wbs_cti_i));
5654 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(2)) mux4 ( .a(wbm_bte_o), .sel(sel), .dout(wbs_bte_i));
5655 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux5 ( .a(wbm_we_o), .sel(sel), .dout(wbs_we_i));
5656 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux6 ( .a(wbm_stb_o), .sel(sel), .dout(wbs_stb_i));
5657 
`undef MODULE
5658 39 unneback 
    assign wbs_cyc_i = |sel;
5659 
 
5660 
    assign wbm_dat_i = {nr_of_ports{wbs_dat_o}};
5661 
    assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
5662 
    assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
5663 
    assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
5664 
 
5665 
endmodule
5666 40 unneback 
`endif
5667 39 unneback 
 
5668 60 unneback 
`ifdef WB_B3_RAM_BE
5669 49 unneback 
// WB RAM with byte enable
5670 59 unneback 
`define MODULE wb_b3_ram_be
5671 
module `BASE`MODULE (
5672 
`undef MODULE
5673 69 unneback 
    wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
5674 
    wbs_dat_o, wbs_ack_o, wb_clk, wb_rst);
5675 59 unneback 
 
5676 68 unneback 
parameter adr_size = 16;
5677 85 unneback 
parameter mem_size = 1<<adr_size;
5678 60 unneback 
parameter dat_size = 32;
5679 83 unneback 
parameter max_burst_width = 4;
5680 60 unneback 
parameter memory_init = 1;
5681 
parameter memory_file = "vl_ram.vmem";
5682 59 unneback 
 
5683 85 unneback 
localparam aw = (adr_size);
5684 69 unneback 
localparam dw = dat_size;
5685 
localparam sw = dat_size/8;
5686 
localparam cw = 3;
5687 
localparam bw = 2;
5688 60 unneback 
 
5689 70 unneback 
input [dw-1:0] wbs_dat_i;
5690 
input [aw-1:0] wbs_adr_i;
5691 
input [cw-1:0] wbs_cti_i;
5692 
input [bw-1:0] wbs_bte_i;
5693 
input [sw-1:0] wbs_sel_i;
5694 
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
5695 
output [dw-1:0] wbs_dat_o;
5696 
output wbs_ack_o;
5697 71 unneback 
input wb_clk, wb_rst;
5698 59 unneback 
 
5699 83 unneback 
wire [aw-1:0] adr;
5700 59 unneback 
 
5701 60 unneback 
`define MODULE ram_be
5702 
`BASE`MODULE # (
5703 
    .data_width(dat_size),
5704 83 unneback 
    .addr_width(aw),
5705 69 unneback 
    .mem_size(mem_size),
5706 68 unneback 
    .memory_init(memory_init),
5707 
    .memory_file(memory_file))
5708 60 unneback 
ram0(
5709 
`undef MODULE
5710 
    .d(wbs_dat_i),
5711 83 unneback 
    .adr(adr),
5712 60 unneback 
    .be(wbs_sel_i),
5713 86 unneback 
    .we(wbs_we_i & wbs_ack_o),
5714 60 unneback 
    .q(wbs_dat_o),
5715 
    .clk(wb_clk)
5716 
);
5717 
 
5718 83 unneback 
`define MODULE wb_adr_inc
5719 
`BASE`MODULE # ( .adr_width(aw), .max_burst_width(max_burst_width)) adr_inc0 (
5720 
    .cyc_i(wbs_cyc_i),
5721 
    .stb_i(wbs_stb_i),
5722 
    .cti_i(wbs_cti_i),
5723 
    .bte_i(wbs_bte_i),
5724 
    .adr_i(wbs_adr_i),
5725 85 unneback 
    .we_i(wbs_we_i),
5726 83 unneback 
    .ack_o(wbs_ack_o),
5727 
    .adr_o(adr),
5728 
    .clk(wb_clk),
5729 
    .rst(wb_rst));
5730 
`undef MODULE
5731 60 unneback 
 
5732 59 unneback 
endmodule
5733 
`endif
5734 
 
5735 
`ifdef WB_B4_RAM_BE
5736 
// WB RAM with byte enable
5737 49 unneback 
`define MODULE wb_b4_ram_be
5738 
module `BASE`MODULE (
5739 
`undef MODULE
5740 
    wb_dat_i, wb_adr_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
5741 52 unneback 
    wb_dat_o, wb_stall_o, wb_ack_o, wb_clk, wb_rst);
5742 49 unneback 
 
5743 100 unneback 
parameter dat_width = 32;
5744 
parameter adr_width = 8;
5745 
parameter mem_size = 1<<adr_width;
5746 
parameter memory_init = 0;
5747 
parameter memory_file = "vl_ram.v";
5748 
parameter debug = 0;
5749 49 unneback 
 
5750 
input [dat_width-1:0] wb_dat_i;
5751 
input [adr_width-1:0] wb_adr_i;
5752 
input [dat_width/8-1:0] wb_sel_i;
5753 
input wb_we_i, wb_stb_i, wb_cyc_i;
5754 
output [dat_width-1:0] wb_dat_o;
5755 52 unneback 
output wb_stall_o;
5756 49 unneback 
output wb_ack_o;
5757 
reg wb_ack_o;
5758 
input wb_clk, wb_rst;
5759 
 
5760 56 unneback 
wire [dat_width/8-1:0] cke;
5761 
 
5762 100 unneback 
`define MODULE ram_be
5763 
`BASE`MODULE # (
5764 
    .data_width(dat_width),
5765 
    .addr_width(adr_width),
5766 
    .mem_size(mem_size),
5767 
    .memory_init(memory_init),
5768 
    .memory_file(memory_file))
5769 
ram0(
5770 
`undef MODULE
5771 
    .d(wb_dat_i),
5772 
    .adr(wb_adr_i),
5773 
    .be(wb_sel_i),
5774 
    .we(wb_we_i & wb_stb_i & wb_cyc_i),
5775 
    .q(wb_dat_o),
5776 
    .clk(wb_clk)
5777 
);
5778 49 unneback 
 
5779 52 unneback 
always @ (posedge wb_clk or posedge wb_rst)
5780 55 unneback 
if (wb_rst)
5781 52 unneback 
    wb_ack_o <= 1'b0;
5782 
else
5783 54 unneback 
    wb_ack_o <= wb_stb_i & wb_cyc_i;
5784 52 unneback 
 
5785 
assign wb_stall_o = 1'b0;
5786 
 
5787 49 unneback 
endmodule
5788 
`endif
5789 
 
5790 48 unneback 
`ifdef WB_B4_ROM
5791 
// WB ROM
5792 
`define MODULE wb_b4_rom
5793 
module `BASE`MODULE (
5794 
`undef MODULE
5795 
    wb_adr_i, wb_stb_i, wb_cyc_i,
5796 
    wb_dat_o, stall_o, wb_ack_o, wb_clk, wb_rst);
5797 
 
5798 
    parameter dat_width = 32;
5799 
    parameter dat_default = 32'h15000000;
5800 
    parameter adr_width = 32;
5801 
 
5802 
/*
5803 
`ifndef ROM
5804 
`define ROM "rom.v"
5805 
`endif
5806 
*/
5807 
    input [adr_width-1:2]   wb_adr_i;
5808 
    input                   wb_stb_i;
5809 
    input                   wb_cyc_i;
5810 
    output [dat_width-1:0]  wb_dat_o;
5811 
    reg [dat_width-1:0]     wb_dat_o;
5812 
    output                  wb_ack_o;
5813 
    reg                     wb_ack_o;
5814 
    output                  stall_o;
5815 
    input                   wb_clk;
5816 
    input                   wb_rst;
5817 
 
5818 
always @ (posedge wb_clk or posedge wb_rst)
5819 
    if (wb_rst)
5820 
        wb_dat_o <= {dat_width{1'b0}};
5821 
    else
5822 
         case (wb_adr_i[adr_width-1:2])
5823 
`ifdef ROM
5824 
`include `ROM
5825 
`endif
5826 
           default:
5827 
             wb_dat_o <= dat_default;
5828 
 
5829 
         endcase // case (wb_adr_i)
5830 
 
5831 
 
5832 
always @ (posedge wb_clk or posedge wb_rst)
5833 
    if (wb_rst)
5834 
        wb_ack_o <= 1'b0;
5835 
    else
5836 
        wb_ack_o <= wb_stb_i & wb_cyc_i;
5837 
 
5838 
assign stall_o = 1'b0;
5839 
 
5840 
endmodule
5841 
`endif
5842 
 
5843 
 
5844 40 unneback 
`ifdef WB_BOOT_ROM
5845 17 unneback 
// WB ROM
5846 40 unneback 
`define MODULE wb_boot_rom
5847 
module `BASE`MODULE (
5848 
`undef MODULE
5849 17 unneback 
    wb_adr_i, wb_stb_i, wb_cyc_i,
5850 18 unneback 
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
5851 17 unneback 
 
5852 18 unneback 
    parameter adr_hi = 31;
5853 
    parameter adr_lo = 28;
5854 
    parameter adr_sel = 4'hf;
5855 
    parameter addr_width = 5;
5856 33 unneback 
/*
5857 17 unneback 
`ifndef BOOT_ROM
5858 
`define BOOT_ROM "boot_rom.v"
5859 
`endif
5860 33 unneback 
*/
5861 18 unneback 
    input [adr_hi:2]    wb_adr_i;
5862 
    input               wb_stb_i;
5863 
    input               wb_cyc_i;
5864 
    output [31:0]        wb_dat_o;
5865 
    output              wb_ack_o;
5866 
    output              hit_o;
5867 
    input               wb_clk;
5868 
    input               wb_rst;
5869 
 
5870 
    wire hit;
5871 
    reg [31:0] wb_dat;
5872 
    reg wb_ack;
5873 
 
5874 
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
5875 17 unneback 
 
5876 
always @ (posedge wb_clk or posedge wb_rst)
5877 
    if (wb_rst)
5878 18 unneback 
        wb_dat <= 32'h15000000;
5879 17 unneback 
    else
5880 18 unneback 
         case (wb_adr_i[addr_width-1:2])
5881 33 unneback 
`ifdef BOOT_ROM
5882 17 unneback 
`include `BOOT_ROM
5883 33 unneback 
`endif
5884 17 unneback 
           /*
5885 
            // Zero r0 and jump to 0x00000100
5886 18 unneback 
 
5887 
            1 : wb_dat <= 32'hA8200000;
5888 
            2 : wb_dat <= 32'hA8C00100;
5889 
            3 : wb_dat <= 32'h44003000;
5890 
            4 : wb_dat <= 32'h15000000;
5891 17 unneback 
            */
5892 
           default:
5893 18 unneback 
             wb_dat <= 32'h00000000;
5894 17 unneback 
 
5895 
         endcase // case (wb_adr_i)
5896 
 
5897 
 
5898 
always @ (posedge wb_clk or posedge wb_rst)
5899 
    if (wb_rst)
5900 18 unneback 
        wb_ack <= 1'b0;
5901 17 unneback 
    else
5902 18 unneback 
        wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
5903 17 unneback 
 
5904 18 unneback 
assign hit_o = hit;
5905 
assign wb_dat_o = wb_dat & {32{wb_ack}};
5906 
assign wb_ack_o = wb_ack;
5907 
 
5908 17 unneback 
endmodule
5909 40 unneback 
`endif
5910 32 unneback 
 
5911 92 unneback 
`ifdef WB_B3_DPRAM
5912 
`define MODULE wb_b3_dpram
5913 40 unneback 
module `BASE`MODULE (
5914 
`undef MODULE
5915 32 unneback 
        // wishbone slave side a
5916 92 unneback 
        wbsa_dat_i, wbsa_adr_i, wbsa_sel_i, wbsa_cti_i, wbsa_bte_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o,
5917 32 unneback 
        wbsa_clk, wbsa_rst,
5918 92 unneback 
        // wishbone slave side b
5919 
        wbsb_dat_i, wbsb_adr_i, wbsb_sel_i, wbsb_cti_i, wbsb_bte_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o,
5920 32 unneback 
        wbsb_clk, wbsb_rst);
5921 
 
5922 92 unneback 
parameter data_width_a = 32;
5923 
parameter data_width_b = data_width_a;
5924 
parameter addr_width_a = 8;
5925 
localparam addr_width_b = data_width_a * addr_width_a / data_width_b;
5926 
   parameter mem_size = (addr_width_a>addr_width_b) ? (1<<addr_width_a) : (1<<addr_width_b);
5927 
parameter max_burst_width_a = 4;
5928 
parameter max_burst_width_b = max_burst_width_a;
5929 32 unneback 
 
5930 92 unneback 
input [data_width_a-1:0] wbsa_dat_i;
5931 
input [addr_width_a-1:0] wbsa_adr_i;
5932 
input [data_width_a/8-1:0] wbsa_sel_i;
5933 
input [2:0] wbsa_cti_i;
5934 
input [1:0] wbsa_bte_i;
5935 32 unneback 
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
5936 92 unneback 
output [data_width_a-1:0] wbsa_dat_o;
5937 32 unneback 
output wbsa_ack_o;
5938 
input wbsa_clk, wbsa_rst;
5939 
 
5940 92 unneback 
input [data_width_b-1:0] wbsb_dat_i;
5941 
input [addr_width_b-1:0] wbsb_adr_i;
5942 
input [data_width_b/8-1:0] wbsb_sel_i;
5943 
input [2:0] wbsb_cti_i;
5944 
input [1:0] wbsb_bte_i;
5945 32 unneback 
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
5946 92 unneback 
output [data_width_b-1:0] wbsb_dat_o;
5947 32 unneback 
output wbsb_ack_o;
5948 
input wbsb_clk, wbsb_rst;
5949 
 
5950 92 unneback 
wire [addr_width_a-1:0] adr_a;
5951 
wire [addr_width_b-1:0] adr_b;
5952 32 unneback 
 
5953 92 unneback 
`define MODULE wb_adr_inc
5954 
`BASE`MODULE # ( .adr_width(addr_width_a), .max_burst_width(max_burst_width_a)) adr_inc0 (
5955 
    .cyc_i(wbsa_cyc_i),
5956 
    .stb_i(wbsa_stb_i),
5957 
    .cti_i(wbsa_cti_i),
5958 
    .bte_i(wbsa_bte_i),
5959 
    .adr_i(wbsa_adr_i),
5960 
    .we_i(wbsa_we_i),
5961 
    .ack_o(wbsa_ack_o),
5962 
    .adr_o(adr_a),
5963 
    .clk(wbsa_clk),
5964 
    .rst(wbsa_rst));
5965 
 
5966 
`BASE`MODULE # ( .adr_width(addr_width_b), .max_burst_width(max_burst_width_b)) adr_inc1 (
5967 
    .cyc_i(wbsb_cyc_i),
5968 
    .stb_i(wbsb_stb_i),
5969 
    .cti_i(wbsb_cti_i),
5970 
    .bte_i(wbsb_bte_i),
5971 
    .adr_i(wbsb_adr_i),
5972 
    .we_i(wbsb_we_i),
5973 
    .ack_o(wbsb_ack_o),
5974 
    .adr_o(adr_b),
5975 
    .clk(wbsb_clk),
5976 
    .rst(wbsb_rst));
5977 40 unneback 
`undef MODULE
5978 92 unneback 
 
5979 
`define MODULE dpram_be_2r2w
5980 
`BASE`MODULE # ( .a_data_width(data_width_a), .a_addr_width(addr_width_a), .mem_size(mem_size))
5981 
`undef MODULE
5982 
ram_i (
5983 32 unneback 
    .d_a(wbsa_dat_i),
5984 92 unneback 
    .q_a(wbsa_dat_o),
5985 
    .adr_a(adr_a),
5986 
    .be_a(wbsa_sel_i),
5987 
    .we_a(wbsa_we_i & wbsa_ack_o),
5988 32 unneback 
    .clk_a(wbsa_clk),
5989 
    .d_b(wbsb_dat_i),
5990 92 unneback 
    .q_b(wbsb_dat_o),
5991 
    .adr_b(adr_b),
5992 
    .be_b(wbsb_sel_i),
5993 
    .we_b(wbsb_we_i & wbsb_ack_o),
5994 32 unneback 
    .clk_b(wbsb_clk) );
5995 
 
5996 
endmodule
5997 40 unneback 
`endif
5998 94 unneback 
 
5999 97 unneback 
`ifdef WBB3_WBB4_CACHE
6000 
`define MODULE wbb3_wbb4_cache
6001 
module `BASE`MODULE (
6002 98 unneback 
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
6003 
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o, wbm_dat_i, wbm_ack_i, wbm_stall_i, wbm_clk, wbm_rst
6004 97 unneback 
);
6005 
`undef MODULE
6006 
 
6007 
parameter dw_s = 32;
6008 
parameter aw_s = 24;
6009 
parameter dw_m = dw_s;
6010 100 unneback 
localparam aw_m = dw_s * aw_s / dw_m;
6011 
parameter wbs_max_burst_width = 4;
6012 97 unneback 
 
6013 
parameter async = 1; // wbs_clk != wbm_clk
6014 
 
6015 
parameter nr_of_ways = 1;
6016 
parameter aw_offset = 4; // 4 => 16 words per cache line
6017 
parameter aw_slot = 10;
6018 100 unneback 
 
6019 
parameter valid_mem = 0;
6020 
parameter debug = 0;
6021 
 
6022 
localparam aw_b_offset = aw_offset * dw_s / dw_m;
6023 98 unneback 
localparam aw_tag = aw_s - aw_slot - aw_offset;
6024 97 unneback 
parameter wbm_burst_size = 4; // valid options 4,8,16
6025 98 unneback 
localparam bte = (wbm_burst_size==4) ? 2'b01 : (wbm_burst_size==8) ? 2'b10 : 2'b11;
6026 97 unneback 
`define SIZE2WIDTH wbm_burst_size
6027 
localparam wbm_burst_width `SIZE2WIDTH_EXPR
6028 
`undef SIZE2WIDTH
6029 
localparam nr_of_wbm_burst = ((1<<aw_offset)/wbm_burst_size) * dw_s / dw_m;
6030 
`define SIZE2WIDTH nr_of_wbm_burst
6031 
localparam nr_of_wbm_burst_width `SIZE2WIDTH_EXPR
6032 
`undef SIZE2WIDTH
6033 100 unneback 
 
6034 97 unneback 
input [dw_s-1:0] wbs_dat_i;
6035 
input [aw_s-1:0] wbs_adr_i; // dont include a1,a0
6036 98 unneback 
input [dw_s/8-1:0] wbs_sel_i;
6037 97 unneback 
input [2:0] wbs_cti_i;
6038 
input [1:0] wbs_bte_i;
6039 98 unneback 
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
6040 97 unneback 
output [dw_s-1:0] wbs_dat_o;
6041 
output wbs_ack_o;
6042 
input wbs_clk, wbs_rst;
6043 
 
6044 
output [dw_m-1:0] wbm_dat_o;
6045 
output [aw_m-1:0] wbm_adr_o;
6046 
output [dw_m/8-1:0] wbm_sel_o;
6047 
output [2:0] wbm_cti_o;
6048 
output [1:0] wbm_bte_o;
6049 98 unneback 
output wbm_stb_o, wbm_cyc_o, wbm_we_o;
6050 97 unneback 
input [dw_m-1:0] wbm_dat_i;
6051 
input wbm_ack_i;
6052 
input wbm_stall_i;
6053 
input wbm_clk, wbm_rst;
6054 
 
6055 100 unneback 
wire valid, dirty, hit;
6056 97 unneback 
wire [aw_tag-1:0] tag;
6057 
wire tag_mem_we;
6058 
wire [aw_tag-1:0] wbs_adr_tag;
6059 
wire [aw_slot-1:0] wbs_adr_slot;
6060 98 unneback 
wire [aw_offset-1:0] wbs_adr_word;
6061 
wire [aw_s-1:0] wbs_adr;
6062 97 unneback 
 
6063 
reg [1:0] state;
6064 
localparam idle = 2'h0;
6065 
localparam rdwr = 2'h1;
6066 
localparam push = 2'h2;
6067 
localparam pull = 2'h3;
6068 
wire eoc;
6069 
 
6070 
// cdc
6071 
wire done, mem_alert, mem_done;
6072 
 
6073 98 unneback 
// wbm side
6074 
reg [aw_m-1:0] wbm_radr;
6075 
reg [aw_m-1:0] wbm_wadr;
6076 100 unneback 
wire [aw_slot-1:0] wbm_adr;
6077 98 unneback 
wire wbm_radr_cke, wbm_wadr_cke;
6078 
 
6079 100 unneback 
reg [2:0] phase;
6080 
// phase = {we,stb,cyc}
6081 
localparam wbm_wait     = 3'b000;
6082 
localparam wbm_wr       = 3'b111;
6083 
localparam wbm_wr_drain = 3'b101;
6084 
localparam wbm_rd       = 3'b011;
6085 
localparam wbm_rd_drain = 3'b001;
6086 98 unneback 
 
6087 97 unneback 
assign {wbs_adr_tag, wbs_adr_slot, wbs_adr_word} = wbs_adr_i;
6088 
assign eoc = (wbs_cti_i==3'b000 | wbs_cti_i==3'b111) & wbs_ack_o;
6089 
 
6090 100 unneback 
generate
6091 
if (valid_mem==0) begin : no_valid_mem
6092 
assign valid = 1'b1;
6093 
end else begin : valid_mem_inst
6094 
`define MODULE dpram_1r1w
6095 97 unneback 
`BASE`MODULE
6096 100 unneback 
    # ( .data_width(1), .addr_width(aw_slot), .memory_init(2), .debug(debug))
6097 
    valid_mem ( .d_a(1'b1), .adr_a(wbs_adr_slot), .we_a(mem_done), .clk_a(wbm_clk),
6098 
                .q_b(valid), .adr_b(wbs_adr_slot), .clk_b(wbs_clk));
6099 97 unneback 
`undef MODULE
6100 100 unneback 
end
6101 
endgenerate
6102 97 unneback 
 
6103 100 unneback 
`define MODULE dpram_1r1w
6104 
`BASE`MODULE
6105 
    # ( .data_width(aw_tag), .addr_width(aw_slot), .memory_init(2), .debug(debug))
6106 
    tag_mem ( .d_a(wbs_adr_tag), .adr_a(wbs_adr_slot), .we_a(mem_done), .clk_a(wbm_clk),
6107 
              .q_b(tag), .adr_b(wbs_adr_slot), .clk_b(wbs_clk));
6108 
assign hit = wbs_adr_tag == tag;
6109 
`undef MODULE
6110 
 
6111 
`define MODULE dpram_1r2w
6112 
`BASE`MODULE
6113 
    # ( .data_width(1), .addr_width(aw_slot), .memory_init(2), .debug(debug))
6114 
    dirty_mem (
6115 
        .d_a(1'b1), .q_a(dirty), .adr_a(wbs_adr_slot), .we_a(wbs_cyc_i & wbs_we_i & wbs_ack_o), .clk_a(wbs_clk),
6116 
        .d_b(1'b0), .adr_b(wbs_adr_slot), .we_b(mem_done), .clk_b(wbm_clk));
6117 
`undef MODULE
6118 
 
6119 97 unneback 
`define MODULE wb_adr_inc
6120 100 unneback 
`BASE`MODULE # ( .adr_width(aw_s), .max_burst_width(wbs_max_burst_width)) adr_inc0 (
6121 
    .cyc_i(wbs_cyc_i & (state==rdwr) & hit & valid),
6122 
    .stb_i(wbs_stb_i & (state==rdwr) & hit & valid), // throttle depending on valid
6123 97 unneback 
    .cti_i(wbs_cti_i),
6124 
    .bte_i(wbs_bte_i),
6125 
    .adr_i(wbs_adr_i),
6126 
    .we_i (wbs_we_i),
6127 
    .ack_o(wbs_ack_o),
6128 
    .adr_o(wbs_adr),
6129 100 unneback 
    .clk(wbs_clk),
6130 
    .rst(wbs_rst));
6131 97 unneback 
`undef MODULE
6132 
 
6133 
`define MODULE dpram_be_2r2w
6134 
`BASE`MODULE
6135 100 unneback 
    # ( .a_data_width(dw_s), .a_addr_width(aw_slot+aw_offset), .b_data_width(dw_m), .debug(debug))
6136 
    cache_mem ( .d_a(wbs_dat_i), .adr_a(wbs_adr[aw_slot+aw_offset-1:0]),   .be_a(wbs_sel_i), .we_a(wbs_cyc_i &  wbs_we_i & wbs_ack_o), .q_a(wbs_dat_o), .clk_a(wbs_clk),
6137 
                .d_b(wbm_dat_i), .adr_b(wbm_adr_o[aw_slot+aw_offset-1:0]), .be_b(wbm_sel_o), .we_b(wbm_cyc_o & !wbm_we_o & wbs_ack_i), .q_b(wbm_dat_o), .clk_b(wbm_clk));
6138 
//                .d_b(wbm_dat_i), .adr_b(wbm_adr), .be_b(wbm_sel_o), .we_b(wbm_cyc_o & !wbm_we_o & wbs_ack_i), .q_b(wbm_dat_o), .clk_b(wbm_clk));
6139 97 unneback 
`undef MODULE
6140 
 
6141 
always @ (posedge wbs_clk or posedge wbs_rst)
6142 
if (wbs_rst)
6143 98 unneback 
    state <= idle;
6144 97 unneback 
else
6145 
    case (state)
6146 
    idle:
6147 
        if (wbs_cyc_i)
6148 
            state <= rdwr;
6149 
    rdwr:
6150 100 unneback 
        casex ({valid, hit, dirty, eoc})
6151 
        4'b0xxx: state <= pull;
6152 
        4'b11x1: state <= idle;
6153 
        4'b101x: state <= push;
6154 
        4'b100x: state <= pull;
6155 
        endcase
6156 97 unneback 
    push:
6157 
        if (done)
6158 
            state <= rdwr;
6159 
    pull:
6160 
        if (done)
6161 
            state <= rdwr;
6162 
    default: state <= idle;
6163 
    endcase
6164 
 
6165 
// cdc
6166 
generate
6167 
if (async==1) begin : cdc0
6168 
`define MODULE cdc
6169 100 unneback 
`BASE`MODULE cdc0 ( .start_pl(state==rdwr & (!valid | !hit)), .take_it_pl(mem_alert), .take_it_grant_pl(mem_done), .got_it_pl(done), .clk_src(wbs_clk), .rst_src(wbs_rst), .clk_dst(wbm_clk), .rst_dst(wbm_rst));
6170 97 unneback 
`undef MODULE
6171 
end
6172 
else begin : nocdc
6173 100 unneback 
    assign mem_alert = state==rdwr & (!valid | !hit);
6174 97 unneback 
    assign done = mem_done;
6175 
end
6176 
endgenerate
6177 
 
6178 
// FSM generating a number of burts 4 cycles
6179 
// actual number depends on data width ratio
6180 
// nr_of_wbm_burst
6181 100 unneback 
reg [wbm_burst_width-1:0]       cnt_rw, cnt_ack;
6182 97 unneback 
 
6183 
always @ (posedge wbm_clk or posedge wbm_rst)
6184 
if (wbm_rst)
6185 100 unneback 
    cnt_rw <= {wbm_burst_width{1'b0}};
6186 97 unneback 
else
6187 100 unneback 
    if (wbm_cyc_o & wbm_stb_o & !wbm_stall_i)
6188 
        cnt_rw <= cnt_rw + 1;
6189 97 unneback 
 
6190 98 unneback 
always @ (posedge wbm_clk or posedge wbm_rst)
6191 
if (wbm_rst)
6192 100 unneback 
    cnt_ack <= {wbm_burst_width{1'b0}};
6193 98 unneback 
else
6194 100 unneback 
    if (wbm_ack_i)
6195 
        cnt_ack <= cnt_ack + 1;
6196 97 unneback 
 
6197 100 unneback 
generate
6198 
if (nr_of_wbm_burst_width==0) begin : one_burst
6199 
 
6200 98 unneback 
always @ (posedge wbm_clk or posedge wbm_rst)
6201 
if (wbm_rst)
6202 
    phase <= wbm_wait;
6203 
else
6204 
    case (phase)
6205 
    wbm_wait:
6206 
        if (mem_alert)
6207 100 unneback 
            if (state==push)
6208 
                phase <= wbm_wr;
6209 
            else
6210 
                phase <= wbm_rd;
6211 98 unneback 
    wbm_wr:
6212 100 unneback 
        if (&cnt_rw)
6213 
            phase <= wbm_wr_drain;
6214 
    wbm_wr_drain:
6215 
        if (&cnt_ack)
6216 98 unneback 
            phase <= wbm_rd;
6217 
    wbm_rd:
6218 100 unneback 
        if (&cnt_rw)
6219 
            phase <= wbm_rd_drain;
6220 
    wbm_rd_drain:
6221 
        if (&cnt_ack)
6222 
            phase <= wbm_wait;
6223 98 unneback 
    default: phase <= wbm_wait;
6224 
    endcase
6225 
 
6226 100 unneback 
    assign mem_done = phase==wbm_rd_drain & (&cnt_ack) & wbm_ack_i;
6227 
 
6228 
end else begin : multiple_burst
6229 
 
6230 
reg [nr_of_wbm_burst_width-1:0] cnt_burst;
6231 
 
6232 
end
6233 
endgenerate
6234 
 
6235 
 
6236 
assign wbm_adr_o = (phase[2]) ? {tag, wbs_adr_slot, cnt_rw} : {wbs_adr_tag, wbs_adr_slot, cnt_rw};
6237 
assign wbm_adr   = (phase[2]) ? {wbs_adr_slot, cnt_rw} : {wbs_adr_slot, cnt_rw};
6238 
assign wbm_sel_o = {dw_m/8{1'b1}};
6239 
assign wbm_cti_o = (&cnt_rw | !wbm_stb_o) ? 3'b111 : 3'b010;
6240 98 unneback 
assign wbm_bte_o = bte;
6241 100 unneback 
assign {wbm_we_o, wbm_stb_o, wbm_cyc_o}  = phase;
6242 98 unneback 
 
6243 97 unneback 
endmodule
6244 
`endif
6245 18 unneback 
//////////////////////////////////////////////////////////////////////
6246 
////                                                              ////
6247 
////  Arithmetic functions                                        ////
6248 
////                                                              ////
6249 
////  Description                                                 ////
6250 
////  Arithmetic functions for ALU and DSP                        ////
6251 
////                                                              ////
6252 
////                                                              ////
6253 
////  To Do:                                                      ////
6254 
////   -                                                          ////
6255 
////                                                              ////
6256 
////  Author(s):                                                  ////
6257 
////      - Michael Unneback, unneback@opencores.org              ////
6258 
////        ORSoC AB                                              ////
6259 
////                                                              ////
6260 
//////////////////////////////////////////////////////////////////////
6261 
////                                                              ////
6262 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
6263 
////                                                              ////
6264 
//// This source file may be used and distributed without         ////
6265 
//// restriction provided that this copyright statement is not    ////
6266 
//// removed from the file and that any derivative work contains  ////
6267 
//// the original copyright notice and the associated disclaimer. ////
6268 
////                                                              ////
6269 
//// This source file is free software; you can redistribute it   ////
6270 
//// and/or modify it under the terms of the GNU Lesser General   ////
6271 
//// Public License as published by the Free Software Foundation; ////
6272 
//// either version 2.1 of the License, or (at your option) any   ////
6273 
//// later version.                                               ////
6274 
////                                                              ////
6275 
//// This source is distributed in the hope that it will be       ////
6276 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
6277 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
6278 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
6279 
//// details.                                                     ////
6280 
////                                                              ////
6281 
//// You should have received a copy of the GNU Lesser General    ////
6282 
//// Public License along with this source; if not, download it   ////
6283 
//// from http://www.opencores.org/lgpl.shtml                     ////
6284 
////                                                              ////
6285 
//////////////////////////////////////////////////////////////////////
6286 
 
6287 40 unneback 
`ifdef MULTS
6288 18 unneback 
// signed multiplication
6289 40 unneback 
`define MODULE mults
6290 
module `BASE`MODULE (a,b,p);
6291 
`undef MODULE
6292 18 unneback 
parameter operand_a_width = 18;
6293 
parameter operand_b_width = 18;
6294 
parameter result_hi = 35;
6295 
parameter result_lo = 0;
6296 
input [operand_a_width-1:0] a;
6297 
input [operand_b_width-1:0] b;
6298 
output [result_hi:result_lo] p;
6299 
wire signed [operand_a_width-1:0] ai;
6300 
wire signed [operand_b_width-1:0] bi;
6301 
wire signed [operand_a_width+operand_b_width-1:0] result;
6302 
 
6303 
    assign ai = a;
6304 
    assign bi = b;
6305 
    assign result = ai * bi;
6306 
    assign p = result[result_hi:result_lo];
6307 
 
6308 
endmodule
6309 40 unneback 
`endif
6310 
`ifdef MULTS18X18
6311 
`define MODULE mults18x18
6312 
module `BASE`MODULE (a,b,p);
6313 
`undef MODULE
6314 18 unneback 
input [17:0] a,b;
6315 
output [35:0] p;
6316 
vl_mult
6317 
    # (.operand_a_width(18), .operand_b_width(18))
6318 
    mult0 (.a(a), .b(b), .p(p));
6319 
endmodule
6320 40 unneback 
`endif
6321 18 unneback 
 
6322 40 unneback 
`ifdef MULT
6323 
`define MODULE mult
6324 18 unneback 
// unsigned multiplication
6325 40 unneback 
module `BASE`MODULE (a,b,p);
6326 
`undef MODULE
6327 18 unneback 
parameter operand_a_width = 18;
6328 
parameter operand_b_width = 18;
6329 
parameter result_hi = 35;
6330 
parameter result_lo = 0;
6331 
input [operand_a_width-1:0] a;
6332 
input [operand_b_width-1:0] b;
6333 
output [result_hi:result_hi] p;
6334 
 
6335 
wire [operand_a_width+operand_b_width-1:0] result;
6336 
 
6337 
    assign result = a * b;
6338 
    assign p = result[result_hi:result_lo];
6339 
 
6340 
endmodule
6341 40 unneback 
`endif
6342 18 unneback 
 
6343 40 unneback 
`ifdef SHIFT_UNIT_32
6344 
`define MODULE shift_unit_32
6345 18 unneback 
// shift unit
6346 
// supporting the following shift functions
6347 
//   SLL
6348 
//   SRL
6349 
//   SRA
6350 
`define SHIFT_UNIT_MULT # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7))
6351 40 unneback 
module `BASE`MODULE( din, s, dout, opcode);
6352 
`undef MODULE
6353 18 unneback 
input [31:0] din; // data in operand
6354 
input [4:0] s; // shift operand
6355 
input [1:0] opcode;
6356 
output [31:0] dout;
6357 
 
6358 
parameter opcode_sll = 2'b00;
6359 
//parameter opcode_srl = 2'b01;
6360 
parameter opcode_sra = 2'b10;
6361 
//parameter opcode_ror = 2'b11;
6362 
 
6363 
wire sll, sra;
6364 
assign sll = opcode == opcode_sll;
6365 
assign sra = opcode == opcode_sra;
6366 
 
6367 
wire [15:1] s1;
6368 
wire [3:0] sign;
6369 
wire [7:0] tmp [0:3];
6370 
 
6371 
// first stage is multiplier based
6372 
// shift operand as fractional 8.7
6373 
assign s1[15] = sll & s[2:0]==3'd7;
6374 
assign s1[14] = sll & s[2:0]==3'd6;
6375 
assign s1[13] = sll & s[2:0]==3'd5;
6376 
assign s1[12] = sll & s[2:0]==3'd4;
6377 
assign s1[11] = sll & s[2:0]==3'd3;
6378 
assign s1[10] = sll & s[2:0]==3'd2;
6379 
assign s1[ 9] = sll & s[2:0]==3'd1;
6380 
assign s1[ 8] = s[2:0]==3'd0;
6381 
assign s1[ 7] = !sll & s[2:0]==3'd1;
6382 
assign s1[ 6] = !sll & s[2:0]==3'd2;
6383 
assign s1[ 5] = !sll & s[2:0]==3'd3;
6384 
assign s1[ 4] = !sll & s[2:0]==3'd4;
6385 
assign s1[ 3] = !sll & s[2:0]==3'd5;
6386 
assign s1[ 2] = !sll & s[2:0]==3'd6;
6387 
assign s1[ 1] = !sll & s[2:0]==3'd7;
6388 
 
6389 
assign sign[3] = din[31] & sra;
6390 
assign sign[2] = sign[3] & (&din[31:24]);
6391 
assign sign[1] = sign[2] & (&din[23:16]);
6392 
assign sign[0] = sign[1] & (&din[15:8]);
6393 40 unneback 
`define MODULE mults
6394 
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte3 ( .a({sign[3], {8{sign[3]}},din[31:24], din[23:16]}), .b({1'b0,s1}), .p(tmp[3]));
6395 
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte2 ( .a({sign[2], din[31:24]  ,din[23:16],  din[15:8]}), .b({1'b0,s1}), .p(tmp[2]));
6396 
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte1 ( .a({sign[1], din[23:16]  ,din[15:8],   din[7:0]}), .b({1'b0,s1}), .p(tmp[1]));
6397 
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte0 ( .a({sign[0], din[15:8]   ,din[7:0],    8'h00}),      .b({1'b0,s1}), .p(tmp[0]));
6398 
`undef MODULE
6399 18 unneback 
// second stage is multiplexer based
6400 
// shift on byte level
6401 
 
6402 
// mux byte 3
6403 
assign dout[31:24] = (s[4:3]==2'b00) ? tmp[3] :
6404 
                     (sll & s[4:3]==2'b01) ? tmp[2] :
6405 
                     (sll & s[4:3]==2'b10) ? tmp[1] :
6406 
                     (sll & s[4:3]==2'b11) ? tmp[0] :
6407 
                     {8{sign[3]}};
6408 
 
6409 
// mux byte 2
6410 
assign dout[23:16] = (s[4:3]==2'b00) ? tmp[2] :
6411 
                     (sll & s[4:3]==2'b01) ? tmp[1] :
6412 
                     (sll & s[4:3]==2'b10) ? tmp[0] :
6413 
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
6414 
                     (s[4:3]==2'b01) ? tmp[3] :
6415 
                     {8{sign[3]}};
6416 
 
6417 
// mux byte 1
6418 
assign dout[15:8]  = (s[4:3]==2'b00) ? tmp[1] :
6419 
                     (sll & s[4:3]==2'b01) ? tmp[0] :
6420 
                     (sll & s[4:3]==2'b10) ? {8{1'b0}} :
6421 
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
6422 
                     (s[4:3]==2'b01) ? tmp[2] :
6423 
                     (s[4:3]==2'b10) ? tmp[3] :
6424 
                     {8{sign[3]}};
6425 
 
6426 
// mux byte 0
6427 
assign dout[7:0]   = (s[4:3]==2'b00) ? tmp[0] :
6428 
                     (sll) ?  {8{1'b0}}:
6429 
                     (s[4:3]==2'b01) ? tmp[1] :
6430 
                     (s[4:3]==2'b10) ? tmp[2] :
6431 
                     tmp[3];
6432 
 
6433 
endmodule
6434 40 unneback 
`endif
6435 18 unneback 
 
6436 40 unneback 
`ifdef LOGIC_UNIT
6437 18 unneback 
// logic unit
6438 
// supporting the following logic functions
6439 
//    a and b
6440 
//    a or  b
6441 
//    a xor b
6442 
//    not b
6443 40 unneback 
`define MODULE logic_unit
6444 
module `BASE`MODULE( a, b, result, opcode);
6445 
`undef MODULE
6446 18 unneback 
parameter width = 32;
6447 
parameter opcode_and = 2'b00;
6448 
parameter opcode_or  = 2'b01;
6449 
parameter opcode_xor = 2'b10;
6450 
input [width-1:0] a,b;
6451 
output [width-1:0] result;
6452 
input [1:0] opcode;
6453 
 
6454 
assign result = (opcode==opcode_and) ? a & b :
6455 
                (opcode==opcode_or)  ? a | b :
6456 
                (opcode==opcode_xor) ? a ^ b :
6457 
                b;
6458 
 
6459 
endmodule
6460 48 unneback 
`endif
6461 18 unneback 
 
6462 48 unneback 
`ifdef ARITH_UNIT
6463 
`define MODULE arith_unit
6464 
module `BASE`MODULE ( a, b, c_in, add_sub, sign, result, c_out, z, ovfl);
6465 
`undef MODULE
6466 18 unneback 
parameter width = 32;
6467 
parameter opcode_add = 1'b0;
6468 
parameter opcode_sub = 1'b1;
6469 
input [width-1:0] a,b;
6470 
input c_in, add_sub, sign;
6471 
output [width-1:0] result;
6472 
output c_out, z, ovfl;
6473 
 
6474 
assign {c_out,result} = {(a[width-1] & sign),a} + ({a[width-1] & sign,b} ^ {(width+1){(add_sub==opcode_sub)}}) + {{(width-1){1'b0}},(c_in | (add_sub==opcode_sub))};
6475 
assign z = (result=={width{1'b0}});
6476 
assign ovfl = ( a[width-1] &  b[width-1] & ~result[width-1]) |
6477 
               (~a[width-1] & ~b[width-1] &  result[width-1]);
6478 
endmodule
6479 40 unneback 
`endif
6480 48 unneback 
 
6481 
`ifdef COUNT_UNIT
6482 
`define MODULE count_unit
6483 
module `BASE`MODULE (din, dout, opcode);
6484 
`undef MODULE
6485 
parameter width = 32;
6486 
input [width-1:0] din;
6487 
output [width-1:0] dout;
6488 
input opcode;
6489 
 
6490 
integer i;
6491 58 unneback 
wire [width/32+4:0] ff1, fl1;
6492 48 unneback 
 
6493 57 unneback 
/*
6494 48 unneback 
always @(din) begin
6495 
    ff1 = 0; i = 0;
6496 
    while (din[i] == 0 && i < width) begin // complex condition
6497 
        ff1 = ff1 + 1;
6498 
        i = i + 1;
6499 
    end
6500 
end
6501 
 
6502 
always @(din) begin
6503 
    fl1 = width; i = width-1;
6504 
    while (din[i] == 0 && i >= width) begin // complex condition
6505 
        fl1 = fl1 - 1;
6506 
        i = i - 1;
6507 
    end
6508 
end
6509 57 unneback 
*/
6510 48 unneback 
 
6511 
generate
6512 
if (width==32) begin
6513 57 unneback 
 
6514 
    assign ff1 = din[0] ? 6'd1 :
6515 
                 din[1] ? 6'd2 :
6516 
                 din[2] ? 6'd3 :
6517 
                 din[3] ? 6'd4 :
6518 
                 din[4] ? 6'd5 :
6519 
                 din[5] ? 6'd6 :
6520 
                 din[6] ? 6'd7 :
6521 
                 din[7] ? 6'd8 :
6522 
                 din[8] ? 6'd9 :
6523 
                 din[9] ? 6'd10 :
6524 
                 din[10] ? 6'd11 :
6525 
                 din[11] ? 6'd12 :
6526 
                 din[12] ? 6'd13 :
6527 
                 din[13] ? 6'd14 :
6528 
                 din[14] ? 6'd15 :
6529 
                 din[15] ? 6'd16 :
6530 
                 din[16] ? 6'd17 :
6531 
                 din[17] ? 6'd18 :
6532 
                 din[18] ? 6'd19 :
6533 
                 din[19] ? 6'd20 :
6534 
                 din[20] ? 6'd21 :
6535 
                 din[21] ? 6'd22 :
6536 
                 din[22] ? 6'd23 :
6537 
                 din[23] ? 6'd24 :
6538 
                 din[24] ? 6'd25 :
6539 
                 din[25] ? 6'd26 :
6540 
                 din[26] ? 6'd27 :
6541 
                 din[27] ? 6'd28 :
6542 
                 din[28] ? 6'd29 :
6543 
                 din[29] ? 6'd30 :
6544 
                 din[30] ? 6'd31 :
6545 
                 din[31] ? 6'd32 :
6546 
                 6'd0;
6547 
 
6548 
    assign fl1 = din[31] ? 6'd32 :
6549 
                 din[30] ? 6'd31 :
6550 
                 din[29] ? 6'd30 :
6551 
                 din[28] ? 6'd29 :
6552 
                 din[27] ? 6'd28 :
6553 
                 din[26] ? 6'd27 :
6554 
                 din[25] ? 6'd26 :
6555 
                 din[24] ? 6'd25 :
6556 
                 din[23] ? 6'd24 :
6557 
                 din[22] ? 6'd23 :
6558 
                 din[21] ? 6'd22 :
6559 
                 din[20] ? 6'd21 :
6560 
                 din[19] ? 6'd20 :
6561 
                 din[18] ? 6'd19 :
6562 
                 din[17] ? 6'd18 :
6563 
                 din[16] ? 6'd17 :
6564 
                 din[15] ? 6'd16 :
6565 
                 din[14] ? 6'd15 :
6566 
                 din[13] ? 6'd14 :
6567 
                 din[12] ? 6'd13 :
6568 
                 din[11] ? 6'd12 :
6569 
                 din[10] ? 6'd11 :
6570 
                 din[9] ? 6'd10 :
6571 
                 din[8] ? 6'd9 :
6572 
                 din[7] ? 6'd8 :
6573 
                 din[6] ? 6'd7 :
6574 
                 din[5] ? 6'd6 :
6575 
                 din[4] ? 6'd5 :
6576 
                 din[3] ? 6'd4 :
6577 
                 din[2] ? 6'd3 :
6578 
                 din[1] ? 6'd2 :
6579 
                 din[0] ? 6'd1 :
6580 
                 6'd0;
6581 
 
6582 
    assign dout = (!opcode) ? {{26{1'b0}}, ff1} : {{26{1'b0}}, fl1};
6583 48 unneback 
end
6584 
endgenerate
6585 57 unneback 
 
6586 48 unneback 
generate
6587 
if (width==64) begin
6588 57 unneback 
    assign ff1 = 7'd0;
6589 
    assign fl1 = 7'd0;
6590 
    assign dout = (!opcode) ? {{57{1'b0}}, ff1} : {{57{1'b0}}, fl1};
6591 48 unneback 
end
6592 
endgenerate
6593 
 
6594 
endmodule
6595 
`endif
6596 
 
6597 
`ifdef EXT_UNIT
6598 
`define MODULE ext_unit
6599 
module `BASE`MODULE ( a, b, F, result, opcode);
6600 
`undef MODULE
6601 
parameter width = 32;
6602 
input [width-1:0] a, b;
6603 
input F;
6604 
output reg [width-1:0] result;
6605 
input [2:0] opcode;
6606 
 
6607 
generate
6608 
if (width==32) begin
6609 
always @ (a or b or F or opcode)
6610 
begin
6611 
    case (opcode)
6612 
    3'b000: result = {{24{1'b0}},a[7:0]};
6613 
    3'b001: result = {{24{a[7]}},a[7:0]};
6614 
    3'b010: result = {{16{1'b0}},a[7:0]};
6615 
    3'b011: result = {{16{a[15]}},a[15:0]};
6616 
    3'b110: result = (F) ? a : b;
6617 
    default: result = {b[15:0],16'h0000};
6618 
    endcase
6619 
end
6620 
end
6621 
endgenerate
6622 
 
6623 
generate
6624 
if (width==64) begin
6625 
always @ (a or b or F or opcode)
6626 
begin
6627 
    case (opcode)
6628 
    3'b000: result = {{56{1'b0}},a[7:0]};
6629 
    3'b001: result = {{56{a[7]}},a[7:0]};
6630 
    3'b010: result = {{48{1'b0}},a[7:0]};
6631 
    3'b011: result = {{48{a[15]}},a[15:0]};
6632 57 unneback 
    3'b110: result = (F) ? a : b;
6633 48 unneback 
    default: result = {32'h00000000,b[15:0],16'h0000};
6634 
    endcase
6635 
end
6636 
end
6637 
endgenerate
6638 
endmodule
6639 
`endif

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