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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Blame information for rev 100

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Line No. Rev Author Line
1 40 unneback
`ifndef BASE
2
`define BASE vl_
3
`endif
4
 
5 60 unneback
// default SYN_KEEP definition
6
`define SYN_KEEP /*synthesis syn_keep = 1*/
7
 
8 44 unneback
`ifdef ACTEL
9 60 unneback
`undef SYN_KEEP
10 44 unneback
`define SYN_KEEP /*synthesis syn_keep = 1*/
11
`endif
12
 
13 98 unneback
`ifdef ACTEL
14
    // ACTEL FPGA should not use logic to handle rw collision
15
    `define SYN_NO_RW_CHECK /*synthesis syn_ramstyle = "no_rw_check"*/
16
`else
17
    `define SYN_NO_RW_CHECK
18
`endif
19
 
20 40 unneback
`ifdef ALL
21
 
22
`define GBUF
23
`define SYNC_RST
24
`define PLL
25
 
26
`define MULTS
27
`define MULTS18X18
28
`define MULT
29
`define SHIFT_UNIT_32
30
`define LOGIC_UNIT
31
 
32
`define CNT_SHREG_WRAP
33
`define CNT_SHREG_CE_WRAP
34
`define CNT_SHREG_CE_CLEAR
35
`define CNT_SHREG_CE_CLEAR_WRAP
36
 
37
`define MUX_ANDOR
38
`define MUX2_ANDOR
39
`define MUX3_ANDOR
40
`define MUX4_ANDOR
41
`define MUX5_ANDOR
42
`define MUX6_ANDOR
43 43 unneback
`define PARITY
44 40 unneback
 
45
`define ROM_INIT
46
`define RAM
47
`define RAM_BE
48
`define DPRAM_1R1W
49
`define DPRAM_2R1W
50 100 unneback
`define DPRAM_1R2W
51 40 unneback
`define DPRAM_2R2W
52 75 unneback
`define DPRAM_BE_2R2W
53 40 unneback
`define FIFO_1R1W_FILL_LEVEL_SYNC
54
`define FIFO_2R2W_SYNC_SIMPLEX
55
`define FIFO_CMP_ASYNC
56
`define FIFO_1R1W_ASYNC
57
`define FIFO_2R2W_ASYNC
58
`define FIFO_2R2W_ASYNC_SIMPLEX
59 48 unneback
`define REG_FILE
60 40 unneback
 
61
`define DFF
62
`define DFF_ARRAY
63
`define DFF_CE
64
`define DFF_CE_CLEAR
65
`define DF_CE_SET
66
`define SPR
67
`define SRP
68
`define DFF_SR
69
`define LATCH
70
`define SHREG
71
`define SHREG_CE
72
`define DELAY
73
`define DELAY_EMPTYFLAG
74 94 unneback
`define PULSE2TOGGLE
75
`define TOGGLE2PULSE
76
`define SYNCHRONIZER
77
`define CDC
78 40 unneback
 
79 75 unneback
`define WB3AVALON_BRIDGE
80 40 unneback
`define WB3WB3_BRIDGE
81
`define WB3_ARBITER_TYPE1
82 83 unneback
`define WB_ADR_INC
83 59 unneback
`define WB_B3_RAM_BE
84 49 unneback
`define WB_B4_RAM_BE
85 48 unneback
`define WB_B4_ROM
86 40 unneback
`define WB_BOOT_ROM
87
`define WB_DPRAM
88 97 unneback
`define WBB3_WBB4_CACHE
89 40 unneback
 
90 44 unneback
`define IO_DFF_OE
91
`define O_DFF
92
 
93 40 unneback
`endif
94
 
95
`ifdef PLL
96
`ifndef SYNC_RST
97
`define SYNC_RST
98
`endif
99
`endif
100
 
101
`ifdef SYNC_RST
102
`ifndef GBUF
103
`define GBUF
104
`endif
105
`endif
106
 
107 92 unneback
`ifdef WB_B3_DPRAM
108
`ifndef WB_ADR_INC
109
`define WB_ADR_INC
110 40 unneback
`endif
111 92 unneback
`ifndef DPRAM_BE_2R2W
112
`define DPRAM_BE_2R2W
113 40 unneback
`endif
114
`endif
115
 
116 62 unneback
`ifdef WB_B3_RAM_BE
117 83 unneback
`ifndef WB_ADR_INC
118
`define WB_ADR_INC
119 62 unneback
`endif
120
`ifndef RAM_BE
121
`define RAM_BE
122
`endif
123
`endif
124
 
125 40 unneback
`ifdef WB3_ARBITER_TYPE1
126 42 unneback
`ifndef SPR
127
`define SPR
128
`endif
129 40 unneback
`ifndef MUX_ANDOR
130
`define MUX_ANDOR
131
`endif
132
`endif
133
 
134 76 unneback
`ifdef WB3AVALON_BRIDGE
135
`ifndef WB3WB3_BRIDGE
136
`define WB3WB3_BRIDGE
137
`endif
138
`endif
139
 
140 40 unneback
`ifdef WB3WB3_BRIDGE
141
`ifndef CNT_SHREG_CE_CLEAR
142
`define CNT_SHREG_CE_CLEAR
143
`endif
144
`ifndef DFF
145
`define DFF
146
`endif
147
`ifndef DFF_CE
148
`define DFF_CE
149
`endif
150
`ifndef CNT_SHREG_CE_CLEAR
151
`define CNT_SHREG_CE_CLEAR
152
`endif
153
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
154
`define FIFO_2R2W_ASYNC_SIMPLEX
155
`endif
156
`endif
157
 
158 100 unneback
`ifdef WBB3_WBB4_CACHE
159
`ifndef RAM
160
`define RAM
161
`endif
162
`ifndef WB_ADR_INC
163
`define WB_ADR_INC
164
`endif
165
`ifndef DPRAM_1R1W
166
`define DPRAM_1R1W
167
`endif
168
`ifndef DPRAM_1R2W
169
`define DPRAM_1R2W
170
`endif
171
`ifndef DPRAM_BE_2R2W
172
`define DPRAM_BE_2R2W
173
`endif
174
`ifndef CDC
175
`define CDC
176
`endif
177
`endif
178 97 unneback
 
179 40 unneback
`ifdef MULTS18X18
180
`ifndef MULTS
181
`define MULTS
182
`endif
183
`endif
184
 
185
`ifdef SHIFT_UNIT_32
186
`ifndef MULTS
187
`define MULTS
188
`endif
189
`endif
190
 
191
`ifdef MUX2_ANDOR
192
`ifndef MUX_ANDOR
193
`define MUX_ANDOR
194
`endif
195
`endif
196
 
197
`ifdef MUX3_ANDOR
198
`ifndef MUX_ANDOR
199
`define MUX_ANDOR
200
`endif
201
`endif
202
 
203
`ifdef MUX4_ANDOR
204
`ifndef MUX_ANDOR
205
`define MUX_ANDOR
206
`endif
207
`endif
208
 
209
`ifdef MUX5_ANDOR
210
`ifndef MUX_ANDOR
211
`define MUX_ANDOR
212
`endif
213
`endif
214
 
215
`ifdef MUX6_ANDOR
216
`ifndef MUX_ANDOR
217
`define MUX_ANDOR
218
`endif
219
`endif
220
 
221
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
222
`ifndef CNT_BIN_CE
223
`define CNT_BIN_CE
224
`endif
225
`ifndef DPRAM_1R1W
226
`define DPRAM_1R1W
227
`endif
228
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
229
`define CNT_BIN_CE_REW_Q_ZQ_L1
230
`endif
231
`endif
232
 
233
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
234
`ifndef CNT_LFSR_CE
235
`define CNT_LFSR_CE
236
`endif
237
`ifndef DPRAM_2R2W
238
`define DPRAM_2R2W
239
`endif
240
`ifndef CNT_BIN_CE_REW_ZQ_L1
241
`define CNT_BIN_CE_REW_ZQ_L1
242
`endif
243
`endif
244
 
245
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
246
`ifndef CNT_GRAY_CE_BIN
247
`define CNT_GRAY_CE_BIN
248
`endif
249
`ifndef DPRAM_2R2W
250
`define DPRAM_2R2W
251
`endif
252
`ifndef FIFO_CMP_ASYNC
253
`define FIFO_CMP_ASYNC
254
`endif
255
`endif
256
 
257
`ifdef FIFO_2R2W_ASYNC
258
`ifndef FIFO_1R1W_ASYNC
259
`define FIFO_1R1W_ASYNC
260
`endif
261
`endif
262
 
263
`ifdef FIFO_1R1W_ASYNC
264
`ifndef CNT_GRAY_CE_BIN
265
`define CNT_GRAY_CE_BIN
266
`endif
267
`ifndef DPRAM_1R1W
268
`define DPRAM_1R1W
269
`endif
270
`ifndef FIFO_CMP_ASYNC
271
`define FIFO_CMP_ASYNC
272
`endif
273
`endif
274
 
275
`ifdef FIFO_CMP_ASYNC
276
`ifndef DFF_SR
277
`define DFF_SR
278
`endif
279
`ifndef DFF
280
`define DFF
281
`endif
282
`endif
283 48 unneback
 
284
`ifdef REG_FILE
285
`ifndef DPRAM_1R1W
286
`define DPRAM_1R1W
287
`endif
288
`endif
289 97 unneback
 
290 98 unneback
`ifdef CDC
291
`ifndef PULSE2TOGGLE
292
`define PULSE2TOGGLE
293
`endif
294
`ifndef TOGGLE2PULSE
295
`define TOGGLE2PULSE
296
`endif
297
`ifndef SYNCHRONIZER
298
`define SYNCHRONIZER
299
`endif
300
`endif
301
 
302 97 unneback
// size to width
303 100 unneback
`define SIZE2WIDTH_EXPR = (`SIZE2WIDTH==1) ? 0 : (`SIZE2WIDTH==2) ? 1 : (`SIZE2WIDTH==4) ? 2 : (`SIZE2WIDTH==8) ? 3 : (`SIZE2WIDTH==16) ? 4 : (`SIZE2WIDTH==32) ? 5 : (`SIZE2WIDTH==64) ? 6 : (`SIZE2WIDTH==128) ? 7 : 8;
304 62 unneback
//////////////////////////////////////////////////////////////////////
305 6 unneback
////                                                              ////
306
////  Versatile library, clock and reset                          ////
307
////                                                              ////
308
////  Description                                                 ////
309
////  Logic related to clock and reset                            ////
310
////                                                              ////
311
////                                                              ////
312
////  To Do:                                                      ////
313
////   - add more different registers                             ////
314
////                                                              ////
315
////  Author(s):                                                  ////
316
////      - Michael Unneback, unneback@opencores.org              ////
317
////        ORSoC AB                                              ////
318
////                                                              ////
319
//////////////////////////////////////////////////////////////////////
320
////                                                              ////
321
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
322
////                                                              ////
323
//// This source file may be used and distributed without         ////
324
//// restriction provided that this copyright statement is not    ////
325
//// removed from the file and that any derivative work contains  ////
326
//// the original copyright notice and the associated disclaimer. ////
327
////                                                              ////
328
//// This source file is free software; you can redistribute it   ////
329
//// and/or modify it under the terms of the GNU Lesser General   ////
330
//// Public License as published by the Free Software Foundation; ////
331
//// either version 2.1 of the License, or (at your option) any   ////
332
//// later version.                                               ////
333
////                                                              ////
334
//// This source is distributed in the hope that it will be       ////
335
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
336
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
337
//// PURPOSE.  See the GNU Lesser General Public License for more ////
338
//// details.                                                     ////
339
////                                                              ////
340
//// You should have received a copy of the GNU Lesser General    ////
341
//// Public License along with this source; if not, download it   ////
342
//// from http://www.opencores.org/lgpl.shtml                     ////
343
////                                                              ////
344
//////////////////////////////////////////////////////////////////////
345
 
346 48 unneback
`ifdef ACTEL
347
`ifdef GBUF
348
`timescale 1 ns/100 ps
349 6 unneback
// Global buffer
350
// usage:
351
// use to enable global buffers for high fan out signals such as clock and reset
352
// Version: 8.4 8.4.0.33
353
module gbuf(GL,CLK);
354
output GL;
355
input  CLK;
356
 
357
    wire GND;
358
 
359
    GND GND_1_net(.Y(GND));
360
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
361
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
362
 
363
endmodule
364
`timescale 1 ns/1 ns
365 40 unneback
`define MODULE gbuf
366
module `BASE`MODULE ( i, o);
367
`undef MODULE
368 6 unneback
input i;
369
output o;
370
`ifdef SIM_GBUF
371
assign o=i;
372
`else
373
gbuf gbuf_i0 ( .CLK(i), .GL(o));
374
`endif
375
endmodule
376 40 unneback
`endif
377 33 unneback
 
378 6 unneback
`else
379 33 unneback
 
380 40 unneback
`ifdef ALTERA
381
`ifdef GBUF
382 21 unneback
//altera
383 40 unneback
`define MODULE gbuf
384
module `BASE`MODULE ( i, o);
385
`undef MODULE
386 33 unneback
input i;
387
output o;
388
assign o = i;
389
endmodule
390 40 unneback
`endif
391 33 unneback
 
392 6 unneback
`else
393
 
394 40 unneback
`ifdef GBUF
395 6 unneback
`timescale 1 ns/100 ps
396 40 unneback
`define MODULE
397
module `BASE`MODULE ( i, o);
398
`undef MODULE
399 6 unneback
input i;
400
output o;
401
assign o = i;
402
endmodule
403 40 unneback
`endif
404 6 unneback
`endif // ALTERA
405
`endif //ACTEL
406
 
407 40 unneback
`ifdef SYNC_RST
408 6 unneback
// sync reset
409 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
410 6 unneback
// output active high global reset sync with two DFFs 
411
`timescale 1 ns/100 ps
412 40 unneback
`define MODULE sync_rst
413
module `BASE`MODULE ( rst_n_i, rst_o, clk);
414
`undef MODULE
415 6 unneback
input rst_n_i, clk;
416
output rst_o;
417 18 unneback
reg [1:0] tmp;
418 6 unneback
always @ (posedge clk or negedge rst_n_i)
419
if (!rst_n_i)
420 17 unneback
        tmp <= 2'b11;
421 6 unneback
else
422 33 unneback
        tmp <= {1'b0,tmp[1]};
423 40 unneback
`define MODULE gbuf
424
`BASE`MODULE buf_i0( .i(tmp[0]), .o(rst_o));
425
`undef MODULE
426 6 unneback
endmodule
427 40 unneback
`endif
428 6 unneback
 
429 40 unneback
`ifdef PLL
430 6 unneback
// vl_pll
431
`ifdef ACTEL
432 32 unneback
///////////////////////////////////////////////////////////////////////////////
433 17 unneback
`timescale 1 ps/1 ps
434 40 unneback
`define MODULE pll
435
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
436
`undef MODULE
437 6 unneback
parameter index = 0;
438
parameter number_of_clk = 1;
439 17 unneback
parameter period_time_0 = 20000;
440
parameter period_time_1 = 20000;
441
parameter period_time_2 = 20000;
442
parameter lock_delay = 2000000;
443 6 unneback
input clk_i, rst_n_i;
444
output lock;
445
output reg [0:number_of_clk-1] clk_o;
446
output [0:number_of_clk-1] rst_o;
447
 
448
`ifdef SIM_PLL
449
 
450
always
451
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
452
 
453
generate if (number_of_clk > 1)
454
always
455
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
456
endgenerate
457
 
458
generate if (number_of_clk > 2)
459
always
460
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
461
endgenerate
462
 
463
genvar i;
464
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
465
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
466
end
467
endgenerate
468
 
469
assign #lock_delay lock = rst_n_i;
470
 
471
endmodule
472
`else
473
generate if (number_of_clk==1 & index==0) begin
474
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
475
end
476
endgenerate // index==0
477
generate if (number_of_clk==1 & index==1) begin
478
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
479
end
480
endgenerate // index==1
481
generate if (number_of_clk==1 & index==2) begin
482
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
483
end
484
endgenerate // index==2
485
generate if (number_of_clk==1 & index==3) begin
486
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
487
end
488
endgenerate // index==0
489
 
490
generate if (number_of_clk==2 & index==0) begin
491
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
492
end
493
endgenerate // index==0
494
generate if (number_of_clk==2 & index==1) begin
495
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
496
end
497
endgenerate // index==1
498
generate if (number_of_clk==2 & index==2) begin
499
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
500
end
501
endgenerate // index==2
502
generate if (number_of_clk==2 & index==3) begin
503
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
504
end
505
endgenerate // index==0
506
 
507
generate if (number_of_clk==3 & index==0) begin
508
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
509
end
510
endgenerate // index==0
511
generate if (number_of_clk==3 & index==1) begin
512
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
513
end
514
endgenerate // index==1
515
generate if (number_of_clk==3 & index==2) begin
516
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
517
end
518
endgenerate // index==2
519
generate if (number_of_clk==3 & index==3) begin
520
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
521
end
522
endgenerate // index==0
523
 
524
genvar i;
525
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
526 40 unneback
`define MODULE sync_rst
527
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
528
`undef MODULE
529 6 unneback
end
530
endgenerate
531
endmodule
532
`endif
533 32 unneback
///////////////////////////////////////////////////////////////////////////////
534 6 unneback
 
535
`else
536
 
537 32 unneback
///////////////////////////////////////////////////////////////////////////////
538 6 unneback
`ifdef ALTERA
539
 
540 32 unneback
`timescale 1 ps/1 ps
541 40 unneback
`define MODULE pll
542
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
543
`undef MODULE
544 32 unneback
parameter index = 0;
545
parameter number_of_clk = 1;
546
parameter period_time_0 = 20000;
547
parameter period_time_1 = 20000;
548
parameter period_time_2 = 20000;
549
parameter period_time_3 = 20000;
550
parameter period_time_4 = 20000;
551
parameter lock_delay = 2000000;
552
input clk_i, rst_n_i;
553
output lock;
554
output reg [0:number_of_clk-1] clk_o;
555
output [0:number_of_clk-1] rst_o;
556
 
557
`ifdef SIM_PLL
558
 
559
always
560
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
561
 
562
generate if (number_of_clk > 1)
563
always
564
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
565
endgenerate
566
 
567
generate if (number_of_clk > 2)
568
always
569
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
570
endgenerate
571
 
572 33 unneback
generate if (number_of_clk > 3)
573 32 unneback
always
574
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
575
endgenerate
576
 
577 33 unneback
generate if (number_of_clk > 4)
578 32 unneback
always
579
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
580
endgenerate
581
 
582
genvar i;
583
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
584
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
585
end
586
endgenerate
587
 
588 33 unneback
//assign #lock_delay lock = rst_n_i;
589
assign lock = rst_n_i;
590 32 unneback
 
591
endmodule
592 6 unneback
`else
593
 
594 33 unneback
`ifdef VL_PLL0
595
`ifdef VL_PLL0_CLK1
596
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
597
`endif
598
`ifdef VL_PLL0_CLK2
599
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
600
`endif
601
`ifdef VL_PLL0_CLK3
602
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
603
`endif
604
`ifdef VL_PLL0_CLK4
605
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
606
`endif
607
`ifdef VL_PLL0_CLK5
608
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
609
`endif
610
`endif
611 32 unneback
 
612 33 unneback
`ifdef VL_PLL1
613
`ifdef VL_PLL1_CLK1
614
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
615
`endif
616
`ifdef VL_PLL1_CLK2
617
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
618
`endif
619
`ifdef VL_PLL1_CLK3
620
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
621
`endif
622
`ifdef VL_PLL1_CLK4
623
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
624
`endif
625
`ifdef VL_PLL1_CLK5
626
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
627
`endif
628
`endif
629 32 unneback
 
630 33 unneback
`ifdef VL_PLL2
631
`ifdef VL_PLL2_CLK1
632
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
633
`endif
634
`ifdef VL_PLL2_CLK2
635
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
636
`endif
637
`ifdef VL_PLL2_CLK3
638
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
639
`endif
640
`ifdef VL_PLL2_CLK4
641
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
642
`endif
643
`ifdef VL_PLL2_CLK5
644
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
645
`endif
646
`endif
647 32 unneback
 
648 33 unneback
`ifdef VL_PLL3
649
`ifdef VL_PLL3_CLK1
650
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
651
`endif
652
`ifdef VL_PLL3_CLK2
653
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
654
`endif
655
`ifdef VL_PLL3_CLK3
656
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
657
`endif
658
`ifdef VL_PLL3_CLK4
659
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
660
`endif
661
`ifdef VL_PLL3_CLK5
662
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
663
`endif
664
`endif
665 32 unneback
 
666
genvar i;
667
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
668 40 unneback
`define MODULE sync_rst
669
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
670
`undef MODULE
671 32 unneback
end
672
endgenerate
673
endmodule
674
`endif
675
///////////////////////////////////////////////////////////////////////////////
676
 
677
`else
678
 
679 6 unneback
// generic PLL
680 17 unneback
`timescale 1 ps/1 ps
681 40 unneback
`define MODULE pll
682
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
683
`undef MODULE
684 6 unneback
parameter index = 0;
685
parameter number_of_clk = 1;
686 17 unneback
parameter period_time_0 = 20000;
687
parameter period_time_1 = 20000;
688
parameter period_time_2 = 20000;
689 6 unneback
parameter lock_delay = 2000;
690
input clk_i, rst_n_i;
691
output lock;
692
output reg [0:number_of_clk-1] clk_o;
693
output [0:number_of_clk-1] rst_o;
694
 
695
always
696
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
697
 
698
generate if (number_of_clk > 1)
699
always
700
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
701
endgenerate
702
 
703
generate if (number_of_clk > 2)
704
always
705
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
706
endgenerate
707
 
708
genvar i;
709
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
710 40 unneback
`define MODULE sync_rst
711
     `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
712
`undef MODULE
713 6 unneback
end
714
endgenerate
715
 
716
assign #lock_delay lock = rst_n_i;
717
 
718
endmodule
719
 
720
`endif //altera
721 17 unneback
`endif //actel
722 40 unneback
`undef MODULE
723
`endif//////////////////////////////////////////////////////////////////////
724 6 unneback
////                                                              ////
725
////  Versatile library, registers                                ////
726
////                                                              ////
727
////  Description                                                 ////
728
////  Different type of registers                                 ////
729
////                                                              ////
730
////                                                              ////
731
////  To Do:                                                      ////
732
////   - add more different registers                             ////
733
////                                                              ////
734
////  Author(s):                                                  ////
735
////      - Michael Unneback, unneback@opencores.org              ////
736
////        ORSoC AB                                              ////
737
////                                                              ////
738
//////////////////////////////////////////////////////////////////////
739
////                                                              ////
740
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
741
////                                                              ////
742
//// This source file may be used and distributed without         ////
743
//// restriction provided that this copyright statement is not    ////
744
//// removed from the file and that any derivative work contains  ////
745
//// the original copyright notice and the associated disclaimer. ////
746
////                                                              ////
747
//// This source file is free software; you can redistribute it   ////
748
//// and/or modify it under the terms of the GNU Lesser General   ////
749
//// Public License as published by the Free Software Foundation; ////
750
//// either version 2.1 of the License, or (at your option) any   ////
751
//// later version.                                               ////
752
////                                                              ////
753
//// This source is distributed in the hope that it will be       ////
754
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
755
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
756
//// PURPOSE.  See the GNU Lesser General Public License for more ////
757
//// details.                                                     ////
758
////                                                              ////
759
//// You should have received a copy of the GNU Lesser General    ////
760
//// Public License along with this source; if not, download it   ////
761
//// from http://www.opencores.org/lgpl.shtml                     ////
762
////                                                              ////
763
//////////////////////////////////////////////////////////////////////
764
 
765 40 unneback
`ifdef DFF
766
`define MODULE dff
767
module `BASE`MODULE ( d, q, clk, rst);
768
`undef MODULE
769 6 unneback
        parameter width = 1;
770
        parameter reset_value = 0;
771
 
772
        input [width-1:0] d;
773
        input clk, rst;
774
        output reg [width-1:0] q;
775
 
776
        always @ (posedge clk or posedge rst)
777
        if (rst)
778
                q <= reset_value;
779
        else
780
                q <= d;
781
 
782
endmodule
783 40 unneback
`endif
784 6 unneback
 
785 40 unneback
`ifdef DFF_ARRAY
786
`define MODULE dff_array
787
module `BASE`MODULE ( d, q, clk, rst);
788
`undef MODULE
789 6 unneback
 
790
        parameter width = 1;
791
        parameter depth = 2;
792
        parameter reset_value = 1'b0;
793
 
794
        input [width-1:0] d;
795
        input clk, rst;
796
        output [width-1:0] q;
797
        reg  [0:depth-1] q_tmp [width-1:0];
798
        integer i;
799
        always @ (posedge clk or posedge rst)
800
        if (rst) begin
801
            for (i=0;i<depth;i=i+1)
802
                q_tmp[i] <= {width{reset_value}};
803
        end else begin
804
            q_tmp[0] <= d;
805
            for (i=1;i<depth;i=i+1)
806
                q_tmp[i] <= q_tmp[i-1];
807
        end
808
 
809
    assign q = q_tmp[depth-1];
810
 
811
endmodule
812 40 unneback
`endif
813 6 unneback
 
814 40 unneback
`ifdef DFF_CE
815
`define MODULE dff_ce
816
module `BASE`MODULE ( d, ce, q, clk, rst);
817
`undef MODULE
818 6 unneback
 
819
        parameter width = 1;
820
        parameter reset_value = 0;
821
 
822
        input [width-1:0] d;
823
        input ce, clk, rst;
824
        output reg [width-1:0] q;
825
 
826
        always @ (posedge clk or posedge rst)
827
        if (rst)
828
                q <= reset_value;
829
        else
830
                if (ce)
831
                        q <= d;
832
 
833
endmodule
834 40 unneback
`endif
835 6 unneback
 
836 40 unneback
`ifdef DFF_CE_CLEAR
837
`define MODULE dff_ce_clear
838
module `BASE`MODULE ( d, ce, clear, q, clk, rst);
839
`undef MODULE
840 8 unneback
 
841
        parameter width = 1;
842
        parameter reset_value = 0;
843
 
844
        input [width-1:0] d;
845 10 unneback
        input ce, clear, clk, rst;
846 8 unneback
        output reg [width-1:0] q;
847
 
848
        always @ (posedge clk or posedge rst)
849
        if (rst)
850
            q <= reset_value;
851
        else
852
            if (ce)
853
                if (clear)
854
                    q <= {width{1'b0}};
855
                else
856
                    q <= d;
857
 
858
endmodule
859 40 unneback
`endif
860 8 unneback
 
861 40 unneback
`ifdef DF_CE_SET
862
`define MODULE dff_ce_set
863
module `BASE`MODULE ( d, ce, set, q, clk, rst);
864
`undef MODULE
865 24 unneback
 
866
        parameter width = 1;
867
        parameter reset_value = 0;
868
 
869
        input [width-1:0] d;
870
        input ce, set, clk, rst;
871
        output reg [width-1:0] q;
872
 
873
        always @ (posedge clk or posedge rst)
874
        if (rst)
875
            q <= reset_value;
876
        else
877
            if (ce)
878
                if (set)
879
                    q <= {width{1'b1}};
880
                else
881
                    q <= d;
882
 
883
endmodule
884 40 unneback
`endif
885 24 unneback
 
886 40 unneback
`ifdef SPR
887
`define MODULE spr
888
module `BASE`MODULE ( sp, r, q, clk, rst);
889
`undef MODULE
890
 
891 64 unneback
        //parameter width = 1;
892
        parameter reset_value = 1'b0;
893 29 unneback
 
894
        input sp, r;
895
        output reg q;
896
        input clk, rst;
897
 
898
        always @ (posedge clk or posedge rst)
899
        if (rst)
900
            q <= reset_value;
901
        else
902
            if (sp)
903
                q <= 1'b1;
904
            else if (r)
905
                q <= 1'b0;
906
 
907
endmodule
908 40 unneback
`endif
909 29 unneback
 
910 40 unneback
`ifdef SRP
911
`define MODULE srp
912
module `BASE`MODULE ( s, rp, q, clk, rst);
913
`undef MODULE
914
 
915 29 unneback
        parameter width = 1;
916
        parameter reset_value = 0;
917
 
918
        input s, rp;
919
        output reg q;
920
        input clk, rst;
921
 
922
        always @ (posedge clk or posedge rst)
923
        if (rst)
924
            q <= reset_value;
925
        else
926
            if (rp)
927
                q <= 1'b0;
928
            else if (s)
929
                q <= 1'b1;
930
 
931
endmodule
932 40 unneback
`endif
933 29 unneback
 
934 40 unneback
`ifdef ALTERA
935 29 unneback
 
936 40 unneback
`ifdef DFF_SR
937 6 unneback
// megafunction wizard: %LPM_FF%
938
// GENERATION: STANDARD
939
// VERSION: WM1.0
940
// MODULE: lpm_ff 
941
 
942
// ============================================================
943
// File Name: dff_sr.v
944
// Megafunction Name(s):
945
//                      lpm_ff
946
//
947
// Simulation Library Files(s):
948
//                      lpm
949
// ============================================================
950
// ************************************************************
951
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
952
//
953
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
954
// ************************************************************
955
 
956
 
957
//Copyright (C) 1991-2010 Altera Corporation
958
//Your use of Altera Corporation's design tools, logic functions 
959
//and other software and tools, and its AMPP partner logic 
960
//functions, and any output files from any of the foregoing 
961
//(including device programming or simulation files), and any 
962
//associated documentation or information are expressly subject 
963
//to the terms and conditions of the Altera Program License 
964
//Subscription Agreement, Altera MegaCore Function License 
965
//Agreement, or other applicable license agreement, including, 
966
//without limitation, that your use is for the sole purpose of 
967
//programming logic devices manufactured by Altera and sold by 
968
//Altera or its authorized distributors.  Please refer to the 
969
//applicable agreement for further details.
970
 
971
 
972
// synopsys translate_off
973
`timescale 1 ps / 1 ps
974
// synopsys translate_on
975 40 unneback
`define MODULE dff_sr
976
module `BASE`MODULE (
977
`undef MODULE
978
 
979 6 unneback
        aclr,
980
        aset,
981
        clock,
982
        data,
983
        q);
984
 
985
        input     aclr;
986
        input     aset;
987
        input     clock;
988
        input     data;
989
        output    q;
990
 
991
        wire [0:0] sub_wire0;
992
        wire [0:0] sub_wire1 = sub_wire0[0:0];
993
        wire  q = sub_wire1;
994
        wire  sub_wire2 = data;
995
        wire  sub_wire3 = sub_wire2;
996
 
997
        lpm_ff  lpm_ff_component (
998
                                .aclr (aclr),
999
                                .clock (clock),
1000
                                .data (sub_wire3),
1001
                                .aset (aset),
1002
                                .q (sub_wire0)
1003
                                // synopsys translate_off
1004
                                ,
1005
                                .aload (),
1006
                                .enable (),
1007
                                .sclr (),
1008
                                .sload (),
1009
                                .sset ()
1010
                                // synopsys translate_on
1011
                                );
1012
        defparam
1013
                lpm_ff_component.lpm_fftype = "DFF",
1014
                lpm_ff_component.lpm_type = "LPM_FF",
1015
                lpm_ff_component.lpm_width = 1;
1016
 
1017
 
1018
endmodule
1019
 
1020
// ============================================================
1021
// CNX file retrieval info
1022
// ============================================================
1023
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
1024
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
1025
// Retrieval info: PRIVATE: ASET NUMERIC "1"
1026
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
1027
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
1028
// Retrieval info: PRIVATE: DFF NUMERIC "1"
1029
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
1030
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
1031
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
1032
// Retrieval info: PRIVATE: SSET NUMERIC "0"
1033
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
1034
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
1035
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
1036
// Retrieval info: PRIVATE: nBit NUMERIC "1"
1037
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
1038
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
1039
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
1040
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
1041
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
1042
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
1043
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
1044
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
1045
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
1046
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
1047
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
1048
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
1049
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
1050
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
1051
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
1052
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
1053
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
1054
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
1055
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
1056
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
1057
// Retrieval info: LIB_FILE: lpm
1058 40 unneback
`endif
1059 6 unneback
 
1060
`else
1061
 
1062 40 unneback
`ifdef DFF_SR
1063
`define MODULE dff_sr
1064
module `BASE`MODULE ( aclr, aset, clock, data, q);
1065
`undef MODULE
1066 6 unneback
 
1067
    input         aclr;
1068
    input         aset;
1069
    input         clock;
1070
    input         data;
1071
    output reg    q;
1072
 
1073
   always @ (posedge clock or posedge aclr or posedge aset)
1074
     if (aclr)
1075
       q <= 1'b0;
1076
     else if (aset)
1077
       q <= 1'b1;
1078
     else
1079
       q <= data;
1080
 
1081
endmodule
1082 40 unneback
`endif
1083 6 unneback
 
1084
`endif
1085
 
1086
// LATCH
1087
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
1088
`ifdef ALTERA
1089 40 unneback
 
1090
`ifdef LATCH
1091
`define MODULE latch
1092
module `BASE`MODULE ( d, le, q, clk);
1093
`undef MODULE
1094 6 unneback
input d, le;
1095
output q;
1096
input clk;
1097
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
1098
endmodule
1099 40 unneback
`endif
1100
 
1101 6 unneback
`else
1102 40 unneback
 
1103
`ifdef LATCH
1104
`define MODULE latch
1105
module `BASE`MODULE ( d, le, q, clk);
1106
`undef MODULE
1107 6 unneback
input d, le;
1108 48 unneback
input clk;
1109
always @ (le or d)
1110 60 unneback
if (le)
1111 48 unneback
    d <= q;
1112 6 unneback
endmodule
1113 15 unneback
`endif
1114
 
1115 40 unneback
`endif
1116
 
1117
`ifdef SHREG
1118
`define MODULE shreg
1119
module `BASE`MODULE ( d, q, clk, rst);
1120
`undef MODULE
1121
 
1122 17 unneback
parameter depth = 10;
1123
input d;
1124
output q;
1125
input clk, rst;
1126
 
1127
reg [1:depth] dffs;
1128
 
1129
always @ (posedge clk or posedge rst)
1130
if (rst)
1131
    dffs <= {depth{1'b0}};
1132
else
1133
    dffs <= {d,dffs[1:depth-1]};
1134
assign q = dffs[depth];
1135
endmodule
1136 40 unneback
`endif
1137 17 unneback
 
1138 40 unneback
`ifdef SHREG_CE
1139
`define MODULE shreg_ce
1140
module `BASE`MODULE ( d, ce, q, clk, rst);
1141
`undef MODULE
1142 17 unneback
parameter depth = 10;
1143
input d, ce;
1144
output q;
1145
input clk, rst;
1146
 
1147
reg [1:depth] dffs;
1148
 
1149
always @ (posedge clk or posedge rst)
1150
if (rst)
1151
    dffs <= {depth{1'b0}};
1152
else
1153
    if (ce)
1154
        dffs <= {d,dffs[1:depth-1]};
1155
assign q = dffs[depth];
1156
endmodule
1157 40 unneback
`endif
1158 17 unneback
 
1159 40 unneback
`ifdef DELAY
1160
`define MODULE delay
1161
module `BASE`MODULE ( d, q, clk, rst);
1162
`undef MODULE
1163 15 unneback
parameter depth = 10;
1164
input d;
1165
output q;
1166
input clk, rst;
1167
 
1168
reg [1:depth] dffs;
1169
 
1170
always @ (posedge clk or posedge rst)
1171
if (rst)
1172
    dffs <= {depth{1'b0}};
1173
else
1174
    dffs <= {d,dffs[1:depth-1]};
1175
assign q = dffs[depth];
1176 17 unneback
endmodule
1177 40 unneback
`endif
1178 17 unneback
 
1179 40 unneback
`ifdef DELAY_EMPTYFLAG
1180
`define MODULE delay_emptyflag
1181 41 unneback
module `BASE`MODULE ( d, q, emptyflag, clk, rst);
1182 40 unneback
`undef MODULE
1183 17 unneback
parameter depth = 10;
1184
input d;
1185
output q, emptyflag;
1186
input clk, rst;
1187
 
1188
reg [1:depth] dffs;
1189
 
1190
always @ (posedge clk or posedge rst)
1191
if (rst)
1192
    dffs <= {depth{1'b0}};
1193
else
1194
    dffs <= {d,dffs[1:depth-1]};
1195
assign q = dffs[depth];
1196
assign emptyflag = !(|dffs);
1197
endmodule
1198 40 unneback
`endif
1199 75 unneback
 
1200 94 unneback
`ifdef PULSE2TOGGLE
1201 98 unneback
`define MODULE pulse2toggle
1202
module `BASE`MODULE ( pl, q, clk, rst);
1203 75 unneback
`undef MODULE
1204 94 unneback
input pl;
1205 98 unneback
output reg q;
1206 94 unneback
input clk, rst;
1207
always @ (posedge clk or posedge rst)
1208 75 unneback
if (rst)
1209 94 unneback
    q <= 1'b0;
1210 75 unneback
else
1211 94 unneback
    q <= pl ^ q;
1212
endmodule
1213
`endif
1214 75 unneback
 
1215 94 unneback
`ifdef TOGGLE2PULSE
1216 98 unneback
`define MODULE toggle2pulse
1217 94 unneback
module `BASE`MODULE (d, pl, clk, rst);
1218 97 unneback
`undef MODULE
1219 94 unneback
input d;
1220
output pl;
1221
input clk, rst;
1222
reg dff;
1223
always @ (posedge clk or posedge rst)
1224
if (rst)
1225
    dff <= 1'b0;
1226 75 unneback
else
1227 94 unneback
    dff <= d;
1228 98 unneback
assign pl = d ^ dff;
1229 94 unneback
endmodule
1230
`endif
1231 75 unneback
 
1232 94 unneback
`ifdef SYNCHRONIZER
1233
`define MODULE synchronizer
1234
module `BASE`MODULE (d, q, clk, rst);
1235
`undef MODULE
1236
input d;
1237
output reg q;
1238
output clk, rst;
1239
reg dff;
1240
always @ (posedge clk or posedge rst)
1241
if (rst)
1242 100 unneback
    {q,dff} <= 2'b00;
1243 75 unneback
else
1244 100 unneback
    {q,dff} <= {dff,d};
1245 94 unneback
endmodule
1246
`endif
1247 75 unneback
 
1248 94 unneback
`ifdef CDC
1249
`define MODULE cdc
1250 97 unneback
module `BASE`MODULE ( start_pl, take_it_pl, take_it_grant_pl, got_it_pl, clk_src, rst_src, clk_dst, rst_dst);
1251 94 unneback
`undef MODULE
1252
input start_pl;
1253
output take_it_pl;
1254
input take_it_grant_pl; // note: connect to take_it_pl to generate automatic ack
1255
output got_it_pl;
1256
input clk_src, rst_src;
1257
input clk_dst, rst_dst;
1258
wire take_it_tg, take_it_tg_sync;
1259
wire got_it_tg, got_it_tg_sync;
1260
// src -> dst
1261
`define MODULE pulse2toggle
1262
`BASE`MODULE p2t0 (
1263
`undef MODULE
1264
    .pl(start_pl),
1265
    .q(take_it_tg),
1266
    .clk(clk_src),
1267
    .rst(rst_src));
1268 75 unneback
 
1269 94 unneback
`define MODULE synchronizer
1270
`BASE`MODULE sync0 (
1271
`undef MODULE
1272
    .d(take_it_tg),
1273
    .q(take_it_tg_sync),
1274
    .clk(clk_dst),
1275
    .rst(rst_dst));
1276
 
1277
`define MODULE toggle2pulse
1278
`BASE`MODULE t2p0 (
1279
`undef MODULE
1280 100 unneback
    .d(take_it_tg_sync),
1281 94 unneback
    .pl(take_it_pl),
1282
    .clk(clk_dst),
1283
    .rst(rst_dst));
1284
 
1285
// dst -> src
1286
`define MODULE pulse2toggle
1287 98 unneback
`BASE`MODULE p2t1 (
1288 94 unneback
`undef MODULE
1289
    .pl(take_it_grant_pl),
1290
    .q(got_it_tg),
1291
    .clk(clk_dst),
1292
    .rst(rst_dst));
1293
 
1294
`define MODULE synchronizer
1295
`BASE`MODULE sync1 (
1296
`undef MODULE
1297
    .d(got_it_tg),
1298
    .q(got_it_tg_sync),
1299
    .clk(clk_src),
1300
    .rst(rst_src));
1301
 
1302
`define MODULE toggle2pulse
1303
`BASE`MODULE t2p1 (
1304
`undef MODULE
1305 100 unneback
    .d(got_it_tg_sync),
1306 94 unneback
    .pl(got_it_pl),
1307
    .clk(clk_src),
1308
    .rst(rst_src));
1309
 
1310 75 unneback
endmodule
1311
`endif
1312 17 unneback
//////////////////////////////////////////////////////////////////////
1313 6 unneback
////                                                              ////
1314 18 unneback
////  Logic functions                                             ////
1315
////                                                              ////
1316
////  Description                                                 ////
1317
////  Logic functions such as multiplexers                        ////
1318
////                                                              ////
1319
////                                                              ////
1320
////  To Do:                                                      ////
1321
////   -                                                          ////
1322
////                                                              ////
1323
////  Author(s):                                                  ////
1324
////      - Michael Unneback, unneback@opencores.org              ////
1325
////        ORSoC AB                                              ////
1326
////                                                              ////
1327
//////////////////////////////////////////////////////////////////////
1328
////                                                              ////
1329
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1330
////                                                              ////
1331
//// This source file may be used and distributed without         ////
1332
//// restriction provided that this copyright statement is not    ////
1333
//// removed from the file and that any derivative work contains  ////
1334
//// the original copyright notice and the associated disclaimer. ////
1335
////                                                              ////
1336
//// This source file is free software; you can redistribute it   ////
1337
//// and/or modify it under the terms of the GNU Lesser General   ////
1338
//// Public License as published by the Free Software Foundation; ////
1339
//// either version 2.1 of the License, or (at your option) any   ////
1340
//// later version.                                               ////
1341
////                                                              ////
1342
//// This source is distributed in the hope that it will be       ////
1343
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1344
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1345
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1346
//// details.                                                     ////
1347
////                                                              ////
1348
//// You should have received a copy of the GNU Lesser General    ////
1349
//// Public License along with this source; if not, download it   ////
1350
//// from http://www.opencores.org/lgpl.shtml                     ////
1351
////                                                              ////
1352
//////////////////////////////////////////////////////////////////////
1353 40 unneback
`ifdef MUX_ANDOR
1354
`define MODULE mux_andor
1355
module `BASE`MODULE ( a, sel, dout);
1356
`undef MODULE
1357 36 unneback
 
1358
parameter width = 32;
1359
parameter nr_of_ports = 4;
1360
 
1361
input [nr_of_ports*width-1:0] a;
1362
input [nr_of_ports-1:0] sel;
1363
output reg [width-1:0] dout;
1364
 
1365 38 unneback
integer i,j;
1366
 
1367 36 unneback
always @ (a, sel)
1368
begin
1369
    dout = a[width-1:0] & {width{sel[0]}};
1370 42 unneback
    for (i=1;i<nr_of_ports;i=i+1)
1371
        for (j=0;j<width;j=j+1)
1372
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
1373 36 unneback
end
1374
 
1375
endmodule
1376 40 unneback
`endif
1377 36 unneback
 
1378 40 unneback
`ifdef MUX2_ANDOR
1379
`define MODULE mux2_andor
1380
module `BASE`MODULE ( a1, a0, sel, dout);
1381
`undef MODULE
1382 18 unneback
 
1383 34 unneback
parameter width = 32;
1384 35 unneback
localparam nr_of_ports = 2;
1385 34 unneback
input [width-1:0] a1, a0;
1386
input [nr_of_ports-1:0] sel;
1387
output [width-1:0] dout;
1388
 
1389 40 unneback
`define MODULE mux_andor
1390
`BASE`MODULE
1391 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1392 36 unneback
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
1393 40 unneback
`undef MODULE
1394
 
1395 34 unneback
endmodule
1396 40 unneback
`endif
1397 34 unneback
 
1398 40 unneback
`ifdef MUX3_ANDOR
1399
`define MODULE mux3_andor
1400
module `BASE`MODULE ( a2, a1, a0, sel, dout);
1401
`undef MODULE
1402 34 unneback
 
1403
parameter width = 32;
1404 35 unneback
localparam nr_of_ports = 3;
1405 34 unneback
input [width-1:0] a2, a1, a0;
1406
input [nr_of_ports-1:0] sel;
1407
output [width-1:0] dout;
1408
 
1409 40 unneback
`define MODULE mux_andor
1410
`BASE`MODULE
1411 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1412 36 unneback
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
1413 40 unneback
`undef MODULE
1414 34 unneback
endmodule
1415 40 unneback
`endif
1416 34 unneback
 
1417 40 unneback
`ifdef MUX4_ANDOR
1418
`define MODULE mux4_andor
1419
module `BASE`MODULE ( a3, a2, a1, a0, sel, dout);
1420
`undef MODULE
1421 18 unneback
 
1422
parameter width = 32;
1423 35 unneback
localparam nr_of_ports = 4;
1424 18 unneback
input [width-1:0] a3, a2, a1, a0;
1425
input [nr_of_ports-1:0] sel;
1426 22 unneback
output [width-1:0] dout;
1427 18 unneback
 
1428 40 unneback
`define MODULE mux_andor
1429
`BASE`MODULE
1430 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1431 36 unneback
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
1432 40 unneback
`undef MODULE
1433 18 unneback
 
1434
endmodule
1435 40 unneback
`endif
1436 18 unneback
 
1437 40 unneback
`ifdef MUX5_ANDOR
1438
`define MODULE mux5_andor
1439
module `BASE`MODULE ( a4, a3, a2, a1, a0, sel, dout);
1440
`undef MODULE
1441 18 unneback
 
1442
parameter width = 32;
1443 35 unneback
localparam nr_of_ports = 5;
1444 18 unneback
input [width-1:0] a4, a3, a2, a1, a0;
1445
input [nr_of_ports-1:0] sel;
1446 22 unneback
output [width-1:0] dout;
1447 18 unneback
 
1448 40 unneback
`define MODULE mux_andor
1449
`BASE`MODULE
1450 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1451 36 unneback
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1452 40 unneback
`undef MODULE
1453 18 unneback
 
1454
endmodule
1455 40 unneback
`endif
1456 18 unneback
 
1457 40 unneback
`ifdef MUX6_ANDOR
1458
`define MODULE mux6_andor
1459
module `BASE`MODULE ( a5, a4, a3, a2, a1, a0, sel, dout);
1460
`undef MODULE
1461 18 unneback
 
1462
parameter width = 32;
1463 35 unneback
localparam nr_of_ports = 6;
1464 18 unneback
input [width-1:0] a5, a4, a3, a2, a1, a0;
1465
input [nr_of_ports-1:0] sel;
1466 22 unneback
output [width-1:0] dout;
1467 18 unneback
 
1468 40 unneback
`define MODULE mux_andor
1469
`BASE`MODULE
1470 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1471 36 unneback
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1472 40 unneback
`undef MODULE
1473 18 unneback
 
1474
endmodule
1475 40 unneback
`endif
1476 43 unneback
 
1477
`ifdef PARITY
1478
 
1479
`define MODULE parity_generate
1480
module `BASE`MODULE (data, parity);
1481
`undef MODULE
1482
parameter word_size = 32;
1483
parameter chunk_size = 8;
1484
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1485
input [word_size-1:0] data;
1486
output reg [word_size/chunk_size-1:0] parity;
1487
integer i,j;
1488
always @ (data)
1489
for (i=0;i<word_size/chunk_size;i=i+1) begin
1490
    parity[i] = parity_type;
1491
    for (j=0;j<chunk_size;j=j+1) begin
1492 46 unneback
        parity[i] = data[i*chunk_size+j] ^ parity[i];
1493 43 unneback
    end
1494
end
1495
endmodule
1496
 
1497
`define MODULE parity_check
1498
module `BASE`MODULE( data, parity, parity_error);
1499
`undef MODULE
1500
parameter word_size = 32;
1501
parameter chunk_size = 8;
1502
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1503
input [word_size-1:0] data;
1504
input [word_size/chunk_size-1:0] parity;
1505
output parity_error;
1506 44 unneback
reg [word_size/chunk_size-1:0] error_flag;
1507 43 unneback
integer i,j;
1508
always @ (data or parity)
1509
for (i=0;i<word_size/chunk_size;i=i+1) begin
1510
    error_flag[i] = parity[i] ^ parity_type;
1511
    for (j=0;j<chunk_size;j=j+1) begin
1512 46 unneback
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
1513 43 unneback
    end
1514
end
1515
assign parity_error = |error_flag;
1516
endmodule
1517
 
1518 44 unneback
`endif//////////////////////////////////////////////////////////////////////
1519
////                                                              ////
1520
////  IO functions                                                ////
1521
////                                                              ////
1522
////  Description                                                 ////
1523
////  IO functions such as IOB flip-flops                         ////
1524
////                                                              ////
1525
////                                                              ////
1526
////  To Do:                                                      ////
1527
////   -                                                          ////
1528
////                                                              ////
1529
////  Author(s):                                                  ////
1530
////      - Michael Unneback, unneback@opencores.org              ////
1531
////        ORSoC AB                                              ////
1532
////                                                              ////
1533 18 unneback
//////////////////////////////////////////////////////////////////////
1534
////                                                              ////
1535 44 unneback
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1536
////                                                              ////
1537
//// This source file may be used and distributed without         ////
1538
//// restriction provided that this copyright statement is not    ////
1539
//// removed from the file and that any derivative work contains  ////
1540
//// the original copyright notice and the associated disclaimer. ////
1541
////                                                              ////
1542
//// This source file is free software; you can redistribute it   ////
1543
//// and/or modify it under the terms of the GNU Lesser General   ////
1544
//// Public License as published by the Free Software Foundation; ////
1545
//// either version 2.1 of the License, or (at your option) any   ////
1546
//// later version.                                               ////
1547
////                                                              ////
1548
//// This source is distributed in the hope that it will be       ////
1549
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1550
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1551
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1552
//// details.                                                     ////
1553
////                                                              ////
1554
//// You should have received a copy of the GNU Lesser General    ////
1555
//// Public License along with this source; if not, download it   ////
1556
//// from http://www.opencores.org/lgpl.shtml                     ////
1557
////                                                              ////
1558
//////////////////////////////////////////////////////////////////////
1559 45 unneback
`timescale 1ns/1ns
1560 44 unneback
`ifdef O_DFF
1561
`define MODULE o_dff
1562
module `BASE`MODULE (d_i, o_pad, clk, rst);
1563
`undef MODULE
1564
parameter width = 1;
1565 45 unneback
parameter reset_value = {width{1'b0}};
1566
input  [width-1:0]  d_i;
1567 44 unneback
output [width-1:0] o_pad;
1568
input clk, rst;
1569
wire [width-1:0] d_i_int `SYN_KEEP;
1570 45 unneback
reg  [width-1:0] o_pad_int;
1571 44 unneback
assign d_i_int = d_i;
1572
genvar i;
1573 45 unneback
generate
1574 44 unneback
for (i=0;i<width;i=i+1) begin
1575
    always @ (posedge clk or posedge rst)
1576
    if (rst)
1577 45 unneback
        o_pad_int[i] <= reset_value[i];
1578 44 unneback
    else
1579 45 unneback
        o_pad_int[i] <= d_i_int[i];
1580
    assign #1 o_pad[i] = o_pad_int[i];
1581 44 unneback
end
1582
endgenerate
1583
endmodule
1584
`endif
1585
 
1586 45 unneback
`timescale 1ns/1ns
1587 44 unneback
`ifdef IO_DFF_OE
1588
`define MODULE io_dff_oe
1589
module `BASE`MODULE ( d_i, d_o, oe, io_pad, clk, rst);
1590
`undef MODULE
1591
parameter width = 1;
1592
input  [width-1:0] d_o;
1593
output reg [width-1:0] d_i;
1594
input oe;
1595
inout [width-1:0] io_pad;
1596
input clk, rst;
1597
wire [width-1:0] oe_d `SYN_KEEP;
1598
reg [width-1:0] oe_q;
1599
reg [width-1:0] d_o_q;
1600
assign oe_d = {width{oe}};
1601
genvar i;
1602
generate
1603
for (i=0;i<width;i=i+1) begin
1604
    always @ (posedge clk or posedge rst)
1605
    if (rst)
1606
        oe_q[i] <= 1'b0;
1607
    else
1608
        oe_q[i] <= oe_d[i];
1609
    always @ (posedge clk or posedge rst)
1610
    if (rst)
1611
        d_o_q[i] <= 1'b0;
1612
    else
1613
        d_o_q[i] <= d_o[i];
1614
    always @ (posedge clk or posedge rst)
1615
    if (rst)
1616
        d_i[i] <= 1'b0;
1617
    else
1618
        d_i[i] <= io_pad[i];
1619 45 unneback
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
1620 44 unneback
end
1621
endgenerate
1622
endmodule
1623
`endif
1624
`ifdef CNT_BIN
1625
//////////////////////////////////////////////////////////////////////
1626
////                                                              ////
1627 6 unneback
////  Versatile counter                                           ////
1628
////                                                              ////
1629
////  Description                                                 ////
1630
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1631
////  counter                                                     ////
1632
////                                                              ////
1633
////  To Do:                                                      ////
1634
////   - add LFSR with more taps                                  ////
1635
////                                                              ////
1636
////  Author(s):                                                  ////
1637
////      - Michael Unneback, unneback@opencores.org              ////
1638
////        ORSoC AB                                              ////
1639
////                                                              ////
1640
//////////////////////////////////////////////////////////////////////
1641
////                                                              ////
1642
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1643
////                                                              ////
1644
//// This source file may be used and distributed without         ////
1645
//// restriction provided that this copyright statement is not    ////
1646
//// removed from the file and that any derivative work contains  ////
1647
//// the original copyright notice and the associated disclaimer. ////
1648
////                                                              ////
1649
//// This source file is free software; you can redistribute it   ////
1650
//// and/or modify it under the terms of the GNU Lesser General   ////
1651
//// Public License as published by the Free Software Foundation; ////
1652
//// either version 2.1 of the License, or (at your option) any   ////
1653
//// later version.                                               ////
1654
////                                                              ////
1655
//// This source is distributed in the hope that it will be       ////
1656
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1657
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1658
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1659
//// details.                                                     ////
1660
////                                                              ////
1661
//// You should have received a copy of the GNU Lesser General    ////
1662
//// Public License along with this source; if not, download it   ////
1663
//// from http://www.opencores.org/lgpl.shtml                     ////
1664
////                                                              ////
1665
//////////////////////////////////////////////////////////////////////
1666
 
1667
// binary counter
1668 22 unneback
 
1669 40 unneback
`define MODULE cnt_bin
1670
module `BASE`MODULE (
1671
`undef MODULE
1672
 q, rst, clk);
1673
 
1674 22 unneback
   parameter length = 4;
1675
   output [length:1] q;
1676
   input rst;
1677
   input clk;
1678
 
1679
   parameter clear_value = 0;
1680
   parameter set_value = 1;
1681
   parameter wrap_value = 0;
1682
   parameter level1_value = 15;
1683
 
1684
   reg  [length:1] qi;
1685
   wire [length:1] q_next;
1686
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1687
 
1688
   always @ (posedge clk or posedge rst)
1689
     if (rst)
1690
       qi <= {length{1'b0}};
1691
     else
1692
       qi <= q_next;
1693
 
1694
   assign q = qi;
1695
 
1696
endmodule
1697 40 unneback
`endif
1698
`ifdef CNT_BIN_CLEAR
1699 22 unneback
//////////////////////////////////////////////////////////////////////
1700
////                                                              ////
1701
////  Versatile counter                                           ////
1702
////                                                              ////
1703
////  Description                                                 ////
1704
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1705
////  counter                                                     ////
1706
////                                                              ////
1707
////  To Do:                                                      ////
1708
////   - add LFSR with more taps                                  ////
1709
////                                                              ////
1710
////  Author(s):                                                  ////
1711
////      - Michael Unneback, unneback@opencores.org              ////
1712
////        ORSoC AB                                              ////
1713
////                                                              ////
1714
//////////////////////////////////////////////////////////////////////
1715
////                                                              ////
1716
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1717
////                                                              ////
1718
//// This source file may be used and distributed without         ////
1719
//// restriction provided that this copyright statement is not    ////
1720
//// removed from the file and that any derivative work contains  ////
1721
//// the original copyright notice and the associated disclaimer. ////
1722
////                                                              ////
1723
//// This source file is free software; you can redistribute it   ////
1724
//// and/or modify it under the terms of the GNU Lesser General   ////
1725
//// Public License as published by the Free Software Foundation; ////
1726
//// either version 2.1 of the License, or (at your option) any   ////
1727
//// later version.                                               ////
1728
////                                                              ////
1729
//// This source is distributed in the hope that it will be       ////
1730
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1731
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1732
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1733
//// details.                                                     ////
1734
////                                                              ////
1735
//// You should have received a copy of the GNU Lesser General    ////
1736
//// Public License along with this source; if not, download it   ////
1737
//// from http://www.opencores.org/lgpl.shtml                     ////
1738
////                                                              ////
1739
//////////////////////////////////////////////////////////////////////
1740
 
1741
// binary counter
1742
 
1743 40 unneback
`define MODULE cnt_bin_clear
1744
module `BASE`MODULE (
1745
`undef MODULE
1746
 clear, q, rst, clk);
1747
 
1748 22 unneback
   parameter length = 4;
1749
   input clear;
1750
   output [length:1] q;
1751
   input rst;
1752
   input clk;
1753
 
1754
   parameter clear_value = 0;
1755
   parameter set_value = 1;
1756
   parameter wrap_value = 0;
1757
   parameter level1_value = 15;
1758
 
1759
   reg  [length:1] qi;
1760
   wire [length:1] q_next;
1761
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1762
 
1763
   always @ (posedge clk or posedge rst)
1764
     if (rst)
1765
       qi <= {length{1'b0}};
1766
     else
1767
       qi <= q_next;
1768
 
1769
   assign q = qi;
1770
 
1771
endmodule
1772 40 unneback
`endif
1773
`ifdef CNT_BIN_CE
1774 22 unneback
//////////////////////////////////////////////////////////////////////
1775
////                                                              ////
1776
////  Versatile counter                                           ////
1777
////                                                              ////
1778
////  Description                                                 ////
1779
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1780
////  counter                                                     ////
1781
////                                                              ////
1782
////  To Do:                                                      ////
1783
////   - add LFSR with more taps                                  ////
1784
////                                                              ////
1785
////  Author(s):                                                  ////
1786
////      - Michael Unneback, unneback@opencores.org              ////
1787
////        ORSoC AB                                              ////
1788
////                                                              ////
1789
//////////////////////////////////////////////////////////////////////
1790
////                                                              ////
1791
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1792
////                                                              ////
1793
//// This source file may be used and distributed without         ////
1794
//// restriction provided that this copyright statement is not    ////
1795
//// removed from the file and that any derivative work contains  ////
1796
//// the original copyright notice and the associated disclaimer. ////
1797
////                                                              ////
1798
//// This source file is free software; you can redistribute it   ////
1799
//// and/or modify it under the terms of the GNU Lesser General   ////
1800
//// Public License as published by the Free Software Foundation; ////
1801
//// either version 2.1 of the License, or (at your option) any   ////
1802
//// later version.                                               ////
1803
////                                                              ////
1804
//// This source is distributed in the hope that it will be       ////
1805
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1806
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1807
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1808
//// details.                                                     ////
1809
////                                                              ////
1810
//// You should have received a copy of the GNU Lesser General    ////
1811
//// Public License along with this source; if not, download it   ////
1812
//// from http://www.opencores.org/lgpl.shtml                     ////
1813
////                                                              ////
1814
//////////////////////////////////////////////////////////////////////
1815
 
1816
// binary counter
1817 6 unneback
 
1818 40 unneback
`define MODULE cnt_bin_ce
1819
module `BASE`MODULE (
1820
`undef MODULE
1821
 cke, q, rst, clk);
1822
 
1823 6 unneback
   parameter length = 4;
1824
   input cke;
1825
   output [length:1] q;
1826
   input rst;
1827
   input clk;
1828
 
1829
   parameter clear_value = 0;
1830
   parameter set_value = 1;
1831
   parameter wrap_value = 0;
1832
   parameter level1_value = 15;
1833
 
1834
   reg  [length:1] qi;
1835
   wire [length:1] q_next;
1836
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1837
 
1838
   always @ (posedge clk or posedge rst)
1839
     if (rst)
1840
       qi <= {length{1'b0}};
1841
     else
1842
     if (cke)
1843
       qi <= q_next;
1844
 
1845
   assign q = qi;
1846
 
1847
endmodule
1848 40 unneback
`endif
1849
`ifdef CNT_BIN_CE_CLEAR
1850 6 unneback
//////////////////////////////////////////////////////////////////////
1851
////                                                              ////
1852
////  Versatile counter                                           ////
1853
////                                                              ////
1854
////  Description                                                 ////
1855
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1856
////  counter                                                     ////
1857
////                                                              ////
1858
////  To Do:                                                      ////
1859
////   - add LFSR with more taps                                  ////
1860
////                                                              ////
1861
////  Author(s):                                                  ////
1862
////      - Michael Unneback, unneback@opencores.org              ////
1863
////        ORSoC AB                                              ////
1864
////                                                              ////
1865
//////////////////////////////////////////////////////////////////////
1866
////                                                              ////
1867
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1868
////                                                              ////
1869
//// This source file may be used and distributed without         ////
1870
//// restriction provided that this copyright statement is not    ////
1871
//// removed from the file and that any derivative work contains  ////
1872
//// the original copyright notice and the associated disclaimer. ////
1873
////                                                              ////
1874
//// This source file is free software; you can redistribute it   ////
1875
//// and/or modify it under the terms of the GNU Lesser General   ////
1876
//// Public License as published by the Free Software Foundation; ////
1877
//// either version 2.1 of the License, or (at your option) any   ////
1878
//// later version.                                               ////
1879
////                                                              ////
1880
//// This source is distributed in the hope that it will be       ////
1881
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1882
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1883
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1884
//// details.                                                     ////
1885
////                                                              ////
1886
//// You should have received a copy of the GNU Lesser General    ////
1887
//// Public License along with this source; if not, download it   ////
1888
//// from http://www.opencores.org/lgpl.shtml                     ////
1889
////                                                              ////
1890
//////////////////////////////////////////////////////////////////////
1891
 
1892
// binary counter
1893
 
1894 40 unneback
`define MODULE cnt_bin_ce_clear
1895
module `BASE`MODULE (
1896
`undef MODULE
1897
 clear, cke, q, rst, clk);
1898
 
1899 6 unneback
   parameter length = 4;
1900
   input clear;
1901
   input cke;
1902
   output [length:1] q;
1903
   input rst;
1904
   input clk;
1905
 
1906
   parameter clear_value = 0;
1907
   parameter set_value = 1;
1908
   parameter wrap_value = 0;
1909
   parameter level1_value = 15;
1910
 
1911
   reg  [length:1] qi;
1912
   wire [length:1] q_next;
1913
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1914
 
1915
   always @ (posedge clk or posedge rst)
1916
     if (rst)
1917
       qi <= {length{1'b0}};
1918
     else
1919
     if (cke)
1920
       qi <= q_next;
1921
 
1922
   assign q = qi;
1923
 
1924
endmodule
1925 40 unneback
`endif
1926
`ifdef CNT_BIN_CE_CLEAR_L1_L2
1927 6 unneback
//////////////////////////////////////////////////////////////////////
1928
////                                                              ////
1929
////  Versatile counter                                           ////
1930
////                                                              ////
1931
////  Description                                                 ////
1932
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1933
////  counter                                                     ////
1934
////                                                              ////
1935
////  To Do:                                                      ////
1936
////   - add LFSR with more taps                                  ////
1937
////                                                              ////
1938
////  Author(s):                                                  ////
1939
////      - Michael Unneback, unneback@opencores.org              ////
1940
////        ORSoC AB                                              ////
1941
////                                                              ////
1942
//////////////////////////////////////////////////////////////////////
1943
////                                                              ////
1944
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1945
////                                                              ////
1946
//// This source file may be used and distributed without         ////
1947
//// restriction provided that this copyright statement is not    ////
1948
//// removed from the file and that any derivative work contains  ////
1949
//// the original copyright notice and the associated disclaimer. ////
1950
////                                                              ////
1951
//// This source file is free software; you can redistribute it   ////
1952
//// and/or modify it under the terms of the GNU Lesser General   ////
1953
//// Public License as published by the Free Software Foundation; ////
1954
//// either version 2.1 of the License, or (at your option) any   ////
1955
//// later version.                                               ////
1956
////                                                              ////
1957
//// This source is distributed in the hope that it will be       ////
1958
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1959
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1960
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1961
//// details.                                                     ////
1962
////                                                              ////
1963
//// You should have received a copy of the GNU Lesser General    ////
1964
//// Public License along with this source; if not, download it   ////
1965
//// from http://www.opencores.org/lgpl.shtml                     ////
1966
////                                                              ////
1967
//////////////////////////////////////////////////////////////////////
1968
 
1969
// binary counter
1970 29 unneback
 
1971 40 unneback
`define MODULE cnt_bin_ce_clear_l1_l2
1972
module `BASE`MODULE (
1973
`undef MODULE
1974
 clear, cke, q, level1, level2, rst, clk);
1975
 
1976 29 unneback
   parameter length = 4;
1977
   input clear;
1978
   input cke;
1979
   output [length:1] q;
1980
   output reg level1;
1981
   output reg level2;
1982
   input rst;
1983
   input clk;
1984
 
1985
   parameter clear_value = 0;
1986
   parameter set_value = 1;
1987 30 unneback
   parameter wrap_value = 15;
1988
   parameter level1_value = 8;
1989
   parameter level2_value = 15;
1990 29 unneback
 
1991
   wire rew;
1992 30 unneback
   assign rew = 1'b0;
1993 29 unneback
   reg  [length:1] qi;
1994
   wire [length:1] q_next;
1995
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1996
 
1997
   always @ (posedge clk or posedge rst)
1998
     if (rst)
1999
       qi <= {length{1'b0}};
2000
     else
2001
     if (cke)
2002
       qi <= q_next;
2003
 
2004
   assign q = qi;
2005
 
2006
 
2007
    always @ (posedge clk or posedge rst)
2008
    if (rst)
2009
        level1 <= 1'b0;
2010
    else
2011
    if (cke)
2012
    if (clear)
2013
        level1 <= 1'b0;
2014
    else if (q_next == level1_value)
2015
        level1 <= 1'b1;
2016
    else if (qi == level1_value & rew)
2017
        level1 <= 1'b0;
2018
 
2019
    always @ (posedge clk or posedge rst)
2020
    if (rst)
2021
        level2 <= 1'b0;
2022
    else
2023
    if (cke)
2024
    if (clear)
2025
        level2 <= 1'b0;
2026
    else if (q_next == level2_value)
2027
        level2 <= 1'b1;
2028
    else if (qi == level2_value & rew)
2029
        level2 <= 1'b0;
2030
endmodule
2031 40 unneback
`endif
2032
`ifdef CNT_BIN_CE_CLEAR_SET_REW
2033 29 unneback
//////////////////////////////////////////////////////////////////////
2034
////                                                              ////
2035
////  Versatile counter                                           ////
2036
////                                                              ////
2037
////  Description                                                 ////
2038
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2039
////  counter                                                     ////
2040
////                                                              ////
2041
////  To Do:                                                      ////
2042
////   - add LFSR with more taps                                  ////
2043
////                                                              ////
2044
////  Author(s):                                                  ////
2045
////      - Michael Unneback, unneback@opencores.org              ////
2046
////        ORSoC AB                                              ////
2047
////                                                              ////
2048
//////////////////////////////////////////////////////////////////////
2049
////                                                              ////
2050
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2051
////                                                              ////
2052
//// This source file may be used and distributed without         ////
2053
//// restriction provided that this copyright statement is not    ////
2054
//// removed from the file and that any derivative work contains  ////
2055
//// the original copyright notice and the associated disclaimer. ////
2056
////                                                              ////
2057
//// This source file is free software; you can redistribute it   ////
2058
//// and/or modify it under the terms of the GNU Lesser General   ////
2059
//// Public License as published by the Free Software Foundation; ////
2060
//// either version 2.1 of the License, or (at your option) any   ////
2061
//// later version.                                               ////
2062
////                                                              ////
2063
//// This source is distributed in the hope that it will be       ////
2064
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2065
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2066
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2067
//// details.                                                     ////
2068
////                                                              ////
2069
//// You should have received a copy of the GNU Lesser General    ////
2070
//// Public License along with this source; if not, download it   ////
2071
//// from http://www.opencores.org/lgpl.shtml                     ////
2072
////                                                              ////
2073
//////////////////////////////////////////////////////////////////////
2074
 
2075
// binary counter
2076 6 unneback
 
2077 40 unneback
`define MODULE cnt_bin_ce_clear_set_rew
2078
module `BASE`MODULE (
2079
`undef MODULE
2080
 clear, set, cke, rew, q, rst, clk);
2081
 
2082 6 unneback
   parameter length = 4;
2083
   input clear;
2084
   input set;
2085
   input cke;
2086
   input rew;
2087
   output [length:1] q;
2088
   input rst;
2089
   input clk;
2090
 
2091
   parameter clear_value = 0;
2092
   parameter set_value = 1;
2093
   parameter wrap_value = 0;
2094
   parameter level1_value = 15;
2095
 
2096
   reg  [length:1] qi;
2097
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2098
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
2099
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
2100
   assign q_next = rew ? q_next_rew : q_next_fw;
2101
 
2102
   always @ (posedge clk or posedge rst)
2103
     if (rst)
2104
       qi <= {length{1'b0}};
2105
     else
2106
     if (cke)
2107
       qi <= q_next;
2108
 
2109
   assign q = qi;
2110
 
2111
endmodule
2112 40 unneback
`endif
2113
`ifdef CNT_BIN_CE_REW_L1
2114 6 unneback
//////////////////////////////////////////////////////////////////////
2115
////                                                              ////
2116
////  Versatile counter                                           ////
2117
////                                                              ////
2118
////  Description                                                 ////
2119
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2120
////  counter                                                     ////
2121
////                                                              ////
2122
////  To Do:                                                      ////
2123
////   - add LFSR with more taps                                  ////
2124
////                                                              ////
2125
////  Author(s):                                                  ////
2126
////      - Michael Unneback, unneback@opencores.org              ////
2127
////        ORSoC AB                                              ////
2128
////                                                              ////
2129
//////////////////////////////////////////////////////////////////////
2130
////                                                              ////
2131
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2132
////                                                              ////
2133
//// This source file may be used and distributed without         ////
2134
//// restriction provided that this copyright statement is not    ////
2135
//// removed from the file and that any derivative work contains  ////
2136
//// the original copyright notice and the associated disclaimer. ////
2137
////                                                              ////
2138
//// This source file is free software; you can redistribute it   ////
2139
//// and/or modify it under the terms of the GNU Lesser General   ////
2140
//// Public License as published by the Free Software Foundation; ////
2141
//// either version 2.1 of the License, or (at your option) any   ////
2142
//// later version.                                               ////
2143
////                                                              ////
2144
//// This source is distributed in the hope that it will be       ////
2145
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2146
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2147
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2148
//// details.                                                     ////
2149
////                                                              ////
2150
//// You should have received a copy of the GNU Lesser General    ////
2151
//// Public License along with this source; if not, download it   ////
2152
//// from http://www.opencores.org/lgpl.shtml                     ////
2153
////                                                              ////
2154
//////////////////////////////////////////////////////////////////////
2155
 
2156
// binary counter
2157
 
2158 40 unneback
`define MODULE cnt_bin_ce_rew_l1
2159
module `BASE`MODULE (
2160
`undef MODULE
2161
 cke, rew, level1, rst, clk);
2162
 
2163 6 unneback
   parameter length = 4;
2164
   input cke;
2165
   input rew;
2166
   output reg level1;
2167
   input rst;
2168
   input clk;
2169
 
2170
   parameter clear_value = 0;
2171
   parameter set_value = 1;
2172
   parameter wrap_value = 1;
2173
   parameter level1_value = 15;
2174
 
2175 29 unneback
   wire clear;
2176 30 unneback
   assign clear = 1'b0;
2177 6 unneback
   reg  [length:1] qi;
2178
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2179
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2180
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2181
   assign q_next = rew ? q_next_rew : q_next_fw;
2182
 
2183
   always @ (posedge clk or posedge rst)
2184
     if (rst)
2185
       qi <= {length{1'b0}};
2186
     else
2187
     if (cke)
2188
       qi <= q_next;
2189
 
2190
 
2191
 
2192
    always @ (posedge clk or posedge rst)
2193
    if (rst)
2194
        level1 <= 1'b0;
2195
    else
2196
    if (cke)
2197 29 unneback
    if (clear)
2198
        level1 <= 1'b0;
2199
    else if (q_next == level1_value)
2200 6 unneback
        level1 <= 1'b1;
2201
    else if (qi == level1_value & rew)
2202
        level1 <= 1'b0;
2203
endmodule
2204 40 unneback
`endif
2205
`ifdef CNT_BIN_CE_REW_ZQ_L1
2206 6 unneback
//////////////////////////////////////////////////////////////////////
2207
////                                                              ////
2208
////  Versatile counter                                           ////
2209
////                                                              ////
2210
////  Description                                                 ////
2211
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2212
////  counter                                                     ////
2213
////                                                              ////
2214
////  To Do:                                                      ////
2215
////   - add LFSR with more taps                                  ////
2216
////                                                              ////
2217
////  Author(s):                                                  ////
2218
////      - Michael Unneback, unneback@opencores.org              ////
2219
////        ORSoC AB                                              ////
2220
////                                                              ////
2221
//////////////////////////////////////////////////////////////////////
2222
////                                                              ////
2223
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2224
////                                                              ////
2225
//// This source file may be used and distributed without         ////
2226
//// restriction provided that this copyright statement is not    ////
2227
//// removed from the file and that any derivative work contains  ////
2228
//// the original copyright notice and the associated disclaimer. ////
2229
////                                                              ////
2230
//// This source file is free software; you can redistribute it   ////
2231
//// and/or modify it under the terms of the GNU Lesser General   ////
2232
//// Public License as published by the Free Software Foundation; ////
2233
//// either version 2.1 of the License, or (at your option) any   ////
2234
//// later version.                                               ////
2235
////                                                              ////
2236
//// This source is distributed in the hope that it will be       ////
2237
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2238
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2239
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2240
//// details.                                                     ////
2241
////                                                              ////
2242
//// You should have received a copy of the GNU Lesser General    ////
2243
//// Public License along with this source; if not, download it   ////
2244
//// from http://www.opencores.org/lgpl.shtml                     ////
2245
////                                                              ////
2246
//////////////////////////////////////////////////////////////////////
2247
 
2248 25 unneback
// binary counter
2249
 
2250 40 unneback
`define MODULE cnt_bin_ce_rew_zq_l1
2251
module `BASE`MODULE (
2252
`undef MODULE
2253
 cke, rew, zq, level1, rst, clk);
2254
 
2255 25 unneback
   parameter length = 4;
2256
   input cke;
2257
   input rew;
2258
   output reg zq;
2259
   output reg level1;
2260
   input rst;
2261
   input clk;
2262
 
2263
   parameter clear_value = 0;
2264
   parameter set_value = 1;
2265
   parameter wrap_value = 1;
2266
   parameter level1_value = 15;
2267
 
2268 29 unneback
   wire clear;
2269 30 unneback
   assign clear = 1'b0;
2270 25 unneback
   reg  [length:1] qi;
2271
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2272
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2273
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2274
   assign q_next = rew ? q_next_rew : q_next_fw;
2275
 
2276
   always @ (posedge clk or posedge rst)
2277
     if (rst)
2278
       qi <= {length{1'b0}};
2279
     else
2280
     if (cke)
2281
       qi <= q_next;
2282
 
2283
 
2284
 
2285
   always @ (posedge clk or posedge rst)
2286
     if (rst)
2287
       zq <= 1'b1;
2288
     else
2289
     if (cke)
2290
       zq <= q_next == {length{1'b0}};
2291
 
2292
    always @ (posedge clk or posedge rst)
2293
    if (rst)
2294
        level1 <= 1'b0;
2295
    else
2296
    if (cke)
2297 29 unneback
    if (clear)
2298
        level1 <= 1'b0;
2299
    else if (q_next == level1_value)
2300 25 unneback
        level1 <= 1'b1;
2301
    else if (qi == level1_value & rew)
2302
        level1 <= 1'b0;
2303
endmodule
2304 40 unneback
`endif
2305
`ifdef CNT_BIN_CE_REW_Q_ZQ_L1
2306 25 unneback
//////////////////////////////////////////////////////////////////////
2307
////                                                              ////
2308
////  Versatile counter                                           ////
2309
////                                                              ////
2310
////  Description                                                 ////
2311
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2312
////  counter                                                     ////
2313
////                                                              ////
2314
////  To Do:                                                      ////
2315
////   - add LFSR with more taps                                  ////
2316
////                                                              ////
2317
////  Author(s):                                                  ////
2318
////      - Michael Unneback, unneback@opencores.org              ////
2319
////        ORSoC AB                                              ////
2320
////                                                              ////
2321
//////////////////////////////////////////////////////////////////////
2322
////                                                              ////
2323
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2324
////                                                              ////
2325
//// This source file may be used and distributed without         ////
2326
//// restriction provided that this copyright statement is not    ////
2327
//// removed from the file and that any derivative work contains  ////
2328
//// the original copyright notice and the associated disclaimer. ////
2329
////                                                              ////
2330
//// This source file is free software; you can redistribute it   ////
2331
//// and/or modify it under the terms of the GNU Lesser General   ////
2332
//// Public License as published by the Free Software Foundation; ////
2333
//// either version 2.1 of the License, or (at your option) any   ////
2334
//// later version.                                               ////
2335
////                                                              ////
2336
//// This source is distributed in the hope that it will be       ////
2337
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2338
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2339
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2340
//// details.                                                     ////
2341
////                                                              ////
2342
//// You should have received a copy of the GNU Lesser General    ////
2343
//// Public License along with this source; if not, download it   ////
2344
//// from http://www.opencores.org/lgpl.shtml                     ////
2345
////                                                              ////
2346
//////////////////////////////////////////////////////////////////////
2347
 
2348
// binary counter
2349
 
2350 40 unneback
`define MODULE cnt_bin_ce_rew_q_zq_l1
2351
module `BASE`MODULE (
2352
`undef MODULE
2353
 cke, rew, q, zq, level1, rst, clk);
2354
 
2355 25 unneback
   parameter length = 4;
2356
   input cke;
2357
   input rew;
2358
   output [length:1] q;
2359
   output reg zq;
2360
   output reg level1;
2361
   input rst;
2362
   input clk;
2363
 
2364
   parameter clear_value = 0;
2365
   parameter set_value = 1;
2366
   parameter wrap_value = 1;
2367
   parameter level1_value = 15;
2368
 
2369 29 unneback
   wire clear;
2370 30 unneback
   assign clear = 1'b0;
2371 25 unneback
   reg  [length:1] qi;
2372
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2373
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2374
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2375
   assign q_next = rew ? q_next_rew : q_next_fw;
2376
 
2377
   always @ (posedge clk or posedge rst)
2378
     if (rst)
2379
       qi <= {length{1'b0}};
2380
     else
2381
     if (cke)
2382
       qi <= q_next;
2383
 
2384
   assign q = qi;
2385
 
2386
 
2387
   always @ (posedge clk or posedge rst)
2388
     if (rst)
2389
       zq <= 1'b1;
2390
     else
2391
     if (cke)
2392
       zq <= q_next == {length{1'b0}};
2393
 
2394
    always @ (posedge clk or posedge rst)
2395
    if (rst)
2396
        level1 <= 1'b0;
2397
    else
2398
    if (cke)
2399 29 unneback
    if (clear)
2400
        level1 <= 1'b0;
2401
    else if (q_next == level1_value)
2402 25 unneback
        level1 <= 1'b1;
2403
    else if (qi == level1_value & rew)
2404
        level1 <= 1'b0;
2405
endmodule
2406 40 unneback
`endif
2407
`ifdef CNT_LFSR_ZQ
2408 25 unneback
//////////////////////////////////////////////////////////////////////
2409
////                                                              ////
2410
////  Versatile counter                                           ////
2411
////                                                              ////
2412
////  Description                                                 ////
2413
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2414
////  counter                                                     ////
2415
////                                                              ////
2416
////  To Do:                                                      ////
2417
////   - add LFSR with more taps                                  ////
2418
////                                                              ////
2419
////  Author(s):                                                  ////
2420
////      - Michael Unneback, unneback@opencores.org              ////
2421
////        ORSoC AB                                              ////
2422
////                                                              ////
2423
//////////////////////////////////////////////////////////////////////
2424
////                                                              ////
2425
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2426
////                                                              ////
2427
//// This source file may be used and distributed without         ////
2428
//// restriction provided that this copyright statement is not    ////
2429
//// removed from the file and that any derivative work contains  ////
2430
//// the original copyright notice and the associated disclaimer. ////
2431
////                                                              ////
2432
//// This source file is free software; you can redistribute it   ////
2433
//// and/or modify it under the terms of the GNU Lesser General   ////
2434
//// Public License as published by the Free Software Foundation; ////
2435
//// either version 2.1 of the License, or (at your option) any   ////
2436
//// later version.                                               ////
2437
////                                                              ////
2438
//// This source is distributed in the hope that it will be       ////
2439
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2440
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2441
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2442
//// details.                                                     ////
2443
////                                                              ////
2444
//// You should have received a copy of the GNU Lesser General    ////
2445
//// Public License along with this source; if not, download it   ////
2446
//// from http://www.opencores.org/lgpl.shtml                     ////
2447
////                                                              ////
2448
//////////////////////////////////////////////////////////////////////
2449
 
2450 6 unneback
// LFSR counter
2451
 
2452 40 unneback
`define MODULE cnt_lfsr_zq
2453
module `BASE`MODULE (
2454
`undef MODULE
2455
 zq, rst, clk);
2456
 
2457 6 unneback
   parameter length = 4;
2458
   output reg zq;
2459
   input rst;
2460
   input clk;
2461
 
2462
   parameter clear_value = 0;
2463
   parameter set_value = 1;
2464
   parameter wrap_value = 8;
2465
   parameter level1_value = 15;
2466
 
2467
   reg  [length:1] qi;
2468
   reg lfsr_fb;
2469
   wire [length:1] q_next;
2470
   reg [32:1] polynom;
2471
   integer i;
2472
 
2473
   always @ (qi)
2474
   begin
2475
        case (length)
2476
         2: polynom = 32'b11;                               // 0x3
2477
         3: polynom = 32'b110;                              // 0x6
2478
         4: polynom = 32'b1100;                             // 0xC
2479
         5: polynom = 32'b10100;                            // 0x14
2480
         6: polynom = 32'b110000;                           // 0x30
2481
         7: polynom = 32'b1100000;                          // 0x60
2482
         8: polynom = 32'b10111000;                         // 0xb8
2483
         9: polynom = 32'b100010000;                        // 0x110
2484
        10: polynom = 32'b1001000000;                       // 0x240
2485
        11: polynom = 32'b10100000000;                      // 0x500
2486
        12: polynom = 32'b100000101001;                     // 0x829
2487
        13: polynom = 32'b1000000001100;                    // 0x100C
2488
        14: polynom = 32'b10000000010101;                   // 0x2015
2489
        15: polynom = 32'b110000000000000;                  // 0x6000
2490
        16: polynom = 32'b1101000000001000;                 // 0xD008
2491
        17: polynom = 32'b10010000000000000;                // 0x12000
2492
        18: polynom = 32'b100000010000000000;               // 0x20400
2493
        19: polynom = 32'b1000000000000100011;              // 0x40023
2494 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2495 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2496
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2497
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2498
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2499
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2500
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2501
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2502
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2503
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2504
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2505
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2506
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2507
        default: polynom = 32'b0;
2508
        endcase
2509
        lfsr_fb = qi[length];
2510
        for (i=length-1; i>=1; i=i-1) begin
2511
            if (polynom[i])
2512
                lfsr_fb = lfsr_fb  ~^ qi[i];
2513
        end
2514
    end
2515
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2516
 
2517
   always @ (posedge clk or posedge rst)
2518
     if (rst)
2519
       qi <= {length{1'b0}};
2520
     else
2521
       qi <= q_next;
2522
 
2523
 
2524
 
2525
   always @ (posedge clk or posedge rst)
2526
     if (rst)
2527
       zq <= 1'b1;
2528
     else
2529
       zq <= q_next == {length{1'b0}};
2530
endmodule
2531 40 unneback
`endif
2532 75 unneback
`ifdef CNT_LFSR_CE
2533
//////////////////////////////////////////////////////////////////////
2534
////                                                              ////
2535
////  Versatile counter                                           ////
2536
////                                                              ////
2537
////  Description                                                 ////
2538
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2539
////  counter                                                     ////
2540
////                                                              ////
2541
////  To Do:                                                      ////
2542
////   - add LFSR with more taps                                  ////
2543
////                                                              ////
2544
////  Author(s):                                                  ////
2545
////      - Michael Unneback, unneback@opencores.org              ////
2546
////        ORSoC AB                                              ////
2547
////                                                              ////
2548
//////////////////////////////////////////////////////////////////////
2549
////                                                              ////
2550
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2551
////                                                              ////
2552
//// This source file may be used and distributed without         ////
2553
//// restriction provided that this copyright statement is not    ////
2554
//// removed from the file and that any derivative work contains  ////
2555
//// the original copyright notice and the associated disclaimer. ////
2556
////                                                              ////
2557
//// This source file is free software; you can redistribute it   ////
2558
//// and/or modify it under the terms of the GNU Lesser General   ////
2559
//// Public License as published by the Free Software Foundation; ////
2560
//// either version 2.1 of the License, or (at your option) any   ////
2561
//// later version.                                               ////
2562
////                                                              ////
2563
//// This source is distributed in the hope that it will be       ////
2564
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2565
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2566
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2567
//// details.                                                     ////
2568
////                                                              ////
2569
//// You should have received a copy of the GNU Lesser General    ////
2570
//// Public License along with this source; if not, download it   ////
2571
//// from http://www.opencores.org/lgpl.shtml                     ////
2572
////                                                              ////
2573
//////////////////////////////////////////////////////////////////////
2574
 
2575
// LFSR counter
2576
 
2577
`define MODULE cnt_lfsr_ce
2578
module `BASE`MODULE (
2579
`undef MODULE
2580
 cke, zq, rst, clk);
2581
 
2582
   parameter length = 4;
2583
   input cke;
2584
   output reg zq;
2585
   input rst;
2586
   input clk;
2587
 
2588
   parameter clear_value = 0;
2589
   parameter set_value = 1;
2590
   parameter wrap_value = 0;
2591
   parameter level1_value = 15;
2592
 
2593
   reg  [length:1] qi;
2594
   reg lfsr_fb;
2595
   wire [length:1] q_next;
2596
   reg [32:1] polynom;
2597
   integer i;
2598
 
2599
   always @ (qi)
2600
   begin
2601
        case (length)
2602
         2: polynom = 32'b11;                               // 0x3
2603
         3: polynom = 32'b110;                              // 0x6
2604
         4: polynom = 32'b1100;                             // 0xC
2605
         5: polynom = 32'b10100;                            // 0x14
2606
         6: polynom = 32'b110000;                           // 0x30
2607
         7: polynom = 32'b1100000;                          // 0x60
2608
         8: polynom = 32'b10111000;                         // 0xb8
2609
         9: polynom = 32'b100010000;                        // 0x110
2610
        10: polynom = 32'b1001000000;                       // 0x240
2611
        11: polynom = 32'b10100000000;                      // 0x500
2612
        12: polynom = 32'b100000101001;                     // 0x829
2613
        13: polynom = 32'b1000000001100;                    // 0x100C
2614
        14: polynom = 32'b10000000010101;                   // 0x2015
2615
        15: polynom = 32'b110000000000000;                  // 0x6000
2616
        16: polynom = 32'b1101000000001000;                 // 0xD008
2617
        17: polynom = 32'b10010000000000000;                // 0x12000
2618
        18: polynom = 32'b100000010000000000;               // 0x20400
2619
        19: polynom = 32'b1000000000000100011;              // 0x40023
2620
        20: polynom = 32'b10010000000000000000;             // 0x90000
2621
        21: polynom = 32'b101000000000000000000;            // 0x140000
2622
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2623
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2624
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2625
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2626
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2627
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2628
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2629
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2630
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2631
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2632
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2633
        default: polynom = 32'b0;
2634
        endcase
2635
        lfsr_fb = qi[length];
2636
        for (i=length-1; i>=1; i=i-1) begin
2637
            if (polynom[i])
2638
                lfsr_fb = lfsr_fb  ~^ qi[i];
2639
        end
2640
    end
2641
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2642
 
2643
   always @ (posedge clk or posedge rst)
2644
     if (rst)
2645
       qi <= {length{1'b0}};
2646
     else
2647
     if (cke)
2648
       qi <= q_next;
2649
 
2650
 
2651
 
2652
   always @ (posedge clk or posedge rst)
2653
     if (rst)
2654
       zq <= 1'b1;
2655
     else
2656
     if (cke)
2657
       zq <= q_next == {length{1'b0}};
2658
endmodule
2659
`endif
2660 40 unneback
`ifdef CNT_LFSR_CE_ZQ
2661 6 unneback
//////////////////////////////////////////////////////////////////////
2662
////                                                              ////
2663
////  Versatile counter                                           ////
2664
////                                                              ////
2665
////  Description                                                 ////
2666
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2667
////  counter                                                     ////
2668
////                                                              ////
2669
////  To Do:                                                      ////
2670
////   - add LFSR with more taps                                  ////
2671
////                                                              ////
2672
////  Author(s):                                                  ////
2673
////      - Michael Unneback, unneback@opencores.org              ////
2674
////        ORSoC AB                                              ////
2675
////                                                              ////
2676
//////////////////////////////////////////////////////////////////////
2677
////                                                              ////
2678
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2679
////                                                              ////
2680
//// This source file may be used and distributed without         ////
2681
//// restriction provided that this copyright statement is not    ////
2682
//// removed from the file and that any derivative work contains  ////
2683
//// the original copyright notice and the associated disclaimer. ////
2684
////                                                              ////
2685
//// This source file is free software; you can redistribute it   ////
2686
//// and/or modify it under the terms of the GNU Lesser General   ////
2687
//// Public License as published by the Free Software Foundation; ////
2688
//// either version 2.1 of the License, or (at your option) any   ////
2689
//// later version.                                               ////
2690
////                                                              ////
2691
//// This source is distributed in the hope that it will be       ////
2692
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2693
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2694
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2695
//// details.                                                     ////
2696
////                                                              ////
2697
//// You should have received a copy of the GNU Lesser General    ////
2698
//// Public License along with this source; if not, download it   ////
2699
//// from http://www.opencores.org/lgpl.shtml                     ////
2700
////                                                              ////
2701
//////////////////////////////////////////////////////////////////////
2702
 
2703
// LFSR counter
2704
 
2705 40 unneback
`define MODULE cnt_lfsr_ce_zq
2706
module `BASE`MODULE (
2707
`undef MODULE
2708
 cke, zq, rst, clk);
2709
 
2710 6 unneback
   parameter length = 4;
2711
   input cke;
2712
   output reg zq;
2713
   input rst;
2714
   input clk;
2715
 
2716
   parameter clear_value = 0;
2717
   parameter set_value = 1;
2718
   parameter wrap_value = 8;
2719
   parameter level1_value = 15;
2720
 
2721
   reg  [length:1] qi;
2722
   reg lfsr_fb;
2723
   wire [length:1] q_next;
2724
   reg [32:1] polynom;
2725
   integer i;
2726
 
2727
   always @ (qi)
2728
   begin
2729
        case (length)
2730
         2: polynom = 32'b11;                               // 0x3
2731
         3: polynom = 32'b110;                              // 0x6
2732
         4: polynom = 32'b1100;                             // 0xC
2733
         5: polynom = 32'b10100;                            // 0x14
2734
         6: polynom = 32'b110000;                           // 0x30
2735
         7: polynom = 32'b1100000;                          // 0x60
2736
         8: polynom = 32'b10111000;                         // 0xb8
2737
         9: polynom = 32'b100010000;                        // 0x110
2738
        10: polynom = 32'b1001000000;                       // 0x240
2739
        11: polynom = 32'b10100000000;                      // 0x500
2740
        12: polynom = 32'b100000101001;                     // 0x829
2741
        13: polynom = 32'b1000000001100;                    // 0x100C
2742
        14: polynom = 32'b10000000010101;                   // 0x2015
2743
        15: polynom = 32'b110000000000000;                  // 0x6000
2744
        16: polynom = 32'b1101000000001000;                 // 0xD008
2745
        17: polynom = 32'b10010000000000000;                // 0x12000
2746
        18: polynom = 32'b100000010000000000;               // 0x20400
2747
        19: polynom = 32'b1000000000000100011;              // 0x40023
2748 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2749 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2750
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2751
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2752
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2753
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2754
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2755
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2756
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2757
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2758
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2759
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2760
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2761
        default: polynom = 32'b0;
2762
        endcase
2763
        lfsr_fb = qi[length];
2764
        for (i=length-1; i>=1; i=i-1) begin
2765
            if (polynom[i])
2766
                lfsr_fb = lfsr_fb  ~^ qi[i];
2767
        end
2768
    end
2769
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2770
 
2771
   always @ (posedge clk or posedge rst)
2772
     if (rst)
2773
       qi <= {length{1'b0}};
2774
     else
2775
     if (cke)
2776
       qi <= q_next;
2777
 
2778
 
2779
 
2780
   always @ (posedge clk or posedge rst)
2781
     if (rst)
2782
       zq <= 1'b1;
2783
     else
2784
     if (cke)
2785
       zq <= q_next == {length{1'b0}};
2786
endmodule
2787 40 unneback
`endif
2788
`ifdef CNT_LFSR_CE_Q
2789 6 unneback
//////////////////////////////////////////////////////////////////////
2790
////                                                              ////
2791
////  Versatile counter                                           ////
2792
////                                                              ////
2793
////  Description                                                 ////
2794
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2795
////  counter                                                     ////
2796
////                                                              ////
2797
////  To Do:                                                      ////
2798
////   - add LFSR with more taps                                  ////
2799
////                                                              ////
2800
////  Author(s):                                                  ////
2801
////      - Michael Unneback, unneback@opencores.org              ////
2802
////        ORSoC AB                                              ////
2803
////                                                              ////
2804
//////////////////////////////////////////////////////////////////////
2805
////                                                              ////
2806
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2807
////                                                              ////
2808
//// This source file may be used and distributed without         ////
2809
//// restriction provided that this copyright statement is not    ////
2810
//// removed from the file and that any derivative work contains  ////
2811
//// the original copyright notice and the associated disclaimer. ////
2812
////                                                              ////
2813
//// This source file is free software; you can redistribute it   ////
2814
//// and/or modify it under the terms of the GNU Lesser General   ////
2815
//// Public License as published by the Free Software Foundation; ////
2816
//// either version 2.1 of the License, or (at your option) any   ////
2817
//// later version.                                               ////
2818
////                                                              ////
2819
//// This source is distributed in the hope that it will be       ////
2820
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2821
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2822
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2823
//// details.                                                     ////
2824
////                                                              ////
2825
//// You should have received a copy of the GNU Lesser General    ////
2826
//// Public License along with this source; if not, download it   ////
2827
//// from http://www.opencores.org/lgpl.shtml                     ////
2828
////                                                              ////
2829
//////////////////////////////////////////////////////////////////////
2830 22 unneback
 
28