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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Blame information for rev 103

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Line No. Rev Author Line
1 40 unneback
`ifndef BASE
2
`define BASE vl_
3
`endif
4
 
5 60 unneback
// default SYN_KEEP definition
6
`define SYN_KEEP /*synthesis syn_keep = 1*/
7
 
8 44 unneback
`ifdef ACTEL
9 60 unneback
`undef SYN_KEEP
10 44 unneback
`define SYN_KEEP /*synthesis syn_keep = 1*/
11
`endif
12
 
13 98 unneback
`ifdef ACTEL
14
    // ACTEL FPGA should not use logic to handle rw collision
15
    `define SYN_NO_RW_CHECK /*synthesis syn_ramstyle = "no_rw_check"*/
16
`else
17
    `define SYN_NO_RW_CHECK
18
`endif
19
 
20 40 unneback
`ifdef ALL
21
 
22
`define GBUF
23
`define SYNC_RST
24
`define PLL
25
 
26
`define MULTS
27
`define MULTS18X18
28
`define MULT
29
`define SHIFT_UNIT_32
30
`define LOGIC_UNIT
31
 
32
`define CNT_SHREG_WRAP
33
`define CNT_SHREG_CE_WRAP
34
`define CNT_SHREG_CE_CLEAR
35
`define CNT_SHREG_CE_CLEAR_WRAP
36
 
37
`define MUX_ANDOR
38
`define MUX2_ANDOR
39
`define MUX3_ANDOR
40
`define MUX4_ANDOR
41
`define MUX5_ANDOR
42
`define MUX6_ANDOR
43 43 unneback
`define PARITY
44 40 unneback
 
45
`define ROM_INIT
46
`define RAM
47
`define RAM_BE
48
`define DPRAM_1R1W
49
`define DPRAM_2R1W
50 100 unneback
`define DPRAM_1R2W
51 40 unneback
`define DPRAM_2R2W
52 75 unneback
`define DPRAM_BE_2R2W
53 40 unneback
`define FIFO_1R1W_FILL_LEVEL_SYNC
54
`define FIFO_2R2W_SYNC_SIMPLEX
55
`define FIFO_CMP_ASYNC
56
`define FIFO_1R1W_ASYNC
57
`define FIFO_2R2W_ASYNC
58
`define FIFO_2R2W_ASYNC_SIMPLEX
59 48 unneback
`define REG_FILE
60 40 unneback
 
61
`define DFF
62
`define DFF_ARRAY
63
`define DFF_CE
64
`define DFF_CE_CLEAR
65
`define DF_CE_SET
66
`define SPR
67
`define SRP
68
`define DFF_SR
69
`define LATCH
70
`define SHREG
71
`define SHREG_CE
72
`define DELAY
73
`define DELAY_EMPTYFLAG
74 94 unneback
`define PULSE2TOGGLE
75
`define TOGGLE2PULSE
76
`define SYNCHRONIZER
77
`define CDC
78 40 unneback
 
79 75 unneback
`define WB3AVALON_BRIDGE
80 40 unneback
`define WB3WB3_BRIDGE
81
`define WB3_ARBITER_TYPE1
82 83 unneback
`define WB_ADR_INC
83 101 unneback
`define WB_RAM
84 103 unneback
`define WB_SHADOW_RAM
85 48 unneback
`define WB_B4_ROM
86 40 unneback
`define WB_BOOT_ROM
87
`define WB_DPRAM
88 101 unneback
`define WB_CACHE
89 103 unneback
`define WB_AVALON_BRIDGE
90
`define WB_AVALON_MEM_CACHE
91 40 unneback
 
92 44 unneback
`define IO_DFF_OE
93
`define O_DFF
94
 
95 40 unneback
`endif
96
 
97
`ifdef PLL
98
`ifndef SYNC_RST
99
`define SYNC_RST
100
`endif
101
`endif
102
 
103
`ifdef SYNC_RST
104
`ifndef GBUF
105
`define GBUF
106
`endif
107
`endif
108
 
109 92 unneback
`ifdef WB_B3_DPRAM
110
`ifndef WB_ADR_INC
111
`define WB_ADR_INC
112 40 unneback
`endif
113 92 unneback
`ifndef DPRAM_BE_2R2W
114
`define DPRAM_BE_2R2W
115 40 unneback
`endif
116
`endif
117
 
118 101 unneback
`ifdef WB_RAM
119 83 unneback
`ifndef WB_ADR_INC
120
`define WB_ADR_INC
121 62 unneback
`endif
122
`ifndef RAM_BE
123
`define RAM_BE
124
`endif
125
`endif
126
 
127 40 unneback
`ifdef WB3_ARBITER_TYPE1
128 42 unneback
`ifndef SPR
129
`define SPR
130
`endif
131 40 unneback
`ifndef MUX_ANDOR
132
`define MUX_ANDOR
133
`endif
134
`endif
135
 
136 76 unneback
`ifdef WB3AVALON_BRIDGE
137
`ifndef WB3WB3_BRIDGE
138
`define WB3WB3_BRIDGE
139
`endif
140
`endif
141
 
142 40 unneback
`ifdef WB3WB3_BRIDGE
143
`ifndef CNT_SHREG_CE_CLEAR
144
`define CNT_SHREG_CE_CLEAR
145
`endif
146
`ifndef DFF
147
`define DFF
148
`endif
149
`ifndef DFF_CE
150
`define DFF_CE
151
`endif
152
`ifndef CNT_SHREG_CE_CLEAR
153
`define CNT_SHREG_CE_CLEAR
154
`endif
155
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
156
`define FIFO_2R2W_ASYNC_SIMPLEX
157
`endif
158
`endif
159
 
160 103 unneback
 
161
`ifdef WB_AVALON_MEM_CACHE
162
`ifndef WB_SHADOW_RAM
163
`define WB_SHADOW_RAM
164
`endif
165
`ifndef WB_CACHE
166
`define WB_CACHE
167
`endif
168
`ifndef WB_AVALON_BRIDGE
169
`define WB_AVALON_BRIDGE
170
`endif
171
`endif
172
 
173 101 unneback
`ifdef WB_CACHE
174 100 unneback
`ifndef RAM
175
`define RAM
176
`endif
177
`ifndef WB_ADR_INC
178
`define WB_ADR_INC
179
`endif
180
`ifndef DPRAM_1R1W
181
`define DPRAM_1R1W
182
`endif
183
`ifndef DPRAM_1R2W
184
`define DPRAM_1R2W
185
`endif
186
`ifndef DPRAM_BE_2R2W
187
`define DPRAM_BE_2R2W
188
`endif
189
`ifndef CDC
190
`define CDC
191
`endif
192
`endif
193 103 unneback
 
194
`ifdef WB_SHADOW_RAM
195
`ifndef WB_RAM
196
`define WB_RAM
197
`endif
198
`endif
199
 
200
`ifdef WB_RAM
201
`ifndef WB_ADR_INC
202
`define WB_ADR_INC
203
`endif
204
`endif
205 97 unneback
 
206 40 unneback
`ifdef MULTS18X18
207
`ifndef MULTS
208
`define MULTS
209
`endif
210
`endif
211
 
212
`ifdef SHIFT_UNIT_32
213
`ifndef MULTS
214
`define MULTS
215
`endif
216
`endif
217
 
218
`ifdef MUX2_ANDOR
219
`ifndef MUX_ANDOR
220
`define MUX_ANDOR
221
`endif
222
`endif
223
 
224
`ifdef MUX3_ANDOR
225
`ifndef MUX_ANDOR
226
`define MUX_ANDOR
227
`endif
228
`endif
229
 
230
`ifdef MUX4_ANDOR
231
`ifndef MUX_ANDOR
232
`define MUX_ANDOR
233
`endif
234
`endif
235
 
236
`ifdef MUX5_ANDOR
237
`ifndef MUX_ANDOR
238
`define MUX_ANDOR
239
`endif
240
`endif
241
 
242
`ifdef MUX6_ANDOR
243
`ifndef MUX_ANDOR
244
`define MUX_ANDOR
245
`endif
246
`endif
247
 
248
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
249
`ifndef CNT_BIN_CE
250
`define CNT_BIN_CE
251
`endif
252
`ifndef DPRAM_1R1W
253
`define DPRAM_1R1W
254
`endif
255
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
256
`define CNT_BIN_CE_REW_Q_ZQ_L1
257
`endif
258
`endif
259
 
260
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
261
`ifndef CNT_LFSR_CE
262
`define CNT_LFSR_CE
263
`endif
264
`ifndef DPRAM_2R2W
265
`define DPRAM_2R2W
266
`endif
267
`ifndef CNT_BIN_CE_REW_ZQ_L1
268
`define CNT_BIN_CE_REW_ZQ_L1
269
`endif
270
`endif
271
 
272
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
273
`ifndef CNT_GRAY_CE_BIN
274
`define CNT_GRAY_CE_BIN
275
`endif
276
`ifndef DPRAM_2R2W
277
`define DPRAM_2R2W
278
`endif
279
`ifndef FIFO_CMP_ASYNC
280
`define FIFO_CMP_ASYNC
281
`endif
282
`endif
283
 
284
`ifdef FIFO_2R2W_ASYNC
285
`ifndef FIFO_1R1W_ASYNC
286
`define FIFO_1R1W_ASYNC
287
`endif
288
`endif
289
 
290
`ifdef FIFO_1R1W_ASYNC
291
`ifndef CNT_GRAY_CE_BIN
292
`define CNT_GRAY_CE_BIN
293
`endif
294
`ifndef DPRAM_1R1W
295
`define DPRAM_1R1W
296
`endif
297
`ifndef FIFO_CMP_ASYNC
298
`define FIFO_CMP_ASYNC
299
`endif
300
`endif
301
 
302
`ifdef FIFO_CMP_ASYNC
303
`ifndef DFF_SR
304
`define DFF_SR
305
`endif
306
`ifndef DFF
307
`define DFF
308
`endif
309
`endif
310 48 unneback
 
311
`ifdef REG_FILE
312
`ifndef DPRAM_1R1W
313
`define DPRAM_1R1W
314
`endif
315
`endif
316 97 unneback
 
317 98 unneback
`ifdef CDC
318
`ifndef PULSE2TOGGLE
319
`define PULSE2TOGGLE
320
`endif
321
`ifndef TOGGLE2PULSE
322
`define TOGGLE2PULSE
323
`endif
324
`ifndef SYNCHRONIZER
325
`define SYNCHRONIZER
326
`endif
327
`endif
328
 
329 97 unneback
// size to width
330 100 unneback
`define SIZE2WIDTH_EXPR = (`SIZE2WIDTH==1) ? 0 : (`SIZE2WIDTH==2) ? 1 : (`SIZE2WIDTH==4) ? 2 : (`SIZE2WIDTH==8) ? 3 : (`SIZE2WIDTH==16) ? 4 : (`SIZE2WIDTH==32) ? 5 : (`SIZE2WIDTH==64) ? 6 : (`SIZE2WIDTH==128) ? 7 : 8;
331 62 unneback
//////////////////////////////////////////////////////////////////////
332 6 unneback
////                                                              ////
333
////  Versatile library, clock and reset                          ////
334
////                                                              ////
335
////  Description                                                 ////
336
////  Logic related to clock and reset                            ////
337
////                                                              ////
338
////                                                              ////
339
////  To Do:                                                      ////
340
////   - add more different registers                             ////
341
////                                                              ////
342
////  Author(s):                                                  ////
343
////      - Michael Unneback, unneback@opencores.org              ////
344
////        ORSoC AB                                              ////
345
////                                                              ////
346
//////////////////////////////////////////////////////////////////////
347
////                                                              ////
348
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
349
////                                                              ////
350
//// This source file may be used and distributed without         ////
351
//// restriction provided that this copyright statement is not    ////
352
//// removed from the file and that any derivative work contains  ////
353
//// the original copyright notice and the associated disclaimer. ////
354
////                                                              ////
355
//// This source file is free software; you can redistribute it   ////
356
//// and/or modify it under the terms of the GNU Lesser General   ////
357
//// Public License as published by the Free Software Foundation; ////
358
//// either version 2.1 of the License, or (at your option) any   ////
359
//// later version.                                               ////
360
////                                                              ////
361
//// This source is distributed in the hope that it will be       ////
362
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
363
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
364
//// PURPOSE.  See the GNU Lesser General Public License for more ////
365
//// details.                                                     ////
366
////                                                              ////
367
//// You should have received a copy of the GNU Lesser General    ////
368
//// Public License along with this source; if not, download it   ////
369
//// from http://www.opencores.org/lgpl.shtml                     ////
370
////                                                              ////
371
//////////////////////////////////////////////////////////////////////
372
 
373 48 unneback
`ifdef ACTEL
374
`ifdef GBUF
375
`timescale 1 ns/100 ps
376 6 unneback
// Global buffer
377
// usage:
378
// use to enable global buffers for high fan out signals such as clock and reset
379
// Version: 8.4 8.4.0.33
380
module gbuf(GL,CLK);
381
output GL;
382
input  CLK;
383
 
384
    wire GND;
385
 
386
    GND GND_1_net(.Y(GND));
387
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
388
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
389
 
390
endmodule
391
`timescale 1 ns/1 ns
392 40 unneback
`define MODULE gbuf
393
module `BASE`MODULE ( i, o);
394
`undef MODULE
395 6 unneback
input i;
396
output o;
397
`ifdef SIM_GBUF
398
assign o=i;
399
`else
400
gbuf gbuf_i0 ( .CLK(i), .GL(o));
401
`endif
402
endmodule
403 40 unneback
`endif
404 33 unneback
 
405 6 unneback
`else
406 33 unneback
 
407 40 unneback
`ifdef ALTERA
408
`ifdef GBUF
409 21 unneback
//altera
410 40 unneback
`define MODULE gbuf
411
module `BASE`MODULE ( i, o);
412
`undef MODULE
413 33 unneback
input i;
414
output o;
415
assign o = i;
416
endmodule
417 40 unneback
`endif
418 33 unneback
 
419 6 unneback
`else
420
 
421 40 unneback
`ifdef GBUF
422 6 unneback
`timescale 1 ns/100 ps
423 40 unneback
`define MODULE
424
module `BASE`MODULE ( i, o);
425
`undef MODULE
426 6 unneback
input i;
427
output o;
428
assign o = i;
429
endmodule
430 40 unneback
`endif
431 6 unneback
`endif // ALTERA
432
`endif //ACTEL
433
 
434 40 unneback
`ifdef SYNC_RST
435 6 unneback
// sync reset
436 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
437 6 unneback
// output active high global reset sync with two DFFs 
438
`timescale 1 ns/100 ps
439 40 unneback
`define MODULE sync_rst
440
module `BASE`MODULE ( rst_n_i, rst_o, clk);
441
`undef MODULE
442 6 unneback
input rst_n_i, clk;
443
output rst_o;
444 18 unneback
reg [1:0] tmp;
445 6 unneback
always @ (posedge clk or negedge rst_n_i)
446
if (!rst_n_i)
447 17 unneback
        tmp <= 2'b11;
448 6 unneback
else
449 33 unneback
        tmp <= {1'b0,tmp[1]};
450 40 unneback
`define MODULE gbuf
451
`BASE`MODULE buf_i0( .i(tmp[0]), .o(rst_o));
452
`undef MODULE
453 6 unneback
endmodule
454 40 unneback
`endif
455 6 unneback
 
456 40 unneback
`ifdef PLL
457 6 unneback
// vl_pll
458
`ifdef ACTEL
459 32 unneback
///////////////////////////////////////////////////////////////////////////////
460 17 unneback
`timescale 1 ps/1 ps
461 40 unneback
`define MODULE pll
462
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
463
`undef MODULE
464 6 unneback
parameter index = 0;
465
parameter number_of_clk = 1;
466 17 unneback
parameter period_time_0 = 20000;
467
parameter period_time_1 = 20000;
468
parameter period_time_2 = 20000;
469
parameter lock_delay = 2000000;
470 6 unneback
input clk_i, rst_n_i;
471
output lock;
472
output reg [0:number_of_clk-1] clk_o;
473
output [0:number_of_clk-1] rst_o;
474
 
475
`ifdef SIM_PLL
476
 
477
always
478
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
479
 
480
generate if (number_of_clk > 1)
481
always
482
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
483
endgenerate
484
 
485
generate if (number_of_clk > 2)
486
always
487
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
488
endgenerate
489
 
490
genvar i;
491
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
492
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
493
end
494
endgenerate
495
 
496
assign #lock_delay lock = rst_n_i;
497
 
498
endmodule
499
`else
500
generate if (number_of_clk==1 & index==0) begin
501
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
502
end
503
endgenerate // index==0
504
generate if (number_of_clk==1 & index==1) begin
505
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
506
end
507
endgenerate // index==1
508
generate if (number_of_clk==1 & index==2) begin
509
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
510
end
511
endgenerate // index==2
512
generate if (number_of_clk==1 & index==3) begin
513
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
514
end
515
endgenerate // index==0
516
 
517
generate if (number_of_clk==2 & index==0) begin
518
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
519
end
520
endgenerate // index==0
521
generate if (number_of_clk==2 & index==1) begin
522
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
523
end
524
endgenerate // index==1
525
generate if (number_of_clk==2 & index==2) begin
526
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
527
end
528
endgenerate // index==2
529
generate if (number_of_clk==2 & index==3) begin
530
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
531
end
532
endgenerate // index==0
533
 
534
generate if (number_of_clk==3 & index==0) begin
535
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
536
end
537
endgenerate // index==0
538
generate if (number_of_clk==3 & index==1) begin
539
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
540
end
541
endgenerate // index==1
542
generate if (number_of_clk==3 & index==2) begin
543
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
544
end
545
endgenerate // index==2
546
generate if (number_of_clk==3 & index==3) begin
547
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
548
end
549
endgenerate // index==0
550
 
551
genvar i;
552
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
553 40 unneback
`define MODULE sync_rst
554
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
555
`undef MODULE
556 6 unneback
end
557
endgenerate
558
endmodule
559
`endif
560 32 unneback
///////////////////////////////////////////////////////////////////////////////
561 6 unneback
 
562
`else
563
 
564 32 unneback
///////////////////////////////////////////////////////////////////////////////
565 6 unneback
`ifdef ALTERA
566
 
567 32 unneback
`timescale 1 ps/1 ps
568 40 unneback
`define MODULE pll
569
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
570
`undef MODULE
571 32 unneback
parameter index = 0;
572
parameter number_of_clk = 1;
573
parameter period_time_0 = 20000;
574
parameter period_time_1 = 20000;
575
parameter period_time_2 = 20000;
576
parameter period_time_3 = 20000;
577
parameter period_time_4 = 20000;
578
parameter lock_delay = 2000000;
579
input clk_i, rst_n_i;
580
output lock;
581
output reg [0:number_of_clk-1] clk_o;
582
output [0:number_of_clk-1] rst_o;
583
 
584
`ifdef SIM_PLL
585
 
586
always
587
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
588
 
589
generate if (number_of_clk > 1)
590
always
591
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
592
endgenerate
593
 
594
generate if (number_of_clk > 2)
595
always
596
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
597
endgenerate
598
 
599 33 unneback
generate if (number_of_clk > 3)
600 32 unneback
always
601
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
602
endgenerate
603
 
604 33 unneback
generate if (number_of_clk > 4)
605 32 unneback
always
606
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
607
endgenerate
608
 
609
genvar i;
610
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
611
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
612
end
613
endgenerate
614
 
615 33 unneback
//assign #lock_delay lock = rst_n_i;
616
assign lock = rst_n_i;
617 32 unneback
 
618
endmodule
619 6 unneback
`else
620
 
621 33 unneback
`ifdef VL_PLL0
622
`ifdef VL_PLL0_CLK1
623
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
624
`endif
625
`ifdef VL_PLL0_CLK2
626
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
627
`endif
628
`ifdef VL_PLL0_CLK3
629
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
630
`endif
631
`ifdef VL_PLL0_CLK4
632
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
633
`endif
634
`ifdef VL_PLL0_CLK5
635
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
636
`endif
637
`endif
638 32 unneback
 
639 33 unneback
`ifdef VL_PLL1
640
`ifdef VL_PLL1_CLK1
641
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
642
`endif
643
`ifdef VL_PLL1_CLK2
644
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
645
`endif
646
`ifdef VL_PLL1_CLK3
647
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
648
`endif
649
`ifdef VL_PLL1_CLK4
650
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
651
`endif
652
`ifdef VL_PLL1_CLK5
653
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
654
`endif
655
`endif
656 32 unneback
 
657 33 unneback
`ifdef VL_PLL2
658
`ifdef VL_PLL2_CLK1
659
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
660
`endif
661
`ifdef VL_PLL2_CLK2
662
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
663
`endif
664
`ifdef VL_PLL2_CLK3
665
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
666
`endif
667
`ifdef VL_PLL2_CLK4
668
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
669
`endif
670
`ifdef VL_PLL2_CLK5
671
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
672
`endif
673
`endif
674 32 unneback
 
675 33 unneback
`ifdef VL_PLL3
676
`ifdef VL_PLL3_CLK1
677
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
678
`endif
679
`ifdef VL_PLL3_CLK2
680
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
681
`endif
682
`ifdef VL_PLL3_CLK3
683
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
684
`endif
685
`ifdef VL_PLL3_CLK4
686
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
687
`endif
688
`ifdef VL_PLL3_CLK5
689
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
690
`endif
691
`endif
692 32 unneback
 
693
genvar i;
694
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
695 40 unneback
`define MODULE sync_rst
696
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
697
`undef MODULE
698 32 unneback
end
699
endgenerate
700
endmodule
701
`endif
702
///////////////////////////////////////////////////////////////////////////////
703
 
704
`else
705
 
706 6 unneback
// generic PLL
707 17 unneback
`timescale 1 ps/1 ps
708 40 unneback
`define MODULE pll
709
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
710
`undef MODULE
711 6 unneback
parameter index = 0;
712
parameter number_of_clk = 1;
713 17 unneback
parameter period_time_0 = 20000;
714
parameter period_time_1 = 20000;
715
parameter period_time_2 = 20000;
716 6 unneback
parameter lock_delay = 2000;
717
input clk_i, rst_n_i;
718
output lock;
719
output reg [0:number_of_clk-1] clk_o;
720
output [0:number_of_clk-1] rst_o;
721
 
722
always
723
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
724
 
725
generate if (number_of_clk > 1)
726
always
727
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
728
endgenerate
729
 
730
generate if (number_of_clk > 2)
731
always
732
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
733
endgenerate
734
 
735
genvar i;
736
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
737 40 unneback
`define MODULE sync_rst
738
     `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
739
`undef MODULE
740 6 unneback
end
741
endgenerate
742
 
743
assign #lock_delay lock = rst_n_i;
744
 
745
endmodule
746
 
747
`endif //altera
748 17 unneback
`endif //actel
749 40 unneback
`undef MODULE
750
`endif//////////////////////////////////////////////////////////////////////
751 6 unneback
////                                                              ////
752
////  Versatile library, registers                                ////
753
////                                                              ////
754
////  Description                                                 ////
755
////  Different type of registers                                 ////
756
////                                                              ////
757
////                                                              ////
758
////  To Do:                                                      ////
759
////   - add more different registers                             ////
760
////                                                              ////
761
////  Author(s):                                                  ////
762
////      - Michael Unneback, unneback@opencores.org              ////
763
////        ORSoC AB                                              ////
764
////                                                              ////
765
//////////////////////////////////////////////////////////////////////
766
////                                                              ////
767
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
768
////                                                              ////
769
//// This source file may be used and distributed without         ////
770
//// restriction provided that this copyright statement is not    ////
771
//// removed from the file and that any derivative work contains  ////
772
//// the original copyright notice and the associated disclaimer. ////
773
////                                                              ////
774
//// This source file is free software; you can redistribute it   ////
775
//// and/or modify it under the terms of the GNU Lesser General   ////
776
//// Public License as published by the Free Software Foundation; ////
777
//// either version 2.1 of the License, or (at your option) any   ////
778
//// later version.                                               ////
779
////                                                              ////
780
//// This source is distributed in the hope that it will be       ////
781
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
782
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
783
//// PURPOSE.  See the GNU Lesser General Public License for more ////
784
//// details.                                                     ////
785
////                                                              ////
786
//// You should have received a copy of the GNU Lesser General    ////
787
//// Public License along with this source; if not, download it   ////
788
//// from http://www.opencores.org/lgpl.shtml                     ////
789
////                                                              ////
790
//////////////////////////////////////////////////////////////////////
791
 
792 40 unneback
`ifdef DFF
793
`define MODULE dff
794
module `BASE`MODULE ( d, q, clk, rst);
795
`undef MODULE
796 6 unneback
        parameter width = 1;
797
        parameter reset_value = 0;
798
 
799
        input [width-1:0] d;
800
        input clk, rst;
801
        output reg [width-1:0] q;
802
 
803
        always @ (posedge clk or posedge rst)
804
        if (rst)
805
                q <= reset_value;
806
        else
807
                q <= d;
808
 
809
endmodule
810 40 unneback
`endif
811 6 unneback
 
812 40 unneback
`ifdef DFF_ARRAY
813
`define MODULE dff_array
814
module `BASE`MODULE ( d, q, clk, rst);
815
`undef MODULE
816 6 unneback
 
817
        parameter width = 1;
818
        parameter depth = 2;
819
        parameter reset_value = 1'b0;
820
 
821
        input [width-1:0] d;
822
        input clk, rst;
823
        output [width-1:0] q;
824
        reg  [0:depth-1] q_tmp [width-1:0];
825
        integer i;
826
        always @ (posedge clk or posedge rst)
827
        if (rst) begin
828
            for (i=0;i<depth;i=i+1)
829
                q_tmp[i] <= {width{reset_value}};
830
        end else begin
831
            q_tmp[0] <= d;
832
            for (i=1;i<depth;i=i+1)
833
                q_tmp[i] <= q_tmp[i-1];
834
        end
835
 
836
    assign q = q_tmp[depth-1];
837
 
838
endmodule
839 40 unneback
`endif
840 6 unneback
 
841 40 unneback
`ifdef DFF_CE
842
`define MODULE dff_ce
843
module `BASE`MODULE ( d, ce, q, clk, rst);
844
`undef MODULE
845 6 unneback
 
846
        parameter width = 1;
847
        parameter reset_value = 0;
848
 
849
        input [width-1:0] d;
850
        input ce, clk, rst;
851
        output reg [width-1:0] q;
852
 
853
        always @ (posedge clk or posedge rst)
854
        if (rst)
855
                q <= reset_value;
856
        else
857
                if (ce)
858
                        q <= d;
859
 
860
endmodule
861 40 unneback
`endif
862 6 unneback
 
863 40 unneback
`ifdef DFF_CE_CLEAR
864
`define MODULE dff_ce_clear
865
module `BASE`MODULE ( d, ce, clear, q, clk, rst);
866
`undef MODULE
867 8 unneback
 
868
        parameter width = 1;
869
        parameter reset_value = 0;
870
 
871
        input [width-1:0] d;
872 10 unneback
        input ce, clear, clk, rst;
873 8 unneback
        output reg [width-1:0] q;
874
 
875
        always @ (posedge clk or posedge rst)
876
        if (rst)
877
            q <= reset_value;
878
        else
879
            if (ce)
880
                if (clear)
881
                    q <= {width{1'b0}};
882
                else
883
                    q <= d;
884
 
885
endmodule
886 40 unneback
`endif
887 8 unneback
 
888 40 unneback
`ifdef DF_CE_SET
889
`define MODULE dff_ce_set
890
module `BASE`MODULE ( d, ce, set, q, clk, rst);
891
`undef MODULE
892 24 unneback
 
893
        parameter width = 1;
894
        parameter reset_value = 0;
895
 
896
        input [width-1:0] d;
897
        input ce, set, clk, rst;
898
        output reg [width-1:0] q;
899
 
900
        always @ (posedge clk or posedge rst)
901
        if (rst)
902
            q <= reset_value;
903
        else
904
            if (ce)
905
                if (set)
906
                    q <= {width{1'b1}};
907
                else
908
                    q <= d;
909
 
910
endmodule
911 40 unneback
`endif
912 24 unneback
 
913 40 unneback
`ifdef SPR
914
`define MODULE spr
915
module `BASE`MODULE ( sp, r, q, clk, rst);
916
`undef MODULE
917
 
918 64 unneback
        //parameter width = 1;
919
        parameter reset_value = 1'b0;
920 29 unneback
 
921
        input sp, r;
922
        output reg q;
923
        input clk, rst;
924
 
925
        always @ (posedge clk or posedge rst)
926
        if (rst)
927
            q <= reset_value;
928
        else
929
            if (sp)
930
                q <= 1'b1;
931
            else if (r)
932
                q <= 1'b0;
933
 
934
endmodule
935 40 unneback
`endif
936 29 unneback
 
937 40 unneback
`ifdef SRP
938
`define MODULE srp
939
module `BASE`MODULE ( s, rp, q, clk, rst);
940
`undef MODULE
941
 
942 29 unneback
        parameter width = 1;
943
        parameter reset_value = 0;
944
 
945
        input s, rp;
946
        output reg q;
947
        input clk, rst;
948
 
949
        always @ (posedge clk or posedge rst)
950
        if (rst)
951
            q <= reset_value;
952
        else
953
            if (rp)
954
                q <= 1'b0;
955
            else if (s)
956
                q <= 1'b1;
957
 
958
endmodule
959 40 unneback
`endif
960 29 unneback
 
961 40 unneback
`ifdef ALTERA
962 29 unneback
 
963 40 unneback
`ifdef DFF_SR
964 6 unneback
// megafunction wizard: %LPM_FF%
965
// GENERATION: STANDARD
966
// VERSION: WM1.0
967
// MODULE: lpm_ff 
968
 
969
// ============================================================
970
// File Name: dff_sr.v
971
// Megafunction Name(s):
972
//                      lpm_ff
973
//
974
// Simulation Library Files(s):
975
//                      lpm
976
// ============================================================
977
// ************************************************************
978
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
979
//
980
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
981
// ************************************************************
982
 
983
 
984
//Copyright (C) 1991-2010 Altera Corporation
985
//Your use of Altera Corporation's design tools, logic functions 
986
//and other software and tools, and its AMPP partner logic 
987
//functions, and any output files from any of the foregoing 
988
//(including device programming or simulation files), and any 
989
//associated documentation or information are expressly subject 
990
//to the terms and conditions of the Altera Program License 
991
//Subscription Agreement, Altera MegaCore Function License 
992
//Agreement, or other applicable license agreement, including, 
993
//without limitation, that your use is for the sole purpose of 
994
//programming logic devices manufactured by Altera and sold by 
995
//Altera or its authorized distributors.  Please refer to the 
996
//applicable agreement for further details.
997
 
998
 
999
// synopsys translate_off
1000
`timescale 1 ps / 1 ps
1001
// synopsys translate_on
1002 40 unneback
`define MODULE dff_sr
1003
module `BASE`MODULE (
1004
`undef MODULE
1005
 
1006 6 unneback
        aclr,
1007
        aset,
1008
        clock,
1009
        data,
1010
        q);
1011
 
1012
        input     aclr;
1013
        input     aset;
1014
        input     clock;
1015
        input     data;
1016
        output    q;
1017
 
1018
        wire [0:0] sub_wire0;
1019
        wire [0:0] sub_wire1 = sub_wire0[0:0];
1020
        wire  q = sub_wire1;
1021
        wire  sub_wire2 = data;
1022
        wire  sub_wire3 = sub_wire2;
1023
 
1024
        lpm_ff  lpm_ff_component (
1025
                                .aclr (aclr),
1026
                                .clock (clock),
1027
                                .data (sub_wire3),
1028
                                .aset (aset),
1029
                                .q (sub_wire0)
1030
                                // synopsys translate_off
1031
                                ,
1032
                                .aload (),
1033
                                .enable (),
1034
                                .sclr (),
1035
                                .sload (),
1036
                                .sset ()
1037
                                // synopsys translate_on
1038
                                );
1039
        defparam
1040
                lpm_ff_component.lpm_fftype = "DFF",
1041
                lpm_ff_component.lpm_type = "LPM_FF",
1042
                lpm_ff_component.lpm_width = 1;
1043
 
1044
 
1045
endmodule
1046
 
1047
// ============================================================
1048
// CNX file retrieval info
1049
// ============================================================
1050
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
1051
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
1052
// Retrieval info: PRIVATE: ASET NUMERIC "1"
1053
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
1054
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
1055
// Retrieval info: PRIVATE: DFF NUMERIC "1"
1056
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
1057
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
1058
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
1059
// Retrieval info: PRIVATE: SSET NUMERIC "0"
1060
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
1061
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
1062
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
1063
// Retrieval info: PRIVATE: nBit NUMERIC "1"
1064
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
1065
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
1066
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
1067
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
1068
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
1069
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
1070
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
1071
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
1072
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
1073
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
1074
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
1075
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
1076
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
1077
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
1078
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
1079
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
1080
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
1081
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
1082
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
1083
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
1084
// Retrieval info: LIB_FILE: lpm
1085 40 unneback
`endif
1086 6 unneback
 
1087
`else
1088
 
1089 40 unneback
`ifdef DFF_SR
1090
`define MODULE dff_sr
1091
module `BASE`MODULE ( aclr, aset, clock, data, q);
1092
`undef MODULE
1093 6 unneback
 
1094
    input         aclr;
1095
    input         aset;
1096
    input         clock;
1097
    input         data;
1098
    output reg    q;
1099
 
1100
   always @ (posedge clock or posedge aclr or posedge aset)
1101
     if (aclr)
1102
       q <= 1'b0;
1103
     else if (aset)
1104
       q <= 1'b1;
1105
     else
1106
       q <= data;
1107
 
1108
endmodule
1109 40 unneback
`endif
1110 6 unneback
 
1111
`endif
1112
 
1113
// LATCH
1114
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
1115
`ifdef ALTERA
1116 40 unneback
 
1117
`ifdef LATCH
1118
`define MODULE latch
1119
module `BASE`MODULE ( d, le, q, clk);
1120
`undef MODULE
1121 6 unneback
input d, le;
1122
output q;
1123
input clk;
1124
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
1125
endmodule
1126 40 unneback
`endif
1127
 
1128 6 unneback
`else
1129 40 unneback
 
1130
`ifdef LATCH
1131
`define MODULE latch
1132
module `BASE`MODULE ( d, le, q, clk);
1133
`undef MODULE
1134 6 unneback
input d, le;
1135 48 unneback
input clk;
1136
always @ (le or d)
1137 60 unneback
if (le)
1138 48 unneback
    d <= q;
1139 6 unneback
endmodule
1140 15 unneback
`endif
1141
 
1142 40 unneback
`endif
1143
 
1144
`ifdef SHREG
1145
`define MODULE shreg
1146
module `BASE`MODULE ( d, q, clk, rst);
1147
`undef MODULE
1148
 
1149 17 unneback
parameter depth = 10;
1150
input d;
1151
output q;
1152
input clk, rst;
1153
 
1154
reg [1:depth] dffs;
1155
 
1156
always @ (posedge clk or posedge rst)
1157
if (rst)
1158
    dffs <= {depth{1'b0}};
1159
else
1160
    dffs <= {d,dffs[1:depth-1]};
1161
assign q = dffs[depth];
1162
endmodule
1163 40 unneback
`endif
1164 17 unneback
 
1165 40 unneback
`ifdef SHREG_CE
1166
`define MODULE shreg_ce
1167
module `BASE`MODULE ( d, ce, q, clk, rst);
1168
`undef MODULE
1169 17 unneback
parameter depth = 10;
1170
input d, ce;
1171
output q;
1172
input clk, rst;
1173
 
1174
reg [1:depth] dffs;
1175
 
1176
always @ (posedge clk or posedge rst)
1177
if (rst)
1178
    dffs <= {depth{1'b0}};
1179
else
1180
    if (ce)
1181
        dffs <= {d,dffs[1:depth-1]};
1182
assign q = dffs[depth];
1183
endmodule
1184 40 unneback
`endif
1185 17 unneback
 
1186 40 unneback
`ifdef DELAY
1187
`define MODULE delay
1188
module `BASE`MODULE ( d, q, clk, rst);
1189
`undef MODULE
1190 15 unneback
parameter depth = 10;
1191
input d;
1192
output q;
1193
input clk, rst;
1194
 
1195
reg [1:depth] dffs;
1196
 
1197
always @ (posedge clk or posedge rst)
1198
if (rst)
1199
    dffs <= {depth{1'b0}};
1200
else
1201
    dffs <= {d,dffs[1:depth-1]};
1202
assign q = dffs[depth];
1203 17 unneback
endmodule
1204 40 unneback
`endif
1205 17 unneback
 
1206 40 unneback
`ifdef DELAY_EMPTYFLAG
1207
`define MODULE delay_emptyflag
1208 41 unneback
module `BASE`MODULE ( d, q, emptyflag, clk, rst);
1209 40 unneback
`undef MODULE
1210 17 unneback
parameter depth = 10;
1211
input d;
1212
output q, emptyflag;
1213
input clk, rst;
1214
 
1215
reg [1:depth] dffs;
1216
 
1217
always @ (posedge clk or posedge rst)
1218
if (rst)
1219
    dffs <= {depth{1'b0}};
1220
else
1221
    dffs <= {d,dffs[1:depth-1]};
1222
assign q = dffs[depth];
1223
assign emptyflag = !(|dffs);
1224
endmodule
1225 40 unneback
`endif
1226 75 unneback
 
1227 94 unneback
`ifdef PULSE2TOGGLE
1228 98 unneback
`define MODULE pulse2toggle
1229
module `BASE`MODULE ( pl, q, clk, rst);
1230 75 unneback
`undef MODULE
1231 94 unneback
input pl;
1232 98 unneback
output reg q;
1233 94 unneback
input clk, rst;
1234
always @ (posedge clk or posedge rst)
1235 75 unneback
if (rst)
1236 94 unneback
    q <= 1'b0;
1237 75 unneback
else
1238 94 unneback
    q <= pl ^ q;
1239
endmodule
1240
`endif
1241 75 unneback
 
1242 94 unneback
`ifdef TOGGLE2PULSE
1243 98 unneback
`define MODULE toggle2pulse
1244 94 unneback
module `BASE`MODULE (d, pl, clk, rst);
1245 97 unneback
`undef MODULE
1246 94 unneback
input d;
1247
output pl;
1248
input clk, rst;
1249
reg dff;
1250
always @ (posedge clk or posedge rst)
1251
if (rst)
1252
    dff <= 1'b0;
1253 75 unneback
else
1254 94 unneback
    dff <= d;
1255 98 unneback
assign pl = d ^ dff;
1256 94 unneback
endmodule
1257
`endif
1258 75 unneback
 
1259 94 unneback
`ifdef SYNCHRONIZER
1260
`define MODULE synchronizer
1261
module `BASE`MODULE (d, q, clk, rst);
1262
`undef MODULE
1263
input d;
1264
output reg q;
1265
output clk, rst;
1266
reg dff;
1267
always @ (posedge clk or posedge rst)
1268
if (rst)
1269 100 unneback
    {q,dff} <= 2'b00;
1270 75 unneback
else
1271 100 unneback
    {q,dff} <= {dff,d};
1272 94 unneback
endmodule
1273
`endif
1274 75 unneback
 
1275 94 unneback
`ifdef CDC
1276
`define MODULE cdc
1277 97 unneback
module `BASE`MODULE ( start_pl, take_it_pl, take_it_grant_pl, got_it_pl, clk_src, rst_src, clk_dst, rst_dst);
1278 94 unneback
`undef MODULE
1279
input start_pl;
1280
output take_it_pl;
1281
input take_it_grant_pl; // note: connect to take_it_pl to generate automatic ack
1282
output got_it_pl;
1283
input clk_src, rst_src;
1284
input clk_dst, rst_dst;
1285
wire take_it_tg, take_it_tg_sync;
1286
wire got_it_tg, got_it_tg_sync;
1287
// src -> dst
1288
`define MODULE pulse2toggle
1289
`BASE`MODULE p2t0 (
1290
`undef MODULE
1291
    .pl(start_pl),
1292
    .q(take_it_tg),
1293
    .clk(clk_src),
1294
    .rst(rst_src));
1295 75 unneback
 
1296 94 unneback
`define MODULE synchronizer
1297
`BASE`MODULE sync0 (
1298
`undef MODULE
1299
    .d(take_it_tg),
1300
    .q(take_it_tg_sync),
1301
    .clk(clk_dst),
1302
    .rst(rst_dst));
1303
 
1304
`define MODULE toggle2pulse
1305
`BASE`MODULE t2p0 (
1306
`undef MODULE
1307 100 unneback
    .d(take_it_tg_sync),
1308 94 unneback
    .pl(take_it_pl),
1309
    .clk(clk_dst),
1310
    .rst(rst_dst));
1311
 
1312
// dst -> src
1313
`define MODULE pulse2toggle
1314 98 unneback
`BASE`MODULE p2t1 (
1315 94 unneback
`undef MODULE
1316
    .pl(take_it_grant_pl),
1317
    .q(got_it_tg),
1318
    .clk(clk_dst),
1319
    .rst(rst_dst));
1320
 
1321
`define MODULE synchronizer
1322
`BASE`MODULE sync1 (
1323
`undef MODULE
1324
    .d(got_it_tg),
1325
    .q(got_it_tg_sync),
1326
    .clk(clk_src),
1327
    .rst(rst_src));
1328
 
1329
`define MODULE toggle2pulse
1330
`BASE`MODULE t2p1 (
1331
`undef MODULE
1332 100 unneback
    .d(got_it_tg_sync),
1333 94 unneback
    .pl(got_it_pl),
1334
    .clk(clk_src),
1335
    .rst(rst_src));
1336
 
1337 75 unneback
endmodule
1338
`endif
1339 17 unneback
//////////////////////////////////////////////////////////////////////
1340 6 unneback
////                                                              ////
1341 18 unneback
////  Logic functions                                             ////
1342
////                                                              ////
1343
////  Description                                                 ////
1344
////  Logic functions such as multiplexers                        ////
1345
////                                                              ////
1346
////                                                              ////
1347
////  To Do:                                                      ////
1348
////   -                                                          ////
1349
////                                                              ////
1350
////  Author(s):                                                  ////
1351
////      - Michael Unneback, unneback@opencores.org              ////
1352
////        ORSoC AB                                              ////
1353
////                                                              ////
1354
//////////////////////////////////////////////////////////////////////
1355
////                                                              ////
1356
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1357
////                                                              ////
1358
//// This source file may be used and distributed without         ////
1359
//// restriction provided that this copyright statement is not    ////
1360
//// removed from the file and that any derivative work contains  ////
1361
//// the original copyright notice and the associated disclaimer. ////
1362
////                                                              ////
1363
//// This source file is free software; you can redistribute it   ////
1364
//// and/or modify it under the terms of the GNU Lesser General   ////
1365
//// Public License as published by the Free Software Foundation; ////
1366
//// either version 2.1 of the License, or (at your option) any   ////
1367
//// later version.                                               ////
1368
////                                                              ////
1369
//// This source is distributed in the hope that it will be       ////
1370
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1371
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1372
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1373
//// details.                                                     ////
1374
////                                                              ////
1375
//// You should have received a copy of the GNU Lesser General    ////
1376
//// Public License along with this source; if not, download it   ////
1377
//// from http://www.opencores.org/lgpl.shtml                     ////
1378
////                                                              ////
1379
//////////////////////////////////////////////////////////////////////
1380 40 unneback
`ifdef MUX_ANDOR
1381
`define MODULE mux_andor
1382
module `BASE`MODULE ( a, sel, dout);
1383
`undef MODULE
1384 36 unneback
 
1385
parameter width = 32;
1386
parameter nr_of_ports = 4;
1387
 
1388
input [nr_of_ports*width-1:0] a;
1389
input [nr_of_ports-1:0] sel;
1390
output reg [width-1:0] dout;
1391
 
1392 38 unneback
integer i,j;
1393
 
1394 36 unneback
always @ (a, sel)
1395
begin
1396
    dout = a[width-1:0] & {width{sel[0]}};
1397 42 unneback
    for (i=1;i<nr_of_ports;i=i+1)
1398
        for (j=0;j<width;j=j+1)
1399
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
1400 36 unneback
end
1401
 
1402
endmodule
1403 40 unneback
`endif
1404 36 unneback
 
1405 40 unneback
`ifdef MUX2_ANDOR
1406
`define MODULE mux2_andor
1407
module `BASE`MODULE ( a1, a0, sel, dout);
1408
`undef MODULE
1409 18 unneback
 
1410 34 unneback
parameter width = 32;
1411 35 unneback
localparam nr_of_ports = 2;
1412 34 unneback
input [width-1:0] a1, a0;
1413
input [nr_of_ports-1:0] sel;
1414
output [width-1:0] dout;
1415
 
1416 40 unneback
`define MODULE mux_andor
1417
`BASE`MODULE
1418 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1419 36 unneback
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
1420 40 unneback
`undef MODULE
1421
 
1422 34 unneback
endmodule
1423 40 unneback
`endif
1424 34 unneback
 
1425 40 unneback
`ifdef MUX3_ANDOR
1426
`define MODULE mux3_andor
1427
module `BASE`MODULE ( a2, a1, a0, sel, dout);
1428
`undef MODULE
1429 34 unneback
 
1430
parameter width = 32;
1431 35 unneback
localparam nr_of_ports = 3;
1432 34 unneback
input [width-1:0] a2, a1, a0;
1433
input [nr_of_ports-1:0] sel;
1434
output [width-1:0] dout;
1435
 
1436 40 unneback
`define MODULE mux_andor
1437
`BASE`MODULE
1438 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1439 36 unneback
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
1440 40 unneback
`undef MODULE
1441 34 unneback
endmodule
1442 40 unneback
`endif
1443 34 unneback
 
1444 40 unneback
`ifdef MUX4_ANDOR
1445
`define MODULE mux4_andor
1446
module `BASE`MODULE ( a3, a2, a1, a0, sel, dout);
1447
`undef MODULE
1448 18 unneback
 
1449
parameter width = 32;
1450 35 unneback
localparam nr_of_ports = 4;
1451 18 unneback
input [width-1:0] a3, a2, a1, a0;
1452
input [nr_of_ports-1:0] sel;
1453 22 unneback
output [width-1:0] dout;
1454 18 unneback
 
1455 40 unneback
`define MODULE mux_andor
1456
`BASE`MODULE
1457 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1458 36 unneback
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
1459 40 unneback
`undef MODULE
1460 18 unneback
 
1461
endmodule
1462 40 unneback
`endif
1463 18 unneback
 
1464 40 unneback
`ifdef MUX5_ANDOR
1465
`define MODULE mux5_andor
1466
module `BASE`MODULE ( a4, a3, a2, a1, a0, sel, dout);
1467
`undef MODULE
1468 18 unneback
 
1469
parameter width = 32;
1470 35 unneback
localparam nr_of_ports = 5;
1471 18 unneback
input [width-1:0] a4, a3, a2, a1, a0;
1472
input [nr_of_ports-1:0] sel;
1473 22 unneback
output [width-1:0] dout;
1474 18 unneback
 
1475 40 unneback
`define MODULE mux_andor
1476
`BASE`MODULE
1477 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1478 36 unneback
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1479 40 unneback
`undef MODULE
1480 18 unneback
 
1481
endmodule
1482 40 unneback
`endif
1483 18 unneback
 
1484 40 unneback
`ifdef MUX6_ANDOR
1485
`define MODULE mux6_andor
1486
module `BASE`MODULE ( a5, a4, a3, a2, a1, a0, sel, dout);
1487
`undef MODULE
1488 18 unneback
 
1489
parameter width = 32;
1490 35 unneback
localparam nr_of_ports = 6;
1491 18 unneback
input [width-1:0] a5, a4, a3, a2, a1, a0;
1492
input [nr_of_ports-1:0] sel;
1493 22 unneback
output [width-1:0] dout;
1494 18 unneback
 
1495 40 unneback
`define MODULE mux_andor
1496
`BASE`MODULE
1497 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1498 36 unneback
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1499 40 unneback
`undef MODULE
1500 18 unneback
 
1501
endmodule
1502 40 unneback
`endif
1503 43 unneback
 
1504
`ifdef PARITY
1505
 
1506
`define MODULE parity_generate
1507
module `BASE`MODULE (data, parity);
1508
`undef MODULE
1509
parameter word_size = 32;
1510
parameter chunk_size = 8;
1511
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1512
input [word_size-1:0] data;
1513
output reg [word_size/chunk_size-1:0] parity;
1514
integer i,j;
1515
always @ (data)
1516
for (i=0;i<word_size/chunk_size;i=i+1) begin
1517
    parity[i] = parity_type;
1518
    for (j=0;j<chunk_size;j=j+1) begin
1519 46 unneback
        parity[i] = data[i*chunk_size+j] ^ parity[i];
1520 43 unneback
    end
1521
end
1522
endmodule
1523
 
1524
`define MODULE parity_check
1525
module `BASE`MODULE( data, parity, parity_error);
1526
`undef MODULE
1527
parameter word_size = 32;
1528
parameter chunk_size = 8;
1529
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1530
input [word_size-1:0] data;
1531
input [word_size/chunk_size-1:0] parity;
1532
output parity_error;
1533 44 unneback
reg [word_size/chunk_size-1:0] error_flag;
1534 43 unneback
integer i,j;
1535
always @ (data or parity)
1536
for (i=0;i<word_size/chunk_size;i=i+1) begin
1537
    error_flag[i] = parity[i] ^ parity_type;
1538
    for (j=0;j<chunk_size;j=j+1) begin
1539 46 unneback
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
1540 43 unneback
    end
1541
end
1542
assign parity_error = |error_flag;
1543
endmodule
1544
 
1545 44 unneback
`endif//////////////////////////////////////////////////////////////////////
1546
////                                                              ////
1547
////  IO functions                                                ////
1548
////                                                              ////
1549
////  Description                                                 ////
1550
////  IO functions such as IOB flip-flops                         ////
1551
////                                                              ////
1552
////                                                              ////
1553
////  To Do:                                                      ////
1554
////   -                                                          ////
1555
////                                                              ////
1556
////  Author(s):                                                  ////
1557
////      - Michael Unneback, unneback@opencores.org              ////
1558
////        ORSoC AB                                              ////
1559
////                                                              ////
1560 18 unneback
//////////////////////////////////////////////////////////////////////
1561
////                                                              ////
1562 44 unneback
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1563
////                                                              ////
1564
//// This source file may be used and distributed without         ////
1565
//// restriction provided that this copyright statement is not    ////
1566
//// removed from the file and that any derivative work contains  ////
1567
//// the original copyright notice and the associated disclaimer. ////
1568
////                                                              ////
1569
//// This source file is free software; you can redistribute it   ////
1570
//// and/or modify it under the terms of the GNU Lesser General   ////
1571
//// Public License as published by the Free Software Foundation; ////
1572
//// either version 2.1 of the License, or (at your option) any   ////
1573
//// later version.                                               ////
1574
////                                                              ////
1575
//// This source is distributed in the hope that it will be       ////
1576
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1577
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1578
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1579
//// details.                                                     ////
1580
////                                                              ////
1581
//// You should have received a copy of the GNU Lesser General    ////
1582
//// Public License along with this source; if not, download it   ////
1583
//// from http://www.opencores.org/lgpl.shtml                     ////
1584
////                                                              ////
1585
//////////////////////////////////////////////////////////////////////
1586 45 unneback
`timescale 1ns/1ns
1587 44 unneback
`ifdef O_DFF
1588
`define MODULE o_dff
1589
module `BASE`MODULE (d_i, o_pad, clk, rst);
1590
`undef MODULE
1591
parameter width = 1;
1592 45 unneback
parameter reset_value = {width{1'b0}};
1593
input  [width-1:0]  d_i;
1594 44 unneback
output [width-1:0] o_pad;
1595
input clk, rst;
1596
wire [width-1:0] d_i_int `SYN_KEEP;
1597 45 unneback
reg  [width-1:0] o_pad_int;
1598 44 unneback
assign d_i_int = d_i;
1599
genvar i;
1600 45 unneback
generate
1601 44 unneback
for (i=0;i<width;i=i+1) begin
1602
    always @ (posedge clk or posedge rst)
1603
    if (rst)
1604 45 unneback
        o_pad_int[i] <= reset_value[i];
1605 44 unneback
    else
1606 45 unneback
        o_pad_int[i] <= d_i_int[i];
1607
    assign #1 o_pad[i] = o_pad_int[i];
1608 44 unneback
end
1609
endgenerate
1610
endmodule
1611
`endif
1612
 
1613 45 unneback
`timescale 1ns/1ns
1614 44 unneback
`ifdef IO_DFF_OE
1615
`define MODULE io_dff_oe
1616
module `BASE`MODULE ( d_i, d_o, oe, io_pad, clk, rst);
1617
`undef MODULE
1618
parameter width = 1;
1619
input  [width-1:0] d_o;
1620
output reg [width-1:0] d_i;
1621
input oe;
1622
inout [width-1:0] io_pad;
1623
input clk, rst;
1624
wire [width-1:0] oe_d `SYN_KEEP;
1625
reg [width-1:0] oe_q;
1626
reg [width-1:0] d_o_q;
1627
assign oe_d = {width{oe}};
1628
genvar i;
1629
generate
1630
for (i=0;i<width;i=i+1) begin
1631
    always @ (posedge clk or posedge rst)
1632
    if (rst)
1633
        oe_q[i] <= 1'b0;
1634
    else
1635
        oe_q[i] <= oe_d[i];
1636
    always @ (posedge clk or posedge rst)
1637
    if (rst)
1638
        d_o_q[i] <= 1'b0;
1639
    else
1640
        d_o_q[i] <= d_o[i];
1641
    always @ (posedge clk or posedge rst)
1642
    if (rst)
1643
        d_i[i] <= 1'b0;
1644
    else
1645
        d_i[i] <= io_pad[i];
1646 45 unneback
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
1647 44 unneback
end
1648
endgenerate
1649
endmodule
1650
`endif
1651
`ifdef CNT_BIN
1652
//////////////////////////////////////////////////////////////////////
1653
////                                                              ////
1654 6 unneback
////  Versatile counter                                           ////
1655
////                                                              ////
1656
////  Description                                                 ////
1657
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1658
////  counter                                                     ////
1659
////                                                              ////
1660
////  To Do:                                                      ////
1661
////   - add LFSR with more taps                                  ////
1662
////                                                              ////
1663
////  Author(s):                                                  ////
1664
////      - Michael Unneback, unneback@opencores.org              ////
1665
////        ORSoC AB                                              ////
1666
////                                                              ////
1667
//////////////////////////////////////////////////////////////////////
1668
////                                                              ////
1669
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1670
////                                                              ////
1671
//// This source file may be used and distributed without         ////
1672
//// restriction provided that this copyright statement is not    ////
1673
//// removed from the file and that any derivative work contains  ////
1674
//// the original copyright notice and the associated disclaimer. ////
1675
////                                                              ////
1676
//// This source file is free software; you can redistribute it   ////
1677
//// and/or modify it under the terms of the GNU Lesser General   ////
1678
//// Public License as published by the Free Software Foundation; ////
1679
//// either version 2.1 of the License, or (at your option) any   ////
1680
//// later version.                                               ////
1681
////                                                              ////
1682
//// This source is distributed in the hope that it will be       ////
1683
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1684
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1685
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1686
//// details.                                                     ////
1687
////                                                              ////
1688
//// You should have received a copy of the GNU Lesser General    ////
1689
//// Public License along with this source; if not, download it   ////
1690
//// from http://www.opencores.org/lgpl.shtml                     ////
1691
////                                                              ////
1692
//////////////////////////////////////////////////////////////////////
1693
 
1694
// binary counter
1695 22 unneback
 
1696 40 unneback
`define MODULE cnt_bin
1697
module `BASE`MODULE (
1698
`undef MODULE
1699
 q, rst, clk);
1700
 
1701 22 unneback
   parameter length = 4;
1702
   output [length:1] q;
1703
   input rst;
1704
   input clk;
1705
 
1706
   parameter clear_value = 0;
1707
   parameter set_value = 1;
1708
   parameter wrap_value = 0;
1709
   parameter level1_value = 15;
1710
 
1711
   reg  [length:1] qi;
1712
   wire [length:1] q_next;
1713
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1714
 
1715
   always @ (posedge clk or posedge rst)
1716
     if (rst)
1717
       qi <= {length{1'b0}};
1718
     else
1719
       qi <= q_next;
1720
 
1721
   assign q = qi;
1722
 
1723
endmodule
1724 40 unneback
`endif
1725
`ifdef CNT_BIN_CLEAR
1726 22 unneback
//////////////////////////////////////////////////////////////////////
1727
////                                                              ////
1728
////  Versatile counter                                           ////
1729
////                                                              ////
1730
////  Description                                                 ////
1731
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1732
////  counter                                                     ////
1733
////                                                              ////
1734
////  To Do:                                                      ////
1735
////   - add LFSR with more taps                                  ////
1736
////                                                              ////
1737
////  Author(s):                                                  ////
1738
////      - Michael Unneback, unneback@opencores.org              ////
1739
////        ORSoC AB                                              ////
1740
////                                                              ////
1741
//////////////////////////////////////////////////////////////////////
1742
////                                                              ////
1743
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1744
////                                                              ////
1745
//// This source file may be used and distributed without         ////
1746
//// restriction provided that this copyright statement is not    ////
1747
//// removed from the file and that any derivative work contains  ////
1748
//// the original copyright notice and the associated disclaimer. ////
1749
////                                                              ////
1750
//// This source file is free software; you can redistribute it   ////
1751
//// and/or modify it under the terms of the GNU Lesser General   ////
1752
//// Public License as published by the Free Software Foundation; ////
1753
//// either version 2.1 of the License, or (at your option) any   ////
1754
//// later version.                                               ////
1755
////                                                              ////
1756
//// This source is distributed in the hope that it will be       ////
1757
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1758
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1759
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1760
//// details.                                                     ////
1761
////                                                              ////
1762
//// You should have received a copy of the GNU Lesser General    ////
1763
//// Public License along with this source; if not, download it   ////
1764
//// from http://www.opencores.org/lgpl.shtml                     ////
1765
////                                                              ////
1766
//////////////////////////////////////////////////////////////////////
1767
 
1768
// binary counter
1769
 
1770 40 unneback
`define MODULE cnt_bin_clear
1771
module `BASE`MODULE (
1772
`undef MODULE
1773
 clear, q, rst, clk);
1774
 
1775 22 unneback
   parameter length = 4;
1776
   input clear;
1777
   output [length:1] q;
1778
   input rst;
1779
   input clk;
1780
 
1781
   parameter clear_value = 0;
1782
   parameter set_value = 1;
1783
   parameter wrap_value = 0;
1784
   parameter level1_value = 15;
1785
 
1786
   reg  [length:1] qi;
1787
   wire [length:1] q_next;
1788
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1789
 
1790
   always @ (posedge clk or posedge rst)
1791
     if (rst)
1792
       qi <= {length{1'b0}};
1793
     else
1794
       qi <= q_next;
1795
 
1796
   assign q = qi;
1797
 
1798
endmodule
1799 40 unneback
`endif
1800
`ifdef CNT_BIN_CE
1801 22 unneback
//////////////////////////////////////////////////////////////////////
1802
////                                                              ////
1803
////  Versatile counter                                           ////
1804
////                                                              ////
1805
////  Description                                                 ////
1806
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1807
////  counter                                                     ////
1808
////                                                              ////
1809
////  To Do:                                                      ////
1810
////   - add LFSR with more taps                                  ////
1811
////                                                              ////
1812
////  Author(s):                                                  ////
1813
////      - Michael Unneback, unneback@opencores.org              ////
1814
////        ORSoC AB                                              ////
1815
////                                                              ////
1816
//////////////////////////////////////////////////////////////////////
1817
////                                                              ////
1818
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1819
////                                                              ////
1820
//// This source file may be used and distributed without         ////
1821
//// restriction provided that this copyright statement is not    ////
1822
//// removed from the file and that any derivative work contains  ////
1823
//// the original copyright notice and the associated disclaimer. ////
1824
////                                                              ////
1825
//// This source file is free software; you can redistribute it   ////
1826
//// and/or modify it under the terms of the GNU Lesser General   ////
1827
//// Public License as published by the Free Software Foundation; ////
1828
//// either version 2.1 of the License, or (at your option) any   ////
1829
//// later version.                                               ////
1830
////                                                              ////
1831
//// This source is distributed in the hope that it will be       ////
1832
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1833
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1834
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1835
//// details.                                                     ////
1836
////                                                              ////
1837
//// You should have received a copy of the GNU Lesser General    ////
1838
//// Public License along with this source; if not, download it   ////
1839
//// from http://www.opencores.org/lgpl.shtml                     ////
1840
////                                                              ////
1841
//////////////////////////////////////////////////////////////////////
1842
 
1843
// binary counter
1844 6 unneback
 
1845 40 unneback
`define MODULE cnt_bin_ce
1846
module `BASE`MODULE (
1847
`undef MODULE
1848
 cke, q, rst, clk);
1849
 
1850 6 unneback
   parameter length = 4;
1851
   input cke;
1852
   output [length:1] q;
1853
   input rst;
1854
   input clk;
1855
 
1856
   parameter clear_value = 0;
1857
   parameter set_value = 1;
1858
   parameter wrap_value = 0;
1859
   parameter level1_value = 15;
1860
 
1861
   reg  [length:1] qi;
1862
   wire [length:1] q_next;
1863
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1864
 
1865
   always @ (posedge clk or posedge rst)
1866
     if (rst)
1867
       qi <= {length{1'b0}};
1868
     else
1869
     if (cke)
1870
       qi <= q_next;
1871
 
1872
   assign q = qi;
1873
 
1874
endmodule
1875 40 unneback
`endif
1876
`ifdef CNT_BIN_CE_CLEAR
1877 6 unneback
//////////////////////////////////////////////////////////////////////
1878
////                                                              ////
1879
////  Versatile counter                                           ////
1880
////                                                              ////
1881
////  Description                                                 ////
1882
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1883
////  counter                                                     ////
1884
////                                                              ////
1885
////  To Do:                                                      ////
1886
////   - add LFSR with more taps                                  ////
1887
////                                                              ////
1888
////  Author(s):                                                  ////
1889
////      - Michael Unneback, unneback@opencores.org              ////
1890
////        ORSoC AB                                              ////
1891
////                                                              ////
1892
//////////////////////////////////////////////////////////////////////
1893
////                                                              ////
1894
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1895
////                                                              ////
1896
//// This source file may be used and distributed without         ////
1897
//// restriction provided that this copyright statement is not    ////
1898
//// removed from the file and that any derivative work contains  ////
1899
//// the original copyright notice and the associated disclaimer. ////
1900
////                                                              ////
1901
//// This source file is free software; you can redistribute it   ////
1902
//// and/or modify it under the terms of the GNU Lesser General   ////
1903
//// Public License as published by the Free Software Foundation; ////
1904
//// either version 2.1 of the License, or (at your option) any   ////
1905
//// later version.                                               ////
1906
////                                                              ////
1907
//// This source is distributed in the hope that it will be       ////
1908
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1909
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1910
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1911
//// details.                                                     ////
1912
////                                                              ////
1913
//// You should have received a copy of the GNU Lesser General    ////
1914
//// Public License along with this source; if not, download it   ////
1915
//// from http://www.opencores.org/lgpl.shtml                     ////
1916
////                                                              ////
1917
//////////////////////////////////////////////////////////////////////
1918
 
1919
// binary counter
1920
 
1921 40 unneback
`define MODULE cnt_bin_ce_clear
1922
module `BASE`MODULE (
1923
`undef MODULE
1924
 clear, cke, q, rst, clk);
1925
 
1926 6 unneback
   parameter length = 4;
1927
   input clear;
1928
   input cke;
1929
   output [length:1] q;
1930
   input rst;
1931
   input clk;
1932
 
1933
   parameter clear_value = 0;
1934
   parameter set_value = 1;
1935
   parameter wrap_value = 0;
1936
   parameter level1_value = 15;
1937
 
1938
   reg  [length:1] qi;
1939
   wire [length:1] q_next;
1940
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1941
 
1942
   always @ (posedge clk or posedge rst)
1943
     if (rst)
1944
       qi <= {length{1'b0}};
1945
     else
1946
     if (cke)
1947
       qi <= q_next;
1948
 
1949
   assign q = qi;
1950
 
1951
endmodule
1952 40 unneback
`endif
1953
`ifdef CNT_BIN_CE_CLEAR_L1_L2
1954 6 unneback
//////////////////////////////////////////////////////////////////////
1955
////                                                              ////
1956
////  Versatile counter                                           ////
1957
////                                                              ////
1958
////  Description                                                 ////
1959
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1960
////  counter                                                     ////
1961
////                                                              ////
1962
////  To Do:                                                      ////
1963
////   - add LFSR with more taps                                  ////
1964
////                                                              ////
1965
////  Author(s):                                                  ////
1966
////      - Michael Unneback, unneback@opencores.org              ////
1967
////        ORSoC AB                                              ////
1968
////                                                              ////
1969
//////////////////////////////////////////////////////////////////////
1970
////                                                              ////
1971
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1972
////                                                              ////
1973
//// This source file may be used and distributed without         ////
1974
//// restriction provided that this copyright statement is not    ////
1975
//// removed from the file and that any derivative work contains  ////
1976
//// the original copyright notice and the associated disclaimer. ////
1977
////                                                              ////
1978
//// This source file is free software; you can redistribute it   ////
1979
//// and/or modify it under the terms of the GNU Lesser General   ////
1980
//// Public License as published by the Free Software Foundation; ////
1981
//// either version 2.1 of the License, or (at your option) any   ////
1982
//// later version.                                               ////
1983
////                                                              ////
1984
//// This source is distributed in the hope that it will be       ////
1985
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1986
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1987
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1988
//// details.                                                     ////
1989
////                                                              ////
1990
//// You should have received a copy of the GNU Lesser General    ////
1991
//// Public License along with this source; if not, download it   ////
1992
//// from http://www.opencores.org/lgpl.shtml                     ////
1993
////                                                              ////
1994
//////////////////////////////////////////////////////////////////////
1995
 
1996
// binary counter
1997 29 unneback
 
1998 40 unneback
`define MODULE cnt_bin_ce_clear_l1_l2
1999
module `BASE`MODULE (
2000
`undef MODULE
2001
 clear, cke, q, level1, level2, rst, clk);
2002
 
2003 29 unneback
   parameter length = 4;
2004
   input clear;
2005
   input cke;
2006
   output [length:1] q;
2007
   output reg level1;
2008
   output reg level2;
2009
   input rst;
2010
   input clk;
2011
 
2012
   parameter clear_value = 0;
2013
   parameter set_value = 1;
2014 30 unneback
   parameter wrap_value = 15;
2015
   parameter level1_value = 8;
2016
   parameter level2_value = 15;
2017 29 unneback
 
2018
   wire rew;
2019 30 unneback
   assign rew = 1'b0;
2020 29 unneback
   reg  [length:1] qi;
2021
   wire [length:1] q_next;
2022
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
2023
 
2024
   always @ (posedge clk or posedge rst)
2025
     if (rst)
2026
       qi <= {length{1'b0}};
2027
     else
2028
     if (cke)
2029
       qi <= q_next;
2030
 
2031
   assign q = qi;
2032
 
2033
 
2034
    always @ (posedge clk or posedge rst)
2035
    if (rst)
2036
        level1 <= 1'b0;
2037
    else
2038
    if (cke)
2039
    if (clear)
2040
        level1 <= 1'b0;
2041
    else if (q_next == level1_value)
2042
        level1 <= 1'b1;
2043
    else if (qi == level1_value & rew)
2044
        level1 <= 1'b0;
2045
 
2046
    always @ (posedge clk or posedge rst)
2047
    if (rst)
2048
        level2 <= 1'b0;
2049
    else
2050
    if (cke)
2051
    if (clear)
2052
        level2 <= 1'b0;
2053
    else if (q_next == level2_value)
2054
        level2 <= 1'b1;
2055
    else if (qi == level2_value & rew)
2056
        level2 <= 1'b0;
2057
endmodule
2058 40 unneback
`endif
2059
`ifdef CNT_BIN_CE_CLEAR_SET_REW
2060 29 unneback
//////////////////////////////////////////////////////////////////////
2061
////                                                              ////
2062
////  Versatile counter                                           ////
2063
////                                                              ////
2064
////  Description                                                 ////
2065
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2066
////  counter                                                     ////
2067
////                                                              ////
2068
////  To Do:                                                      ////
2069
////   - add LFSR with more taps                                  ////
2070
////                                                              ////
2071
////  Author(s):                                                  ////
2072
////      - Michael Unneback, unneback@opencores.org              ////
2073
////        ORSoC AB                                              ////
2074
////                                                              ////
2075
//////////////////////////////////////////////////////////////////////
2076
////                                                              ////
2077
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2078
////                                                              ////
2079
//// This source file may be used and distributed without         ////
2080
//// restriction provided that this copyright statement is not    ////
2081
//// removed from the file and that any derivative work contains  ////
2082
//// the original copyright notice and the associated disclaimer. ////
2083
////                                                              ////
2084
//// This source file is free software; you can redistribute it   ////
2085
//// and/or modify it under the terms of the GNU Lesser General   ////
2086
//// Public License as published by the Free Software Foundation; ////
2087
//// either version 2.1 of the License, or (at your option) any   ////
2088
//// later version.                                               ////
2089
////                                                              ////
2090
//// This source is distributed in the hope that it will be       ////
2091
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2092
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2093
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2094
//// details.                                                     ////
2095
////                                                              ////
2096
//// You should have received a copy of the GNU Lesser General    ////
2097
//// Public License along with this source; if not, download it   ////
2098
//// from http://www.opencores.org/lgpl.shtml                     ////
2099
////                                                              ////
2100
//////////////////////////////////////////////////////////////////////
2101
 
2102
// binary counter
2103 6 unneback
 
2104 40 unneback
`define MODULE cnt_bin_ce_clear_set_rew
2105
module `BASE`MODULE (
2106
`undef MODULE
2107
 clear, set, cke, rew, q, rst, clk);
2108
 
2109 6 unneback
   parameter length = 4;
2110
   input clear;
2111
   input set;
2112
   input cke;
2113
   input rew;
2114
   output [length:1] q;
2115
   input rst;
2116
   input clk;
2117
 
2118
   parameter clear_value = 0;
2119
   parameter set_value = 1;
2120
   parameter wrap_value = 0;
2121
   parameter level1_value = 15;
2122
 
2123
   reg  [length:1] qi;
2124
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2125
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
2126
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
2127
   assign q_next = rew ? q_next_rew : q_next_fw;
2128
 
2129
   always @ (posedge clk or posedge rst)
2130
     if (rst)
2131
       qi <= {length{1'b0}};
2132
     else
2133
     if (cke)
2134
       qi <= q_next;
2135
 
2136
   assign q = qi;
2137
 
2138
endmodule
2139 40 unneback
`endif
2140
`ifdef CNT_BIN_CE_REW_L1
2141 6 unneback
//////////////////////////////////////////////////////////////////////
2142
////                                                              ////
2143
////  Versatile counter                                           ////
2144
////                                                              ////
2145
////  Description                                                 ////
2146
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2147
////  counter                                                     ////
2148
////                                                              ////
2149
////  To Do:                                                      ////
2150
////   - add LFSR with more taps                                  ////
2151
////                                                              ////
2152
////  Author(s):                                                  ////
2153
////      - Michael Unneback, unneback@opencores.org              ////
2154
////        ORSoC AB                                              ////
2155
////                                                              ////
2156
//////////////////////////////////////////////////////////////////////
2157
////                                                              ////
2158
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2159
////                                                              ////
2160
//// This source file may be used and distributed without         ////
2161
//// restriction provided that this copyright statement is not    ////
2162
//// removed from the file and that any derivative work contains  ////
2163
//// the original copyright notice and the associated disclaimer. ////
2164
////                                                              ////
2165
//// This source file is free software; you can redistribute it   ////
2166
//// and/or modify it under the terms of the GNU Lesser General   ////
2167
//// Public License as published by the Free Software Foundation; ////
2168
//// either version 2.1 of the License, or (at your option) any   ////
2169
//// later version.                                               ////
2170
////                                                              ////
2171
//// This source is distributed in the hope that it will be       ////
2172
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2173
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2174
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2175
//// details.                                                     ////
2176
////                                                              ////
2177
//// You should have received a copy of the GNU Lesser General    ////
2178
//// Public License along with this source; if not, download it   ////
2179
//// from http://www.opencores.org/lgpl.shtml                     ////
2180
////                                                              ////
2181
//////////////////////////////////////////////////////////////////////
2182
 
2183
// binary counter
2184
 
2185 40 unneback
`define MODULE cnt_bin_ce_rew_l1
2186
module `BASE`MODULE (
2187
`undef MODULE
2188
 cke, rew, level1, rst, clk);
2189
 
2190 6 unneback
   parameter length = 4;
2191
   input cke;
2192
   input rew;
2193
   output reg level1;
2194
   input rst;
2195
   input clk;
2196
 
2197
   parameter clear_value = 0;
2198
   parameter set_value = 1;
2199
   parameter wrap_value = 1;
2200
   parameter level1_value = 15;
2201
 
2202 29 unneback
   wire clear;
2203 30 unneback
   assign clear = 1'b0;
2204 6 unneback
   reg  [length:1] qi;
2205
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2206
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2207
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2208
   assign q_next = rew ? q_next_rew : q_next_fw;
2209
 
2210
   always @ (posedge clk or posedge rst)
2211
     if (rst)
2212
       qi <= {length{1'b0}};
2213
     else
2214
     if (cke)
2215
       qi <= q_next;
2216
 
2217
 
2218
 
2219
    always @ (posedge clk or posedge rst)
2220
    if (rst)
2221
        level1 <= 1'b0;
2222
    else
2223
    if (cke)
2224 29 unneback
    if (clear)
2225
        level1 <= 1'b0;
2226
    else if (q_next == level1_value)
2227 6 unneback
        level1 <= 1'b1;
2228
    else if (qi == level1_value & rew)
2229
        level1 <= 1'b0;
2230
endmodule
2231 40 unneback
`endif
2232
`ifdef CNT_BIN_CE_REW_ZQ_L1
2233 6 unneback
//////////////////////////////////////////////////////////////////////
2234
////                                                              ////
2235
////  Versatile counter                                           ////
2236
////                                                              ////
2237
////  Description                                                 ////
2238
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2239
////  counter                                                     ////
2240
////                                                              ////
2241
////  To Do:                                                      ////
2242
////   - add LFSR with more taps                                  ////
2243
////                                                              ////
2244
////  Author(s):                                                  ////
2245
////      - Michael Unneback, unneback@opencores.org              ////
2246
////        ORSoC AB                                              ////
2247
////                                                              ////
2248
//////////////////////////////////////////////////////////////////////
2249
////                                                              ////
2250
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2251
////                                                              ////
2252
//// This source file may be used and distributed without         ////
2253
//// restriction provided that this copyright statement is not    ////
2254
//// removed from the file and that any derivative work contains  ////
2255
//// the original copyright notice and the associated disclaimer. ////
2256
////                                                              ////
2257
//// This source file is free software; you can redistribute it   ////
2258
//// and/or modify it under the terms of the GNU Lesser General   ////
2259
//// Public License as published by the Free Software Foundation; ////
2260
//// either version 2.1 of the License, or (at your option) any   ////
2261
//// later version.                                               ////
2262
////                                                              ////
2263
//// This source is distributed in the hope that it will be       ////
2264
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2265
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2266
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2267
//// details.                                                     ////
2268
////                                                              ////
2269
//// You should have received a copy of the GNU Lesser General    ////
2270
//// Public License along with this source; if not, download it   ////
2271
//// from http://www.opencores.org/lgpl.shtml                     ////
2272
////                                                              ////
2273
//////////////////////////////////////////////////////////////////////
2274
 
2275 25 unneback
// binary counter
2276
 
2277 40 unneback
`define MODULE cnt_bin_ce_rew_zq_l1
2278
module `BASE`MODULE (
2279
`undef MODULE
2280
 cke, rew, zq, level1, rst, clk);
2281
 
2282 25 unneback
   parameter length = 4;
2283
   input cke;
2284
   input rew;
2285
   output reg zq;
2286
   output reg level1;
2287
   input rst;
2288
   input clk;
2289
 
2290
   parameter clear_value = 0;
2291
   parameter set_value = 1;
2292
   parameter wrap_value = 1;
2293
   parameter level1_value = 15;
2294
 
2295 29 unneback
   wire clear;
2296 30 unneback
   assign clear = 1'b0;
2297 25 unneback
   reg  [length:1] qi;
2298
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2299
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2300
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2301
   assign q_next = rew ? q_next_rew : q_next_fw;
2302
 
2303
   always @ (posedge clk or posedge rst)
2304
     if (rst)
2305
       qi <= {length{1'b0}};
2306
     else
2307
     if (cke)
2308
       qi <= q_next;
2309
 
2310
 
2311
 
2312
   always @ (posedge clk or posedge rst)
2313
     if (rst)
2314
       zq <= 1'b1;
2315
     else
2316
     if (cke)
2317
       zq <= q_next == {length{1'b0}};
2318
 
2319
    always @ (posedge clk or posedge rst)
2320
    if (rst)
2321
        level1 <= 1'b0;
2322
    else
2323
    if (cke)
2324 29 unneback
    if (clear)
2325
        level1 <= 1'b0;
2326
    else if (q_next == level1_value)
2327 25 unneback
        level1 <= 1'b1;
2328
    else if (qi == level1_value & rew)
2329
        level1 <= 1'b0;
2330
endmodule
2331 40 unneback
`endif
2332
`ifdef CNT_BIN_CE_REW_Q_ZQ_L1
2333 25 unneback
//////////////////////////////////////////////////////////////////////
2334
////                                                              ////
2335
////  Versatile counter                                           ////
2336
////                                                              ////
2337
////  Description                                                 ////
2338
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2339
////  counter                                                     ////
2340
////                                                              ////
2341
////  To Do:                                                      ////
2342
////   - add LFSR with more taps                                  ////
2343
////                                                              ////
2344
////  Author(s):                                                  ////
2345
////      - Michael Unneback, unneback@opencores.org              ////
2346
////        ORSoC AB                                              ////
2347
////                                                              ////
2348
//////////////////////////////////////////////////////////////////////
2349
////                                                              ////
2350
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2351
////                                                              ////
2352
//// This source file may be used and distributed without         ////
2353
//// restriction provided that this copyright statement is not    ////
2354
//// removed from the file and that any derivative work contains  ////
2355
//// the original copyright notice and the associated disclaimer. ////
2356
////                                                              ////
2357
//// This source file is free software; you can redistribute it   ////
2358
//// and/or modify it under the terms of the GNU Lesser General   ////
2359
//// Public License as published by the Free Software Foundation; ////
2360
//// either version 2.1 of the License, or (at your option) any   ////
2361
//// later version.                                               ////
2362
////                                                              ////
2363
//// This source is distributed in the hope that it will be       ////
2364
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2365
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2366
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2367
//// details.                                                     ////
2368
////                                                              ////
2369
//// You should have received a copy of the GNU Lesser General    ////
2370
//// Public License along with this source; if not, download it   ////
2371
//// from http://www.opencores.org/lgpl.shtml                     ////
2372
////                                                              ////
2373
//////////////////////////////////////////////////////////////////////
2374
 
2375
// binary counter
2376
 
2377 40 unneback
`define MODULE cnt_bin_ce_rew_q_zq_l1
2378
module `BASE`MODULE (
2379
`undef MODULE
2380
 cke, rew, q, zq, level1, rst, clk);
2381
 
2382 25 unneback
   parameter length = 4;
2383
   input cke;
2384
   input rew;
2385
   output [length:1] q;
2386
   output reg zq;
2387
   output reg level1;
2388
   input rst;
2389
   input clk;
2390
 
2391
   parameter clear_value = 0;
2392
   parameter set_value = 1;
2393
   parameter wrap_value = 1;
2394
   parameter level1_value = 15;
2395
 
2396 29 unneback
   wire clear;
2397 30 unneback
   assign clear = 1'b0;
2398 25 unneback
   reg  [length:1] qi;
2399
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2400
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2401
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2402
   assign q_next = rew ? q_next_rew : q_next_fw;
2403
 
2404
   always @ (posedge clk or posedge rst)
2405
     if (rst)
2406
       qi <= {length{1'b0}};
2407
     else
2408
     if (cke)
2409
       qi <= q_next;
2410
 
2411
   assign q = qi;
2412
 
2413
 
2414
   always @ (posedge clk or posedge rst)
2415
     if (rst)
2416
       zq <= 1'b1;
2417
     else
2418
     if (cke)
2419
       zq <= q_next == {length{1'b0}};
2420
 
2421
    always @ (posedge clk or posedge rst)
2422
    if (rst)
2423
        level1 <= 1'b0;
2424
    else
2425
    if (cke)
2426 29 unneback
    if (clear)
2427
        level1 <= 1'b0;
2428
    else if (q_next == level1_value)
2429 25 unneback
        level1 <= 1'b1;
2430
    else if (qi == level1_value & rew)
2431
        level1 <= 1'b0;
2432
endmodule
2433 40 unneback
`endif
2434
`ifdef CNT_LFSR_ZQ
2435 25 unneback
//////////////////////////////////////////////////////////////////////
2436
////                                                              ////
2437
////  Versatile counter                                           ////
2438
////                                                              ////
2439
////  Description                                                 ////
2440
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2441
////  counter                                                     ////
2442
////                                                              ////
2443
////  To Do:                                                      ////
2444
////   - add LFSR with more taps                                  ////
2445
////                                                              ////
2446
////  Author(s):                                                  ////
2447
////      - Michael Unneback, unneback@opencores.org              ////
2448
////        ORSoC AB                                              ////
2449
////                                                              ////
2450
//////////////////////////////////////////////////////////////////////
2451
////                                                              ////
2452
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2453
////                                                              ////
2454
//// This source file may be used and distributed without         ////
2455
//// restriction provided that this copyright statement is not    ////
2456
//// removed from the file and that any derivative work contains  ////
2457
//// the original copyright notice and the associated disclaimer. ////
2458
////                                                              ////
2459
//// This source file is free software; you can redistribute it   ////
2460
//// and/or modify it under the terms of the GNU Lesser General   ////
2461
//// Public License as published by the Free Software Foundation; ////
2462
//// either version 2.1 of the License, or (at your option) any   ////
2463
//// later version.                                               ////
2464
////                                                              ////
2465
//// This source is distributed in the hope that it will be       ////
2466
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2467
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2468
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2469
//// details.                                                     ////
2470
////                                                              ////
2471
//// You should have received a copy of the GNU Lesser General    ////
2472
//// Public License along with this source; if not, download it   ////
2473
//// from http://www.opencores.org/lgpl.shtml                     ////
2474
////                                                              ////
2475
//////////////////////////////////////////////////////////////////////
2476
 
2477 6 unneback
// LFSR counter
2478
 
2479 40 unneback
`define MODULE cnt_lfsr_zq
2480
module `BASE`MODULE (
2481
`undef MODULE
2482
 zq, rst, clk);
2483
 
2484 6 unneback
   parameter length = 4;
2485
   output reg zq;
2486
   input rst;
2487
   input clk;
2488
 
2489
   parameter clear_value = 0;
2490
   parameter set_value = 1;
2491
   parameter wrap_value = 8;
2492
   parameter level1_value = 15;
2493
 
2494
   reg  [length:1] qi;
2495
   reg lfsr_fb;
2496
   wire [length:1] q_next;
2497
   reg [32:1] polynom;
2498
   integer i;
2499
 
2500
   always @ (qi)
2501
   begin
2502
        case (length)
2503
         2: polynom = 32'b11;                               // 0x3
2504
         3: polynom = 32'b110;                              // 0x6
2505
         4: polynom = 32'b1100;                             // 0xC
2506
         5: polynom = 32'b10100;                            // 0x14
2507
         6: polynom = 32'b110000;                           // 0x30
2508
         7: polynom = 32'b1100000;                          // 0x60
2509
         8: polynom = 32'b10111000;                         // 0xb8
2510
         9: polynom = 32'b100010000;                        // 0x110
2511
        10: polynom = 32'b1001000000;                       // 0x240
2512
        11: polynom = 32'b10100000000;                      // 0x500
2513
        12: polynom = 32'b100000101001;                     // 0x829
2514
        13: polynom = 32'b1000000001100;                    // 0x100C
2515
        14: polynom = 32'b10000000010101;                   // 0x2015
2516
        15: polynom = 32'b110000000000000;                  // 0x6000
2517
        16: polynom = 32'b1101000000001000;                 // 0xD008
2518
        17: polynom = 32'b10010000000000000;                // 0x12000
2519
        18: polynom = 32'b100000010000000000;               // 0x20400
2520
        19: polynom = 32'b1000000000000100011;              // 0x40023
2521 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2522 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2523
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2524
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2525
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2526
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2527
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2528
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2529
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2530
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2531
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2532
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2533
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2534
        default: polynom = 32'b0;
2535
        endcase
2536
        lfsr_fb = qi[length];
2537
        for (i=length-1; i>=1; i=i-1) begin
2538
            if (polynom[i])
2539
                lfsr_fb = lfsr_fb  ~^ qi[i];
2540
        end
2541
    end
2542
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2543
 
2544
   always @ (posedge clk or posedge rst)
2545
     if (rst)
2546
       qi <= {length{1'b0}};
2547
     else
2548
       qi <= q_next;
2549
 
2550
 
2551
 
2552
   always @ (posedge clk or posedge rst)
2553
     if (rst)
2554
       zq <= 1'b1;
2555
     else
2556
       zq <= q_next == {length{1'b0}};
2557
endmodule
2558 40 unneback
`endif
2559 75 unneback
`ifdef CNT_LFSR_CE
2560
//////////////////////////////////////////////////////////////////////
2561
////                                                              ////
2562
////  Versatile counter                                           ////
2563
////                                                              ////
2564
////  Description                                                 ////
2565
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2566
////  counter                                                     ////
2567
////                                                              ////
2568
////  To Do:                                                      ////
2569
////   - add LFSR with more taps                                  ////
2570
////                                                              ////
2571
////  Author(s):                                                  ////
2572
////      - Michael Unneback, unneback@opencores.org              ////
2573
////        ORSoC AB                                              ////
2574
////                                                              ////
2575
//////////////////////////////////////////////////////////////////////
2576
////                                                              ////
2577
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2578
////                                                              ////
2579
//// This source file may be used and distributed without         ////
2580
//// restriction provided that this copyright statement is not    ////
2581
//// removed from the file and that any derivative work contains  ////
2582
//// the original copyright notice and the associated disclaimer. ////
2583
////                                                              ////
2584
//// This source file is free software; you can redistribute it   ////
2585
//// and/or modify it under the terms of the GNU Lesser General   ////
2586
//// Public License as published by the Free Software Foundation; ////
2587
//// either version 2.1 of the License, or (at your option) any   ////
2588
//// later version.                                               ////
2589
////                                                              ////
2590
//// This source is distributed in the hope that it will be       ////
2591
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2592
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2593
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2594
//// details.                                                     ////
2595
////                                                              ////
2596
//// You should have received a copy of the GNU Lesser General    ////
2597
//// Public License along with this source; if not, download it   ////
2598
//// from http://www.opencores.org/lgpl.shtml                     ////
2599
////                                                              ////
2600
//////////////////////////////////////////////////////////////////////
2601
 
2602
// LFSR counter
2603
 
2604
`define MODULE cnt_lfsr_ce
2605
module `BASE`MODULE (
2606
`undef MODULE
2607
 cke, zq, rst, clk);
2608
 
2609
   parameter length = 4;
2610
   input cke;
2611
   output reg zq;
2612
   input rst;
2613
   input clk;
2614
 
2615
   parameter clear_value = 0;
2616
   parameter set_value = 1;
2617
   parameter wrap_value = 0;
2618
   parameter level1_value = 15;
2619
 
2620
   reg  [length:1] qi;
2621
   reg lfsr_fb;
2622
   wire [length:1] q_next;
2623
   reg [32:1] polynom;
2624
   integer i;
2625
 
2626
   always @ (qi)
2627
   begin
2628
        case (length)
2629
         2: polynom = 32'b11;                               // 0x3
2630
         3: polynom = 32'b110;                              // 0x6
2631
         4: polynom = 32'b1100;                             // 0xC
2632
         5: polynom = 32'b10100;                            // 0x14
2633
         6: polynom = 32'b110000;                           // 0x30
2634
         7: polynom = 32'b1100000;                          // 0x60
2635
         8: polynom = 32'b10111000;                         // 0xb8
2636
         9: polynom = 32'b100010000;                        // 0x110
2637
        10: polynom = 32'b1001000000;                       // 0x240
2638
        11: polynom = 32'b10100000000;                      // 0x500
2639
        12: polynom = 32'b100000101001;                     // 0x829
2640
        13: polynom = 32'b1000000001100;                    // 0x100C
2641
        14: polynom = 32'b10000000010101;                   // 0x2015
2642
        15: polynom = 32'b110000000000000;                  // 0x6000
2643
        16: polynom = 32'b1101000000001000;                 // 0xD008
2644
        17: polynom = 32'b10010000000000000;                // 0x12000
2645
        18: polynom = 32'b100000010000000000;               // 0x20400
2646
        19: polynom = 32'b1000000000000100011;              // 0x40023
2647
        20: polynom = 32'b10010000000000000000;             // 0x90000
2648
        21: polynom = 32'b101000000000000000000;            // 0x140000
2649
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2650
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2651
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2652
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2653
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2654
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2655
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2656
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2657
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2658
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2659
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2660
        default: polynom = 32'b0;
2661
        endcase
2662
        lfsr_fb = qi[length];
2663
        for (i=length-1; i>=1; i=i-1) begin
2664
            if (polynom[i])
2665
                lfsr_fb = lfsr_fb  ~^ qi[i];
2666
        end
2667
    end
2668
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2669
 
2670
   always @ (posedge clk or posedge rst)
2671
     if (rst)
2672
       qi <= {length{1'b0}};
2673
     else
2674
     if (cke)
2675
       qi <= q_next;
2676
 
2677
 
2678
 
2679
   always @ (posedge clk or posedge rst)
2680
     if (rst)
2681
       zq <= 1'b1;
2682
     else
2683
     if (cke)
2684
       zq <= q_next == {length{1'b0}};
2685
endmodule
2686
`endif
2687 40 unneback
`ifdef CNT_LFSR_CE_ZQ
2688 6 unneback
//////////////////////////////////////////////////////////////////////
2689
////                                                              ////
2690
////  Versatile counter                                           ////
2691
////                                                              ////
2692
////  Description                                                 ////
2693
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2694
////  counter                                                     ////
2695
////                                                              ////
2696
////  To Do:                                                      ////
2697
////   - add LFSR with more taps                                  ////
2698
////                                                              ////
2699
////  Author(s):                                                  ////
2700
////      - Michael Unneback, unneback@opencores.org              ////
2701
////        ORSoC AB                                              ////
2702
////                                                              ////
2703
//////////////////////////////////////////////////////////////////////
2704
////                                                              ////
2705
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2706
////                                                              ////
2707
//// This source file may be used and distributed without         ////
2708
//// restriction provided that this copyright statement is not    ////
2709
//// removed from the file and that any derivative work contains  ////
2710
//// the original copyright notice and the associated disclaimer. ////
2711
////                                                              ////
2712
//// This source file is free software; you can redistribute it   ////
2713
//// and/or modify it under the terms of the GNU Lesser General   ////
2714
//// Public License as published by the Free Software Foundation; ////
2715
//// either version 2.1 of the License, or (at your option) any   ////
2716
//// later version.                                               ////
2717
////                                                              ////
2718
//// This source is distributed in the hope that it will be       ////
2719
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2720
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2721
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2722
//// details.                                                     ////
2723
////                                                              ////
2724
//// You should have received a copy of the GNU Lesser General    ////
2725
//// Public License along with this source; if not, download it   ////
2726
//// from http://www.opencores.org/lgpl.shtml                     ////
2727
////                                                              ////
2728
//////////////////////////////////////////////////////////////////////
2729
 
2730
// LFSR counter
2731
 
2732 40 unneback
`define MODULE cnt_lfsr_ce_zq
2733
module `BASE`MODULE (
2734
`undef MODULE
2735
 cke, zq, rst, clk);
2736
 
2737 6 unneback
   parameter length = 4;
2738
   input cke;
2739
   output reg zq;
2740
   input rst;
2741
   input clk;
2742
 
2743
   parameter clear_value = 0;
2744
   parameter set_value = 1;
2745
   parameter wrap_value = 8;
2746
   parameter level1_value = 15;
2747
 
2748
   reg  [length:1] qi;
2749
   reg lfsr_fb;
2750
   wire [length:1] q_next;
2751
   reg [32:1] polynom;
2752
   integer i;
2753
 
2754
   always @ (qi)
2755
   begin
2756
        case (length)
2757
         2: polynom = 32'b11;                               // 0x3
2758
         3: polynom = 32'b110;                              // 0x6
2759
         4: polynom = 32'b1100;                             // 0xC
2760
         5: polynom = 32'b10100;                            // 0x14
2761
         6: polynom = 32'b110000;                           // 0x30
2762
         7: polynom = 32'b1100000;                          // 0x60
2763
         8: polynom = 32'b10111000;                         // 0xb8
2764
         9: polynom = 32'b100010000;                        // 0x110
2765
        10: polynom = 32'b1001000000;                       // 0x240
2766
        11: polynom = 32'b10100000000;                      // 0x500
2767
        12: polynom = 32'b100000101001;                     // 0x829
2768
        13: polynom = 32'b1000000001100;                    // 0x100C
2769
        14: polynom = 32'b10000000010101;                   // 0x2015
2770
        15: polynom = 32'b110000000000000;                  // 0x6000
2771
        16: polynom = 32'b1101000000001000;                 // 0xD008
2772
        17: polynom = 32'b10010000000000000;                // 0x12000
2773
        18: polynom = 32'b100000010000000000;               // 0x20400
2774
        19: polynom = 32'b1000000000000100011;              // 0x40023
2775 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2776 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2777
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2778
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2779
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2780
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2781
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2782
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2783
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2784
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2785
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2786
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2787
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2788
        default: polynom = 32'b0;
2789
        endcase
2790
        lfsr_fb = qi[length];
2791
        for (i=length-1; i>=1; i=i-1) begin
2792
            if (polynom[i])
2793
                lfsr_fb = lfsr_fb  ~^ qi[i];
2794
        end
2795
    end
2796
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2797
 
2798
   always @ (posedge clk or posedge rst)
2799
     if (rst)
2800
       qi <= {length{1'b0}};
2801
     else
2802
     if (cke)
2803
       qi <= q_next;
2804
 
2805
 
2806
 
2807
   always @ (posedge clk or posedge rst)
2808
     if (rst)
2809
       zq <= 1'b1;
2810
     else
2811
     if (cke)
2812
       zq <= q_next == {length{1'b0}};
2813
endmodule
2814 40 unneback
`endif
2815
`ifdef CNT_LFSR_CE_Q
2816 6 unneback
//////////////////////////////////////////////////////////////////////
2817
////                                                              ////
2818
////  Versatile counter                                           ////
2819
////                                                              ////
2820
////  Description                                                 ////
2821
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2822
////  counter                                                     ////
2823
////                                                              ////
2824
////  To Do:                                                      ////
2825
////   - add LFSR with more taps                                  ////
2826
////                                                              ////
2827
////  Author(s):                                                  ////
2828
////      - Michael Unneback, unneback@opencores.org              ////
2829
////        ORSoC AB                                              ////
2830
////                                                              ////
2831
//////////////////////////////////////////////////////////////////////
2832
////                                                              ////
2833
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2834
////                                                              ////
2835
//// This source file may be used and distributed without         ////
2836
//// restriction provided that this copyright statement is not    ////
2837