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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Blame information for rev 104

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Line No. Rev Author Line
1 40 unneback
`ifndef BASE
2
`define BASE vl_
3
`endif
4
 
5 60 unneback
// default SYN_KEEP definition
6
`define SYN_KEEP /*synthesis syn_keep = 1*/
7
 
8 44 unneback
`ifdef ACTEL
9 60 unneback
`undef SYN_KEEP
10 44 unneback
`define SYN_KEEP /*synthesis syn_keep = 1*/
11
`endif
12
 
13 98 unneback
`ifdef ACTEL
14
    // ACTEL FPGA should not use logic to handle rw collision
15
    `define SYN_NO_RW_CHECK /*synthesis syn_ramstyle = "no_rw_check"*/
16
`else
17
    `define SYN_NO_RW_CHECK
18
`endif
19
 
20 40 unneback
`ifdef ALL
21
 
22
`define GBUF
23
`define SYNC_RST
24
`define PLL
25
 
26
`define MULTS
27
`define MULTS18X18
28
`define MULT
29
`define SHIFT_UNIT_32
30
`define LOGIC_UNIT
31
 
32
`define CNT_SHREG_WRAP
33
`define CNT_SHREG_CE_WRAP
34
`define CNT_SHREG_CE_CLEAR
35
`define CNT_SHREG_CE_CLEAR_WRAP
36
 
37
`define MUX_ANDOR
38
`define MUX2_ANDOR
39
`define MUX3_ANDOR
40
`define MUX4_ANDOR
41
`define MUX5_ANDOR
42
`define MUX6_ANDOR
43 43 unneback
`define PARITY
44 40 unneback
 
45
`define ROM_INIT
46
`define RAM
47
`define RAM_BE
48
`define DPRAM_1R1W
49
`define DPRAM_2R1W
50 100 unneback
`define DPRAM_1R2W
51 40 unneback
`define DPRAM_2R2W
52 75 unneback
`define DPRAM_BE_2R2W
53 40 unneback
`define FIFO_1R1W_FILL_LEVEL_SYNC
54
`define FIFO_2R2W_SYNC_SIMPLEX
55
`define FIFO_CMP_ASYNC
56
`define FIFO_1R1W_ASYNC
57
`define FIFO_2R2W_ASYNC
58
`define FIFO_2R2W_ASYNC_SIMPLEX
59 48 unneback
`define REG_FILE
60 40 unneback
 
61
`define DFF
62
`define DFF_ARRAY
63
`define DFF_CE
64
`define DFF_CE_CLEAR
65
`define DF_CE_SET
66
`define SPR
67
`define SRP
68
`define DFF_SR
69
`define LATCH
70
`define SHREG
71
`define SHREG_CE
72
`define DELAY
73
`define DELAY_EMPTYFLAG
74 94 unneback
`define PULSE2TOGGLE
75
`define TOGGLE2PULSE
76
`define SYNCHRONIZER
77
`define CDC
78 40 unneback
 
79 75 unneback
`define WB3AVALON_BRIDGE
80 40 unneback
`define WB3WB3_BRIDGE
81
`define WB3_ARBITER_TYPE1
82 83 unneback
`define WB_ADR_INC
83 101 unneback
`define WB_RAM
84 103 unneback
`define WB_SHADOW_RAM
85 48 unneback
`define WB_B4_ROM
86 40 unneback
`define WB_BOOT_ROM
87
`define WB_DPRAM
88 101 unneback
`define WB_CACHE
89 103 unneback
`define WB_AVALON_BRIDGE
90
`define WB_AVALON_MEM_CACHE
91 40 unneback
 
92 44 unneback
`define IO_DFF_OE
93
`define O_DFF
94
 
95 40 unneback
`endif
96
 
97
`ifdef PLL
98
`ifndef SYNC_RST
99
`define SYNC_RST
100
`endif
101
`endif
102
 
103
`ifdef SYNC_RST
104
`ifndef GBUF
105
`define GBUF
106
`endif
107
`endif
108
 
109 92 unneback
`ifdef WB_B3_DPRAM
110
`ifndef WB_ADR_INC
111
`define WB_ADR_INC
112 40 unneback
`endif
113 92 unneback
`ifndef DPRAM_BE_2R2W
114
`define DPRAM_BE_2R2W
115 40 unneback
`endif
116
`endif
117
 
118 101 unneback
`ifdef WB_RAM
119 83 unneback
`ifndef WB_ADR_INC
120
`define WB_ADR_INC
121 62 unneback
`endif
122
`ifndef RAM_BE
123
`define RAM_BE
124
`endif
125
`endif
126
 
127 40 unneback
`ifdef WB3_ARBITER_TYPE1
128 42 unneback
`ifndef SPR
129
`define SPR
130
`endif
131 40 unneback
`ifndef MUX_ANDOR
132
`define MUX_ANDOR
133
`endif
134
`endif
135
 
136 76 unneback
`ifdef WB3AVALON_BRIDGE
137
`ifndef WB3WB3_BRIDGE
138
`define WB3WB3_BRIDGE
139
`endif
140
`endif
141
 
142 40 unneback
`ifdef WB3WB3_BRIDGE
143
`ifndef CNT_SHREG_CE_CLEAR
144
`define CNT_SHREG_CE_CLEAR
145
`endif
146
`ifndef DFF
147
`define DFF
148
`endif
149
`ifndef DFF_CE
150
`define DFF_CE
151
`endif
152
`ifndef CNT_SHREG_CE_CLEAR
153
`define CNT_SHREG_CE_CLEAR
154
`endif
155
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
156
`define FIFO_2R2W_ASYNC_SIMPLEX
157
`endif
158
`endif
159
 
160 103 unneback
 
161
`ifdef WB_AVALON_MEM_CACHE
162
`ifndef WB_SHADOW_RAM
163
`define WB_SHADOW_RAM
164
`endif
165
`ifndef WB_CACHE
166
`define WB_CACHE
167
`endif
168
`ifndef WB_AVALON_BRIDGE
169
`define WB_AVALON_BRIDGE
170
`endif
171
`endif
172
 
173 101 unneback
`ifdef WB_CACHE
174 100 unneback
`ifndef RAM
175
`define RAM
176
`endif
177
`ifndef WB_ADR_INC
178
`define WB_ADR_INC
179
`endif
180
`ifndef DPRAM_1R1W
181
`define DPRAM_1R1W
182
`endif
183
`ifndef DPRAM_1R2W
184
`define DPRAM_1R2W
185
`endif
186
`ifndef DPRAM_BE_2R2W
187
`define DPRAM_BE_2R2W
188
`endif
189
`ifndef CDC
190
`define CDC
191
`endif
192
`endif
193 103 unneback
 
194
`ifdef WB_SHADOW_RAM
195
`ifndef WB_RAM
196
`define WB_RAM
197
`endif
198
`endif
199
 
200
`ifdef WB_RAM
201
`ifndef WB_ADR_INC
202
`define WB_ADR_INC
203
`endif
204
`endif
205 97 unneback
 
206 40 unneback
`ifdef MULTS18X18
207
`ifndef MULTS
208
`define MULTS
209
`endif
210
`endif
211
 
212
`ifdef SHIFT_UNIT_32
213
`ifndef MULTS
214
`define MULTS
215
`endif
216
`endif
217
 
218
`ifdef MUX2_ANDOR
219
`ifndef MUX_ANDOR
220
`define MUX_ANDOR
221
`endif
222
`endif
223
 
224
`ifdef MUX3_ANDOR
225
`ifndef MUX_ANDOR
226
`define MUX_ANDOR
227
`endif
228
`endif
229
 
230
`ifdef MUX4_ANDOR
231
`ifndef MUX_ANDOR
232
`define MUX_ANDOR
233
`endif
234
`endif
235
 
236
`ifdef MUX5_ANDOR
237
`ifndef MUX_ANDOR
238
`define MUX_ANDOR
239
`endif
240
`endif
241
 
242
`ifdef MUX6_ANDOR
243
`ifndef MUX_ANDOR
244
`define MUX_ANDOR
245
`endif
246
`endif
247
 
248
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
249
`ifndef CNT_BIN_CE
250
`define CNT_BIN_CE
251
`endif
252
`ifndef DPRAM_1R1W
253
`define DPRAM_1R1W
254
`endif
255
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
256
`define CNT_BIN_CE_REW_Q_ZQ_L1
257
`endif
258
`endif
259
 
260
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
261
`ifndef CNT_LFSR_CE
262
`define CNT_LFSR_CE
263
`endif
264
`ifndef DPRAM_2R2W
265
`define DPRAM_2R2W
266
`endif
267
`ifndef CNT_BIN_CE_REW_ZQ_L1
268
`define CNT_BIN_CE_REW_ZQ_L1
269
`endif
270
`endif
271
 
272
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
273
`ifndef CNT_GRAY_CE_BIN
274
`define CNT_GRAY_CE_BIN
275
`endif
276
`ifndef DPRAM_2R2W
277
`define DPRAM_2R2W
278
`endif
279
`ifndef FIFO_CMP_ASYNC
280
`define FIFO_CMP_ASYNC
281
`endif
282
`endif
283
 
284
`ifdef FIFO_2R2W_ASYNC
285
`ifndef FIFO_1R1W_ASYNC
286
`define FIFO_1R1W_ASYNC
287
`endif
288
`endif
289
 
290
`ifdef FIFO_1R1W_ASYNC
291
`ifndef CNT_GRAY_CE_BIN
292
`define CNT_GRAY_CE_BIN
293
`endif
294
`ifndef DPRAM_1R1W
295
`define DPRAM_1R1W
296
`endif
297
`ifndef FIFO_CMP_ASYNC
298
`define FIFO_CMP_ASYNC
299
`endif
300
`endif
301
 
302
`ifdef FIFO_CMP_ASYNC
303
`ifndef DFF_SR
304
`define DFF_SR
305
`endif
306
`ifndef DFF
307
`define DFF
308
`endif
309
`endif
310 48 unneback
 
311
`ifdef REG_FILE
312
`ifndef DPRAM_1R1W
313
`define DPRAM_1R1W
314
`endif
315
`endif
316 97 unneback
 
317 98 unneback
`ifdef CDC
318
`ifndef PULSE2TOGGLE
319
`define PULSE2TOGGLE
320
`endif
321
`ifndef TOGGLE2PULSE
322
`define TOGGLE2PULSE
323
`endif
324
`ifndef SYNCHRONIZER
325
`define SYNCHRONIZER
326
`endif
327
`endif
328
 
329 97 unneback
// size to width
330 100 unneback
`define SIZE2WIDTH_EXPR = (`SIZE2WIDTH==1) ? 0 : (`SIZE2WIDTH==2) ? 1 : (`SIZE2WIDTH==4) ? 2 : (`SIZE2WIDTH==8) ? 3 : (`SIZE2WIDTH==16) ? 4 : (`SIZE2WIDTH==32) ? 5 : (`SIZE2WIDTH==64) ? 6 : (`SIZE2WIDTH==128) ? 7 : 8;
331 62 unneback
//////////////////////////////////////////////////////////////////////
332 6 unneback
////                                                              ////
333
////  Versatile library, clock and reset                          ////
334
////                                                              ////
335
////  Description                                                 ////
336
////  Logic related to clock and reset                            ////
337
////                                                              ////
338
////                                                              ////
339
////  To Do:                                                      ////
340
////   - add more different registers                             ////
341
////                                                              ////
342
////  Author(s):                                                  ////
343
////      - Michael Unneback, unneback@opencores.org              ////
344
////        ORSoC AB                                              ////
345
////                                                              ////
346
//////////////////////////////////////////////////////////////////////
347
////                                                              ////
348
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
349
////                                                              ////
350
//// This source file may be used and distributed without         ////
351
//// restriction provided that this copyright statement is not    ////
352
//// removed from the file and that any derivative work contains  ////
353
//// the original copyright notice and the associated disclaimer. ////
354
////                                                              ////
355
//// This source file is free software; you can redistribute it   ////
356
//// and/or modify it under the terms of the GNU Lesser General   ////
357
//// Public License as published by the Free Software Foundation; ////
358
//// either version 2.1 of the License, or (at your option) any   ////
359
//// later version.                                               ////
360
////                                                              ////
361
//// This source is distributed in the hope that it will be       ////
362
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
363
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
364
//// PURPOSE.  See the GNU Lesser General Public License for more ////
365
//// details.                                                     ////
366
////                                                              ////
367
//// You should have received a copy of the GNU Lesser General    ////
368
//// Public License along with this source; if not, download it   ////
369
//// from http://www.opencores.org/lgpl.shtml                     ////
370
////                                                              ////
371
//////////////////////////////////////////////////////////////////////
372
 
373 48 unneback
`ifdef ACTEL
374
`ifdef GBUF
375
`timescale 1 ns/100 ps
376 6 unneback
// Global buffer
377
// usage:
378
// use to enable global buffers for high fan out signals such as clock and reset
379
// Version: 8.4 8.4.0.33
380
module gbuf(GL,CLK);
381
output GL;
382
input  CLK;
383
 
384
    wire GND;
385
 
386
    GND GND_1_net(.Y(GND));
387
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
388
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
389
 
390
endmodule
391
`timescale 1 ns/1 ns
392 40 unneback
`define MODULE gbuf
393
module `BASE`MODULE ( i, o);
394
`undef MODULE
395 6 unneback
input i;
396
output o;
397
`ifdef SIM_GBUF
398
assign o=i;
399
`else
400
gbuf gbuf_i0 ( .CLK(i), .GL(o));
401
`endif
402
endmodule
403 40 unneback
`endif
404 33 unneback
 
405 6 unneback
`else
406 33 unneback
 
407 40 unneback
`ifdef ALTERA
408
`ifdef GBUF
409 21 unneback
//altera
410 40 unneback
`define MODULE gbuf
411
module `BASE`MODULE ( i, o);
412
`undef MODULE
413 33 unneback
input i;
414
output o;
415
assign o = i;
416
endmodule
417 40 unneback
`endif
418 33 unneback
 
419 6 unneback
`else
420
 
421 40 unneback
`ifdef GBUF
422 6 unneback
`timescale 1 ns/100 ps
423 40 unneback
`define MODULE
424
module `BASE`MODULE ( i, o);
425
`undef MODULE
426 6 unneback
input i;
427
output o;
428
assign o = i;
429
endmodule
430 40 unneback
`endif
431 6 unneback
`endif // ALTERA
432
`endif //ACTEL
433
 
434 40 unneback
`ifdef SYNC_RST
435 6 unneback
// sync reset
436 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
437 6 unneback
// output active high global reset sync with two DFFs 
438
`timescale 1 ns/100 ps
439 40 unneback
`define MODULE sync_rst
440
module `BASE`MODULE ( rst_n_i, rst_o, clk);
441
`undef MODULE
442 6 unneback
input rst_n_i, clk;
443
output rst_o;
444 18 unneback
reg [1:0] tmp;
445 6 unneback
always @ (posedge clk or negedge rst_n_i)
446
if (!rst_n_i)
447 17 unneback
        tmp <= 2'b11;
448 6 unneback
else
449 33 unneback
        tmp <= {1'b0,tmp[1]};
450 40 unneback
`define MODULE gbuf
451
`BASE`MODULE buf_i0( .i(tmp[0]), .o(rst_o));
452
`undef MODULE
453 6 unneback
endmodule
454 40 unneback
`endif
455 6 unneback
 
456 40 unneback
`ifdef PLL
457 6 unneback
// vl_pll
458
`ifdef ACTEL
459 32 unneback
///////////////////////////////////////////////////////////////////////////////
460 17 unneback
`timescale 1 ps/1 ps
461 40 unneback
`define MODULE pll
462
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
463
`undef MODULE
464 6 unneback
parameter index = 0;
465
parameter number_of_clk = 1;
466 17 unneback
parameter period_time_0 = 20000;
467
parameter period_time_1 = 20000;
468
parameter period_time_2 = 20000;
469
parameter lock_delay = 2000000;
470 6 unneback
input clk_i, rst_n_i;
471
output lock;
472
output reg [0:number_of_clk-1] clk_o;
473
output [0:number_of_clk-1] rst_o;
474
 
475
`ifdef SIM_PLL
476
 
477
always
478
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
479
 
480
generate if (number_of_clk > 1)
481
always
482
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
483
endgenerate
484
 
485
generate if (number_of_clk > 2)
486
always
487
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
488
endgenerate
489
 
490
genvar i;
491
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
492
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
493
end
494
endgenerate
495
 
496
assign #lock_delay lock = rst_n_i;
497
 
498
endmodule
499
`else
500
generate if (number_of_clk==1 & index==0) begin
501
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
502
end
503
endgenerate // index==0
504
generate if (number_of_clk==1 & index==1) begin
505
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
506
end
507
endgenerate // index==1
508
generate if (number_of_clk==1 & index==2) begin
509
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
510
end
511
endgenerate // index==2
512
generate if (number_of_clk==1 & index==3) begin
513
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
514
end
515
endgenerate // index==0
516
 
517
generate if (number_of_clk==2 & index==0) begin
518
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
519
end
520
endgenerate // index==0
521
generate if (number_of_clk==2 & index==1) begin
522
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
523
end
524
endgenerate // index==1
525
generate if (number_of_clk==2 & index==2) begin
526
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
527
end
528
endgenerate // index==2
529
generate if (number_of_clk==2 & index==3) begin
530
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
531
end
532
endgenerate // index==0
533
 
534
generate if (number_of_clk==3 & index==0) begin
535
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
536
end
537
endgenerate // index==0
538
generate if (number_of_clk==3 & index==1) begin
539
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
540
end
541
endgenerate // index==1
542
generate if (number_of_clk==3 & index==2) begin
543
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
544
end
545
endgenerate // index==2
546
generate if (number_of_clk==3 & index==3) begin
547
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
548
end
549
endgenerate // index==0
550
 
551
genvar i;
552
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
553 40 unneback
`define MODULE sync_rst
554
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
555
`undef MODULE
556 6 unneback
end
557
endgenerate
558
endmodule
559
`endif
560 32 unneback
///////////////////////////////////////////////////////////////////////////////
561 6 unneback
 
562
`else
563
 
564 32 unneback
///////////////////////////////////////////////////////////////////////////////
565 6 unneback
`ifdef ALTERA
566
 
567 32 unneback
`timescale 1 ps/1 ps
568 40 unneback
`define MODULE pll
569
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
570
`undef MODULE
571 32 unneback
parameter index = 0;
572
parameter number_of_clk = 1;
573
parameter period_time_0 = 20000;
574
parameter period_time_1 = 20000;
575
parameter period_time_2 = 20000;
576
parameter period_time_3 = 20000;
577
parameter period_time_4 = 20000;
578
parameter lock_delay = 2000000;
579
input clk_i, rst_n_i;
580
output lock;
581
output reg [0:number_of_clk-1] clk_o;
582
output [0:number_of_clk-1] rst_o;
583
 
584
`ifdef SIM_PLL
585
 
586
always
587
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
588
 
589
generate if (number_of_clk > 1)
590
always
591
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
592
endgenerate
593
 
594
generate if (number_of_clk > 2)
595
always
596
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
597
endgenerate
598
 
599 33 unneback
generate if (number_of_clk > 3)
600 32 unneback
always
601
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
602
endgenerate
603
 
604 33 unneback
generate if (number_of_clk > 4)
605 32 unneback
always
606
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
607
endgenerate
608
 
609
genvar i;
610
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
611
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
612
end
613
endgenerate
614
 
615 33 unneback
//assign #lock_delay lock = rst_n_i;
616
assign lock = rst_n_i;
617 32 unneback
 
618
endmodule
619 6 unneback
`else
620
 
621 33 unneback
`ifdef VL_PLL0
622
`ifdef VL_PLL0_CLK1
623
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
624
`endif
625
`ifdef VL_PLL0_CLK2
626
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
627
`endif
628
`ifdef VL_PLL0_CLK3
629
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
630
`endif
631
`ifdef VL_PLL0_CLK4
632
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
633
`endif
634
`ifdef VL_PLL0_CLK5
635
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
636
`endif
637
`endif
638 32 unneback
 
639 33 unneback
`ifdef VL_PLL1
640
`ifdef VL_PLL1_CLK1
641
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
642
`endif
643
`ifdef VL_PLL1_CLK2
644
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
645
`endif
646
`ifdef VL_PLL1_CLK3
647
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
648
`endif
649
`ifdef VL_PLL1_CLK4
650
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
651
`endif
652
`ifdef VL_PLL1_CLK5
653
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
654
`endif
655
`endif
656 32 unneback
 
657 33 unneback
`ifdef VL_PLL2
658
`ifdef VL_PLL2_CLK1
659
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
660
`endif
661
`ifdef VL_PLL2_CLK2
662
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
663
`endif
664
`ifdef VL_PLL2_CLK3
665
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
666
`endif
667
`ifdef VL_PLL2_CLK4
668
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
669
`endif
670
`ifdef VL_PLL2_CLK5
671
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
672
`endif
673
`endif
674 32 unneback
 
675 33 unneback
`ifdef VL_PLL3
676
`ifdef VL_PLL3_CLK1
677
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
678
`endif
679
`ifdef VL_PLL3_CLK2
680
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
681
`endif
682
`ifdef VL_PLL3_CLK3
683
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
684
`endif
685
`ifdef VL_PLL3_CLK4
686
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
687
`endif
688
`ifdef VL_PLL3_CLK5
689
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
690
`endif
691
`endif
692 32 unneback
 
693
genvar i;
694
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
695 40 unneback
`define MODULE sync_rst
696
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
697
`undef MODULE
698 32 unneback
end
699
endgenerate
700
endmodule
701
`endif
702
///////////////////////////////////////////////////////////////////////////////
703
 
704
`else
705
 
706 6 unneback
// generic PLL
707 17 unneback
`timescale 1 ps/1 ps
708 40 unneback
`define MODULE pll
709
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
710
`undef MODULE
711 6 unneback
parameter index = 0;
712
parameter number_of_clk = 1;
713 17 unneback
parameter period_time_0 = 20000;
714
parameter period_time_1 = 20000;
715
parameter period_time_2 = 20000;
716 6 unneback
parameter lock_delay = 2000;
717
input clk_i, rst_n_i;
718
output lock;
719
output reg [0:number_of_clk-1] clk_o;
720
output [0:number_of_clk-1] rst_o;
721
 
722
always
723
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
724
 
725
generate if (number_of_clk > 1)
726
always
727
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
728
endgenerate
729
 
730
generate if (number_of_clk > 2)
731
always
732
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
733
endgenerate
734
 
735
genvar i;
736
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
737 40 unneback
`define MODULE sync_rst
738
     `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
739
`undef MODULE
740 6 unneback
end
741
endgenerate
742
 
743
assign #lock_delay lock = rst_n_i;
744
 
745
endmodule
746
 
747
`endif //altera
748 17 unneback
`endif //actel
749 40 unneback
`undef MODULE
750
`endif//////////////////////////////////////////////////////////////////////
751 6 unneback
////                                                              ////
752
////  Versatile library, registers                                ////
753
////                                                              ////
754
////  Description                                                 ////
755
////  Different type of registers                                 ////
756
////                                                              ////
757
////                                                              ////
758
////  To Do:                                                      ////
759
////   - add more different registers                             ////
760
////                                                              ////
761
////  Author(s):                                                  ////
762
////      - Michael Unneback, unneback@opencores.org              ////
763
////        ORSoC AB                                              ////
764
////                                                              ////
765
//////////////////////////////////////////////////////////////////////
766
////                                                              ////
767
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
768
////                                                              ////
769
//// This source file may be used and distributed without         ////
770
//// restriction provided that this copyright statement is not    ////
771
//// removed from the file and that any derivative work contains  ////
772
//// the original copyright notice and the associated disclaimer. ////
773
////                                                              ////
774
//// This source file is free software; you can redistribute it   ////
775
//// and/or modify it under the terms of the GNU Lesser General   ////
776
//// Public License as published by the Free Software Foundation; ////
777
//// either version 2.1 of the License, or (at your option) any   ////
778
//// later version.                                               ////
779
////                                                              ////
780
//// This source is distributed in the hope that it will be       ////
781
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
782
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
783
//// PURPOSE.  See the GNU Lesser General Public License for more ////
784
//// details.                                                     ////
785
////                                                              ////
786
//// You should have received a copy of the GNU Lesser General    ////
787
//// Public License along with this source; if not, download it   ////
788
//// from http://www.opencores.org/lgpl.shtml                     ////
789
////                                                              ////
790
//////////////////////////////////////////////////////////////////////
791
 
792 40 unneback
`ifdef DFF
793
`define MODULE dff
794
module `BASE`MODULE ( d, q, clk, rst);
795
`undef MODULE
796 6 unneback
        parameter width = 1;
797
        parameter reset_value = 0;
798
 
799
        input [width-1:0] d;
800
        input clk, rst;
801
        output reg [width-1:0] q;
802
 
803
        always @ (posedge clk or posedge rst)
804
        if (rst)
805
                q <= reset_value;
806
        else
807
                q <= d;
808
 
809
endmodule
810 40 unneback
`endif
811 6 unneback
 
812 40 unneback
`ifdef DFF_ARRAY
813
`define MODULE dff_array
814
module `BASE`MODULE ( d, q, clk, rst);
815
`undef MODULE
816 6 unneback
 
817
        parameter width = 1;
818
        parameter depth = 2;
819
        parameter reset_value = 1'b0;
820
 
821
        input [width-1:0] d;
822
        input clk, rst;
823
        output [width-1:0] q;
824
        reg  [0:depth-1] q_tmp [width-1:0];
825
        integer i;
826
        always @ (posedge clk or posedge rst)
827
        if (rst) begin
828
            for (i=0;i<depth;i=i+1)
829
                q_tmp[i] <= {width{reset_value}};
830
        end else begin
831
            q_tmp[0] <= d;
832
            for (i=1;i<depth;i=i+1)
833
                q_tmp[i] <= q_tmp[i-1];
834
        end
835
 
836
    assign q = q_tmp[depth-1];
837
 
838
endmodule
839 40 unneback
`endif
840 6 unneback
 
841 40 unneback
`ifdef DFF_CE
842
`define MODULE dff_ce
843
module `BASE`MODULE ( d, ce, q, clk, rst);
844
`undef MODULE
845 6 unneback
 
846
        parameter width = 1;
847
        parameter reset_value = 0;
848
 
849
        input [width-1:0] d;
850
        input ce, clk, rst;
851
        output reg [width-1:0] q;
852
 
853
        always @ (posedge clk or posedge rst)
854
        if (rst)
855
                q <= reset_value;
856
        else
857
                if (ce)
858
                        q <= d;
859
 
860
endmodule
861 40 unneback
`endif
862 6 unneback
 
863 40 unneback
`ifdef DFF_CE_CLEAR
864
`define MODULE dff_ce_clear
865
module `BASE`MODULE ( d, ce, clear, q, clk, rst);
866
`undef MODULE
867 8 unneback
 
868
        parameter width = 1;
869
        parameter reset_value = 0;
870
 
871
        input [width-1:0] d;
872 10 unneback
        input ce, clear, clk, rst;
873 8 unneback
        output reg [width-1:0] q;
874
 
875
        always @ (posedge clk or posedge rst)
876
        if (rst)
877
            q <= reset_value;
878
        else
879
            if (ce)
880
                if (clear)
881
                    q <= {width{1'b0}};
882
                else
883
                    q <= d;
884
 
885
endmodule
886 40 unneback
`endif
887 8 unneback
 
888 40 unneback
`ifdef DF_CE_SET
889
`define MODULE dff_ce_set
890
module `BASE`MODULE ( d, ce, set, q, clk, rst);
891
`undef MODULE
892 24 unneback
 
893
        parameter width = 1;
894
        parameter reset_value = 0;
895
 
896
        input [width-1:0] d;
897
        input ce, set, clk, rst;
898
        output reg [width-1:0] q;
899
 
900
        always @ (posedge clk or posedge rst)
901
        if (rst)
902
            q <= reset_value;
903
        else
904
            if (ce)
905
                if (set)
906
                    q <= {width{1'b1}};
907
                else
908
                    q <= d;
909
 
910
endmodule
911 40 unneback
`endif
912 24 unneback
 
913 40 unneback
`ifdef SPR
914
`define MODULE spr
915
module `BASE`MODULE ( sp, r, q, clk, rst);
916
`undef MODULE
917
 
918 64 unneback
        //parameter width = 1;
919
        parameter reset_value = 1'b0;
920 29 unneback
 
921
        input sp, r;
922
        output reg q;
923
        input clk, rst;
924
 
925
        always @ (posedge clk or posedge rst)
926
        if (rst)
927
            q <= reset_value;
928
        else
929
            if (sp)
930
                q <= 1'b1;
931
            else if (r)
932
                q <= 1'b0;
933
 
934
endmodule
935 40 unneback
`endif
936 29 unneback
 
937 40 unneback
`ifdef SRP
938
`define MODULE srp
939
module `BASE`MODULE ( s, rp, q, clk, rst);
940
`undef MODULE
941
 
942 29 unneback
        parameter width = 1;
943
        parameter reset_value = 0;
944
 
945
        input s, rp;
946
        output reg q;
947
        input clk, rst;
948
 
949
        always @ (posedge clk or posedge rst)
950
        if (rst)
951
            q <= reset_value;
952
        else
953
            if (rp)
954
                q <= 1'b0;
955
            else if (s)
956
                q <= 1'b1;
957
 
958
endmodule
959 40 unneback
`endif
960 29 unneback
 
961 40 unneback
`ifdef ALTERA
962 29 unneback
 
963 40 unneback
`ifdef DFF_SR
964 6 unneback
// megafunction wizard: %LPM_FF%
965
// GENERATION: STANDARD
966
// VERSION: WM1.0
967
// MODULE: lpm_ff 
968
 
969
// ============================================================
970
// File Name: dff_sr.v
971
// Megafunction Name(s):
972
//                      lpm_ff
973
//
974
// Simulation Library Files(s):
975
//                      lpm
976
// ============================================================
977
// ************************************************************
978
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
979
//
980
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
981
// ************************************************************
982
 
983
 
984
//Copyright (C) 1991-2010 Altera Corporation
985
//Your use of Altera Corporation's design tools, logic functions 
986
//and other software and tools, and its AMPP partner logic 
987
//functions, and any output files from any of the foregoing 
988
//(including device programming or simulation files), and any 
989
//associated documentation or information are expressly subject 
990
//to the terms and conditions of the Altera Program License 
991
//Subscription Agreement, Altera MegaCore Function License 
992
//Agreement, or other applicable license agreement, including, 
993
//without limitation, that your use is for the sole purpose of 
994
//programming logic devices manufactured by Altera and sold by 
995
//Altera or its authorized distributors.  Please refer to the 
996
//applicable agreement for further details.
997
 
998
 
999
// synopsys translate_off
1000
`timescale 1 ps / 1 ps
1001
// synopsys translate_on
1002 40 unneback
`define MODULE dff_sr
1003
module `BASE`MODULE (
1004
`undef MODULE
1005
 
1006 6 unneback
        aclr,
1007
        aset,
1008
        clock,
1009
        data,
1010
        q);
1011
 
1012
        input     aclr;
1013
        input     aset;
1014
        input     clock;
1015
        input     data;
1016
        output    q;
1017
 
1018
        wire [0:0] sub_wire0;
1019
        wire [0:0] sub_wire1 = sub_wire0[0:0];
1020
        wire  q = sub_wire1;
1021
        wire  sub_wire2 = data;
1022
        wire  sub_wire3 = sub_wire2;
1023
 
1024
        lpm_ff  lpm_ff_component (
1025
                                .aclr (aclr),
1026
                                .clock (clock),
1027
                                .data (sub_wire3),
1028
                                .aset (aset),
1029
                                .q (sub_wire0)
1030
                                // synopsys translate_off
1031
                                ,
1032
                                .aload (),
1033
                                .enable (),
1034
                                .sclr (),
1035
                                .sload (),
1036
                                .sset ()
1037
                                // synopsys translate_on
1038
                                );
1039
        defparam
1040
                lpm_ff_component.lpm_fftype = "DFF",
1041
                lpm_ff_component.lpm_type = "LPM_FF",
1042
                lpm_ff_component.lpm_width = 1;
1043
 
1044
 
1045
endmodule
1046
 
1047
// ============================================================
1048
// CNX file retrieval info
1049
// ============================================================
1050
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
1051
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
1052
// Retrieval info: PRIVATE: ASET NUMERIC "1"
1053
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
1054
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
1055
// Retrieval info: PRIVATE: DFF NUMERIC "1"
1056
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
1057
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
1058
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
1059
// Retrieval info: PRIVATE: SSET NUMERIC "0"
1060
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
1061
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
1062
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
1063
// Retrieval info: PRIVATE: nBit NUMERIC "1"
1064
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
1065
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
1066
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
1067
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
1068
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
1069
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
1070
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
1071
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
1072
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
1073
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
1074
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
1075
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
1076
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
1077
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
1078
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
1079
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
1080
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
1081
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
1082
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
1083
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
1084
// Retrieval info: LIB_FILE: lpm
1085 40 unneback
`endif
1086 6 unneback
 
1087
`else
1088
 
1089 40 unneback
`ifdef DFF_SR
1090
`define MODULE dff_sr
1091
module `BASE`MODULE ( aclr, aset, clock, data, q);
1092
`undef MODULE
1093 6 unneback
 
1094
    input         aclr;
1095
    input         aset;
1096
    input         clock;
1097
    input         data;
1098
    output reg    q;
1099
 
1100
   always @ (posedge clock or posedge aclr or posedge aset)
1101
     if (aclr)
1102
       q <= 1'b0;
1103
     else if (aset)
1104
       q <= 1'b1;
1105
     else
1106
       q <= data;
1107
 
1108
endmodule
1109 40 unneback
`endif
1110 6 unneback
 
1111
`endif
1112
 
1113
// LATCH
1114
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
1115
`ifdef ALTERA
1116 40 unneback
 
1117
`ifdef LATCH
1118
`define MODULE latch
1119
module `BASE`MODULE ( d, le, q, clk);
1120
`undef MODULE
1121 6 unneback
input d, le;
1122
output q;
1123
input clk;
1124
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
1125
endmodule
1126 40 unneback
`endif
1127
 
1128 6 unneback
`else
1129 40 unneback
 
1130
`ifdef LATCH
1131
`define MODULE latch
1132
module `BASE`MODULE ( d, le, q, clk);
1133
`undef MODULE
1134 6 unneback
input d, le;
1135 48 unneback
input clk;
1136
always @ (le or d)
1137 60 unneback
if (le)
1138 48 unneback
    d <= q;
1139 6 unneback
endmodule
1140 15 unneback
`endif
1141
 
1142 40 unneback
`endif
1143
 
1144
`ifdef SHREG
1145
`define MODULE shreg
1146
module `BASE`MODULE ( d, q, clk, rst);
1147
`undef MODULE
1148
 
1149 17 unneback
parameter depth = 10;
1150
input d;
1151
output q;
1152
input clk, rst;
1153
 
1154
reg [1:depth] dffs;
1155
 
1156
always @ (posedge clk or posedge rst)
1157
if (rst)
1158
    dffs <= {depth{1'b0}};
1159
else
1160
    dffs <= {d,dffs[1:depth-1]};
1161
assign q = dffs[depth];
1162
endmodule
1163 40 unneback
`endif
1164 17 unneback
 
1165 40 unneback
`ifdef SHREG_CE
1166
`define MODULE shreg_ce
1167
module `BASE`MODULE ( d, ce, q, clk, rst);
1168
`undef MODULE
1169 17 unneback
parameter depth = 10;
1170
input d, ce;
1171
output q;
1172
input clk, rst;
1173
 
1174
reg [1:depth] dffs;
1175
 
1176
always @ (posedge clk or posedge rst)
1177
if (rst)
1178
    dffs <= {depth{1'b0}};
1179
else
1180
    if (ce)
1181
        dffs <= {d,dffs[1:depth-1]};
1182
assign q = dffs[depth];
1183
endmodule
1184 40 unneback
`endif
1185 17 unneback
 
1186 40 unneback
`ifdef DELAY
1187
`define MODULE delay
1188
module `BASE`MODULE ( d, q, clk, rst);
1189
`undef MODULE
1190 15 unneback
parameter depth = 10;
1191
input d;
1192
output q;
1193
input clk, rst;
1194
 
1195
reg [1:depth] dffs;
1196
 
1197
always @ (posedge clk or posedge rst)
1198
if (rst)
1199
    dffs <= {depth{1'b0}};
1200
else
1201
    dffs <= {d,dffs[1:depth-1]};
1202
assign q = dffs[depth];
1203 17 unneback
endmodule
1204 40 unneback
`endif
1205 17 unneback
 
1206 40 unneback
`ifdef DELAY_EMPTYFLAG
1207
`define MODULE delay_emptyflag
1208 41 unneback
module `BASE`MODULE ( d, q, emptyflag, clk, rst);
1209 40 unneback
`undef MODULE
1210 17 unneback
parameter depth = 10;
1211
input d;
1212
output q, emptyflag;
1213
input clk, rst;
1214
 
1215
reg [1:depth] dffs;
1216
 
1217
always @ (posedge clk or posedge rst)
1218
if (rst)
1219
    dffs <= {depth{1'b0}};
1220
else
1221
    dffs <= {d,dffs[1:depth-1]};
1222
assign q = dffs[depth];
1223
assign emptyflag = !(|dffs);
1224
endmodule
1225 40 unneback
`endif
1226 75 unneback
 
1227 94 unneback
`ifdef PULSE2TOGGLE
1228 98 unneback
`define MODULE pulse2toggle
1229
module `BASE`MODULE ( pl, q, clk, rst);
1230 75 unneback
`undef MODULE
1231 94 unneback
input pl;
1232 98 unneback
output reg q;
1233 94 unneback
input clk, rst;
1234
always @ (posedge clk or posedge rst)
1235 75 unneback
if (rst)
1236 94 unneback
    q <= 1'b0;
1237 75 unneback
else
1238 94 unneback
    q <= pl ^ q;
1239
endmodule
1240
`endif
1241 75 unneback
 
1242 94 unneback
`ifdef TOGGLE2PULSE
1243 98 unneback
`define MODULE toggle2pulse
1244 94 unneback
module `BASE`MODULE (d, pl, clk, rst);
1245 97 unneback
`undef MODULE
1246 94 unneback
input d;
1247
output pl;
1248
input clk, rst;
1249
reg dff;
1250
always @ (posedge clk or posedge rst)
1251
if (rst)
1252
    dff <= 1'b0;
1253 75 unneback
else
1254 94 unneback
    dff <= d;
1255 98 unneback
assign pl = d ^ dff;
1256 94 unneback
endmodule
1257
`endif
1258 75 unneback
 
1259 94 unneback
`ifdef SYNCHRONIZER
1260
`define MODULE synchronizer
1261
module `BASE`MODULE (d, q, clk, rst);
1262
`undef MODULE
1263
input d;
1264
output reg q;
1265
output clk, rst;
1266
reg dff;
1267
always @ (posedge clk or posedge rst)
1268
if (rst)
1269 100 unneback
    {q,dff} <= 2'b00;
1270 75 unneback
else
1271 100 unneback
    {q,dff} <= {dff,d};
1272 94 unneback
endmodule
1273
`endif
1274 75 unneback
 
1275 94 unneback
`ifdef CDC
1276
`define MODULE cdc
1277 97 unneback
module `BASE`MODULE ( start_pl, take_it_pl, take_it_grant_pl, got_it_pl, clk_src, rst_src, clk_dst, rst_dst);
1278 94 unneback
`undef MODULE
1279
input start_pl;
1280
output take_it_pl;
1281
input take_it_grant_pl; // note: connect to take_it_pl to generate automatic ack
1282
output got_it_pl;
1283
input clk_src, rst_src;
1284
input clk_dst, rst_dst;
1285
wire take_it_tg, take_it_tg_sync;
1286
wire got_it_tg, got_it_tg_sync;
1287
// src -> dst
1288
`define MODULE pulse2toggle
1289
`BASE`MODULE p2t0 (
1290
`undef MODULE
1291
    .pl(start_pl),
1292
    .q(take_it_tg),
1293
    .clk(clk_src),
1294
    .rst(rst_src));
1295 75 unneback
 
1296 94 unneback
`define MODULE synchronizer
1297
`BASE`MODULE sync0 (
1298
`undef MODULE
1299
    .d(take_it_tg),
1300
    .q(take_it_tg_sync),
1301
    .clk(clk_dst),
1302
    .rst(rst_dst));
1303
 
1304
`define MODULE toggle2pulse
1305
`BASE`MODULE t2p0 (
1306
`undef MODULE
1307 100 unneback
    .d(take_it_tg_sync),
1308 94 unneback
    .pl(take_it_pl),
1309
    .clk(clk_dst),
1310
    .rst(rst_dst));
1311
 
1312
// dst -> src
1313
`define MODULE pulse2toggle
1314 98 unneback
`BASE`MODULE p2t1 (
1315 94 unneback
`undef MODULE
1316
    .pl(take_it_grant_pl),
1317
    .q(got_it_tg),
1318
    .clk(clk_dst),
1319
    .rst(rst_dst));
1320
 
1321
`define MODULE synchronizer
1322
`BASE`MODULE sync1 (
1323
`undef MODULE
1324
    .d(got_it_tg),
1325
    .q(got_it_tg_sync),
1326
    .clk(clk_src),
1327
    .rst(rst_src));
1328
 
1329
`define MODULE toggle2pulse
1330
`BASE`MODULE t2p1 (
1331
`undef MODULE
1332 100 unneback
    .d(got_it_tg_sync),
1333 94 unneback
    .pl(got_it_pl),
1334
    .clk(clk_src),
1335
    .rst(rst_src));
1336
 
1337 75 unneback
endmodule
1338
`endif
1339 17 unneback
//////////////////////////////////////////////////////////////////////
1340 6 unneback
////                                                              ////
1341 18 unneback
////  Logic functions                                             ////
1342
////                                                              ////
1343
////  Description                                                 ////
1344
////  Logic functions such as multiplexers                        ////
1345
////                                                              ////
1346
////                                                              ////
1347
////  To Do:                                                      ////
1348
////   -                                                          ////
1349
////                                                              ////
1350
////  Author(s):                                                  ////
1351
////      - Michael Unneback, unneback@opencores.org              ////
1352
////        ORSoC AB                                              ////
1353
////                                                              ////
1354
//////////////////////////////////////////////////////////////////////
1355
////                                                              ////
1356
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1357
////                                                              ////
1358
//// This source file may be used and distributed without         ////
1359
//// restriction provided that this copyright statement is not    ////
1360
//// removed from the file and that any derivative work contains  ////
1361
//// the original copyright notice and the associated disclaimer. ////
1362
////                                                              ////
1363
//// This source file is free software; you can redistribute it   ////
1364
//// and/or modify it under the terms of the GNU Lesser General   ////
1365
//// Public License as published by the Free Software Foundation; ////
1366
//// either version 2.1 of the License, or (at your option) any   ////
1367
//// later version.                                               ////
1368
////                                                              ////
1369
//// This source is distributed in the hope that it will be       ////
1370
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1371
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1372
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1373
//// details.                                                     ////
1374
////                                                              ////
1375
//// You should have received a copy of the GNU Lesser General    ////
1376
//// Public License along with this source; if not, download it   ////
1377
//// from http://www.opencores.org/lgpl.shtml                     ////
1378
////                                                              ////
1379
//////////////////////////////////////////////////////////////////////
1380 40 unneback
`ifdef MUX_ANDOR
1381
`define MODULE mux_andor
1382
module `BASE`MODULE ( a, sel, dout);
1383
`undef MODULE
1384 36 unneback
 
1385
parameter width = 32;
1386
parameter nr_of_ports = 4;
1387
 
1388
input [nr_of_ports*width-1:0] a;
1389
input [nr_of_ports-1:0] sel;
1390
output reg [width-1:0] dout;
1391
 
1392 38 unneback
integer i,j;
1393
 
1394 36 unneback
always @ (a, sel)
1395
begin
1396
    dout = a[width-1:0] & {width{sel[0]}};
1397 42 unneback
    for (i=1;i<nr_of_ports;i=i+1)
1398
        for (j=0;j<width;j=j+1)
1399
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
1400 36 unneback
end
1401
 
1402
endmodule
1403 40 unneback
`endif
1404 36 unneback
 
1405 40 unneback
`ifdef MUX2_ANDOR
1406
`define MODULE mux2_andor
1407
module `BASE`MODULE ( a1, a0, sel, dout);
1408
`undef MODULE
1409 18 unneback
 
1410 34 unneback
parameter width = 32;
1411 35 unneback
localparam nr_of_ports = 2;
1412 34 unneback
input [width-1:0] a1, a0;
1413
input [nr_of_ports-1:0] sel;
1414
output [width-1:0] dout;
1415
 
1416 40 unneback
`define MODULE mux_andor
1417
`BASE`MODULE
1418 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1419 36 unneback
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
1420 40 unneback
`undef MODULE
1421
 
1422 34 unneback
endmodule
1423 40 unneback
`endif
1424 34 unneback
 
1425 40 unneback
`ifdef MUX3_ANDOR
1426
`define MODULE mux3_andor
1427
module `BASE`MODULE ( a2, a1, a0, sel, dout);
1428
`undef MODULE
1429 34 unneback
 
1430
parameter width = 32;
1431 35 unneback
localparam nr_of_ports = 3;
1432 34 unneback
input [width-1:0] a2, a1, a0;
1433
input [nr_of_ports-1:0] sel;
1434
output [width-1:0] dout;
1435
 
1436 40 unneback
`define MODULE mux_andor
1437
`BASE`MODULE
1438 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1439 36 unneback
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
1440 40 unneback
`undef MODULE
1441 34 unneback
endmodule
1442 40 unneback
`endif
1443 34 unneback
 
1444 40 unneback
`ifdef MUX4_ANDOR
1445
`define MODULE mux4_andor
1446
module `BASE`MODULE ( a3, a2, a1, a0, sel, dout);
1447
`undef MODULE
1448 18 unneback
 
1449
parameter width = 32;
1450 35 unneback
localparam nr_of_ports = 4;
1451 18 unneback
input [width-1:0] a3, a2, a1, a0;
1452
input [nr_of_ports-1:0] sel;
1453 22 unneback
output [width-1:0] dout;
1454 18 unneback
 
1455 40 unneback
`define MODULE mux_andor
1456
`BASE`MODULE
1457 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1458 36 unneback
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
1459 40 unneback
`undef MODULE
1460 18 unneback
 
1461
endmodule
1462 40 unneback
`endif
1463 18 unneback
 
1464 40 unneback
`ifdef MUX5_ANDOR
1465
`define MODULE mux5_andor
1466
module `BASE`MODULE ( a4, a3, a2, a1, a0, sel, dout);
1467
`undef MODULE
1468 18 unneback
 
1469
parameter width = 32;
1470 35 unneback
localparam nr_of_ports = 5;
1471 18 unneback
input [width-1:0] a4, a3, a2, a1, a0;
1472
input [nr_of_ports-1:0] sel;
1473 22 unneback
output [width-1:0] dout;
1474 18 unneback
 
1475 40 unneback
`define MODULE mux_andor
1476
`BASE`MODULE
1477 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1478 36 unneback
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1479 40 unneback
`undef MODULE
1480 18 unneback
 
1481
endmodule
1482 40 unneback
`endif
1483 18 unneback
 
1484 40 unneback
`ifdef MUX6_ANDOR
1485
`define MODULE mux6_andor
1486
module `BASE`MODULE ( a5, a4, a3, a2, a1, a0, sel, dout);
1487
`undef MODULE
1488 18 unneback
 
1489
parameter width = 32;
1490 35 unneback
localparam nr_of_ports = 6;
1491 18 unneback
input [width-1:0] a5, a4, a3, a2, a1, a0;
1492
input [nr_of_ports-1:0] sel;
1493 22 unneback
output [width-1:0] dout;
1494 18 unneback
 
1495 40 unneback
`define MODULE mux_andor
1496
`BASE`MODULE
1497 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1498 36 unneback
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1499 40 unneback
`undef MODULE
1500 18 unneback
 
1501
endmodule
1502 40 unneback
`endif
1503 43 unneback
 
1504
`ifdef PARITY
1505
 
1506
`define MODULE parity_generate
1507
module `BASE`MODULE (data, parity);
1508
`undef MODULE
1509
parameter word_size = 32;
1510
parameter chunk_size = 8;
1511
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1512
input [word_size-1:0] data;
1513
output reg [word_size/chunk_size-1:0] parity;
1514
integer i,j;
1515
always @ (data)
1516
for (i=0;i<word_size/chunk_size;i=i+1) begin
1517
    parity[i] = parity_type;
1518
    for (j=0;j<chunk_size;j=j+1) begin
1519 46 unneback
        parity[i] = data[i*chunk_size+j] ^ parity[i];
1520 43 unneback
    end
1521
end
1522
endmodule
1523
 
1524
`define MODULE parity_check
1525
module `BASE`MODULE( data, parity, parity_error);
1526
`undef MODULE
1527
parameter word_size = 32;
1528
parameter chunk_size = 8;
1529
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1530
input [word_size-1:0] data;
1531
input [word_size/chunk_size-1:0] parity;
1532
output parity_error;
1533 44 unneback
reg [word_size/chunk_size-1:0] error_flag;
1534 43 unneback
integer i,j;
1535
always @ (data or parity)
1536
for (i=0;i<word_size/chunk_size;i=i+1) begin
1537
    error_flag[i] = parity[i] ^ parity_type;
1538
    for (j=0;j<chunk_size;j=j+1) begin
1539 46 unneback
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
1540 43 unneback
    end
1541
end
1542
assign parity_error = |error_flag;
1543
endmodule
1544
 
1545 44 unneback
`endif//////////////////////////////////////////////////////////////////////
1546
////                                                              ////
1547
////  IO functions                                                ////
1548
////                                                              ////
1549
////  Description                                                 ////
1550
////  IO functions such as IOB flip-flops                         ////
1551
////                                                              ////
1552
////                                                              ////
1553
////  To Do:                                                      ////
1554
////   -                                                          ////
1555
////                                                              ////
1556
////  Author(s):                                                  ////
1557
////      - Michael Unneback, unneback@opencores.org              ////
1558
////        ORSoC AB                                              ////
1559
////                                                              ////
1560 18 unneback
//////////////////////////////////////////////////////////////////////
1561
////                                                              ////
1562 44 unneback
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1563
////                                                              ////
1564
//// This source file may be used and distributed without         ////
1565
//// restriction provided that this copyright statement is not    ////
1566
//// removed from the file and that any derivative work contains  ////
1567
//// the original copyright notice and the associated disclaimer. ////
1568
////                                                              ////
1569
//// This source file is free software; you can redistribute it   ////
1570
//// and/or modify it under the terms of the GNU Lesser General   ////
1571
//// Public License as published by the Free Software Foundation; ////
1572
//// either version 2.1 of the License, or (at your option) any   ////
1573
//// later version.                                               ////
1574
////                                                              ////
1575
//// This source is distributed in the hope that it will be       ////
1576
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1577
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1578
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1579
//// details.                                                     ////
1580
////                                                              ////
1581
//// You should have received a copy of the GNU Lesser General    ////
1582
//// Public License along with this source; if not, download it   ////
1583
//// from http://www.opencores.org/lgpl.shtml                     ////
1584
////                                                              ////
1585
//////////////////////////////////////////////////////////////////////
1586 45 unneback
`timescale 1ns/1ns
1587 44 unneback
`ifdef O_DFF
1588
`define MODULE o_dff
1589
module `BASE`MODULE (d_i, o_pad, clk, rst);
1590
`undef MODULE
1591
parameter width = 1;
1592 45 unneback
parameter reset_value = {width{1'b0}};
1593
input  [width-1:0]  d_i;
1594 44 unneback
output [width-1:0] o_pad;
1595
input clk, rst;
1596
wire [width-1:0] d_i_int `SYN_KEEP;
1597 45 unneback
reg  [width-1:0] o_pad_int;
1598 44 unneback
assign d_i_int = d_i;
1599
genvar i;
1600 45 unneback
generate
1601 44 unneback
for (i=0;i<width;i=i+1) begin
1602
    always @ (posedge clk or posedge rst)
1603
    if (rst)
1604 45 unneback
        o_pad_int[i] <= reset_value[i];
1605 44 unneback
    else
1606 45 unneback
        o_pad_int[i] <= d_i_int[i];
1607
    assign #1 o_pad[i] = o_pad_int[i];
1608 44 unneback
end
1609
endgenerate
1610
endmodule
1611
`endif
1612
 
1613 45 unneback
`timescale 1ns/1ns
1614 44 unneback
`ifdef IO_DFF_OE
1615
`define MODULE io_dff_oe
1616
module `BASE`MODULE ( d_i, d_o, oe, io_pad, clk, rst);
1617
`undef MODULE
1618
parameter width = 1;
1619
input  [width-1:0] d_o;
1620
output reg [width-1:0] d_i;
1621
input oe;
1622
inout [width-1:0] io_pad;
1623
input clk, rst;
1624
wire [width-1:0] oe_d `SYN_KEEP;
1625
reg [width-1:0] oe_q;
1626
reg [width-1:0] d_o_q;
1627
assign oe_d = {width{oe}};
1628
genvar i;
1629
generate
1630
for (i=0;i<width;i=i+1) begin
1631
    always @ (posedge clk or posedge rst)
1632
    if (rst)
1633
        oe_q[i] <= 1'b0;
1634
    else
1635
        oe_q[i] <= oe_d[i];
1636
    always @ (posedge clk or posedge rst)
1637
    if (rst)
1638
        d_o_q[i] <= 1'b0;
1639
    else
1640
        d_o_q[i] <= d_o[i];
1641
    always @ (posedge clk or posedge rst)
1642
    if (rst)
1643
        d_i[i] <= 1'b0;
1644
    else
1645
        d_i[i] <= io_pad[i];
1646 45 unneback
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
1647 44 unneback
end
1648
endgenerate
1649
endmodule
1650
`endif
1651
`ifdef CNT_BIN
1652
//////////////////////////////////////////////////////////////////////
1653
////                                                              ////
1654 6 unneback
////  Versatile counter                                           ////
1655
////                                                              ////
1656
////  Description                                                 ////
1657
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1658
////  counter                                                     ////
1659
////                                                              ////
1660
////  To Do:                                                      ////
1661
////   - add LFSR with more taps                                  ////
1662
////                                                              ////
1663
////  Author(s):                                                  ////
1664
////      - Michael Unneback, unneback@opencores.org              ////
1665
////        ORSoC AB                                              ////
1666
////                                                              ////
1667
//////////////////////////////////////////////////////////////////////
1668
////                                                              ////
1669
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1670
////                                                              ////
1671
//// This source file may be used and distributed without         ////
1672
//// restriction provided that this copyright statement is not    ////
1673
//// removed from the file and that any derivative work contains  ////
1674
//// the original copyright notice and the associated disclaimer. ////
1675
////                                                              ////
1676
//// This source file is free software; you can redistribute it   ////
1677
//// and/or modify it under the terms of the GNU Lesser General   ////
1678
//// Public License as published by the Free Software Foundation; ////
1679
//// either version 2.1 of the License, or (at your option) any   ////
1680
//// later version.                                               ////
1681
////                                                              ////
1682
//// This source is distributed in the hope that it will be       ////
1683
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1684
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1685
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1686
//// details.                                                     ////
1687
////                                                              ////
1688
//// You should have received a copy of the GNU Lesser General    ////
1689
//// Public License along with this source; if not, download it   ////
1690
//// from http://www.opencores.org/lgpl.shtml                     ////
1691
////                                                              ////
1692
//////////////////////////////////////////////////////////////////////
1693
 
1694
// binary counter
1695 22 unneback
 
1696 40 unneback
`define MODULE cnt_bin
1697
module `BASE`MODULE (
1698
`undef MODULE
1699
 q, rst, clk);
1700
 
1701 22 unneback
   parameter length = 4;
1702
   output [length:1] q;
1703
   input rst;
1704
   input clk;
1705
 
1706
   parameter clear_value = 0;
1707
   parameter set_value = 1;
1708
   parameter wrap_value = 0;
1709
   parameter level1_value = 15;
1710
 
1711
   reg  [length:1] qi;
1712
   wire [length:1] q_next;
1713
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1714
 
1715
   always @ (posedge clk or posedge rst)
1716
     if (rst)
1717
       qi <= {length{1'b0}};
1718
     else
1719
       qi <= q_next;
1720
 
1721
   assign q = qi;
1722
 
1723
endmodule
1724 40 unneback
`endif
1725
`ifdef CNT_BIN_CLEAR
1726 22 unneback
//////////////////////////////////////////////////////////////////////
1727
////                                                              ////
1728
////  Versatile counter                                           ////
1729
////                                                              ////
1730
////  Description                                                 ////
1731
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1732
////  counter                                                     ////
1733
////                                                              ////
1734
////  To Do:                                                      ////
1735
////   - add LFSR with more taps                                  ////
1736
////                                                              ////
1737
////  Author(s):                                                  ////
1738
////      - Michael Unneback, unneback@opencores.org              ////
1739
////        ORSoC AB                                              ////
1740
////                                                              ////
1741
//////////////////////////////////////////////////////////////////////
1742
////                                                              ////
1743
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1744
////                                                              ////
1745
//// This source file may be used and distributed without         ////
1746
//// restriction provided that this copyright statement is not    ////
1747
//// removed from the file and that any derivative work contains  ////
1748
//// the original copyright notice and the associated disclaimer. ////
1749
////                                                              ////
1750
//// This source file is free software; you can redistribute it   ////
1751
//// and/or modify it under the terms of the GNU Lesser General   ////
1752
//// Public License as published by the Free Software Foundation; ////
1753
//// either version 2.1 of the License, or (at your option) any   ////
1754
//// later version.                                               ////
1755
////                                                              ////
1756
//// This source is distributed in the hope that it will be       ////
1757
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1758
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1759
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1760
//// details.                                                     ////
1761
////                                                              ////
1762
//// You should have received a copy of the GNU Lesser General    ////
1763
//// Public License along with this source; if not, download it   ////
1764
//// from http://www.opencores.org/lgpl.shtml                     ////
1765
////                                                              ////
1766
//////////////////////////////////////////////////////////////////////
1767
 
1768
// binary counter
1769
 
1770 40 unneback
`define MODULE cnt_bin_clear
1771
module `BASE`MODULE (
1772
`undef MODULE
1773
 clear, q, rst, clk);
1774
 
1775 22 unneback
   parameter length = 4;
1776
   input clear;
1777
   output [length:1] q;
1778
   input rst;
1779
   input clk;
1780
 
1781
   parameter clear_value = 0;
1782
   parameter set_value = 1;
1783
   parameter wrap_value = 0;
1784
   parameter level1_value = 15;
1785
 
1786
   reg  [length:1] qi;
1787
   wire [length:1] q_next;
1788
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1789
 
1790
   always @ (posedge clk or posedge rst)
1791
     if (rst)
1792
       qi <= {length{1'b0}};
1793
     else
1794
       qi <= q_next;
1795
 
1796
   assign q = qi;
1797
 
1798
endmodule
1799 40 unneback
`endif
1800
`ifdef CNT_BIN_CE
1801 22 unneback
//////////////////////////////////////////////////////////////////////
1802
////                                                              ////
1803
////  Versatile counter                                           ////
1804
////                                                              ////
1805
////  Description                                                 ////
1806
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1807
////  counter                                                     ////
1808
////                                                              ////
1809
////  To Do:                                                      ////
1810
////   - add LFSR with more taps                                  ////
1811
////                                                              ////
1812
////  Author(s):                                                  ////
1813
////      - Michael Unneback, unneback@opencores.org              ////
1814
////        ORSoC AB                                              ////
1815
////                                                              ////
1816
//////////////////////////////////////////////////////////////////////
1817
////                                                              ////
1818
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1819
////                                                              ////
1820
//// This source file may be used and distributed without         ////
1821
//// restriction provided that this copyright statement is not    ////
1822
//// removed from the file and that any derivative work contains  ////
1823
//// the original copyright notice and the associated disclaimer. ////
1824
////                                                              ////
1825
//// This source file is free software; you can redistribute it   ////
1826
//// and/or modify it under the terms of the GNU Lesser General   ////
1827
//// Public License as published by the Free Software Foundation; ////
1828
//// either version 2.1 of the License, or (at your option) any   ////
1829
//// later version.                                               ////
1830
////                                                              ////
1831
//// This source is distributed in the hope that it will be       ////
1832
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1833
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1834
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1835
//// details.                                                     ////
1836
////                                                              ////
1837
//// You should have received a copy of the GNU Lesser General    ////
1838
//// Public License along with this source; if not, download it   ////
1839
//// from http://www.opencores.org/lgpl.shtml                     ////
1840
////                                                              ////
1841
//////////////////////////////////////////////////////////////////////
1842
 
1843
// binary counter
1844 6 unneback
 
1845 40 unneback
`define MODULE cnt_bin_ce
1846
module `BASE`MODULE (
1847
`undef MODULE
1848
 cke, q, rst, clk);
1849
 
1850 6 unneback
   parameter length = 4;
1851
   input cke;
1852
   output [length:1] q;
1853
   input rst;
1854
   input clk;
1855
 
1856
   parameter clear_value = 0;
1857
   parameter set_value = 1;
1858
   parameter wrap_value = 0;
1859
   parameter level1_value = 15;
1860
 
1861
   reg  [length:1] qi;
1862
   wire [length:1] q_next;
1863
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1864
 
1865
   always @ (posedge clk or posedge rst)
1866
     if (rst)
1867
       qi <= {length{1'b0}};
1868
     else
1869
     if (cke)
1870
       qi <= q_next;
1871
 
1872
   assign q = qi;
1873
 
1874
endmodule
1875 40 unneback
`endif
1876
`ifdef CNT_BIN_CE_CLEAR
1877 6 unneback
//////////////////////////////////////////////////////////////////////
1878
////                                                              ////
1879
////  Versatile counter                                           ////
1880
////                                                              ////
1881
////  Description                                                 ////
1882
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1883
////  counter                                                     ////
1884
////                                                              ////
1885
////  To Do:                                                      ////
1886
////   - add LFSR with more taps                                  ////
1887
////                                                              ////
1888
////  Author(s):                                                  ////
1889
////      - Michael Unneback, unneback@opencores.org              ////
1890
////        ORSoC AB                                              ////
1891
////                                                              ////
1892
//////////////////////////////////////////////////////////////////////
1893
////                                                              ////
1894
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1895
////                                                              ////
1896
//// This source file may be used and distributed without         ////
1897
//// restriction provided that this copyright statement is not    ////
1898
//// removed from the file and that any derivative work contains  ////
1899
//// the original copyright notice and the associated disclaimer. ////
1900
////                                                              ////
1901
//// This source file is free software; you can redistribute it   ////
1902
//// and/or modify it under the terms of the GNU Lesser General   ////
1903
//// Public License as published by the Free Software Foundation; ////
1904
//// either version 2.1 of the License, or (at your option) any   ////
1905
//// later version.                                               ////
1906
////                                                              ////
1907
//// This source is distributed in the hope that it will be       ////
1908
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1909
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1910
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1911
//// details.                                                     ////
1912
////                                                              ////
1913
//// You should have received a copy of the GNU Lesser General    ////
1914
//// Public License along with this source; if not, download it   ////
1915
//// from http://www.opencores.org/lgpl.shtml                     ////
1916
////                                                              ////
1917
//////////////////////////////////////////////////////////////////////
1918
 
1919
// binary counter
1920
 
1921 40 unneback
`define MODULE cnt_bin_ce_clear
1922
module `BASE`MODULE (
1923
`undef MODULE
1924
 clear, cke, q, rst, clk);
1925
 
1926 6 unneback
   parameter length = 4;
1927
   input clear;
1928
   input cke;
1929
   output [length:1] q;
1930
   input rst;
1931
   input clk;
1932
 
1933
   parameter clear_value = 0;
1934
   parameter set_value = 1;
1935
   parameter wrap_value = 0;
1936
   parameter level1_value = 15;
1937
 
1938
   reg  [length:1] qi;
1939
   wire [length:1] q_next;
1940
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1941
 
1942
   always @ (posedge clk or posedge rst)
1943
     if (rst)
1944
       qi <= {length{1'b0}};
1945
     else
1946
     if (cke)
1947
       qi <= q_next;
1948
 
1949
   assign q = qi;
1950
 
1951
endmodule
1952 40 unneback
`endif
1953
`ifdef CNT_BIN_CE_CLEAR_L1_L2
1954 6 unneback
//////////////////////////////////////////////////////////////////////
1955
////                                                              ////
1956
////  Versatile counter                                           ////
1957
////                                                              ////
1958
////  Description                                                 ////
1959
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1960
////  counter                                                     ////
1961
////                                                              ////
1962
////  To Do:                                                      ////
1963
////   - add LFSR with more taps                                  ////
1964
////                                                              ////
1965
////  Author(s):                                                  ////
1966
////      - Michael Unneback, unneback@opencores.org              ////
1967
////        ORSoC AB                                              ////
1968
////                                                              ////
1969
//////////////////////////////////////////////////////////////////////
1970
////                                                              ////
1971
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1972
////                                                              ////
1973
//// This source file may be used and distributed without         ////
1974
//// restriction provided that this copyright statement is not    ////
1975
//// removed from the file and that any derivative work contains  ////
1976
//// the original copyright notice and the associated disclaimer. ////
1977
////                                                              ////
1978
//// This source file is free software; you can redistribute it   ////
1979
//// and/or modify it under the terms of the GNU Lesser General   ////
1980
//// Public License as published by the Free Software Foundation; ////
1981
//// either version 2.1 of the License, or (at your option) any   ////
1982
//// later version.                                               ////
1983
////                                                              ////
1984
//// This source is distributed in the hope that it will be       ////
1985
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1986
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1987
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1988
//// details.                                                     ////
1989
////                                                              ////
1990
//// You should have received a copy of the GNU Lesser General    ////
1991
//// Public License along with this source; if not, download it   ////
1992
//// from http://www.opencores.org/lgpl.shtml                     ////
1993
////                                                              ////
1994
//////////////////////////////////////////////////////////////////////
1995
 
1996
// binary counter
1997 29 unneback
 
1998 40 unneback
`define MODULE cnt_bin_ce_clear_l1_l2
1999
module `BASE`MODULE (
2000
`undef MODULE
2001
 clear, cke, q, level1, level2, rst, clk);
2002
 
2003 29 unneback
   parameter length = 4;
2004
   input clear;
2005
   input cke;
2006
   output [length:1] q;
2007
   output reg level1;
2008
   output reg level2;
2009
   input rst;
2010
   input clk;
2011
 
2012
   parameter clear_value = 0;
2013
   parameter set_value = 1;
2014 30 unneback
   parameter wrap_value = 15;
2015
   parameter level1_value = 8;
2016
   parameter level2_value = 15;
2017 29 unneback
 
2018
   wire rew;
2019 30 unneback
   assign rew = 1'b0;
2020 29 unneback
   reg  [length:1] qi;
2021
   wire [length:1] q_next;
2022
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
2023
 
2024
   always @ (posedge clk or posedge rst)
2025
     if (rst)
2026
       qi <= {length{1'b0}};
2027
     else
2028
     if (cke)
2029
       qi <= q_next;
2030
 
2031
   assign q = qi;
2032
 
2033
 
2034
    always @ (posedge clk or posedge rst)
2035
    if (rst)
2036
        level1 <= 1'b0;
2037
    else
2038
    if (cke)
2039
    if (clear)
2040
        level1 <= 1'b0;
2041
    else if (q_next == level1_value)
2042
        level1 <= 1'b1;
2043
    else if (qi == level1_value & rew)
2044
        level1 <= 1'b0;
2045
 
2046
    always @ (posedge clk or posedge rst)
2047
    if (rst)
2048
        level2 <= 1'b0;
2049
    else
2050
    if (cke)
2051
    if (clear)
2052
        level2 <= 1'b0;
2053
    else if (q_next == level2_value)
2054
        level2 <= 1'b1;
2055
    else if (qi == level2_value & rew)
2056
        level2 <= 1'b0;
2057
endmodule
2058 40 unneback
`endif
2059
`ifdef CNT_BIN_CE_CLEAR_SET_REW
2060 29 unneback
//////////////////////////////////////////////////////////////////////
2061
////                                                              ////
2062
////  Versatile counter                                           ////
2063
////                                                              ////
2064
////  Description                                                 ////
2065
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2066
////  counter                                                     ////
2067
////                                                              ////
2068
////  To Do:                                                      ////
2069
////   - add LFSR with more taps                                  ////
2070
////                                                              ////
2071
////  Author(s):                                                  ////
2072
////      - Michael Unneback, unneback@opencores.org              ////
2073
////        ORSoC AB                                              ////
2074
////                                                              ////
2075
//////////////////////////////////////////////////////////////////////
2076
////                                                              ////
2077
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2078
////                                                              ////
2079
//// This source file may be used and distributed without         ////
2080
//// restriction provided that this copyright statement is not    ////
2081
//// removed from the file and that any derivative work contains  ////
2082
//// the original copyright notice and the associated disclaimer. ////
2083
////                                                              ////
2084
//// This source file is free software; you can redistribute it   ////
2085
//// and/or modify it under the terms of the GNU Lesser General   ////
2086
//// Public License as published by the Free Software Foundation; ////
2087
//// either version 2.1 of the License, or (at your option) any   ////
2088
//// later version.                                               ////
2089
////                                                              ////
2090
//// This source is distributed in the hope that it will be       ////
2091
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2092
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2093
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2094
//// details.                                                     ////
2095
////                                                              ////
2096
//// You should have received a copy of the GNU Lesser General    ////
2097
//// Public License along with this source; if not, download it   ////
2098
//// from http://www.opencores.org/lgpl.shtml                     ////
2099
////                                                              ////
2100
//////////////////////////////////////////////////////////////////////
2101
 
2102
// binary counter
2103 6 unneback
 
2104 40 unneback
`define MODULE cnt_bin_ce_clear_set_rew
2105
module `BASE`MODULE (
2106
`undef MODULE
2107
 clear, set, cke, rew, q, rst, clk);
2108
 
2109 6 unneback
   parameter length = 4;
2110
   input clear;
2111
   input set;
2112
   input cke;
2113
   input rew;
2114
   output [length:1] q;
2115
   input rst;
2116
   input clk;
2117
 
2118
   parameter clear_value = 0;
2119
   parameter set_value = 1;
2120
   parameter wrap_value = 0;
2121
   parameter level1_value = 15;
2122
 
2123
   reg  [length:1] qi;
2124
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2125
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
2126
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
2127
   assign q_next = rew ? q_next_rew : q_next_fw;
2128
 
2129
   always @ (posedge clk or posedge rst)
2130
     if (rst)
2131
       qi <= {length{1'b0}};
2132
     else
2133
     if (cke)
2134
       qi <= q_next;
2135
 
2136
   assign q = qi;
2137
 
2138
endmodule
2139 40 unneback
`endif
2140
`ifdef CNT_BIN_CE_REW_L1
2141 6 unneback
//////////////////////////////////////////////////////////////////////
2142
////                                                              ////
2143
////  Versatile counter                                           ////
2144
////                                                              ////
2145
////  Description                                                 ////
2146
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2147
////  counter                                                     ////
2148
////                                                              ////
2149
////  To Do:                                                      ////
2150
////   - add LFSR with more taps                                  ////
2151
////                                                              ////
2152
////  Author(s):                                                  ////
2153
////      - Michael Unneback, unneback@opencores.org              ////
2154
////        ORSoC AB                                              ////
2155
////                                                              ////
2156
//////////////////////////////////////////////////////////////////////
2157
////                                                              ////
2158
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2159
////                                                              ////
2160
//// This source file may be used and distributed without         ////
2161
//// restriction provided that this copyright statement is not    ////
2162
//// removed from the file and that any derivative work contains  ////
2163
//// the original copyright notice and the associated disclaimer. ////
2164
////                                                              ////
2165
//// This source file is free software; you can redistribute it   ////
2166
//// and/or modify it under the terms of the GNU Lesser General   ////
2167
//// Public License as published by the Free Software Foundation; ////
2168
//// either version 2.1 of the License, or (at your option) any   ////
2169
//// later version.                                               ////
2170
////                                                              ////
2171
//// This source is distributed in the hope that it will be       ////
2172
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2173
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2174
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2175
//// details.                                                     ////
2176
////                                                              ////
2177
//// You should have received a copy of the GNU Lesser General    ////
2178
//// Public License along with this source; if not, download it   ////
2179
//// from http://www.opencores.org/lgpl.shtml                     ////
2180
////                                                              ////
2181
//////////////////////////////////////////////////////////////////////
2182
 
2183
// binary counter
2184
 
2185 40 unneback
`define MODULE cnt_bin_ce_rew_l1
2186
module `BASE`MODULE (
2187
`undef MODULE
2188
 cke, rew, level1, rst, clk);
2189
 
2190 6 unneback
   parameter length = 4;
2191
   input cke;
2192
   input rew;
2193
   output reg level1;
2194
   input rst;
2195
   input clk;
2196
 
2197
   parameter clear_value = 0;
2198
   parameter set_value = 1;
2199
   parameter wrap_value = 1;
2200
   parameter level1_value = 15;
2201
 
2202 29 unneback
   wire clear;
2203 30 unneback
   assign clear = 1'b0;
2204 6 unneback
   reg  [length:1] qi;
2205
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2206
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2207
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2208
   assign q_next = rew ? q_next_rew : q_next_fw;
2209
 
2210
   always @ (posedge clk or posedge rst)
2211
     if (rst)
2212
       qi <= {length{1'b0}};
2213
     else
2214
     if (cke)
2215
       qi <= q_next;
2216
 
2217
 
2218
 
2219
    always @ (posedge clk or posedge rst)
2220
    if (rst)
2221
        level1 <= 1'b0;
2222
    else
2223
    if (cke)
2224 29 unneback
    if (clear)
2225
        level1 <= 1'b0;
2226
    else if (q_next == level1_value)
2227 6 unneback
        level1 <= 1'b1;
2228
    else if (qi == level1_value & rew)
2229
        level1 <= 1'b0;
2230
endmodule
2231 40 unneback
`endif
2232
`ifdef CNT_BIN_CE_REW_ZQ_L1
2233 6 unneback
//////////////////////////////////////////////////////////////////////
2234
////                                                              ////
2235
////  Versatile counter                                           ////
2236
////                                                              ////
2237
////  Description                                                 ////
2238
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2239
////  counter                                                     ////
2240
////                                                              ////
2241
////  To Do:                                                      ////
2242
////   - add LFSR with more taps                                  ////
2243
////                                                              ////
2244
////  Author(s):                                                  ////
2245
////      - Michael Unneback, unneback@opencores.org              ////
2246
////        ORSoC AB                                              ////
2247
////                                                              ////
2248
//////////////////////////////////////////////////////////////////////
2249
////                                                              ////
2250
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2251
////                                                              ////
2252
//// This source file may be used and distributed without         ////
2253
//// restriction provided that this copyright statement is not    ////
2254
//// removed from the file and that any derivative work contains  ////
2255
//// the original copyright notice and the associated disclaimer. ////
2256
////                                                              ////
2257
//// This source file is free software; you can redistribute it   ////
2258
//// and/or modify it under the terms of the GNU Lesser General   ////
2259
//// Public License as published by the Free Software Foundation; ////
2260
//// either version 2.1 of the License, or (at your option) any   ////
2261
//// later version.                                               ////
2262
////                                                              ////
2263
//// This source is distributed in the hope that it will be       ////
2264
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2265
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2266
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2267
//// details.                                                     ////
2268
////                                                              ////
2269
//// You should have received a copy of the GNU Lesser General    ////
2270
//// Public License along with this source; if not, download it   ////
2271
//// from http://www.opencores.org/lgpl.shtml                     ////
2272
////                                                              ////
2273
//////////////////////////////////////////////////////////////////////
2274
 
2275 25 unneback
// binary counter
2276
 
2277 40 unneback
`define MODULE cnt_bin_ce_rew_zq_l1
2278
module `BASE`MODULE (
2279
`undef MODULE
2280
 cke, rew, zq, level1, rst, clk);
2281
 
2282 25 unneback
   parameter length = 4;
2283
   input cke;
2284
   input rew;
2285
   output reg zq;
2286
   output reg level1;
2287
   input rst;
2288
   input clk;
2289
 
2290
   parameter clear_value = 0;
2291
   parameter set_value = 1;
2292
   parameter wrap_value = 1;
2293
   parameter level1_value = 15;
2294
 
2295 29 unneback
   wire clear;
2296 30 unneback
   assign clear = 1'b0;
2297 25 unneback
   reg  [length:1] qi;
2298
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2299
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2300
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2301
   assign q_next = rew ? q_next_rew : q_next_fw;
2302
 
2303
   always @ (posedge clk or posedge rst)
2304
     if (rst)
2305
       qi <= {length{1'b0}};
2306
     else
2307
     if (cke)
2308
       qi <= q_next;
2309
 
2310
 
2311
 
2312
   always @ (posedge clk or posedge rst)
2313
     if (rst)
2314
       zq <= 1'b1;
2315
     else
2316
     if (cke)
2317
       zq <= q_next == {length{1'b0}};
2318
 
2319
    always @ (posedge clk or posedge rst)
2320
    if (rst)
2321
        level1 <= 1'b0;
2322
    else
2323
    if (cke)
2324 29 unneback
    if (clear)
2325
        level1 <= 1'b0;
2326
    else if (q_next == level1_value)
2327 25 unneback
        level1 <= 1'b1;
2328
    else if (qi == level1_value & rew)
2329
        level1 <= 1'b0;
2330
endmodule
2331 40 unneback
`endif
2332
`ifdef CNT_BIN_CE_REW_Q_ZQ_L1
2333 25 unneback
//////////////////////////////////////////////////////////////////////
2334
////                                                              ////
2335
////  Versatile counter                                           ////
2336
////                                                              ////
2337
////  Description                                                 ////
2338
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2339
////  counter                                                     ////
2340
////                                                              ////
2341
////  To Do:                                                      ////
2342
////   - add LFSR with more taps                                  ////
2343
////                                                              ////
2344
////  Author(s):                                                  ////
2345
////      - Michael Unneback, unneback@opencores.org              ////
2346
////        ORSoC AB                                              ////
2347
////                                                              ////
2348
//////////////////////////////////////////////////////////////////////
2349
////                                                              ////
2350
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2351
////                                                              ////
2352
//// This source file may be used and distributed without         ////
2353
//// restriction provided that this copyright statement is not    ////
2354
//// removed from the file and that any derivative work contains  ////
2355
//// the original copyright notice and the associated disclaimer. ////
2356
////                                                              ////
2357
//// This source file is free software; you can redistribute it   ////
2358
//// and/or modify it under the terms of the GNU Lesser General   ////
2359
//// Public License as published by the Free Software Foundation; ////
2360
//// either version 2.1 of the License, or (at your option) any   ////
2361
//// later version.                                               ////
2362
////                                                              ////
2363
//// This source is distributed in the hope that it will be       ////
2364
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2365
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2366
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2367
//// details.                                                     ////
2368
////                                                              ////
2369
//// You should have received a copy of the GNU Lesser General    ////
2370
//// Public License along with this source; if not, download it   ////
2371
//// from http://www.opencores.org/lgpl.shtml                     ////
2372
////                                                              ////
2373
//////////////////////////////////////////////////////////////////////
2374
 
2375
// binary counter
2376
 
2377 40 unneback
`define MODULE cnt_bin_ce_rew_q_zq_l1
2378
module `BASE`MODULE (
2379
`undef MODULE
2380
 cke, rew, q, zq, level1, rst, clk);
2381
 
2382 25 unneback
   parameter length = 4;
2383
   input cke;
2384
   input rew;
2385
   output [length:1] q;
2386
   output reg zq;
2387
   output reg level1;
2388
   input rst;
2389
   input clk;
2390
 
2391
   parameter clear_value = 0;
2392
   parameter set_value = 1;
2393
   parameter wrap_value = 1;
2394
   parameter level1_value = 15;
2395
 
2396 29 unneback
   wire clear;
2397 30 unneback
   assign clear = 1'b0;
2398 25 unneback
   reg  [length:1] qi;
2399
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2400
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2401
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2402
   assign q_next = rew ? q_next_rew : q_next_fw;
2403
 
2404
   always @ (posedge clk or posedge rst)
2405
     if (rst)
2406
       qi <= {length{1'b0}};
2407
     else
2408
     if (cke)
2409
       qi <= q_next;
2410
 
2411
   assign q = qi;
2412
 
2413
 
2414
   always @ (posedge clk or posedge rst)
2415
     if (rst)
2416
       zq <= 1'b1;
2417
     else
2418
     if (cke)
2419
       zq <= q_next == {length{1'b0}};
2420
 
2421
    always @ (posedge clk or posedge rst)
2422
    if (rst)
2423
        level1 <= 1'b0;
2424
    else
2425
    if (cke)
2426 29 unneback
    if (clear)
2427
        level1 <= 1'b0;
2428
    else if (q_next == level1_value)
2429 25 unneback
        level1 <= 1'b1;
2430
    else if (qi == level1_value & rew)
2431
        level1 <= 1'b0;
2432
endmodule
2433 40 unneback
`endif
2434
`ifdef CNT_LFSR_ZQ
2435 25 unneback
//////////////////////////////////////////////////////////////////////
2436
////                                                              ////
2437
////  Versatile counter                                           ////
2438
////                                                              ////
2439
////  Description                                                 ////
2440
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2441
////  counter                                                     ////
2442
////                                                              ////
2443
////  To Do:                                                      ////
2444
////   - add LFSR with more taps                                  ////
2445
////                                                              ////
2446
////  Author(s):                                                  ////
2447
////      - Michael Unneback, unneback@opencores.org              ////
2448
////        ORSoC AB                                              ////
2449
////                                                              ////
2450
//////////////////////////////////////////////////////////////////////
2451
////                                                              ////
2452
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2453
////                                                              ////
2454
//// This source file may be used and distributed without         ////
2455
//// restriction provided that this copyright statement is not    ////
2456
//// removed from the file and that any derivative work contains  ////
2457
//// the original copyright notice and the associated disclaimer. ////
2458
////                                                              ////
2459
//// This source file is free software; you can redistribute it   ////
2460
//// and/or modify it under the terms of the GNU Lesser General   ////
2461
//// Public License as published by the Free Software Foundation; ////
2462
//// either version 2.1 of the License, or (at your option) any   ////
2463
//// later version.                                               ////
2464
////                                                              ////
2465
//// This source is distributed in the hope that it will be       ////
2466
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2467
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2468
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2469
//// details.                                                     ////
2470
////                                                              ////
2471
//// You should have received a copy of the GNU Lesser General    ////
2472
//// Public License along with this source; if not, download it   ////
2473
//// from http://www.opencores.org/lgpl.shtml                     ////
2474
////                                                              ////
2475
//////////////////////////////////////////////////////////////////////
2476
 
2477 6 unneback
// LFSR counter
2478
 
2479 40 unneback
`define MODULE cnt_lfsr_zq
2480
module `BASE`MODULE (
2481
`undef MODULE
2482
 zq, rst, clk);
2483
 
2484 6 unneback
   parameter length = 4;
2485
   output reg zq;
2486
   input rst;
2487
   input clk;
2488
 
2489
   parameter clear_value = 0;
2490
   parameter set_value = 1;
2491
   parameter wrap_value = 8;
2492
   parameter level1_value = 15;
2493
 
2494
   reg  [length:1] qi;
2495
   reg lfsr_fb;
2496
   wire [length:1] q_next;
2497
   reg [32:1] polynom;
2498
   integer i;
2499
 
2500
   always @ (qi)
2501
   begin
2502
        case (length)
2503
         2: polynom = 32'b11;                               // 0x3
2504
         3: polynom = 32'b110;                              // 0x6
2505
         4: polynom = 32'b1100;                             // 0xC
2506
         5: polynom = 32'b10100;                            // 0x14
2507
         6: polynom = 32'b110000;                           // 0x30
2508
         7: polynom = 32'b1100000;                          // 0x60
2509
         8: polynom = 32'b10111000;                         // 0xb8
2510
         9: polynom = 32'b100010000;                        // 0x110
2511
        10: polynom = 32'b1001000000;                       // 0x240
2512
        11: polynom = 32'b10100000000;                      // 0x500
2513
        12: polynom = 32'b100000101001;                     // 0x829
2514
        13: polynom = 32'b1000000001100;                    // 0x100C
2515
        14: polynom = 32'b10000000010101;                   // 0x2015
2516
        15: polynom = 32'b110000000000000;                  // 0x6000
2517
        16: polynom = 32'b1101000000001000;                 // 0xD008
2518
        17: polynom = 32'b10010000000000000;                // 0x12000
2519
        18: polynom = 32'b100000010000000000;               // 0x20400
2520
        19: polynom = 32'b1000000000000100011;              // 0x40023
2521 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2522 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2523
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2524
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2525
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2526
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2527
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2528
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2529
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2530
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2531
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2532
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2533
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2534
        default: polynom = 32'b0;
2535
        endcase
2536
        lfsr_fb = qi[length];
2537
        for (i=length-1; i>=1; i=i-1) begin
2538
            if (polynom[i])
2539
                lfsr_fb = lfsr_fb  ~^ qi[i];
2540
        end
2541
    end
2542
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2543
 
2544
   always @ (posedge clk or posedge rst)
2545
     if (rst)
2546
       qi <= {length{1'b0}};
2547
     else
2548
       qi <= q_next;
2549
 
2550
 
2551
 
2552
   always @ (posedge clk or posedge rst)
2553
     if (rst)
2554
       zq <= 1'b1;
2555
     else
2556
       zq <= q_next == {length{1'b0}};
2557
endmodule
2558 40 unneback
`endif
2559 75 unneback
`ifdef CNT_LFSR_CE
2560
//////////////////////////////////////////////////////////////////////
2561
////                                                              ////
2562
////  Versatile counter                                           ////
2563
////                                                              ////
2564
////  Description                                                 ////
2565
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2566
////  counter                                                     ////
2567
////                                                              ////
2568
////  To Do:                                                      ////
2569
////   - add LFSR with more taps                                  ////
2570
////                                                              ////
2571
////  Author(s):                                                  ////
2572
////      - Michael Unneback, unneback@opencores.org              ////
2573
////        ORSoC AB                                              ////
2574
////                                                              ////
2575
//////////////////////////////////////////////////////////////////////
2576
////                                                              ////
2577
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2578
////                                                              ////
2579
//// This source file may be used and distributed without         ////
2580
//// restriction provided that this copyright statement is not    ////
2581
//// removed from the file and that any derivative work contains  ////
2582
//// the original copyright notice and the associated disclaimer. ////
2583
////                                                              ////
2584
//// This source file is free software; you can redistribute it   ////
2585
//// and/or modify it under the terms of the GNU Lesser General   ////
2586
//// Public License as published by the Free Software Foundation; ////
2587
//// either version 2.1 of the License, or (at your option) any   ////
2588
//// later version.                                               ////
2589
////                                                              ////
2590
//// This source is distributed in the hope that it will be       ////
2591
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2592
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2593
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2594
//// details.                                                     ////
2595
////                                                              ////
2596
//// You should have received a copy of the GNU Lesser General    ////
2597
//// Public License along with this source; if not, download it   ////
2598
//// from http://www.opencores.org/lgpl.shtml                     ////
2599
////                                                              ////
2600
//////////////////////////////////////////////////////////////////////
2601
 
2602
// LFSR counter
2603
 
2604
`define MODULE cnt_lfsr_ce
2605
module `BASE`MODULE (
2606
`undef MODULE
2607
 cke, zq, rst, clk);
2608
 
2609
   parameter length = 4;
2610
   input cke;
2611
   output reg zq;
2612
   input rst;
2613
   input clk;
2614
 
2615
   parameter clear_value = 0;
2616
   parameter set_value = 1;
2617
   parameter wrap_value = 0;
2618
   parameter level1_value = 15;
2619
 
2620
   reg  [length:1] qi;
2621
   reg lfsr_fb;
2622
   wire [length:1] q_next;
2623
   reg [32:1] polynom;
2624
   integer i;
2625
 
2626
   always @ (qi)
2627
   begin
2628
        case (length)
2629
         2: polynom = 32'b11;                               // 0x3
2630
         3: polynom = 32'b110;                              // 0x6
2631
         4: polynom = 32'b1100;                             // 0xC
2632
         5: polynom = 32'b10100;                            // 0x14
2633
         6: polynom = 32'b110000;                           // 0x30
2634
         7: polynom = 32'b1100000;                          // 0x60
2635
         8: polynom = 32'b10111000;                         // 0xb8
2636
         9: polynom = 32'b100010000;                        // 0x110
2637
        10: polynom = 32'b1001000000;                       // 0x240
2638
        11: polynom = 32'b10100000000;                      // 0x500
2639
        12: polynom = 32'b100000101001;                     // 0x829
2640
        13: polynom = 32'b1000000001100;                    // 0x100C
2641
        14: polynom = 32'b10000000010101;                   // 0x2015
2642
        15: polynom = 32'b110000000000000;                  // 0x6000
2643
        16: polynom = 32'b1101000000001000;                 // 0xD008
2644
        17: polynom = 32'b10010000000000000;                // 0x12000
2645
        18: polynom = 32'b100000010000000000;               // 0x20400
2646
        19: polynom = 32'b1000000000000100011;              // 0x40023
2647
        20: polynom = 32'b10010000000000000000;             // 0x90000
2648
        21: polynom = 32'b101000000000000000000;            // 0x140000
2649
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2650
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2651
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2652
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2653
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2654
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2655
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2656
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2657
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2658
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2659
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2660
        default: polynom = 32'b0;
2661
        endcase
2662
        lfsr_fb = qi[length];
2663
        for (i=length-1; i>=1; i=i-1) begin
2664
            if (polynom[i])
2665
                lfsr_fb = lfsr_fb  ~^ qi[i];
2666
        end
2667
    end
2668
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2669
 
2670
   always @ (posedge clk or posedge rst)
2671
     if (rst)
2672
       qi <= {length{1'b0}};
2673
     else
2674
     if (cke)
2675
       qi <= q_next;
2676
 
2677
 
2678
 
2679
   always @ (posedge clk or posedge rst)
2680
     if (rst)
2681
       zq <= 1'b1;
2682
     else
2683
     if (cke)
2684
       zq <= q_next == {length{1'b0}};
2685
endmodule
2686
`endif
2687 40 unneback
`ifdef CNT_LFSR_CE_ZQ
2688 6 unneback
//////////////////////////////////////////////////////////////////////
2689
////                                                              ////
2690
////  Versatile counter                                           ////
2691
////                                                              ////
2692
////  Description                                                 ////
2693
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2694
////  counter                                                     ////
2695
////                                                              ////
2696
////  To Do:                                                      ////
2697
////   - add LFSR with more taps                                  ////
2698
////                                                              ////
2699
////  Author(s):                                                  ////
2700
////      - Michael Unneback, unneback@opencores.org              ////
2701
////        ORSoC AB                                              ////
2702
////                                                              ////
2703
//////////////////////////////////////////////////////////////////////
2704
////                                                              ////
2705
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2706
////                                                              ////
2707
//// This source file may be used and distributed without         ////
2708
//// restriction provided that this copyright statement is not    ////
2709
//// removed from the file and that any derivative work contains  ////
2710
//// the original copyright notice and the associated disclaimer. ////
2711
////                                                              ////
2712
//// This source file is free software; you can redistribute it   ////
2713
//// and/or modify it under the terms of the GNU Lesser General   ////
2714
//// Public License as published by the Free Software Foundation; ////
2715
//// either version 2.1 of the License, or (at your option) any   ////
2716
//// later version.                                               ////
2717
////                                                              ////
2718
//// This source is distributed in the hope that it will be       ////
2719
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2720
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2721
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2722
//// details.                                                     ////
2723
////                                                              ////
2724
//// You should have received a copy of the GNU Lesser General    ////
2725
//// Public License along with this source; if not, download it   ////
2726
//// from http://www.opencores.org/lgpl.shtml                     ////
2727
////                                                              ////
2728
//////////////////////////////////////////////////////////////////////
2729
 
2730
// LFSR counter
2731
 
2732 40 unneback
`define MODULE cnt_lfsr_ce_zq
2733
module `BASE`MODULE (
2734
`undef MODULE
2735
 cke, zq, rst, clk);
2736
 
2737 6 unneback
   parameter length = 4;
2738
   input cke;
2739
   output reg zq;
2740
   input rst;
2741
   input clk;
2742
 
2743
   parameter clear_value = 0;
2744
   parameter set_value = 1;
2745
   parameter wrap_value = 8;
2746
   parameter level1_value = 15;
2747
 
2748
   reg  [length:1] qi;
2749
   reg lfsr_fb;
2750
   wire [length:1] q_next;
2751
   reg [32:1] polynom;
2752
   integer i;
2753
 
2754
   always @ (qi)
2755
   begin
2756
        case (length)
2757
         2: polynom = 32'b11;                               // 0x3
2758
         3: polynom = 32'b110;                              // 0x6
2759
         4: polynom = 32'b1100;                             // 0xC
2760
         5: polynom = 32'b10100;                            // 0x14
2761
         6: polynom = 32'b110000;                           // 0x30
2762
         7: polynom = 32'b1100000;                          // 0x60
2763
         8: polynom = 32'b10111000;                         // 0xb8
2764
         9: polynom = 32'b100010000;                        // 0x110
2765
        10: polynom = 32'b1001000000;                       // 0x240
2766
        11: polynom = 32'b10100000000;                      // 0x500
2767
        12: polynom = 32'b100000101001;                     // 0x829
2768
        13: polynom = 32'b1000000001100;                    // 0x100C
2769
        14: polynom = 32'b10000000010101;                   // 0x2015
2770
        15: polynom = 32'b110000000000000;                  // 0x6000
2771
        16: polynom = 32'b1101000000001000;                 // 0xD008
2772
        17: polynom = 32'b10010000000000000;                // 0x12000
2773
        18: polynom = 32'b100000010000000000;               // 0x20400
2774
        19: polynom = 32'b1000000000000100011;              // 0x40023
2775 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2776 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2777
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2778
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2779
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2780
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2781
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2782
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2783
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2784
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2785
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2786
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2787
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2788
        default: polynom = 32'b0;
2789
        endcase
2790
        lfsr_fb = qi[length];
2791
        for (i=length-1; i>=1; i=i-1) begin
2792
            if (polynom[i])
2793
                lfsr_fb = lfsr_fb  ~^ qi[i];
2794
        end
2795
    end
2796
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2797
 
2798
   always @ (posedge clk or posedge rst)
2799
     if (rst)
2800
       qi <= {length{1'b0}};
2801
     else
2802
     if (cke)
2803
       qi <= q_next;
2804
 
2805
 
2806
 
2807
   always @ (posedge clk or posedge rst)
2808
     if (rst)
2809
       zq <= 1'b1;
2810
     else
2811
     if (cke)
2812
       zq <= q_next == {length{1'b0}};
2813
endmodule
2814 40 unneback
`endif
2815
`ifdef CNT_LFSR_CE_Q
2816 6 unneback
//////////////////////////////////////////////////////////////////////
2817
////                                                              ////
2818
////  Versatile counter                                           ////
2819
////                                                              ////
2820
////  Description                                                 ////
2821
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2822
////  counter                                                     ////
2823
////                                                              ////
2824
////  To Do:                                                      ////
2825
////   - add LFSR with more taps                                  ////
2826
////                                                              ////
2827
////  Author(s):                                                  ////
2828
////      - Michael Unneback, unneback@opencores.org              ////
2829
////        ORSoC AB                                              ////
2830
////                                                              ////
2831
//////////////////////////////////////////////////////////////////////
2832
////                                                              ////
2833
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2834
////                                                              ////
2835
//// This source file may be used and distributed without         ////
2836
//// restriction provided that this copyright statement is not    ////
2837
//// removed from the file and that any derivative work contains  ////
2838
//// the original copyright notice and the associated disclaimer. ////
2839
////                                                              ////
2840
//// This source file is free software; you can redistribute it   ////
2841
//// and/or modify it under the terms of the GNU Lesser General   ////
2842
//// Public License as published by the Free Software Foundation; ////
2843
//// either version 2.1 of the License, or (at your option) any   ////
2844
//// later version.                                               ////
2845
////                                                              ////
2846
//// This source is distributed in the hope that it will be       ////
2847
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2848
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2849
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2850
//// details.                                                     ////
2851
////                                                              ////
2852
//// You should have received a copy of the GNU Lesser General    ////
2853
//// Public License along with this source; if not, download it   ////
2854
//// from http://www.opencores.org/lgpl.shtml                     ////
2855
////                                                              ////
2856
//////////////////////////////////////////////////////////////////////
2857 22 unneback
 
2858
// LFSR counter
2859 27 unneback
 
2860 40 unneback
`define MODULE cnt_lfsr_ce_q
2861
module `BASE`MODULE (
2862
`undef MODULE
2863
 cke, q, rst, clk);
2864
 
2865 27 unneback
   parameter length = 4;
2866
   input cke;
2867
   output [length:1] q;
2868
   input rst;
2869
   input clk;
2870
 
2871
   parameter clear_value = 0;
2872
   parameter set_value = 1;
2873
   parameter wrap_value = 8;
2874
   parameter level1_value = 15;
2875
 
2876
   reg  [length:1] qi;
2877
   reg lfsr_fb;
2878
   wire [length:1] q_next;
2879
   reg [32:1] polynom;
2880
   integer i;
2881
 
2882
   always @ (qi)
2883
   begin
2884
        case (length)
2885
         2: polynom = 32'b11;                               // 0x3
2886
         3: polynom = 32'b110;                              // 0x6
2887
         4: polynom = 32'b1100;                             // 0xC
2888
         5: polynom = 32'b10100;                            // 0x14
2889
         6: polynom = 32'b110000;                           // 0x30
2890
         7: polynom = 32'b1100000;                          // 0x60
2891
         8: polynom = 32'b10111000;                         // 0xb8
2892
         9: polynom = 32'b100010000;                        // 0x110
2893
        10: polynom = 32'b1001000000;                       // 0x240
2894
        11: polynom = 32'b10100000000;                      // 0x500
2895
        12: polynom = 32'b100000101001;                     // 0x829
2896
        13: polynom = 32'b1000000001100;                    // 0x100C
2897
        14: polynom = 32'b10000000010101;                   // 0x2015
2898
        15: polynom = 32'b110000000000000;                  // 0x6000
2899
        16: polynom = 32'b1101000000001000;                 // 0xD008
2900
        17: polynom = 32'b10010000000000000;                // 0x12000
2901
        18: polynom = 32'b100000010000000000;               // 0x20400
2902
        19: polynom = 32'b1000000000000100011;              // 0x40023
2903 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2904 27 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2905
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2906
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2907
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2908
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2909
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2910
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2911
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2912
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2913
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2914
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2915
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2916
        default: polynom = 32'b0;
2917
        endcase
2918
        lfsr_fb = qi[length];
2919
        for (i=length-1; i>=1; i=i-1) begin
2920
            if (polynom[i])
2921
                lfsr_fb = lfsr_fb  ~^ qi[i];
2922
        end
2923
    end
2924
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2925
 
2926
   always @ (posedge clk or posedge rst)
2927
     if (rst)
2928
       qi <= {length{1'b0}};
2929
     else
2930
     if (cke)
2931
       qi <= q_next;
2932
 
2933
   assign q = qi;
2934
 
2935
endmodule
2936 40 unneback
`endif
2937
`ifdef CNT_LFSR_CE_CLEAR_Q
2938 27 unneback
//////////////////////////////////////////////////////////////////////
2939
////                                                              ////
2940
////  Versatile counter                                           ////
2941
////                                                              ////
2942
////  Description                                                 ////
2943
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2944
////  counter                                                     ////
2945
////                                                              ////
2946
////  To Do:                                                      ////
2947
////   - add LFSR with more taps                                  ////
2948
////                                                              ////
2949
////  Author(s):                                                  ////
2950
////      - Michael Unneback, unneback@opencores.org              ////
2951
////        ORSoC AB                                              ////
2952
////                                                              ////
2953
//////////////////////////////////////////////////////////////////////
2954
////                                                              ////
2955
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2956
////                                                              ////
2957
//// This source file may be used and distributed without         ////
2958
//// restriction provided that this copyright statement is not    ////
2959
//// removed from the file and that any derivative work contains  ////
2960
//// the original copyright notice and the associated disclaimer. ////
2961
////                                                              ////
2962
//// This source file is free software; you can redistribute it   ////
2963
//// and/or modify it under the terms of the GNU Lesser General   ////
2964
//// Public License as published by the Free Software Foundation; ////
2965
//// either version 2.1 of the License, or (at your option) any   ////
2966
//// later version.                                               ////
2967
////                                                              ////
2968
//// This source is distributed in the hope that it will be       ////
2969
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2970
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2971
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2972
//// details.                                                     ////
2973
////                                                              ////
2974
//// You should have received a copy of the GNU Lesser General    ////
2975
//// Public License along with this source; if not, download it   ////
2976
//// from http://www.opencores.org/lgpl.shtml                     ////
2977
////                                                              ////
2978
//////////////////////////////////////////////////////////////////////
2979
 
2980
// LFSR counter
2981
 
2982 40 unneback
`define MODULE cnt_lfsr_ce_clear_q
2983
module `BASE`MODULE (
2984
`undef MODULE
2985
 clear, cke, q, rst, clk);
2986
 
2987 27 unneback
   parameter length = 4;
2988
   input clear;
2989
   input cke;
2990
   output [length:1] q;
2991
   input rst;
2992
   input clk;
2993
 
2994
   parameter clear_value = 0;
2995
   parameter set_value = 1;
2996
   parameter wrap_value = 8;
2997
   parameter level1_value = 15;
2998
 
2999
   reg  [length:1] qi;
3000
   reg lfsr_fb;
3001
   wire [length:1] q_next;
3002
   reg [32:1] polynom;
3003
   integer i;
3004
 
3005
   always @ (qi)
3006
   begin
3007
        case (length)
3008
         2: polynom = 32'b11;                               // 0x3
3009
         3: polynom = 32'b110;                              // 0x6
3010
         4: polynom = 32'b1100;                             // 0xC
3011
         5: polynom = 32'b10100;                            // 0x14
3012
         6: polynom = 32'b110000;                           // 0x30
3013
         7: polynom = 32'b1100000;                          // 0x60
3014
         8: polynom = 32'b10111000;                         // 0xb8
3015
         9: polynom = 32'b100010000;                        // 0x110
3016
        10: polynom = 32'b1001000000;                       // 0x240
3017
        11: polynom = 32'b10100000000;                      // 0x500
3018
        12: polynom = 32'b100000101001;                     // 0x829
3019
        13: polynom = 32'b1000000001100;                    // 0x100C
3020
        14: polynom = 32'b10000000010101;                   // 0x2015
3021
        15: polynom = 32'b110000000000000;                  // 0x6000
3022
        16: polynom = 32'b1101000000001000;                 // 0xD008
3023
        17: polynom = 32'b10010000000000000;                // 0x12000
3024
        18: polynom = 32'b100000010000000000;               // 0x20400
3025
        19: polynom = 32'b1000000000000100011;              // 0x40023
3026 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
3027 27 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
3028
        22: polynom = 32'b1100000000000000000000;           // 0x300000
3029
        23: polynom = 32'b10000100000000000000000;          // 0x420000
3030
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
3031
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
3032
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
3033
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
3034
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
3035
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
3036
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
3037
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
3038
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
3039
        default: polynom = 32'b0;
3040
        endcase
3041
        lfsr_fb = qi[length];
3042
        for (i=length-1; i>=1; i=i-1) begin
3043
            if (polynom[i])
3044
                lfsr_fb = lfsr_fb  ~^ qi[i];
3045
        end
3046
    end
3047
   assign q_next =  clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
3048
 
3049
   always @ (posedge clk or posedge rst)
3050
     if (rst)
3051
       qi <= {length{1'b0}};
3052
     else
3053
     if (cke)
3054
       qi <= q_next;
3055
 
3056
   assign q = qi;
3057
 
3058
endmodule
3059 40 unneback
`endif
3060
`ifdef CNT_LFSR_CE_Q_ZQ
3061 27 unneback
//////////////////////////////////////////////////////////////////////
3062
////                                                              ////
3063
////  Versatile counter                                           ////
3064
////                                                              ////
3065
////  Description                                                 ////
3066
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3067
////  counter                                                     ////
3068
////                                                              ////
3069
////  To Do:                                                      ////
3070
////   - add LFSR with more taps                                  ////
3071
////                                                              ////
3072
////  Author(s):                                                  ////
3073
////      - Michael Unneback, unneback@opencores.org              ////
3074
////        ORSoC AB                                              ////
3075
////                                                              ////
3076
//////////////////////////////////////////////////////////////////////
3077
////                                                              ////
3078
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3079
////                                                              ////
3080
//// This source file may be used and distributed without         ////
3081
//// restriction provided that this copyright statement is not    ////
3082
//// removed from the file and that any derivative work contains  ////
3083
//// the original copyright notice and the associated disclaimer. ////
3084
////                                                              ////
3085
//// This source file is free software; you can redistribute it   ////
3086
//// and/or modify it under the terms of the GNU Lesser General   ////
3087
//// Public License as published by the Free Software Foundation; ////
3088
//// either version 2.1 of the License, or (at your option) any   ////
3089
//// later version.                                               ////
3090
////                                                              ////
3091
//// This source is distributed in the hope that it will be       ////
3092
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3093
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3094
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3095
//// details.                                                     ////
3096
////                                                              ////
3097
//// You should have received a copy of the GNU Lesser General    ////
3098
//// Public License along with this source; if not, download it   ////
3099
//// from http://www.opencores.org/lgpl.shtml                     ////
3100
////                                                              ////
3101
//////////////////////////////////////////////////////////////////////
3102
 
3103
// LFSR counter
3104 22 unneback
 
3105 40 unneback
`define MODULE cnt_lfsr_ce_q_zq
3106
module `BASE`MODULE (
3107
`undef MODULE
3108
 cke, q, zq, rst, clk);
3109
 
3110 22 unneback
   parameter length = 4;
3111
   input cke;
3112
   output [length:1] q;
3113
   output reg zq;
3114
   input rst;
3115
   input clk;
3116
 
3117
   parameter clear_value = 0;
3118
   parameter set_value = 1;
3119
   parameter wrap_value = 8;
3120
   parameter level1_value = 15;
3121
 
3122
   reg  [length:1] qi;
3123
   reg lfsr_fb;
3124
   wire [length:1] q_next;
3125
   reg [32:1] polynom;
3126
   integer i;
3127
 
3128
   always @ (qi)
3129
   begin
3130
        case (length)
3131
         2: polynom = 32'b11;                               // 0x3
3132
         3: polynom = 32'b110;                              // 0x6
3133
         4: polynom = 32'b1100;                             // 0xC
3134
         5: polynom = 32'b10100;                            // 0x14
3135
         6: polynom = 32'b110000;                           // 0x30
3136
         7: polynom = 32'b1100000;                          // 0x60
3137
         8: polynom = 32'b10111000;                         // 0xb8
3138
         9: polynom = 32'b100010000;                        // 0x110
3139
        10: polynom = 32'b1001000000;                       // 0x240
3140
        11: polynom = 32'b10100000000;                      // 0x500
3141
        12: polynom = 32'b100000101001;                     // 0x829
3142
        13: polynom = 32'b1000000001100;                    // 0x100C
3143
        14: polynom = 32'b10000000010101;                   // 0x2015
3144
        15: polynom = 32'b110000000000000;                  // 0x6000
3145
        16: polynom = 32'b1101000000001000;                 // 0xD008
3146
        17: polynom = 32'b10010000000000000;                // 0x12000
3147
        18: polynom = 32'b100000010000000000;               // 0x20400
3148
        19: polynom = 32'b1000000000000100011;              // 0x40023
3149 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
3150 22 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
3151
        22: polynom = 32'b1100000000000000000000;           // 0x300000
3152
        23: polynom = 32'b10000100000000000000000;          // 0x420000
3153
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
3154
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
3155
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
3156
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
3157
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
3158
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
3159
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
3160
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
3161
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
3162
        default: polynom = 32'b0;
3163
        endcase
3164
        lfsr_fb = qi[length];
3165
        for (i=length-1; i>=1; i=i-1) begin
3166
            if (polynom[i])
3167
                lfsr_fb = lfsr_fb  ~^ qi[i];
3168
        end
3169
    end
3170
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
3171
 
3172
   always @ (posedge clk or posedge rst)
3173
     if (rst)
3174
       qi <= {length{1'b0}};
3175
     else
3176
     if (cke)
3177
       qi <= q_next;
3178
 
3179
   assign q = qi;
3180
 
3181
 
3182
   always @ (posedge clk or posedge rst)
3183
     if (rst)
3184
       zq <= 1'b1;
3185
     else
3186
     if (cke)
3187
       zq <= q_next == {length{1'b0}};
3188
endmodule
3189 40 unneback
`endif
3190
`ifdef CNT_LFSR_CE_REW_L1
3191 22 unneback
//////////////////////////////////////////////////////////////////////
3192
////                                                              ////
3193
////  Versatile counter                                           ////
3194
////                                                              ////
3195
////  Description                                                 ////
3196
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3197
////  counter                                                     ////
3198
////                                                              ////
3199
////  To Do:                                                      ////
3200
////   - add LFSR with more taps                                  ////
3201
////                                                              ////
3202
////  Author(s):                                                  ////
3203
////      - Michael Unneback, unneback@opencores.org              ////
3204
////        ORSoC AB                                              ////
3205
////                                                              ////
3206
//////////////////////////////////////////////////////////////////////
3207
////                                                              ////
3208
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3209
////                                                              ////
3210
//// This source file may be used and distributed without         ////
3211
//// restriction provided that this copyright statement is not    ////
3212
//// removed from the file and that any derivative work contains  ////
3213
//// the original copyright notice and the associated disclaimer. ////
3214
////                                                              ////
3215
//// This source file is free software; you can redistribute it   ////
3216
//// and/or modify it under the terms of the GNU Lesser General   ////
3217
//// Public License as published by the Free Software Foundation; ////
3218
//// either version 2.1 of the License, or (at your option) any   ////
3219
//// later version.                                               ////
3220
////                                                              ////
3221
//// This source is distributed in the hope that it will be       ////
3222
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3223
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3224
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3225
//// details.                                                     ////
3226
////                                                              ////
3227
//// You should have received a copy of the GNU Lesser General    ////
3228
//// Public License along with this source; if not, download it   ////
3229
//// from http://www.opencores.org/lgpl.shtml                     ////
3230
////                                                              ////
3231
//////////////////////////////////////////////////////////////////////
3232 6 unneback
 
3233
// LFSR counter
3234
 
3235 40 unneback
`define MODULE cnt_lfsr_ce_rew_l1
3236
module `BASE`MODULE (
3237
`undef MODULE
3238
 cke, rew, level1, rst, clk);
3239
 
3240 6 unneback
   parameter length = 4;
3241
   input cke;
3242
   input rew;
3243
   output reg level1;
3244
   input rst;
3245
   input clk;
3246
 
3247
   parameter clear_value = 0;
3248
   parameter set_value = 1;
3249
   parameter wrap_value = 8;
3250
   parameter level1_value = 15;
3251
 
3252 29 unneback
   wire clear;
3253 30 unneback
   assign clear = 1'b0;
3254 6 unneback
   reg  [length:1] qi;
3255
   reg lfsr_fb, lfsr_fb_rew;
3256
   wire  [length:1] q_next, q_next_fw, q_next_rew;
3257
   reg [32:1] polynom_rew;
3258
   integer j;
3259
   reg [32:1] polynom;
3260
   integer i;
3261
 
3262
   always @ (qi)
3263
   begin
3264
        case (length)
3265
         2: polynom = 32'b11;                               // 0x3
3266
         3: polynom = 32'b110;                              // 0x6
3267
         4: polynom = 32'b1100;                             // 0xC
3268
         5: polynom = 32'b10100;                            // 0x14
3269
         6: polynom = 32'b110000;                           // 0x30
3270
         7: polynom = 32'b1100000;                          // 0x60
3271
         8: polynom = 32'b10111000;                         // 0xb8
3272
         9: polynom = 32'b100010000;                        // 0x110
3273
        10: polynom = 32'b1001000000;                       // 0x240
3274
        11: polynom = 32'b10100000000;                      // 0x500
3275
        12: polynom = 32'b100000101001;                     // 0x829
3276
        13: polynom = 32'b1000000001100;                    // 0x100C
3277
        14: polynom = 32'b10000000010101;                   // 0x2015
3278
        15: polynom = 32'b110000000000000;                  // 0x6000
3279
        16: polynom = 32'b1101000000001000;                 // 0xD008
3280
        17: polynom = 32'b10010000000000000;                // 0x12000
3281
        18: polynom = 32'b100000010000000000;               // 0x20400
3282
        19: polynom = 32'b1000000000000100011;              // 0x40023
3283 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
3284 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
3285
        22: polynom = 32'b1100000000000000000000;           // 0x300000
3286
        23: polynom = 32'b10000100000000000000000;          // 0x420000
3287
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
3288
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
3289
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
3290
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
3291
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
3292
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
3293
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
3294
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
3295
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
3296
        default: polynom = 32'b0;
3297
        endcase
3298
        lfsr_fb = qi[length];
3299
        for (i=length-1; i>=1; i=i-1) begin
3300
            if (polynom[i])
3301
                lfsr_fb = lfsr_fb  ~^ qi[i];
3302
        end
3303
    end
3304
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
3305
   always @ (qi)
3306
   begin
3307
        case (length)
3308
         2: polynom_rew = 32'b11;
3309
         3: polynom_rew = 32'b110;
3310
         4: polynom_rew = 32'b1100;
3311
         5: polynom_rew = 32'b10100;
3312
         6: polynom_rew = 32'b110000;
3313
         7: polynom_rew = 32'b1100000;
3314
         8: polynom_rew = 32'b10111000;
3315
         9: polynom_rew = 32'b100010000;
3316
        10: polynom_rew = 32'b1001000000;
3317
        11: polynom_rew = 32'b10100000000;
3318
        12: polynom_rew = 32'b100000101001;
3319
        13: polynom_rew = 32'b1000000001100;
3320
        14: polynom_rew = 32'b10000000010101;
3321
        15: polynom_rew = 32'b110000000000000;
3322
        16: polynom_rew = 32'b1101000000001000;
3323
        17: polynom_rew = 32'b10010000000000000;
3324
        18: polynom_rew = 32'b100000010000000000;
3325
        19: polynom_rew = 32'b1000000000000100011;
3326
        20: polynom_rew = 32'b10000010000000000000;
3327
        21: polynom_rew = 32'b101000000000000000000;
3328
        22: polynom_rew = 32'b1100000000000000000000;
3329
        23: polynom_rew = 32'b10000100000000000000000;
3330
        24: polynom_rew = 32'b111000010000000000000000;
3331
        25: polynom_rew = 32'b1001000000000000000000000;
3332
        26: polynom_rew = 32'b10000000000000000000100011;
3333
        27: polynom_rew = 32'b100000000000000000000010011;
3334
        28: polynom_rew = 32'b1100100000000000000000000000;
3335
        29: polynom_rew = 32'b10100000000000000000000000000;
3336
        30: polynom_rew = 32'b100000000000000000000000101001;
3337
        31: polynom_rew = 32'b1001000000000000000000000000000;
3338
        32: polynom_rew = 32'b10000000001000000000000000000011;
3339
        default: polynom_rew = 32'b0;
3340
        endcase
3341
        // rotate left
3342
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
3343
        lfsr_fb_rew = qi[length];
3344
        for (i=length-1; i>=1; i=i-1) begin
3345
            if (polynom_rew[i])
3346
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
3347
        end
3348
    end
3349
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
3350
   assign q_next = rew ? q_next_rew : q_next_fw;
3351
 
3352
   always @ (posedge clk or posedge rst)
3353
     if (rst)
3354
       qi <= {length{1'b0}};
3355
     else
3356
     if (cke)
3357
       qi <= q_next;
3358
 
3359
 
3360
 
3361
    always @ (posedge clk or posedge rst)
3362
    if (rst)
3363
        level1 <= 1'b0;
3364
    else
3365
    if (cke)
3366 29 unneback
    if (clear)
3367
        level1 <= 1'b0;
3368
    else if (q_next == level1_value)
3369 6 unneback
        level1 <= 1'b1;
3370
    else if (qi == level1_value & rew)
3371
        level1 <= 1'b0;
3372
endmodule
3373 40 unneback
`endif
3374
`ifdef CNT_GRAY
3375 6 unneback
//////////////////////////////////////////////////////////////////////
3376
////                                                              ////
3377
////  Versatile counter                                           ////
3378
////                                                              ////
3379
////  Description                                                 ////
3380
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3381
////  counter                                                     ////
3382
////                                                              ////
3383
////  To Do:                                                      ////
3384
////   - add LFSR with more taps                                  ////
3385
////                                                              ////
3386
////  Author(s):                                                  ////
3387
////      - Michael Unneback, unneback@opencores.org              ////
3388
////        ORSoC AB                                              ////
3389
////                                                              ////
3390
//////////////////////////////////////////////////////////////////////
3391
////                                                              ////
3392
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3393
////                                                              ////
3394
//// This source file may be used and distributed without         ////
3395
//// restriction provided that this copyright statement is not    ////
3396
//// removed from the file and that any derivative work contains  ////
3397
//// the original copyright notice and the associated disclaimer. ////
3398
////                                                              ////
3399
//// This source file is free software; you can redistribute it   ////
3400
//// and/or modify it under the terms of the GNU Lesser General   ////
3401
//// Public License as published by the Free Software Foundation; ////
3402
//// either version 2.1 of the License, or (at your option) any   ////
3403
//// later version.                                               ////
3404
////                                                              ////
3405
//// This source is distributed in the hope that it will be       ////
3406
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3407
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3408
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3409
//// details.                                                     ////
3410
////                                                              ////
3411
//// You should have received a copy of the GNU Lesser General    ////
3412
//// Public License along with this source; if not, download it   ////
3413
//// from http://www.opencores.org/lgpl.shtml                     ////
3414
////                                                              ////
3415
//////////////////////////////////////////////////////////////////////
3416
 
3417
// GRAY counter
3418
 
3419 40 unneback
`define MODULE cnt_gray
3420
module `BASE`MODULE (
3421
`undef MODULE
3422
 q, rst, clk);
3423
 
3424 6 unneback
   parameter length = 4;
3425
   output reg [length:1] q;
3426
   input rst;
3427
   input clk;
3428
 
3429
   parameter clear_value = 0;
3430
   parameter set_value = 1;
3431
   parameter wrap_value = 8;
3432
   parameter level1_value = 15;
3433
 
3434
   reg  [length:1] qi;
3435
   wire [length:1] q_next;
3436
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3437
 
3438
   always @ (posedge clk or posedge rst)
3439
     if (rst)
3440
       qi <= {length{1'b0}};
3441
     else
3442
       qi <= q_next;
3443
 
3444
   always @ (posedge clk or posedge rst)
3445
     if (rst)
3446
       q <= {length{1'b0}};
3447
     else
3448
         q <= (q_next>>1) ^ q_next;
3449
 
3450
endmodule
3451 40 unneback
`endif
3452
`ifdef CNT_GRAY_CE
3453 6 unneback
//////////////////////////////////////////////////////////////////////
3454
////                                                              ////
3455
////  Versatile counter                                           ////
3456
////                                                              ////
3457
////  Description                                                 ////
3458
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3459
////  counter                                                     ////
3460
////                                                              ////
3461
////  To Do:                                                      ////
3462
////   - add LFSR with more taps                                  ////
3463
////                                                              ////
3464
////  Author(s):                                                  ////
3465
////      - Michael Unneback, unneback@opencores.org              ////
3466
////        ORSoC AB                                              ////
3467
////                                                              ////
3468
//////////////////////////////////////////////////////////////////////
3469
////                                                              ////
3470
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3471
////                                                              ////
3472
//// This source file may be used and distributed without         ////
3473
//// restriction provided that this copyright statement is not    ////
3474
//// removed from the file and that any derivative work contains  ////
3475
//// the original copyright notice and the associated disclaimer. ////
3476
////                                                              ////
3477
//// This source file is free software; you can redistribute it   ////
3478
//// and/or modify it under the terms of the GNU Lesser General   ////
3479
//// Public License as published by the Free Software Foundation; ////
3480
//// either version 2.1 of the License, or (at your option) any   ////
3481
//// later version.                                               ////
3482
////                                                              ////
3483
//// This source is distributed in the hope that it will be       ////
3484
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3485
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3486
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3487
//// details.                                                     ////
3488
////                                                              ////
3489
//// You should have received a copy of the GNU Lesser General    ////
3490
//// Public License along with this source; if not, download it   ////
3491
//// from http://www.opencores.org/lgpl.shtml                     ////
3492
////                                                              ////
3493
//////////////////////////////////////////////////////////////////////
3494
 
3495
// GRAY counter
3496
 
3497 40 unneback
`define MODULE cnt_gray_ce
3498
module `BASE`MODULE (
3499
`undef MODULE
3500
 cke, q, rst, clk);
3501
 
3502 6 unneback
   parameter length = 4;
3503
   input cke;
3504
   output reg [length:1] q;
3505
   input rst;
3506
   input clk;
3507
 
3508
   parameter clear_value = 0;
3509
   parameter set_value = 1;
3510
   parameter wrap_value = 8;
3511
   parameter level1_value = 15;
3512
 
3513
   reg  [length:1] qi;
3514
   wire [length:1] q_next;
3515
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3516
 
3517
   always @ (posedge clk or posedge rst)
3518
     if (rst)
3519
       qi <= {length{1'b0}};
3520
     else
3521
     if (cke)
3522
       qi <= q_next;
3523
 
3524
   always @ (posedge clk or posedge rst)
3525
     if (rst)
3526
       q <= {length{1'b0}};
3527
     else
3528
       if (cke)
3529
         q <= (q_next>>1) ^ q_next;
3530
 
3531
endmodule
3532 40 unneback
`endif
3533
`ifdef CNT_GRAY_CE_BIN
3534 6 unneback
//////////////////////////////////////////////////////////////////////
3535
////                                                              ////
3536
////  Versatile counter                                           ////
3537
////                                                              ////
3538
////  Description                                                 ////
3539
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3540
////  counter                                                     ////
3541
////                                                              ////
3542
////  To Do:                                                      ////
3543
////   - add LFSR with more taps                                  ////
3544
////                                                              ////
3545
////  Author(s):                                                  ////
3546
////      - Michael Unneback, unneback@opencores.org              ////
3547
////        ORSoC AB                                              ////
3548
////                                                              ////
3549
//////////////////////////////////////////////////////////////////////
3550
////                                                              ////
3551
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3552
////                                                              ////
3553
//// This source file may be used and distributed without         ////
3554
//// restriction provided that this copyright statement is not    ////
3555
//// removed from the file and that any derivative work contains  ////
3556
//// the original copyright notice and the associated disclaimer. ////
3557
////                                                              ////
3558
//// This source file is free software; you can redistribute it   ////
3559
//// and/or modify it under the terms of the GNU Lesser General   ////
3560
//// Public License as published by the Free Software Foundation; ////
3561
//// either version 2.1 of the License, or (at your option) any   ////
3562
//// later version.                                               ////
3563
////                                                              ////
3564
//// This source is distributed in the hope that it will be       ////
3565
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3566
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3567
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3568
//// details.                                                     ////
3569
////                                                              ////
3570
//// You should have received a copy of the GNU Lesser General    ////
3571
//// Public License along with this source; if not, download it   ////
3572
//// from http://www.opencores.org/lgpl.shtml                     ////
3573
////                                                              ////
3574
//////////////////////////////////////////////////////////////////////
3575
 
3576
// GRAY counter
3577
 
3578 40 unneback
`define MODULE cnt_gray_ce_bin
3579
module `BASE`MODULE (
3580
`undef MODULE
3581
 cke, q, q_bin, rst, clk);
3582
 
3583 6 unneback
   parameter length = 4;
3584
   input cke;
3585
   output reg [length:1] q;
3586
   output [length:1] q_bin;
3587
   input rst;
3588
   input clk;
3589
 
3590
   parameter clear_value = 0;
3591
   parameter set_value = 1;
3592
   parameter wrap_value = 8;
3593
   parameter level1_value = 15;
3594
 
3595
   reg  [length:1] qi;
3596
   wire [length:1] q_next;
3597
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3598
 
3599
   always @ (posedge clk or posedge rst)
3600
     if (rst)
3601
       qi <= {length{1'b0}};
3602
     else
3603
     if (cke)
3604
       qi <= q_next;
3605
 
3606
   always @ (posedge clk or posedge rst)
3607
     if (rst)
3608
       q <= {length{1'b0}};
3609
     else
3610
       if (cke)
3611
         q <= (q_next>>1) ^ q_next;
3612
 
3613
   assign q_bin = qi;
3614
 
3615
endmodule
3616 40 unneback
`endif
3617 6 unneback
//////////////////////////////////////////////////////////////////////
3618
////                                                              ////
3619
////  Versatile library, counters                                 ////
3620
////                                                              ////
3621
////  Description                                                 ////
3622
////  counters                                                    ////
3623
////                                                              ////
3624
////                                                              ////
3625
////  To Do:                                                      ////
3626
////   - add more counters                                        ////
3627
////                                                              ////
3628
////  Author(s):                                                  ////
3629
////      - Michael Unneback, unneback@opencores.org              ////
3630
////        ORSoC AB                                              ////
3631
////                                                              ////
3632
//////////////////////////////////////////////////////////////////////
3633
////                                                              ////
3634
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
3635
////                                                              ////
3636
//// This source file may be used and distributed without         ////
3637
//// restriction provided that this copyright statement is not    ////
3638
//// removed from the file and that any derivative work contains  ////
3639
//// the original copyright notice and the associated disclaimer. ////
3640
////                                                              ////
3641
//// This source file is free software; you can redistribute it   ////
3642
//// and/or modify it under the terms of the GNU Lesser General   ////
3643
//// Public License as published by the Free Software Foundation; ////
3644
//// either version 2.1 of the License, or (at your option) any   ////
3645
//// later version.                                               ////
3646
////                                                              ////
3647
//// This source is distributed in the hope that it will be       ////
3648
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3649
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3650
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3651
//// details.                                                     ////
3652
////                                                              ////
3653
//// You should have received a copy of the GNU Lesser General    ////
3654
//// Public License along with this source; if not, download it   ////
3655
//// from http://www.opencores.org/lgpl.shtml                     ////
3656
////                                                              ////
3657
//////////////////////////////////////////////////////////////////////
3658
 
3659 40 unneback
`ifdef CNT_SHREG_WRAP
3660
`define MODULE cnt_shreg_wrap
3661
module `BASE`MODULE ( q, rst, clk);
3662
`undef MODULE
3663 6 unneback
 
3664
   parameter length = 4;
3665
   output reg [0:length-1] q;
3666
   input rst;
3667
   input clk;
3668
 
3669
    always @ (posedge clk or posedge rst)
3670
    if (rst)
3671
        q <= {1'b1,{length-1{1'b0}}};
3672
    else
3673
        q <= {q[length-1],q[0:length-2]};
3674
 
3675
endmodule
3676 40 unneback
`endif
3677 6 unneback
 
3678 40 unneback
`ifdef CNT_SHREG_CE_WRAP
3679
`define MODULE cnt_shreg_ce_wrap
3680
module `BASE`MODULE ( cke, q, rst, clk);
3681
`undef MODULE
3682 6 unneback
 
3683
   parameter length = 4;
3684
   input cke;
3685
   output reg [0:length-1] q;
3686
   input rst;
3687
   input clk;
3688
 
3689
    always @ (posedge clk or posedge rst)
3690
    if (rst)
3691
        q <= {1'b1,{length-1{1'b0}}};
3692
    else
3693
        if (cke)
3694
            q <= {q[length-1],q[0:length-2]};
3695
 
3696
endmodule
3697 40 unneback
`endif
3698 6 unneback
 
3699 40 unneback
`ifdef CNT_SHREG_CE_CLEAR
3700
`define MODULE cnt_shreg_ce_clear
3701
module `BASE`MODULE ( cke, clear, q, rst, clk);
3702
`undef MODULE
3703 6 unneback
 
3704
   parameter length = 4;
3705
   input cke, clear;
3706
   output reg [0:length-1] q;
3707
   input rst;
3708
   input clk;
3709
 
3710
    always @ (posedge clk or posedge rst)
3711
    if (rst)
3712
        q <= {1'b1,{length-1{1'b0}}};
3713
    else
3714
        if (cke)
3715
            if (clear)
3716
                q <= {1'b1,{length-1{1'b0}}};
3717
            else
3718
                q <= q >> 1;
3719
 
3720
endmodule
3721 40 unneback
`endif
3722 6 unneback
 
3723 40 unneback
`ifdef CNT_SHREG_CE_CLEAR_WRAP
3724
`define MODULE cnt_shreg_ce_clear_wrap
3725
module `BASE`MODULE ( cke, clear, q, rst, clk);
3726
`undef MODULE
3727 6 unneback
 
3728
   parameter length = 4;
3729
   input cke, clear;
3730
   output reg [0:length-1] q;
3731
   input rst;
3732
   input clk;
3733
 
3734
    always @ (posedge clk or posedge rst)
3735
    if (rst)
3736
        q <= {1'b1,{length-1{1'b0}}};
3737
    else
3738
        if (cke)
3739
            if (clear)
3740
                q <= {1'b1,{length-1{1'b0}}};
3741
            else
3742
            q <= {q[length-1],q[0:length-2]};
3743
 
3744
endmodule
3745 40 unneback
`endif
3746 6 unneback
//////////////////////////////////////////////////////////////////////
3747
////                                                              ////
3748
////  Versatile library, memories                                 ////
3749
////                                                              ////
3750
////  Description                                                 ////
3751
////  memories                                                    ////
3752
////                                                              ////
3753
////                                                              ////
3754
////  To Do:                                                      ////
3755
////   - add more memory types                                    ////
3756
////                                                              ////
3757
////  Author(s):                                                  ////
3758
////      - Michael Unneback, unneback@opencores.org              ////
3759
////        ORSoC AB                                              ////
3760
////                                                              ////
3761
//////////////////////////////////////////////////////////////////////
3762
////                                                              ////
3763
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
3764
////                                                              ////
3765
//// This source file may be used and distributed without         ////
3766
//// restriction provided that this copyright statement is not    ////
3767
//// removed from the file and that any derivative work contains  ////
3768
//// the original copyright notice and the associated disclaimer. ////
3769
////                                                              ////
3770
//// This source file is free software; you can redistribute it   ////
3771
//// and/or modify it under the terms of the GNU Lesser General   ////
3772
//// Public License as published by the Free Software Foundation; ////
3773
//// either version 2.1 of the License, or (at your option) any   ////
3774
//// later version.                                               ////
3775
////                                                              ////
3776
//// This source is distributed in the hope that it will be       ////
3777
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3778
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3779
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3780
//// details.                                                     ////
3781
////                                                              ////
3782
//// You should have received a copy of the GNU Lesser General    ////
3783
//// Public License along with this source; if not, download it   ////
3784
//// from http://www.opencores.org/lgpl.shtml                     ////
3785
////                                                              ////
3786
//////////////////////////////////////////////////////////////////////
3787
 
3788 40 unneback
`ifdef ROM_INIT
3789 6 unneback
/// ROM
3790 40 unneback
`define MODULE rom_init
3791
module `BASE`MODULE ( adr, q, clk);
3792
`undef MODULE
3793 6 unneback
 
3794 7 unneback
   parameter data_width = 32;
3795
   parameter addr_width = 8;
3796 75 unneback
   parameter mem_size = 1<<addr_width;
3797 7 unneback
   input [(addr_width-1):0]       adr;
3798
   output reg [(data_width-1):0] q;
3799
   input                         clk;
3800 75 unneback
   reg [data_width-1:0] rom [mem_size-1:0];
3801 7 unneback
   parameter memory_file = "vl_rom.vmem";
3802
   initial
3803
     begin
3804
        $readmemh(memory_file, rom);
3805
     end
3806
 
3807
   always @ (posedge clk)
3808
     q <= rom[adr];
3809 6 unneback
 
3810 7 unneback
endmodule
3811 40 unneback
`endif
3812 7 unneback
 
3813 40 unneback
`ifdef RAM
3814
`define MODULE ram
3815 6 unneback
// Single port RAM
3816 40 unneback
module `BASE`MODULE ( d, adr, we, q, clk);
3817
`undef MODULE
3818 6 unneback
 
3819
   parameter data_width = 32;
3820
   parameter addr_width = 8;
3821 75 unneback
   parameter mem_size = 1<<addr_width;
3822 100 unneback
   parameter debug = 0;
3823 6 unneback
   input [(data_width-1):0]      d;
3824
   input [(addr_width-1):0]       adr;
3825
   input                         we;
3826 7 unneback
   output reg [(data_width-1):0] q;
3827 6 unneback
   input                         clk;
3828 98 unneback
   reg [data_width-1:0] ram [mem_size-1:0];
3829 100 unneback
 
3830
    parameter memory_init = 0;
3831
    parameter memory_file = "vl_ram.vmem";
3832
    generate
3833
    if (memory_init == 1) begin : init_mem
3834
        initial
3835
            $readmemh(memory_file, ram);
3836
   end else if (memory_init == 2) begin : init_zero
3837
        integer k;
3838
        initial
3839
            for (k = 0; k < mem_size; k = k + 1)
3840
                ram[k] = 0;
3841 7 unneback
   end
3842
   endgenerate
3843
 
3844 100 unneback
    generate
3845
    if (debug==1) begin : debug_we
3846
        always @ (posedge clk)
3847
        if (we)
3848
            $display ("Value %h written at address %h : time %t", d, adr, $time);
3849
 
3850
    end
3851
    endgenerate
3852
 
3853 6 unneback
   always @ (posedge clk)
3854
   begin
3855
   if (we)
3856
     ram[adr] <= d;
3857
   q <= ram[adr];
3858
   end
3859
 
3860
endmodule
3861 40 unneback
`endif
3862 6 unneback
 
3863 40 unneback
`ifdef RAM_BE
3864
`define MODULE ram_be
3865 91 unneback
module `BASE`MODULE ( d, adr, be, we, q, clk);
3866 40 unneback
`undef MODULE
3867
 
3868 7 unneback
   parameter data_width = 32;
3869 72 unneback
   parameter addr_width = 6;
3870 75 unneback
   parameter mem_size = 1<<addr_width;
3871 7 unneback
   input [(data_width-1):0]      d;
3872
   input [(addr_width-1):0]       adr;
3873 73 unneback
   input [(data_width/8)-1:0]    be;
3874 7 unneback
   input                         we;
3875
   output reg [(data_width-1):0] q;
3876
   input                         clk;
3877
 
3878 85 unneback
 
3879 65 unneback
`ifdef SYSTEMVERILOG
3880 95 unneback
    // use a multi-dimensional packed array
3881
    //t o model individual bytes within the word
3882
    logic [data_width/8-1:0][7:0] ram [0:mem_size-1];// # words = 1 << address width
3883 65 unneback
`else
3884 85 unneback
    reg [data_width-1:0] ram [mem_size-1:0];
3885
    wire [data_width/8-1:0] cke;
3886 65 unneback
`endif
3887
 
3888 100 unneback
    parameter memory_init = 0;
3889
    parameter memory_file = "vl_ram.vmem";
3890
    generate
3891
    if (memory_init == 1) begin : init_mem
3892
        initial
3893
            $readmemh(memory_file, ram);
3894
    end else if (memory_init == 2) begin : init_zero
3895
        integer k;
3896
        initial
3897
            for (k = 0; k < mem_size; k = k + 1)
3898
                ram[k] = 0;
3899
    end
3900 7 unneback
   endgenerate
3901
 
3902 60 unneback
`ifdef SYSTEMVERILOG
3903
 
3904
always_ff@(posedge clk)
3905
begin
3906 95 unneback
    if(we) begin
3907 86 unneback
        if(be[3]) ram[adr][3] <= d[31:24];
3908
        if(be[2]) ram[adr][2] <= d[23:16];
3909
        if(be[1]) ram[adr][1] <= d[15:8];
3910
        if(be[0]) ram[adr][0] <= d[7:0];
3911 60 unneback
    end
3912 90 unneback
        q <= ram[adr];
3913 60 unneback
end
3914
 
3915
`else
3916
 
3917 85 unneback
assign cke = {data_width/8{we}} & be;
3918 7 unneback
   genvar i;
3919 85 unneback
   generate for (i=0;i<data_width/8;i=i+1) begin : be_ram
3920 7 unneback
      always @ (posedge clk)
3921 85 unneback
      if (cke[i])
3922 7 unneback
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
3923
   end
3924
   endgenerate
3925
 
3926
   always @ (posedge clk)
3927
      q <= ram[adr];
3928
 
3929 60 unneback
`endif
3930
 
3931 93 unneback
`ifdef verilator
3932 85 unneback
   // Function to access RAM (for use by Verilator).
3933
   function [31:0] get_mem;
3934
      // verilator public
3935 90 unneback
      input [addr_width-1:0]             addr;
3936 85 unneback
      get_mem = ram[addr];
3937
   endfunction // get_mem
3938
 
3939
   // Function to write RAM (for use by Verilator).
3940
   function set_mem;
3941
      // verilator public
3942 90 unneback
      input [addr_width-1:0]             addr;
3943
      input [data_width-1:0]             data;
3944 85 unneback
      ram[addr] = data;
3945
   endfunction // set_mem
3946 93 unneback
`endif
3947 85 unneback
 
3948 7 unneback
endmodule
3949 40 unneback
`endif
3950 7 unneback
 
3951 40 unneback
`ifdef DPRAM_1R1W
3952
`define MODULE dpram_1r1w
3953
module `BASE`MODULE ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
3954
`undef MODULE
3955 6 unneback
   parameter data_width = 32;
3956
   parameter addr_width = 8;
3957 75 unneback
   parameter mem_size = 1<<addr_width;
3958 6 unneback
   input [(data_width-1):0]      d_a;
3959
   input [(addr_width-1):0]       adr_a;
3960
   input [(addr_width-1):0]       adr_b;
3961
   input                         we_a;
3962
   output [(data_width-1):0]      q_b;
3963
   input                         clk_a, clk_b;
3964
   reg [(addr_width-1):0]         adr_b_reg;
3965 100 unneback
   reg [data_width-1:0] ram [mem_size-1:0] `SYN_NO_RW_CHECK;
3966 7 unneback
 
3967 100 unneback
    parameter memory_init = 0;
3968
    parameter memory_file = "vl_ram.vmem";
3969
    parameter debug = 0;
3970
 
3971
    generate
3972
    if (memory_init == 1) begin : init_mem
3973
        initial
3974
            $readmemh(memory_file, ram);
3975
    end else if (memory_init == 2) begin : init_zero
3976
        integer k;
3977
        initial
3978
            for (k = 0; k < mem_size; k = k + 1)
3979
                ram[k] = 0;
3980
    end
3981 7 unneback
   endgenerate
3982
 
3983 100 unneback
    generate
3984
    if (debug==1) begin : debug_we
3985
        always @ (posedge clk_a)
3986
        if (we_a)
3987
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
3988
 
3989
    end
3990
    endgenerate
3991
 
3992 6 unneback
   always @ (posedge clk_a)
3993
   if (we_a)
3994
     ram[adr_a] <= d_a;
3995
   always @ (posedge clk_b)
3996
   adr_b_reg <= adr_b;
3997
   assign q_b = ram[adr_b_reg];
3998 40 unneback
 
3999 6 unneback
endmodule
4000 40 unneback
`endif
4001 6 unneback
 
4002 40 unneback
`ifdef DPRAM_2R1W
4003
`define MODULE dpram_2r1w
4004
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
4005
`undef MODULE
4006
 
4007 6 unneback
   parameter data_width = 32;
4008
   parameter addr_width = 8;
4009 75 unneback
   parameter mem_size = 1<<addr_width;
4010 6 unneback
   input [(data_width-1):0]      d_a;
4011
   input [(addr_width-1):0]       adr_a;
4012
   input [(addr_width-1):0]       adr_b;
4013
   input                         we_a;
4014
   output [(data_width-1):0]      q_b;
4015
   output reg [(data_width-1):0] q_a;
4016
   input                         clk_a, clk_b;
4017
   reg [(data_width-1):0]         q_b;
4018 98 unneback
   reg [data_width-1:0] ram [mem_szie-1:0] `SYN_NO_RW_CHECK;
4019 7 unneback
 
4020 100 unneback
    parameter memory_init = 0;
4021
    parameter memory_file = "vl_ram.vmem";
4022
    parameter debug = 0;
4023
 
4024
    generate
4025
    if (memory_init == 1) begin : init_mem
4026
        initial
4027
            $readmemh(memory_file, ram);
4028
    end else if (memory_init == 2) begin : init_zero
4029
        integer k;
4030
        initial
4031
            for (k = 0; k < mem_size; k = k + 1)
4032
                ram[k] = 0;
4033
    end
4034 7 unneback
   endgenerate
4035
 
4036 100 unneback
    generate
4037
    if (debug==1) begin : debug_we
4038
        always @ (posedge clk_a)
4039
        if (we_a)
4040
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
4041
 
4042
    end
4043
    endgenerate
4044
 
4045 6 unneback
   always @ (posedge clk_a)
4046
     begin
4047
        q_a <= ram[adr_a];
4048
        if (we_a)
4049
             ram[adr_a] <= d_a;
4050
     end
4051
   always @ (posedge clk_b)
4052
          q_b <= ram[adr_b];
4053
endmodule
4054 40 unneback
`endif
4055 6 unneback
 
4056 100 unneback
`ifdef DPRAM_1R2W
4057
`define MODULE dpram_1r2w
4058
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, adr_b, we_b, clk_b );
4059
`undef MODULE
4060
 
4061
   parameter data_width = 32;
4062
   parameter addr_width = 8;
4063
   parameter mem_size = 1<<addr_width;
4064
   input [(data_width-1):0]      d_a;
4065
   input [(addr_width-1):0]       adr_a;
4066
   input [(addr_width-1):0]       adr_b;
4067
   input                         we_a;
4068
   input [(data_width-1):0]       d_b;
4069
   output reg [(data_width-1):0] q_a;
4070
   input                         we_b;
4071
   input                         clk_a, clk_b;
4072
   reg [(data_width-1):0]         q_b;
4073
   reg [data_width-1:0] ram [mem_size-1:0] `SYN_NO_RW_CHECK;
4074
 
4075
    parameter memory_init = 0;
4076
    parameter memory_file = "vl_ram.vmem";
4077
    parameter debug = 0;
4078
 
4079
    generate
4080
    if (memory_init == 1) begin : init_mem
4081
        initial
4082
            $readmemh(memory_file, ram);
4083
    end else if (memory_init == 2) begin : init_zero
4084
        integer k;
4085
        initial
4086
            for (k = 0; k < mem_size; k = k + 1)
4087
                ram[k] = 0;
4088
    end
4089
   endgenerate
4090
 
4091
    generate
4092
    if (debug==1) begin : debug_we
4093
        always @ (posedge clk_a)
4094
        if (we_a)
4095
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
4096
        always @ (posedge clk_b)
4097
        if (we_b)
4098
            $display ("Debug: Value %h written at address %h : time %t", d_b, adr_b, $time);
4099
    end
4100
    endgenerate
4101
 
4102
   always @ (posedge clk_a)
4103
     begin
4104
        q_a <= ram[adr_a];
4105
        if (we_a)
4106
             ram[adr_a] <= d_a;
4107
     end
4108
   always @ (posedge clk_b)
4109
     begin
4110
        if (we_b)
4111
          ram[adr_b] <= d_b;
4112
     end
4113
endmodule
4114
`endif
4115
 
4116 40 unneback
`ifdef DPRAM_2R2W
4117
`define MODULE dpram_2r2w
4118
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
4119
`undef MODULE
4120
 
4121 6 unneback
   parameter data_width = 32;
4122
   parameter addr_width = 8;
4123 75 unneback
   parameter mem_size = 1<<addr_width;
4124 6 unneback
   input [(data_width-1):0]      d_a;
4125
   input [(addr_width-1):0]       adr_a;
4126
   input [(addr_width-1):0]       adr_b;
4127
   input                         we_a;
4128
   output [(data_width-1):0]      q_b;
4129
   input [(data_width-1):0]       d_b;
4130
   output reg [(data_width-1):0] q_a;
4131
   input                         we_b;
4132
   input                         clk_a, clk_b;
4133
   reg [(data_width-1):0]         q_b;
4134 98 unneback
   reg [data_width-1:0] ram [mem_size-1:0] `SYN_NO_RW_CHECK;
4135 7 unneback
 
4136 100 unneback
    parameter memory_init = 0;
4137
    parameter memory_file = "vl_ram.vmem";
4138
    parameter debug = 0;
4139
 
4140
    generate
4141
    if (memory_init) begin : init_mem
4142
        initial
4143
            $readmemh(memory_file, ram);
4144
    end else if (memory_init == 2) begin : init_zero
4145
        integer k;
4146
        initial
4147
            for (k = 0; k < mem_size; k = k + 1)
4148
                ram[k] = 0;
4149
    end
4150 7 unneback
   endgenerate
4151
 
4152 100 unneback
    generate
4153
    if (debug==1) begin : debug_we
4154
        always @ (posedge clk_a)
4155
        if (we_a)
4156
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
4157
        always @ (posedge clk_b)
4158
        if (we_b)
4159
            $display ("Debug: Value %h written at address %h : time %t", d_b, adr_b, $time);
4160
    end
4161
    endgenerate
4162
 
4163 6 unneback
   always @ (posedge clk_a)
4164
     begin
4165
        q_a <= ram[adr_a];
4166
        if (we_a)
4167
             ram[adr_a] <= d_a;
4168
     end
4169
   always @ (posedge clk_b)
4170
     begin
4171
        q_b <= ram[adr_b];
4172
        if (we_b)
4173
          ram[adr_b] <= d_b;
4174
     end
4175
endmodule
4176 40 unneback
`endif
4177 6 unneback
 
4178 83 unneback
 
4179 75 unneback
`ifdef DPRAM_BE_2R2W
4180
`define MODULE dpram_be_2r2w
4181 92 unneback
module `BASE`MODULE ( d_a, q_a, adr_a, be_a, we_a, clk_a, d_b, q_b, adr_b, be_b, we_b, clk_b );
4182 75 unneback
`undef MODULE
4183
 
4184
   parameter a_data_width = 32;
4185
   parameter a_addr_width = 8;
4186 95 unneback
   parameter b_data_width = 64; //a_data_width;
4187 91 unneback
   localparam b_addr_width = a_data_width * a_addr_width / b_data_width;
4188 95 unneback
   localparam ratio = (a_addr_width>b_addr_width) ? (a_addr_width/b_addr_width) : (b_addr_width/a_addr_width);
4189
   parameter mem_size = (a_addr_width>b_addr_width) ? (1<<b_addr_width) : (1<<a_addr_width);
4190 91 unneback
 
4191 100 unneback
   parameter memory_init = 0;
4192 95 unneback
   parameter memory_file = "vl_ram.vmem";
4193 100 unneback
   parameter debug = 0;
4194 95 unneback
 
4195 75 unneback
   input [(a_data_width-1):0]      d_a;
4196 91 unneback
   input [(a_addr_width-1):0]       adr_a;
4197
   input [(a_data_width/8-1):0]    be_a;
4198
   input                           we_a;
4199 75 unneback
   output reg [(a_data_width-1):0] q_a;
4200 91 unneback
   input [(b_data_width-1):0]       d_b;
4201
   input [(b_addr_width-1):0]       adr_b;
4202 92 unneback
   input [(b_data_width/8-1):0]    be_b;
4203
   input                           we_b;
4204
   output reg [(b_data_width-1):0]          q_b;
4205 91 unneback
   input                           clk_a, clk_b;
4206 75 unneback
 
4207 100 unneback
    generate
4208
    if (debug==1) begin : debug_we
4209
        always @ (posedge clk_a)
4210
        if (we_a)
4211
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
4212
        always @ (posedge clk_b)
4213
        if (we_b)
4214
            $display ("Debug: Value %h written at address %h : time %t", d_b, adr_b, $time);
4215
    end
4216
    endgenerate
4217
 
4218
 
4219 91 unneback
`ifdef SYSTEMVERILOG
4220
// use a multi-dimensional packed array
4221
//to model individual bytes within the word
4222
 
4223 75 unneback
generate
4224 91 unneback
if (a_data_width==32 & b_data_width==32) begin : dpram_3232
4225 75 unneback
 
4226 98 unneback
    logic [0:3][7:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
4227 95 unneback
 
4228
    initial
4229 100 unneback
        if (memory_init==1)
4230 95 unneback
            $readmemh(memory_file, ram);
4231 100 unneback
 
4232
    integer k;
4233
    initial
4234
        if (memory_init==2)
4235
            for (k = 0; k < mem_size; k = k + 1)
4236
                ram[k] = 0;
4237 91 unneback
 
4238
    always_ff@(posedge clk_a)
4239
    begin
4240
        if(we_a) begin
4241 100 unneback
            if(be_a[3]) ram[adr_a][0] <= d_a[31:24];
4242
            if(be_a[2]) ram[adr_a][1] <= d_a[23:16];
4243
            if(be_a[1]) ram[adr_a][2] <= d_a[15:8];
4244
            if(be_a[0]) ram[adr_a][3] <= d_a[7:0];
4245 91 unneback
        end
4246
    end
4247
 
4248 92 unneback
    always@(posedge clk_a)
4249
        q_a = ram[adr_a];
4250 91 unneback
 
4251
    always_ff@(posedge clk_b)
4252 92 unneback
    begin
4253
        if(we_b) begin
4254 100 unneback
            if(be_b[3]) ram[adr_b][0] <= d_b[31:24];
4255
            if(be_b[2]) ram[adr_b][1] <= d_b[23:16];
4256
            if(be_b[1]) ram[adr_b][2] <= d_b[15:8];
4257
            if(be_b[0]) ram[adr_b][3] <= d_b[7:0];
4258 92 unneback
        end
4259
    end
4260 91 unneback
 
4261 92 unneback
    always@(posedge clk_b)
4262
        q_b = ram[adr_b];
4263 91 unneback
 
4264 75 unneback
end
4265
endgenerate
4266
 
4267 95 unneback
generate
4268
if (a_data_width==64 & b_data_width==64) begin : dpram_6464
4269
 
4270 98 unneback
    logic [0:7][7:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
4271 95 unneback
 
4272
    initial
4273 100 unneback
        if (memory_init==1)
4274 95 unneback
            $readmemh(memory_file, ram);
4275 100 unneback
 
4276
    integer k;
4277
    initial
4278
        if (memory_init==2)
4279
            for (k = 0; k < mem_size; k = k + 1)
4280
                ram[k] = 0;
4281 95 unneback
 
4282
    always_ff@(posedge clk_a)
4283
    begin
4284
        if(we_a) begin
4285
            if(be_a[7]) ram[adr_a][7] <= d_a[63:56];
4286
            if(be_a[6]) ram[adr_a][6] <= d_a[55:48];
4287
            if(be_a[5]) ram[adr_a][5] <= d_a[47:40];
4288
            if(be_a[4]) ram[adr_a][4] <= d_a[39:32];
4289
            if(be_a[3]) ram[adr_a][3] <= d_a[31:24];
4290
            if(be_a[2]) ram[adr_a][2] <= d_a[23:16];
4291
            if(be_a[1]) ram[adr_a][1] <= d_a[15:8];
4292
            if(be_a[0]) ram[adr_a][0] <= d_a[7:0];
4293
        end
4294
    end
4295
 
4296
    always@(posedge clk_a)
4297
        q_a = ram[adr_a];
4298
 
4299
    always_ff@(posedge clk_b)
4300
    begin
4301
        if(we_b) begin
4302
            if(be_b[7]) ram[adr_b][7] <= d_b[63:56];
4303
            if(be_b[6]) ram[adr_b][6] <= d_b[55:48];
4304
            if(be_b[5]) ram[adr_b][5] <= d_b[47:40];
4305
            if(be_b[4]) ram[adr_b][4] <= d_b[39:32];
4306
            if(be_b[3]) ram[adr_b][3] <= d_b[31:24];
4307
            if(be_b[2]) ram[adr_b][2] <= d_b[23:16];
4308
            if(be_b[1]) ram[adr_b][1] <= d_b[15:8];
4309
            if(be_b[0]) ram[adr_b][0] <= d_b[7:0];
4310
        end
4311
    end
4312
 
4313
    always@(posedge clk_b)
4314
        q_b = ram[adr_b];
4315
 
4316
end
4317
endgenerate
4318
 
4319
generate
4320
if (a_data_width==32 & b_data_width==16) begin : dpram_3216
4321
logic [31:0] temp;
4322
`define MODULE dpram_be_2r2w
4323 100 unneback
`BASE`MODULE # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .init(memory_init), .memory_file(memory_file))
4324 95 unneback
`undef MODULE
4325
dpram6464 (
4326
    .d_a(d_a),
4327
    .q_a(q_a),
4328
    .adr_a(adr_a),
4329
    .be_a(be_a),
4330
    .we_a(we_a),
4331
    .clk_a(clk_a),
4332
    .d_b({d_b,d_b}),
4333
    .q_b(temp),
4334
    .adr_b(adr_b),
4335
    .be_b({be_b,be_b} & {{2{adr_b[0]}},{2{!adr_b[0]}}}),
4336
    .we_b(we_b),
4337
    .clk_b(clk_b)
4338
);
4339
 
4340 100 unneback
always @ (adr_b[0] or temp)
4341 95 unneback
    if (adr_b[0])
4342
        q_b = temp[31:16];
4343
    else
4344
        q_b = temp[15:0];
4345
 
4346
end
4347
endgenerate
4348
 
4349
generate
4350
if (a_data_width==32 & b_data_width==64) begin : dpram_3264
4351
logic [63:0] temp;
4352
`define MODULE dpram_be_2r2w
4353 100 unneback
`BASE`MODULE # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .init(memory_init), .memory_file(memory_file))
4354 95 unneback
`undef MODULE
4355
dpram6464 (
4356
    .d_a({d_a,d_a}),
4357
    .q_a(temp),
4358
    .adr_a(adr_a[a_addr_width-1:1]),
4359
    .be_a({be_a,be_a} & {{4{adr_a[0]}},{4{!adr_a[0]}}}),
4360
    .we_a(we_a),
4361
    .clk_a(clk_a),
4362
    .d_b(d_b),
4363
    .q_b(q_b),
4364
    .adr_b(adr_b),
4365
    .be_b(be_b),
4366
    .we_b(we_b),
4367
    .clk_b(clk_b)
4368
);
4369
 
4370 100 unneback
always @ (adr_a[0] or temp)
4371 95 unneback
    if (adr_a[0])
4372
        q_a = temp[63:32];
4373
    else
4374
        q_a = temp[31:0];
4375
 
4376
end
4377
endgenerate
4378
 
4379 91 unneback
`else
4380 92 unneback
    // This modules requires SystemVerilog
4381 98 unneback
    // at this point anyway
4382 91 unneback
`endif
4383 75 unneback
endmodule
4384
`endif
4385
 
4386 91 unneback
`ifdef CAM
4387 6 unneback
// Content addresable memory, CAM
4388 91 unneback
`endif
4389 6 unneback
 
4390 40 unneback
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
4391 6 unneback
// FIFO
4392 40 unneback
`define MODULE fifo_1r1w_fill_level_sync
4393
module `BASE`MODULE (
4394
`undef MODULE
4395 25 unneback
    d, wr, fifo_full,
4396
    q, rd, fifo_empty,
4397
    fill_level,
4398
    clk, rst
4399
    );
4400
 
4401
parameter data_width = 18;
4402
parameter addr_width = 4;
4403 6 unneback
 
4404 25 unneback
// write side
4405
input  [data_width-1:0] d;
4406
input                   wr;
4407
output                  fifo_full;
4408
// read side
4409
output [data_width-1:0] q;
4410
input                   rd;
4411
output                  fifo_empty;
4412
// common
4413
output [addr_width:0]   fill_level;
4414
input rst, clk;
4415
 
4416
wire [addr_width:1] wadr, radr;
4417
 
4418 40 unneback
`define MODULE cnt_bin_ce
4419
`BASE`MODULE
4420 25 unneback
    # ( .length(addr_width))
4421
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
4422 40 unneback
`BASE`MODULE
4423 25 unneback
    # (.length(addr_width))
4424
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
4425 40 unneback
`undef MODULE
4426 25 unneback
 
4427 40 unneback
`define MODULE dpram_1r1w
4428
`BASE`MODULE
4429 25 unneback
    # (.data_width(data_width), .addr_width(addr_width))
4430
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
4431 40 unneback
`undef MODULE
4432 25 unneback
 
4433 40 unneback
`define MODULE cnt_bin_ce_rew_q_zq_l1
4434
`BASE`MODULE
4435 27 unneback
    # (.length(addr_width+1), .level1_value(1<<addr_width))
4436 25 unneback
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
4437 40 unneback
`undef MODULE
4438 25 unneback
endmodule
4439 40 unneback
`endif
4440 25 unneback
 
4441 40 unneback
`ifdef FIFO_2R2W_SYNC_SIMPLEX
4442 27 unneback
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
4443
// RAM is supposed to be larger than the two FIFOs
4444
// LFSR counters used adr pointers
4445 40 unneback
`define MODULE fifo_2r2w_sync_simplex
4446
module `BASE`MODULE (
4447
`undef MODULE
4448 27 unneback
    // a side
4449
    a_d, a_wr, a_fifo_full,
4450
    a_q, a_rd, a_fifo_empty,
4451
    a_fill_level,
4452
    // b side
4453
    b_d, b_wr, b_fifo_full,
4454
    b_q, b_rd, b_fifo_empty,
4455
    b_fill_level,
4456
    // common
4457
    clk, rst
4458
    );
4459
parameter data_width = 8;
4460
parameter addr_width = 5;
4461
parameter fifo_full_level = (1<<addr_width)-1;
4462
 
4463
// a side
4464
input  [data_width-1:0] a_d;
4465
input                   a_wr;
4466
output                  a_fifo_full;
4467
output [data_width-1:0] a_q;
4468
input                   a_rd;
4469
output                  a_fifo_empty;
4470
output [addr_width-1:0] a_fill_level;
4471
 
4472
// b side
4473
input  [data_width-1:0] b_d;
4474
input                   b_wr;
4475
output                  b_fifo_full;
4476
output [data_width-1:0] b_q;
4477
input                   b_rd;
4478
output                  b_fifo_empty;
4479
output [addr_width-1:0] b_fill_level;
4480
 
4481
input                   clk;
4482
input                   rst;
4483
 
4484
// adr_gen
4485
wire [addr_width:1] a_wadr, a_radr;
4486
wire [addr_width:1] b_wadr, b_radr;
4487
// dpram
4488
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
4489
 
4490 40 unneback
`define MODULE cnt_lfsr_ce
4491
`BASE`MODULE
4492 27 unneback
    # ( .length(addr_width))
4493
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
4494
 
4495 40 unneback
`BASE`MODULE
4496 27 unneback
    # (.length(addr_width))
4497
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
4498
 
4499 40 unneback
`BASE`MODULE
4500 27 unneback
    # ( .length(addr_width))
4501
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
4502
 
4503 40 unneback
`BASE`MODULE
4504 27 unneback
    # (.length(addr_width))
4505
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
4506 40 unneback
`undef MODULE
4507 27 unneback
 
4508
// mux read or write adr to DPRAM
4509
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
4510
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
4511
 
4512 40 unneback
`define MODULE dpram_2r2w
4513
`BASE`MODULE
4514 27 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
4515
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
4516
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
4517 40 unneback
`undef MODULE
4518
 
4519
`define MODULE cnt_bin_ce_rew_zq_l1
4520
`BASE`MODULE
4521 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
4522 27 unneback
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
4523
 
4524 40 unneback
`BASE`MODULE
4525 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
4526 27 unneback
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
4527 40 unneback
`undef MODULE
4528 27 unneback
 
4529
endmodule
4530 40 unneback
`endif
4531 27 unneback
 
4532 40 unneback
`ifdef FIFO_CMP_ASYNC
4533
`define MODULE fifo_cmp_async
4534
module `BASE`MODULE ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
4535
`undef MODULE
4536 6 unneback
 
4537 11 unneback
   parameter addr_width = 4;
4538
   parameter N = addr_width-1;
4539 6 unneback
 
4540
   parameter Q1 = 2'b00;
4541
   parameter Q2 = 2'b01;
4542
   parameter Q3 = 2'b11;
4543
   parameter Q4 = 2'b10;
4544
 
4545
   parameter going_empty = 1'b0;
4546
   parameter going_full  = 1'b1;
4547
 
4548
   input [N:0]  wptr, rptr;
4549 14 unneback
   output       fifo_empty;
4550 6 unneback
   output       fifo_full;
4551
   input        wclk, rclk, rst;
4552
 
4553
`ifndef GENERATE_DIRECTION_AS_LATCH
4554
   wire direction;
4555
`endif
4556
`ifdef GENERATE_DIRECTION_AS_LATCH
4557
   reg direction;
4558
`endif
4559
   reg  direction_set, direction_clr;
4560
 
4561
   wire async_empty, async_full;
4562
   wire fifo_full2;
4563 14 unneback
   wire fifo_empty2;
4564 6 unneback
 
4565
   // direction_set
4566
   always @ (wptr[N:N-1] or rptr[N:N-1])
4567
     case ({wptr[N:N-1],rptr[N:N-1]})
4568
       {Q1,Q2} : direction_set <= 1'b1;
4569
       {Q2,Q3} : direction_set <= 1'b1;
4570
       {Q3,Q4} : direction_set <= 1'b1;
4571
       {Q4,Q1} : direction_set <= 1'b1;
4572
       default : direction_set <= 1'b0;
4573
     endcase
4574
 
4575
   // direction_clear
4576
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
4577
     if (rst)
4578
       direction_clr <= 1'b1;
4579
     else
4580
       case ({wptr[N:N-1],rptr[N:N-1]})
4581
         {Q2,Q1} : direction_clr <= 1'b1;
4582
         {Q3,Q2} : direction_clr <= 1'b1;
4583
         {Q4,Q3} : direction_clr <= 1'b1;
4584
         {Q1,Q4} : direction_clr <= 1'b1;
4585
         default : direction_clr <= 1'b0;
4586
       endcase
4587
 
4588 40 unneback
`define MODULE dff_sr
4589 6 unneback
`ifndef GENERATE_DIRECTION_AS_LATCH
4590 40 unneback
    `BASE`MODULE dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
4591 6 unneback
`endif
4592
 
4593
`ifdef GENERATE_DIRECTION_AS_LATCH
4594
   always @ (posedge direction_set or posedge direction_clr)
4595
     if (direction_clr)
4596
       direction <= going_empty;
4597
     else
4598
       direction <= going_full;
4599
`endif
4600
 
4601
   assign async_empty = (wptr == rptr) && (direction==going_empty);
4602
   assign async_full  = (wptr == rptr) && (direction==going_full);
4603
 
4604 40 unneback
    `BASE`MODULE dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
4605
    `BASE`MODULE dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
4606
`undef MODULE
4607 6 unneback
 
4608
/*
4609
   always @ (posedge wclk or posedge rst or posedge async_full)
4610
     if (rst)
4611
       {fifo_full, fifo_full2} <= 2'b00;
4612
     else if (async_full)
4613
       {fifo_full, fifo_full2} <= 2'b11;
4614
     else
4615
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
4616
*/
4617 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
4618 6 unneback
     if (async_empty)
4619
       {fifo_empty, fifo_empty2} <= 2'b11;
4620
     else
4621 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
4622 40 unneback
`define MODULE dff
4623
    `BASE`MODULE # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
4624
    `BASE`MODULE # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
4625
`undef MODULE
4626 27 unneback
endmodule // async_compb
4627 40 unneback
`endif
4628 6 unneback
 
4629 40 unneback
`ifdef FIFO_1R1W_ASYNC
4630
`define MODULE fifo_1r1w_async
4631
module `BASE`MODULE (
4632
`undef MODULE
4633 6 unneback
    d, wr, fifo_full, wr_clk, wr_rst,
4634
    q, rd, fifo_empty, rd_clk, rd_rst
4635
    );
4636
 
4637
parameter data_width = 18;
4638
parameter addr_width = 4;
4639
 
4640
// write side
4641
input  [data_width-1:0] d;
4642
input                   wr;
4643
output                  fifo_full;
4644
input                   wr_clk;
4645
input                   wr_rst;
4646
// read side
4647
output [data_width-1:0] q;
4648
input                   rd;
4649
output                  fifo_empty;
4650
input                   rd_clk;
4651
input                   rd_rst;
4652
 
4653
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
4654 23 unneback
 
4655 40 unneback
`define MODULE cnt_gray_ce_bin
4656
`BASE`MODULE
4657 6 unneback
    # ( .length(addr_width))
4658
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
4659
 
4660 40 unneback
`BASE`MODULE
4661 6 unneback
    # (.length(addr_width))
4662 23 unneback
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
4663 40 unneback
`undef MODULE
4664 6 unneback
 
4665 40 unneback
`define MODULE dpram_1r1w
4666
`BASE`MODULE
4667 6 unneback
    # (.data_width(data_width), .addr_width(addr_width))
4668
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
4669 40 unneback
`undef MODULE
4670 6 unneback
 
4671 40 unneback
`define MODULE fifo_cmp_async
4672
`BASE`MODULE
4673 6 unneback
    # (.addr_width(addr_width))
4674
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
4675 40 unneback
`undef MODULE
4676 6 unneback
 
4677
endmodule
4678 40 unneback
`endif
4679 6 unneback
 
4680 40 unneback
`ifdef FIFO_2R2W_ASYNC
4681
`define MODULE fifo_2r2w_async
4682
module `BASE`MODULE (
4683
`undef MODULE
4684 6 unneback
    // a side
4685
    a_d, a_wr, a_fifo_full,
4686
    a_q, a_rd, a_fifo_empty,
4687
    a_clk, a_rst,
4688
    // b side
4689
    b_d, b_wr, b_fifo_full,
4690
    b_q, b_rd, b_fifo_empty,
4691
    b_clk, b_rst
4692
    );
4693
 
4694
parameter data_width = 18;
4695
parameter addr_width = 4;
4696
 
4697
// a side
4698
input  [data_width-1:0] a_d;
4699
input                   a_wr;
4700
output                  a_fifo_full;
4701
output [data_width-1:0] a_q;
4702
input                   a_rd;
4703
output                  a_fifo_empty;
4704
input                   a_clk;
4705
input                   a_rst;
4706
 
4707
// b side
4708
input  [data_width-1:0] b_d;
4709
input                   b_wr;
4710
output                  b_fifo_full;
4711
output [data_width-1:0] b_q;
4712
input                   b_rd;
4713
output                  b_fifo_empty;
4714
input                   b_clk;
4715
input                   b_rst;
4716
 
4717 40 unneback
`define MODULE fifo_1r1w_async
4718
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
4719 6 unneback
vl_fifo_1r1w_async_a (
4720
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
4721
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
4722
    );
4723
 
4724 40 unneback
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
4725 6 unneback
vl_fifo_1r1w_async_b (
4726
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
4727
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
4728
    );
4729 40 unneback
`undef MODULE
4730
 
4731 6 unneback
endmodule
4732 40 unneback
`endif
4733 6 unneback
 
4734 40 unneback
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
4735
`define MODULE fifo_2r2w_async_simplex
4736
module `BASE`MODULE (
4737
`undef MODULE
4738 6 unneback
    // a side
4739
    a_d, a_wr, a_fifo_full,
4740
    a_q, a_rd, a_fifo_empty,
4741
    a_clk, a_rst,
4742
    // b side
4743
    b_d, b_wr, b_fifo_full,
4744
    b_q, b_rd, b_fifo_empty,
4745
    b_clk, b_rst
4746
    );
4747
 
4748
parameter data_width = 18;
4749
parameter addr_width = 4;
4750
 
4751
// a side
4752
input  [data_width-1:0] a_d;
4753
input                   a_wr;
4754
output                  a_fifo_full;
4755
output [data_width-1:0] a_q;
4756
input                   a_rd;
4757
output                  a_fifo_empty;
4758
input                   a_clk;
4759
input                   a_rst;
4760
 
4761
// b side
4762
input  [data_width-1:0] b_d;
4763
input                   b_wr;
4764
output                  b_fifo_full;
4765
output [data_width-1:0] b_q;
4766
input                   b_rd;
4767
output                  b_fifo_empty;
4768
input                   b_clk;
4769
input                   b_rst;
4770
 
4771
// adr_gen
4772
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
4773
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
4774
// dpram
4775
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
4776
 
4777 40 unneback
`define MODULE cnt_gray_ce_bin
4778
`BASE`MODULE
4779 6 unneback
    # ( .length(addr_width))
4780
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
4781
 
4782 40 unneback
`BASE`MODULE
4783 6 unneback
    # (.length(addr_width))
4784
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
4785
 
4786 40 unneback
`BASE`MODULE
4787 6 unneback
    # ( .length(addr_width))
4788
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
4789
 
4790 40 unneback
`BASE`MODULE
4791 6 unneback
    # (.length(addr_width))
4792
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
4793 40 unneback
`undef MODULE
4794 6 unneback
 
4795
// mux read or write adr to DPRAM
4796
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
4797
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
4798
 
4799 40 unneback
`define MODULE dpram_2r2w
4800
`BASE`MODULE
4801 6 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
4802
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
4803
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
4804 40 unneback
`undef MODULE
4805 6 unneback
 
4806 40 unneback
`define MODULE fifo_cmp_async
4807
`BASE`MODULE
4808 6 unneback
    # (.addr_width(addr_width))
4809
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
4810
 
4811 40 unneback
`BASE`MODULE
4812 6 unneback
    # (.addr_width(addr_width))
4813
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
4814 40 unneback
`undef MODULE
4815 6 unneback
 
4816
endmodule
4817 40 unneback
`endif
4818 48 unneback
 
4819
`ifdef REG_FILE
4820
`define MODULE reg_file
4821
module `BASE`MODULE (
4822
`undef MODULE
4823
    a1, a2, a3, wd3, we3, rd1, rd2, clk
4824
);
4825
parameter data_width = 32;
4826
parameter addr_width = 5;
4827
input [addr_width-1:0] a1, a2, a3;
4828
input [data_width-1:0] wd3;
4829
input we3;
4830
output [data_width-1:0] rd1, rd2;
4831
input clk;
4832
 
4833
`ifdef ACTEL
4834
reg [data_width-1:0] wd3_reg;
4835
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
4836
reg we3_reg;
4837 98 unneback
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] `SYN_NO_RW_CHECK;
4838
reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] `SYN_NO_RW_CHECK;
4839 48 unneback
always @ (posedge clk or posedge rst)
4840
if (rst)
4841
    {wd3_reg, a3_reg, we3_reg} <= {(data_width+addr_width+1){1'b0}};
4842
else
4843
    {wd3_reg, a3_reg, we3_reg} <= {wd3,a3,wd3};
4844
 
4845
    always @ (negedge clk)
4846
    if (we3_reg)
4847
        ram1[a3_reg] <= wd3;
4848
    always @ (posedge clk)
4849
        a1_reg <= a1;
4850
    assign rd1 = ram1[a1_reg];
4851
 
4852
    always @ (negedge clk)
4853
    if (we3_reg)
4854
        ram2[a3_reg] <= wd3;
4855
    always @ (posedge clk)
4856
        a2_reg <= a2;
4857
    assign rd2 = ram2[a2_reg];
4858
 
4859
`else
4860
 
4861
`define MODULE dpram_1r1w
4862
`BASE`MODULE
4863
    # ( .data_width(data_width), .addr_width(addr_width))
4864
    ram1 (
4865
        .d_a(wd3),
4866
        .adr_a(a3),
4867
        .we_a(we3),
4868
        .clk_a(clk),
4869
        .q_b(rd1),
4870
        .adr_b(a1),
4871
        .clk_b(clk) );
4872
 
4873
`BASE`MODULE
4874
    # ( .data_width(data_width), .addr_width(addr_width))
4875
    ram2 (
4876
        .d_a(wd3),
4877
        .adr_a(a3),
4878
        .we_a(we3),
4879
        .clk_a(clk),
4880
        .q_b(rd2),
4881
        .adr_b(a2),
4882
        .clk_b(clk) );
4883
`undef MODULE
4884
 
4885
`endif
4886
 
4887
endmodule
4888
`endif
4889 12 unneback
//////////////////////////////////////////////////////////////////////
4890
////                                                              ////
4891
////  Versatile library, wishbone stuff                           ////
4892
////                                                              ////
4893
////  Description                                                 ////
4894
////  Wishbone compliant modules                                  ////
4895
////                                                              ////
4896
////                                                              ////
4897
////  To Do:                                                      ////
4898
////   -                                                          ////
4899
////                                                              ////
4900
////  Author(s):                                                  ////
4901
////      - Michael Unneback, unneback@opencores.org              ////
4902
////        ORSoC AB                                              ////
4903
////                                                              ////
4904
//////////////////////////////////////////////////////////////////////
4905
////                                                              ////
4906
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
4907
////                                                              ////
4908
//// This source file may be used and distributed without         ////
4909
//// restriction provided that this copyright statement is not    ////
4910
//// removed from the file and that any derivative work contains  ////
4911
//// the original copyright notice and the associated disclaimer. ////
4912
////                                                              ////
4913
//// This source file is free software; you can redistribute it   ////
4914
//// and/or modify it under the terms of the GNU Lesser General   ////
4915
//// Public License as published by the Free Software Foundation; ////
4916
//// either version 2.1 of the License, or (at your option) any   ////
4917
//// later version.                                               ////
4918
////                                                              ////
4919
//// This source is distributed in the hope that it will be       ////
4920
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
4921
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
4922
//// PURPOSE.  See the GNU Lesser General Public License for more ////
4923
//// details.                                                     ////
4924
////                                                              ////
4925
//// You should have received a copy of the GNU Lesser General    ////
4926
//// Public License along with this source; if not, download it   ////
4927
//// from http://www.opencores.org/lgpl.shtml                     ////
4928
////                                                              ////
4929
//////////////////////////////////////////////////////////////////////
4930
 
4931 75 unneback
`ifdef WB_ADR_INC
4932
`timescale 1ns/1ns
4933
`define MODULE wb_adr_inc
4934 85 unneback
module `BASE`MODULE ( cyc_i, stb_i, cti_i, bte_i, adr_i, we_i, ack_o, adr_o, clk, rst);
4935 75 unneback
`undef MODULE
4936 83 unneback
parameter adr_width = 10;
4937
parameter max_burst_width = 4;
4938 85 unneback
input cyc_i, stb_i, we_i;
4939 83 unneback
input [2:0] cti_i;
4940
input [1:0] bte_i;
4941
input [adr_width-1:0] adr_i;
4942
output [adr_width-1:0] adr_o;
4943
output ack_o;
4944
input clk, rst;
4945 75 unneback
 
4946 83 unneback
reg [adr_width-1:0] adr;
4947 90 unneback
wire [max_burst_width-1:0] to_adr;
4948 91 unneback
reg [max_burst_width-1:0] last_adr;
4949 92 unneback
reg last_cycle;
4950
localparam idle_or_eoc = 1'b0;
4951
localparam cyc_or_ws   = 1'b1;
4952 90 unneback
 
4953 91 unneback
always @ (posedge clk or posedge rst)
4954
if (rst)
4955
    last_adr <= {max_burst_width{1'b0}};
4956
else
4957
    if (stb_i)
4958 92 unneback
        last_adr <=adr_o[max_burst_width-1:0];
4959 91 unneback
 
4960 83 unneback
generate
4961
if (max_burst_width==0) begin : inst_0
4962 97 unneback
 
4963
        reg ack_o;
4964
        assign adr_o = adr_i;
4965
        always @ (posedge clk or posedge rst)
4966
        if (rst)
4967
            ack_o <= 1'b0;
4968
        else
4969
            ack_o <= cyc_i & stb_i & !ack_o;
4970
 
4971 83 unneback
end else begin
4972
 
4973
    always @ (posedge clk or posedge rst)
4974
    if (rst)
4975 92 unneback
        last_cycle <= idle_or_eoc;
4976 83 unneback
    else
4977 92 unneback
        last_cycle <= (!cyc_i) ? idle_or_eoc : //idle
4978
                      (cyc_i & ack_o & (cti_i==3'b000 | cti_i==3'b111)) ? idle_or_eoc : // eoc
4979
                      (cyc_i & !stb_i) ? cyc_or_ws : //ws
4980
                      cyc_or_ws; // cyc
4981
    assign to_adr = (last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
4982 85 unneback
    assign adr_o[max_burst_width-1:0] = (we_i) ? adr_i[max_burst_width-1:0] :
4983 91 unneback
                                        (!stb_i) ? last_adr :
4984 92 unneback
                                        (last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] :
4985 85 unneback
                                        adr[max_burst_width-1:0];
4986 92 unneback
    assign ack_o = (last_cycle==cyc_or_ws) & stb_i;
4987 97 unneback
 
4988 83 unneback
end
4989
endgenerate
4990
 
4991
generate
4992
if (max_burst_width==2) begin : inst_2
4993
    always @ (posedge clk or posedge rst)
4994
    if (rst)
4995
        adr <= 2'h0;
4996
    else
4997
        if (cyc_i & stb_i)
4998
            adr[1:0] <= to_adr[1:0] + 2'd1;
4999 75 unneback
        else
5000 83 unneback
            adr <= to_adr[1:0];
5001
end
5002
endgenerate
5003
 
5004
generate
5005
if (max_burst_width==3) begin : inst_3
5006
    always @ (posedge clk or posedge rst)
5007
    if (rst)
5008
        adr <= 3'h0;
5009
    else
5010
        if (cyc_i & stb_i)
5011
            case (bte_i)
5012
            2'b01: adr[2:0] <= {to_adr[2],to_adr[1:0] + 2'd1};
5013
            default: adr[3:0] <= to_adr[2:0] + 3'd1;
5014 75 unneback
            endcase
5015 83 unneback
        else
5016
            adr <= to_adr[2:0];
5017
end
5018
endgenerate
5019
 
5020
generate
5021
if (max_burst_width==4) begin : inst_4
5022
    always @ (posedge clk or posedge rst)
5023
    if (rst)
5024
        adr <= 4'h0;
5025
    else
5026 91 unneback
        if (stb_i) // | (!stb_i & last_cycle!=ws)) // for !stb_i restart with adr_i +1, only inc once
5027 83 unneback
            case (bte_i)
5028
            2'b01: adr[3:0] <= {to_adr[3:2],to_adr[1:0] + 2'd1};
5029
            2'b10: adr[3:0] <= {to_adr[3],to_adr[2:0] + 3'd1};
5030
            default: adr[3:0] <= to_adr + 4'd1;
5031
            endcase
5032
        else
5033
            adr <= to_adr[3:0];
5034
end
5035
endgenerate
5036
 
5037
generate
5038
if (adr_width > max_burst_width) begin : pass_through
5039
    assign adr_o[adr_width-1:max_burst_width] = adr_i[adr_width-1:max_burst_width];
5040
end
5041
endgenerate
5042
 
5043
endmodule
5044 75 unneback
`endif
5045
 
5046 40 unneback
`ifdef WB3WB3_BRIDGE
5047 12 unneback
// async wb3 - wb3 bridge
5048
`timescale 1ns/1ns
5049 40 unneback
`define MODULE wb3wb3_bridge
5050
module `BASE`MODULE (
5051
`undef MODULE
5052 12 unneback
        // wishbone slave side
5053
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
5054
        // wishbone master side
5055
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
5056
 
5057 95 unneback
parameter style = "FIFO"; // valid: simple, FIFO
5058
parameter addr_width = 4;
5059
 
5060 12 unneback
input [31:0] wbs_dat_i;
5061
input [31:2] wbs_adr_i;
5062
input [3:0]  wbs_sel_i;
5063
input [1:0]  wbs_bte_i;
5064
input [2:0]  wbs_cti_i;
5065
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
5066
output [31:0] wbs_dat_o;
5067 14 unneback
output wbs_ack_o;
5068 12 unneback
input wbs_clk, wbs_rst;
5069
 
5070
output [31:0] wbm_dat_o;
5071
output reg [31:2] wbm_adr_o;
5072
output [3:0]  wbm_sel_o;
5073
output reg [1:0]  wbm_bte_o;
5074
output reg [2:0]  wbm_cti_o;
5075 14 unneback
output reg wbm_we_o;
5076
output wbm_cyc_o;
5077 12 unneback
output wbm_stb_o;
5078
input [31:0]  wbm_dat_i;
5079
input wbm_ack_i;
5080
input wbm_clk, wbm_rst;
5081
 
5082
// bte
5083
parameter linear       = 2'b00;
5084
parameter wrap4        = 2'b01;
5085
parameter wrap8        = 2'b10;
5086
parameter wrap16       = 2'b11;
5087
// cti
5088
parameter classic      = 3'b000;
5089
parameter incburst     = 3'b010;
5090
parameter endofburst   = 3'b111;
5091
 
5092 95 unneback
localparam wbs_adr  = 1'b0;
5093
localparam wbs_data = 1'b1;
5094 12 unneback
 
5095 95 unneback
localparam wbm_adr0      = 2'b00;
5096
localparam wbm_adr1      = 2'b01;
5097
localparam wbm_data      = 2'b10;
5098
localparam wbm_data_wait = 2'b11;
5099 12 unneback
 
5100
reg [1:0] wbs_bte_reg;
5101
reg wbs;
5102
wire wbs_eoc_alert, wbm_eoc_alert;
5103
reg wbs_eoc, wbm_eoc;
5104
reg [1:0] wbm;
5105
 
5106 14 unneback
wire [1:16] wbs_count, wbm_count;
5107 12 unneback
 
5108
wire [35:0] a_d, a_q, b_d, b_q;
5109
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
5110
reg a_rd_reg;
5111
wire b_rd_adr, b_rd_data;
5112 14 unneback
wire b_rd_data_reg;
5113
wire [35:0] temp;
5114 12 unneback
 
5115
`define WE 5
5116
`define BTE 4:3
5117
`define CTI 2:0
5118
 
5119
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
5120
always @ (posedge wbs_clk or posedge wbs_rst)
5121
if (wbs_rst)
5122
        wbs_eoc <= 1'b0;
5123
else
5124
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
5125 78 unneback
                wbs_eoc <= (wbs_bte_i==linear) | (wbs_cti_i==3'b111);
5126 12 unneback
        else if (wbs_eoc_alert & (a_rd | a_wr))
5127
                wbs_eoc <= 1'b1;
5128
 
5129 40 unneback
`define MODULE cnt_shreg_ce_clear
5130
`BASE`MODULE # ( .length(16))
5131
`undef MODULE
5132 12 unneback
    cnt0 (
5133
        .cke(wbs_ack_o),
5134
        .clear(wbs_eoc),
5135
        .q(wbs_count),
5136
        .rst(wbs_rst),
5137
        .clk(wbs_clk));
5138
 
5139
always @ (posedge wbs_clk or posedge wbs_rst)
5140
if (wbs_rst)
5141
        wbs <= wbs_adr;
5142
else
5143 75 unneback
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & a_fifo_empty)
5144 12 unneback
                wbs <= wbs_data;
5145
        else if (wbs_eoc & wbs_ack_o)
5146
                wbs <= wbs_adr;
5147
 
5148
// wbs FIFO
5149 75 unneback
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,((wbs_cti_i==3'b111) ? {2'b00,3'b000} : {wbs_bte_i,wbs_cti_i})} : {wbs_dat_i,wbs_sel_i};
5150
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & a_fifo_empty :
5151 12 unneback
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
5152
              1'b0;
5153
assign a_rd = !a_fifo_empty;
5154
always @ (posedge wbs_clk or posedge wbs_rst)
5155
if (wbs_rst)
5156
        a_rd_reg <= 1'b0;
5157
else
5158
        a_rd_reg <= a_rd;
5159
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
5160
 
5161
assign wbs_dat_o = a_q[35:4];
5162
 
5163
always @ (posedge wbs_clk or posedge wbs_rst)
5164
if (wbs_rst)
5165 13 unneback
        wbs_bte_reg <= 2'b00;
5166 12 unneback
else
5167 13 unneback
        wbs_bte_reg <= wbs_bte_i;
5168 12 unneback
 
5169
// wbm FIFO
5170
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
5171
always @ (posedge wbm_clk or posedge wbm_rst)
5172
if (wbm_rst)
5173
        wbm_eoc <= 1'b0;
5174
else
5175
        if (wbm==wbm_adr0 & !b_fifo_empty)
5176
                wbm_eoc <= b_q[`BTE] == linear;
5177
        else if (wbm_eoc_alert & wbm_ack_i)
5178
                wbm_eoc <= 1'b1;
5179
 
5180
always @ (posedge wbm_clk or posedge wbm_rst)
5181
if (wbm_rst)
5182
        wbm <= wbm_adr0;
5183
else
5184 33 unneback
/*
5185 12 unneback
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
5186
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
5187
        (wbm==wbm_adr1 & !wbm_we_o) |
5188
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
5189
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
5190 33 unneback
*/
5191
    case (wbm)
5192
    wbm_adr0:
5193
        if (!b_fifo_empty)
5194
            wbm <= wbm_adr1;
5195
    wbm_adr1:
5196
        if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
5197
            wbm <= wbm_data;
5198
    wbm_data:
5199
        if (wbm_ack_i & wbm_eoc)
5200
            wbm <= wbm_adr0;
5201
        else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
5202
            wbm <= wbm_data_wait;
5203
    wbm_data_wait:
5204
        if (!b_fifo_empty)
5205
            wbm <= wbm_data;
5206
    endcase
5207 12 unneback
 
5208
assign b_d = {wbm_dat_i,4'b1111};
5209
assign b_wr = !wbm_we_o & wbm_ack_i;
5210
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
5211
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
5212
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
5213 33 unneback
                   (wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
5214 12 unneback
                   1'b0;
5215
assign b_rd = b_rd_adr | b_rd_data;
5216
 
5217 40 unneback
`define MODULE dff
5218
`BASE`MODULE dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
5219
`undef MODULE
5220
`define MODULE dff_ce
5221
`BASE`MODULE # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
5222
`undef MODULE
5223 12 unneback
 
5224
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
5225
 
5226 40 unneback
`define MODULE cnt_shreg_ce_clear
5227 42 unneback
`BASE`MODULE # ( .length(16))
5228 40 unneback
`undef MODULE
5229 12 unneback
    cnt1 (
5230
        .cke(wbm_ack_i),
5231
        .clear(wbm_eoc),
5232
        .q(wbm_count),
5233
        .rst(wbm_rst),
5234
        .clk(wbm_clk));
5235
 
5236 33 unneback
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
5237
assign wbm_stb_o = (wbm==wbm_data);
5238 12 unneback
 
5239
always @ (posedge wbm_clk or posedge wbm_rst)
5240
if (wbm_rst)
5241
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
5242
else begin
5243
        if (wbm==wbm_adr0 & !b_fifo_empty)
5244
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
5245
        else if (wbm_eoc_alert & wbm_ack_i)
5246
                wbm_cti_o <= endofburst;
5247
end
5248
 
5249
//async_fifo_dw_simplex_top
5250 40 unneback
`define MODULE fifo_2r2w_async_simplex
5251
`BASE`MODULE
5252
`undef MODULE
5253 12 unneback
# ( .data_width(36), .addr_width(addr_width))
5254
fifo (
5255
    // a side
5256
    .a_d(a_d),
5257
    .a_wr(a_wr),
5258
    .a_fifo_full(a_fifo_full),
5259
    .a_q(a_q),
5260
    .a_rd(a_rd),
5261
    .a_fifo_empty(a_fifo_empty),
5262
    .a_clk(wbs_clk),
5263
    .a_rst(wbs_rst),
5264
    // b side
5265
    .b_d(b_d),
5266
    .b_wr(b_wr),
5267
    .b_fifo_full(b_fifo_full),
5268
    .b_q(b_q),
5269
    .b_rd(b_rd),
5270
    .b_fifo_empty(b_fifo_empty),
5271
    .b_clk(wbm_clk),
5272
    .b_rst(wbm_rst)
5273
    );
5274
 
5275
endmodule
5276 40 unneback
`undef WE
5277
`undef BTE
5278
`undef CTI
5279
`endif
5280 17 unneback
 
5281 75 unneback
`ifdef WB3AVALON_BRIDGE
5282
`define MODULE wb3avalon_bridge
5283
module `BASE`MODULE (
5284
`undef MODULE
5285
        // wishbone slave side
5286
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
5287 77 unneback
        // avalon master side
5288 75 unneback
        readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst);
5289
 
5290 85 unneback
parameter linewrapburst = 1'b0;
5291
 
5292 75 unneback
input [31:0] wbs_dat_i;
5293
input [31:2] wbs_adr_i;
5294
input [3:0]  wbs_sel_i;
5295
input [1:0]  wbs_bte_i;
5296
input [2:0]  wbs_cti_i;
5297 83 unneback
input wbs_we_i;
5298
input wbs_cyc_i;
5299
input wbs_stb_i;
5300 75 unneback
output [31:0] wbs_dat_o;
5301
output wbs_ack_o;
5302
input wbs_clk, wbs_rst;
5303
 
5304
input [31:0] readdata;
5305
output [31:0] writedata;
5306
output [31:2] address;
5307
output [3:0]  be;
5308
output write;
5309 81 unneback
output read;
5310 75 unneback
output beginbursttransfer;
5311
output [3:0] burstcount;
5312
input readdatavalid;
5313
input waitrequest;
5314
input clk;
5315
input rst;
5316
 
5317
wire [1:0] wbm_bte_o;
5318
wire [2:0] wbm_cti_o;
5319
wire wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_ack_i;
5320
reg last_cyc;
5321 79 unneback
reg [3:0] counter;
5322 82 unneback
reg read_busy;
5323 75 unneback
 
5324
always @ (posedge clk or posedge rst)
5325
if (rst)
5326
    last_cyc <= 1'b0;
5327
else
5328
    last_cyc <= wbm_cyc_o;
5329
 
5330 79 unneback
always @ (posedge clk or posedge rst)
5331
if (rst)
5332 82 unneback
    read_busy <= 1'b0;
5333 79 unneback
else
5334 82 unneback
    if (read & !waitrequest)
5335
        read_busy <= 1'b1;
5336
    else if (wbm_ack_i & wbm_cti_o!=3'b010)
5337
        read_busy <= 1'b0;
5338
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o & !read_busy;
5339 81 unneback
 
5340 75 unneback
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010;
5341
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 :
5342
                    (wbm_bte_o==2'b10) ? 4'd8 :
5343 78 unneback
                    (wbm_bte_o==2'b11) ? 4'd16:
5344
                    4'd1;
5345 82 unneback
assign wbm_ack_i = (readdatavalid) | (write & !waitrequest);
5346 75 unneback
 
5347 79 unneback
always @ (posedge clk or posedge rst)
5348
if (rst) begin
5349
    counter <= 4'd0;
5350
end else
5351 80 unneback
    if (wbm_we_o) begin
5352
        if (!waitrequest & !last_cyc & wbm_cyc_o) begin
5353 85 unneback
            counter <= burstcount -4'd1;
5354 80 unneback
        end else if (waitrequest & !last_cyc & wbm_cyc_o) begin
5355
            counter <= burstcount;
5356
        end else if (!waitrequest & wbm_stb_o) begin
5357
            counter <= counter - 4'd1;
5358
        end
5359 82 unneback
    end
5360 81 unneback
assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o & counter!=4'd0;
5361 79 unneback
 
5362 75 unneback
`define MODULE wb3wb3_bridge
5363 77 unneback
`BASE`MODULE wbwb3inst (
5364 75 unneback
`undef MODULE
5365
    // wishbone slave side
5366
    .wbs_dat_i(wbs_dat_i),
5367
    .wbs_adr_i(wbs_adr_i),
5368
    .wbs_sel_i(wbs_sel_i),
5369
    .wbs_bte_i(wbs_bte_i),
5370
    .wbs_cti_i(wbs_cti_i),
5371
    .wbs_we_i(wbs_we_i),
5372
    .wbs_cyc_i(wbs_cyc_i),
5373
    .wbs_stb_i(wbs_stb_i),
5374
    .wbs_dat_o(wbs_dat_o),
5375
    .wbs_ack_o(wbs_ack_o),
5376
    .wbs_clk(wbs_clk),
5377
    .wbs_rst(wbs_rst),
5378
    // wishbone master side
5379
    .wbm_dat_o(writedata),
5380 78 unneback
    .wbm_adr_o(address),
5381 75 unneback
    .wbm_sel_o(be),
5382
    .wbm_bte_o(wbm_bte_o),
5383
    .wbm_cti_o(wbm_cti_o),
5384
    .wbm_we_o(wbm_we_o),
5385
    .wbm_cyc_o(wbm_cyc_o),
5386
    .wbm_stb_o(wbm_stb_o),
5387
    .wbm_dat_i(readdata),
5388
    .wbm_ack_i(wbm_ack_i),
5389
    .wbm_clk(clk),
5390
    .wbm_rst(rst));
5391
 
5392
 
5393
endmodule
5394
`endif
5395
 
5396 40 unneback
`ifdef WB3_ARBITER_TYPE1
5397
`define MODULE wb3_arbiter_type1
5398 42 unneback
module `BASE`MODULE (
5399 40 unneback
`undef MODULE
5400 39 unneback
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
5401
    wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
5402
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
5403
    wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
5404
    wb_clk, wb_rst
5405
);
5406
 
5407
parameter nr_of_ports = 3;
5408
parameter adr_size = 26;
5409
parameter adr_lo   = 2;
5410
parameter dat_size = 32;
5411
parameter sel_size = dat_size/8;
5412
 
5413
localparam aw = (adr_size - adr_lo) * nr_of_ports;
5414
localparam dw = dat_size * nr_of_ports;
5415
localparam sw = sel_size * nr_of_ports;
5416
localparam cw = 3 * nr_of_ports;
5417
localparam bw = 2 * nr_of_ports;
5418
 
5419
input  [dw-1:0] wbm_dat_o;
5420
input  [aw-1:0] wbm_adr_o;
5421
input  [sw-1:0] wbm_sel_o;
5422
input  [cw-1:0] wbm_cti_o;
5423
input  [bw-1:0] wbm_bte_o;
5424
input  [nr_of_ports-1:0] wbm_we_o, wbm_stb_o, wbm_cyc_o;
5425
output [dw-1:0] wbm_dat_i;
5426
output [nr_of_ports-1:0] wbm_ack_i, wbm_err_i, wbm_rty_i;
5427
 
5428
output [dat_size-1:0] wbs_dat_i;
5429
output [adr_size-1:adr_lo] wbs_adr_i;
5430
output [sel_size-1:0] wbs_sel_i;
5431
output [2:0] wbs_cti_i;
5432
output [1:0] wbs_bte_i;
5433
output wbs_we_i, wbs_stb_i, wbs_cyc_i;
5434
input  [dat_size-1:0] wbs_dat_o;
5435
input  wbs_ack_o, wbs_err_o, wbs_rty_o;
5436
 
5437
input wb_clk, wb_rst;
5438
 
5439 44 unneback
reg  [nr_of_ports-1:0] select;
5440 39 unneback
wire [nr_of_ports-1:0] state;
5441
wire [nr_of_ports-1:0] eoc; // end-of-cycle
5442
wire [nr_of_ports-1:0] sel;
5443
wire idle;
5444
 
5445
genvar i;
5446
 
5447
assign idle = !(|state);
5448
 
5449
generate
5450
if (nr_of_ports == 2) begin
5451
 
5452
    wire [2:0] wbm1_cti_o, wbm0_cti_o;
5453
 
5454
    assign {wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5455
 
5456 44 unneback
    //assign select = (idle) ? {wbm_cyc_o[1],!wbm_cyc_o[1] & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5457
 
5458
    always @ (idle or wbm_cyc_o)
5459
    if (idle)
5460
        casex (wbm_cyc_o)
5461
        2'b1x : select = 2'b10;
5462
        2'b01 : select = 2'b01;
5463
        default : select = {nr_of_ports{1'b0}};
5464
        endcase
5465
    else
5466
        select = {nr_of_ports{1'b0}};
5467
 
5468 39 unneback
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5469
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5470
 
5471
end
5472
endgenerate
5473
 
5474
generate
5475
if (nr_of_ports == 3) begin
5476
 
5477
    wire [2:0] wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5478
 
5479
    assign {wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5480
 
5481 44 unneback
    always @ (idle or wbm_cyc_o)
5482
    if (idle)
5483
        casex (wbm_cyc_o)
5484
        3'b1xx : select = 3'b100;
5485
        3'b01x : select = 3'b010;
5486
        3'b001 : select = 3'b001;
5487
        default : select = {nr_of_ports{1'b0}};
5488
        endcase
5489
    else
5490
        select = {nr_of_ports{1'b0}};
5491
 
5492
//    assign select = (idle) ? {wbm_cyc_o[2],!wbm_cyc_o[2] & wbm_cyc_o[1],wbm_cyc_o[2:1]==2'b00 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5493 39 unneback
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5494
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5495
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5496
 
5497
end
5498
endgenerate
5499
 
5500
generate
5501 44 unneback
if (nr_of_ports == 4) begin
5502
 
5503
    wire [2:0] wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5504
 
5505
    assign {wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5506
 
5507
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5508
 
5509
    always @ (idle or wbm_cyc_o)
5510
    if (idle)
5511
        casex (wbm_cyc_o)
5512
        4'b1xxx : select = 4'b1000;
5513
        4'b01xx : select = 4'b0100;
5514
        4'b001x : select = 4'b0010;
5515
        4'b0001 : select = 4'b0001;
5516
        default : select = {nr_of_ports{1'b0}};
5517
        endcase
5518
    else
5519
        select = {nr_of_ports{1'b0}};
5520
 
5521
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5522
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5523
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5524
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5525
 
5526
end
5527
endgenerate
5528
 
5529
generate
5530
if (nr_of_ports == 5) begin
5531
 
5532
    wire [2:0] wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5533
 
5534
    assign {wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5535
 
5536
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5537
 
5538
    always @ (idle or wbm_cyc_o)
5539
    if (idle)
5540
        casex (wbm_cyc_o)
5541
        5'b1xxxx : select = 5'b10000;
5542
        5'b01xxx : select = 5'b01000;
5543
        5'b001xx : select = 5'b00100;
5544
        5'b0001x : select = 5'b00010;
5545
        5'b00001 : select = 5'b00001;
5546
        default : select = {nr_of_ports{1'b0}};
5547
        endcase
5548
    else
5549
        select = {nr_of_ports{1'b0}};
5550
 
5551
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
5552
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5553
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5554
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5555
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5556
 
5557
end
5558
endgenerate
5559
 
5560
generate
5561 67 unneback
if (nr_of_ports == 6) begin
5562
 
5563
    wire [2:0] wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5564
 
5565
    assign {wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5566
 
5567
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5568
 
5569
    always @ (idle or wbm_cyc_o)
5570
    if (idle)
5571
        casex (wbm_cyc_o)
5572
        6'b1xxxxx : select = 6'b100000;
5573
        6'b01xxxx : select = 6'b010000;
5574
        6'b001xxx : select = 6'b001000;
5575
        6'b0001xx : select = 6'b000100;
5576
        6'b00001x : select = 6'b000010;
5577
        6'b000001 : select = 6'b000001;
5578
        default : select = {nr_of_ports{1'b0}};
5579
        endcase
5580
    else
5581
        select = {nr_of_ports{1'b0}};
5582
 
5583
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
5584
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
5585
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5586
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5587
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5588
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5589
 
5590
end
5591
endgenerate
5592
 
5593
generate
5594
if (nr_of_ports == 7) begin
5595
 
5596
    wire [2:0] wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5597
 
5598
    assign {wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5599
 
5600
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5601
 
5602
    always @ (idle or wbm_cyc_o)
5603
    if (idle)
5604
        casex (wbm_cyc_o)
5605
        7'b1xxxxxx : select = 7'b1000000;
5606
        7'b01xxxxx : select = 7'b0100000;
5607
        7'b001xxxx : select = 7'b0010000;
5608
        7'b0001xxx : select = 7'b0001000;
5609
        7'b00001xx : select = 7'b0000100;
5610
        7'b000001x : select = 7'b0000010;
5611
        7'b0000001 : select = 7'b0000001;
5612
        default : select = {nr_of_ports{1'b0}};
5613
        endcase
5614
    else
5615
        select = {nr_of_ports{1'b0}};
5616
 
5617
    assign eoc[6] = (wbm_ack_i[6] & (wbm6_cti_o == 3'b000 | wbm6_cti_o == 3'b111)) | !wbm_cyc_o[6];
5618
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
5619
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
5620
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5621
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5622
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5623
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5624
 
5625
end
5626
endgenerate
5627
 
5628
generate
5629
if (nr_of_ports == 8) begin
5630
 
5631
    wire [2:0] wbm7_cti_o, wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5632
 
5633
    assign {wbm7_cti_o, wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5634
 
5635
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5636
 
5637
    always @ (idle or wbm_cyc_o)
5638
    if (idle)
5639
        casex (wbm_cyc_o)
5640
        8'b1xxxxxxx : select = 8'b10000000;
5641
        8'b01xxxxxx : select = 8'b01000000;
5642
        8'b001xxxxx : select = 8'b00100000;
5643
        8'b0001xxxx : select = 8'b00010000;
5644
        8'b00001xxx : select = 8'b00001000;
5645
        8'b000001xx : select = 8'b00000100;
5646
        8'b0000001x : select = 8'b00000010;
5647
        8'b00000001 : select = 8'b00000001;
5648
        default : select = {nr_of_ports{1'b0}};
5649
        endcase
5650
    else
5651
        select = {nr_of_ports{1'b0}};
5652
 
5653
    assign eoc[7] = (wbm_ack_i[7] & (wbm7_cti_o == 3'b000 | wbm7_cti_o == 3'b111)) | !wbm_cyc_o[7];
5654
    assign eoc[6] = (wbm_ack_i[6] & (wbm6_cti_o == 3'b000 | wbm6_cti_o == 3'b111)) | !wbm_cyc_o[6];
5655
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
5656
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
5657
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5658
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5659
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5660
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5661
 
5662
end
5663
endgenerate
5664
 
5665
generate
5666 63 unneback
for (i=0;i<nr_of_ports;i=i+1) begin : spr0
5667 42 unneback
`define MODULE spr
5668
    `BASE`MODULE sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));
5669
`undef MODULE
5670 39 unneback
end
5671
endgenerate
5672
 
5673
    assign sel = select | state;
5674
 
5675 40 unneback
`define MODULE mux_andor
5676
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i));
5677
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(adr_size-adr_lo)) mux1 ( .a(wbm_adr_o), .sel(sel), .dout(wbs_adr_i));
5678
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(sel_size)) mux2 ( .a(wbm_sel_o), .sel(sel), .dout(wbs_sel_i));
5679
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(3)) mux3 ( .a(wbm_cti_o), .sel(sel), .dout(wbs_cti_i));
5680
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(2)) mux4 ( .a(wbm_bte_o), .sel(sel), .dout(wbs_bte_i));
5681
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux5 ( .a(wbm_we_o), .sel(sel), .dout(wbs_we_i));
5682
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux6 ( .a(wbm_stb_o), .sel(sel), .dout(wbs_stb_i));
5683
`undef MODULE
5684 39 unneback
    assign wbs_cyc_i = |sel;
5685
 
5686
    assign wbm_dat_i = {nr_of_ports{wbs_dat_o}};
5687
    assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
5688
    assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
5689
    assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
5690
 
5691
endmodule
5692 40 unneback
`endif
5693 39 unneback
 
5694 101 unneback
`ifdef WB_RAM
5695 49 unneback
// WB RAM with byte enable
5696 101 unneback
`define MODULE wb_ram
5697 59 unneback
module `BASE`MODULE (
5698
`undef MODULE
5699 69 unneback
    wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
5700 101 unneback
    wbs_dat_o, wbs_ack_o, wbs_stall_o, wb_clk, wb_rst);
5701 59 unneback
 
5702 101 unneback
parameter adr_width = 16;
5703
parameter mem_size = 1<<adr_width;
5704
parameter dat_width = 32;
5705
parameter max_burst_width = 4; // only used for B3
5706
parameter mode = "B3"; // valid options: B3, B4
5707 60 unneback
parameter memory_init = 1;
5708
parameter memory_file = "vl_ram.vmem";
5709 59 unneback
 
5710 101 unneback
input [dat_width-1:0] wbs_dat_i;
5711
input [adr_width-1:0] wbs_adr_i;
5712
input [2:0] wbs_cti_i;
5713
input [1:0] wbs_bte_i;
5714
input [dat_width/8-1:0] wbs_sel_i;
5715 70 unneback
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
5716 101 unneback
output [dat_width-1:0] wbs_dat_o;
5717 70 unneback
output wbs_ack_o;
5718 101 unneback
output wbs_stall_o;
5719 71 unneback
input wb_clk, wb_rst;
5720 59 unneback
 
5721 101 unneback
wire [adr_width-1:0] adr;
5722
wire we;
5723 59 unneback
 
5724 101 unneback
generate
5725
if (mode=="B3") begin : B3_inst
5726 83 unneback
`define MODULE wb_adr_inc
5727 101 unneback
`BASE`MODULE # ( .adr_width(adr_width), .max_burst_width(max_burst_width)) adr_inc0 (
5728 83 unneback
    .cyc_i(wbs_cyc_i),
5729
    .stb_i(wbs_stb_i),
5730
    .cti_i(wbs_cti_i),
5731
    .bte_i(wbs_bte_i),
5732
    .adr_i(wbs_adr_i),
5733 85 unneback
    .we_i(wbs_we_i),
5734 83 unneback
    .ack_o(wbs_ack_o),
5735
    .adr_o(adr),
5736
    .clk(wb_clk),
5737
    .rst(wb_rst));
5738
`undef MODULE
5739 101 unneback
assign we = wbs_we_i & wbs_ack_o;
5740
end else if (mode=="B4") begin : B4_inst
5741
reg wbs_ack_o_reg;
5742
always @ (posedge wb_clk or posedge wb_rst)
5743
    if (wb_rst)
5744
        wbs_ack_o_reg <= 1'b0;
5745
    else
5746
        wbs_ack_o_reg <= wbs_stb_i & wbs_cyc_i;
5747
assign wbs_ack_o = wbs_ack_o_reg;
5748
assign wbs_stall_o = 1'b0;
5749
assign adr = wbs_adr_i;
5750
assign we = wbs_we_i & wbs_cyc_i & wbs_stb_i;
5751
end
5752
endgenerate
5753 60 unneback
 
5754 100 unneback
`define MODULE ram_be
5755
`BASE`MODULE # (
5756
    .data_width(dat_width),
5757
    .addr_width(adr_width),
5758
    .mem_size(mem_size),
5759
    .memory_init(memory_init),
5760
    .memory_file(memory_file))
5761
ram0(
5762
`undef MODULE
5763 101 unneback
    .d(wbs_dat_i),
5764
    .adr(adr),
5765
    .be(wbs_sel_i),
5766
    .we(we),
5767
    .q(wbs_dat_o),
5768 100 unneback
    .clk(wb_clk)
5769
);
5770 49 unneback
 
5771
endmodule
5772
`endif
5773
 
5774 103 unneback
`ifdef WB_SHADOW_RAM
5775
// A wishbone compliant RAM module that can be placed in front of other memory controllers
5776
`define MODULE wb_shadow_ram
5777
module `BASE`MODULE (
5778
`undef MODULE
5779
    wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
5780
    wbs_dat_o, wbs_ack_o, wbs_stall_o,
5781
    wbm_dat_o, wbm_adr_o, wbm_cti_o, wbm_bte_o, wbm_sel_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
5782
    wbm_dat_i, wbm_ack_i, wbm_stall_i,
5783
    wb_clk, wb_rst);
5784
 
5785
parameter dat_width = 32;
5786
parameter mode = "B4";
5787
parameter max_burst_width = 4; // only used for B3
5788
 
5789
parameter shadow_mem_adr_width = 10;
5790
parameter shadow_mem_size = 1024;
5791
parameter shadow_mem_init = 2;
5792
parameter shadow_mem_file = "vl_ram.v";
5793
 
5794
parameter main_mem_adr_width = 24;
5795
 
5796
input [dat_width-1:0] wbs_dat_i;
5797
input [main_mem_adr_width-1:0] wbs_adr_i;
5798
input [2:0] wbs_cti_i;
5799
input [1:0] wbs_bte_i;
5800
input [dat_width/8-1:0] wbs_sel_i;
5801
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
5802
output [dat_width-1:0] wbs_dat_o;
5803
output wbs_ack_o;
5804
output wbs_stall_o;
5805
 
5806
output [dat_width-1:0] wbm_dat_o;
5807
output [main_mem_adr_width-1:0] wbm_adr_o;
5808
output [2:0] wbm_cti_o;
5809
output [1:0] wbm_bte_o;
5810
output [dat_width/8-1:0] wbm_sel_o;
5811
output wbm_we_o, wbm_stb_o, wbm_cyc_o;
5812
input [dat_width-1:0] wbm_dat_i;
5813
input wbm_ack_i, wbm_stall_i;
5814
 
5815
input wb_clk, wb_rst;
5816
 
5817
generate
5818
if (shadow_mem_size>0) begin : shadow_ram_inst
5819
 
5820
wire cyc;
5821
wire [dat_width-1:0] dat;
5822
wire stall, ack;
5823
 
5824
assign cyc = wbs_cyc_i & (wbs_adr_i<=shadow_mem_size);
5825
`define MODULE wb_ram
5826
`BASE`MODULE # (
5827
    .dat_width(dat_width),
5828
    .adr_width(shadow_mem_adr_width),
5829
    .mem_size(shadow_mem_size),
5830
    .memory_init(shadow_mem_init),
5831
    .mode(mode))
5832
shadow_mem0 (
5833
    .wbs_dat_i(wbs_dat_i),
5834
    .wbs_adr_i(wbs_adr_i[shadow_mem_adr_width-1:0]),
5835
    .wbs_sel_i(wbs_sel_i),
5836
    .wbs_we_i (wbs_we_i),
5837
    .wbs_bte_i(wbs_bte_i),
5838
    .wbs_cti_i(wbs_cti_i),
5839
    .wbs_stb_i(wbs_stb_i),
5840
    .wbs_cyc_i(cyc),
5841
    .wbs_dat_o(dat),
5842
    .wbs_stall_o(stall),
5843
    .wbs_ack_o(ack),
5844
    .wb_clk(wb_clk),
5845
    .wb_rst(wb_rst));
5846
`undef MODULE
5847
 
5848
assign {wbm_dat_o, wbm_adr_o, wbm_cti_o, wbm_bte_o, wbm_sel_o, wbm_we_o, wbm_stb_o} =
5849
       {wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i};
5850
assign wbm_cyc_o = wbs_cyc_i & (wbs_adr_i>shadow_mem_size);
5851
 
5852
assign wbs_dat_o = (dat & {dat_width{cyc}}) | (wbm_dat_i & {dat_width{wbm_cyc_o}});
5853
assign wbs_ack_o = (ack & cyc) | (wbm_ack_i & wbm_cyc_o);
5854
assign wbs_stall_o = (stall & cyc) | (wbm_stall_i & wbm_cyc_o);
5855
 
5856
end else begin : no_shadow_ram_inst
5857
 
5858
assign {wbm_dat_o, wbm_adr_o, wbm_cti_o, wbm_bte_o, wbm_sel_o, wbm_we_o, wbm_stb_o, wbm_cyc_o} =
5859
       {wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i};
5860
assign {wbs_dat_o, wbs_ack_o, wbs_stall_o} = {wbm_dat_i, wbm_ack_i, wbm_stall_i};
5861
 
5862
end
5863
endgenerate
5864
 
5865
endmodule
5866
`endif
5867
 
5868 48 unneback
`ifdef WB_B4_ROM
5869
// WB ROM
5870
`define MODULE wb_b4_rom
5871
module `BASE`MODULE (
5872
`undef MODULE
5873
    wb_adr_i, wb_stb_i, wb_cyc_i,
5874
    wb_dat_o, stall_o, wb_ack_o, wb_clk, wb_rst);
5875
 
5876
    parameter dat_width = 32;
5877
    parameter dat_default = 32'h15000000;
5878
    parameter adr_width = 32;
5879
 
5880
/*
5881
`ifndef ROM
5882
`define ROM "rom.v"
5883
`endif
5884
*/
5885
    input [adr_width-1:2]   wb_adr_i;
5886
    input                   wb_stb_i;
5887
    input                   wb_cyc_i;
5888
    output [dat_width-1:0]  wb_dat_o;
5889
    reg [dat_width-1:0]     wb_dat_o;
5890
    output                  wb_ack_o;
5891
    reg                     wb_ack_o;
5892
    output                  stall_o;
5893
    input                   wb_clk;
5894
    input                   wb_rst;
5895
 
5896
always @ (posedge wb_clk or posedge wb_rst)
5897
    if (wb_rst)
5898
        wb_dat_o <= {dat_width{1'b0}};
5899
    else
5900
         case (wb_adr_i[adr_width-1:2])
5901
`ifdef ROM
5902
`include `ROM
5903
`endif
5904
           default:
5905
             wb_dat_o <= dat_default;
5906
 
5907
         endcase // case (wb_adr_i)
5908
 
5909
 
5910
always @ (posedge wb_clk or posedge wb_rst)
5911
    if (wb_rst)
5912
        wb_ack_o <= 1'b0;
5913
    else
5914
        wb_ack_o <= wb_stb_i & wb_cyc_i;
5915
 
5916
assign stall_o = 1'b0;
5917
 
5918
endmodule
5919
`endif
5920
 
5921
 
5922 40 unneback
`ifdef WB_BOOT_ROM
5923 17 unneback
// WB ROM
5924 40 unneback
`define MODULE wb_boot_rom
5925
module `BASE`MODULE (
5926
`undef MODULE
5927 17 unneback
    wb_adr_i, wb_stb_i, wb_cyc_i,
5928 18 unneback
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
5929 17 unneback
 
5930 18 unneback
    parameter adr_hi = 31;
5931
    parameter adr_lo = 28;
5932
    parameter adr_sel = 4'hf;
5933
    parameter addr_width = 5;
5934 33 unneback
/*
5935 17 unneback
`ifndef BOOT_ROM
5936
`define BOOT_ROM "boot_rom.v"
5937
`endif
5938 33 unneback
*/
5939 18 unneback
    input [adr_hi:2]    wb_adr_i;
5940
    input               wb_stb_i;
5941
    input               wb_cyc_i;
5942
    output [31:0]        wb_dat_o;
5943
    output              wb_ack_o;
5944
    output              hit_o;
5945
    input               wb_clk;
5946
    input               wb_rst;
5947
 
5948
    wire hit;
5949
    reg [31:0] wb_dat;
5950
    reg wb_ack;
5951
 
5952
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
5953 17 unneback
 
5954
always @ (posedge wb_clk or posedge wb_rst)
5955
    if (wb_rst)
5956 18 unneback
        wb_dat <= 32'h15000000;
5957 17 unneback
    else
5958 18 unneback
         case (wb_adr_i[addr_width-1:2])
5959 33 unneback
`ifdef BOOT_ROM
5960 17 unneback
`include `BOOT_ROM
5961 33 unneback
`endif
5962 17 unneback
           /*
5963
            // Zero r0 and jump to 0x00000100
5964 18 unneback
 
5965
            1 : wb_dat <= 32'hA8200000;
5966
            2 : wb_dat <= 32'hA8C00100;
5967
            3 : wb_dat <= 32'h44003000;
5968
            4 : wb_dat <= 32'h15000000;
5969 17 unneback
            */
5970
           default:
5971 18 unneback
             wb_dat <= 32'h00000000;
5972 17 unneback
 
5973
         endcase // case (wb_adr_i)
5974
 
5975
 
5976
always @ (posedge wb_clk or posedge wb_rst)
5977
    if (wb_rst)
5978 18 unneback
        wb_ack <= 1'b0;
5979 17 unneback
    else
5980 18 unneback
        wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
5981 17 unneback
 
5982 18 unneback
assign hit_o = hit;
5983
assign wb_dat_o = wb_dat & {32{wb_ack}};
5984
assign wb_ack_o = wb_ack;
5985
 
5986 17 unneback
endmodule
5987 40 unneback
`endif
5988 32 unneback
 
5989 92 unneback
`ifdef WB_B3_DPRAM
5990
`define MODULE wb_b3_dpram
5991 40 unneback
module `BASE`MODULE (
5992
`undef MODULE
5993 32 unneback
        // wishbone slave side a
5994 92 unneback
        wbsa_dat_i, wbsa_adr_i, wbsa_sel_i, wbsa_cti_i, wbsa_bte_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o,
5995 32 unneback
        wbsa_clk, wbsa_rst,
5996 92 unneback
        // wishbone slave side b
5997
        wbsb_dat_i, wbsb_adr_i, wbsb_sel_i, wbsb_cti_i, wbsb_bte_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o,
5998 32 unneback
        wbsb_clk, wbsb_rst);
5999
 
6000 92 unneback
parameter data_width_a = 32;
6001
parameter data_width_b = data_width_a;
6002
parameter addr_width_a = 8;
6003
localparam addr_width_b = data_width_a * addr_width_a / data_width_b;
6004 101 unneback
parameter mem_size = (addr_width_a>addr_width_b) ? (1<<addr_width_a) : (1<<addr_width_b);
6005 92 unneback
parameter max_burst_width_a = 4;
6006
parameter max_burst_width_b = max_burst_width_a;
6007 101 unneback
parameter mode = "B3";
6008 92 unneback
input [data_width_a-1:0] wbsa_dat_i;
6009
input [addr_width_a-1:0] wbsa_adr_i;
6010
input [data_width_a/8-1:0] wbsa_sel_i;
6011
input [2:0] wbsa_cti_i;
6012
input [1:0] wbsa_bte_i;
6013 32 unneback
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
6014 92 unneback
output [data_width_a-1:0] wbsa_dat_o;
6015 32 unneback
output wbsa_ack_o;
6016
input wbsa_clk, wbsa_rst;
6017
 
6018 92 unneback
input [data_width_b-1:0] wbsb_dat_i;
6019
input [addr_width_b-1:0] wbsb_adr_i;
6020
input [data_width_b/8-1:0] wbsb_sel_i;
6021
input [2:0] wbsb_cti_i;
6022
input [1:0] wbsb_bte_i;
6023 32 unneback
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
6024 92 unneback
output [data_width_b-1:0] wbsb_dat_o;
6025 32 unneback
output wbsb_ack_o;
6026
input wbsb_clk, wbsb_rst;
6027
 
6028 92 unneback
wire [addr_width_a-1:0] adr_a;
6029
wire [addr_width_b-1:0] adr_b;
6030 101 unneback
wire we_a, we_b;
6031
generate
6032
if (mode=="B3") begin : b3_inst
6033 92 unneback
`define MODULE wb_adr_inc
6034
`BASE`MODULE # ( .adr_width(addr_width_a), .max_burst_width(max_burst_width_a)) adr_inc0 (
6035
    .cyc_i(wbsa_cyc_i),
6036
    .stb_i(wbsa_stb_i),
6037
    .cti_i(wbsa_cti_i),
6038
    .bte_i(wbsa_bte_i),
6039
    .adr_i(wbsa_adr_i),
6040
    .we_i(wbsa_we_i),
6041
    .ack_o(wbsa_ack_o),
6042
    .adr_o(adr_a),
6043
    .clk(wbsa_clk),
6044
    .rst(wbsa_rst));
6045 101 unneback
assign we_a = wbsa_we_i & wbsa_ack_o;
6046 92 unneback
`BASE`MODULE # ( .adr_width(addr_width_b), .max_burst_width(max_burst_width_b)) adr_inc1 (
6047
    .cyc_i(wbsb_cyc_i),
6048
    .stb_i(wbsb_stb_i),
6049
    .cti_i(wbsb_cti_i),
6050
    .bte_i(wbsb_bte_i),
6051
    .adr_i(wbsb_adr_i),
6052
    .we_i(wbsb_we_i),
6053
    .ack_o(wbsb_ack_o),
6054
    .adr_o(adr_b),
6055
    .clk(wbsb_clk),
6056
    .rst(wbsb_rst));
6057 40 unneback
`undef MODULE
6058 101 unneback
assign we_b = wbsb_we_i & wbsb_ack_o;
6059
end else if (mode=="B4") begin : b4_inst
6060
always @ (posedge wbsa_clk or posedge wbsa_rst)
6061
    if (wbsa_rst)
6062
        wbsa_ack_o <= 1'b0;
6063
    else
6064
        wbsa_ack_o <= wbsa_stb_i & wbsa_cyc_i;
6065
assign wbsa_stall_o = 1'b0;
6066
assign we_a = wbsa_we_i & wbsa_cyc_i & wbsa_stb_i;
6067
always @ (posedge wbsb_clk or posedge wbsb_rst)
6068
    if (wbsb_rst)
6069
        wbsb_ack_o <= 1'b0;
6070
    else
6071
        wbsb_ack_o <= wbsb_stb_i & wbsb_cyc_i;
6072
assign wbsb_stall_o = 1'b0;
6073
assign we_b = wbsb_we_i & wbsb_cyc_i & wbsb_stb_i;
6074
end
6075
endgenerate
6076 92 unneback
 
6077
`define MODULE dpram_be_2r2w
6078
`BASE`MODULE # ( .a_data_width(data_width_a), .a_addr_width(addr_width_a), .mem_size(mem_size))
6079
`undef MODULE
6080
ram_i (
6081 32 unneback
    .d_a(wbsa_dat_i),
6082 92 unneback
    .q_a(wbsa_dat_o),
6083
    .adr_a(adr_a),
6084
    .be_a(wbsa_sel_i),
6085 101 unneback
    .we_a(we_a),
6086 32 unneback
    .clk_a(wbsa_clk),
6087
    .d_b(wbsb_dat_i),
6088 92 unneback
    .q_b(wbsb_dat_o),
6089
    .adr_b(adr_b),
6090
    .be_b(wbsb_sel_i),
6091 101 unneback
    .we_b(we_b),
6092 32 unneback
    .clk_b(wbsb_clk) );
6093
 
6094
endmodule
6095 40 unneback
`endif
6096 94 unneback
 
6097 101 unneback
`ifdef WB_CACHE
6098
`define MODULE wb_cache
6099 97 unneback
module `BASE`MODULE (
6100 103 unneback
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i, wbs_dat_o, wbs_ack_o, wbs_stall_o, wbs_clk, wbs_rst,
6101 98 unneback
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o, wbm_dat_i, wbm_ack_i, wbm_stall_i, wbm_clk, wbm_rst
6102 97 unneback
);
6103
`undef MODULE
6104
 
6105
parameter dw_s = 32;
6106
parameter aw_s = 24;
6107
parameter dw_m = dw_s;
6108 100 unneback
localparam aw_m = dw_s * aw_s / dw_m;
6109
parameter wbs_max_burst_width = 4;
6110 103 unneback
parameter wbs_mode = "B3";
6111 97 unneback
 
6112
parameter async = 1; // wbs_clk != wbm_clk
6113
 
6114
parameter nr_of_ways = 1;
6115
parameter aw_offset = 4; // 4 => 16 words per cache line
6116
parameter aw_slot = 10;
6117 100 unneback
 
6118
parameter valid_mem = 0;
6119
parameter debug = 0;
6120
 
6121
localparam aw_b_offset = aw_offset * dw_s / dw_m;
6122 98 unneback
localparam aw_tag = aw_s - aw_slot - aw_offset;
6123 97 unneback
parameter wbm_burst_size = 4; // valid options 4,8,16
6124 98 unneback
localparam bte = (wbm_burst_size==4) ? 2'b01 : (wbm_burst_size==8) ? 2'b10 : 2'b11;
6125 97 unneback
`define SIZE2WIDTH wbm_burst_size
6126
localparam wbm_burst_width `SIZE2WIDTH_EXPR
6127
`undef SIZE2WIDTH
6128
localparam nr_of_wbm_burst = ((1<<aw_offset)/wbm_burst_size) * dw_s / dw_m;
6129
`define SIZE2WIDTH nr_of_wbm_burst
6130
localparam nr_of_wbm_burst_width `SIZE2WIDTH_EXPR
6131
`undef SIZE2WIDTH
6132 100 unneback
 
6133 97 unneback
input [dw_s-1:0] wbs_dat_i;
6134
input [aw_s-1:0] wbs_adr_i; // dont include a1,a0
6135 98 unneback
input [dw_s/8-1:0] wbs_sel_i;
6136 97 unneback
input [2:0] wbs_cti_i;
6137
input [1:0] wbs_bte_i;
6138 98 unneback
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
6139 97 unneback
output [dw_s-1:0] wbs_dat_o;
6140
output wbs_ack_o;
6141 103 unneback
output wbs_stall_o;
6142 97 unneback
input wbs_clk, wbs_rst;
6143
 
6144
output [dw_m-1:0] wbm_dat_o;
6145
output [aw_m-1:0] wbm_adr_o;
6146
output [dw_m/8-1:0] wbm_sel_o;
6147
output [2:0] wbm_cti_o;
6148
output [1:0] wbm_bte_o;
6149 98 unneback
output wbm_stb_o, wbm_cyc_o, wbm_we_o;
6150 97 unneback
input [dw_m-1:0] wbm_dat_i;
6151
input wbm_ack_i;
6152
input wbm_stall_i;
6153
input wbm_clk, wbm_rst;
6154
 
6155 100 unneback
wire valid, dirty, hit;
6156 97 unneback
wire [aw_tag-1:0] tag;
6157
wire tag_mem_we;
6158
wire [aw_tag-1:0] wbs_adr_tag;
6159
wire [aw_slot-1:0] wbs_adr_slot;
6160 98 unneback
wire [aw_offset-1:0] wbs_adr_word;
6161
wire [aw_s-1:0] wbs_adr;
6162 97 unneback
 
6163
reg [1:0] state;
6164
localparam idle = 2'h0;
6165
localparam rdwr = 2'h1;
6166
localparam push = 2'h2;
6167
localparam pull = 2'h3;
6168
wire eoc;
6169 103 unneback
wire we;
6170 97 unneback
 
6171
// cdc
6172
wire done, mem_alert, mem_done;
6173
 
6174 98 unneback
// wbm side
6175
reg [aw_m-1:0] wbm_radr;
6176
reg [aw_m-1:0] wbm_wadr;
6177 100 unneback
wire [aw_slot-1:0] wbm_adr;
6178 98 unneback
wire wbm_radr_cke, wbm_wadr_cke;
6179
 
6180 100 unneback
reg [2:0] phase;
6181
// phase = {we,stb,cyc}
6182
localparam wbm_wait     = 3'b000;
6183
localparam wbm_wr       = 3'b111;
6184
localparam wbm_wr_drain = 3'b101;
6185
localparam wbm_rd       = 3'b011;
6186
localparam wbm_rd_drain = 3'b001;
6187 98 unneback
 
6188 97 unneback
assign {wbs_adr_tag, wbs_adr_slot, wbs_adr_word} = wbs_adr_i;
6189
 
6190 100 unneback
generate
6191
if (valid_mem==0) begin : no_valid_mem
6192
assign valid = 1'b1;
6193
end else begin : valid_mem_inst
6194
`define MODULE dpram_1r1w
6195 97 unneback
`BASE`MODULE
6196 100 unneback
    # ( .data_width(1), .addr_width(aw_slot), .memory_init(2), .debug(debug))
6197
    valid_mem ( .d_a(1'b1), .adr_a(wbs_adr_slot), .we_a(mem_done), .clk_a(wbm_clk),
6198
                .q_b(valid), .adr_b(wbs_adr_slot), .clk_b(wbs_clk));
6199 97 unneback
`undef MODULE
6200 100 unneback
end
6201
endgenerate
6202 97 unneback
 
6203 100 unneback
`define MODULE dpram_1r1w
6204
`BASE`MODULE
6205
    # ( .data_width(aw_tag), .addr_width(aw_slot), .memory_init(2), .debug(debug))
6206
    tag_mem ( .d_a(wbs_adr_tag), .adr_a(wbs_adr_slot), .we_a(mem_done), .clk_a(wbm_clk),
6207
              .q_b(tag), .adr_b(wbs_adr_slot), .clk_b(wbs_clk));
6208
assign hit = wbs_adr_tag == tag;
6209
`undef MODULE
6210
 
6211
`define MODULE dpram_1r2w
6212
`BASE`MODULE
6213
    # ( .data_width(1), .addr_width(aw_slot), .memory_init(2), .debug(debug))
6214
    dirty_mem (
6215
        .d_a(1'b1), .q_a(dirty), .adr_a(wbs_adr_slot), .we_a(wbs_cyc_i & wbs_we_i & wbs_ack_o), .clk_a(wbs_clk),
6216
        .d_b(1'b0), .adr_b(wbs_adr_slot), .we_b(mem_done), .clk_b(wbm_clk));
6217
`undef MODULE
6218
 
6219 103 unneback
generate
6220
if (wbs_mode=="B3") begin : inst_b3
6221 97 unneback
`define MODULE wb_adr_inc
6222 100 unneback
`BASE`MODULE # ( .adr_width(aw_s), .max_burst_width(wbs_max_burst_width)) adr_inc0 (
6223
    .cyc_i(wbs_cyc_i & (state==rdwr) & hit & valid),
6224
    .stb_i(wbs_stb_i & (state==rdwr) & hit & valid), // throttle depending on valid
6225 97 unneback
    .cti_i(wbs_cti_i),
6226
    .bte_i(wbs_bte_i),
6227
    .adr_i(wbs_adr_i),
6228
    .we_i (wbs_we_i),
6229
    .ack_o(wbs_ack_o),
6230
    .adr_o(wbs_adr),
6231 100 unneback
    .clk(wbs_clk),
6232
    .rst(wbs_rst));
6233 97 unneback
`undef MODULE
6234 103 unneback
assign eoc = (wbs_cti_i==3'b000 | wbs_cti_i==3'b111) & wbs_ack_o;
6235
assign we = wbs_cyc_i &  wbs_we_i & wbs_ack_o;
6236
end else if (wbs_mode=="B4") begin : inst_b4
6237
end
6238 97 unneback
 
6239 103 unneback
endgenerate
6240
 
6241 97 unneback
`define MODULE dpram_be_2r2w
6242
`BASE`MODULE
6243 100 unneback
    # ( .a_data_width(dw_s), .a_addr_width(aw_slot+aw_offset), .b_data_width(dw_m), .debug(debug))
6244 103 unneback
    cache_mem ( .d_a(wbs_dat_i), .adr_a(wbs_adr[aw_slot+aw_offset-1:0]),   .be_a(wbs_sel_i), .we_a(we), .q_a(wbs_dat_o), .clk_a(wbs_clk),
6245 100 unneback
                .d_b(wbm_dat_i), .adr_b(wbm_adr_o[aw_slot+aw_offset-1:0]), .be_b(wbm_sel_o), .we_b(wbm_cyc_o & !wbm_we_o & wbs_ack_i), .q_b(wbm_dat_o), .clk_b(wbm_clk));
6246 97 unneback
`undef MODULE
6247
 
6248
always @ (posedge wbs_clk or posedge wbs_rst)
6249
if (wbs_rst)
6250 98 unneback
    state <= idle;
6251 97 unneback
else
6252
    case (state)
6253
    idle:
6254
        if (wbs_cyc_i)
6255
            state <= rdwr;
6256
    rdwr:
6257 100 unneback
        casex ({valid, hit, dirty, eoc})
6258
        4'b0xxx: state <= pull;
6259
        4'b11x1: state <= idle;
6260
        4'b101x: state <= push;
6261
        4'b100x: state <= pull;
6262
        endcase
6263 97 unneback
    push:
6264
        if (done)
6265
            state <= rdwr;
6266
    pull:
6267
        if (done)
6268
            state <= rdwr;
6269
    default: state <= idle;
6270
    endcase
6271
 
6272
// cdc
6273
generate
6274
if (async==1) begin : cdc0
6275
`define MODULE cdc
6276 100 unneback
`BASE`MODULE cdc0 ( .start_pl(state==rdwr & (!valid | !hit)), .take_it_pl(mem_alert), .take_it_grant_pl(mem_done), .got_it_pl(done), .clk_src(wbs_clk), .rst_src(wbs_rst), .clk_dst(wbm_clk), .rst_dst(wbm_rst));
6277 97 unneback
`undef MODULE
6278
end
6279
else begin : nocdc
6280 100 unneback
    assign mem_alert = state==rdwr & (!valid | !hit);
6281 97 unneback
    assign done = mem_done;
6282
end
6283
endgenerate
6284
 
6285
// FSM generating a number of burts 4 cycles
6286
// actual number depends on data width ratio
6287
// nr_of_wbm_burst
6288 101 unneback
reg [nr_of_wbm_burst_width+wbm_burst_width-1:0]       cnt_rw, cnt_ack;
6289 97 unneback
 
6290
always @ (posedge wbm_clk or posedge wbm_rst)
6291
if (wbm_rst)
6292 100 unneback
    cnt_rw <= {wbm_burst_width{1'b0}};
6293 97 unneback
else
6294 100 unneback
    if (wbm_cyc_o & wbm_stb_o & !wbm_stall_i)
6295
        cnt_rw <= cnt_rw + 1;
6296 97 unneback
 
6297 98 unneback
always @ (posedge wbm_clk or posedge wbm_rst)
6298
if (wbm_rst)
6299 100 unneback
    cnt_ack <= {wbm_burst_width{1'b0}};
6300 98 unneback
else
6301 100 unneback
    if (wbm_ack_i)
6302
        cnt_ack <= cnt_ack + 1;
6303 97 unneback
 
6304 100 unneback
generate
6305 101 unneback
if (nr_of_wbm_burst==1) begin : one_burst
6306 100 unneback
 
6307 98 unneback
always @ (posedge wbm_clk or posedge wbm_rst)
6308
if (wbm_rst)
6309
    phase <= wbm_wait;
6310
else
6311
    case (phase)
6312
    wbm_wait:
6313
        if (mem_alert)
6314 100 unneback
            if (state==push)
6315
                phase <= wbm_wr;
6316
            else
6317
                phase <= wbm_rd;
6318 98 unneback
    wbm_wr:
6319 100 unneback
        if (&cnt_rw)
6320
            phase <= wbm_wr_drain;
6321
    wbm_wr_drain:
6322
        if (&cnt_ack)
6323 98 unneback
            phase <= wbm_rd;
6324
    wbm_rd:
6325 100 unneback
        if (&cnt_rw)
6326
            phase <= wbm_rd_drain;
6327
    wbm_rd_drain:
6328
        if (&cnt_ack)
6329
            phase <= wbm_wait;
6330 98 unneback
    default: phase <= wbm_wait;
6331
    endcase
6332
 
6333 100 unneback
end else begin : multiple_burst
6334
 
6335 101 unneback
always @ (posedge wbm_clk or posedge wbm_rst)
6336
if (wbm_rst)
6337
    phase <= wbm_wait;
6338
else
6339
    case (phase)
6340
    wbm_wait:
6341
        if (mem_alert)
6342
            if (state==push)
6343
                phase <= wbm_wr;
6344
            else
6345
                phase <= wbm_rd;
6346
    wbm_wr:
6347
        if (&cnt_rw[wbm_burst_width-1:0])
6348
            phase <= wbm_wr_drain;
6349
    wbm_wr_drain:
6350
        if (&cnt_ack)
6351
            phase <= wbm_rd;
6352
        else if (&cnt_ack[wbm_burst_width-1:0])
6353
            phase <= wbm_wr;
6354
    wbm_rd:
6355
        if (&cnt_rw[wbm_burst_width-1:0])
6356
            phase <= wbm_rd_drain;
6357
    wbm_rd_drain:
6358
        if (&cnt_ack)
6359
            phase <= wbm_wait;
6360
        else if (&cnt_ack[wbm_burst_width-1:0])
6361
            phase <= wbm_rd;
6362
    default: phase <= wbm_wait;
6363
    endcase
6364 100 unneback
 
6365 101 unneback
 
6366 100 unneback
end
6367
endgenerate
6368
 
6369 101 unneback
assign mem_done = phase==wbm_rd_drain & (&cnt_ack) & wbm_ack_i;
6370 100 unneback
 
6371
assign wbm_adr_o = (phase[2]) ? {tag, wbs_adr_slot, cnt_rw} : {wbs_adr_tag, wbs_adr_slot, cnt_rw};
6372
assign wbm_adr   = (phase[2]) ? {wbs_adr_slot, cnt_rw} : {wbs_adr_slot, cnt_rw};
6373
assign wbm_sel_o = {dw_m/8{1'b1}};
6374
assign wbm_cti_o = (&cnt_rw | !wbm_stb_o) ? 3'b111 : 3'b010;
6375 98 unneback
assign wbm_bte_o = bte;
6376 100 unneback
assign {wbm_we_o, wbm_stb_o, wbm_cyc_o}  = phase;
6377 98 unneback
 
6378 97 unneback
endmodule
6379
`endif
6380 103 unneback
 
6381
`ifdef WB_AVALON_BRIDGE
6382
// Wishbone to avalon bridge supporting one type of burst transfer only
6383
// intended use is together with cache above
6384
// WB B4 -> pipelined avalon
6385
`define MODULE wb_avalon_bridge
6386
module `BASE`MODULE (
6387
`undef MODULE
6388
        // wishbone slave side
6389
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_stall_o,
6390
        // avalon master side
6391
        readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer,
6392
        // common
6393
        clk, rst);
6394
 
6395
parameter adr_width = 30;
6396
parameter dat_width = 32;
6397
parameter burst_size = 4;
6398
 
6399
input [dat_width-1:0] wbs_dat_i;
6400
input [adr_width-1:0] wbs_adr_i;
6401
input [dat_width/8-1:0]  wbs_sel_i;
6402
input [1:0]  wbs_bte_i;
6403
input [2:0]  wbs_cti_i;
6404
input wbs_we_i;
6405
input wbs_cyc_i;
6406
input wbs_stb_i;
6407
output [dat_width:0] wbs_dat_o;
6408
output wbs_ack_o;
6409
output wbs_stall_o;
6410
 
6411
input [dat_width-1:0] readdata;
6412
input readdatavalid;
6413
output [dat_width-1:0] writedata;
6414
output [adr_width-1:0] address;
6415
output [dat_width/8-1:0]  be;
6416
output write;
6417
output read;
6418
output beginbursttransfer;
6419
output [3:0] burstcount;
6420
input waitrequest;
6421
input clk, rst;
6422
 
6423
reg last_cyc_idle_or_eoc;
6424
 
6425
reg [3:0] cnt;
6426
always @ (posedge clk or posedge rst)
6427
if (rst)
6428
    cnt <= 4'h0;
6429
else
6430
    if (beginbursttransfer & waitrequest)
6431
        cnt <= burst_size - 1;
6432
    else if (beginbursttransfer & !waitrequest)
6433
        cnt <= burst_size - 2;
6434
    else if (wbs_ack_o)
6435
        cnt <= cnt - 1;
6436
 
6437
reg wr_ack;
6438
always @ (posedge clk or posedge rst)
6439
if (rst)
6440
    wr_ack <= 1'b0;
6441
else
6442
    wr_ack <=  (wbs_we_i & wbs_cyc_i & wbs_stb_i & !wbs_stall_o);
6443
 
6444
// to avalon
6445
assign writedata = wbs_dat_i;
6446
assign address = wbs_adr_i;
6447
assign be = wbs_sel_i;
6448
assign write = cnt==(burst_size-1) & wbs_cyc_i &  wbs_we_i;
6449
assign read  = cnt==(burst_size-1) & wbs_cyc_i & !wbs_we_i;
6450
assign beginbursttransfer = cnt==4'h0 & wbs_cyc_i;
6451
assign burstcount = burst_size;
6452
 
6453
// to wishbone
6454
assign wbs_dat_o = readdata;
6455
assign wbs_ack_o = wr_ack | readdatavalid;
6456
assign wbs_stall_o = waitrequest;
6457
 
6458
endmodule
6459
`endif
6460
 
6461
`ifdef WB_AVALON_MEM_CACHE
6462
`define MODULE wb_avalon_mem_cache
6463
module `BASE`MODULE (
6464
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i, wbs_dat_o, wbs_ack_o, wbs_stall_o, wbs_clk, wbs_rst,
6465
    readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst
6466
);
6467
`undef MODULE
6468
 
6469
// wishbone
6470
parameter wb_dat_width = 32;
6471
parameter wb_adr_width = 22;
6472
parameter wb_max_burst_width = 4;
6473
parameter wb_mode = "B4";
6474
// avalon
6475
parameter avalon_dat_width = 32;
6476
localparam avalon_adr_width = wb_dat_width * wb_adr_width / avalon_dat_width;
6477
parameter avalon_burst_size = 4;
6478
// cache
6479
parameter async = 1;
6480
parameter nr_of_ways = 1;
6481
parameter aw_offset = 4;
6482
parameter aw_slot = 10;
6483
parameter valid_mem = 1;
6484
// shadow RAM
6485
parameter shadow_ram = 0;
6486
parameter shadow_ram_adr_width = 10;
6487
parameter shadow_ram_size = 1024;
6488
parameter shadow_ram_init = 2; // 0: no init, 1: from file, 2: with zero
6489
parameter shadow_ram_file = "vl_ram.v";
6490
 
6491
input [wb_dat_width-1:0] wbs_dat_i;
6492
input [wb_adr_width-1:0] wbs_adr_i; // dont include a1,a0
6493
input [wb_dat_width/8-1:0] wbs_sel_i;
6494
input [2:0] wbs_cti_i;
6495
input [1:0] wbs_bte_i;
6496
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
6497
output [wb_dat_width-1:0] wbs_dat_o;
6498
output wbs_ack_o;
6499
output wbs_stall_o;
6500
input wbs_clk, wbs_rst;
6501
 
6502
input [avalon_dat_width-1:0] readdata;
6503
input readdatavalid;
6504
output [avalon_dat_width-1:0] writedata;
6505
output [avalon_adr_width-1:0] address;
6506
output [avalon_dat_width/8-1:0]  be;
6507
output write;
6508
output read;
6509
output beginbursttransfer;
6510
output [3:0] burstcount;
6511
input waitrequest;
6512
input clk, rst;
6513
 
6514
`define DAT_WIDTH wb_dat_width
6515
`define ADR_WIDTH wb_adr_width
6516
`define WB wb1
6517
`include "wb_wires.v"
6518
`define WB wb2
6519
`include "wb_wires.v"
6520
`undef DAT_WIDTH
6521
`undef ADR_WIDTH
6522
 
6523
`define MODULE wb_shadow_ram
6524
`BASE`MODULE # ( .dat_width(wb_dat_width), .mode(wb_mode), .max_burst_width(wb_max_burst_width),
6525
                 .shadow_mem_adr_width(shadow_ram_adr_width), .shadow_mem_size(shadow_ram_adr_width), .shadow_mem_init(shadow_ram_init), .shadow_mem_file(shadow_ram_file),
6526
                 .main_mem_adr_width(wb_adr_width))
6527
shadow_ram0 (
6528
    .wbs_dat_i(wbs_dat_i), .wbs_adr_i(wbs_adr_i), .wbs_cti_i(wbs_cti_i), .wbs_bte_i(wbs_bte_i), .wbs_sel_i(wbs_sel_i), .wbs_we_i(wbs_we_i), .wbs_stb_i(wbs_stb_i), .wbs_cyc_i(wbs_cyc_i),
6529
    .wbs_dat_o(wbs_dat_o), .wbs_ack_o(wbs_ack_o), .wbs_stall_o(wbs_stall_o),
6530
    .wbm_dat_o(wb1_dat_o), .wbm_adr_o(wb1_adr_o), .wbm_cti_o(wb1_cti_o), .wbm_bte_o(wb1_bte_o), .wbm_sel_o(wb1_sel_o), .wbm_we_o(wb1_we_o), .wbm_stb_o(wb1_stb_o), .wbm_cyc_o(wb1_cyc_o),
6531
    .wbm_dat_i(wb1_dat_i), .wbm_ack_i(wb1_ack_i), .wbm_stall_i(wb1_stall_i),
6532
    .wb_clk(wbs_clk), .wb_rst(wbs_rst));
6533
`undef MODULE
6534
 
6535
`define MODULE wb_cache
6536
`BASE`MODULE
6537
# ( .dw_s(wb_dat_width), .aw_s(wb_adr_width), .dw_m(avalon_dat_width), .wbs_mode(wb_mode), .wbs_max_burst_width(wb_max_burst_width), .async(async), .nr_of_ways(nr_of_ways), .aw_offset(aw_offset), .aw_slot(aw_slot), .valid_mem(valid_mem))
6538
cache0 (
6539
    .wbs_dat_i(wb1_dat_o), .wbs_adr_i(wb1_adr_o), .wbs_sel_i(wb1_sel_o), .wbs_cti_i(wb1_cti_o), .wbs_bte_i(wb1_bte_o), .wbs_we_i(wb1_we_o), .wbs_stb_i(wb1_stb_o), .wbs_cyc_i(wb1_cyc_o),
6540
    .wbs_dat_o(wb1_dat_i), .wbs_ack_o(wb1_ack_i), .wbs_stall_o(wb1_stall_i), .wbs_clk(wbs_clk), .wbs_rst(wbs_rst),
6541
    .wbm_dat_o(wb2_dat_o), .wbm_adr_o(wb2_adr_o), .wbm_sel_o(wb2_sel_o), .wbm_cti_o(wb2_cti_o), .wbm_bte_o(wb2_bte_o), .wbm_we_o(wb2_we_o), .wbm_stb_o(wb2_stb_o), .wbm_cyc_o(wb2_cyc_o),
6542
    .wbm_dat_i(wb2_dat_i), .wbm_ack_i(wb2_ack_i), .wbm_stall_i(wb2_stall_i), .wbm_clk(clk), .wbm_rst(rst));
6543
`undef MODULE
6544
 
6545
`define MODULE wb_avalon_bridge
6546
`BASE`MODULE # ( .adr_width(avalon_adr_width), .dat_width(avalon_dat_width), .burst_size(avalon_burst_size))
6547
bridge0 (
6548
        // wishbone slave side
6549
        .wbs_dat_i(wb2_dat_o), .wbs_adr_i(wb2_adr_o), .wbs_sel_i(wb2_sel_o), .wbs_bte_i(wb2_bte_o), .wbs_cti_i(wb2_cti_o), .wbs_we_i(wb2_we_o), .wbs_cyc_i(wb2_cyc_o), .wbs_stb_i(wb2_stb_o),
6550
        .wbs_dat_o(wb2_dat_i), .wbs_ack_o(wb2_ack_i), .wbs_stall_o(wb2_stall_i),
6551
        // avalon master side
6552
        .readdata(readdata), .readdatavalid(readdatavalid), .address(address), .read(read), .be(be), .write(write), .burstcount(burstcount), .writedata(writedata), .waitrequest(waitrequest), .beginbursttransfer(beginbursttransfer),
6553
        // common
6554
        .clk(clk), .rst(rst));
6555
`undef MODULE
6556
 
6557
endmodule
6558
`endif
6559 18 unneback
//////////////////////////////////////////////////////////////////////
6560
////                                                              ////
6561
////  Arithmetic functions                                        ////
6562
////                                                              ////
6563
////  Description                                                 ////
6564
////  Arithmetic functions for ALU and DSP                        ////
6565
////                                                              ////
6566
////                                                              ////
6567
////  To Do:                                                      ////
6568
////   -                                                          ////
6569
////                                                              ////
6570
////  Author(s):                                                  ////
6571
////      - Michael Unneback, unneback@opencores.org              ////
6572
////        ORSoC AB                                              ////
6573
////                                                              ////
6574
//////////////////////////////////////////////////////////////////////
6575
////                                                              ////
6576
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
6577
////                                                              ////
6578
//// This source file may be used and distributed without         ////
6579
//// restriction provided that this copyright statement is not    ////
6580
//// removed from the file and that any derivative work contains  ////
6581
//// the original copyright notice and the associated disclaimer. ////
6582
////                                                              ////
6583
//// This source file is free software; you can redistribute it   ////
6584
//// and/or modify it under the terms of the GNU Lesser General   ////
6585
//// Public License as published by the Free Software Foundation; ////
6586
//// either version 2.1 of the License, or (at your option) any   ////
6587
//// later version.                                               ////
6588
////                                                              ////
6589
//// This source is distributed in the hope that it will be       ////
6590
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
6591
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
6592
//// PURPOSE.  See the GNU Lesser General Public License for more ////
6593
//// details.                                                     ////
6594
////                                                              ////
6595
//// You should have received a copy of the GNU Lesser General    ////
6596
//// Public License along with this source; if not, download it   ////
6597
//// from http://www.opencores.org/lgpl.shtml                     ////
6598
////                                                              ////
6599
//////////////////////////////////////////////////////////////////////
6600
 
6601 40 unneback
`ifdef MULTS
6602 18 unneback
// signed multiplication
6603 40 unneback
`define MODULE mults
6604
module `BASE`MODULE (a,b,p);
6605
`undef MODULE
6606 18 unneback
parameter operand_a_width = 18;
6607
parameter operand_b_width = 18;
6608
parameter result_hi = 35;
6609
parameter result_lo = 0;
6610
input [operand_a_width-1:0] a;
6611
input [operand_b_width-1:0] b;
6612
output [result_hi:result_lo] p;
6613
wire signed [operand_a_width-1:0] ai;
6614
wire signed [operand_b_width-1:0] bi;
6615
wire signed [operand_a_width+operand_b_width-1:0] result;
6616
 
6617
    assign ai = a;
6618
    assign bi = b;
6619
    assign result = ai * bi;
6620
    assign p = result[result_hi:result_lo];
6621
 
6622
endmodule
6623 40 unneback
`endif
6624
`ifdef MULTS18X18
6625
`define MODULE mults18x18
6626
module `BASE`MODULE (a,b,p);
6627
`undef MODULE
6628 18 unneback
input [17:0] a,b;
6629
output [35:0] p;
6630
vl_mult
6631
    # (.operand_a_width(18), .operand_b_width(18))
6632
    mult0 (.a(a), .b(b), .p(p));
6633
endmodule
6634 40 unneback
`endif
6635 18 unneback
 
6636 40 unneback
`ifdef MULT
6637
`define MODULE mult
6638 18 unneback
// unsigned multiplication
6639 40 unneback
module `BASE`MODULE (a,b,p);
6640
`undef MODULE
6641 18 unneback
parameter operand_a_width = 18;
6642
parameter operand_b_width = 18;
6643
parameter result_hi = 35;
6644
parameter result_lo = 0;
6645
input [operand_a_width-1:0] a;
6646
input [operand_b_width-1:0] b;
6647
output [result_hi:result_hi] p;
6648
 
6649
wire [operand_a_width+operand_b_width-1:0] result;
6650
 
6651
    assign result = a * b;
6652
    assign p = result[result_hi:result_lo];
6653
 
6654
endmodule
6655 40 unneback
`endif
6656 18 unneback
 
6657 40 unneback
`ifdef SHIFT_UNIT_32
6658
`define MODULE shift_unit_32
6659 18 unneback
// shift unit
6660
// supporting the following shift functions
6661
//   SLL
6662
//   SRL
6663
//   SRA
6664
`define SHIFT_UNIT_MULT # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7))
6665 40 unneback
module `BASE`MODULE( din, s, dout, opcode);
6666
`undef MODULE
6667 18 unneback
input [31:0] din; // data in operand
6668
input [4:0] s; // shift operand
6669
input [1:0] opcode;
6670
output [31:0] dout;
6671
 
6672
parameter opcode_sll = 2'b00;
6673
//parameter opcode_srl = 2'b01;
6674
parameter opcode_sra = 2'b10;
6675
//parameter opcode_ror = 2'b11;
6676
 
6677
wire sll, sra;
6678
assign sll = opcode == opcode_sll;
6679
assign sra = opcode == opcode_sra;
6680
 
6681
wire [15:1] s1;
6682
wire [3:0] sign;
6683
wire [7:0] tmp [0:3];
6684
 
6685
// first stage is multiplier based
6686
// shift operand as fractional 8.7
6687
assign s1[15] = sll & s[2:0]==3'd7;
6688
assign s1[14] = sll & s[2:0]==3'd6;
6689
assign s1[13] = sll & s[2:0]==3'd5;
6690
assign s1[12] = sll & s[2:0]==3'd4;
6691
assign s1[11] = sll & s[2:0]==3'd3;
6692
assign s1[10] = sll & s[2:0]==3'd2;
6693
assign s1[ 9] = sll & s[2:0]==3'd1;
6694
assign s1[ 8] = s[2:0]==3'd0;
6695
assign s1[ 7] = !sll & s[2:0]==3'd1;
6696
assign s1[ 6] = !sll & s[2:0]==3'd2;
6697
assign s1[ 5] = !sll & s[2:0]==3'd3;
6698
assign s1[ 4] = !sll & s[2:0]==3'd4;
6699
assign s1[ 3] = !sll & s[2:0]==3'd5;
6700
assign s1[ 2] = !sll & s[2:0]==3'd6;
6701
assign s1[ 1] = !sll & s[2:0]==3'd7;
6702
 
6703
assign sign[3] = din[31] & sra;
6704
assign sign[2] = sign[3] & (&din[31:24]);
6705
assign sign[1] = sign[2] & (&din[23:16]);
6706
assign sign[0] = sign[1] & (&din[15:8]);
6707 40 unneback
`define MODULE mults
6708
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte3 ( .a({sign[3], {8{sign[3]}},din[31:24], din[23:16]}), .b({1'b0,s1}), .p(tmp[3]));
6709
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte2 ( .a({sign[2], din[31:24]  ,din[23:16],  din[15:8]}), .b({1'b0,s1}), .p(tmp[2]));
6710
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte1 ( .a({sign[1], din[23:16]  ,din[15:8],   din[7:0]}), .b({1'b0,s1}), .p(tmp[1]));
6711
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte0 ( .a({sign[0], din[15:8]   ,din[7:0],    8'h00}),      .b({1'b0,s1}), .p(tmp[0]));
6712
`undef MODULE
6713 18 unneback
// second stage is multiplexer based
6714
// shift on byte level
6715
 
6716
// mux byte 3
6717
assign dout[31:24] = (s[4:3]==2'b00) ? tmp[3] :
6718
                     (sll & s[4:3]==2'b01) ? tmp[2] :
6719
                     (sll & s[4:3]==2'b10) ? tmp[1] :
6720
                     (sll & s[4:3]==2'b11) ? tmp[0] :
6721
                     {8{sign[3]}};
6722
 
6723
// mux byte 2
6724
assign dout[23:16] = (s[4:3]==2'b00) ? tmp[2] :
6725
                     (sll & s[4:3]==2'b01) ? tmp[1] :
6726
                     (sll & s[4:3]==2'b10) ? tmp[0] :
6727
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
6728
                     (s[4:3]==2'b01) ? tmp[3] :
6729
                     {8{sign[3]}};
6730
 
6731
// mux byte 1
6732
assign dout[15:8]  = (s[4:3]==2'b00) ? tmp[1] :
6733
                     (sll & s[4:3]==2'b01) ? tmp[0] :
6734
                     (sll & s[4:3]==2'b10) ? {8{1'b0}} :
6735
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
6736
                     (s[4:3]==2'b01) ? tmp[2] :
6737
                     (s[4:3]==2'b10) ? tmp[3] :
6738
                     {8{sign[3]}};
6739
 
6740
// mux byte 0
6741
assign dout[7:0]   = (s[4:3]==2'b00) ? tmp[0] :
6742
                     (sll) ?  {8{1'b0}}:
6743
                     (s[4:3]==2'b01) ? tmp[1] :
6744
                     (s[4:3]==2'b10) ? tmp[2] :
6745
                     tmp[3];
6746
 
6747
endmodule
6748 40 unneback
`endif
6749 18 unneback
 
6750 40 unneback
`ifdef LOGIC_UNIT
6751 18 unneback
// logic unit
6752
// supporting the following logic functions
6753
//    a and b
6754
//    a or  b
6755
//    a xor b
6756
//    not b
6757 40 unneback
`define MODULE logic_unit
6758
module `BASE`MODULE( a, b, result, opcode);
6759
`undef MODULE
6760 18 unneback
parameter width = 32;
6761
parameter opcode_and = 2'b00;
6762
parameter opcode_or  = 2'b01;
6763
parameter opcode_xor = 2'b10;
6764
input [width-1:0] a,b;
6765
output [width-1:0] result;
6766
input [1:0] opcode;
6767
 
6768
assign result = (opcode==opcode_and) ? a & b :
6769
                (opcode==opcode_or)  ? a | b :
6770
                (opcode==opcode_xor) ? a ^ b :
6771
                b;
6772
 
6773
endmodule
6774 48 unneback
`endif
6775 18 unneback
 
6776 48 unneback
`ifdef ARITH_UNIT
6777
`define MODULE arith_unit
6778
module `BASE`MODULE ( a, b, c_in, add_sub, sign, result, c_out, z, ovfl);
6779
`undef MODULE
6780 18 unneback
parameter width = 32;
6781
parameter opcode_add = 1'b0;
6782
parameter opcode_sub = 1'b1;
6783
input [width-1:0] a,b;
6784
input c_in, add_sub, sign;
6785
output [width-1:0] result;
6786
output c_out, z, ovfl;
6787
 
6788
assign {c_out,result} = {(a[width-1] & sign),a} + ({a[width-1] & sign,b} ^ {(width+1){(add_sub==opcode_sub)}}) + {{(width-1){1'b0}},(c_in | (add_sub==opcode_sub))};
6789
assign z = (result=={width{1'b0}});
6790
assign ovfl = ( a[width-1] &  b[width-1] & ~result[width-1]) |
6791
               (~a[width-1] & ~b[width-1] &  result[width-1]);
6792
endmodule
6793 40 unneback
`endif
6794 48 unneback
 
6795
`ifdef COUNT_UNIT
6796
`define MODULE count_unit
6797
module `BASE`MODULE (din, dout, opcode);
6798
`undef MODULE
6799
parameter width = 32;
6800
input [width-1:0] din;
6801
output [width-1:0] dout;
6802
input opcode;
6803
 
6804
integer i;
6805 58 unneback
wire [width/32+4:0] ff1, fl1;
6806 48 unneback
 
6807 57 unneback
/*
6808 48 unneback
always @(din) begin
6809
    ff1 = 0; i = 0;
6810
    while (din[i] == 0 && i < width) begin // complex condition
6811
        ff1 = ff1 + 1;
6812
        i = i + 1;
6813
    end
6814
end
6815
 
6816
always @(din) begin
6817
    fl1 = width; i = width-1;
6818
    while (din[i] == 0 && i >= width) begin // complex condition
6819
        fl1 = fl1 - 1;
6820
        i = i - 1;
6821
    end
6822
end
6823 57 unneback
*/
6824 48 unneback
 
6825
generate
6826
if (width==32) begin
6827 57 unneback
 
6828
    assign ff1 = din[0] ? 6'd1 :
6829
                 din[1] ? 6'd2 :
6830
                 din[2] ? 6'd3 :
6831
                 din[3] ? 6'd4 :
6832
                 din[4] ? 6'd5 :
6833
                 din[5] ? 6'd6 :
6834
                 din[6] ? 6'd7 :
6835
                 din[7] ? 6'd8 :
6836
                 din[8] ? 6'd9 :
6837
                 din[9] ? 6'd10 :
6838
                 din[10] ? 6'd11 :
6839
                 din[11] ? 6'd12 :
6840
                 din[12] ? 6'd13 :
6841
                 din[13] ? 6'd14 :
6842
                 din[14] ? 6'd15 :
6843
                 din[15] ? 6'd16 :
6844
                 din[16] ? 6'd17 :
6845
                 din[17] ? 6'd18 :
6846
                 din[18] ? 6'd19 :
6847
                 din[19] ? 6'd20 :
6848
                 din[20] ? 6'd21 :
6849
                 din[21] ? 6'd22 :
6850
                 din[22] ? 6'd23 :
6851
                 din[23] ? 6'd24 :
6852
                 din[24] ? 6'd25 :
6853
                 din[25] ? 6'd26 :
6854
                 din[26] ? 6'd27 :
6855
                 din[27] ? 6'd28 :
6856
                 din[28] ? 6'd29 :
6857
                 din[29] ? 6'd30 :
6858
                 din[30] ? 6'd31 :
6859
                 din[31] ? 6'd32 :
6860
                 6'd0;
6861
 
6862
    assign fl1 = din[31] ? 6'd32 :
6863
                 din[30] ? 6'd31 :
6864
                 din[29] ? 6'd30 :
6865
                 din[28] ? 6'd29 :
6866
                 din[27] ? 6'd28 :
6867
                 din[26] ? 6'd27 :
6868
                 din[25] ? 6'd26 :
6869
                 din[24] ? 6'd25 :
6870
                 din[23] ? 6'd24 :
6871
                 din[22] ? 6'd23 :
6872
                 din[21] ? 6'd22 :
6873
                 din[20] ? 6'd21 :
6874
                 din[19] ? 6'd20 :
6875
                 din[18] ? 6'd19 :
6876
                 din[17] ? 6'd18 :
6877
                 din[16] ? 6'd17 :
6878
                 din[15] ? 6'd16 :
6879
                 din[14] ? 6'd15 :
6880
                 din[13] ? 6'd14 :
6881
                 din[12] ? 6'd13 :
6882
                 din[11] ? 6'd12 :
6883
                 din[10] ? 6'd11 :
6884
                 din[9] ? 6'd10 :
6885
                 din[8] ? 6'd9 :
6886
                 din[7] ? 6'd8 :
6887
                 din[6] ? 6'd7 :
6888
                 din[5] ? 6'd6 :
6889
                 din[4] ? 6'd5 :
6890
                 din[3] ? 6'd4 :
6891
                 din[2] ? 6'd3 :
6892
                 din[1] ? 6'd2 :
6893
                 din[0] ? 6'd1 :
6894
                 6'd0;
6895
 
6896
    assign dout = (!opcode) ? {{26{1'b0}}, ff1} : {{26{1'b0}}, fl1};
6897 48 unneback
end
6898
endgenerate
6899 57 unneback
 
6900 48 unneback
generate
6901
if (width==64) begin
6902 57 unneback
    assign ff1 = 7'd0;
6903
    assign fl1 = 7'd0;
6904
    assign dout = (!opcode) ? {{57{1'b0}}, ff1} : {{57{1'b0}}, fl1};
6905 48 unneback
end
6906
endgenerate
6907
 
6908
endmodule
6909
`endif
6910
 
6911
`ifdef EXT_UNIT
6912
`define MODULE ext_unit
6913
module `BASE`MODULE ( a, b, F, result, opcode);
6914
`undef MODULE
6915
parameter width = 32;
6916
input [width-1:0] a, b;
6917
input F;
6918
output reg [width-1:0] result;
6919
input [2:0] opcode;
6920
 
6921
generate
6922
if (width==32) begin
6923
always @ (a or b or F or opcode)
6924
begin
6925
    case (opcode)
6926
    3'b000: result = {{24{1'b0}},a[7:0]};
6927
    3'b001: result = {{24{a[7]}},a[7:0]};
6928
    3'b010: result = {{16{1'b0}},a[7:0]};
6929
    3'b011: result = {{16{a[15]}},a[15:0]};
6930
    3'b110: result = (F) ? a : b;
6931
    default: result = {b[15:0],16'h0000};
6932
    endcase
6933
end
6934
end
6935
endgenerate
6936
 
6937
generate
6938
if (width==64) begin
6939
always @ (a or b or F or opcode)
6940
begin
6941
    case (opcode)
6942
    3'b000: result = {{56{1'b0}},a[7:0]};
6943
    3'b001: result = {{56{a[7]}},a[7:0]};
6944
    3'b010: result = {{48{1'b0}},a[7:0]};
6945
    3'b011: result = {{48{a[15]}},a[15:0]};
6946 57 unneback
    3'b110: result = (F) ? a : b;
6947 48 unneback
    default: result = {32'h00000000,b[15:0],16'h0000};
6948
    endcase
6949
end
6950
end
6951
endgenerate
6952
endmodule
6953
`endif

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