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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Blame information for rev 110

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Line No. Rev Author Line
1 40 unneback
`ifndef BASE
2
`define BASE vl_
3
`endif
4
 
5 60 unneback
// default SYN_KEEP definition
6
`define SYN_KEEP /*synthesis syn_keep = 1*/
7
 
8 44 unneback
`ifdef ACTEL
9 60 unneback
`undef SYN_KEEP
10 44 unneback
`define SYN_KEEP /*synthesis syn_keep = 1*/
11
`endif
12
 
13 98 unneback
`ifdef ACTEL
14
    // ACTEL FPGA should not use logic to handle rw collision
15
    `define SYN_NO_RW_CHECK /*synthesis syn_ramstyle = "no_rw_check"*/
16
`else
17
    `define SYN_NO_RW_CHECK
18
`endif
19
 
20 40 unneback
`ifdef ALL
21
 
22
`define GBUF
23
`define SYNC_RST
24
`define PLL
25
 
26
`define MULTS
27
`define MULTS18X18
28
`define MULT
29
`define SHIFT_UNIT_32
30
`define LOGIC_UNIT
31
 
32
`define CNT_SHREG_WRAP
33
`define CNT_SHREG_CE_WRAP
34 105 unneback
`define CNT_SHREG_CLEAR
35 40 unneback
`define CNT_SHREG_CE_CLEAR
36
`define CNT_SHREG_CE_CLEAR_WRAP
37
 
38
`define MUX_ANDOR
39
`define MUX2_ANDOR
40
`define MUX3_ANDOR
41
`define MUX4_ANDOR
42
`define MUX5_ANDOR
43
`define MUX6_ANDOR
44 43 unneback
`define PARITY
45 40 unneback
 
46
`define ROM_INIT
47
`define RAM
48
`define RAM_BE
49
`define DPRAM_1R1W
50
`define DPRAM_2R1W
51 100 unneback
`define DPRAM_1R2W
52 40 unneback
`define DPRAM_2R2W
53 75 unneback
`define DPRAM_BE_2R2W
54 40 unneback
`define FIFO_1R1W_FILL_LEVEL_SYNC
55
`define FIFO_2R2W_SYNC_SIMPLEX
56
`define FIFO_CMP_ASYNC
57
`define FIFO_1R1W_ASYNC
58
`define FIFO_2R2W_ASYNC
59
`define FIFO_2R2W_ASYNC_SIMPLEX
60 48 unneback
`define REG_FILE
61 40 unneback
 
62
`define DFF
63
`define DFF_ARRAY
64
`define DFF_CE
65
`define DFF_CE_CLEAR
66
`define DF_CE_SET
67
`define SPR
68
`define SRP
69
`define DFF_SR
70
`define LATCH
71
`define SHREG
72
`define SHREG_CE
73
`define DELAY
74
`define DELAY_EMPTYFLAG
75 94 unneback
`define PULSE2TOGGLE
76
`define TOGGLE2PULSE
77
`define SYNCHRONIZER
78
`define CDC
79 40 unneback
 
80 75 unneback
`define WB3AVALON_BRIDGE
81 40 unneback
`define WB3WB3_BRIDGE
82
`define WB3_ARBITER_TYPE1
83 83 unneback
`define WB_ADR_INC
84 101 unneback
`define WB_RAM
85 103 unneback
`define WB_SHADOW_RAM
86 48 unneback
`define WB_B4_ROM
87 40 unneback
`define WB_BOOT_ROM
88
`define WB_DPRAM
89 101 unneback
`define WB_CACHE
90 103 unneback
`define WB_AVALON_BRIDGE
91
`define WB_AVALON_MEM_CACHE
92 40 unneback
 
93 44 unneback
`define IO_DFF_OE
94
`define O_DFF
95
 
96 40 unneback
`endif
97
 
98
`ifdef PLL
99
`ifndef SYNC_RST
100
`define SYNC_RST
101
`endif
102
`endif
103
 
104
`ifdef SYNC_RST
105
`ifndef GBUF
106
`define GBUF
107
`endif
108
`endif
109
 
110 108 unneback
`ifdef WB_DPRAM
111 92 unneback
`ifndef WB_ADR_INC
112
`define WB_ADR_INC
113 40 unneback
`endif
114 92 unneback
`ifndef DPRAM_BE_2R2W
115
`define DPRAM_BE_2R2W
116 40 unneback
`endif
117
`endif
118
 
119 101 unneback
`ifdef WB_RAM
120 83 unneback
`ifndef WB_ADR_INC
121
`define WB_ADR_INC
122 62 unneback
`endif
123
`ifndef RAM_BE
124
`define RAM_BE
125
`endif
126
`endif
127
 
128 40 unneback
`ifdef WB3_ARBITER_TYPE1
129 42 unneback
`ifndef SPR
130
`define SPR
131
`endif
132 40 unneback
`ifndef MUX_ANDOR
133
`define MUX_ANDOR
134
`endif
135
`endif
136
 
137 76 unneback
`ifdef WB3AVALON_BRIDGE
138
`ifndef WB3WB3_BRIDGE
139
`define WB3WB3_BRIDGE
140
`endif
141
`endif
142
 
143 40 unneback
`ifdef WB3WB3_BRIDGE
144
`ifndef CNT_SHREG_CE_CLEAR
145
`define CNT_SHREG_CE_CLEAR
146
`endif
147
`ifndef DFF
148
`define DFF
149
`endif
150
`ifndef DFF_CE
151
`define DFF_CE
152
`endif
153
`ifndef CNT_SHREG_CE_CLEAR
154
`define CNT_SHREG_CE_CLEAR
155
`endif
156
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
157
`define FIFO_2R2W_ASYNC_SIMPLEX
158
`endif
159
`endif
160
 
161 103 unneback
 
162
`ifdef WB_AVALON_MEM_CACHE
163
`ifndef WB_SHADOW_RAM
164
`define WB_SHADOW_RAM
165
`endif
166
`ifndef WB_CACHE
167
`define WB_CACHE
168
`endif
169
`ifndef WB_AVALON_BRIDGE
170
`define WB_AVALON_BRIDGE
171
`endif
172
`endif
173
 
174 101 unneback
`ifdef WB_CACHE
175 100 unneback
`ifndef RAM
176
`define RAM
177
`endif
178
`ifndef WB_ADR_INC
179
`define WB_ADR_INC
180
`endif
181
`ifndef DPRAM_1R1W
182
`define DPRAM_1R1W
183
`endif
184
`ifndef DPRAM_1R2W
185
`define DPRAM_1R2W
186
`endif
187
`ifndef DPRAM_BE_2R2W
188
`define DPRAM_BE_2R2W
189
`endif
190
`ifndef CDC
191
`define CDC
192
`endif
193
`endif
194 103 unneback
 
195
`ifdef WB_SHADOW_RAM
196
`ifndef WB_RAM
197
`define WB_RAM
198
`endif
199
`endif
200
 
201
`ifdef WB_RAM
202
`ifndef WB_ADR_INC
203
`define WB_ADR_INC
204
`endif
205
`endif
206 97 unneback
 
207 40 unneback
`ifdef MULTS18X18
208
`ifndef MULTS
209
`define MULTS
210
`endif
211
`endif
212
 
213
`ifdef SHIFT_UNIT_32
214
`ifndef MULTS
215
`define MULTS
216
`endif
217
`endif
218
 
219
`ifdef MUX2_ANDOR
220
`ifndef MUX_ANDOR
221
`define MUX_ANDOR
222
`endif
223
`endif
224
 
225
`ifdef MUX3_ANDOR
226
`ifndef MUX_ANDOR
227
`define MUX_ANDOR
228
`endif
229
`endif
230
 
231
`ifdef MUX4_ANDOR
232
`ifndef MUX_ANDOR
233
`define MUX_ANDOR
234
`endif
235
`endif
236
 
237
`ifdef MUX5_ANDOR
238
`ifndef MUX_ANDOR
239
`define MUX_ANDOR
240
`endif
241
`endif
242
 
243
`ifdef MUX6_ANDOR
244
`ifndef MUX_ANDOR
245
`define MUX_ANDOR
246
`endif
247
`endif
248
 
249
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
250
`ifndef CNT_BIN_CE
251
`define CNT_BIN_CE
252
`endif
253
`ifndef DPRAM_1R1W
254
`define DPRAM_1R1W
255
`endif
256
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
257
`define CNT_BIN_CE_REW_Q_ZQ_L1
258
`endif
259
`endif
260
 
261
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
262
`ifndef CNT_LFSR_CE
263
`define CNT_LFSR_CE
264
`endif
265
`ifndef DPRAM_2R2W
266
`define DPRAM_2R2W
267
`endif
268
`ifndef CNT_BIN_CE_REW_ZQ_L1
269
`define CNT_BIN_CE_REW_ZQ_L1
270
`endif
271
`endif
272
 
273
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
274
`ifndef CNT_GRAY_CE_BIN
275
`define CNT_GRAY_CE_BIN
276
`endif
277
`ifndef DPRAM_2R2W
278
`define DPRAM_2R2W
279
`endif
280
`ifndef FIFO_CMP_ASYNC
281
`define FIFO_CMP_ASYNC
282
`endif
283
`endif
284
 
285
`ifdef FIFO_2R2W_ASYNC
286
`ifndef FIFO_1R1W_ASYNC
287
`define FIFO_1R1W_ASYNC
288
`endif
289
`endif
290
 
291
`ifdef FIFO_1R1W_ASYNC
292
`ifndef CNT_GRAY_CE_BIN
293
`define CNT_GRAY_CE_BIN
294
`endif
295
`ifndef DPRAM_1R1W
296
`define DPRAM_1R1W
297
`endif
298
`ifndef FIFO_CMP_ASYNC
299
`define FIFO_CMP_ASYNC
300
`endif
301
`endif
302
 
303
`ifdef FIFO_CMP_ASYNC
304
`ifndef DFF_SR
305
`define DFF_SR
306
`endif
307
`ifndef DFF
308
`define DFF
309
`endif
310
`endif
311 48 unneback
 
312
`ifdef REG_FILE
313
`ifndef DPRAM_1R1W
314
`define DPRAM_1R1W
315
`endif
316
`endif
317 97 unneback
 
318 98 unneback
`ifdef CDC
319
`ifndef PULSE2TOGGLE
320
`define PULSE2TOGGLE
321
`endif
322
`ifndef TOGGLE2PULSE
323
`define TOGGLE2PULSE
324
`endif
325
`ifndef SYNCHRONIZER
326
`define SYNCHRONIZER
327
`endif
328
`endif
329
 
330 97 unneback
// size to width
331 100 unneback
`define SIZE2WIDTH_EXPR = (`SIZE2WIDTH==1) ? 0 : (`SIZE2WIDTH==2) ? 1 : (`SIZE2WIDTH==4) ? 2 : (`SIZE2WIDTH==8) ? 3 : (`SIZE2WIDTH==16) ? 4 : (`SIZE2WIDTH==32) ? 5 : (`SIZE2WIDTH==64) ? 6 : (`SIZE2WIDTH==128) ? 7 : 8;
332 62 unneback
//////////////////////////////////////////////////////////////////////
333 6 unneback
////                                                              ////
334
////  Versatile library, clock and reset                          ////
335
////                                                              ////
336
////  Description                                                 ////
337
////  Logic related to clock and reset                            ////
338
////                                                              ////
339
////                                                              ////
340
////  To Do:                                                      ////
341
////   - add more different registers                             ////
342
////                                                              ////
343
////  Author(s):                                                  ////
344
////      - Michael Unneback, unneback@opencores.org              ////
345
////        ORSoC AB                                              ////
346
////                                                              ////
347
//////////////////////////////////////////////////////////////////////
348
////                                                              ////
349
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
350
////                                                              ////
351
//// This source file may be used and distributed without         ////
352
//// restriction provided that this copyright statement is not    ////
353
//// removed from the file and that any derivative work contains  ////
354
//// the original copyright notice and the associated disclaimer. ////
355
////                                                              ////
356
//// This source file is free software; you can redistribute it   ////
357
//// and/or modify it under the terms of the GNU Lesser General   ////
358
//// Public License as published by the Free Software Foundation; ////
359
//// either version 2.1 of the License, or (at your option) any   ////
360
//// later version.                                               ////
361
////                                                              ////
362
//// This source is distributed in the hope that it will be       ////
363
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
364
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
365
//// PURPOSE.  See the GNU Lesser General Public License for more ////
366
//// details.                                                     ////
367
////                                                              ////
368
//// You should have received a copy of the GNU Lesser General    ////
369
//// Public License along with this source; if not, download it   ////
370
//// from http://www.opencores.org/lgpl.shtml                     ////
371
////                                                              ////
372
//////////////////////////////////////////////////////////////////////
373
 
374 48 unneback
`ifdef ACTEL
375
`ifdef GBUF
376
`timescale 1 ns/100 ps
377 6 unneback
// Global buffer
378
// usage:
379
// use to enable global buffers for high fan out signals such as clock and reset
380
// Version: 8.4 8.4.0.33
381
module gbuf(GL,CLK);
382
output GL;
383
input  CLK;
384
 
385
    wire GND;
386
 
387
    GND GND_1_net(.Y(GND));
388
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
389
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
390
 
391
endmodule
392
`timescale 1 ns/1 ns
393 40 unneback
`define MODULE gbuf
394
module `BASE`MODULE ( i, o);
395
`undef MODULE
396 6 unneback
input i;
397
output o;
398
`ifdef SIM_GBUF
399
assign o=i;
400
`else
401
gbuf gbuf_i0 ( .CLK(i), .GL(o));
402
`endif
403
endmodule
404 40 unneback
`endif
405 33 unneback
 
406 6 unneback
`else
407 33 unneback
 
408 40 unneback
`ifdef ALTERA
409
`ifdef GBUF
410 21 unneback
//altera
411 40 unneback
`define MODULE gbuf
412
module `BASE`MODULE ( i, o);
413
`undef MODULE
414 33 unneback
input i;
415
output o;
416
assign o = i;
417
endmodule
418 40 unneback
`endif
419 33 unneback
 
420 6 unneback
`else
421
 
422 40 unneback
`ifdef GBUF
423 6 unneback
`timescale 1 ns/100 ps
424 40 unneback
`define MODULE
425
module `BASE`MODULE ( i, o);
426
`undef MODULE
427 6 unneback
input i;
428
output o;
429
assign o = i;
430
endmodule
431 40 unneback
`endif
432 6 unneback
`endif // ALTERA
433
`endif //ACTEL
434
 
435 40 unneback
`ifdef SYNC_RST
436 6 unneback
// sync reset
437 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
438 6 unneback
// output active high global reset sync with two DFFs 
439
`timescale 1 ns/100 ps
440 40 unneback
`define MODULE sync_rst
441
module `BASE`MODULE ( rst_n_i, rst_o, clk);
442
`undef MODULE
443 6 unneback
input rst_n_i, clk;
444
output rst_o;
445 18 unneback
reg [1:0] tmp;
446 6 unneback
always @ (posedge clk or negedge rst_n_i)
447
if (!rst_n_i)
448 17 unneback
        tmp <= 2'b11;
449 6 unneback
else
450 33 unneback
        tmp <= {1'b0,tmp[1]};
451 40 unneback
`define MODULE gbuf
452
`BASE`MODULE buf_i0( .i(tmp[0]), .o(rst_o));
453
`undef MODULE
454 6 unneback
endmodule
455 40 unneback
`endif
456 6 unneback
 
457 40 unneback
`ifdef PLL
458 6 unneback
// vl_pll
459
`ifdef ACTEL
460 32 unneback
///////////////////////////////////////////////////////////////////////////////
461 17 unneback
`timescale 1 ps/1 ps
462 40 unneback
`define MODULE pll
463
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
464
`undef MODULE
465 6 unneback
parameter index = 0;
466
parameter number_of_clk = 1;
467 17 unneback
parameter period_time_0 = 20000;
468
parameter period_time_1 = 20000;
469
parameter period_time_2 = 20000;
470
parameter lock_delay = 2000000;
471 6 unneback
input clk_i, rst_n_i;
472
output lock;
473
output reg [0:number_of_clk-1] clk_o;
474
output [0:number_of_clk-1] rst_o;
475
 
476
`ifdef SIM_PLL
477
 
478
always
479
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
480
 
481
generate if (number_of_clk > 1)
482
always
483
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
484
endgenerate
485
 
486
generate if (number_of_clk > 2)
487
always
488
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
489
endgenerate
490
 
491
genvar i;
492
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
493
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
494
end
495
endgenerate
496
 
497
assign #lock_delay lock = rst_n_i;
498
 
499
endmodule
500
`else
501
generate if (number_of_clk==1 & index==0) begin
502
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
503
end
504
endgenerate // index==0
505
generate if (number_of_clk==1 & index==1) begin
506
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
507
end
508
endgenerate // index==1
509
generate if (number_of_clk==1 & index==2) begin
510
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
511
end
512
endgenerate // index==2
513
generate if (number_of_clk==1 & index==3) begin
514
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
515
end
516
endgenerate // index==0
517
 
518
generate if (number_of_clk==2 & index==0) begin
519
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
520
end
521
endgenerate // index==0
522
generate if (number_of_clk==2 & index==1) begin
523
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
524
end
525
endgenerate // index==1
526
generate if (number_of_clk==2 & index==2) begin
527
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
528
end
529
endgenerate // index==2
530
generate if (number_of_clk==2 & index==3) begin
531
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
532
end
533
endgenerate // index==0
534
 
535
generate if (number_of_clk==3 & index==0) begin
536
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
537
end
538
endgenerate // index==0
539
generate if (number_of_clk==3 & index==1) begin
540
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
541
end
542
endgenerate // index==1
543
generate if (number_of_clk==3 & index==2) begin
544
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
545
end
546
endgenerate // index==2
547
generate if (number_of_clk==3 & index==3) begin
548
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
549
end
550
endgenerate // index==0
551
 
552
genvar i;
553
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
554 40 unneback
`define MODULE sync_rst
555
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
556
`undef MODULE
557 6 unneback
end
558
endgenerate
559
endmodule
560
`endif
561 32 unneback
///////////////////////////////////////////////////////////////////////////////
562 6 unneback
 
563
`else
564
 
565 32 unneback
///////////////////////////////////////////////////////////////////////////////
566 6 unneback
`ifdef ALTERA
567
 
568 32 unneback
`timescale 1 ps/1 ps
569 40 unneback
`define MODULE pll
570
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
571
`undef MODULE
572 32 unneback
parameter index = 0;
573
parameter number_of_clk = 1;
574
parameter period_time_0 = 20000;
575
parameter period_time_1 = 20000;
576
parameter period_time_2 = 20000;
577
parameter period_time_3 = 20000;
578
parameter period_time_4 = 20000;
579
parameter lock_delay = 2000000;
580
input clk_i, rst_n_i;
581
output lock;
582
output reg [0:number_of_clk-1] clk_o;
583
output [0:number_of_clk-1] rst_o;
584
 
585
`ifdef SIM_PLL
586
 
587
always
588
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
589
 
590
generate if (number_of_clk > 1)
591
always
592
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
593
endgenerate
594
 
595
generate if (number_of_clk > 2)
596
always
597
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
598
endgenerate
599
 
600 33 unneback
generate if (number_of_clk > 3)
601 32 unneback
always
602
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
603
endgenerate
604
 
605 33 unneback
generate if (number_of_clk > 4)
606 32 unneback
always
607
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
608
endgenerate
609
 
610
genvar i;
611
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
612
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
613
end
614
endgenerate
615
 
616 33 unneback
//assign #lock_delay lock = rst_n_i;
617
assign lock = rst_n_i;
618 32 unneback
 
619
endmodule
620 6 unneback
`else
621
 
622 33 unneback
`ifdef VL_PLL0
623
`ifdef VL_PLL0_CLK1
624
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
625
`endif
626
`ifdef VL_PLL0_CLK2
627
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
628
`endif
629
`ifdef VL_PLL0_CLK3
630
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
631
`endif
632
`ifdef VL_PLL0_CLK4
633
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
634
`endif
635
`ifdef VL_PLL0_CLK5
636
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
637
`endif
638
`endif
639 32 unneback
 
640 33 unneback
`ifdef VL_PLL1
641
`ifdef VL_PLL1_CLK1
642
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
643
`endif
644
`ifdef VL_PLL1_CLK2
645
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
646
`endif
647
`ifdef VL_PLL1_CLK3
648
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
649
`endif
650
`ifdef VL_PLL1_CLK4
651
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
652
`endif
653
`ifdef VL_PLL1_CLK5
654
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
655
`endif
656
`endif
657 32 unneback
 
658 33 unneback
`ifdef VL_PLL2
659
`ifdef VL_PLL2_CLK1
660
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
661
`endif
662
`ifdef VL_PLL2_CLK2
663
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
664
`endif
665
`ifdef VL_PLL2_CLK3
666
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
667
`endif
668
`ifdef VL_PLL2_CLK4
669
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
670
`endif
671
`ifdef VL_PLL2_CLK5
672
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
673
`endif
674
`endif
675 32 unneback
 
676 33 unneback
`ifdef VL_PLL3
677
`ifdef VL_PLL3_CLK1
678
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
679
`endif
680
`ifdef VL_PLL3_CLK2
681
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
682
`endif
683
`ifdef VL_PLL3_CLK3
684
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
685
`endif
686
`ifdef VL_PLL3_CLK4
687
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
688
`endif
689
`ifdef VL_PLL3_CLK5
690
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
691
`endif
692
`endif
693 32 unneback
 
694
genvar i;
695
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
696 40 unneback
`define MODULE sync_rst
697
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
698
`undef MODULE
699 32 unneback
end
700
endgenerate
701
endmodule
702
`endif
703
///////////////////////////////////////////////////////////////////////////////
704
 
705
`else
706
 
707 6 unneback
// generic PLL
708 17 unneback
`timescale 1 ps/1 ps
709 40 unneback
`define MODULE pll
710
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
711
`undef MODULE
712 6 unneback
parameter index = 0;
713
parameter number_of_clk = 1;
714 17 unneback
parameter period_time_0 = 20000;
715
parameter period_time_1 = 20000;
716
parameter period_time_2 = 20000;
717 6 unneback
parameter lock_delay = 2000;
718
input clk_i, rst_n_i;
719
output lock;
720
output reg [0:number_of_clk-1] clk_o;
721
output [0:number_of_clk-1] rst_o;
722
 
723
always
724
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
725
 
726
generate if (number_of_clk > 1)
727
always
728
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
729
endgenerate
730
 
731
generate if (number_of_clk > 2)
732
always
733
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
734
endgenerate
735
 
736
genvar i;
737
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
738 40 unneback
`define MODULE sync_rst
739
     `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
740
`undef MODULE
741 6 unneback
end
742
endgenerate
743
 
744
assign #lock_delay lock = rst_n_i;
745
 
746
endmodule
747
 
748
`endif //altera
749 17 unneback
`endif //actel
750 40 unneback
`undef MODULE
751
`endif//////////////////////////////////////////////////////////////////////
752 6 unneback
////                                                              ////
753
////  Versatile library, registers                                ////
754
////                                                              ////
755
////  Description                                                 ////
756
////  Different type of registers                                 ////
757
////                                                              ////
758
////                                                              ////
759
////  To Do:                                                      ////
760
////   - add more different registers                             ////
761
////                                                              ////
762
////  Author(s):                                                  ////
763
////      - Michael Unneback, unneback@opencores.org              ////
764
////        ORSoC AB                                              ////
765
////                                                              ////
766
//////////////////////////////////////////////////////////////////////
767
////                                                              ////
768
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
769
////                                                              ////
770
//// This source file may be used and distributed without         ////
771
//// restriction provided that this copyright statement is not    ////
772
//// removed from the file and that any derivative work contains  ////
773
//// the original copyright notice and the associated disclaimer. ////
774
////                                                              ////
775
//// This source file is free software; you can redistribute it   ////
776
//// and/or modify it under the terms of the GNU Lesser General   ////
777
//// Public License as published by the Free Software Foundation; ////
778
//// either version 2.1 of the License, or (at your option) any   ////
779
//// later version.                                               ////
780
////                                                              ////
781
//// This source is distributed in the hope that it will be       ////
782
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
783
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
784
//// PURPOSE.  See the GNU Lesser General Public License for more ////
785
//// details.                                                     ////
786
////                                                              ////
787
//// You should have received a copy of the GNU Lesser General    ////
788
//// Public License along with this source; if not, download it   ////
789
//// from http://www.opencores.org/lgpl.shtml                     ////
790
////                                                              ////
791
//////////////////////////////////////////////////////////////////////
792
 
793 40 unneback
`ifdef DFF
794
`define MODULE dff
795
module `BASE`MODULE ( d, q, clk, rst);
796
`undef MODULE
797 6 unneback
        parameter width = 1;
798
        parameter reset_value = 0;
799
 
800
        input [width-1:0] d;
801
        input clk, rst;
802
        output reg [width-1:0] q;
803
 
804
        always @ (posedge clk or posedge rst)
805
        if (rst)
806
                q <= reset_value;
807
        else
808
                q <= d;
809
 
810
endmodule
811 40 unneback
`endif
812 6 unneback
 
813 40 unneback
`ifdef DFF_ARRAY
814
`define MODULE dff_array
815
module `BASE`MODULE ( d, q, clk, rst);
816
`undef MODULE
817 6 unneback
 
818
        parameter width = 1;
819
        parameter depth = 2;
820
        parameter reset_value = 1'b0;
821
 
822
        input [width-1:0] d;
823
        input clk, rst;
824
        output [width-1:0] q;
825
        reg  [0:depth-1] q_tmp [width-1:0];
826
        integer i;
827
        always @ (posedge clk or posedge rst)
828
        if (rst) begin
829
            for (i=0;i<depth;i=i+1)
830
                q_tmp[i] <= {width{reset_value}};
831
        end else begin
832
            q_tmp[0] <= d;
833
            for (i=1;i<depth;i=i+1)
834
                q_tmp[i] <= q_tmp[i-1];
835
        end
836
 
837
    assign q = q_tmp[depth-1];
838
 
839
endmodule
840 40 unneback
`endif
841 6 unneback
 
842 40 unneback
`ifdef DFF_CE
843
`define MODULE dff_ce
844
module `BASE`MODULE ( d, ce, q, clk, rst);
845
`undef MODULE
846 6 unneback
 
847
        parameter width = 1;
848
        parameter reset_value = 0;
849
 
850
        input [width-1:0] d;
851
        input ce, clk, rst;
852
        output reg [width-1:0] q;
853
 
854
        always @ (posedge clk or posedge rst)
855
        if (rst)
856
                q <= reset_value;
857
        else
858
                if (ce)
859
                        q <= d;
860
 
861
endmodule
862 40 unneback
`endif
863 6 unneback
 
864 40 unneback
`ifdef DFF_CE_CLEAR
865
`define MODULE dff_ce_clear
866
module `BASE`MODULE ( d, ce, clear, q, clk, rst);
867
`undef MODULE
868 8 unneback
 
869
        parameter width = 1;
870
        parameter reset_value = 0;
871
 
872
        input [width-1:0] d;
873 10 unneback
        input ce, clear, clk, rst;
874 8 unneback
        output reg [width-1:0] q;
875
 
876
        always @ (posedge clk or posedge rst)
877
        if (rst)
878
            q <= reset_value;
879
        else
880
            if (ce)
881
                if (clear)
882
                    q <= {width{1'b0}};
883
                else
884
                    q <= d;
885
 
886
endmodule
887 40 unneback
`endif
888 8 unneback
 
889 40 unneback
`ifdef DF_CE_SET
890
`define MODULE dff_ce_set
891
module `BASE`MODULE ( d, ce, set, q, clk, rst);
892
`undef MODULE
893 24 unneback
 
894
        parameter width = 1;
895
        parameter reset_value = 0;
896
 
897
        input [width-1:0] d;
898
        input ce, set, clk, rst;
899
        output reg [width-1:0] q;
900
 
901
        always @ (posedge clk or posedge rst)
902
        if (rst)
903
            q <= reset_value;
904
        else
905
            if (ce)
906
                if (set)
907
                    q <= {width{1'b1}};
908
                else
909
                    q <= d;
910
 
911
endmodule
912 40 unneback
`endif
913 24 unneback
 
914 40 unneback
`ifdef SPR
915
`define MODULE spr
916
module `BASE`MODULE ( sp, r, q, clk, rst);
917
`undef MODULE
918
 
919 64 unneback
        //parameter width = 1;
920
        parameter reset_value = 1'b0;
921 29 unneback
 
922
        input sp, r;
923
        output reg q;
924
        input clk, rst;
925
 
926
        always @ (posedge clk or posedge rst)
927
        if (rst)
928
            q <= reset_value;
929
        else
930
            if (sp)
931
                q <= 1'b1;
932
            else if (r)
933
                q <= 1'b0;
934
 
935
endmodule
936 40 unneback
`endif
937 29 unneback
 
938 40 unneback
`ifdef SRP
939
`define MODULE srp
940
module `BASE`MODULE ( s, rp, q, clk, rst);
941
`undef MODULE
942
 
943 29 unneback
        parameter width = 1;
944
        parameter reset_value = 0;
945
 
946
        input s, rp;
947
        output reg q;
948
        input clk, rst;
949
 
950
        always @ (posedge clk or posedge rst)
951
        if (rst)
952
            q <= reset_value;
953
        else
954
            if (rp)
955
                q <= 1'b0;
956
            else if (s)
957
                q <= 1'b1;
958
 
959
endmodule
960 40 unneback
`endif
961 29 unneback
 
962 40 unneback
`ifdef ALTERA
963 29 unneback
 
964 40 unneback
`ifdef DFF_SR
965 6 unneback
// megafunction wizard: %LPM_FF%
966
// GENERATION: STANDARD
967
// VERSION: WM1.0
968
// MODULE: lpm_ff 
969
 
970
// ============================================================
971
// File Name: dff_sr.v
972
// Megafunction Name(s):
973
//                      lpm_ff
974
//
975
// Simulation Library Files(s):
976
//                      lpm
977
// ============================================================
978
// ************************************************************
979
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
980
//
981
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
982
// ************************************************************
983
 
984
 
985
//Copyright (C) 1991-2010 Altera Corporation
986
//Your use of Altera Corporation's design tools, logic functions 
987
//and other software and tools, and its AMPP partner logic 
988
//functions, and any output files from any of the foregoing 
989
//(including device programming or simulation files), and any 
990
//associated documentation or information are expressly subject 
991
//to the terms and conditions of the Altera Program License 
992
//Subscription Agreement, Altera MegaCore Function License 
993
//Agreement, or other applicable license agreement, including, 
994
//without limitation, that your use is for the sole purpose of 
995
//programming logic devices manufactured by Altera and sold by 
996
//Altera or its authorized distributors.  Please refer to the 
997
//applicable agreement for further details.
998
 
999
 
1000
// synopsys translate_off
1001
`timescale 1 ps / 1 ps
1002
// synopsys translate_on
1003 40 unneback
`define MODULE dff_sr
1004
module `BASE`MODULE (
1005
`undef MODULE
1006
 
1007 6 unneback
        aclr,
1008
        aset,
1009
        clock,
1010
        data,
1011
        q);
1012
 
1013
        input     aclr;
1014
        input     aset;
1015
        input     clock;
1016
        input     data;
1017
        output    q;
1018
 
1019
        wire [0:0] sub_wire0;
1020
        wire [0:0] sub_wire1 = sub_wire0[0:0];
1021
        wire  q = sub_wire1;
1022
        wire  sub_wire2 = data;
1023
        wire  sub_wire3 = sub_wire2;
1024
 
1025
        lpm_ff  lpm_ff_component (
1026
                                .aclr (aclr),
1027
                                .clock (clock),
1028
                                .data (sub_wire3),
1029
                                .aset (aset),
1030
                                .q (sub_wire0)
1031
                                // synopsys translate_off
1032
                                ,
1033
                                .aload (),
1034
                                .enable (),
1035
                                .sclr (),
1036
                                .sload (),
1037
                                .sset ()
1038
                                // synopsys translate_on
1039
                                );
1040
        defparam
1041
                lpm_ff_component.lpm_fftype = "DFF",
1042
                lpm_ff_component.lpm_type = "LPM_FF",
1043
                lpm_ff_component.lpm_width = 1;
1044
 
1045
 
1046
endmodule
1047
 
1048
// ============================================================
1049
// CNX file retrieval info
1050
// ============================================================
1051
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
1052
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
1053
// Retrieval info: PRIVATE: ASET NUMERIC "1"
1054
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
1055
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
1056
// Retrieval info: PRIVATE: DFF NUMERIC "1"
1057
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
1058
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
1059
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
1060
// Retrieval info: PRIVATE: SSET NUMERIC "0"
1061
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
1062
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
1063
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
1064
// Retrieval info: PRIVATE: nBit NUMERIC "1"
1065
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
1066
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
1067
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
1068
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
1069
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
1070
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
1071
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
1072
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
1073
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
1074
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
1075
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
1076
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
1077
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
1078
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
1079
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
1080
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
1081
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
1082
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
1083
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
1084
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
1085
// Retrieval info: LIB_FILE: lpm
1086 40 unneback
`endif
1087 6 unneback
 
1088
`else
1089
 
1090 40 unneback
`ifdef DFF_SR
1091
`define MODULE dff_sr
1092
module `BASE`MODULE ( aclr, aset, clock, data, q);
1093
`undef MODULE
1094 6 unneback
 
1095
    input         aclr;
1096
    input         aset;
1097
    input         clock;
1098
    input         data;
1099
    output reg    q;
1100
 
1101
   always @ (posedge clock or posedge aclr or posedge aset)
1102
     if (aclr)
1103
       q <= 1'b0;
1104
     else if (aset)
1105
       q <= 1'b1;
1106
     else
1107
       q <= data;
1108
 
1109
endmodule
1110 40 unneback
`endif
1111 6 unneback
 
1112
`endif
1113
 
1114
// LATCH
1115
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
1116
`ifdef ALTERA
1117 40 unneback
 
1118
`ifdef LATCH
1119
`define MODULE latch
1120
module `BASE`MODULE ( d, le, q, clk);
1121
`undef MODULE
1122 6 unneback
input d, le;
1123
output q;
1124
input clk;
1125
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
1126
endmodule
1127 40 unneback
`endif
1128
 
1129 6 unneback
`else
1130 40 unneback
 
1131
`ifdef LATCH
1132
`define MODULE latch
1133
module `BASE`MODULE ( d, le, q, clk);
1134
`undef MODULE
1135 6 unneback
input d, le;
1136 48 unneback
input clk;
1137
always @ (le or d)
1138 60 unneback
if (le)
1139 48 unneback
    d <= q;
1140 6 unneback
endmodule
1141 15 unneback
`endif
1142
 
1143 40 unneback
`endif
1144
 
1145
`ifdef SHREG
1146
`define MODULE shreg
1147
module `BASE`MODULE ( d, q, clk, rst);
1148
`undef MODULE
1149
 
1150 17 unneback
parameter depth = 10;
1151
input d;
1152
output q;
1153
input clk, rst;
1154
 
1155
reg [1:depth] dffs;
1156
 
1157
always @ (posedge clk or posedge rst)
1158
if (rst)
1159
    dffs <= {depth{1'b0}};
1160
else
1161
    dffs <= {d,dffs[1:depth-1]};
1162
assign q = dffs[depth];
1163
endmodule
1164 40 unneback
`endif
1165 17 unneback
 
1166 40 unneback
`ifdef SHREG_CE
1167
`define MODULE shreg_ce
1168
module `BASE`MODULE ( d, ce, q, clk, rst);
1169
`undef MODULE
1170 17 unneback
parameter depth = 10;
1171
input d, ce;
1172
output q;
1173
input clk, rst;
1174
 
1175
reg [1:depth] dffs;
1176
 
1177
always @ (posedge clk or posedge rst)
1178
if (rst)
1179
    dffs <= {depth{1'b0}};
1180
else
1181
    if (ce)
1182
        dffs <= {d,dffs[1:depth-1]};
1183
assign q = dffs[depth];
1184
endmodule
1185 40 unneback
`endif
1186 17 unneback
 
1187 40 unneback
`ifdef DELAY
1188
`define MODULE delay
1189
module `BASE`MODULE ( d, q, clk, rst);
1190
`undef MODULE
1191 15 unneback
parameter depth = 10;
1192
input d;
1193
output q;
1194
input clk, rst;
1195
 
1196
reg [1:depth] dffs;
1197
 
1198
always @ (posedge clk or posedge rst)
1199
if (rst)
1200
    dffs <= {depth{1'b0}};
1201
else
1202
    dffs <= {d,dffs[1:depth-1]};
1203
assign q = dffs[depth];
1204 17 unneback
endmodule
1205 40 unneback
`endif
1206 17 unneback
 
1207 40 unneback
`ifdef DELAY_EMPTYFLAG
1208
`define MODULE delay_emptyflag
1209 41 unneback
module `BASE`MODULE ( d, q, emptyflag, clk, rst);
1210 40 unneback
`undef MODULE
1211 17 unneback
parameter depth = 10;
1212
input d;
1213
output q, emptyflag;
1214
input clk, rst;
1215
 
1216
reg [1:depth] dffs;
1217
 
1218
always @ (posedge clk or posedge rst)
1219
if (rst)
1220
    dffs <= {depth{1'b0}};
1221
else
1222
    dffs <= {d,dffs[1:depth-1]};
1223
assign q = dffs[depth];
1224
assign emptyflag = !(|dffs);
1225
endmodule
1226 40 unneback
`endif
1227 75 unneback
 
1228 94 unneback
`ifdef PULSE2TOGGLE
1229 98 unneback
`define MODULE pulse2toggle
1230
module `BASE`MODULE ( pl, q, clk, rst);
1231 75 unneback
`undef MODULE
1232 94 unneback
input pl;
1233 98 unneback
output reg q;
1234 94 unneback
input clk, rst;
1235
always @ (posedge clk or posedge rst)
1236 75 unneback
if (rst)
1237 94 unneback
    q <= 1'b0;
1238 75 unneback
else
1239 94 unneback
    q <= pl ^ q;
1240
endmodule
1241
`endif
1242 75 unneback
 
1243 94 unneback
`ifdef TOGGLE2PULSE
1244 98 unneback
`define MODULE toggle2pulse
1245 94 unneback
module `BASE`MODULE (d, pl, clk, rst);
1246 97 unneback
`undef MODULE
1247 94 unneback
input d;
1248
output pl;
1249
input clk, rst;
1250
reg dff;
1251
always @ (posedge clk or posedge rst)
1252
if (rst)
1253
    dff <= 1'b0;
1254 75 unneback
else
1255 94 unneback
    dff <= d;
1256 98 unneback
assign pl = d ^ dff;
1257 94 unneback
endmodule
1258
`endif
1259 75 unneback
 
1260 94 unneback
`ifdef SYNCHRONIZER
1261
`define MODULE synchronizer
1262
module `BASE`MODULE (d, q, clk, rst);
1263
`undef MODULE
1264
input d;
1265
output reg q;
1266
output clk, rst;
1267
reg dff;
1268
always @ (posedge clk or posedge rst)
1269
if (rst)
1270 100 unneback
    {q,dff} <= 2'b00;
1271 75 unneback
else
1272 100 unneback
    {q,dff} <= {dff,d};
1273 94 unneback
endmodule
1274
`endif
1275 75 unneback
 
1276 94 unneback
`ifdef CDC
1277
`define MODULE cdc
1278 97 unneback
module `BASE`MODULE ( start_pl, take_it_pl, take_it_grant_pl, got_it_pl, clk_src, rst_src, clk_dst, rst_dst);
1279 94 unneback
`undef MODULE
1280
input start_pl;
1281
output take_it_pl;
1282
input take_it_grant_pl; // note: connect to take_it_pl to generate automatic ack
1283
output got_it_pl;
1284
input clk_src, rst_src;
1285
input clk_dst, rst_dst;
1286
wire take_it_tg, take_it_tg_sync;
1287
wire got_it_tg, got_it_tg_sync;
1288
// src -> dst
1289
`define MODULE pulse2toggle
1290
`BASE`MODULE p2t0 (
1291
`undef MODULE
1292
    .pl(start_pl),
1293
    .q(take_it_tg),
1294
    .clk(clk_src),
1295
    .rst(rst_src));
1296 75 unneback
 
1297 94 unneback
`define MODULE synchronizer
1298
`BASE`MODULE sync0 (
1299
`undef MODULE
1300
    .d(take_it_tg),
1301
    .q(take_it_tg_sync),
1302
    .clk(clk_dst),
1303
    .rst(rst_dst));
1304
 
1305
`define MODULE toggle2pulse
1306
`BASE`MODULE t2p0 (
1307
`undef MODULE
1308 100 unneback
    .d(take_it_tg_sync),
1309 94 unneback
    .pl(take_it_pl),
1310
    .clk(clk_dst),
1311
    .rst(rst_dst));
1312
 
1313
// dst -> src
1314
`define MODULE pulse2toggle
1315 98 unneback
`BASE`MODULE p2t1 (
1316 94 unneback
`undef MODULE
1317
    .pl(take_it_grant_pl),
1318
    .q(got_it_tg),
1319
    .clk(clk_dst),
1320
    .rst(rst_dst));
1321
 
1322
`define MODULE synchronizer
1323
`BASE`MODULE sync1 (
1324
`undef MODULE
1325
    .d(got_it_tg),
1326
    .q(got_it_tg_sync),
1327
    .clk(clk_src),
1328
    .rst(rst_src));
1329
 
1330
`define MODULE toggle2pulse
1331
`BASE`MODULE t2p1 (
1332
`undef MODULE
1333 100 unneback
    .d(got_it_tg_sync),
1334 94 unneback
    .pl(got_it_pl),
1335
    .clk(clk_src),
1336
    .rst(rst_src));
1337
 
1338 75 unneback
endmodule
1339
`endif
1340 17 unneback
//////////////////////////////////////////////////////////////////////
1341 6 unneback
////                                                              ////
1342 18 unneback
////  Logic functions                                             ////
1343
////                                                              ////
1344
////  Description                                                 ////
1345
////  Logic functions such as multiplexers                        ////
1346
////                                                              ////
1347
////                                                              ////
1348
////  To Do:                                                      ////
1349
////   -                                                          ////
1350
////                                                              ////
1351
////  Author(s):                                                  ////
1352
////      - Michael Unneback, unneback@opencores.org              ////
1353
////        ORSoC AB                                              ////
1354
////                                                              ////
1355
//////////////////////////////////////////////////////////////////////
1356
////                                                              ////
1357
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1358
////                                                              ////
1359
//// This source file may be used and distributed without         ////
1360
//// restriction provided that this copyright statement is not    ////
1361
//// removed from the file and that any derivative work contains  ////
1362
//// the original copyright notice and the associated disclaimer. ////
1363
////                                                              ////
1364
//// This source file is free software; you can redistribute it   ////
1365
//// and/or modify it under the terms of the GNU Lesser General   ////
1366
//// Public License as published by the Free Software Foundation; ////
1367
//// either version 2.1 of the License, or (at your option) any   ////
1368
//// later version.                                               ////
1369
////                                                              ////
1370
//// This source is distributed in the hope that it will be       ////
1371
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1372
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1373
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1374
//// details.                                                     ////
1375
////                                                              ////
1376
//// You should have received a copy of the GNU Lesser General    ////
1377
//// Public License along with this source; if not, download it   ////
1378
//// from http://www.opencores.org/lgpl.shtml                     ////
1379
////                                                              ////
1380
//////////////////////////////////////////////////////////////////////
1381 40 unneback
`ifdef MUX_ANDOR
1382
`define MODULE mux_andor
1383
module `BASE`MODULE ( a, sel, dout);
1384
`undef MODULE
1385 36 unneback
 
1386
parameter width = 32;
1387
parameter nr_of_ports = 4;
1388
 
1389
input [nr_of_ports*width-1:0] a;
1390
input [nr_of_ports-1:0] sel;
1391
output reg [width-1:0] dout;
1392
 
1393 38 unneback
integer i,j;
1394
 
1395 36 unneback
always @ (a, sel)
1396
begin
1397
    dout = a[width-1:0] & {width{sel[0]}};
1398 42 unneback
    for (i=1;i<nr_of_ports;i=i+1)
1399
        for (j=0;j<width;j=j+1)
1400
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
1401 36 unneback
end
1402
 
1403
endmodule
1404 40 unneback
`endif
1405 36 unneback
 
1406 40 unneback
`ifdef MUX2_ANDOR
1407
`define MODULE mux2_andor
1408
module `BASE`MODULE ( a1, a0, sel, dout);
1409
`undef MODULE
1410 18 unneback
 
1411 34 unneback
parameter width = 32;
1412 35 unneback
localparam nr_of_ports = 2;
1413 34 unneback
input [width-1:0] a1, a0;
1414
input [nr_of_ports-1:0] sel;
1415
output [width-1:0] dout;
1416
 
1417 40 unneback
`define MODULE mux_andor
1418
`BASE`MODULE
1419 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1420 36 unneback
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
1421 40 unneback
`undef MODULE
1422
 
1423 34 unneback
endmodule
1424 40 unneback
`endif
1425 34 unneback
 
1426 40 unneback
`ifdef MUX3_ANDOR
1427
`define MODULE mux3_andor
1428
module `BASE`MODULE ( a2, a1, a0, sel, dout);
1429
`undef MODULE
1430 34 unneback
 
1431
parameter width = 32;
1432 35 unneback
localparam nr_of_ports = 3;
1433 34 unneback
input [width-1:0] a2, a1, a0;
1434
input [nr_of_ports-1:0] sel;
1435
output [width-1:0] dout;
1436
 
1437 40 unneback
`define MODULE mux_andor
1438
`BASE`MODULE
1439 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1440 36 unneback
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
1441 40 unneback
`undef MODULE
1442 34 unneback
endmodule
1443 40 unneback
`endif
1444 34 unneback
 
1445 40 unneback
`ifdef MUX4_ANDOR
1446
`define MODULE mux4_andor
1447
module `BASE`MODULE ( a3, a2, a1, a0, sel, dout);
1448
`undef MODULE
1449 18 unneback
 
1450
parameter width = 32;
1451 35 unneback
localparam nr_of_ports = 4;
1452 18 unneback
input [width-1:0] a3, a2, a1, a0;
1453
input [nr_of_ports-1:0] sel;
1454 22 unneback
output [width-1:0] dout;
1455 18 unneback
 
1456 40 unneback
`define MODULE mux_andor
1457
`BASE`MODULE
1458 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1459 36 unneback
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
1460 40 unneback
`undef MODULE
1461 18 unneback
 
1462
endmodule
1463 40 unneback
`endif
1464 18 unneback
 
1465 40 unneback
`ifdef MUX5_ANDOR
1466
`define MODULE mux5_andor
1467
module `BASE`MODULE ( a4, a3, a2, a1, a0, sel, dout);
1468
`undef MODULE
1469 18 unneback
 
1470
parameter width = 32;
1471 35 unneback
localparam nr_of_ports = 5;
1472 18 unneback
input [width-1:0] a4, a3, a2, a1, a0;
1473
input [nr_of_ports-1:0] sel;
1474 22 unneback
output [width-1:0] dout;
1475 18 unneback
 
1476 40 unneback
`define MODULE mux_andor
1477
`BASE`MODULE
1478 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1479 36 unneback
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1480 40 unneback
`undef MODULE
1481 18 unneback
 
1482
endmodule
1483 40 unneback
`endif
1484 18 unneback
 
1485 40 unneback
`ifdef MUX6_ANDOR
1486
`define MODULE mux6_andor
1487
module `BASE`MODULE ( a5, a4, a3, a2, a1, a0, sel, dout);
1488
`undef MODULE
1489 18 unneback
 
1490
parameter width = 32;
1491 35 unneback
localparam nr_of_ports = 6;
1492 18 unneback
input [width-1:0] a5, a4, a3, a2, a1, a0;
1493
input [nr_of_ports-1:0] sel;
1494 22 unneback
output [width-1:0] dout;
1495 18 unneback
 
1496 40 unneback
`define MODULE mux_andor
1497
`BASE`MODULE
1498 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1499 36 unneback
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1500 40 unneback
`undef MODULE
1501 18 unneback
 
1502
endmodule
1503 40 unneback
`endif
1504 43 unneback
 
1505
`ifdef PARITY
1506
 
1507
`define MODULE parity_generate
1508
module `BASE`MODULE (data, parity);
1509
`undef MODULE
1510
parameter word_size = 32;
1511
parameter chunk_size = 8;
1512
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1513
input [word_size-1:0] data;
1514
output reg [word_size/chunk_size-1:0] parity;
1515
integer i,j;
1516
always @ (data)
1517
for (i=0;i<word_size/chunk_size;i=i+1) begin
1518
    parity[i] = parity_type;
1519
    for (j=0;j<chunk_size;j=j+1) begin
1520 46 unneback
        parity[i] = data[i*chunk_size+j] ^ parity[i];
1521 43 unneback
    end
1522
end
1523
endmodule
1524
 
1525
`define MODULE parity_check
1526
module `BASE`MODULE( data, parity, parity_error);
1527
`undef MODULE
1528
parameter word_size = 32;
1529
parameter chunk_size = 8;
1530
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1531
input [word_size-1:0] data;
1532
input [word_size/chunk_size-1:0] parity;
1533
output parity_error;
1534 44 unneback
reg [word_size/chunk_size-1:0] error_flag;
1535 43 unneback
integer i,j;
1536
always @ (data or parity)
1537
for (i=0;i<word_size/chunk_size;i=i+1) begin
1538
    error_flag[i] = parity[i] ^ parity_type;
1539
    for (j=0;j<chunk_size;j=j+1) begin
1540 46 unneback
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
1541 43 unneback
    end
1542
end
1543
assign parity_error = |error_flag;
1544
endmodule
1545
 
1546 44 unneback
`endif//////////////////////////////////////////////////////////////////////
1547
////                                                              ////
1548
////  IO functions                                                ////
1549
////                                                              ////
1550
////  Description                                                 ////
1551
////  IO functions such as IOB flip-flops                         ////
1552
////                                                              ////
1553
////                                                              ////
1554
////  To Do:                                                      ////
1555
////   -                                                          ////
1556
////                                                              ////
1557
////  Author(s):                                                  ////
1558
////      - Michael Unneback, unneback@opencores.org              ////
1559
////        ORSoC AB                                              ////
1560
////                                                              ////
1561 18 unneback
//////////////////////////////////////////////////////////////////////
1562
////                                                              ////
1563 44 unneback
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1564
////                                                              ////
1565
//// This source file may be used and distributed without         ////
1566
//// restriction provided that this copyright statement is not    ////
1567
//// removed from the file and that any derivative work contains  ////
1568
//// the original copyright notice and the associated disclaimer. ////
1569
////                                                              ////
1570
//// This source file is free software; you can redistribute it   ////
1571
//// and/or modify it under the terms of the GNU Lesser General   ////
1572
//// Public License as published by the Free Software Foundation; ////
1573
//// either version 2.1 of the License, or (at your option) any   ////
1574
//// later version.                                               ////
1575
////                                                              ////
1576
//// This source is distributed in the hope that it will be       ////
1577
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1578
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1579
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1580
//// details.                                                     ////
1581
////                                                              ////
1582
//// You should have received a copy of the GNU Lesser General    ////
1583
//// Public License along with this source; if not, download it   ////
1584
//// from http://www.opencores.org/lgpl.shtml                     ////
1585
////                                                              ////
1586
//////////////////////////////////////////////////////////////////////
1587 45 unneback
`timescale 1ns/1ns
1588 44 unneback
`ifdef O_DFF
1589
`define MODULE o_dff
1590
module `BASE`MODULE (d_i, o_pad, clk, rst);
1591
`undef MODULE
1592
parameter width = 1;
1593 45 unneback
parameter reset_value = {width{1'b0}};
1594
input  [width-1:0]  d_i;
1595 44 unneback
output [width-1:0] o_pad;
1596
input clk, rst;
1597
wire [width-1:0] d_i_int `SYN_KEEP;
1598 45 unneback
reg  [width-1:0] o_pad_int;
1599 44 unneback
assign d_i_int = d_i;
1600
genvar i;
1601 45 unneback
generate
1602 44 unneback
for (i=0;i<width;i=i+1) begin
1603
    always @ (posedge clk or posedge rst)
1604
    if (rst)
1605 45 unneback
        o_pad_int[i] <= reset_value[i];
1606 44 unneback
    else
1607 45 unneback
        o_pad_int[i] <= d_i_int[i];
1608
    assign #1 o_pad[i] = o_pad_int[i];
1609 44 unneback
end
1610
endgenerate
1611
endmodule
1612
`endif
1613
 
1614 45 unneback
`timescale 1ns/1ns
1615 44 unneback
`ifdef IO_DFF_OE
1616
`define MODULE io_dff_oe
1617
module `BASE`MODULE ( d_i, d_o, oe, io_pad, clk, rst);
1618
`undef MODULE
1619
parameter width = 1;
1620
input  [width-1:0] d_o;
1621
output reg [width-1:0] d_i;
1622
input oe;
1623
inout [width-1:0] io_pad;
1624
input clk, rst;
1625
wire [width-1:0] oe_d `SYN_KEEP;
1626
reg [width-1:0] oe_q;
1627
reg [width-1:0] d_o_q;
1628
assign oe_d = {width{oe}};
1629
genvar i;
1630
generate
1631
for (i=0;i<width;i=i+1) begin
1632
    always @ (posedge clk or posedge rst)
1633
    if (rst)
1634
        oe_q[i] <= 1'b0;
1635
    else
1636
        oe_q[i] <= oe_d[i];
1637
    always @ (posedge clk or posedge rst)
1638
    if (rst)
1639
        d_o_q[i] <= 1'b0;
1640
    else
1641
        d_o_q[i] <= d_o[i];
1642
    always @ (posedge clk or posedge rst)
1643
    if (rst)
1644
        d_i[i] <= 1'b0;
1645
    else
1646
        d_i[i] <= io_pad[i];
1647 45 unneback
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
1648 44 unneback
end
1649
endgenerate
1650
endmodule
1651
`endif
1652
`ifdef CNT_BIN
1653
//////////////////////////////////////////////////////////////////////
1654
////                                                              ////
1655 6 unneback
////  Versatile counter                                           ////
1656
////                                                              ////
1657
////  Description                                                 ////
1658
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1659
////  counter                                                     ////
1660
////                                                              ////
1661
////  To Do:                                                      ////
1662
////   - add LFSR with more taps                                  ////
1663
////                                                              ////
1664
////  Author(s):                                                  ////
1665
////      - Michael Unneback, unneback@opencores.org              ////
1666
////        ORSoC AB                                              ////
1667
////                                                              ////
1668
//////////////////////////////////////////////////////////////////////
1669
////                                                              ////
1670
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1671
////                                                              ////
1672
//// This source file may be used and distributed without         ////
1673
//// restriction provided that this copyright statement is not    ////
1674
//// removed from the file and that any derivative work contains  ////
1675
//// the original copyright notice and the associated disclaimer. ////
1676
////                                                              ////
1677
//// This source file is free software; you can redistribute it   ////
1678
//// and/or modify it under the terms of the GNU Lesser General   ////
1679
//// Public License as published by the Free Software Foundation; ////
1680
//// either version 2.1 of the License, or (at your option) any   ////
1681
//// later version.                                               ////
1682
////                                                              ////
1683
//// This source is distributed in the hope that it will be       ////
1684
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1685
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1686
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1687
//// details.                                                     ////
1688
////                                                              ////
1689
//// You should have received a copy of the GNU Lesser General    ////
1690
//// Public License along with this source; if not, download it   ////
1691
//// from http://www.opencores.org/lgpl.shtml                     ////
1692
////                                                              ////
1693
//////////////////////////////////////////////////////////////////////
1694
 
1695
// binary counter
1696 22 unneback
 
1697 40 unneback
`define MODULE cnt_bin
1698
module `BASE`MODULE (
1699
`undef MODULE
1700
 q, rst, clk);
1701
 
1702 22 unneback
   parameter length = 4;
1703
   output [length:1] q;
1704
   input rst;
1705
   input clk;
1706
 
1707
   parameter clear_value = 0;
1708
   parameter set_value = 1;
1709
   parameter wrap_value = 0;
1710
   parameter level1_value = 15;
1711
 
1712
   reg  [length:1] qi;
1713
   wire [length:1] q_next;
1714
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1715
 
1716
   always @ (posedge clk or posedge rst)
1717
     if (rst)
1718
       qi <= {length{1'b0}};
1719
     else
1720
       qi <= q_next;
1721
 
1722
   assign q = qi;
1723
 
1724
endmodule
1725 40 unneback
`endif
1726
`ifdef CNT_BIN_CLEAR
1727 22 unneback
//////////////////////////////////////////////////////////////////////
1728
////                                                              ////
1729
////  Versatile counter                                           ////
1730
////                                                              ////
1731
////  Description                                                 ////
1732
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1733
////  counter                                                     ////
1734
////                                                              ////
1735
////  To Do:                                                      ////
1736
////   - add LFSR with more taps                                  ////
1737
////                                                              ////
1738
////  Author(s):                                                  ////
1739
////      - Michael Unneback, unneback@opencores.org              ////
1740
////        ORSoC AB                                              ////
1741
////                                                              ////
1742
//////////////////////////////////////////////////////////////////////
1743
////                                                              ////
1744
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1745
////                                                              ////
1746
//// This source file may be used and distributed without         ////
1747
//// restriction provided that this copyright statement is not    ////
1748
//// removed from the file and that any derivative work contains  ////
1749
//// the original copyright notice and the associated disclaimer. ////
1750
////                                                              ////
1751
//// This source file is free software; you can redistribute it   ////
1752
//// and/or modify it under the terms of the GNU Lesser General   ////
1753
//// Public License as published by the Free Software Foundation; ////
1754
//// either version 2.1 of the License, or (at your option) any   ////
1755
//// later version.                                               ////
1756
////                                                              ////
1757
//// This source is distributed in the hope that it will be       ////
1758
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1759
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1760
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1761
//// details.                                                     ////
1762
////                                                              ////
1763
//// You should have received a copy of the GNU Lesser General    ////
1764
//// Public License along with this source; if not, download it   ////
1765
//// from http://www.opencores.org/lgpl.shtml                     ////
1766
////                                                              ////
1767
//////////////////////////////////////////////////////////////////////
1768
 
1769
// binary counter
1770
 
1771 40 unneback
`define MODULE cnt_bin_clear
1772
module `BASE`MODULE (
1773
`undef MODULE
1774
 clear, q, rst, clk);
1775
 
1776 22 unneback
   parameter length = 4;
1777
   input clear;
1778
   output [length:1] q;
1779
   input rst;
1780
   input clk;
1781
 
1782
   parameter clear_value = 0;
1783
   parameter set_value = 1;
1784
   parameter wrap_value = 0;
1785
   parameter level1_value = 15;
1786
 
1787
   reg  [length:1] qi;
1788
   wire [length:1] q_next;
1789
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1790
 
1791
   always @ (posedge clk or posedge rst)
1792
     if (rst)
1793
       qi <= {length{1'b0}};
1794
     else
1795
       qi <= q_next;
1796
 
1797
   assign q = qi;
1798
 
1799
endmodule
1800 40 unneback
`endif
1801
`ifdef CNT_BIN_CE
1802 22 unneback
//////////////////////////////////////////////////////////////////////
1803
////                                                              ////
1804
////  Versatile counter                                           ////
1805
////                                                              ////
1806
////  Description                                                 ////
1807
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1808
////  counter                                                     ////
1809
////                                                              ////
1810
////  To Do:                                                      ////
1811
////   - add LFSR with more taps                                  ////
1812
////                                                              ////
1813
////  Author(s):                                                  ////
1814
////      - Michael Unneback, unneback@opencores.org              ////
1815
////        ORSoC AB                                              ////
1816
////                                                              ////
1817
//////////////////////////////////////////////////////////////////////
1818
////                                                              ////
1819
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1820
////                                                              ////
1821
//// This source file may be used and distributed without         ////
1822
//// restriction provided that this copyright statement is not    ////
1823
//// removed from the file and that any derivative work contains  ////
1824
//// the original copyright notice and the associated disclaimer. ////
1825
////                                                              ////
1826
//// This source file is free software; you can redistribute it   ////
1827
//// and/or modify it under the terms of the GNU Lesser General   ////
1828
//// Public License as published by the Free Software Foundation; ////
1829
//// either version 2.1 of the License, or (at your option) any   ////
1830
//// later version.                                               ////
1831
////                                                              ////
1832
//// This source is distributed in the hope that it will be       ////
1833
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1834
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1835
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1836
//// details.                                                     ////
1837
////                                                              ////
1838
//// You should have received a copy of the GNU Lesser General    ////
1839
//// Public License along with this source; if not, download it   ////
1840
//// from http://www.opencores.org/lgpl.shtml                     ////
1841
////                                                              ////
1842
//////////////////////////////////////////////////////////////////////
1843
 
1844
// binary counter
1845 6 unneback
 
1846 40 unneback
`define MODULE cnt_bin_ce
1847
module `BASE`MODULE (
1848
`undef MODULE
1849
 cke, q, rst, clk);
1850
 
1851 6 unneback
   parameter length = 4;
1852
   input cke;
1853
   output [length:1] q;
1854
   input rst;
1855
   input clk;
1856
 
1857
   parameter clear_value = 0;
1858
   parameter set_value = 1;
1859
   parameter wrap_value = 0;
1860
   parameter level1_value = 15;
1861
 
1862
   reg  [length:1] qi;
1863
   wire [length:1] q_next;
1864
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1865
 
1866
   always @ (posedge clk or posedge rst)
1867
     if (rst)
1868
       qi <= {length{1'b0}};
1869
     else
1870
     if (cke)
1871
       qi <= q_next;
1872
 
1873
   assign q = qi;
1874
 
1875
endmodule
1876 40 unneback
`endif
1877
`ifdef CNT_BIN_CE_CLEAR
1878 6 unneback
//////////////////////////////////////////////////////////////////////
1879
////                                                              ////
1880
////  Versatile counter                                           ////
1881
////                                                              ////
1882
////  Description                                                 ////
1883
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1884
////  counter                                                     ////
1885
////                                                              ////
1886
////  To Do:                                                      ////
1887
////   - add LFSR with more taps                                  ////
1888
////                                                              ////
1889
////  Author(s):                                                  ////
1890
////      - Michael Unneback, unneback@opencores.org              ////
1891
////        ORSoC AB                                              ////
1892
////                                                              ////
1893
//////////////////////////////////////////////////////////////////////
1894
////                                                              ////
1895
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1896
////                                                              ////
1897
//// This source file may be used and distributed without         ////
1898
//// restriction provided that this copyright statement is not    ////
1899
//// removed from the file and that any derivative work contains  ////
1900
//// the original copyright notice and the associated disclaimer. ////
1901
////                                                              ////
1902
//// This source file is free software; you can redistribute it   ////
1903
//// and/or modify it under the terms of the GNU Lesser General   ////
1904
//// Public License as published by the Free Software Foundation; ////
1905
//// either version 2.1 of the License, or (at your option) any   ////
1906
//// later version.                                               ////
1907
////                                                              ////
1908
//// This source is distributed in the hope that it will be       ////
1909
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1910
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1911
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1912
//// details.                                                     ////
1913
////                                                              ////
1914
//// You should have received a copy of the GNU Lesser General    ////
1915
//// Public License along with this source; if not, download it   ////
1916
//// from http://www.opencores.org/lgpl.shtml                     ////
1917
////                                                              ////
1918
//////////////////////////////////////////////////////////////////////
1919
 
1920
// binary counter
1921
 
1922 40 unneback
`define MODULE cnt_bin_ce_clear
1923
module `BASE`MODULE (
1924
`undef MODULE
1925
 clear, cke, q, rst, clk);
1926
 
1927 6 unneback
   parameter length = 4;
1928
   input clear;
1929
   input cke;
1930
   output [length:1] q;
1931
   input rst;
1932
   input clk;
1933
 
1934
   parameter clear_value = 0;
1935
   parameter set_value = 1;
1936
   parameter wrap_value = 0;
1937
   parameter level1_value = 15;
1938
 
1939
   reg  [length:1] qi;
1940
   wire [length:1] q_next;
1941
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1942
 
1943
   always @ (posedge clk or posedge rst)
1944
     if (rst)
1945
       qi <= {length{1'b0}};
1946
     else
1947
     if (cke)
1948
       qi <= q_next;
1949
 
1950
   assign q = qi;
1951
 
1952
endmodule
1953 40 unneback
`endif
1954
`ifdef CNT_BIN_CE_CLEAR_L1_L2
1955 6 unneback
//////////////////////////////////////////////////////////////////////
1956
////                                                              ////
1957
////  Versatile counter                                           ////
1958
////                                                              ////
1959
////  Description                                                 ////
1960
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1961
////  counter                                                     ////
1962
////                                                              ////
1963
////  To Do:                                                      ////
1964
////   - add LFSR with more taps                                  ////
1965
////                                                              ////
1966
////  Author(s):                                                  ////
1967
////      - Michael Unneback, unneback@opencores.org              ////
1968
////        ORSoC AB                                              ////
1969
////                                                              ////
1970
//////////////////////////////////////////////////////////////////////
1971
////                                                              ////
1972
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1973
////                                                              ////
1974
//// This source file may be used and distributed without         ////
1975
//// restriction provided that this copyright statement is not    ////
1976
//// removed from the file and that any derivative work contains  ////
1977
//// the original copyright notice and the associated disclaimer. ////
1978
////                                                              ////
1979
//// This source file is free software; you can redistribute it   ////
1980
//// and/or modify it under the terms of the GNU Lesser General   ////
1981
//// Public License as published by the Free Software Foundation; ////
1982
//// either version 2.1 of the License, or (at your option) any   ////
1983
//// later version.                                               ////
1984
////                                                              ////
1985
//// This source is distributed in the hope that it will be       ////
1986
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1987
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1988
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1989
//// details.                                                     ////
1990
////                                                              ////
1991
//// You should have received a copy of the GNU Lesser General    ////
1992
//// Public License along with this source; if not, download it   ////
1993
//// from http://www.opencores.org/lgpl.shtml                     ////
1994
////                                                              ////
1995
//////////////////////////////////////////////////////////////////////
1996
 
1997
// binary counter
1998 29 unneback
 
1999 40 unneback
`define MODULE cnt_bin_ce_clear_l1_l2
2000
module `BASE`MODULE (
2001
`undef MODULE
2002
 clear, cke, q, level1, level2, rst, clk);
2003
 
2004 29 unneback
   parameter length = 4;
2005
   input clear;
2006
   input cke;
2007
   output [length:1] q;
2008
   output reg level1;
2009
   output reg level2;
2010
   input rst;
2011
   input clk;
2012
 
2013
   parameter clear_value = 0;
2014
   parameter set_value = 1;
2015 30 unneback
   parameter wrap_value = 15;
2016
   parameter level1_value = 8;
2017
   parameter level2_value = 15;
2018 29 unneback
 
2019
   wire rew;
2020 30 unneback
   assign rew = 1'b0;
2021 29 unneback
   reg  [length:1] qi;
2022
   wire [length:1] q_next;
2023
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
2024
 
2025
   always @ (posedge clk or posedge rst)
2026
     if (rst)
2027
       qi <= {length{1'b0}};
2028
     else
2029
     if (cke)
2030
       qi <= q_next;
2031
 
2032
   assign q = qi;
2033
 
2034
 
2035
    always @ (posedge clk or posedge rst)
2036
    if (rst)
2037
        level1 <= 1'b0;
2038
    else
2039
    if (cke)
2040
    if (clear)
2041
        level1 <= 1'b0;
2042
    else if (q_next == level1_value)
2043
        level1 <= 1'b1;
2044
    else if (qi == level1_value & rew)
2045
        level1 <= 1'b0;
2046
 
2047
    always @ (posedge clk or posedge rst)
2048
    if (rst)
2049
        level2 <= 1'b0;
2050
    else
2051
    if (cke)
2052
    if (clear)
2053
        level2 <= 1'b0;
2054
    else if (q_next == level2_value)
2055
        level2 <= 1'b1;
2056
    else if (qi == level2_value & rew)
2057
        level2 <= 1'b0;
2058
endmodule
2059 40 unneback
`endif
2060
`ifdef CNT_BIN_CE_CLEAR_SET_REW
2061 29 unneback
//////////////////////////////////////////////////////////////////////
2062
////                                                              ////
2063
////  Versatile counter                                           ////
2064
////                                                              ////
2065
////  Description                                                 ////
2066
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2067
////  counter                                                     ////
2068
////                                                              ////
2069
////  To Do:                                                      ////
2070
////   - add LFSR with more taps                                  ////
2071
////                                                              ////
2072
////  Author(s):                                                  ////
2073
////      - Michael Unneback, unneback@opencores.org              ////
2074
////        ORSoC AB                                              ////
2075
////                                                              ////
2076
//////////////////////////////////////////////////////////////////////
2077
////                                                              ////
2078
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2079
////                                                              ////
2080
//// This source file may be used and distributed without         ////
2081
//// restriction provided that this copyright statement is not    ////
2082
//// removed from the file and that any derivative work contains  ////
2083
//// the original copyright notice and the associated disclaimer. ////
2084
////                                                              ////
2085
//// This source file is free software; you can redistribute it   ////
2086
//// and/or modify it under the terms of the GNU Lesser General   ////
2087
//// Public License as published by the Free Software Foundation; ////
2088
//// either version 2.1 of the License, or (at your option) any   ////
2089
//// later version.                                               ////
2090
////                                                              ////
2091
//// This source is distributed in the hope that it will be       ////
2092
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2093
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2094
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2095
//// details.                                                     ////
2096
////                                                              ////
2097
//// You should have received a copy of the GNU Lesser General    ////
2098
//// Public License along with this source; if not, download it   ////
2099
//// from http://www.opencores.org/lgpl.shtml                     ////
2100
////                                                              ////
2101
//////////////////////////////////////////////////////////////////////
2102
 
2103
// binary counter
2104 6 unneback
 
2105 40 unneback
`define MODULE cnt_bin_ce_clear_set_rew
2106
module `BASE`MODULE (
2107
`undef MODULE
2108
 clear, set, cke, rew, q, rst, clk);
2109
 
2110 6 unneback
   parameter length = 4;
2111
   input clear;
2112
   input set;
2113
   input cke;
2114
   input rew;
2115
   output [length:1] q;
2116
   input rst;
2117
   input clk;
2118
 
2119
   parameter clear_value = 0;
2120
   parameter set_value = 1;
2121
   parameter wrap_value = 0;
2122
   parameter level1_value = 15;
2123
 
2124
   reg  [length:1] qi;
2125
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2126
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
2127
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
2128
   assign q_next = rew ? q_next_rew : q_next_fw;
2129
 
2130
   always @ (posedge clk or posedge rst)
2131
     if (rst)
2132
       qi <= {length{1'b0}};
2133
     else
2134
     if (cke)
2135
       qi <= q_next;
2136
 
2137
   assign q = qi;
2138
 
2139
endmodule
2140 40 unneback
`endif
2141
`ifdef CNT_BIN_CE_REW_L1
2142 6 unneback
//////////////////////////////////////////////////////////////////////
2143
////                                                              ////
2144
////  Versatile counter                                           ////
2145
////                                                              ////
2146
////  Description                                                 ////
2147
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2148
////  counter                                                     ////
2149
////                                                              ////
2150
////  To Do:                                                      ////
2151
////   - add LFSR with more taps                                  ////
2152
////                                                              ////
2153
////  Author(s):                                                  ////
2154
////      - Michael Unneback, unneback@opencores.org              ////
2155
////        ORSoC AB                                              ////
2156
////                                                              ////
2157
//////////////////////////////////////////////////////////////////////
2158
////                                                              ////
2159
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2160
////                                                              ////
2161
//// This source file may be used and distributed without         ////
2162
//// restriction provided that this copyright statement is not    ////
2163
//// removed from the file and that any derivative work contains  ////
2164
//// the original copyright notice and the associated disclaimer. ////
2165
////                                                              ////
2166
//// This source file is free software; you can redistribute it   ////
2167
//// and/or modify it under the terms of the GNU Lesser General   ////
2168
//// Public License as published by the Free Software Foundation; ////
2169
//// either version 2.1 of the License, or (at your option) any   ////
2170
//// later version.                                               ////
2171
////                                                              ////
2172
//// This source is distributed in the hope that it will be       ////
2173
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2174
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2175
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2176
//// details.                                                     ////
2177
////                                                              ////
2178
//// You should have received a copy of the GNU Lesser General    ////
2179
//// Public License along with this source; if not, download it   ////
2180
//// from http://www.opencores.org/lgpl.shtml                     ////
2181
////                                                              ////
2182
//////////////////////////////////////////////////////////////////////
2183
 
2184
// binary counter
2185
 
2186 40 unneback
`define MODULE cnt_bin_ce_rew_l1
2187
module `BASE`MODULE (
2188
`undef MODULE
2189
 cke, rew, level1, rst, clk);
2190
 
2191 6 unneback
   parameter length = 4;
2192
   input cke;
2193
   input rew;
2194
   output reg level1;
2195
   input rst;
2196
   input clk;
2197
 
2198
   parameter clear_value = 0;
2199
   parameter set_value = 1;
2200
   parameter wrap_value = 1;
2201
   parameter level1_value = 15;
2202
 
2203 29 unneback
   wire clear;
2204 30 unneback
   assign clear = 1'b0;
2205 6 unneback
   reg  [length:1] qi;
2206
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2207
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2208
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2209
   assign q_next = rew ? q_next_rew : q_next_fw;
2210
 
2211
   always @ (posedge clk or posedge rst)
2212
     if (rst)
2213
       qi <= {length{1'b0}};
2214
     else
2215
     if (cke)
2216
       qi <= q_next;
2217
 
2218
 
2219
 
2220
    always @ (posedge clk or posedge rst)
2221
    if (rst)
2222
        level1 <= 1'b0;
2223
    else
2224
    if (cke)
2225 29 unneback
    if (clear)
2226
        level1 <= 1'b0;
2227
    else if (q_next == level1_value)
2228 6 unneback
        level1 <= 1'b1;
2229
    else if (qi == level1_value & rew)
2230
        level1 <= 1'b0;
2231
endmodule
2232 40 unneback
`endif
2233
`ifdef CNT_BIN_CE_REW_ZQ_L1
2234 6 unneback
//////////////////////////////////////////////////////////////////////
2235
////                                                              ////
2236
////  Versatile counter                                           ////
2237
////                                                              ////
2238
////  Description                                                 ////
2239
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2240
////  counter                                                     ////
2241
////                                                              ////
2242
////  To Do:                                                      ////
2243
////   - add LFSR with more taps                                  ////
2244
////                                                              ////
2245
////  Author(s):                                                  ////
2246
////      - Michael Unneback, unneback@opencores.org              ////
2247
////        ORSoC AB                                              ////
2248
////                                                              ////
2249
//////////////////////////////////////////////////////////////////////
2250
////                                                              ////
2251
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2252
////                                                              ////
2253
//// This source file may be used and distributed without         ////
2254
//// restriction provided that this copyright statement is not    ////
2255
//// removed from the file and that any derivative work contains  ////
2256
//// the original copyright notice and the associated disclaimer. ////
2257
////                                                              ////
2258
//// This source file is free software; you can redistribute it   ////
2259
//// and/or modify it under the terms of the GNU Lesser General   ////
2260
//// Public License as published by the Free Software Foundation; ////
2261
//// either version 2.1 of the License, or (at your option) any   ////
2262
//// later version.                                               ////
2263
////                                                              ////
2264
//// This source is distributed in the hope that it will be       ////
2265
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2266
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2267
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2268
//// details.                                                     ////
2269
////                                                              ////
2270
//// You should have received a copy of the GNU Lesser General    ////
2271
//// Public License along with this source; if not, download it   ////
2272
//// from http://www.opencores.org/lgpl.shtml                     ////
2273
////                                                              ////
2274
//////////////////////////////////////////////////////////////////////
2275
 
2276 25 unneback
// binary counter
2277
 
2278 40 unneback
`define MODULE cnt_bin_ce_rew_zq_l1
2279
module `BASE`MODULE (
2280
`undef MODULE
2281
 cke, rew, zq, level1, rst, clk);
2282
 
2283 25 unneback
   parameter length = 4;
2284
   input cke;
2285
   input rew;
2286
   output reg zq;
2287
   output reg level1;
2288
   input rst;
2289
   input clk;
2290
 
2291
   parameter clear_value = 0;
2292
   parameter set_value = 1;
2293
   parameter wrap_value = 1;
2294
   parameter level1_value = 15;
2295
 
2296 29 unneback
   wire clear;
2297 30 unneback
   assign clear = 1'b0;
2298 25 unneback
   reg  [length:1] qi;
2299
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2300
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2301
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2302
   assign q_next = rew ? q_next_rew : q_next_fw;
2303
 
2304
   always @ (posedge clk or posedge rst)
2305
     if (rst)
2306
       qi <= {length{1'b0}};
2307
     else
2308
     if (cke)
2309
       qi <= q_next;
2310
 
2311
 
2312
 
2313
   always @ (posedge clk or posedge rst)
2314
     if (rst)
2315
       zq <= 1'b1;
2316
     else
2317
     if (cke)
2318
       zq <= q_next == {length{1'b0}};
2319
 
2320
    always @ (posedge clk or posedge rst)
2321
    if (rst)
2322
        level1 <= 1'b0;
2323
    else
2324
    if (cke)
2325 29 unneback
    if (clear)
2326
        level1 <= 1'b0;
2327
    else if (q_next == level1_value)
2328 25 unneback
        level1 <= 1'b1;
2329
    else if (qi == level1_value & rew)
2330
        level1 <= 1'b0;
2331
endmodule
2332 40 unneback
`endif
2333
`ifdef CNT_BIN_CE_REW_Q_ZQ_L1
2334 25 unneback
//////////////////////////////////////////////////////////////////////
2335
////                                                              ////
2336
////  Versatile counter                                           ////
2337
////                                                              ////
2338
////  Description                                                 ////
2339
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2340
////  counter                                                     ////
2341
////                                                              ////
2342
////  To Do:                                                      ////
2343
////   - add LFSR with more taps                                  ////
2344
////                                                              ////
2345
////  Author(s):                                                  ////
2346
////      - Michael Unneback, unneback@opencores.org              ////
2347
////        ORSoC AB                                              ////
2348
////                                                              ////
2349
//////////////////////////////////////////////////////////////////////
2350
////                                                              ////
2351
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2352
////                                                              ////
2353
//// This source file may be used and distributed without         ////
2354
//// restriction provided that this copyright statement is not    ////
2355
//// removed from the file and that any derivative work contains  ////
2356
//// the original copyright notice and the associated disclaimer. ////
2357
////                                                              ////
2358
//// This source file is free software; you can redistribute it   ////
2359
//// and/or modify it under the terms of the GNU Lesser General   ////
2360
//// Public License as published by the Free Software Foundation; ////
2361
//// either version 2.1 of the License, or (at your option) any   ////
2362
//// later version.                                               ////
2363
////                                                              ////
2364
//// This source is distributed in the hope that it will be       ////
2365
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2366
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2367
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2368
//// details.                                                     ////
2369
////                                                              ////
2370
//// You should have received a copy of the GNU Lesser General    ////
2371
//// Public License along with this source; if not, download it   ////
2372
//// from http://www.opencores.org/lgpl.shtml                     ////
2373
////                                                              ////
2374
//////////////////////////////////////////////////////////////////////
2375
 
2376
// binary counter
2377
 
2378 40 unneback
`define MODULE cnt_bin_ce_rew_q_zq_l1
2379
module `BASE`MODULE (
2380
`undef MODULE
2381
 cke, rew, q, zq, level1, rst, clk);
2382
 
2383 25 unneback
   parameter length = 4;
2384
   input cke;
2385
   input rew;
2386
   output [length:1] q;
2387
   output reg zq;
2388
   output reg level1;
2389
   input rst;
2390
   input clk;
2391
 
2392
   parameter clear_value = 0;
2393
   parameter set_value = 1;
2394
   parameter wrap_value = 1;
2395
   parameter level1_value = 15;
2396
 
2397 29 unneback
   wire clear;
2398 30 unneback
   assign clear = 1'b0;
2399 25 unneback
   reg  [length:1] qi;
2400
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2401
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2402
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2403
   assign q_next = rew ? q_next_rew : q_next_fw;
2404
 
2405
   always @ (posedge clk or posedge rst)
2406
     if (rst)
2407
       qi <= {length{1'b0}};
2408
     else
2409
     if (cke)
2410
       qi <= q_next;
2411
 
2412
   assign q = qi;
2413
 
2414
 
2415
   always @ (posedge clk or posedge rst)
2416
     if (rst)
2417
       zq <= 1'b1;
2418
     else
2419
     if (cke)
2420
       zq <= q_next == {length{1'b0}};
2421
 
2422
    always @ (posedge clk or posedge rst)
2423
    if (rst)
2424
        level1 <= 1'b0;
2425
    else
2426
    if (cke)
2427 29 unneback
    if (clear)
2428
        level1 <= 1'b0;
2429
    else if (q_next == level1_value)
2430 25 unneback
        level1 <= 1'b1;
2431
    else if (qi == level1_value & rew)
2432
        level1 <= 1'b0;
2433
endmodule
2434 40 unneback
`endif
2435
`ifdef CNT_LFSR_ZQ
2436 25 unneback
//////////////////////////////////////////////////////////////////////
2437
////                                                              ////
2438
////  Versatile counter                                           ////
2439
////                                                              ////
2440
////  Description                                                 ////
2441
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2442
////  counter                                                     ////
2443
////                                                              ////
2444
////  To Do:                                                      ////
2445
////   - add LFSR with more taps                                  ////
2446
////                                                              ////
2447
////  Author(s):                                                  ////
2448
////      - Michael Unneback, unneback@opencores.org              ////
2449
////        ORSoC AB                                              ////
2450
////                                                              ////
2451
//////////////////////////////////////////////////////////////////////
2452
////                                                              ////
2453
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2454
////                                                              ////
2455
//// This source file may be used and distributed without         ////
2456
//// restriction provided that this copyright statement is not    ////
2457
//// removed from the file and that any derivative work contains  ////
2458
//// the original copyright notice and the associated disclaimer. ////
2459
////                                                              ////
2460
//// This source file is free software; you can redistribute it   ////
2461
//// and/or modify it under the terms of the GNU Lesser General   ////
2462
//// Public License as published by the Free Software Foundation; ////
2463
//// either version 2.1 of the License, or (at your option) any   ////
2464
//// later version.                                               ////
2465
////                                                              ////
2466
//// This source is distributed in the hope that it will be       ////
2467
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2468
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2469
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2470
//// details.                                                     ////
2471
////                                                              ////
2472
//// You should have received a copy of the GNU Lesser General    ////
2473
//// Public License along with this source; if not, download it   ////
2474
//// from http://www.opencores.org/lgpl.shtml                     ////
2475
////                                                              ////
2476
//////////////////////////////////////////////////////////////////////
2477
 
2478 6 unneback
// LFSR counter
2479
 
2480 40 unneback
`define MODULE cnt_lfsr_zq
2481
module `BASE`MODULE (
2482
`undef MODULE
2483
 zq, rst, clk);
2484
 
2485 6 unneback
   parameter length = 4;
2486
   output reg zq;
2487
   input rst;
2488
   input clk;
2489
 
2490
   parameter clear_value = 0;
2491
   parameter set_value = 1;
2492
   parameter wrap_value = 8;
2493
   parameter level1_value = 15;
2494
 
2495
   reg  [length:1] qi;
2496
   reg lfsr_fb;
2497
   wire [length:1] q_next;
2498
   reg [32:1] polynom;
2499
   integer i;
2500
 
2501
   always @ (qi)
2502
   begin
2503
        case (length)
2504
         2: polynom = 32'b11;                               // 0x3
2505
         3: polynom = 32'b110;                              // 0x6
2506
         4: polynom = 32'b1100;                             // 0xC
2507
         5: polynom = 32'b10100;                            // 0x14
2508
         6: polynom = 32'b110000;                           // 0x30
2509
         7: polynom = 32'b1100000;                          // 0x60
2510
         8: polynom = 32'b10111000;                         // 0xb8
2511
         9: polynom = 32'b100010000;                        // 0x110
2512
        10: polynom = 32'b1001000000;                       // 0x240
2513
        11: polynom = 32'b10100000000;                      // 0x500
2514
        12: polynom = 32'b100000101001;                     // 0x829
2515
        13: polynom = 32'b1000000001100;                    // 0x100C
2516
        14: polynom = 32'b10000000010101;                   // 0x2015
2517
        15: polynom = 32'b110000000000000;                  // 0x6000
2518
        16: polynom = 32'b1101000000001000;                 // 0xD008
2519
        17: polynom = 32'b10010000000000000;                // 0x12000
2520
        18: polynom = 32'b100000010000000000;               // 0x20400
2521
        19: polynom = 32'b1000000000000100011;              // 0x40023
2522 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2523 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2524
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2525
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2526
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2527
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2528
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2529
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2530
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2531
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2532
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2533
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2534
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2535
        default: polynom = 32'b0;
2536
        endcase
2537
        lfsr_fb = qi[length];
2538
        for (i=length-1; i>=1; i=i-1) begin
2539
            if (polynom[i])
2540
                lfsr_fb = lfsr_fb  ~^ qi[i];
2541
        end
2542
    end
2543
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2544
 
2545
   always @ (posedge clk or posedge rst)
2546
     if (rst)
2547
       qi <= {length{1'b0}};
2548
     else
2549
       qi <= q_next;
2550
 
2551
 
2552
 
2553
   always @ (posedge clk or posedge rst)
2554
     if (rst)
2555
       zq <= 1'b1;
2556
     else
2557
       zq <= q_next == {length{1'b0}};
2558
endmodule
2559 40 unneback
`endif
2560 75 unneback
`ifdef CNT_LFSR_CE
2561
//////////////////////////////////////////////////////////////////////
2562
////                                                              ////
2563
////  Versatile counter                                           ////
2564
////                                                              ////
2565
////  Description                                                 ////
2566
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2567
////  counter                                                     ////
2568
////                                                              ////
2569
////  To Do:                                                      ////
2570
////   - add LFSR with more taps                                  ////
2571
////                                                              ////
2572
////  Author(s):                                                  ////
2573
////      - Michael Unneback, unneback@opencores.org              ////
2574
////        ORSoC AB                                              ////
2575
////                                                              ////
2576
//////////////////////////////////////////////////////////////////////
2577
////                                                              ////
2578
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2579
////                                                              ////
2580
//// This source file may be used and distributed without         ////
2581
//// restriction provided that this copyright statement is not    ////
2582
//// removed from the file and that any derivative work contains  ////
2583
//// the original copyright notice and the associated disclaimer. ////
2584
////                                                              ////
2585
//// This source file is free software; you can redistribute it   ////
2586
//// and/or modify it under the terms of the GNU Lesser General   ////
2587
//// Public License as published by the Free Software Foundation; ////
2588
//// either version 2.1 of the License, or (at your option) any   ////
2589
//// later version.                                               ////
2590
////                                                              ////
2591
//// This source is distributed in the hope that it will be       ////
2592
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2593
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2594
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2595
//// details.                                                     ////
2596
////                                                              ////
2597
//// You should have received a copy of the GNU Lesser General    ////
2598
//// Public License along with this source; if not, download it   ////
2599
//// from http://www.opencores.org/lgpl.shtml                     ////
2600
////                                                              ////
2601
//////////////////////////////////////////////////////////////////////
2602
 
2603
// LFSR counter
2604
 
2605
`define MODULE cnt_lfsr_ce
2606
module `BASE`MODULE (
2607
`undef MODULE
2608
 cke, zq, rst, clk);
2609
 
2610
   parameter length = 4;
2611
   input cke;
2612
   output reg zq;
2613
   input rst;
2614
   input clk;
2615
 
2616
   parameter clear_value = 0;
2617
   parameter set_value = 1;
2618
   parameter wrap_value = 0;
2619
   parameter level1_value = 15;
2620
 
2621
   reg  [length:1] qi;
2622
   reg lfsr_fb;
2623
   wire [length:1] q_next;
2624
   reg [32:1] polynom;
2625
   integer i;
2626
 
2627
   always @ (qi)
2628
   begin
2629
        case (length)
2630
         2: polynom = 32'b11;                               // 0x3
2631
         3: polynom = 32'b110;                              // 0x6
2632
         4: polynom = 32'b1100;                             // 0xC
2633
         5: polynom = 32'b10100;                            // 0x14
2634
         6: polynom = 32'b110000;                           // 0x30
2635
         7: polynom = 32'b1100000;                          // 0x60
2636
         8: polynom = 32'b10111000;                         // 0xb8
2637
         9: polynom = 32'b100010000;                        // 0x110
2638
        10: polynom = 32'b1001000000;                       // 0x240
2639
        11: polynom = 32'b10100000000;                      // 0x500
2640
        12: polynom = 32'b100000101001;                     // 0x829
2641
        13: polynom = 32'b1000000001100;                    // 0x100C
2642
        14: polynom = 32'b10000000010101;                   // 0x2015
2643
        15: polynom = 32'b110000000000000;                  // 0x6000
2644
        16: polynom = 32'b1101000000001000;                 // 0xD008
2645
        17: polynom = 32'b10010000000000000;                // 0x12000
2646
        18: polynom = 32'b100000010000000000;               // 0x20400
2647
        19: polynom = 32'b1000000000000100011;              // 0x40023
2648
        20: polynom = 32'b10010000000000000000;             // 0x90000
2649
        21: polynom = 32'b101000000000000000000;            // 0x140000
2650
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2651
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2652
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2653
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2654
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2655
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2656
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2657
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2658
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2659
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2660
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2661
        default: polynom = 32'b0;
2662
        endcase
2663
        lfsr_fb = qi[length];
2664
        for (i=length-1; i>=1; i=i-1) begin
2665
            if (polynom[i])
2666
                lfsr_fb = lfsr_fb  ~^ qi[i];
2667
        end
2668
    end
2669
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2670
 
2671
   always @ (posedge clk or posedge rst)
2672
     if (rst)
2673
       qi <= {length{1'b0}};
2674
     else
2675
     if (cke)
2676
       qi <= q_next;
2677
 
2678
 
2679
 
2680
   always @ (posedge clk or posedge rst)
2681
     if (rst)
2682
       zq <= 1'b1;
2683
     else
2684
     if (cke)
2685
       zq <= q_next == {length{1'b0}};
2686
endmodule
2687
`endif
2688 40 unneback
`ifdef CNT_LFSR_CE_ZQ
2689 6 unneback
//////////////////////////////////////////////////////////////////////
2690
////                                                              ////
2691
////  Versatile counter                                           ////
2692
////                                                              ////
2693
////  Description                                                 ////
2694
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2695
////  counter                                                     ////
2696
////                                                              ////
2697
////  To Do:                                                      ////
2698
////   - add LFSR with more taps                                  ////
2699
////                                                              ////
2700
////  Author(s):                                                  ////
2701
////      - Michael Unneback, unneback@opencores.org              ////
2702
////        ORSoC AB                                              ////
2703
////                                                              ////
2704
//////////////////////////////////////////////////////////////////////
2705
////                                                              ////
2706
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2707
////                                                              ////
2708
//// This source file may be used and distributed without         ////
2709
//// restriction provided that this copyright statement is not    ////
2710
//// removed from the file and that any derivative work contains  ////
2711
//// the original copyright notice and the associated disclaimer. ////
2712
////                                                              ////
2713
//// This source file is free software; you can redistribute it   ////
2714
//// and/or modify it under the terms of the GNU Lesser General   ////
2715
//// Public License as published by the Free Software Foundation; ////
2716
//// either version 2.1 of the License, or (at your option) any   ////
2717
//// later version.                                               ////
2718
////                                                              ////
2719
//// This source is distributed in the hope that it will be       ////
2720
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2721
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2722
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2723
//// details.                                                     ////
2724
////                                                              ////
2725
//// You should have received a copy of the GNU Lesser General    ////
2726
//// Public License along with this source; if not, download it   ////
2727
//// from http://www.opencores.org/lgpl.shtml                     ////
2728
////                                                              ////
2729
//////////////////////////////////////////////////////////////////////
2730
 
2731
// LFSR counter
2732
 
2733 40 unneback
`define MODULE cnt_lfsr_ce_zq
2734
module `BASE`MODULE (
2735
`undef MODULE
2736
 cke, zq, rst, clk);
2737
 
2738 6 unneback
   parameter length = 4;
2739
   input cke;
2740
   output reg zq;
2741
   input rst;
2742
   input clk;
2743
 
2744
   parameter clear_value = 0;
2745
   parameter set_value = 1;
2746
   parameter wrap_value = 8;
2747
   parameter level1_value = 15;
2748
 
2749
   reg  [length:1] qi;
2750
   reg lfsr_fb;
2751
   wire [length:1] q_next;
2752
   reg [32:1] polynom;
2753
   integer i;
2754
 
2755
   always @ (qi)
2756
   begin
2757
        case (length)
2758
         2: polynom = 32'b11;                               // 0x3
2759
         3: polynom = 32'b110;                              // 0x6
2760
         4: polynom = 32'b1100;                             // 0xC
2761
         5: polynom = 32'b10100;                            // 0x14
2762
         6: polynom = 32'b110000;                           // 0x30
2763
         7: polynom = 32'b1100000;                          // 0x60
2764
         8: polynom = 32'b10111000;                         // 0xb8
2765
         9: polynom = 32'b100010000;                        // 0x110
2766
        10: polynom = 32'b1001000000;                       // 0x240
2767
        11: polynom = 32'b10100000000;                      // 0x500
2768
        12: polynom = 32'b100000101001;                     // 0x829
2769
        13: polynom = 32'b1000000001100;                    // 0x100C
2770
        14: polynom = 32'b10000000010101;                   // 0x2015
2771
        15: polynom = 32'b110000000000000;                  // 0x6000
2772
        16: polynom = 32'b1101000000001000;                 // 0xD008
2773
        17: polynom = 32'b10010000000000000;                // 0x12000
2774
        18: polynom = 32'b100000010000000000;               // 0x20400
2775
        19: polynom = 32'b1000000000000100011;              // 0x40023
2776 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2777 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2778
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2779
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2780
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2781
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2782
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2783
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2784
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2785
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2786
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2787
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2788
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2789
        default: polynom = 32'b0;
2790
        endcase
2791
        lfsr_fb = qi[length];
2792
        for (i=length-1; i>=1; i=i-1) begin
2793
            if (polynom[i])
2794
                lfsr_fb = lfsr_fb  ~^ qi[i];
2795
        end
2796
    end
2797
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2798
 
2799
   always @ (posedge clk or posedge rst)
2800
     if (rst)
2801
       qi <= {length{1'b0}};
2802
     else
2803
     if (cke)
2804
       qi <= q_next;
2805
 
2806
 
2807
 
2808
   always @ (posedge clk or posedge rst)
2809
     if (rst)
2810
       zq <= 1'b1;
2811
     else
2812
     if (cke)
2813
       zq <= q_next == {length{1'b0}};
2814
endmodule
2815 40 unneback
`endif
2816
`ifdef CNT_LFSR_CE_Q
2817 6 unneback
//////////////////////////////////////////////////////////////////////
2818
////                                                              ////
2819
////  Versatile counter                                           ////
2820
////                                                              ////
2821
////  Description                                                 ////
2822
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2823
////  counter                                                     ////
2824
////                                                              ////
2825
////  To Do:                                                      ////
2826
////   - add LFSR with more taps                                  ////
2827
////                                                              ////
2828
////  Author(s):                                                  ////
2829
////      - Michael Unneback, unneback@opencores.org              ////
2830
////        ORSoC AB                                              ////
2831
////                                                              ////
2832
//////////////////////////////////////////////////////////////////////
2833
////                                                              ////
2834
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2835