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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Blame information for rev 140

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Line No. Rev Author Line
1 40 unneback
`ifndef BASE
2
`define BASE vl_
3
`endif
4
 
5 60 unneback
// default SYN_KEEP definition
6
`define SYN_KEEP /*synthesis syn_keep = 1*/
7
 
8 44 unneback
`ifdef ACTEL
9 60 unneback
`undef SYN_KEEP
10 44 unneback
`define SYN_KEEP /*synthesis syn_keep = 1*/
11
`endif
12
 
13 98 unneback
`ifdef ACTEL
14
    // ACTEL FPGA should not use logic to handle rw collision
15
    `define SYN_NO_RW_CHECK /*synthesis syn_ramstyle = "no_rw_check"*/
16
`else
17
    `define SYN_NO_RW_CHECK
18
`endif
19
 
20 40 unneback
`ifdef ALL
21
 
22
`define GBUF
23
`define SYNC_RST
24
`define PLL
25
 
26
`define MULTS
27
`define MULTS18X18
28
`define MULT
29 140 unneback
`define ARITH_UNIT
30 40 unneback
`define SHIFT_UNIT_32
31
`define LOGIC_UNIT
32 140 unneback
`define COUNT_UNIT
33
`define EXT_UNIT
34 40 unneback
 
35
`define CNT_SHREG_WRAP
36
`define CNT_SHREG_CE_WRAP
37 105 unneback
`define CNT_SHREG_CLEAR
38 40 unneback
`define CNT_SHREG_CE_CLEAR
39
`define CNT_SHREG_CE_CLEAR_WRAP
40
 
41 139 unneback
`define CNT_BIN
42
`define CNT_BIN_CE
43
`define CNT_BIN_CLEAR
44
`define CNT_BIN_CE_CLEAR
45
`define CNT_BIN_CE_CLEAR_L1_L2
46
`define CNT_BIN_CE_CLEAR_SET_REW
47
`define CNT_BIN_CE_REW_L1
48
`define CNT_BIN_CE_REW_ZQ_L1
49
`define CNT_BIN_CE_REW_Q_ZQ_L1
50
`define CNT_GRAY
51
`define CNT_GRAY_CE
52
`define CNT_GRAY_CE_BIN
53
`define CNT_LFSR_ZQ
54
`define CNT_LFSR_CE
55
`define CNT_LFSR_CE_CLEAR_Q
56
`define CNT_LFSR_CE_Q
57
`define CNT_LFSR_CE_ZQ
58
`define CNT_LFSR_CE_Q_ZQ
59
`define CNT_LFSR_CE_REW_L1
60
 
61 40 unneback
`define MUX_ANDOR
62
`define MUX2_ANDOR
63
`define MUX3_ANDOR
64
`define MUX4_ANDOR
65
`define MUX5_ANDOR
66
`define MUX6_ANDOR
67 43 unneback
`define PARITY
68 40 unneback
 
69
`define ROM_INIT
70
`define RAM
71
`define RAM_BE
72
`define DPRAM_1R1W
73
`define DPRAM_2R1W
74 100 unneback
`define DPRAM_1R2W
75 40 unneback
`define DPRAM_2R2W
76 75 unneback
`define DPRAM_BE_2R2W
77 40 unneback
`define FIFO_1R1W_FILL_LEVEL_SYNC
78
`define FIFO_2R2W_SYNC_SIMPLEX
79
`define FIFO_CMP_ASYNC
80
`define FIFO_1R1W_ASYNC
81
`define FIFO_2R2W_ASYNC
82
`define FIFO_2R2W_ASYNC_SIMPLEX
83 48 unneback
`define REG_FILE
84 40 unneback
 
85
`define DFF
86
`define DFF_ARRAY
87
`define DFF_CE
88
`define DFF_CE_CLEAR
89
`define DF_CE_SET
90
`define SPR
91
`define SRP
92
`define DFF_SR
93
`define LATCH
94
`define SHREG
95
`define SHREG_CE
96
`define DELAY
97
`define DELAY_EMPTYFLAG
98 94 unneback
`define PULSE2TOGGLE
99
`define TOGGLE2PULSE
100
`define SYNCHRONIZER
101
`define CDC
102 40 unneback
 
103 75 unneback
`define WB3AVALON_BRIDGE
104 40 unneback
`define WB3WB3_BRIDGE
105
`define WB3_ARBITER_TYPE1
106 83 unneback
`define WB_ADR_INC
107 101 unneback
`define WB_RAM
108 103 unneback
`define WB_SHADOW_RAM
109 48 unneback
`define WB_B4_ROM
110 40 unneback
`define WB_BOOT_ROM
111
`define WB_DPRAM
112 101 unneback
`define WB_CACHE
113 103 unneback
`define WB_AVALON_BRIDGE
114
`define WB_AVALON_MEM_CACHE
115 136 unneback
`define WB_SDR_SDRAM_CTRL
116 40 unneback
 
117 44 unneback
`define IO_DFF_OE
118
`define O_DFF
119 136 unneback
`define O_DDR
120
`define O_CLK
121 44 unneback
 
122 40 unneback
`endif
123
 
124 136 unneback
///////////////////////////////////////
125
// dependencies
126
///////////////////////////////////////
127
 
128 40 unneback
`ifdef PLL
129
`ifndef SYNC_RST
130
`define SYNC_RST
131
`endif
132
`endif
133
 
134
`ifdef SYNC_RST
135
`ifndef GBUF
136
`define GBUF
137
`endif
138
`endif
139
 
140 136 unneback
`ifdef WB_SDR_SDRAM_CTRL
141
`ifndef WB_SHADOW_RAM
142
`define WB_SHADOW_RAM
143
`endif
144
`ifndef WB_CACHE
145
`define WB_CACHE
146
`endif
147
`ifndef WB_SDR_SDRAM
148
`define WB_SDR_SDRAM
149
`endif
150
`ifndef IO_DFF_OE
151
`define IO_DFF_OE
152
`endif
153
`ifndef O_DFF
154
`define O_DFF
155
`endif
156
`ifndef O_CLK
157
`define O_CLK
158
`endif
159
`endif
160
 
161
`ifdef WB_SDR_SDRAM
162
`ifndef CNT_SHREG_CLEAR
163
`define CNT_SHREG_CLEAR
164
`endif
165
`ifndef CNT_LFSR_ZQ
166
`define CNT_LFSR_ZQ
167
`endif
168
`ifndef DELAY_EMPTYFLAG
169
`define DELAY_EMPTYFLAG
170
`endif
171
`endif
172
 
173 108 unneback
`ifdef WB_DPRAM
174 92 unneback
`ifndef WB_ADR_INC
175
`define WB_ADR_INC
176 40 unneback
`endif
177 92 unneback
`ifndef DPRAM_BE_2R2W
178
`define DPRAM_BE_2R2W
179 40 unneback
`endif
180
`endif
181
 
182
`ifdef WB3_ARBITER_TYPE1
183 42 unneback
`ifndef SPR
184
`define SPR
185
`endif
186 40 unneback
`ifndef MUX_ANDOR
187
`define MUX_ANDOR
188
`endif
189
`endif
190
 
191 76 unneback
`ifdef WB3AVALON_BRIDGE
192
`ifndef WB3WB3_BRIDGE
193
`define WB3WB3_BRIDGE
194
`endif
195
`endif
196
 
197 40 unneback
`ifdef WB3WB3_BRIDGE
198
`ifndef CNT_SHREG_CE_CLEAR
199
`define CNT_SHREG_CE_CLEAR
200
`endif
201
`ifndef DFF
202
`define DFF
203
`endif
204
`ifndef DFF_CE
205
`define DFF_CE
206
`endif
207
`ifndef CNT_SHREG_CE_CLEAR
208
`define CNT_SHREG_CE_CLEAR
209
`endif
210
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
211
`define FIFO_2R2W_ASYNC_SIMPLEX
212
`endif
213
`endif
214
 
215 103 unneback
 
216
`ifdef WB_AVALON_MEM_CACHE
217
`ifndef WB_SHADOW_RAM
218
`define WB_SHADOW_RAM
219
`endif
220
`ifndef WB_CACHE
221
`define WB_CACHE
222
`endif
223
`ifndef WB_AVALON_BRIDGE
224
`define WB_AVALON_BRIDGE
225
`endif
226
`endif
227
 
228 101 unneback
`ifdef WB_CACHE
229 100 unneback
`ifndef RAM
230
`define RAM
231
`endif
232
`ifndef WB_ADR_INC
233
`define WB_ADR_INC
234
`endif
235
`ifndef DPRAM_1R1W
236
`define DPRAM_1R1W
237
`endif
238
`ifndef DPRAM_1R2W
239
`define DPRAM_1R2W
240
`endif
241
`ifndef DPRAM_BE_2R2W
242
`define DPRAM_BE_2R2W
243
`endif
244
`ifndef CDC
245
`define CDC
246
`endif
247 136 unneback
`ifndef O_DFF
248
`define O_DFF
249 100 unneback
`endif
250 136 unneback
`ifndef O_CLK
251
`define O_CLK
252
`endif
253
`endif
254 103 unneback
 
255
`ifdef WB_SHADOW_RAM
256 115 unneback
`ifndef WB_RAM
257
`define WB_RAM
258 103 unneback
`endif
259
`endif
260
 
261
`ifdef WB_RAM
262
`ifndef WB_ADR_INC
263
`define WB_ADR_INC
264
`endif
265 114 unneback
`ifndef RAM_BE
266
`define RAM_BE
267 103 unneback
`endif
268 114 unneback
`endif
269
 
270 40 unneback
`ifdef MULTS18X18
271
`ifndef MULTS
272
`define MULTS
273
`endif
274
`endif
275
 
276
`ifdef SHIFT_UNIT_32
277
`ifndef MULTS
278
`define MULTS
279
`endif
280
`endif
281
 
282
`ifdef MUX2_ANDOR
283
`ifndef MUX_ANDOR
284
`define MUX_ANDOR
285
`endif
286
`endif
287
 
288
`ifdef MUX3_ANDOR
289
`ifndef MUX_ANDOR
290
`define MUX_ANDOR
291
`endif
292
`endif
293
 
294
`ifdef MUX4_ANDOR
295
`ifndef MUX_ANDOR
296
`define MUX_ANDOR
297
`endif
298
`endif
299
 
300
`ifdef MUX5_ANDOR
301
`ifndef MUX_ANDOR
302
`define MUX_ANDOR
303
`endif
304
`endif
305
 
306
`ifdef MUX6_ANDOR
307
`ifndef MUX_ANDOR
308
`define MUX_ANDOR
309
`endif
310
`endif
311
 
312
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
313
`ifndef CNT_BIN_CE
314
`define CNT_BIN_CE
315
`endif
316
`ifndef DPRAM_1R1W
317
`define DPRAM_1R1W
318
`endif
319
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
320
`define CNT_BIN_CE_REW_Q_ZQ_L1
321
`endif
322
`endif
323
 
324
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
325
`ifndef CNT_LFSR_CE
326
`define CNT_LFSR_CE
327
`endif
328
`ifndef DPRAM_2R2W
329
`define DPRAM_2R2W
330
`endif
331
`ifndef CNT_BIN_CE_REW_ZQ_L1
332
`define CNT_BIN_CE_REW_ZQ_L1
333
`endif
334
`endif
335
 
336
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
337
`ifndef CNT_GRAY_CE_BIN
338
`define CNT_GRAY_CE_BIN
339
`endif
340
`ifndef DPRAM_2R2W
341
`define DPRAM_2R2W
342
`endif
343
`ifndef FIFO_CMP_ASYNC
344
`define FIFO_CMP_ASYNC
345
`endif
346
`endif
347
 
348
`ifdef FIFO_2R2W_ASYNC
349
`ifndef FIFO_1R1W_ASYNC
350
`define FIFO_1R1W_ASYNC
351
`endif
352
`endif
353
 
354
`ifdef FIFO_1R1W_ASYNC
355
`ifndef CNT_GRAY_CE_BIN
356
`define CNT_GRAY_CE_BIN
357
`endif
358
`ifndef DPRAM_1R1W
359
`define DPRAM_1R1W
360
`endif
361
`ifndef FIFO_CMP_ASYNC
362
`define FIFO_CMP_ASYNC
363
`endif
364
`endif
365
 
366
`ifdef FIFO_CMP_ASYNC
367
`ifndef DFF_SR
368
`define DFF_SR
369
`endif
370
`ifndef DFF
371
`define DFF
372
`endif
373
`endif
374 48 unneback
 
375
`ifdef REG_FILE
376
`ifndef DPRAM_1R1W
377
`define DPRAM_1R1W
378
`endif
379
`endif
380 97 unneback
 
381 98 unneback
`ifdef CDC
382
`ifndef PULSE2TOGGLE
383
`define PULSE2TOGGLE
384
`endif
385
`ifndef TOGGLE2PULSE
386
`define TOGGLE2PULSE
387
`endif
388
`ifndef SYNCHRONIZER
389
`define SYNCHRONIZER
390
`endif
391
`endif
392
 
393 136 unneback
`ifdef O_CLK
394
`ifndef O_DDR
395
`define O_DDR
396
`endif
397
`endif
398
 
399 97 unneback
// size to width
400 100 unneback
`define SIZE2WIDTH_EXPR = (`SIZE2WIDTH==1) ? 0 : (`SIZE2WIDTH==2) ? 1 : (`SIZE2WIDTH==4) ? 2 : (`SIZE2WIDTH==8) ? 3 : (`SIZE2WIDTH==16) ? 4 : (`SIZE2WIDTH==32) ? 5 : (`SIZE2WIDTH==64) ? 6 : (`SIZE2WIDTH==128) ? 7 : 8;
401 62 unneback
//////////////////////////////////////////////////////////////////////
402 6 unneback
////                                                              ////
403
////  Versatile library, clock and reset                          ////
404
////                                                              ////
405
////  Description                                                 ////
406
////  Logic related to clock and reset                            ////
407
////                                                              ////
408
////                                                              ////
409
////  To Do:                                                      ////
410
////   - add more different registers                             ////
411
////                                                              ////
412
////  Author(s):                                                  ////
413
////      - Michael Unneback, unneback@opencores.org              ////
414
////        ORSoC AB                                              ////
415
////                                                              ////
416
//////////////////////////////////////////////////////////////////////
417
////                                                              ////
418
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
419
////                                                              ////
420
//// This source file may be used and distributed without         ////
421
//// restriction provided that this copyright statement is not    ////
422
//// removed from the file and that any derivative work contains  ////
423
//// the original copyright notice and the associated disclaimer. ////
424
////                                                              ////
425
//// This source file is free software; you can redistribute it   ////
426
//// and/or modify it under the terms of the GNU Lesser General   ////
427
//// Public License as published by the Free Software Foundation; ////
428
//// either version 2.1 of the License, or (at your option) any   ////
429
//// later version.                                               ////
430
////                                                              ////
431
//// This source is distributed in the hope that it will be       ////
432
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
433
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
434
//// PURPOSE.  See the GNU Lesser General Public License for more ////
435
//// details.                                                     ////
436
////                                                              ////
437
//// You should have received a copy of the GNU Lesser General    ////
438
//// Public License along with this source; if not, download it   ////
439
//// from http://www.opencores.org/lgpl.shtml                     ////
440
////                                                              ////
441
//////////////////////////////////////////////////////////////////////
442
 
443 48 unneback
`ifdef ACTEL
444
`ifdef GBUF
445
`timescale 1 ns/100 ps
446 6 unneback
// Global buffer
447
// usage:
448
// use to enable global buffers for high fan out signals such as clock and reset
449
// Version: 8.4 8.4.0.33
450
module gbuf(GL,CLK);
451
output GL;
452
input  CLK;
453
 
454
    wire GND;
455
 
456
    GND GND_1_net(.Y(GND));
457
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
458
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
459
 
460
endmodule
461
`timescale 1 ns/1 ns
462 40 unneback
`define MODULE gbuf
463
module `BASE`MODULE ( i, o);
464
`undef MODULE
465 6 unneback
input i;
466
output o;
467
`ifdef SIM_GBUF
468
assign o=i;
469
`else
470
gbuf gbuf_i0 ( .CLK(i), .GL(o));
471
`endif
472
endmodule
473 40 unneback
`endif
474 33 unneback
 
475 6 unneback
`else
476 33 unneback
 
477 40 unneback
`ifdef ALTERA
478
`ifdef GBUF
479 21 unneback
//altera
480 40 unneback
`define MODULE gbuf
481
module `BASE`MODULE ( i, o);
482
`undef MODULE
483 33 unneback
input i;
484
output o;
485
assign o = i;
486
endmodule
487 40 unneback
`endif
488 33 unneback
 
489 6 unneback
`else
490
 
491 40 unneback
`ifdef GBUF
492 6 unneback
`timescale 1 ns/100 ps
493 40 unneback
`define MODULE
494
module `BASE`MODULE ( i, o);
495
`undef MODULE
496 6 unneback
input i;
497
output o;
498
assign o = i;
499
endmodule
500 40 unneback
`endif
501 6 unneback
`endif // ALTERA
502
`endif //ACTEL
503
 
504 40 unneback
`ifdef SYNC_RST
505 6 unneback
// sync reset
506 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
507 6 unneback
// output active high global reset sync with two DFFs 
508
`timescale 1 ns/100 ps
509 40 unneback
`define MODULE sync_rst
510
module `BASE`MODULE ( rst_n_i, rst_o, clk);
511
`undef MODULE
512 6 unneback
input rst_n_i, clk;
513
output rst_o;
514 18 unneback
reg [1:0] tmp;
515 6 unneback
always @ (posedge clk or negedge rst_n_i)
516
if (!rst_n_i)
517 17 unneback
        tmp <= 2'b11;
518 6 unneback
else
519 33 unneback
        tmp <= {1'b0,tmp[1]};
520 40 unneback
`define MODULE gbuf
521
`BASE`MODULE buf_i0( .i(tmp[0]), .o(rst_o));
522
`undef MODULE
523 6 unneback
endmodule
524 40 unneback
`endif
525 6 unneback
 
526 40 unneback
`ifdef PLL
527 6 unneback
// vl_pll
528
`ifdef ACTEL
529 32 unneback
///////////////////////////////////////////////////////////////////////////////
530 17 unneback
`timescale 1 ps/1 ps
531 40 unneback
`define MODULE pll
532
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
533
`undef MODULE
534 6 unneback
parameter index = 0;
535
parameter number_of_clk = 1;
536 17 unneback
parameter period_time_0 = 20000;
537
parameter period_time_1 = 20000;
538
parameter period_time_2 = 20000;
539
parameter lock_delay = 2000000;
540 6 unneback
input clk_i, rst_n_i;
541
output lock;
542
output reg [0:number_of_clk-1] clk_o;
543
output [0:number_of_clk-1] rst_o;
544
 
545
`ifdef SIM_PLL
546
 
547
always
548
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
549
 
550
generate if (number_of_clk > 1)
551
always
552
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
553
endgenerate
554
 
555
generate if (number_of_clk > 2)
556
always
557
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
558
endgenerate
559
 
560
genvar i;
561
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
562
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
563
end
564
endgenerate
565
 
566
assign #lock_delay lock = rst_n_i;
567
 
568
endmodule
569
`else
570
generate if (number_of_clk==1 & index==0) begin
571
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
572
end
573
endgenerate // index==0
574
generate if (number_of_clk==1 & index==1) begin
575
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
576
end
577
endgenerate // index==1
578
generate if (number_of_clk==1 & index==2) begin
579
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
580
end
581
endgenerate // index==2
582
generate if (number_of_clk==1 & index==3) begin
583
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
584
end
585
endgenerate // index==0
586
 
587
generate if (number_of_clk==2 & index==0) begin
588
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
589
end
590
endgenerate // index==0
591
generate if (number_of_clk==2 & index==1) begin
592
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
593
end
594
endgenerate // index==1
595
generate if (number_of_clk==2 & index==2) begin
596
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
597
end
598
endgenerate // index==2
599
generate if (number_of_clk==2 & index==3) begin
600
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
601
end
602
endgenerate // index==0
603
 
604
generate if (number_of_clk==3 & index==0) begin
605
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
606
end
607
endgenerate // index==0
608
generate if (number_of_clk==3 & index==1) begin
609
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
610
end
611
endgenerate // index==1
612
generate if (number_of_clk==3 & index==2) begin
613
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
614
end
615
endgenerate // index==2
616
generate if (number_of_clk==3 & index==3) begin
617
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
618
end
619
endgenerate // index==0
620
 
621
genvar i;
622
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
623 40 unneback
`define MODULE sync_rst
624
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
625
`undef MODULE
626 6 unneback
end
627
endgenerate
628
endmodule
629
`endif
630 32 unneback
///////////////////////////////////////////////////////////////////////////////
631 6 unneback
 
632
`else
633
 
634 32 unneback
///////////////////////////////////////////////////////////////////////////////
635 6 unneback
`ifdef ALTERA
636
 
637 32 unneback
`timescale 1 ps/1 ps
638 40 unneback
`define MODULE pll
639
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
640
`undef MODULE
641 32 unneback
parameter index = 0;
642
parameter number_of_clk = 1;
643
parameter period_time_0 = 20000;
644
parameter period_time_1 = 20000;
645
parameter period_time_2 = 20000;
646
parameter period_time_3 = 20000;
647
parameter period_time_4 = 20000;
648
parameter lock_delay = 2000000;
649
input clk_i, rst_n_i;
650
output lock;
651
output reg [0:number_of_clk-1] clk_o;
652
output [0:number_of_clk-1] rst_o;
653
 
654
`ifdef SIM_PLL
655
 
656
always
657
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
658
 
659
generate if (number_of_clk > 1)
660
always
661
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
662
endgenerate
663
 
664
generate if (number_of_clk > 2)
665
always
666
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
667
endgenerate
668
 
669 33 unneback
generate if (number_of_clk > 3)
670 32 unneback
always
671
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
672
endgenerate
673
 
674 33 unneback
generate if (number_of_clk > 4)
675 32 unneback
always
676
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
677
endgenerate
678
 
679
genvar i;
680
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
681
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
682
end
683
endgenerate
684
 
685 33 unneback
//assign #lock_delay lock = rst_n_i;
686
assign lock = rst_n_i;
687 32 unneback
 
688
endmodule
689 6 unneback
`else
690
 
691 33 unneback
`ifdef VL_PLL0
692
`ifdef VL_PLL0_CLK1
693
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
694
`endif
695
`ifdef VL_PLL0_CLK2
696
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
697
`endif
698
`ifdef VL_PLL0_CLK3
699
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
700
`endif
701
`ifdef VL_PLL0_CLK4
702
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
703
`endif
704
`ifdef VL_PLL0_CLK5
705
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
706
`endif
707
`endif
708 32 unneback
 
709 33 unneback
`ifdef VL_PLL1
710
`ifdef VL_PLL1_CLK1
711
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
712
`endif
713
`ifdef VL_PLL1_CLK2
714
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
715
`endif
716
`ifdef VL_PLL1_CLK3
717
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
718
`endif
719
`ifdef VL_PLL1_CLK4
720
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
721
`endif
722
`ifdef VL_PLL1_CLK5
723
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
724
`endif
725
`endif
726 32 unneback
 
727 33 unneback
`ifdef VL_PLL2
728
`ifdef VL_PLL2_CLK1
729
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
730
`endif
731
`ifdef VL_PLL2_CLK2
732
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
733
`endif
734
`ifdef VL_PLL2_CLK3
735
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
736
`endif
737
`ifdef VL_PLL2_CLK4
738
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
739
`endif
740
`ifdef VL_PLL2_CLK5
741
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
742
`endif
743
`endif
744 32 unneback
 
745 33 unneback
`ifdef VL_PLL3
746
`ifdef VL_PLL3_CLK1
747
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
748
`endif
749
`ifdef VL_PLL3_CLK2
750
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
751
`endif
752
`ifdef VL_PLL3_CLK3
753
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
754
`endif
755
`ifdef VL_PLL3_CLK4
756
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
757
`endif
758
`ifdef VL_PLL3_CLK5
759
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
760
`endif
761
`endif
762 32 unneback
 
763
genvar i;
764
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
765 40 unneback
`define MODULE sync_rst
766
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
767
`undef MODULE
768 32 unneback
end
769
endgenerate
770
endmodule
771
`endif
772
///////////////////////////////////////////////////////////////////////////////
773
 
774
`else
775
 
776 6 unneback
// generic PLL
777 17 unneback
`timescale 1 ps/1 ps
778 40 unneback
`define MODULE pll
779
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
780
`undef MODULE
781 6 unneback
parameter index = 0;
782
parameter number_of_clk = 1;
783 140 unneback
parameter period_time = 20000;
784
parameter clk0_mult_by = 1;
785
parameter clk0_div_by  = 1;
786
parameter clk1_mult_by = 1;
787
parameter clk1_div_by  = 1;
788
parameter clk2_mult_by = 1;
789
parameter clk3_div_by  = 1;
790
parameter clk3_mult_by = 1;
791
parameter clk3_div_by  = 1;
792
parameter clk4_mult_by = 1;
793
parameter clk4_div_by  = 1;
794 6 unneback
input clk_i, rst_n_i;
795
output lock;
796
output reg [0:number_of_clk-1] clk_o;
797
 
798 140 unneback
initial
799
    clk_o = {number_of_clk{1'b0}};
800
 
801 6 unneback
always
802 140 unneback
    #((period_time*clk0_div_by/clk0_mult_by)/2) clk_o[0] <=  (!rst_n_i) ? 1'b0 : ~clk_o[0];
803 6 unneback
 
804
generate if (number_of_clk > 1)
805
always
806 140 unneback
    #((period_time*clk1_div_by/clk1_mult_by)/2) clk_o[1] <=  (!rst_n_i) ? 1'b0 : ~clk_o[1];
807 6 unneback
endgenerate
808
 
809
generate if (number_of_clk > 2)
810
always
811 140 unneback
    #((period_time*clk2_div_by/clk2_mult_by)/2) clk_o[2] <=  (!rst_n_i) ? 1'b0 : ~clk_o[2];
812 6 unneback
endgenerate
813
 
814 140 unneback
generate if (number_of_clk > 3)
815
always
816
    #((period_time*clk3_div_by/clk3_mult_by)/2) clk_o[3] <=  (!rst_n_i) ? 1'b0 : ~clk_o[3];
817 6 unneback
endgenerate
818
 
819 140 unneback
generate if (number_of_clk > 4)
820
always
821
    #((period_time*clk4_div_by/clk4_mult_by)/2) clk_o[4] <=  (!rst_n_i) ? 1'b0 : ~clk_o[4];
822
endgenerate
823
 
824 6 unneback
assign #lock_delay lock = rst_n_i;
825
 
826
endmodule
827
 
828
`endif //altera
829 17 unneback
`endif //actel
830 40 unneback
`undef MODULE
831
`endif//////////////////////////////////////////////////////////////////////
832 6 unneback
////                                                              ////
833
////  Versatile library, registers                                ////
834
////                                                              ////
835
////  Description                                                 ////
836
////  Different type of registers                                 ////
837
////                                                              ////
838
////                                                              ////
839
////  To Do:                                                      ////
840
////   - add more different registers                             ////
841
////                                                              ////
842
////  Author(s):                                                  ////
843
////      - Michael Unneback, unneback@opencores.org              ////
844
////        ORSoC AB                                              ////
845
////                                                              ////
846
//////////////////////////////////////////////////////////////////////
847
////                                                              ////
848
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
849
////                                                              ////
850
//// This source file may be used and distributed without         ////
851
//// restriction provided that this copyright statement is not    ////
852
//// removed from the file and that any derivative work contains  ////
853
//// the original copyright notice and the associated disclaimer. ////
854
////                                                              ////
855
//// This source file is free software; you can redistribute it   ////
856
//// and/or modify it under the terms of the GNU Lesser General   ////
857
//// Public License as published by the Free Software Foundation; ////
858
//// either version 2.1 of the License, or (at your option) any   ////
859
//// later version.                                               ////
860
////                                                              ////
861
//// This source is distributed in the hope that it will be       ////
862
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
863
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
864
//// PURPOSE.  See the GNU Lesser General Public License for more ////
865
//// details.                                                     ////
866
////                                                              ////
867
//// You should have received a copy of the GNU Lesser General    ////
868
//// Public License along with this source; if not, download it   ////
869
//// from http://www.opencores.org/lgpl.shtml                     ////
870
////                                                              ////
871
//////////////////////////////////////////////////////////////////////
872
 
873 40 unneback
`ifdef DFF
874
`define MODULE dff
875
module `BASE`MODULE ( d, q, clk, rst);
876
`undef MODULE
877 6 unneback
        parameter width = 1;
878 139 unneback
        parameter reset_value = {width{1'b0}};
879 6 unneback
 
880
        input [width-1:0] d;
881
        input clk, rst;
882
        output reg [width-1:0] q;
883
 
884
        always @ (posedge clk or posedge rst)
885
        if (rst)
886
                q <= reset_value;
887
        else
888
                q <= d;
889
 
890
endmodule
891 40 unneback
`endif
892 6 unneback
 
893 40 unneback
`ifdef DFF_ARRAY
894
`define MODULE dff_array
895
module `BASE`MODULE ( d, q, clk, rst);
896
`undef MODULE
897 6 unneback
 
898
        parameter width = 1;
899
        parameter depth = 2;
900
        parameter reset_value = 1'b0;
901
 
902
        input [width-1:0] d;
903
        input clk, rst;
904
        output [width-1:0] q;
905
        reg  [0:depth-1] q_tmp [width-1:0];
906
        integer i;
907
        always @ (posedge clk or posedge rst)
908
        if (rst) begin
909
            for (i=0;i<depth;i=i+1)
910
                q_tmp[i] <= {width{reset_value}};
911
        end else begin
912
            q_tmp[0] <= d;
913
            for (i=1;i<depth;i=i+1)
914
                q_tmp[i] <= q_tmp[i-1];
915
        end
916
 
917
    assign q = q_tmp[depth-1];
918
 
919
endmodule
920 40 unneback
`endif
921 6 unneback
 
922 40 unneback
`ifdef DFF_CE
923
`define MODULE dff_ce
924
module `BASE`MODULE ( d, ce, q, clk, rst);
925
`undef MODULE
926 6 unneback
 
927
        parameter width = 1;
928 139 unneback
        parameter reset_value = {width{1'b0}};
929 6 unneback
 
930
        input [width-1:0] d;
931
        input ce, clk, rst;
932
        output reg [width-1:0] q;
933
 
934
        always @ (posedge clk or posedge rst)
935
        if (rst)
936
                q <= reset_value;
937
        else
938
                if (ce)
939
                        q <= d;
940
 
941
endmodule
942 40 unneback
`endif
943 6 unneback
 
944 40 unneback
`ifdef DFF_CE_CLEAR
945
`define MODULE dff_ce_clear
946
module `BASE`MODULE ( d, ce, clear, q, clk, rst);
947
`undef MODULE
948 8 unneback
 
949
        parameter width = 1;
950 139 unneback
        parameter reset_value = {width{1'b0}};
951 8 unneback
 
952
        input [width-1:0] d;
953 10 unneback
        input ce, clear, clk, rst;
954 8 unneback
        output reg [width-1:0] q;
955
 
956
        always @ (posedge clk or posedge rst)
957
        if (rst)
958
            q <= reset_value;
959
        else
960
            if (ce)
961
                if (clear)
962
                    q <= {width{1'b0}};
963
                else
964
                    q <= d;
965
 
966
endmodule
967 40 unneback
`endif
968 8 unneback
 
969 40 unneback
`ifdef DF_CE_SET
970
`define MODULE dff_ce_set
971
module `BASE`MODULE ( d, ce, set, q, clk, rst);
972
`undef MODULE
973 24 unneback
 
974
        parameter width = 1;
975 139 unneback
        parameter reset_value = {width{1'b0}};
976 24 unneback
 
977
        input [width-1:0] d;
978
        input ce, set, clk, rst;
979
        output reg [width-1:0] q;
980
 
981
        always @ (posedge clk or posedge rst)
982
        if (rst)
983
            q <= reset_value;
984
        else
985
            if (ce)
986
                if (set)
987
                    q <= {width{1'b1}};
988
                else
989
                    q <= d;
990
 
991
endmodule
992 40 unneback
`endif
993 24 unneback
 
994 40 unneback
`ifdef SPR
995
`define MODULE spr
996
module `BASE`MODULE ( sp, r, q, clk, rst);
997
`undef MODULE
998
 
999 64 unneback
        //parameter width = 1;
1000
        parameter reset_value = 1'b0;
1001 29 unneback
 
1002
        input sp, r;
1003
        output reg q;
1004
        input clk, rst;
1005
 
1006
        always @ (posedge clk or posedge rst)
1007
        if (rst)
1008
            q <= reset_value;
1009
        else
1010
            if (sp)
1011
                q <= 1'b1;
1012
            else if (r)
1013
                q <= 1'b0;
1014
 
1015
endmodule
1016 40 unneback
`endif
1017 29 unneback
 
1018 40 unneback
`ifdef SRP
1019
`define MODULE srp
1020
module `BASE`MODULE ( s, rp, q, clk, rst);
1021
`undef MODULE
1022
 
1023 29 unneback
        parameter width = 1;
1024
        parameter reset_value = 0;
1025
 
1026
        input s, rp;
1027
        output reg q;
1028
        input clk, rst;
1029
 
1030
        always @ (posedge clk or posedge rst)
1031
        if (rst)
1032
            q <= reset_value;
1033
        else
1034
            if (rp)
1035
                q <= 1'b0;
1036
            else if (s)
1037
                q <= 1'b1;
1038
 
1039
endmodule
1040 40 unneback
`endif
1041 29 unneback
 
1042 40 unneback
`ifdef ALTERA
1043 29 unneback
 
1044 40 unneback
`ifdef DFF_SR
1045 6 unneback
// megafunction wizard: %LPM_FF%
1046
// GENERATION: STANDARD
1047
// VERSION: WM1.0
1048
// MODULE: lpm_ff 
1049
 
1050
// ============================================================
1051
// File Name: dff_sr.v
1052
// Megafunction Name(s):
1053
//                      lpm_ff
1054
//
1055
// Simulation Library Files(s):
1056
//                      lpm
1057
// ============================================================
1058
// ************************************************************
1059
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
1060
//
1061
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
1062
// ************************************************************
1063
 
1064
 
1065
//Copyright (C) 1991-2010 Altera Corporation
1066
//Your use of Altera Corporation's design tools, logic functions 
1067
//and other software and tools, and its AMPP partner logic 
1068
//functions, and any output files from any of the foregoing 
1069
//(including device programming or simulation files), and any 
1070
//associated documentation or information are expressly subject 
1071
//to the terms and conditions of the Altera Program License 
1072
//Subscription Agreement, Altera MegaCore Function License 
1073
//Agreement, or other applicable license agreement, including, 
1074
//without limitation, that your use is for the sole purpose of 
1075
//programming logic devices manufactured by Altera and sold by 
1076
//Altera or its authorized distributors.  Please refer to the 
1077
//applicable agreement for further details.
1078
 
1079
 
1080
// synopsys translate_off
1081
`timescale 1 ps / 1 ps
1082
// synopsys translate_on
1083 40 unneback
`define MODULE dff_sr
1084
module `BASE`MODULE (
1085
`undef MODULE
1086
 
1087 6 unneback
        aclr,
1088
        aset,
1089
        clock,
1090
        data,
1091
        q);
1092
 
1093
        input     aclr;
1094
        input     aset;
1095
        input     clock;
1096
        input     data;
1097
        output    q;
1098
 
1099
        wire [0:0] sub_wire0;
1100
        wire [0:0] sub_wire1 = sub_wire0[0:0];
1101
        wire  q = sub_wire1;
1102
        wire  sub_wire2 = data;
1103
        wire  sub_wire3 = sub_wire2;
1104
 
1105
        lpm_ff  lpm_ff_component (
1106
                                .aclr (aclr),
1107
                                .clock (clock),
1108
                                .data (sub_wire3),
1109
                                .aset (aset),
1110
                                .q (sub_wire0)
1111
                                // synopsys translate_off
1112
                                ,
1113
                                .aload (),
1114
                                .enable (),
1115
                                .sclr (),
1116
                                .sload (),
1117
                                .sset ()
1118
                                // synopsys translate_on
1119
                                );
1120
        defparam
1121
                lpm_ff_component.lpm_fftype = "DFF",
1122
                lpm_ff_component.lpm_type = "LPM_FF",
1123
                lpm_ff_component.lpm_width = 1;
1124
 
1125
 
1126
endmodule
1127
 
1128
// ============================================================
1129
// CNX file retrieval info
1130
// ============================================================
1131
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
1132
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
1133
// Retrieval info: PRIVATE: ASET NUMERIC "1"
1134
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
1135
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
1136
// Retrieval info: PRIVATE: DFF NUMERIC "1"
1137
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
1138
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
1139
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
1140
// Retrieval info: PRIVATE: SSET NUMERIC "0"
1141
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
1142
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
1143
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
1144
// Retrieval info: PRIVATE: nBit NUMERIC "1"
1145
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
1146
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
1147
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
1148
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
1149
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
1150
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
1151
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
1152
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
1153
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
1154
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
1155
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
1156
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
1157
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
1158
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
1159
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
1160
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
1161
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
1162
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
1163
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
1164
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
1165
// Retrieval info: LIB_FILE: lpm
1166 40 unneback
`endif
1167 6 unneback
 
1168
`else
1169
 
1170 40 unneback
`ifdef DFF_SR
1171
`define MODULE dff_sr
1172
module `BASE`MODULE ( aclr, aset, clock, data, q);
1173
`undef MODULE
1174 6 unneback
 
1175
    input         aclr;
1176
    input         aset;
1177
    input         clock;
1178
    input         data;
1179
    output reg    q;
1180
 
1181
   always @ (posedge clock or posedge aclr or posedge aset)
1182
     if (aclr)
1183
       q <= 1'b0;
1184
     else if (aset)
1185
       q <= 1'b1;
1186
     else
1187
       q <= data;
1188
 
1189
endmodule
1190 40 unneback
`endif
1191 6 unneback
 
1192
`endif
1193
 
1194
// LATCH
1195
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
1196
`ifdef ALTERA
1197 40 unneback
 
1198
`ifdef LATCH
1199
`define MODULE latch
1200
module `BASE`MODULE ( d, le, q, clk);
1201
`undef MODULE
1202 6 unneback
input d, le;
1203
output q;
1204
input clk;
1205
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
1206
endmodule
1207 40 unneback
`endif
1208
 
1209 6 unneback
`else
1210 40 unneback
 
1211
`ifdef LATCH
1212
`define MODULE latch
1213
module `BASE`MODULE ( d, le, q, clk);
1214
`undef MODULE
1215 6 unneback
input d, le;
1216 48 unneback
input clk;
1217
always @ (le or d)
1218 60 unneback
if (le)
1219 48 unneback
    d <= q;
1220 6 unneback
endmodule
1221 15 unneback
`endif
1222
 
1223 40 unneback
`endif
1224
 
1225
`ifdef SHREG
1226
`define MODULE shreg
1227
module `BASE`MODULE ( d, q, clk, rst);
1228
`undef MODULE
1229
 
1230 17 unneback
parameter depth = 10;
1231
input d;
1232
output q;
1233
input clk, rst;
1234
 
1235
reg [1:depth] dffs;
1236
 
1237
always @ (posedge clk or posedge rst)
1238
if (rst)
1239
    dffs <= {depth{1'b0}};
1240
else
1241
    dffs <= {d,dffs[1:depth-1]};
1242
assign q = dffs[depth];
1243
endmodule
1244 40 unneback
`endif
1245 17 unneback
 
1246 40 unneback
`ifdef SHREG_CE
1247
`define MODULE shreg_ce
1248
module `BASE`MODULE ( d, ce, q, clk, rst);
1249
`undef MODULE
1250 17 unneback
parameter depth = 10;
1251
input d, ce;
1252
output q;
1253
input clk, rst;
1254
 
1255
reg [1:depth] dffs;
1256
 
1257
always @ (posedge clk or posedge rst)
1258
if (rst)
1259
    dffs <= {depth{1'b0}};
1260
else
1261
    if (ce)
1262
        dffs <= {d,dffs[1:depth-1]};
1263
assign q = dffs[depth];
1264
endmodule
1265 40 unneback
`endif
1266 17 unneback
 
1267 40 unneback
`ifdef DELAY
1268
`define MODULE delay
1269
module `BASE`MODULE ( d, q, clk, rst);
1270
`undef MODULE
1271 15 unneback
parameter depth = 10;
1272
input d;
1273
output q;
1274
input clk, rst;
1275
 
1276
reg [1:depth] dffs;
1277
 
1278
always @ (posedge clk or posedge rst)
1279
if (rst)
1280
    dffs <= {depth{1'b0}};
1281
else
1282
    dffs <= {d,dffs[1:depth-1]};
1283
assign q = dffs[depth];
1284 17 unneback
endmodule
1285 40 unneback
`endif
1286 17 unneback
 
1287 40 unneback
`ifdef DELAY_EMPTYFLAG
1288
`define MODULE delay_emptyflag
1289 41 unneback
module `BASE`MODULE ( d, q, emptyflag, clk, rst);
1290 40 unneback
`undef MODULE
1291 17 unneback
parameter depth = 10;
1292
input d;
1293
output q, emptyflag;
1294
input clk, rst;
1295
 
1296
reg [1:depth] dffs;
1297
 
1298
always @ (posedge clk or posedge rst)
1299
if (rst)
1300
    dffs <= {depth{1'b0}};
1301
else
1302
    dffs <= {d,dffs[1:depth-1]};
1303
assign q = dffs[depth];
1304
assign emptyflag = !(|dffs);
1305
endmodule
1306 40 unneback
`endif
1307 75 unneback
 
1308 94 unneback
`ifdef PULSE2TOGGLE
1309 98 unneback
`define MODULE pulse2toggle
1310
module `BASE`MODULE ( pl, q, clk, rst);
1311 75 unneback
`undef MODULE
1312 94 unneback
input pl;
1313 98 unneback
output reg q;
1314 94 unneback
input clk, rst;
1315
always @ (posedge clk or posedge rst)
1316 75 unneback
if (rst)
1317 94 unneback
    q <= 1'b0;
1318 75 unneback
else
1319 94 unneback
    q <= pl ^ q;
1320
endmodule
1321
`endif
1322 75 unneback
 
1323 94 unneback
`ifdef TOGGLE2PULSE
1324 98 unneback
`define MODULE toggle2pulse
1325 94 unneback
module `BASE`MODULE (d, pl, clk, rst);
1326 97 unneback
`undef MODULE
1327 94 unneback
input d;
1328
output pl;
1329
input clk, rst;
1330
reg dff;
1331
always @ (posedge clk or posedge rst)
1332
if (rst)
1333
    dff <= 1'b0;
1334 75 unneback
else
1335 94 unneback
    dff <= d;
1336 98 unneback
assign pl = d ^ dff;
1337 94 unneback
endmodule
1338
`endif
1339 75 unneback
 
1340 94 unneback
`ifdef SYNCHRONIZER
1341
`define MODULE synchronizer
1342
module `BASE`MODULE (d, q, clk, rst);
1343
`undef MODULE
1344
input d;
1345
output reg q;
1346 116 unneback
input clk, rst;
1347 94 unneback
reg dff;
1348
always @ (posedge clk or posedge rst)
1349
if (rst)
1350 100 unneback
    {q,dff} <= 2'b00;
1351 75 unneback
else
1352 100 unneback
    {q,dff} <= {dff,d};
1353 94 unneback
endmodule
1354
`endif
1355 75 unneback
 
1356 94 unneback
`ifdef CDC
1357
`define MODULE cdc
1358 97 unneback
module `BASE`MODULE ( start_pl, take_it_pl, take_it_grant_pl, got_it_pl, clk_src, rst_src, clk_dst, rst_dst);
1359 94 unneback
`undef MODULE
1360
input start_pl;
1361
output take_it_pl;
1362
input take_it_grant_pl; // note: connect to take_it_pl to generate automatic ack
1363
output got_it_pl;
1364
input clk_src, rst_src;
1365
input clk_dst, rst_dst;
1366
wire take_it_tg, take_it_tg_sync;
1367
wire got_it_tg, got_it_tg_sync;
1368
// src -> dst
1369
`define MODULE pulse2toggle
1370
`BASE`MODULE p2t0 (
1371
`undef MODULE
1372
    .pl(start_pl),
1373
    .q(take_it_tg),
1374
    .clk(clk_src),
1375
    .rst(rst_src));
1376 75 unneback
 
1377 94 unneback
`define MODULE synchronizer
1378
`BASE`MODULE sync0 (
1379
`undef MODULE
1380
    .d(take_it_tg),
1381
    .q(take_it_tg_sync),
1382
    .clk(clk_dst),
1383
    .rst(rst_dst));
1384
 
1385
`define MODULE toggle2pulse
1386
`BASE`MODULE t2p0 (
1387
`undef MODULE
1388 100 unneback
    .d(take_it_tg_sync),
1389 94 unneback
    .pl(take_it_pl),
1390
    .clk(clk_dst),
1391
    .rst(rst_dst));
1392
 
1393
// dst -> src
1394
`define MODULE pulse2toggle
1395 98 unneback
`BASE`MODULE p2t1 (
1396 94 unneback
`undef MODULE
1397
    .pl(take_it_grant_pl),
1398
    .q(got_it_tg),
1399
    .clk(clk_dst),
1400
    .rst(rst_dst));
1401
 
1402
`define MODULE synchronizer
1403
`BASE`MODULE sync1 (
1404
`undef MODULE
1405
    .d(got_it_tg),
1406
    .q(got_it_tg_sync),
1407
    .clk(clk_src),
1408
    .rst(rst_src));
1409
 
1410
`define MODULE toggle2pulse
1411
`BASE`MODULE t2p1 (
1412
`undef MODULE
1413 100 unneback
    .d(got_it_tg_sync),
1414 94 unneback
    .pl(got_it_pl),
1415
    .clk(clk_src),
1416
    .rst(rst_src));
1417
 
1418 75 unneback
endmodule
1419
`endif
1420 17 unneback
//////////////////////////////////////////////////////////////////////
1421 6 unneback
////                                                              ////
1422 18 unneback
////  Logic functions                                             ////
1423
////                                                              ////
1424
////  Description                                                 ////
1425
////  Logic functions such as multiplexers                        ////
1426
////                                                              ////
1427
////                                                              ////
1428
////  To Do:                                                      ////
1429
////   -                                                          ////
1430
////                                                              ////
1431
////  Author(s):                                                  ////
1432
////      - Michael Unneback, unneback@opencores.org              ////
1433
////        ORSoC AB                                              ////
1434
////                                                              ////
1435
//////////////////////////////////////////////////////////////////////
1436
////                                                              ////
1437
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1438
////                                                              ////
1439
//// This source file may be used and distributed without         ////
1440
//// restriction provided that this copyright statement is not    ////
1441
//// removed from the file and that any derivative work contains  ////
1442
//// the original copyright notice and the associated disclaimer. ////
1443
////                                                              ////
1444
//// This source file is free software; you can redistribute it   ////
1445
//// and/or modify it under the terms of the GNU Lesser General   ////
1446
//// Public License as published by the Free Software Foundation; ////
1447
//// either version 2.1 of the License, or (at your option) any   ////
1448
//// later version.                                               ////
1449
////                                                              ////
1450
//// This source is distributed in the hope that it will be       ////
1451
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1452
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1453
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1454
//// details.                                                     ////
1455
////                                                              ////
1456
//// You should have received a copy of the GNU Lesser General    ////
1457
//// Public License along with this source; if not, download it   ////
1458
//// from http://www.opencores.org/lgpl.shtml                     ////
1459
////                                                              ////
1460
//////////////////////////////////////////////////////////////////////
1461 40 unneback
`ifdef MUX_ANDOR
1462
`define MODULE mux_andor
1463
module `BASE`MODULE ( a, sel, dout);
1464
`undef MODULE
1465 36 unneback
 
1466
parameter width = 32;
1467
parameter nr_of_ports = 4;
1468
 
1469
input [nr_of_ports*width-1:0] a;
1470
input [nr_of_ports-1:0] sel;
1471
output reg [width-1:0] dout;
1472
 
1473 38 unneback
integer i,j;
1474
 
1475 36 unneback
always @ (a, sel)
1476
begin
1477
    dout = a[width-1:0] & {width{sel[0]}};
1478 42 unneback
    for (i=1;i<nr_of_ports;i=i+1)
1479
        for (j=0;j<width;j=j+1)
1480
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
1481 36 unneback
end
1482
 
1483
endmodule
1484 40 unneback
`endif
1485 36 unneback
 
1486 40 unneback
`ifdef MUX2_ANDOR
1487
`define MODULE mux2_andor
1488
module `BASE`MODULE ( a1, a0, sel, dout);
1489
`undef MODULE
1490 18 unneback
 
1491 34 unneback
parameter width = 32;
1492 35 unneback
localparam nr_of_ports = 2;
1493 34 unneback
input [width-1:0] a1, a0;
1494
input [nr_of_ports-1:0] sel;
1495
output [width-1:0] dout;
1496
 
1497 40 unneback
`define MODULE mux_andor
1498
`BASE`MODULE
1499 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1500 36 unneback
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
1501 40 unneback
`undef MODULE
1502
 
1503 34 unneback
endmodule
1504 40 unneback
`endif
1505 34 unneback
 
1506 40 unneback
`ifdef MUX3_ANDOR
1507
`define MODULE mux3_andor
1508
module `BASE`MODULE ( a2, a1, a0, sel, dout);
1509
`undef MODULE
1510 34 unneback
 
1511
parameter width = 32;
1512 35 unneback
localparam nr_of_ports = 3;
1513 34 unneback
input [width-1:0] a2, a1, a0;
1514
input [nr_of_ports-1:0] sel;
1515
output [width-1:0] dout;
1516
 
1517 40 unneback
`define MODULE mux_andor
1518
`BASE`MODULE
1519 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1520 36 unneback
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
1521 40 unneback
`undef MODULE
1522 34 unneback
endmodule
1523 40 unneback
`endif
1524 34 unneback
 
1525 40 unneback
`ifdef MUX4_ANDOR
1526
`define MODULE mux4_andor
1527
module `BASE`MODULE ( a3, a2, a1, a0, sel, dout);
1528
`undef MODULE
1529 18 unneback
 
1530
parameter width = 32;
1531 35 unneback
localparam nr_of_ports = 4;
1532 18 unneback
input [width-1:0] a3, a2, a1, a0;
1533
input [nr_of_ports-1:0] sel;
1534 22 unneback
output [width-1:0] dout;
1535 18 unneback
 
1536 40 unneback
`define MODULE mux_andor
1537
`BASE`MODULE
1538 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1539 36 unneback
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
1540 40 unneback
`undef MODULE
1541 18 unneback
 
1542
endmodule
1543 40 unneback
`endif
1544 18 unneback
 
1545 40 unneback
`ifdef MUX5_ANDOR
1546
`define MODULE mux5_andor
1547
module `BASE`MODULE ( a4, a3, a2, a1, a0, sel, dout);
1548
`undef MODULE
1549 18 unneback
 
1550
parameter width = 32;
1551 35 unneback
localparam nr_of_ports = 5;
1552 18 unneback
input [width-1:0] a4, a3, a2, a1, a0;
1553
input [nr_of_ports-1:0] sel;
1554 22 unneback
output [width-1:0] dout;
1555 18 unneback
 
1556 40 unneback
`define MODULE mux_andor
1557
`BASE`MODULE
1558 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1559 36 unneback
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1560 40 unneback
`undef MODULE
1561 18 unneback
 
1562
endmodule
1563 40 unneback
`endif
1564 18 unneback
 
1565 40 unneback
`ifdef MUX6_ANDOR
1566
`define MODULE mux6_andor
1567
module `BASE`MODULE ( a5, a4, a3, a2, a1, a0, sel, dout);
1568
`undef MODULE
1569 18 unneback
 
1570
parameter width = 32;
1571 35 unneback
localparam nr_of_ports = 6;
1572 18 unneback
input [width-1:0] a5, a4, a3, a2, a1, a0;
1573
input [nr_of_ports-1:0] sel;
1574 22 unneback
output [width-1:0] dout;
1575 18 unneback
 
1576 40 unneback
`define MODULE mux_andor
1577
`BASE`MODULE
1578 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1579 36 unneback
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1580 40 unneback
`undef MODULE
1581 18 unneback
 
1582
endmodule
1583 40 unneback
`endif
1584 43 unneback
 
1585
`ifdef PARITY
1586
 
1587
`define MODULE parity_generate
1588
module `BASE`MODULE (data, parity);
1589
`undef MODULE
1590
parameter word_size = 32;
1591
parameter chunk_size = 8;
1592
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1593
input [word_size-1:0] data;
1594
output reg [word_size/chunk_size-1:0] parity;
1595
integer i,j;
1596
always @ (data)
1597
for (i=0;i<word_size/chunk_size;i=i+1) begin
1598
    parity[i] = parity_type;
1599
    for (j=0;j<chunk_size;j=j+1) begin
1600 46 unneback
        parity[i] = data[i*chunk_size+j] ^ parity[i];
1601 43 unneback
    end
1602
end
1603
endmodule
1604
 
1605
`define MODULE parity_check
1606
module `BASE`MODULE( data, parity, parity_error);
1607
`undef MODULE
1608
parameter word_size = 32;
1609
parameter chunk_size = 8;
1610
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1611
input [word_size-1:0] data;
1612
input [word_size/chunk_size-1:0] parity;
1613
output parity_error;
1614 44 unneback
reg [word_size/chunk_size-1:0] error_flag;
1615 43 unneback
integer i,j;
1616
always @ (data or parity)
1617
for (i=0;i<word_size/chunk_size;i=i+1) begin
1618
    error_flag[i] = parity[i] ^ parity_type;
1619
    for (j=0;j<chunk_size;j=j+1) begin
1620 46 unneback
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
1621 43 unneback
    end
1622
end
1623
assign parity_error = |error_flag;
1624
endmodule
1625
 
1626 44 unneback
`endif//////////////////////////////////////////////////////////////////////
1627
////                                                              ////
1628
////  IO functions                                                ////
1629
////                                                              ////
1630
////  Description                                                 ////
1631
////  IO functions such as IOB flip-flops                         ////
1632
////                                                              ////
1633
////                                                              ////
1634
////  To Do:                                                      ////
1635
////   -                                                          ////
1636
////                                                              ////
1637
////  Author(s):                                                  ////
1638
////      - Michael Unneback, unneback@opencores.org              ////
1639
////        ORSoC AB                                              ////
1640
////                                                              ////
1641 18 unneback
//////////////////////////////////////////////////////////////////////
1642
////                                                              ////
1643 44 unneback
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1644
////                                                              ////
1645
//// This source file may be used and distributed without         ////
1646
//// restriction provided that this copyright statement is not    ////
1647
//// removed from the file and that any derivative work contains  ////
1648
//// the original copyright notice and the associated disclaimer. ////
1649
////                                                              ////
1650
//// This source file is free software; you can redistribute it   ////
1651
//// and/or modify it under the terms of the GNU Lesser General   ////
1652
//// Public License as published by the Free Software Foundation; ////
1653
//// either version 2.1 of the License, or (at your option) any   ////
1654
//// later version.                                               ////
1655
////                                                              ////
1656
//// This source is distributed in the hope that it will be       ////
1657
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1658
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1659
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1660
//// details.                                                     ////
1661
////                                                              ////
1662
//// You should have received a copy of the GNU Lesser General    ////
1663
//// Public License along with this source; if not, download it   ////
1664
//// from http://www.opencores.org/lgpl.shtml                     ////
1665
////                                                              ////
1666
//////////////////////////////////////////////////////////////////////
1667 136 unneback
`ifdef O_DFF
1668 45 unneback
`timescale 1ns/1ns
1669 44 unneback
`define MODULE o_dff
1670
module `BASE`MODULE (d_i, o_pad, clk, rst);
1671
`undef MODULE
1672
parameter width = 1;
1673 45 unneback
parameter reset_value = {width{1'b0}};
1674
input  [width-1:0]  d_i;
1675 44 unneback
output [width-1:0] o_pad;
1676
input clk, rst;
1677
wire [width-1:0] d_i_int `SYN_KEEP;
1678 45 unneback
reg  [width-1:0] o_pad_int;
1679 44 unneback
assign d_i_int = d_i;
1680
genvar i;
1681 45 unneback
generate
1682 136 unneback
for (i=0;i<width;i=i+1) begin : dffs
1683 44 unneback
    always @ (posedge clk or posedge rst)
1684
    if (rst)
1685 45 unneback
        o_pad_int[i] <= reset_value[i];
1686 44 unneback
    else
1687 45 unneback
        o_pad_int[i] <= d_i_int[i];
1688
    assign #1 o_pad[i] = o_pad_int[i];
1689 44 unneback
end
1690
endgenerate
1691
endmodule
1692
`endif
1693
 
1694 136 unneback
`ifdef IO_DFF_OE
1695 45 unneback
`timescale 1ns/1ns
1696 44 unneback
`define MODULE io_dff_oe
1697
module `BASE`MODULE ( d_i, d_o, oe, io_pad, clk, rst);
1698
`undef MODULE
1699
parameter width = 1;
1700 140 unneback
parameter reset_value = 1'b0;
1701 44 unneback
input  [width-1:0] d_o;
1702
output reg [width-1:0] d_i;
1703
input oe;
1704
inout [width-1:0] io_pad;
1705
input clk, rst;
1706
wire [width-1:0] oe_d `SYN_KEEP;
1707
reg [width-1:0] oe_q;
1708
reg [width-1:0] d_o_q;
1709
assign oe_d = {width{oe}};
1710
genvar i;
1711
generate
1712 136 unneback
for (i=0;i<width;i=i+1) begin : dffs
1713 44 unneback
    always @ (posedge clk or posedge rst)
1714
    if (rst)
1715
        oe_q[i] <= 1'b0;
1716
    else
1717
        oe_q[i] <= oe_d[i];
1718
    always @ (posedge clk or posedge rst)
1719
    if (rst)
1720 140 unneback
        d_o_q[i] <= reset_value;
1721 44 unneback
    else
1722
        d_o_q[i] <= d_o[i];
1723
    always @ (posedge clk or posedge rst)
1724
    if (rst)
1725 140 unneback
        d_i[i] <= reset_value;
1726 44 unneback
    else
1727
        d_i[i] <= io_pad[i];
1728 45 unneback
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
1729 44 unneback
end
1730
endgenerate
1731
endmodule
1732
`endif
1733 136 unneback
 
1734
`ifdef O_DDR
1735
`ifdef ALTERA
1736
`define MODULE o_ddr
1737
module `BASE`MODULE (d_h_i, d_l_i, o_pad, clk, rst);
1738
`undef MODULE
1739
parameter width = 1;
1740
input  [width-1:0] d_h_i, d_l_i;
1741
output [width-1:0] o_pad;
1742
input clk, rst;
1743
genvar i;
1744
generate
1745
for (i=0;i<width;i=i+1) begin : ddr
1746
    ddio_out ddio_out0( .aclr(rst), .datain_h(d_h_i[i]), .datain_l(d_l_i[i]), .outclock(clk), .dataout(o_pad[i]) );
1747
end
1748
endgenerate
1749
endmodule
1750
`else
1751
`define MODULE o_ddr
1752
module `BASE`MODULE (d_h_i, d_l_i, o_pad, clk, rst);
1753
`undef MODULE
1754
parameter width = 1;
1755
input  [width-1:0] d_h_i, d_l_i;
1756
output [width-1:0] o_pad;
1757
input clk, rst;
1758
reg [width-1:0] ff1;
1759
reg [width-1:0] ff2;
1760
genvar i;
1761
generate
1762
for (i=0;i<width;i=i+1) begin : ddr
1763
    always @ (posedge clk or posedge rst)
1764
    if (rst)
1765
        ff1[i] <= 1'b0;
1766
    else
1767
        ff1[i] <= d_h_i[i];
1768
    always @ (posedge clk or posedge rst)
1769
    if (rst)
1770
        ff2[i] <= 1'b0;
1771
    else
1772
        ff2[i] <= d_l_i[i];
1773
    assign o_pad = (clk) ? ff1 : ff2;
1774
end
1775
endgenerate
1776
endmodule
1777
`endif
1778
`endif
1779
 
1780
`ifdef O_CLK
1781
`define MODULE o_clk
1782
module `BASE`MODULE ( clk_o_pad, clk, rst);
1783
`undef MODULE
1784
input clk, rst;
1785
output clk_o_pad;
1786
`define MODULE o_ddr
1787
`BASE`MODULE o_ddr0( .d_h_i(1'b1), .d_l_i(1'b0), .o_pad(clk_o_pad), .clk(clk), .rst(rst));
1788
`undef MODULE
1789
endmodule
1790
`endif`ifdef CNT_BIN
1791 44 unneback
//////////////////////////////////////////////////////////////////////
1792
////                                                              ////
1793 6 unneback
////  Versatile counter                                           ////
1794
////                                                              ////
1795
////  Description                                                 ////
1796
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1797
////  counter                                                     ////
1798
////                                                              ////
1799
////  To Do:                                                      ////
1800
////   - add LFSR with more taps                                  ////
1801
////                                                              ////
1802
////  Author(s):                                                  ////
1803
////      - Michael Unneback, unneback@opencores.org              ////
1804
////        ORSoC AB                                              ////
1805
////                                                              ////
1806
//////////////////////////////////////////////////////////////////////
1807
////                                                              ////
1808
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1809
////                                                              ////
1810
//// This source file may be used and distributed without         ////
1811
//// restriction provided that this copyright statement is not    ////
1812
//// removed from the file and that any derivative work contains  ////
1813
//// the original copyright notice and the associated disclaimer. ////
1814
////                                                              ////
1815
//// This source file is free software; you can redistribute it   ////
1816
//// and/or modify it under the terms of the GNU Lesser General   ////
1817
//// Public License as published by the Free Software Foundation; ////
1818
//// either version 2.1 of the License, or (at your option) any   ////
1819
//// later version.                                               ////
1820
////                                                              ////
1821
//// This source is distributed in the hope that it will be       ////
1822
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1823
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1824
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1825
//// details.                                                     ////
1826
////                                                              ////
1827
//// You should have received a copy of the GNU Lesser General    ////
1828
//// Public License along with this source; if not, download it   ////
1829
//// from http://www.opencores.org/lgpl.shtml                     ////
1830
////                                                              ////
1831
//////////////////////////////////////////////////////////////////////
1832
 
1833
// binary counter
1834 22 unneback
 
1835 40 unneback
`define MODULE cnt_bin
1836
module `BASE`MODULE (
1837
`undef MODULE
1838
 q, rst, clk);
1839
 
1840 22 unneback
   parameter length = 4;
1841
   output [length:1] q;
1842
   input rst;
1843
   input clk;
1844
 
1845
   parameter clear_value = 0;
1846
   parameter set_value = 1;
1847
   parameter wrap_value = 0;
1848
   parameter level1_value = 15;
1849
 
1850
   reg  [length:1] qi;
1851
   wire [length:1] q_next;
1852
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1853
 
1854
   always @ (posedge clk or posedge rst)
1855
     if (rst)
1856
       qi <= {length{1'b0}};
1857
     else
1858
       qi <= q_next;
1859
 
1860
   assign q = qi;
1861
 
1862
endmodule
1863 40 unneback
`endif
1864
`ifdef CNT_BIN_CLEAR
1865 22 unneback
//////////////////////////////////////////////////////////////////////
1866
////                                                              ////
1867
////  Versatile counter                                           ////
1868
////                                                              ////
1869
////  Description                                                 ////
1870
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1871
////  counter                                                     ////
1872
////                                                              ////
1873
////  To Do:                                                      ////
1874
////   - add LFSR with more taps                                  ////
1875
////                                                              ////
1876
////  Author(s):                                                  ////
1877
////      - Michael Unneback, unneback@opencores.org              ////
1878
////        ORSoC AB                                              ////
1879
////                                                              ////
1880
//////////////////////////////////////////////////////////////////////
1881
////                                                              ////
1882
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1883
////                                                              ////
1884
//// This source file may be used and distributed without         ////
1885
//// restriction provided that this copyright statement is not    ////
1886
//// removed from the file and that any derivative work contains  ////
1887
//// the original copyright notice and the associated disclaimer. ////
1888
////                                                              ////
1889
//// This source file is free software; you can redistribute it   ////
1890
//// and/or modify it under the terms of the GNU Lesser General   ////
1891
//// Public License as published by the Free Software Foundation; ////
1892
//// either version 2.1 of the License, or (at your option) any   ////
1893
//// later version.                                               ////
1894
////                                                              ////
1895
//// This source is distributed in the hope that it will be       ////
1896
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1897
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1898
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1899
//// details.                                                     ////
1900
////                                                              ////
1901
//// You should have received a copy of the GNU Lesser General    ////
1902
//// Public License along with this source; if not, download it   ////
1903
//// from http://www.opencores.org/lgpl.shtml                     ////
1904
////                                                              ////
1905
//////////////////////////////////////////////////////////////////////
1906
 
1907
// binary counter
1908
 
1909 40 unneback
`define MODULE cnt_bin_clear
1910
module `BASE`MODULE (
1911
`undef MODULE
1912
 clear, q, rst, clk);
1913
 
1914 22 unneback
   parameter length = 4;
1915
   input clear;
1916
   output [length:1] q;
1917
   input rst;
1918
   input clk;
1919
 
1920
   parameter clear_value = 0;
1921
   parameter set_value = 1;
1922
   parameter wrap_value = 0;
1923
   parameter level1_value = 15;
1924
 
1925
   reg  [length:1] qi;
1926
   wire [length:1] q_next;
1927
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1928
 
1929
   always @ (posedge clk or posedge rst)
1930
     if (rst)
1931
       qi <= {length{1'b0}};
1932
     else
1933
       qi <= q_next;
1934
 
1935
   assign q = qi;
1936
 
1937
endmodule
1938 40 unneback
`endif
1939
`ifdef CNT_BIN_CE
1940 22 unneback
//////////////////////////////////////////////////////////////////////
1941
////                                                              ////
1942
////  Versatile counter                                           ////
1943
////                                                              ////
1944
////  Description                                                 ////
1945
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1946
////  counter                                                     ////
1947
////                                                              ////
1948
////  To Do:                                                      ////
1949
////   - add LFSR with more taps                                  ////
1950
////                                                              ////
1951
////  Author(s):                                                  ////
1952
////      - Michael Unneback, unneback@opencores.org              ////
1953
////        ORSoC AB                                              ////
1954
////                                                              ////
1955
//////////////////////////////////////////////////////////////////////
1956
////                                                              ////
1957
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1958
////                                                              ////
1959
//// This source file may be used and distributed without         ////
1960
//// restriction provided that this copyright statement is not    ////
1961
//// removed from the file and that any derivative work contains  ////
1962
//// the original copyright notice and the associated disclaimer. ////
1963
////                                                              ////
1964
//// This source file is free software; you can redistribute it   ////
1965
//// and/or modify it under the terms of the GNU Lesser General   ////
1966
//// Public License as published by the Free Software Foundation; ////
1967
//// either version 2.1 of the License, or (at your option) any   ////
1968
//// later version.                                               ////
1969
////                                                              ////
1970
//// This source is distributed in the hope that it will be       ////
1971
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1972
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1973
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1974
//// details.                                                     ////
1975
////                                                              ////
1976
//// You should have received a copy of the GNU Lesser General    ////
1977
//// Public License along with this source; if not, download it   ////
1978
//// from http://www.opencores.org/lgpl.shtml                     ////
1979
////                                                              ////
1980
//////////////////////////////////////////////////////////////////////
1981
 
1982
// binary counter
1983 6 unneback
 
1984 40 unneback
`define MODULE cnt_bin_ce
1985
module `BASE`MODULE (
1986
`undef MODULE
1987
 cke, q, rst, clk);
1988
 
1989 6 unneback
   parameter length = 4;
1990
   input cke;
1991
   output [length:1] q;
1992
   input rst;
1993
   input clk;
1994
 
1995
   parameter clear_value = 0;
1996
   parameter set_value = 1;
1997
   parameter wrap_value = 0;
1998
   parameter level1_value = 15;
1999
 
2000
   reg  [length:1] qi;
2001
   wire [length:1] q_next;
2002
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2003
 
2004
   always @ (posedge clk or posedge rst)
2005
     if (rst)
2006
       qi <= {length{1'b0}};
2007
     else
2008
     if (cke)
2009
       qi <= q_next;
2010
 
2011
   assign q = qi;
2012
 
2013
endmodule
2014 40 unneback
`endif
2015
`ifdef CNT_BIN_CE_CLEAR
2016 6 unneback
//////////////////////////////////////////////////////////////////////
2017
////                                                              ////
2018
////  Versatile counter                                           ////
2019
////                                                              ////
2020
////  Description                                                 ////
2021
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2022
////  counter                                                     ////
2023
////                                                              ////
2024
////  To Do:                                                      ////
2025
////   - add LFSR with more taps                                  ////
2026
////                                                              ////
2027
////  Author(s):                                                  ////
2028
////      - Michael Unneback, unneback@opencores.org              ////
2029
////        ORSoC AB                                              ////
2030
////                                                              ////
2031
//////////////////////////////////////////////////////////////////////
2032
////                                                              ////
2033
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2034
////                                                              ////
2035
//// This source file may be used and distributed without         ////
2036
//// restriction provided that this copyright statement is not    ////
2037
//// removed from the file and that any derivative work contains  ////
2038
//// the original copyright notice and the associated disclaimer. ////
2039
////                                                              ////
2040
//// This source file is free software; you can redistribute it   ////
2041
//// and/or modify it under the terms of the GNU Lesser General   ////
2042
//// Public License as published by the Free Software Foundation; ////
2043
//// either version 2.1 of the License, or (at your option) any   ////
2044
//// later version.                                               ////
2045
////                                                              ////
2046
//// This source is distributed in the hope that it will be       ////
2047
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2048
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2049
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2050
//// details.                                                     ////
2051
////                                                              ////
2052
//// You should have received a copy of the GNU Lesser General    ////
2053
//// Public License along with this source; if not, download it   ////
2054
//// from http://www.opencores.org/lgpl.shtml                     ////
2055
////                                                              ////
2056
//////////////////////////////////////////////////////////////////////
2057
 
2058
// binary counter
2059
 
2060 40 unneback
`define MODULE cnt_bin_ce_clear
2061
module `BASE`MODULE (
2062
`undef MODULE
2063
 clear, cke, q, rst, clk);
2064
 
2065 6 unneback
   parameter length = 4;
2066
   input clear;
2067
   input cke;
2068
   output [length:1] q;
2069
   input rst;
2070
   input clk;
2071
 
2072
   parameter clear_value = 0;
2073
   parameter set_value = 1;
2074
   parameter wrap_value = 0;
2075
   parameter level1_value = 15;
2076
 
2077
   reg  [length:1] qi;
2078
   wire [length:1] q_next;
2079
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
2080
 
2081
   always @ (posedge clk or posedge rst)
2082
     if (rst)
2083
       qi <= {length{1'b0}};
2084
     else
2085
     if (cke)
2086
       qi <= q_next;
2087
 
2088
   assign q = qi;
2089
 
2090
endmodule
2091 40 unneback
`endif
2092
`ifdef CNT_BIN_CE_CLEAR_L1_L2
2093 6 unneback
//////////////////////////////////////////////////////////////////////
2094
////                                                              ////
2095
////  Versatile counter                                           ////
2096
////                                                              ////
2097
////  Description                                                 ////
2098
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2099
////  counter                                                     ////
2100
////                                                              ////
2101
////  To Do:                                                      ////
2102
////   - add LFSR with more taps                                  ////
2103
////                                                              ////
2104
////  Author(s):                                                  ////
2105
////      - Michael Unneback, unneback@opencores.org              ////
2106
////        ORSoC AB                                              ////
2107
////                                                              ////
2108
//////////////////////////////////////////////////////////////////////
2109
////                                                              ////
2110
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2111
////                                                              ////
2112
//// This source file may be used and distributed without         ////
2113
//// restriction provided that this copyright statement is not    ////
2114
//// removed from the file and that any derivative work contains  ////
2115
//// the original copyright notice and the associated disclaimer. ////
2116
////                                                              ////
2117
//// This source file is free software; you can redistribute it   ////
2118
//// and/or modify it under the terms of the GNU Lesser General   ////
2119
//// Public License as published by the Free Software Foundation; ////
2120
//// either version 2.1 of the License, or (at your option) any   ////
2121
//// later version.                                               ////
2122
////                                                              ////
2123
//// This source is distributed in the hope that it will be       ////
2124
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2125
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2126
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2127
//// details.                                                     ////
2128
////                                                              ////
2129
//// You should have received a copy of the GNU Lesser General    ////
2130
//// Public License along with this source; if not, download it   ////
2131
//// from http://www.opencores.org/lgpl.shtml                     ////
2132
////                                                              ////
2133
//////////////////////////////////////////////////////////////////////
2134
 
2135
// binary counter
2136 29 unneback
 
2137 40 unneback
`define MODULE cnt_bin_ce_clear_l1_l2
2138
module `BASE`MODULE (
2139
`undef MODULE
2140
 clear, cke, q, level1, level2, rst, clk);
2141
 
2142 29 unneback
   parameter length = 4;
2143
   input clear;
2144
   input cke;
2145
   output [length:1] q;
2146
   output reg level1;
2147
   output reg level2;
2148
   input rst;
2149
   input clk;
2150
 
2151
   parameter clear_value = 0;
2152
   parameter set_value = 1;
2153 30 unneback
   parameter wrap_value = 15;
2154
   parameter level1_value = 8;
2155
   parameter level2_value = 15;
2156 29 unneback
 
2157
   wire rew;
2158 30 unneback
   assign rew = 1'b0;
2159 29 unneback
   reg  [length:1] qi;
2160
   wire [length:1] q_next;
2161
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
2162
 
2163
   always @ (posedge clk or posedge rst)
2164
     if (rst)
2165
       qi <= {length{1'b0}};
2166
     else
2167
     if (cke)
2168
       qi <= q_next;
2169
 
2170
   assign q = qi;
2171
 
2172
 
2173
    always @ (posedge clk or posedge rst)
2174
    if (rst)
2175
        level1 <= 1'b0;
2176
    else
2177
    if (cke)
2178
    if (clear)
2179
        level1 <= 1'b0;
2180
    else if (q_next == level1_value)
2181
        level1 <= 1'b1;
2182
    else if (qi == level1_value & rew)
2183
        level1 <= 1'b0;
2184
 
2185
    always @ (posedge clk or posedge rst)
2186
    if (rst)
2187
        level2 <= 1'b0;
2188
    else
2189
    if (cke)
2190
    if (clear)
2191
        level2 <= 1'b0;
2192
    else if (q_next == level2_value)
2193
        level2 <= 1'b1;
2194
    else if (qi == level2_value & rew)
2195
        level2 <= 1'b0;
2196
endmodule
2197 40 unneback
`endif
2198
`ifdef CNT_BIN_CE_CLEAR_SET_REW
2199 29 unneback
//////////////////////////////////////////////////////////////////////
2200
////                                                              ////
2201
////  Versatile counter                                           ////
2202
////                                                              ////
2203
////  Description                                                 ////
2204
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2205
////  counter                                                     ////
2206
////                                                              ////
2207
////  To Do:                                                      ////
2208
////   - add LFSR with more taps                                  ////
2209
////                                                              ////
2210
////  Author(s):                                                  ////
2211
////      - Michael Unneback, unneback@opencores.org              ////
2212
////        ORSoC AB                                              ////
2213
////                                                              ////
2214
//////////////////////////////////////////////////////////////////////
2215
////                                                              ////
2216
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2217
////                                                              ////
2218
//// This source file may be used and distributed without         ////
2219
//// restriction provided that this copyright statement is not    ////
2220
//// removed from the file and that any derivative work contains  ////
2221
//// the original copyright notice and the associated disclaimer. ////
2222
////                                                              ////
2223
//// This source file is free software; you can redistribute it   ////
2224
//// and/or modify it under the terms of the GNU Lesser General   ////
2225
//// Public License as published by the Free Software Foundation; ////
2226
//// either version 2.1 of the License, or (at your option) any   ////
2227
//// later version.                                               ////
2228
////                                                              ////
2229
//// This source is distributed in the hope that it will be       ////
2230
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2231
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2232
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2233
//// details.                                                     ////
2234
////                                                              ////
2235
//// You should have received a copy of the GNU Lesser General    ////
2236
//// Public License along with this source; if not, download it   ////
2237
//// from http://www.opencores.org/lgpl.shtml                     ////
2238
////                                                              ////
2239
//////////////////////////////////////////////////////////////////////
2240
 
2241
// binary counter
2242 6 unneback
 
2243 40 unneback
`define MODULE cnt_bin_ce_clear_set_rew
2244
module `BASE`MODULE (
2245
`undef MODULE
2246
 clear, set, cke, rew, q, rst, clk);
2247
 
2248 6 unneback
   parameter length = 4;
2249
   input clear;
2250
   input set;
2251
   input cke;
2252
   input rew;
2253
   output [length:1] q;
2254
   input rst;
2255
   input clk;
2256
 
2257
   parameter clear_value = 0;
2258
   parameter set_value = 1;
2259
   parameter wrap_value = 0;
2260
   parameter level1_value = 15;
2261
 
2262
   reg  [length:1] qi;
2263
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2264
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
2265
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
2266
   assign q_next = rew ? q_next_rew : q_next_fw;
2267
 
2268
   always @ (posedge clk or posedge rst)
2269
     if (rst)
2270
       qi <= {length{1'b0}};
2271
     else
2272
     if (cke)
2273
       qi <= q_next;
2274
 
2275
   assign q = qi;
2276
 
2277
endmodule
2278 40 unneback
`endif
2279
`ifdef CNT_BIN_CE_REW_L1
2280 6 unneback
//////////////////////////////////////////////////////////////////////
2281
////                                                              ////
2282
////  Versatile counter                                           ////
2283
////                                                              ////
2284
////  Description                                                 ////
2285
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2286
////  counter                                                     ////
2287
////                                                              ////
2288
////  To Do:                                                      ////
2289
////   - add LFSR with more taps                                  ////
2290
////                                                              ////
2291
////  Author(s):                                                  ////
2292
////      - Michael Unneback, unneback@opencores.org              ////
2293
////        ORSoC AB                                              ////
2294
////                                                              ////
2295
//////////////////////////////////////////////////////////////////////
2296
////                                                              ////
2297
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2298
////                                                              ////
2299
//// This source file may be used and distributed without         ////
2300
//// restriction provided that this copyright statement is not    ////
2301
//// removed from the file and that any derivative work contains  ////
2302
//// the original copyright notice and the associated disclaimer. ////
2303
////                                                              ////
2304
//// This source file is free software; you can redistribute it   ////
2305
//// and/or modify it under the terms of the GNU Lesser General   ////
2306
//// Public License as published by the Free Software Foundation; ////
2307
//// either version 2.1 of the License, or (at your option) any   ////
2308
//// later version.                                               ////
2309
////                                                              ////
2310
//// This source is distributed in the hope that it will be       ////
2311
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2312
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2313
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2314
//// details.                                                     ////
2315
////                                                              ////
2316
//// You should have received a copy of the GNU Lesser General    ////
2317
//// Public License along with this source; if not, download it   ////
2318
//// from http://www.opencores.org/lgpl.shtml                     ////
2319
////                                                              ////
2320
//////////////////////////////////////////////////////////////////////
2321
 
2322
// binary counter
2323
 
2324 40 unneback
`define MODULE cnt_bin_ce_rew_l1
2325
module `BASE`MODULE (
2326
`undef MODULE
2327
 cke, rew, level1, rst, clk);
2328
 
2329 6 unneback
   parameter length = 4;
2330
   input cke;
2331
   input rew;
2332
   output reg level1;
2333
   input rst;
2334
   input clk;
2335
 
2336
   parameter clear_value = 0;
2337
   parameter set_value = 1;
2338
   parameter wrap_value = 1;
2339
   parameter level1_value = 15;
2340
 
2341 29 unneback
   wire clear;
2342 30 unneback
   assign clear = 1'b0;
2343 6 unneback
   reg  [length:1] qi;
2344
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2345
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2346
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2347
   assign q_next = rew ? q_next_rew : q_next_fw;
2348
 
2349
   always @ (posedge clk or posedge rst)
2350
     if (rst)
2351
       qi <= {length{1'b0}};
2352
     else
2353
     if (cke)
2354
       qi <= q_next;
2355
 
2356
 
2357
 
2358
    always @ (posedge clk or posedge rst)
2359
    if (rst)
2360
        level1 <= 1'b0;
2361
    else
2362
    if (cke)
2363 29 unneback
    if (clear)
2364
        level1 <= 1'b0;
2365
    else if (q_next == level1_value)
2366 6 unneback
        level1 <= 1'b1;
2367
    else if (qi == level1_value & rew)
2368
        level1 <= 1'b0;
2369
endmodule
2370 40 unneback
`endif
2371
`ifdef CNT_BIN_CE_REW_ZQ_L1
2372 6 unneback
//////////////////////////////////////////////////////////////////////
2373
////                                                              ////
2374
////  Versatile counter                                           ////
2375
////                                                              ////
2376
////  Description                                                 ////
2377
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2378
////  counter                                                     ////
2379
////                                                              ////
2380
////  To Do:                                                      ////
2381
////   - add LFSR with more taps                                  ////
2382
////                                                              ////
2383
////  Author(s):                                                  ////
2384
////      - Michael Unneback, unneback@opencores.org              ////
2385
////        ORSoC AB                                              ////
2386
////                                                              ////
2387
//////////////////////////////////////////////////////////////////////
2388
////                                                              ////
2389
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2390
////                                                              ////
2391
//// This source file may be used and distributed without         ////
2392
//// restriction provided that this copyright statement is not    ////
2393
//// removed from the file and that any derivative work contains  ////
2394
//// the original copyright notice and the associated disclaimer. ////
2395
////                                                              ////
2396
//// This source file is free software; you can redistribute it   ////
2397
//// and/or modify it under the terms of the GNU Lesser General   ////
2398
//// Public License as published by the Free Software Foundation; ////
2399
//// either version 2.1 of the License, or (at your option) any   ////
2400
//// later version.                                               ////
2401
////                                                              ////
2402
//// This source is distributed in the hope that it will be       ////
2403
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2404
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2405
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2406
//// details.                                                     ////
2407
////                                                              ////
2408
//// You should have received a copy of the GNU Lesser General    ////
2409
//// Public License along with this source; if not, download it   ////
2410
//// from http://www.opencores.org/lgpl.shtml                     ////
2411
////                                                              ////
2412
//////////////////////////////////////////////////////////////////////
2413
 
2414 25 unneback
// binary counter
2415
 
2416 40 unneback
`define MODULE cnt_bin_ce_rew_zq_l1
2417
module `BASE`MODULE (
2418
`undef MODULE
2419
 cke, rew, zq, level1, rst, clk);
2420
 
2421 25 unneback
   parameter length = 4;
2422
   input cke;
2423
   input rew;
2424
   output reg zq;
2425
   output reg level1;
2426
   input rst;
2427
   input clk;
2428
 
2429
   parameter clear_value = 0;
2430
   parameter set_value = 1;
2431
   parameter wrap_value = 1;
2432
   parameter level1_value = 15;
2433
 
2434 29 unneback
   wire clear;
2435 30 unneback
   assign clear = 1'b0;
2436 25 unneback
   reg  [length:1] qi;
2437
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2438
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2439
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2440
   assign q_next = rew ? q_next_rew : q_next_fw;
2441
 
2442
   always @ (posedge clk or posedge rst)
2443
     if (rst)
2444
       qi <= {length{1'b0}};
2445
     else
2446
     if (cke)
2447
       qi <= q_next;
2448
 
2449
 
2450
 
2451
   always @ (posedge clk or posedge rst)
2452
     if (rst)
2453
       zq <= 1'b1;
2454
     else
2455
     if (cke)
2456
       zq <= q_next == {length{1'b0}};
2457
 
2458
    always @ (posedge clk or posedge rst)
2459
    if (rst)
2460
        level1 <= 1'b0;
2461
    else
2462
    if (cke)
2463 29 unneback
    if (clear)
2464
        level1 <= 1'b0;
2465
    else if (q_next == level1_value)
2466 25 unneback
        level1 <= 1'b1;
2467
    else if (qi == level1_value & rew)
2468
        level1 <= 1'b0;
2469
endmodule
2470 40 unneback
`endif
2471
`ifdef CNT_BIN_CE_REW_Q_ZQ_L1
2472 25 unneback
//////////////////////////////////////////////////////////////////////
2473
////                                                              ////
2474
////  Versatile counter                                           ////
2475
////                                                              ////
2476
////  Description                                                 ////
2477
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2478
////  counter                                                     ////
2479
////                                                              ////
2480
////  To Do:                                                      ////
2481
////   - add LFSR with more taps                                  ////
2482
////                                                              ////
2483
////  Author(s):                                                  ////
2484
////      - Michael Unneback, unneback@opencores.org              ////
2485
////        ORSoC AB                                              ////
2486
////                                                              ////
2487
//////////////////////////////////////////////////////////////////////
2488
////                                                              ////
2489
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2490
////                                                              ////
2491
//// This source file may be used and distributed without         ////
2492
//// restriction provided that this copyright statement is not    ////
2493
//// removed from the file and that any derivative work contains  ////
2494
//// the original copyright notice and the associated disclaimer. ////
2495
////                                                              ////
2496
//// This source file is free software; you can redistribute it   ////
2497
//// and/or modify it under the terms of the GNU Lesser General   ////
2498
//// Public License as published by the Free Software Foundation; ////
2499
//// either version 2.1 of the License, or (at your option) any   ////
2500
//// later version.                                               ////
2501
////                                                              ////
2502
//// This source is distributed in the hope that it will be       ////
2503
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2504
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2505
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2506
//// details.                                                     ////
2507
////                                                              ////
2508
//// You should have received a copy of the GNU Lesser General    ////
2509
//// Public License along with this source; if not, download it   ////
2510
//// from http://www.opencores.org/lgpl.shtml                     ////
2511
////                                                              ////
2512
//////////////////////////////////////////////////////////////////////
2513
 
2514
// binary counter
2515
 
2516 40 unneback
`define MODULE cnt_bin_ce_rew_q_zq_l1
2517
module `BASE`MODULE (
2518
`undef MODULE
2519
 cke, rew, q, zq, level1, rst, clk);
2520
 
2521 25 unneback
   parameter length = 4;
2522
   input cke;
2523
   input rew;
2524
   output [length:1] q;
2525
   output reg zq;
2526
   output reg level1;
2527
   input rst;
2528
   input clk;
2529
 
2530
   parameter clear_value = 0;
2531
   parameter set_value = 1;
2532
   parameter wrap_value = 1;
2533
   parameter level1_value = 15;
2534
 
2535 29 unneback
   wire clear;
2536 30 unneback
   assign clear = 1'b0;
2537 25 unneback
   reg  [length:1] qi;
2538
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2539
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2540
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2541
   assign q_next = rew ? q_next_rew : q_next_fw;
2542
 
2543
   always @ (posedge clk or posedge rst)
2544
     if (rst)
2545
       qi <= {length{1'b0}};
2546
     else
2547
     if (cke)
2548
       qi <= q_next;
2549
 
2550
   assign q = qi;
2551
 
2552
 
2553
   always @ (posedge clk or posedge rst)
2554
     if (rst)
2555
       zq <= 1'b1;
2556
     else
2557
     if (cke)
2558
       zq <= q_next == {length{1'b0}};
2559
 
2560
    always @ (posedge clk or posedge rst)
2561
    if (rst)
2562
        level1 <= 1'b0;
2563
    else
2564
    if (cke)
2565 29 unneback
    if (clear)
2566
        level1 <= 1'b0;
2567
    else if (q_next == level1_value)
2568 25 unneback
        level1 <= 1'b1;
2569
    else if (qi == level1_value & rew)
2570
        level1 <= 1'b0;
2571
endmodule
2572 40 unneback
`endif
2573
`ifdef CNT_LFSR_ZQ
2574 25 unneback
//////////////////////////////////////////////////////////////////////
2575
////                                                              ////
2576
////  Versatile counter                                           ////
2577
////                                                              ////
2578
////  Description                                                 ////
2579
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2580
////  counter                                                     ////
2581
////                                                              ////
2582
////  To Do:                                                      ////
2583
////   - add LFSR with more taps                                  ////
2584
////                                                              ////
2585
////  Author(s):                                                  ////
2586
////      - Michael Unneback, unneback@opencores.org              ////
2587
////        ORSoC AB                                              ////
2588
////                                                              ////
2589
//////////////////////////////////////////////////////////////////////
2590
////                                                              ////
2591
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2592
////                                                              ////
2593
//// This source file may be used and distributed without         ////
2594
//// restriction provided that this copyright statement is not    ////
2595
//// removed from the file and that any derivative work contains  ////
2596
//// the original copyright notice and the associated disclaimer. ////
2597
////                                                              ////
2598
//// This source file is free software; you can redistribute it   ////
2599
//// and/or modify it under the terms of the GNU Lesser General   ////
2600
//// Public License as published by the Free Software Foundation; ////
2601
//// either version 2.1 of the License, or (at your option) any   ////
2602
//// later version.                                               ////
2603
////                                                              ////
2604
//// This source is distributed in the hope that it will be       ////
2605
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2606
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2607
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2608
//// details.                                                     ////
2609
////                                                              ////
2610
//// You should have received a copy of the GNU Lesser General    ////
2611
//// Public License along with this source; if not, download it   ////
2612
//// from http://www.opencores.org/lgpl.shtml                     ////
2613
////                                                              ////
2614
//////////////////////////////////////////////////////////////////////
2615
 
2616 6 unneback
// LFSR counter
2617
 
2618 40 unneback
`define MODULE cnt_lfsr_zq
2619
module `BASE`MODULE (
2620
`undef MODULE
2621
 zq, rst, clk);
2622
 
2623 6 unneback
   parameter length = 4;
2624
   output reg zq;
2625
   input rst;
2626
   input clk;
2627
 
2628
   parameter clear_value = 0;
2629
   parameter set_value = 1;
2630
   parameter wrap_value = 8;
2631
   parameter level1_value = 15;
2632
 
2633
   reg  [length:1] qi;
2634
   reg lfsr_fb;
2635
   wire [length:1] q_next;
2636
   reg [32:1] polynom;
2637
   integer i;
2638
 
2639
   always @ (qi)
2640
   begin
2641
        case (length)
2642
         2: polynom = 32'b11;                               // 0x3
2643
         3: polynom = 32'b110;                              // 0x6
2644
         4: polynom = 32'b1100;                             // 0xC
2645
         5: polynom = 32'b10100;                            // 0x14
2646
         6: polynom = 32'b110000;                           // 0x30
2647
         7: polynom = 32'b1100000;                          // 0x60
2648
         8: polynom = 32'b10111000;                         // 0xb8
2649
         9: polynom = 32'b100010000;                        // 0x110
2650
        10: polynom = 32'b1001000000;                       // 0x240
2651
        11: polynom = 32'b10100000000;                      // 0x500
2652
        12: polynom = 32'b100000101001;                     // 0x829
2653
        13: polynom = 32'b1000000001100;                    // 0x100C
2654
        14: polynom = 32'b10000000010101;                   // 0x2015
2655
        15: polynom = 32'b110000000000000;                  // 0x6000
2656
        16: polynom = 32'b1101000000001000;                 // 0xD008
2657
        17: polynom = 32'b10010000000000000;                // 0x12000
2658
        18: polynom = 32'b100000010000000000;               // 0x20400
2659
        19: polynom = 32'b1000000000000100011;              // 0x40023
2660 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2661 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2662
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2663
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2664
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2665
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2666
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2667
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2668
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2669
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2670
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2671
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2672
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2673
        default: polynom = 32'b0;
2674
        endcase
2675
        lfsr_fb = qi[length];
2676
        for (i=length-1; i>=1; i=i-1) begin
2677
            if (polynom[i])
2678
                lfsr_fb = lfsr_fb  ~^ qi[i];
2679
        end
2680
    end
2681
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2682
 
2683
   always @ (posedge clk or posedge rst)
2684
     if (rst)
2685
       qi <= {length{1'b0}};
2686
     else
2687
       qi <= q_next;
2688
 
2689
 
2690
 
2691
   always @ (posedge clk or posedge rst)
2692
     if (rst)
2693
       zq <= 1'b1;
2694
     else
2695
       zq <= q_next == {length{1'b0}};
2696
endmodule
2697 40 unneback
`endif
2698 75 unneback
`ifdef CNT_LFSR_CE
2699
//////////////////////////////////////////////////////////////////////
2700
////                                                              ////
2701
////  Versatile counter                                           ////
2702
////                                                              ////
2703
////  Description                                                 ////
2704
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2705
////  counter                                                     ////
2706
////                                                              ////
2707
////  To Do:                                                      ////
2708
////   - add LFSR with more taps                                  ////
2709
////                                                              ////
2710
////  Author(s):                                                  ////
2711
////      - Michael Unneback, unneback@opencores.org              ////
2712
////        ORSoC AB                                              ////
2713
////                                                              ////
2714
//////////////////////////////////////////////////////////////////////
2715
////                                                              ////
2716
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2717
////                                                              ////
2718
//// This source file may be used and distributed without         ////
2719
//// restriction provided that this copyright statement is not    ////
2720
//// removed from the file and that any derivative work contains  ////
2721
//// the original copyright notice and the associated disclaimer. ////
2722
////                                                              ////
2723
//// This source file is free software; you can redistribute it   ////
2724
//// and/or modify it under the terms of the GNU Lesser General   ////
2725
//// Public License as published by the Free Software Foundation; ////
2726
//// either version 2.1 of the License, or (at your option) any   ////
2727
//// later version.                                               ////
2728
////                                                              ////
2729
//// This source is distributed in the hope that it will be       ////
2730
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2731
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2732
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2733
//// details.                                                     ////
2734
////                                                              ////
2735
//// You should have received a copy of the GNU Lesser General    ////
2736
//// Public License along with this source; if not, download it   ////
2737
//// from http://www.opencores.org/lgpl.shtml                     ////
2738
////                                                              ////
2739
//////////////////////////////////////////////////////////////////////
2740
 
2741
// LFSR counter
2742
 
2743
`define MODULE cnt_lfsr_ce
2744
module `BASE`MODULE (
2745
`undef MODULE
2746
 cke, zq, rst, clk);
2747
 
2748
   parameter length = 4;
2749
   input cke;
2750
   output reg zq;
2751
   input rst;
2752
   input clk;
2753
 
2754
   parameter clear_value = 0;
2755
   parameter set_value = 1;
2756
   parameter wrap_value = 0;
2757
   parameter level1_value = 15;
2758
 
2759
   reg  [length:1] qi;
2760
   reg lfsr_fb;
2761
   wire [length:1] q_next;
2762
   reg [32:1] polynom;
2763
   integer i;
2764
 
2765
   always @ (qi)
2766
   begin
2767
        case (length)
2768
         2: polynom = 32'b11;                               // 0x3
2769
         3: polynom = 32'b110;                              // 0x6
2770
         4: polynom = 32'b1100;                             // 0xC
2771
         5: polynom = 32'b10100;                            // 0x14
2772
         6: polynom = 32'b110000;                           // 0x30
2773
         7: polynom = 32'b1100000;                          // 0x60
2774
         8: polynom = 32'b10111000;                         // 0xb8
2775
         9: polynom = 32'b100010000;                        // 0x110
2776
        10: polynom = 32'b1001000000;                       // 0x240
2777
        11: polynom = 32'b10100000000;                      // 0x500
2778
        12: polynom = 32'b100000101001;                     // 0x829
2779
        13: polynom = 32'b1000000001100;                    // 0x100C
2780
        14: polynom = 32'b10000000010101;                   // 0x2015
2781
        15: polynom = 32'b110000000000000;                  // 0x6000
2782
        16: polynom = 32'b1101000000001000;                 // 0xD008
2783
        17: polynom = 32'b10010000000000000;                // 0x12000
2784
        18: polynom = 32'b100000010000000000;               // 0x20400
2785
        19: polynom = 32'b1000000000000100011;              // 0x40023
2786
        20: polynom = 32'b10010000000000000000;             // 0x90000
2787
        21: polynom = 32'b101000000000000000000;            // 0x140000
2788
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2789
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2790
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2791
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2792
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2793
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2794
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2795
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2796
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2797
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2798
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2799
        default: polynom = 32'b0;
2800
        endcase
2801
        lfsr_fb = qi[length];
2802
        for (i=length-1; i>=1; i=i-1) begin
2803
            if (polynom[i])
2804
                lfsr_fb = lfsr_fb  ~^ qi[i];
2805
        end
2806
    end
2807
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2808
 
2809
   always @ (posedge clk or posedge rst)
2810
     if (rst)
2811
       qi <= {length{1'b0}};
2812
     else
2813
     if (cke)
2814
       qi <= q_next;
2815
 
2816
 
2817
 
2818
   always @ (posedge clk or posedge rst)
2819
     if (rst)
2820
       zq <= 1'b1;
2821
     else
2822
     if (cke)
2823
       zq <= q_next == {length{1'b0}};
2824
endmodule
2825
`endif
2826 40 unneback
`ifdef CNT_LFSR_CE_ZQ
2827 6 unneback
//////////////////////////////////////////////////////////////////////
2828
////                                                              ////
2829
////  Versatile counter                                           ////
2830
////                                                              ////
2831
////  Description                                                 ////
2832
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2833
////  counter                                                     ////
2834