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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Blame information for rev 140

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Line No. Rev Author Line
1 40 unneback
`ifndef BASE
2
`define BASE vl_
3
`endif
4
 
5 60 unneback
// default SYN_KEEP definition
6
`define SYN_KEEP /*synthesis syn_keep = 1*/
7
 
8 44 unneback
`ifdef ACTEL
9 60 unneback
`undef SYN_KEEP
10 44 unneback
`define SYN_KEEP /*synthesis syn_keep = 1*/
11
`endif
12
 
13 98 unneback
`ifdef ACTEL
14
    // ACTEL FPGA should not use logic to handle rw collision
15
    `define SYN_NO_RW_CHECK /*synthesis syn_ramstyle = "no_rw_check"*/
16
`else
17
    `define SYN_NO_RW_CHECK
18
`endif
19
 
20 40 unneback
`ifdef ALL
21
 
22
`define GBUF
23
`define SYNC_RST
24
`define PLL
25
 
26
`define MULTS
27
`define MULTS18X18
28
`define MULT
29 140 unneback
`define ARITH_UNIT
30 40 unneback
`define SHIFT_UNIT_32
31
`define LOGIC_UNIT
32 140 unneback
`define COUNT_UNIT
33
`define EXT_UNIT
34 40 unneback
 
35
`define CNT_SHREG_WRAP
36
`define CNT_SHREG_CE_WRAP
37 105 unneback
`define CNT_SHREG_CLEAR
38 40 unneback
`define CNT_SHREG_CE_CLEAR
39
`define CNT_SHREG_CE_CLEAR_WRAP
40
 
41 139 unneback
`define CNT_BIN
42
`define CNT_BIN_CE
43
`define CNT_BIN_CLEAR
44
`define CNT_BIN_CE_CLEAR
45
`define CNT_BIN_CE_CLEAR_L1_L2
46
`define CNT_BIN_CE_CLEAR_SET_REW
47
`define CNT_BIN_CE_REW_L1
48
`define CNT_BIN_CE_REW_ZQ_L1
49
`define CNT_BIN_CE_REW_Q_ZQ_L1
50
`define CNT_GRAY
51
`define CNT_GRAY_CE
52
`define CNT_GRAY_CE_BIN
53
`define CNT_LFSR_ZQ
54
`define CNT_LFSR_CE
55
`define CNT_LFSR_CE_CLEAR_Q
56
`define CNT_LFSR_CE_Q
57
`define CNT_LFSR_CE_ZQ
58
`define CNT_LFSR_CE_Q_ZQ
59
`define CNT_LFSR_CE_REW_L1
60
 
61 40 unneback
`define MUX_ANDOR
62
`define MUX2_ANDOR
63
`define MUX3_ANDOR
64
`define MUX4_ANDOR
65
`define MUX5_ANDOR
66
`define MUX6_ANDOR
67 43 unneback
`define PARITY
68 40 unneback
 
69
`define ROM_INIT
70
`define RAM
71
`define RAM_BE
72
`define DPRAM_1R1W
73
`define DPRAM_2R1W
74 100 unneback
`define DPRAM_1R2W
75 40 unneback
`define DPRAM_2R2W
76 75 unneback
`define DPRAM_BE_2R2W
77 40 unneback
`define FIFO_1R1W_FILL_LEVEL_SYNC
78
`define FIFO_2R2W_SYNC_SIMPLEX
79
`define FIFO_CMP_ASYNC
80
`define FIFO_1R1W_ASYNC
81
`define FIFO_2R2W_ASYNC
82
`define FIFO_2R2W_ASYNC_SIMPLEX
83 48 unneback
`define REG_FILE
84 40 unneback
 
85
`define DFF
86
`define DFF_ARRAY
87
`define DFF_CE
88
`define DFF_CE_CLEAR
89
`define DF_CE_SET
90
`define SPR
91
`define SRP
92
`define DFF_SR
93
`define LATCH
94
`define SHREG
95
`define SHREG_CE
96
`define DELAY
97
`define DELAY_EMPTYFLAG
98 94 unneback
`define PULSE2TOGGLE
99
`define TOGGLE2PULSE
100
`define SYNCHRONIZER
101
`define CDC
102 40 unneback
 
103 75 unneback
`define WB3AVALON_BRIDGE
104 40 unneback
`define WB3WB3_BRIDGE
105
`define WB3_ARBITER_TYPE1
106 83 unneback
`define WB_ADR_INC
107 101 unneback
`define WB_RAM
108 103 unneback
`define WB_SHADOW_RAM
109 48 unneback
`define WB_B4_ROM
110 40 unneback
`define WB_BOOT_ROM
111
`define WB_DPRAM
112 101 unneback
`define WB_CACHE
113 103 unneback
`define WB_AVALON_BRIDGE
114
`define WB_AVALON_MEM_CACHE
115 136 unneback
`define WB_SDR_SDRAM_CTRL
116 40 unneback
 
117 44 unneback
`define IO_DFF_OE
118
`define O_DFF
119 136 unneback
`define O_DDR
120
`define O_CLK
121 44 unneback
 
122 40 unneback
`endif
123
 
124 136 unneback
///////////////////////////////////////
125
// dependencies
126
///////////////////////////////////////
127
 
128 40 unneback
`ifdef PLL
129
`ifndef SYNC_RST
130
`define SYNC_RST
131
`endif
132
`endif
133
 
134
`ifdef SYNC_RST
135
`ifndef GBUF
136
`define GBUF
137
`endif
138
`endif
139
 
140 136 unneback
`ifdef WB_SDR_SDRAM_CTRL
141
`ifndef WB_SHADOW_RAM
142
`define WB_SHADOW_RAM
143
`endif
144
`ifndef WB_CACHE
145
`define WB_CACHE
146
`endif
147
`ifndef WB_SDR_SDRAM
148
`define WB_SDR_SDRAM
149
`endif
150
`ifndef IO_DFF_OE
151
`define IO_DFF_OE
152
`endif
153
`ifndef O_DFF
154
`define O_DFF
155
`endif
156
`ifndef O_CLK
157
`define O_CLK
158
`endif
159
`endif
160
 
161
`ifdef WB_SDR_SDRAM
162
`ifndef CNT_SHREG_CLEAR
163
`define CNT_SHREG_CLEAR
164
`endif
165
`ifndef CNT_LFSR_ZQ
166
`define CNT_LFSR_ZQ
167
`endif
168
`ifndef DELAY_EMPTYFLAG
169
`define DELAY_EMPTYFLAG
170
`endif
171
`endif
172
 
173 108 unneback
`ifdef WB_DPRAM
174 92 unneback
`ifndef WB_ADR_INC
175
`define WB_ADR_INC
176 40 unneback
`endif
177 92 unneback
`ifndef DPRAM_BE_2R2W
178
`define DPRAM_BE_2R2W
179 40 unneback
`endif
180
`endif
181
 
182
`ifdef WB3_ARBITER_TYPE1
183 42 unneback
`ifndef SPR
184
`define SPR
185
`endif
186 40 unneback
`ifndef MUX_ANDOR
187
`define MUX_ANDOR
188
`endif
189
`endif
190
 
191 76 unneback
`ifdef WB3AVALON_BRIDGE
192
`ifndef WB3WB3_BRIDGE
193
`define WB3WB3_BRIDGE
194
`endif
195
`endif
196
 
197 40 unneback
`ifdef WB3WB3_BRIDGE
198
`ifndef CNT_SHREG_CE_CLEAR
199
`define CNT_SHREG_CE_CLEAR
200
`endif
201
`ifndef DFF
202
`define DFF
203
`endif
204
`ifndef DFF_CE
205
`define DFF_CE
206
`endif
207
`ifndef CNT_SHREG_CE_CLEAR
208
`define CNT_SHREG_CE_CLEAR
209
`endif
210
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
211
`define FIFO_2R2W_ASYNC_SIMPLEX
212
`endif
213
`endif
214
 
215 103 unneback
 
216
`ifdef WB_AVALON_MEM_CACHE
217
`ifndef WB_SHADOW_RAM
218
`define WB_SHADOW_RAM
219
`endif
220
`ifndef WB_CACHE
221
`define WB_CACHE
222
`endif
223
`ifndef WB_AVALON_BRIDGE
224
`define WB_AVALON_BRIDGE
225
`endif
226
`endif
227
 
228 101 unneback
`ifdef WB_CACHE
229 100 unneback
`ifndef RAM
230
`define RAM
231
`endif
232
`ifndef WB_ADR_INC
233
`define WB_ADR_INC
234
`endif
235
`ifndef DPRAM_1R1W
236
`define DPRAM_1R1W
237
`endif
238
`ifndef DPRAM_1R2W
239
`define DPRAM_1R2W
240
`endif
241
`ifndef DPRAM_BE_2R2W
242
`define DPRAM_BE_2R2W
243
`endif
244
`ifndef CDC
245
`define CDC
246
`endif
247 136 unneback
`ifndef O_DFF
248
`define O_DFF
249 100 unneback
`endif
250 136 unneback
`ifndef O_CLK
251
`define O_CLK
252
`endif
253
`endif
254 103 unneback
 
255
`ifdef WB_SHADOW_RAM
256 115 unneback
`ifndef WB_RAM
257
`define WB_RAM
258 103 unneback
`endif
259
`endif
260
 
261
`ifdef WB_RAM
262
`ifndef WB_ADR_INC
263
`define WB_ADR_INC
264
`endif
265 114 unneback
`ifndef RAM_BE
266
`define RAM_BE
267 103 unneback
`endif
268 114 unneback
`endif
269
 
270 40 unneback
`ifdef MULTS18X18
271
`ifndef MULTS
272
`define MULTS
273
`endif
274
`endif
275
 
276
`ifdef SHIFT_UNIT_32
277
`ifndef MULTS
278
`define MULTS
279
`endif
280
`endif
281
 
282
`ifdef MUX2_ANDOR
283
`ifndef MUX_ANDOR
284
`define MUX_ANDOR
285
`endif
286
`endif
287
 
288
`ifdef MUX3_ANDOR
289
`ifndef MUX_ANDOR
290
`define MUX_ANDOR
291
`endif
292
`endif
293
 
294
`ifdef MUX4_ANDOR
295
`ifndef MUX_ANDOR
296
`define MUX_ANDOR
297
`endif
298
`endif
299
 
300
`ifdef MUX5_ANDOR
301
`ifndef MUX_ANDOR
302
`define MUX_ANDOR
303
`endif
304
`endif
305
 
306
`ifdef MUX6_ANDOR
307
`ifndef MUX_ANDOR
308
`define MUX_ANDOR
309
`endif
310
`endif
311
 
312
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
313
`ifndef CNT_BIN_CE
314
`define CNT_BIN_CE
315
`endif
316
`ifndef DPRAM_1R1W
317
`define DPRAM_1R1W
318
`endif
319
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
320
`define CNT_BIN_CE_REW_Q_ZQ_L1
321
`endif
322
`endif
323
 
324
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
325
`ifndef CNT_LFSR_CE
326
`define CNT_LFSR_CE
327
`endif
328
`ifndef DPRAM_2R2W
329
`define DPRAM_2R2W
330
`endif
331
`ifndef CNT_BIN_CE_REW_ZQ_L1
332
`define CNT_BIN_CE_REW_ZQ_L1
333
`endif
334
`endif
335
 
336
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
337
`ifndef CNT_GRAY_CE_BIN
338
`define CNT_GRAY_CE_BIN
339
`endif
340
`ifndef DPRAM_2R2W
341
`define DPRAM_2R2W
342
`endif
343
`ifndef FIFO_CMP_ASYNC
344
`define FIFO_CMP_ASYNC
345
`endif
346
`endif
347
 
348
`ifdef FIFO_2R2W_ASYNC
349
`ifndef FIFO_1R1W_ASYNC
350
`define FIFO_1R1W_ASYNC
351
`endif
352
`endif
353
 
354
`ifdef FIFO_1R1W_ASYNC
355
`ifndef CNT_GRAY_CE_BIN
356
`define CNT_GRAY_CE_BIN
357
`endif
358
`ifndef DPRAM_1R1W
359
`define DPRAM_1R1W
360
`endif
361
`ifndef FIFO_CMP_ASYNC
362
`define FIFO_CMP_ASYNC
363
`endif
364
`endif
365
 
366
`ifdef FIFO_CMP_ASYNC
367
`ifndef DFF_SR
368
`define DFF_SR
369
`endif
370
`ifndef DFF
371
`define DFF
372
`endif
373
`endif
374 48 unneback
 
375
`ifdef REG_FILE
376
`ifndef DPRAM_1R1W
377
`define DPRAM_1R1W
378
`endif
379
`endif
380 97 unneback
 
381 98 unneback
`ifdef CDC
382
`ifndef PULSE2TOGGLE
383
`define PULSE2TOGGLE
384
`endif
385
`ifndef TOGGLE2PULSE
386
`define TOGGLE2PULSE
387
`endif
388
`ifndef SYNCHRONIZER
389
`define SYNCHRONIZER
390
`endif
391
`endif
392
 
393 136 unneback
`ifdef O_CLK
394
`ifndef O_DDR
395
`define O_DDR
396
`endif
397
`endif
398
 
399 97 unneback
// size to width
400 100 unneback
`define SIZE2WIDTH_EXPR = (`SIZE2WIDTH==1) ? 0 : (`SIZE2WIDTH==2) ? 1 : (`SIZE2WIDTH==4) ? 2 : (`SIZE2WIDTH==8) ? 3 : (`SIZE2WIDTH==16) ? 4 : (`SIZE2WIDTH==32) ? 5 : (`SIZE2WIDTH==64) ? 6 : (`SIZE2WIDTH==128) ? 7 : 8;
401 62 unneback
//////////////////////////////////////////////////////////////////////
402 6 unneback
////                                                              ////
403
////  Versatile library, clock and reset                          ////
404
////                                                              ////
405
////  Description                                                 ////
406
////  Logic related to clock and reset                            ////
407
////                                                              ////
408
////                                                              ////
409
////  To Do:                                                      ////
410
////   - add more different registers                             ////
411
////                                                              ////
412
////  Author(s):                                                  ////
413
////      - Michael Unneback, unneback@opencores.org              ////
414
////        ORSoC AB                                              ////
415
////                                                              ////
416
//////////////////////////////////////////////////////////////////////
417
////                                                              ////
418
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
419
////                                                              ////
420
//// This source file may be used and distributed without         ////
421
//// restriction provided that this copyright statement is not    ////
422
//// removed from the file and that any derivative work contains  ////
423
//// the original copyright notice and the associated disclaimer. ////
424
////                                                              ////
425
//// This source file is free software; you can redistribute it   ////
426
//// and/or modify it under the terms of the GNU Lesser General   ////
427
//// Public License as published by the Free Software Foundation; ////
428
//// either version 2.1 of the License, or (at your option) any   ////
429
//// later version.                                               ////
430
////                                                              ////
431
//// This source is distributed in the hope that it will be       ////
432
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
433
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
434
//// PURPOSE.  See the GNU Lesser General Public License for more ////
435
//// details.                                                     ////
436
////                                                              ////
437
//// You should have received a copy of the GNU Lesser General    ////
438
//// Public License along with this source; if not, download it   ////
439
//// from http://www.opencores.org/lgpl.shtml                     ////
440
////                                                              ////
441
//////////////////////////////////////////////////////////////////////
442
 
443 48 unneback
`ifdef ACTEL
444
`ifdef GBUF
445
`timescale 1 ns/100 ps
446 6 unneback
// Global buffer
447
// usage:
448
// use to enable global buffers for high fan out signals such as clock and reset
449
// Version: 8.4 8.4.0.33
450
module gbuf(GL,CLK);
451
output GL;
452
input  CLK;
453
 
454
    wire GND;
455
 
456
    GND GND_1_net(.Y(GND));
457
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
458
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
459
 
460
endmodule
461
`timescale 1 ns/1 ns
462 40 unneback
`define MODULE gbuf
463
module `BASE`MODULE ( i, o);
464
`undef MODULE
465 6 unneback
input i;
466
output o;
467
`ifdef SIM_GBUF
468
assign o=i;
469
`else
470
gbuf gbuf_i0 ( .CLK(i), .GL(o));
471
`endif
472
endmodule
473 40 unneback
`endif
474 33 unneback
 
475 6 unneback
`else
476 33 unneback
 
477 40 unneback
`ifdef ALTERA
478
`ifdef GBUF
479 21 unneback
//altera
480 40 unneback
`define MODULE gbuf
481
module `BASE`MODULE ( i, o);
482
`undef MODULE
483 33 unneback
input i;
484
output o;
485
assign o = i;
486
endmodule
487 40 unneback
`endif
488 33 unneback
 
489 6 unneback
`else
490
 
491 40 unneback
`ifdef GBUF
492 6 unneback
`timescale 1 ns/100 ps
493 40 unneback
`define MODULE
494
module `BASE`MODULE ( i, o);
495
`undef MODULE
496 6 unneback
input i;
497
output o;
498
assign o = i;
499
endmodule
500 40 unneback
`endif
501 6 unneback
`endif // ALTERA
502
`endif //ACTEL
503
 
504 40 unneback
`ifdef SYNC_RST
505 6 unneback
// sync reset
506 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
507 6 unneback
// output active high global reset sync with two DFFs 
508
`timescale 1 ns/100 ps
509 40 unneback
`define MODULE sync_rst
510
module `BASE`MODULE ( rst_n_i, rst_o, clk);
511
`undef MODULE
512 6 unneback
input rst_n_i, clk;
513
output rst_o;
514 18 unneback
reg [1:0] tmp;
515 6 unneback
always @ (posedge clk or negedge rst_n_i)
516
if (!rst_n_i)
517 17 unneback
        tmp <= 2'b11;
518 6 unneback
else
519 33 unneback
        tmp <= {1'b0,tmp[1]};
520 40 unneback
`define MODULE gbuf
521
`BASE`MODULE buf_i0( .i(tmp[0]), .o(rst_o));
522
`undef MODULE
523 6 unneback
endmodule
524 40 unneback
`endif
525 6 unneback
 
526 40 unneback
`ifdef PLL
527 6 unneback
// vl_pll
528
`ifdef ACTEL
529 32 unneback
///////////////////////////////////////////////////////////////////////////////
530 17 unneback
`timescale 1 ps/1 ps
531 40 unneback
`define MODULE pll
532
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
533
`undef MODULE
534 6 unneback
parameter index = 0;
535
parameter number_of_clk = 1;
536 17 unneback
parameter period_time_0 = 20000;
537
parameter period_time_1 = 20000;
538
parameter period_time_2 = 20000;
539
parameter lock_delay = 2000000;
540 6 unneback
input clk_i, rst_n_i;
541
output lock;
542
output reg [0:number_of_clk-1] clk_o;
543
output [0:number_of_clk-1] rst_o;
544
 
545
`ifdef SIM_PLL
546
 
547
always
548
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
549
 
550
generate if (number_of_clk > 1)
551
always
552
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
553
endgenerate
554
 
555
generate if (number_of_clk > 2)
556
always
557
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
558
endgenerate
559
 
560
genvar i;
561
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
562
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
563
end
564
endgenerate
565
 
566
assign #lock_delay lock = rst_n_i;
567
 
568
endmodule
569
`else
570
generate if (number_of_clk==1 & index==0) begin
571
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
572
end
573
endgenerate // index==0
574
generate if (number_of_clk==1 & index==1) begin
575
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
576
end
577
endgenerate // index==1
578
generate if (number_of_clk==1 & index==2) begin
579
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
580
end
581
endgenerate // index==2
582
generate if (number_of_clk==1 & index==3) begin
583
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
584
end
585
endgenerate // index==0
586
 
587
generate if (number_of_clk==2 & index==0) begin
588
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
589
end
590
endgenerate // index==0
591
generate if (number_of_clk==2 & index==1) begin
592
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
593
end
594
endgenerate // index==1
595
generate if (number_of_clk==2 & index==2) begin
596
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
597
end
598
endgenerate // index==2
599
generate if (number_of_clk==2 & index==3) begin
600
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
601
end
602
endgenerate // index==0
603
 
604
generate if (number_of_clk==3 & index==0) begin
605
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
606
end
607
endgenerate // index==0
608
generate if (number_of_clk==3 & index==1) begin
609
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
610
end
611
endgenerate // index==1
612
generate if (number_of_clk==3 & index==2) begin
613
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
614
end
615
endgenerate // index==2
616
generate if (number_of_clk==3 & index==3) begin
617
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
618
end
619
endgenerate // index==0
620
 
621
genvar i;
622
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
623 40 unneback
`define MODULE sync_rst
624
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
625
`undef MODULE
626 6 unneback
end
627
endgenerate
628
endmodule
629
`endif
630 32 unneback
///////////////////////////////////////////////////////////////////////////////
631 6 unneback
 
632
`else
633
 
634 32 unneback
///////////////////////////////////////////////////////////////////////////////
635 6 unneback
`ifdef ALTERA
636
 
637 32 unneback
`timescale 1 ps/1 ps
638 40 unneback
`define MODULE pll
639
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
640
`undef MODULE
641 32 unneback
parameter index = 0;
642
parameter number_of_clk = 1;
643
parameter period_time_0 = 20000;
644
parameter period_time_1 = 20000;
645
parameter period_time_2 = 20000;
646
parameter period_time_3 = 20000;
647
parameter period_time_4 = 20000;
648
parameter lock_delay = 2000000;
649
input clk_i, rst_n_i;
650
output lock;
651
output reg [0:number_of_clk-1] clk_o;
652
output [0:number_of_clk-1] rst_o;
653
 
654
`ifdef SIM_PLL
655
 
656
always
657
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
658
 
659
generate if (number_of_clk > 1)
660
always
661
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
662
endgenerate
663
 
664
generate if (number_of_clk > 2)
665
always
666
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
667
endgenerate
668
 
669 33 unneback
generate if (number_of_clk > 3)
670 32 unneback
always
671
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
672
endgenerate
673
 
674 33 unneback
generate if (number_of_clk > 4)
675 32 unneback
always
676
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
677
endgenerate
678
 
679
genvar i;
680
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
681
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
682
end
683
endgenerate
684
 
685 33 unneback
//assign #lock_delay lock = rst_n_i;
686
assign lock = rst_n_i;
687 32 unneback
 
688
endmodule
689 6 unneback
`else
690
 
691 33 unneback
`ifdef VL_PLL0
692
`ifdef VL_PLL0_CLK1
693
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
694
`endif
695
`ifdef VL_PLL0_CLK2
696
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
697
`endif
698
`ifdef VL_PLL0_CLK3
699
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
700
`endif
701
`ifdef VL_PLL0_CLK4
702
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
703
`endif
704
`ifdef VL_PLL0_CLK5
705
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
706
`endif
707
`endif
708 32 unneback
 
709 33 unneback
`ifdef VL_PLL1
710
`ifdef VL_PLL1_CLK1
711
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
712
`endif
713
`ifdef VL_PLL1_CLK2
714
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
715
`endif
716
`ifdef VL_PLL1_CLK3
717
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
718
`endif
719
`ifdef VL_PLL1_CLK4
720
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
721
`endif
722
`ifdef VL_PLL1_CLK5
723
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
724
`endif
725
`endif
726 32 unneback
 
727 33 unneback
`ifdef VL_PLL2
728
`ifdef VL_PLL2_CLK1
729
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
730
`endif
731
`ifdef VL_PLL2_CLK2
732
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
733
`endif
734
`ifdef VL_PLL2_CLK3
735
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
736
`endif
737
`ifdef VL_PLL2_CLK4
738
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
739
`endif
740
`ifdef VL_PLL2_CLK5
741
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
742
`endif
743
`endif
744 32 unneback
 
745 33 unneback
`ifdef VL_PLL3
746
`ifdef VL_PLL3_CLK1
747
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
748
`endif
749
`ifdef VL_PLL3_CLK2
750
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
751
`endif
752
`ifdef VL_PLL3_CLK3
753
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
754
`endif
755
`ifdef VL_PLL3_CLK4
756
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
757
`endif
758
`ifdef VL_PLL3_CLK5
759
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
760
`endif
761
`endif
762 32 unneback
 
763
genvar i;
764
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
765 40 unneback
`define MODULE sync_rst
766
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
767
`undef MODULE
768 32 unneback
end
769
endgenerate
770
endmodule
771
`endif
772
///////////////////////////////////////////////////////////////////////////////
773
 
774
`else
775
 
776 6 unneback
// generic PLL
777 17 unneback
`timescale 1 ps/1 ps
778 40 unneback
`define MODULE pll
779
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
780
`undef MODULE
781 6 unneback
parameter index = 0;
782
parameter number_of_clk = 1;
783 140 unneback
parameter period_time = 20000;
784
parameter clk0_mult_by = 1;
785
parameter clk0_div_by  = 1;
786
parameter clk1_mult_by = 1;
787
parameter clk1_div_by  = 1;
788
parameter clk2_mult_by = 1;
789
parameter clk3_div_by  = 1;
790
parameter clk3_mult_by = 1;
791
parameter clk3_div_by  = 1;
792
parameter clk4_mult_by = 1;
793
parameter clk4_div_by  = 1;
794 6 unneback
input clk_i, rst_n_i;
795
output lock;
796
output reg [0:number_of_clk-1] clk_o;
797
 
798 140 unneback
initial
799
    clk_o = {number_of_clk{1'b0}};
800
 
801 6 unneback
always
802 140 unneback
    #((period_time*clk0_div_by/clk0_mult_by)/2) clk_o[0] <=  (!rst_n_i) ? 1'b0 : ~clk_o[0];
803 6 unneback
 
804
generate if (number_of_clk > 1)
805
always
806 140 unneback
    #((period_time*clk1_div_by/clk1_mult_by)/2) clk_o[1] <=  (!rst_n_i) ? 1'b0 : ~clk_o[1];
807 6 unneback
endgenerate
808
 
809
generate if (number_of_clk > 2)
810
always
811 140 unneback
    #((period_time*clk2_div_by/clk2_mult_by)/2) clk_o[2] <=  (!rst_n_i) ? 1'b0 : ~clk_o[2];
812 6 unneback
endgenerate
813
 
814 140 unneback
generate if (number_of_clk > 3)
815
always
816
    #((period_time*clk3_div_by/clk3_mult_by)/2) clk_o[3] <=  (!rst_n_i) ? 1'b0 : ~clk_o[3];
817 6 unneback
endgenerate
818
 
819 140 unneback
generate if (number_of_clk > 4)
820
always
821
    #((period_time*clk4_div_by/clk4_mult_by)/2) clk_o[4] <=  (!rst_n_i) ? 1'b0 : ~clk_o[4];
822
endgenerate
823
 
824 6 unneback
assign #lock_delay lock = rst_n_i;
825
 
826
endmodule
827
 
828
`endif //altera
829 17 unneback
`endif //actel
830 40 unneback
`undef MODULE
831
`endif//////////////////////////////////////////////////////////////////////
832 6 unneback
////                                                              ////
833
////  Versatile library, registers                                ////
834
////                                                              ////
835
////  Description                                                 ////
836
////  Different type of registers                                 ////
837
////                                                              ////
838
////                                                              ////
839
////  To Do:                                                      ////
840
////   - add more different registers                             ////
841
////                                                              ////
842
////  Author(s):                                                  ////
843
////      - Michael Unneback, unneback@opencores.org              ////
844
////        ORSoC AB                                              ////
845
////                                                              ////
846
//////////////////////////////////////////////////////////////////////
847
////                                                              ////
848
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
849
////                                                              ////
850
//// This source file may be used and distributed without         ////
851
//// restriction provided that this copyright statement is not    ////
852
//// removed from the file and that any derivative work contains  ////
853
//// the original copyright notice and the associated disclaimer. ////
854
////                                                              ////
855
//// This source file is free software; you can redistribute it   ////
856
//// and/or modify it under the terms of the GNU Lesser General   ////
857
//// Public License as published by the Free Software Foundation; ////
858
//// either version 2.1 of the License, or (at your option) any   ////
859
//// later version.                                               ////
860
////                                                              ////
861
//// This source is distributed in the hope that it will be       ////
862
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
863
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
864
//// PURPOSE.  See the GNU Lesser General Public License for more ////
865
//// details.                                                     ////
866
////                                                              ////
867
//// You should have received a copy of the GNU Lesser General    ////
868
//// Public License along with this source; if not, download it   ////
869
//// from http://www.opencores.org/lgpl.shtml                     ////
870
////                                                              ////
871
//////////////////////////////////////////////////////////////////////
872
 
873 40 unneback
`ifdef DFF
874
`define MODULE dff
875
module `BASE`MODULE ( d, q, clk, rst);
876
`undef MODULE
877 6 unneback
        parameter width = 1;
878 139 unneback
        parameter reset_value = {width{1'b0}};
879 6 unneback
 
880
        input [width-1:0] d;
881
        input clk, rst;
882
        output reg [width-1:0] q;
883
 
884
        always @ (posedge clk or posedge rst)
885
        if (rst)
886
                q <= reset_value;
887
        else
888
                q <= d;
889
 
890
endmodule
891 40 unneback
`endif
892 6 unneback
 
893 40 unneback
`ifdef DFF_ARRAY
894
`define MODULE dff_array
895
module `BASE`MODULE ( d, q, clk, rst);
896
`undef MODULE
897 6 unneback
 
898
        parameter width = 1;
899
        parameter depth = 2;
900
        parameter reset_value = 1'b0;
901
 
902
        input [width-1:0] d;
903
        input clk, rst;
904
        output [width-1:0] q;
905
        reg  [0:depth-1] q_tmp [width-1:0];
906
        integer i;
907
        always @ (posedge clk or posedge rst)
908
        if (rst) begin
909
            for (i=0;i<depth;i=i+1)
910
                q_tmp[i] <= {width{reset_value}};
911
        end else begin
912
            q_tmp[0] <= d;
913
            for (i=1;i<depth;i=i+1)
914
                q_tmp[i] <= q_tmp[i-1];
915
        end
916
 
917
    assign q = q_tmp[depth-1];
918
 
919
endmodule
920 40 unneback
`endif
921 6 unneback
 
922 40 unneback
`ifdef DFF_CE
923
`define MODULE dff_ce
924
module `BASE`MODULE ( d, ce, q, clk, rst);
925
`undef MODULE
926 6 unneback
 
927
        parameter width = 1;
928 139 unneback
        parameter reset_value = {width{1'b0}};
929 6 unneback
 
930
        input [width-1:0] d;
931
        input ce, clk, rst;
932
        output reg [width-1:0] q;
933
 
934
        always @ (posedge clk or posedge rst)
935
        if (rst)
936
                q <= reset_value;
937
        else
938
                if (ce)
939
                        q <= d;
940
 
941
endmodule
942 40 unneback
`endif
943 6 unneback
 
944 40 unneback
`ifdef DFF_CE_CLEAR
945
`define MODULE dff_ce_clear
946
module `BASE`MODULE ( d, ce, clear, q, clk, rst);
947
`undef MODULE
948 8 unneback
 
949
        parameter width = 1;
950 139 unneback
        parameter reset_value = {width{1'b0}};
951 8 unneback
 
952
        input [width-1:0] d;
953 10 unneback
        input ce, clear, clk, rst;
954 8 unneback
        output reg [width-1:0] q;
955
 
956
        always @ (posedge clk or posedge rst)
957
        if (rst)
958
            q <= reset_value;
959
        else
960
            if (ce)
961
                if (clear)
962
                    q <= {width{1'b0}};
963
                else
964
                    q <= d;
965
 
966
endmodule
967 40 unneback
`endif
968 8 unneback
 
969 40 unneback
`ifdef DF_CE_SET
970
`define MODULE dff_ce_set
971
module `BASE`MODULE ( d, ce, set, q, clk, rst);
972
`undef MODULE
973 24 unneback
 
974
        parameter width = 1;
975 139 unneback
        parameter reset_value = {width{1'b0}};
976 24 unneback
 
977
        input [width-1:0] d;
978
        input ce, set, clk, rst;
979
        output reg [width-1:0] q;
980
 
981
        always @ (posedge clk or posedge rst)
982
        if (rst)
983
            q <= reset_value;
984
        else
985
            if (ce)
986
                if (set)
987
                    q <= {width{1'b1}};
988
                else
989
                    q <= d;
990
 
991
endmodule
992 40 unneback
`endif
993 24 unneback
 
994 40 unneback
`ifdef SPR
995
`define MODULE spr
996
module `BASE`MODULE ( sp, r, q, clk, rst);
997
`undef MODULE
998
 
999 64 unneback
        //parameter width = 1;
1000
        parameter reset_value = 1'b0;
1001 29 unneback
 
1002
        input sp, r;
1003
        output reg q;
1004
        input clk, rst;
1005
 
1006
        always @ (posedge clk or posedge rst)
1007
        if (rst)
1008
            q <= reset_value;
1009
        else
1010
            if (sp)
1011
                q <= 1'b1;
1012
            else if (r)
1013
                q <= 1'b0;
1014
 
1015
endmodule
1016 40 unneback
`endif
1017 29 unneback
 
1018 40 unneback
`ifdef SRP
1019
`define MODULE srp
1020
module `BASE`MODULE ( s, rp, q, clk, rst);
1021
`undef MODULE
1022
 
1023 29 unneback
        parameter width = 1;
1024
        parameter reset_value = 0;
1025
 
1026
        input s, rp;
1027
        output reg q;
1028
        input clk, rst;
1029
 
1030
        always @ (posedge clk or posedge rst)
1031
        if (rst)
1032
            q <= reset_value;
1033
        else
1034
            if (rp)
1035
                q <= 1'b0;
1036
            else if (s)
1037
                q <= 1'b1;
1038
 
1039
endmodule
1040 40 unneback
`endif
1041 29 unneback
 
1042 40 unneback
`ifdef ALTERA
1043 29 unneback
 
1044 40 unneback
`ifdef DFF_SR
1045 6 unneback
// megafunction wizard: %LPM_FF%
1046
// GENERATION: STANDARD
1047
// VERSION: WM1.0
1048
// MODULE: lpm_ff 
1049
 
1050
// ============================================================
1051
// File Name: dff_sr.v
1052
// Megafunction Name(s):
1053
//                      lpm_ff
1054
//
1055
// Simulation Library Files(s):
1056
//                      lpm
1057
// ============================================================
1058
// ************************************************************
1059
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
1060
//
1061
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
1062
// ************************************************************
1063
 
1064
 
1065
//Copyright (C) 1991-2010 Altera Corporation
1066
//Your use of Altera Corporation's design tools, logic functions 
1067
//and other software and tools, and its AMPP partner logic 
1068
//functions, and any output files from any of the foregoing 
1069
//(including device programming or simulation files), and any 
1070
//associated documentation or information are expressly subject 
1071
//to the terms and conditions of the Altera Program License 
1072
//Subscription Agreement, Altera MegaCore Function License 
1073
//Agreement, or other applicable license agreement, including, 
1074
//without limitation, that your use is for the sole purpose of 
1075
//programming logic devices manufactured by Altera and sold by 
1076
//Altera or its authorized distributors.  Please refer to the 
1077
//applicable agreement for further details.
1078
 
1079
 
1080
// synopsys translate_off
1081
`timescale 1 ps / 1 ps
1082
// synopsys translate_on
1083 40 unneback
`define MODULE dff_sr
1084
module `BASE`MODULE (
1085
`undef MODULE
1086
 
1087 6 unneback
        aclr,
1088
        aset,
1089
        clock,
1090
        data,
1091
        q);
1092
 
1093
        input     aclr;
1094
        input     aset;
1095
        input     clock;
1096
        input     data;
1097
        output    q;
1098
 
1099
        wire [0:0] sub_wire0;
1100
        wire [0:0] sub_wire1 = sub_wire0[0:0];
1101
        wire  q = sub_wire1;
1102
        wire  sub_wire2 = data;
1103
        wire  sub_wire3 = sub_wire2;
1104
 
1105
        lpm_ff  lpm_ff_component (
1106
                                .aclr (aclr),
1107
                                .clock (clock),
1108
                                .data (sub_wire3),
1109
                                .aset (aset),
1110
                                .q (sub_wire0)
1111
                                // synopsys translate_off
1112
                                ,
1113
                                .aload (),
1114
                                .enable (),
1115
                                .sclr (),
1116
                                .sload (),
1117
                                .sset ()
1118
                                // synopsys translate_on
1119
                                );
1120
        defparam
1121
                lpm_ff_component.lpm_fftype = "DFF",
1122
                lpm_ff_component.lpm_type = "LPM_FF",
1123
                lpm_ff_component.lpm_width = 1;
1124
 
1125
 
1126
endmodule
1127
 
1128
// ============================================================
1129
// CNX file retrieval info
1130
// ============================================================
1131
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
1132
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
1133
// Retrieval info: PRIVATE: ASET NUMERIC "1"
1134
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
1135
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
1136
// Retrieval info: PRIVATE: DFF NUMERIC "1"
1137
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
1138
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
1139
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
1140
// Retrieval info: PRIVATE: SSET NUMERIC "0"
1141
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
1142
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
1143
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
1144
// Retrieval info: PRIVATE: nBit NUMERIC "1"
1145
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
1146
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
1147
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
1148
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
1149
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
1150
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
1151
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
1152
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
1153
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
1154
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
1155
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
1156
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
1157
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
1158
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
1159
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
1160
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
1161
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
1162
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
1163
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
1164
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
1165
// Retrieval info: LIB_FILE: lpm
1166 40 unneback
`endif
1167 6 unneback
 
1168
`else
1169
 
1170 40 unneback
`ifdef DFF_SR
1171
`define MODULE dff_sr
1172
module `BASE`MODULE ( aclr, aset, clock, data, q);
1173
`undef MODULE
1174 6 unneback
 
1175
    input         aclr;
1176
    input         aset;
1177
    input         clock;
1178
    input         data;
1179
    output reg    q;
1180
 
1181
   always @ (posedge clock or posedge aclr or posedge aset)
1182
     if (aclr)
1183
       q <= 1'b0;
1184
     else if (aset)
1185
       q <= 1'b1;
1186
     else
1187
       q <= data;
1188
 
1189
endmodule
1190 40 unneback
`endif
1191 6 unneback
 
1192
`endif
1193
 
1194
// LATCH
1195
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
1196
`ifdef ALTERA
1197 40 unneback
 
1198
`ifdef LATCH
1199
`define MODULE latch
1200
module `BASE`MODULE ( d, le, q, clk);
1201
`undef MODULE
1202 6 unneback
input d, le;
1203
output q;
1204
input clk;
1205
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
1206
endmodule
1207 40 unneback
`endif
1208
 
1209 6 unneback
`else
1210 40 unneback
 
1211
`ifdef LATCH
1212
`define MODULE latch
1213
module `BASE`MODULE ( d, le, q, clk);
1214
`undef MODULE
1215 6 unneback
input d, le;
1216 48 unneback
input clk;
1217
always @ (le or d)
1218 60 unneback
if (le)
1219 48 unneback
    d <= q;
1220 6 unneback
endmodule
1221 15 unneback
`endif
1222
 
1223 40 unneback
`endif
1224
 
1225
`ifdef SHREG
1226
`define MODULE shreg
1227
module `BASE`MODULE ( d, q, clk, rst);
1228
`undef MODULE
1229
 
1230 17 unneback
parameter depth = 10;
1231
input d;
1232
output q;
1233
input clk, rst;
1234
 
1235
reg [1:depth] dffs;
1236
 
1237
always @ (posedge clk or posedge rst)
1238
if (rst)
1239
    dffs <= {depth{1'b0}};
1240
else
1241
    dffs <= {d,dffs[1:depth-1]};
1242
assign q = dffs[depth];
1243
endmodule
1244 40 unneback
`endif
1245 17 unneback
 
1246 40 unneback
`ifdef SHREG_CE
1247
`define MODULE shreg_ce
1248
module `BASE`MODULE ( d, ce, q, clk, rst);
1249
`undef MODULE
1250 17 unneback
parameter depth = 10;
1251
input d, ce;
1252
output q;
1253
input clk, rst;
1254
 
1255
reg [1:depth] dffs;
1256
 
1257
always @ (posedge clk or posedge rst)
1258
if (rst)
1259
    dffs <= {depth{1'b0}};
1260
else
1261
    if (ce)
1262
        dffs <= {d,dffs[1:depth-1]};
1263
assign q = dffs[depth];
1264
endmodule
1265 40 unneback
`endif
1266 17 unneback
 
1267 40 unneback
`ifdef DELAY
1268
`define MODULE delay
1269
module `BASE`MODULE ( d, q, clk, rst);
1270
`undef MODULE
1271 15 unneback
parameter depth = 10;
1272
input d;
1273
output q;
1274
input clk, rst;
1275
 
1276
reg [1:depth] dffs;
1277
 
1278
always @ (posedge clk or posedge rst)
1279
if (rst)
1280
    dffs <= {depth{1'b0}};
1281
else
1282
    dffs <= {d,dffs[1:depth-1]};
1283
assign q = dffs[depth];
1284 17 unneback
endmodule
1285 40 unneback
`endif
1286 17 unneback
 
1287 40 unneback
`ifdef DELAY_EMPTYFLAG
1288
`define MODULE delay_emptyflag
1289 41 unneback
module `BASE`MODULE ( d, q, emptyflag, clk, rst);
1290 40 unneback
`undef MODULE
1291 17 unneback
parameter depth = 10;
1292
input d;
1293
output q, emptyflag;
1294
input clk, rst;
1295
 
1296
reg [1:depth] dffs;
1297
 
1298
always @ (posedge clk or posedge rst)
1299
if (rst)
1300
    dffs <= {depth{1'b0}};
1301
else
1302
    dffs <= {d,dffs[1:depth-1]};
1303
assign q = dffs[depth];
1304
assign emptyflag = !(|dffs);
1305
endmodule
1306 40 unneback
`endif
1307 75 unneback
 
1308 94 unneback
`ifdef PULSE2TOGGLE
1309 98 unneback
`define MODULE pulse2toggle
1310
module `BASE`MODULE ( pl, q, clk, rst);
1311 75 unneback
`undef MODULE
1312 94 unneback
input pl;
1313 98 unneback
output reg q;
1314 94 unneback
input clk, rst;
1315
always @ (posedge clk or posedge rst)
1316 75 unneback
if (rst)
1317 94 unneback
    q <= 1'b0;
1318 75 unneback
else
1319 94 unneback
    q <= pl ^ q;
1320
endmodule
1321
`endif
1322 75 unneback
 
1323 94 unneback
`ifdef TOGGLE2PULSE
1324 98 unneback
`define MODULE toggle2pulse
1325 94 unneback
module `BASE`MODULE (d, pl, clk, rst);
1326 97 unneback
`undef MODULE
1327 94 unneback
input d;
1328
output pl;
1329
input clk, rst;
1330
reg dff;
1331
always @ (posedge clk or posedge rst)
1332
if (rst)
1333
    dff <= 1'b0;
1334 75 unneback
else
1335 94 unneback
    dff <= d;
1336 98 unneback
assign pl = d ^ dff;
1337 94 unneback
endmodule
1338
`endif
1339 75 unneback
 
1340 94 unneback
`ifdef SYNCHRONIZER
1341
`define MODULE synchronizer
1342
module `BASE`MODULE (d, q, clk, rst);
1343
`undef MODULE
1344
input d;
1345
output reg q;
1346 116 unneback
input clk, rst;
1347 94 unneback
reg dff;
1348
always @ (posedge clk or posedge rst)
1349
if (rst)
1350 100 unneback
    {q,dff} <= 2'b00;
1351 75 unneback
else
1352 100 unneback
    {q,dff} <= {dff,d};
1353 94 unneback
endmodule
1354
`endif
1355 75 unneback
 
1356 94 unneback
`ifdef CDC
1357
`define MODULE cdc
1358 97 unneback
module `BASE`MODULE ( start_pl, take_it_pl, take_it_grant_pl, got_it_pl, clk_src, rst_src, clk_dst, rst_dst);
1359 94 unneback
`undef MODULE
1360
input start_pl;
1361
output take_it_pl;
1362
input take_it_grant_pl; // note: connect to take_it_pl to generate automatic ack
1363
output got_it_pl;
1364
input clk_src, rst_src;
1365
input clk_dst, rst_dst;
1366
wire take_it_tg, take_it_tg_sync;
1367
wire got_it_tg, got_it_tg_sync;
1368
// src -> dst
1369
`define MODULE pulse2toggle
1370
`BASE`MODULE p2t0 (
1371
`undef MODULE
1372
    .pl(start_pl),
1373
    .q(take_it_tg),
1374
    .clk(clk_src),
1375
    .rst(rst_src));
1376 75 unneback
 
1377 94 unneback
`define MODULE synchronizer
1378
`BASE`MODULE sync0 (
1379
`undef MODULE
1380
    .d(take_it_tg),
1381
    .q(take_it_tg_sync),
1382
    .clk(clk_dst),
1383
    .rst(rst_dst));
1384
 
1385
`define MODULE toggle2pulse
1386
`BASE`MODULE t2p0 (
1387
`undef MODULE
1388 100 unneback
    .d(take_it_tg_sync),
1389 94 unneback
    .pl(take_it_pl),
1390
    .clk(clk_dst),
1391
    .rst(rst_dst));
1392
 
1393
// dst -> src
1394
`define MODULE pulse2toggle
1395 98 unneback
`BASE`MODULE p2t1 (
1396 94 unneback
`undef MODULE
1397
    .pl(take_it_grant_pl),
1398
    .q(got_it_tg),
1399
    .clk(clk_dst),
1400
    .rst(rst_dst));
1401
 
1402
`define MODULE synchronizer
1403
`BASE`MODULE sync1 (
1404
`undef MODULE
1405
    .d(got_it_tg),
1406
    .q(got_it_tg_sync),
1407
    .clk(clk_src),
1408
    .rst(rst_src));
1409
 
1410
`define MODULE toggle2pulse
1411
`BASE`MODULE t2p1 (
1412
`undef MODULE
1413 100 unneback
    .d(got_it_tg_sync),
1414 94 unneback
    .pl(got_it_pl),
1415
    .clk(clk_src),
1416
    .rst(rst_src));
1417
 
1418 75 unneback
endmodule
1419
`endif
1420 17 unneback
//////////////////////////////////////////////////////////////////////
1421 6 unneback
////                                                              ////
1422 18 unneback
////  Logic functions                                             ////
1423
////                                                              ////
1424
////  Description                                                 ////
1425
////  Logic functions such as multiplexers                        ////
1426
////                                                              ////
1427
////                                                              ////
1428
////  To Do:                                                      ////
1429
////   -                                                          ////
1430
////                                                              ////
1431
////  Author(s):                                                  ////
1432
////      - Michael Unneback, unneback@opencores.org              ////
1433
////        ORSoC AB                                              ////
1434
////                                                              ////
1435
//////////////////////////////////////////////////////////////////////
1436
////                                                              ////
1437
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1438
////                                                              ////
1439
//// This source file may be used and distributed without         ////
1440
//// restriction provided that this copyright statement is not    ////
1441
//// removed from the file and that any derivative work contains  ////
1442
//// the original copyright notice and the associated disclaimer. ////
1443
////                                                              ////
1444
//// This source file is free software; you can redistribute it   ////
1445
//// and/or modify it under the terms of the GNU Lesser General   ////
1446
//// Public License as published by the Free Software Foundation; ////
1447
//// either version 2.1 of the License, or (at your option) any   ////
1448
//// later version.                                               ////
1449
////                                                              ////
1450
//// This source is distributed in the hope that it will be       ////
1451
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1452
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1453
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1454
//// details.                                                     ////
1455
////                                                              ////
1456
//// You should have received a copy of the GNU Lesser General    ////
1457
//// Public License along with this source; if not, download it   ////
1458
//// from http://www.opencores.org/lgpl.shtml                     ////
1459
////                                                              ////
1460
//////////////////////////////////////////////////////////////////////
1461 40 unneback
`ifdef MUX_ANDOR
1462
`define MODULE mux_andor
1463
module `BASE`MODULE ( a, sel, dout);
1464
`undef MODULE
1465 36 unneback
 
1466
parameter width = 32;
1467
parameter nr_of_ports = 4;
1468
 
1469
input [nr_of_ports*width-1:0] a;
1470
input [nr_of_ports-1:0] sel;
1471
output reg [width-1:0] dout;
1472
 
1473 38 unneback
integer i,j;
1474
 
1475 36 unneback
always @ (a, sel)
1476
begin
1477
    dout = a[width-1:0] & {width{sel[0]}};
1478 42 unneback
    for (i=1;i<nr_of_ports;i=i+1)
1479
        for (j=0;j<width;j=j+1)
1480
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
1481 36 unneback
end
1482
 
1483
endmodule
1484 40 unneback
`endif
1485 36 unneback
 
1486 40 unneback
`ifdef MUX2_ANDOR
1487
`define MODULE mux2_andor
1488
module `BASE`MODULE ( a1, a0, sel, dout);
1489
`undef MODULE
1490 18 unneback
 
1491 34 unneback
parameter width = 32;
1492 35 unneback
localparam nr_of_ports = 2;
1493 34 unneback
input [width-1:0] a1, a0;
1494
input [nr_of_ports-1:0] sel;
1495
output [width-1:0] dout;
1496
 
1497 40 unneback
`define MODULE mux_andor
1498
`BASE`MODULE
1499 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1500 36 unneback
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
1501 40 unneback
`undef MODULE
1502
 
1503 34 unneback
endmodule
1504 40 unneback
`endif
1505 34 unneback
 
1506 40 unneback
`ifdef MUX3_ANDOR
1507
`define MODULE mux3_andor
1508
module `BASE`MODULE ( a2, a1, a0, sel, dout);
1509
`undef MODULE
1510 34 unneback
 
1511
parameter width = 32;
1512 35 unneback
localparam nr_of_ports = 3;
1513 34 unneback
input [width-1:0] a2, a1, a0;
1514
input [nr_of_ports-1:0] sel;
1515
output [width-1:0] dout;
1516
 
1517 40 unneback
`define MODULE mux_andor
1518
`BASE`MODULE
1519 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1520 36 unneback
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
1521 40 unneback
`undef MODULE
1522 34 unneback
endmodule
1523 40 unneback
`endif
1524 34 unneback
 
1525 40 unneback
`ifdef MUX4_ANDOR
1526
`define MODULE mux4_andor
1527
module `BASE`MODULE ( a3, a2, a1, a0, sel, dout);
1528
`undef MODULE
1529 18 unneback
 
1530
parameter width = 32;
1531 35 unneback
localparam nr_of_ports = 4;
1532 18 unneback
input [width-1:0] a3, a2, a1, a0;
1533
input [nr_of_ports-1:0] sel;
1534 22 unneback
output [width-1:0] dout;
1535 18 unneback
 
1536 40 unneback
`define MODULE mux_andor
1537
`BASE`MODULE
1538 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1539 36 unneback
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
1540 40 unneback
`undef MODULE
1541 18 unneback
 
1542
endmodule
1543 40 unneback
`endif
1544 18 unneback
 
1545 40 unneback
`ifdef MUX5_ANDOR
1546
`define MODULE mux5_andor
1547
module `BASE`MODULE ( a4, a3, a2, a1, a0, sel, dout);
1548
`undef MODULE
1549 18 unneback
 
1550
parameter width = 32;
1551 35 unneback
localparam nr_of_ports = 5;
1552 18 unneback
input [width-1:0] a4, a3, a2, a1, a0;
1553
input [nr_of_ports-1:0] sel;
1554 22 unneback
output [width-1:0] dout;
1555 18 unneback
 
1556 40 unneback
`define MODULE mux_andor
1557
`BASE`MODULE
1558 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1559 36 unneback
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1560 40 unneback
`undef MODULE
1561 18 unneback
 
1562
endmodule
1563 40 unneback
`endif
1564 18 unneback
 
1565 40 unneback
`ifdef MUX6_ANDOR
1566
`define MODULE mux6_andor
1567
module `BASE`MODULE ( a5, a4, a3, a2, a1, a0, sel, dout);
1568
`undef MODULE
1569 18 unneback
 
1570
parameter width = 32;
1571 35 unneback
localparam nr_of_ports = 6;
1572 18 unneback
input [width-1:0] a5, a4, a3, a2, a1, a0;
1573
input [nr_of_ports-1:0] sel;
1574 22 unneback
output [width-1:0] dout;
1575 18 unneback
 
1576 40 unneback
`define MODULE mux_andor
1577
`BASE`MODULE
1578 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1579 36 unneback
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1580 40 unneback
`undef MODULE
1581 18 unneback
 
1582
endmodule
1583 40 unneback
`endif
1584 43 unneback
 
1585
`ifdef PARITY
1586
 
1587
`define MODULE parity_generate
1588
module `BASE`MODULE (data, parity);
1589
`undef MODULE
1590
parameter word_size = 32;
1591
parameter chunk_size = 8;
1592
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1593
input [word_size-1:0] data;
1594
output reg [word_size/chunk_size-1:0] parity;
1595
integer i,j;
1596
always @ (data)
1597
for (i=0;i<word_size/chunk_size;i=i+1) begin
1598
    parity[i] = parity_type;
1599
    for (j=0;j<chunk_size;j=j+1) begin
1600 46 unneback
        parity[i] = data[i*chunk_size+j] ^ parity[i];
1601 43 unneback
    end
1602
end
1603
endmodule
1604
 
1605
`define MODULE parity_check
1606
module `BASE`MODULE( data, parity, parity_error);
1607
`undef MODULE
1608
parameter word_size = 32;
1609
parameter chunk_size = 8;
1610
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1611
input [word_size-1:0] data;
1612
input [word_size/chunk_size-1:0] parity;
1613
output parity_error;
1614 44 unneback
reg [word_size/chunk_size-1:0] error_flag;
1615 43 unneback
integer i,j;
1616
always @ (data or parity)
1617
for (i=0;i<word_size/chunk_size;i=i+1) begin
1618
    error_flag[i] = parity[i] ^ parity_type;
1619
    for (j=0;j<chunk_size;j=j+1) begin
1620 46 unneback
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
1621 43 unneback
    end
1622
end
1623
assign parity_error = |error_flag;
1624
endmodule
1625
 
1626 44 unneback
`endif//////////////////////////////////////////////////////////////////////
1627
////                                                              ////
1628
////  IO functions                                                ////
1629
////                                                              ////
1630
////  Description                                                 ////
1631
////  IO functions such as IOB flip-flops                         ////
1632
////                                                              ////
1633
////                                                              ////
1634
////  To Do:                                                      ////
1635
////   -                                                          ////
1636
////                                                              ////
1637
////  Author(s):                                                  ////
1638
////      - Michael Unneback, unneback@opencores.org              ////
1639
////        ORSoC AB                                              ////
1640
////                                                              ////
1641 18 unneback
//////////////////////////////////////////////////////////////////////
1642
////                                                              ////
1643 44 unneback
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1644
////                                                              ////
1645
//// This source file may be used and distributed without         ////
1646
//// restriction provided that this copyright statement is not    ////
1647
//// removed from the file and that any derivative work contains  ////
1648
//// the original copyright notice and the associated disclaimer. ////
1649
////                                                              ////
1650
//// This source file is free software; you can redistribute it   ////
1651
//// and/or modify it under the terms of the GNU Lesser General   ////
1652
//// Public License as published by the Free Software Foundation; ////
1653
//// either version 2.1 of the License, or (at your option) any   ////
1654
//// later version.                                               ////
1655
////                                                              ////
1656
//// This source is distributed in the hope that it will be       ////
1657
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1658
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1659
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1660
//// details.                                                     ////
1661
////                                                              ////
1662
//// You should have received a copy of the GNU Lesser General    ////
1663
//// Public License along with this source; if not, download it   ////
1664
//// from http://www.opencores.org/lgpl.shtml                     ////
1665
////                                                              ////
1666
//////////////////////////////////////////////////////////////////////
1667 136 unneback
`ifdef O_DFF
1668 45 unneback
`timescale 1ns/1ns
1669 44 unneback
`define MODULE o_dff
1670
module `BASE`MODULE (d_i, o_pad, clk, rst);
1671
`undef MODULE
1672
parameter width = 1;
1673 45 unneback
parameter reset_value = {width{1'b0}};
1674
input  [width-1:0]  d_i;
1675 44 unneback
output [width-1:0] o_pad;
1676
input clk, rst;
1677
wire [width-1:0] d_i_int `SYN_KEEP;
1678 45 unneback
reg  [width-1:0] o_pad_int;
1679 44 unneback
assign d_i_int = d_i;
1680
genvar i;
1681 45 unneback
generate
1682 136 unneback
for (i=0;i<width;i=i+1) begin : dffs
1683 44 unneback
    always @ (posedge clk or posedge rst)
1684
    if (rst)
1685 45 unneback
        o_pad_int[i] <= reset_value[i];
1686 44 unneback
    else
1687 45 unneback
        o_pad_int[i] <= d_i_int[i];
1688
    assign #1 o_pad[i] = o_pad_int[i];
1689 44 unneback
end
1690
endgenerate
1691
endmodule
1692
`endif
1693
 
1694 136 unneback
`ifdef IO_DFF_OE
1695 45 unneback
`timescale 1ns/1ns
1696 44 unneback
`define MODULE io_dff_oe
1697
module `BASE`MODULE ( d_i, d_o, oe, io_pad, clk, rst);
1698
`undef MODULE
1699
parameter width = 1;
1700 140 unneback
parameter reset_value = 1'b0;
1701 44 unneback
input  [width-1:0] d_o;
1702
output reg [width-1:0] d_i;
1703
input oe;
1704
inout [width-1:0] io_pad;
1705
input clk, rst;
1706
wire [width-1:0] oe_d `SYN_KEEP;
1707
reg [width-1:0] oe_q;
1708
reg [width-1:0] d_o_q;
1709
assign oe_d = {width{oe}};
1710
genvar i;
1711
generate
1712 136 unneback
for (i=0;i<width;i=i+1) begin : dffs
1713 44 unneback
    always @ (posedge clk or posedge rst)
1714
    if (rst)
1715
        oe_q[i] <= 1'b0;
1716
    else
1717
        oe_q[i] <= oe_d[i];
1718
    always @ (posedge clk or posedge rst)
1719
    if (rst)
1720 140 unneback
        d_o_q[i] <= reset_value;
1721 44 unneback
    else
1722
        d_o_q[i] <= d_o[i];
1723
    always @ (posedge clk or posedge rst)
1724
    if (rst)
1725 140 unneback
        d_i[i] <= reset_value;
1726 44 unneback
    else
1727
        d_i[i] <= io_pad[i];
1728 45 unneback
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
1729 44 unneback
end
1730
endgenerate
1731
endmodule
1732
`endif
1733 136 unneback
 
1734
`ifdef O_DDR
1735
`ifdef ALTERA
1736
`define MODULE o_ddr
1737
module `BASE`MODULE (d_h_i, d_l_i, o_pad, clk, rst);
1738
`undef MODULE
1739
parameter width = 1;
1740
input  [width-1:0] d_h_i, d_l_i;
1741
output [width-1:0] o_pad;
1742
input clk, rst;
1743
genvar i;
1744
generate
1745
for (i=0;i<width;i=i+1) begin : ddr
1746
    ddio_out ddio_out0( .aclr(rst), .datain_h(d_h_i[i]), .datain_l(d_l_i[i]), .outclock(clk), .dataout(o_pad[i]) );
1747
end
1748
endgenerate
1749
endmodule
1750
`else
1751
`define MODULE o_ddr
1752
module `BASE`MODULE (d_h_i, d_l_i, o_pad, clk, rst);
1753
`undef MODULE
1754
parameter width = 1;
1755
input  [width-1:0] d_h_i, d_l_i;
1756
output [width-1:0] o_pad;
1757
input clk, rst;
1758
reg [width-1:0] ff1;
1759
reg [width-1:0] ff2;
1760
genvar i;
1761
generate
1762
for (i=0;i<width;i=i+1) begin : ddr
1763
    always @ (posedge clk or posedge rst)
1764
    if (rst)
1765
        ff1[i] <= 1'b0;
1766
    else
1767
        ff1[i] <= d_h_i[i];
1768
    always @ (posedge clk or posedge rst)
1769
    if (rst)
1770
        ff2[i] <= 1'b0;
1771
    else
1772
        ff2[i] <= d_l_i[i];
1773
    assign o_pad = (clk) ? ff1 : ff2;
1774
end
1775
endgenerate
1776
endmodule
1777
`endif
1778
`endif
1779
 
1780
`ifdef O_CLK
1781
`define MODULE o_clk
1782
module `BASE`MODULE ( clk_o_pad, clk, rst);
1783
`undef MODULE
1784
input clk, rst;
1785
output clk_o_pad;
1786
`define MODULE o_ddr
1787
`BASE`MODULE o_ddr0( .d_h_i(1'b1), .d_l_i(1'b0), .o_pad(clk_o_pad), .clk(clk), .rst(rst));
1788
`undef MODULE
1789
endmodule
1790
`endif`ifdef CNT_BIN
1791 44 unneback
//////////////////////////////////////////////////////////////////////
1792
////                                                              ////
1793 6 unneback
////  Versatile counter                                           ////
1794
////                                                              ////
1795
////  Description                                                 ////
1796
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1797
////  counter                                                     ////
1798
////                                                              ////
1799
////  To Do:                                                      ////
1800
////   - add LFSR with more taps                                  ////
1801
////                                                              ////
1802
////  Author(s):                                                  ////
1803
////      - Michael Unneback, unneback@opencores.org              ////
1804
////        ORSoC AB                                              ////
1805
////                                                              ////
1806
//////////////////////////////////////////////////////////////////////
1807
////                                                              ////
1808
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1809
////                                                              ////
1810
//// This source file may be used and distributed without         ////
1811
//// restriction provided that this copyright statement is not    ////
1812
//// removed from the file and that any derivative work contains  ////
1813
//// the original copyright notice and the associated disclaimer. ////
1814
////                                                              ////
1815
//// This source file is free software; you can redistribute it   ////
1816
//// and/or modify it under the terms of the GNU Lesser General   ////
1817
//// Public License as published by the Free Software Foundation; ////
1818
//// either version 2.1 of the License, or (at your option) any   ////
1819
//// later version.                                               ////
1820
////                                                              ////
1821
//// This source is distributed in the hope that it will be       ////
1822
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1823
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1824
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1825
//// details.                                                     ////
1826
////                                                              ////
1827
//// You should have received a copy of the GNU Lesser General    ////
1828
//// Public License along with this source; if not, download it   ////
1829
//// from http://www.opencores.org/lgpl.shtml                     ////
1830
////                                                              ////
1831
//////////////////////////////////////////////////////////////////////
1832
 
1833
// binary counter
1834 22 unneback
 
1835 40 unneback
`define MODULE cnt_bin
1836
module `BASE`MODULE (
1837
`undef MODULE
1838
 q, rst, clk);
1839
 
1840 22 unneback
   parameter length = 4;
1841
   output [length:1] q;
1842
   input rst;
1843
   input clk;
1844
 
1845
   parameter clear_value = 0;
1846
   parameter set_value = 1;
1847
   parameter wrap_value = 0;
1848
   parameter level1_value = 15;
1849
 
1850
   reg  [length:1] qi;
1851
   wire [length:1] q_next;
1852
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1853
 
1854
   always @ (posedge clk or posedge rst)
1855
     if (rst)
1856
       qi <= {length{1'b0}};
1857
     else
1858
       qi <= q_next;
1859
 
1860
   assign q = qi;
1861
 
1862
endmodule
1863 40 unneback
`endif
1864
`ifdef CNT_BIN_CLEAR
1865 22 unneback
//////////////////////////////////////////////////////////////////////
1866
////                                                              ////
1867
////  Versatile counter                                           ////
1868
////                                                              ////
1869
////  Description                                                 ////
1870
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1871
////  counter                                                     ////
1872
////                                                              ////
1873
////  To Do:                                                      ////
1874
////   - add LFSR with more taps                                  ////
1875
////                                                              ////
1876
////  Author(s):                                                  ////
1877
////      - Michael Unneback, unneback@opencores.org              ////
1878
////        ORSoC AB                                              ////
1879
////                                                              ////
1880
//////////////////////////////////////////////////////////////////////
1881
////                                                              ////
1882
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1883
////                                                              ////
1884
//// This source file may be used and distributed without         ////
1885
//// restriction provided that this copyright statement is not    ////
1886
//// removed from the file and that any derivative work contains  ////
1887
//// the original copyright notice and the associated disclaimer. ////
1888
////                                                              ////
1889
//// This source file is free software; you can redistribute it   ////
1890
//// and/or modify it under the terms of the GNU Lesser General   ////
1891
//// Public License as published by the Free Software Foundation; ////
1892
//// either version 2.1 of the License, or (at your option) any   ////
1893
//// later version.                                               ////
1894
////                                                              ////
1895
//// This source is distributed in the hope that it will be       ////
1896
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1897
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1898
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1899
//// details.                                                     ////
1900
////                                                              ////
1901
//// You should have received a copy of the GNU Lesser General    ////
1902
//// Public License along with this source; if not, download it   ////
1903
//// from http://www.opencores.org/lgpl.shtml                     ////
1904
////                                                              ////
1905
//////////////////////////////////////////////////////////////////////
1906
 
1907
// binary counter
1908
 
1909 40 unneback
`define MODULE cnt_bin_clear
1910
module `BASE`MODULE (
1911
`undef MODULE
1912
 clear, q, rst, clk);
1913
 
1914 22 unneback
   parameter length = 4;
1915
   input clear;
1916
   output [length:1] q;
1917
   input rst;
1918
   input clk;
1919
 
1920
   parameter clear_value = 0;
1921
   parameter set_value = 1;
1922
   parameter wrap_value = 0;
1923
   parameter level1_value = 15;
1924
 
1925
   reg  [length:1] qi;
1926
   wire [length:1] q_next;
1927
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1928
 
1929
   always @ (posedge clk or posedge rst)
1930
     if (rst)
1931
       qi <= {length{1'b0}};
1932
     else
1933
       qi <= q_next;
1934
 
1935
   assign q = qi;
1936
 
1937
endmodule
1938 40 unneback
`endif
1939
`ifdef CNT_BIN_CE
1940 22 unneback
//////////////////////////////////////////////////////////////////////
1941
////                                                              ////
1942
////  Versatile counter                                           ////
1943
////                                                              ////
1944
////  Description                                                 ////
1945
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1946
////  counter                                                     ////
1947
////                                                              ////
1948
////  To Do:                                                      ////
1949
////   - add LFSR with more taps                                  ////
1950
////                                                              ////
1951
////  Author(s):                                                  ////
1952
////      - Michael Unneback, unneback@opencores.org              ////
1953
////        ORSoC AB                                              ////
1954
////                                                              ////
1955
//////////////////////////////////////////////////////////////////////
1956
////                                                              ////
1957
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1958
////                                                              ////
1959
//// This source file may be used and distributed without         ////
1960
//// restriction provided that this copyright statement is not    ////
1961
//// removed from the file and that any derivative work contains  ////
1962
//// the original copyright notice and the associated disclaimer. ////
1963
////                                                              ////
1964
//// This source file is free software; you can redistribute it   ////
1965
//// and/or modify it under the terms of the GNU Lesser General   ////
1966
//// Public License as published by the Free Software Foundation; ////
1967
//// either version 2.1 of the License, or (at your option) any   ////
1968
//// later version.                                               ////
1969
////                                                              ////
1970
//// This source is distributed in the hope that it will be       ////
1971
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1972
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1973
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1974
//// details.                                                     ////
1975
////                                                              ////
1976
//// You should have received a copy of the GNU Lesser General    ////
1977
//// Public License along with this source; if not, download it   ////
1978
//// from http://www.opencores.org/lgpl.shtml                     ////
1979
////                                                              ////
1980
//////////////////////////////////////////////////////////////////////
1981
 
1982
// binary counter
1983 6 unneback
 
1984 40 unneback
`define MODULE cnt_bin_ce
1985
module `BASE`MODULE (
1986
`undef MODULE
1987
 cke, q, rst, clk);
1988
 
1989 6 unneback
   parameter length = 4;
1990
   input cke;
1991
   output [length:1] q;
1992
   input rst;
1993
   input clk;
1994
 
1995
   parameter clear_value = 0;
1996
   parameter set_value = 1;
1997
   parameter wrap_value = 0;
1998
   parameter level1_value = 15;
1999
 
2000
   reg  [length:1] qi;
2001
   wire [length:1] q_next;
2002
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2003
 
2004
   always @ (posedge clk or posedge rst)
2005
     if (rst)
2006
       qi <= {length{1'b0}};
2007
     else
2008
     if (cke)
2009
       qi <= q_next;
2010
 
2011
   assign q = qi;
2012
 
2013
endmodule
2014 40 unneback
`endif
2015
`ifdef CNT_BIN_CE_CLEAR
2016 6 unneback
//////////////////////////////////////////////////////////////////////
2017
////                                                              ////
2018
////  Versatile counter                                           ////
2019
////                                                              ////
2020
////  Description                                                 ////
2021
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2022
////  counter                                                     ////
2023
////                                                              ////
2024
////  To Do:                                                      ////
2025
////   - add LFSR with more taps                                  ////
2026
////                                                              ////
2027
////  Author(s):                                                  ////
2028
////      - Michael Unneback, unneback@opencores.org              ////
2029
////        ORSoC AB                                              ////
2030
////                                                              ////
2031
//////////////////////////////////////////////////////////////////////
2032
////                                                              ////
2033
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2034
////                                                              ////
2035
//// This source file may be used and distributed without         ////
2036
//// restriction provided that this copyright statement is not    ////
2037
//// removed from the file and that any derivative work contains  ////
2038
//// the original copyright notice and the associated disclaimer. ////
2039
////                                                              ////
2040
//// This source file is free software; you can redistribute it   ////
2041
//// and/or modify it under the terms of the GNU Lesser General   ////
2042
//// Public License as published by the Free Software Foundation; ////
2043
//// either version 2.1 of the License, or (at your option) any   ////
2044
//// later version.                                               ////
2045
////                                                              ////
2046
//// This source is distributed in the hope that it will be       ////
2047
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2048
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2049
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2050
//// details.                                                     ////
2051
////                                                              ////
2052
//// You should have received a copy of the GNU Lesser General    ////
2053
//// Public License along with this source; if not, download it   ////
2054
//// from http://www.opencores.org/lgpl.shtml                     ////
2055
////                                                              ////
2056
//////////////////////////////////////////////////////////////////////
2057
 
2058
// binary counter
2059
 
2060 40 unneback
`define MODULE cnt_bin_ce_clear
2061
module `BASE`MODULE (
2062
`undef MODULE
2063
 clear, cke, q, rst, clk);
2064
 
2065 6 unneback
   parameter length = 4;
2066
   input clear;
2067
   input cke;
2068
   output [length:1] q;
2069
   input rst;
2070
   input clk;
2071
 
2072
   parameter clear_value = 0;
2073
   parameter set_value = 1;
2074
   parameter wrap_value = 0;
2075
   parameter level1_value = 15;
2076
 
2077
   reg  [length:1] qi;
2078
   wire [length:1] q_next;
2079
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
2080
 
2081
   always @ (posedge clk or posedge rst)
2082
     if (rst)
2083
       qi <= {length{1'b0}};
2084
     else
2085
     if (cke)
2086
       qi <= q_next;
2087
 
2088
   assign q = qi;
2089
 
2090
endmodule
2091 40 unneback
`endif
2092
`ifdef CNT_BIN_CE_CLEAR_L1_L2
2093 6 unneback
//////////////////////////////////////////////////////////////////////
2094
////                                                              ////
2095
////  Versatile counter                                           ////
2096
////                                                              ////
2097
////  Description                                                 ////
2098
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2099
////  counter                                                     ////
2100
////                                                              ////
2101
////  To Do:                                                      ////
2102
////   - add LFSR with more taps                                  ////
2103
////                                                              ////
2104
////  Author(s):                                                  ////
2105
////      - Michael Unneback, unneback@opencores.org              ////
2106
////        ORSoC AB                                              ////
2107
////                                                              ////
2108
//////////////////////////////////////////////////////////////////////
2109
////                                                              ////
2110
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2111
////                                                              ////
2112
//// This source file may be used and distributed without         ////
2113
//// restriction provided that this copyright statement is not    ////
2114
//// removed from the file and that any derivative work contains  ////
2115
//// the original copyright notice and the associated disclaimer. ////
2116
////                                                              ////
2117
//// This source file is free software; you can redistribute it   ////
2118
//// and/or modify it under the terms of the GNU Lesser General   ////
2119
//// Public License as published by the Free Software Foundation; ////
2120
//// either version 2.1 of the License, or (at your option) any   ////
2121
//// later version.                                               ////
2122
////                                                              ////
2123
//// This source is distributed in the hope that it will be       ////
2124
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2125
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2126
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2127
//// details.                                                     ////
2128
////                                                              ////
2129
//// You should have received a copy of the GNU Lesser General    ////
2130
//// Public License along with this source; if not, download it   ////
2131
//// from http://www.opencores.org/lgpl.shtml                     ////
2132
////                                                              ////
2133
//////////////////////////////////////////////////////////////////////
2134
 
2135
// binary counter
2136 29 unneback
 
2137 40 unneback
`define MODULE cnt_bin_ce_clear_l1_l2
2138
module `BASE`MODULE (
2139
`undef MODULE
2140
 clear, cke, q, level1, level2, rst, clk);
2141
 
2142 29 unneback
   parameter length = 4;
2143
   input clear;
2144
   input cke;
2145
   output [length:1] q;
2146
   output reg level1;
2147
   output reg level2;
2148
   input rst;
2149
   input clk;
2150
 
2151
   parameter clear_value = 0;
2152
   parameter set_value = 1;
2153 30 unneback
   parameter wrap_value = 15;
2154
   parameter level1_value = 8;
2155
   parameter level2_value = 15;
2156 29 unneback
 
2157
   wire rew;
2158 30 unneback
   assign rew = 1'b0;
2159 29 unneback
   reg  [length:1] qi;
2160
   wire [length:1] q_next;
2161
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
2162
 
2163
   always @ (posedge clk or posedge rst)
2164
     if (rst)
2165
       qi <= {length{1'b0}};
2166
     else
2167
     if (cke)
2168
       qi <= q_next;
2169
 
2170
   assign q = qi;
2171
 
2172
 
2173
    always @ (posedge clk or posedge rst)
2174
    if (rst)
2175
        level1 <= 1'b0;
2176
    else
2177
    if (cke)
2178
    if (clear)
2179
        level1 <= 1'b0;
2180
    else if (q_next == level1_value)
2181
        level1 <= 1'b1;
2182
    else if (qi == level1_value & rew)
2183
        level1 <= 1'b0;
2184
 
2185
    always @ (posedge clk or posedge rst)
2186
    if (rst)
2187
        level2 <= 1'b0;
2188
    else
2189
    if (cke)
2190
    if (clear)
2191
        level2 <= 1'b0;
2192
    else if (q_next == level2_value)
2193
        level2 <= 1'b1;
2194
    else if (qi == level2_value & rew)
2195
        level2 <= 1'b0;
2196
endmodule
2197 40 unneback
`endif
2198
`ifdef CNT_BIN_CE_CLEAR_SET_REW
2199 29 unneback
//////////////////////////////////////////////////////////////////////
2200
////                                                              ////
2201
////  Versatile counter                                           ////
2202
////                                                              ////
2203
////  Description                                                 ////
2204
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2205
////  counter                                                     ////
2206
////                                                              ////
2207
////  To Do:                                                      ////
2208
////   - add LFSR with more taps                                  ////
2209
////                                                              ////
2210
////  Author(s):                                                  ////
2211
////      - Michael Unneback, unneback@opencores.org              ////
2212
////        ORSoC AB                                              ////
2213
////                                                              ////
2214
//////////////////////////////////////////////////////////////////////
2215
////                                                              ////
2216
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2217
////                                                              ////
2218
//// This source file may be used and distributed without         ////
2219
//// restriction provided that this copyright statement is not    ////
2220
//// removed from the file and that any derivative work contains  ////
2221
//// the original copyright notice and the associated disclaimer. ////
2222
////                                                              ////
2223
//// This source file is free software; you can redistribute it   ////
2224
//// and/or modify it under the terms of the GNU Lesser General   ////
2225
//// Public License as published by the Free Software Foundation; ////
2226
//// either version 2.1 of the License, or (at your option) any   ////
2227
//// later version.                                               ////
2228
////                                                              ////
2229
//// This source is distributed in the hope that it will be       ////
2230
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2231
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2232
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2233
//// details.                                                     ////
2234
////                                                              ////
2235
//// You should have received a copy of the GNU Lesser General    ////
2236
//// Public License along with this source; if not, download it   ////
2237
//// from http://www.opencores.org/lgpl.shtml                     ////
2238
////                                                              ////
2239
//////////////////////////////////////////////////////////////////////
2240
 
2241
// binary counter
2242 6 unneback
 
2243 40 unneback
`define MODULE cnt_bin_ce_clear_set_rew
2244
module `BASE`MODULE (
2245
`undef MODULE
2246
 clear, set, cke, rew, q, rst, clk);
2247
 
2248 6 unneback
   parameter length = 4;
2249
   input clear;
2250
   input set;
2251
   input cke;
2252
   input rew;
2253
   output [length:1] q;
2254
   input rst;
2255
   input clk;
2256
 
2257
   parameter clear_value = 0;
2258
   parameter set_value = 1;
2259
   parameter wrap_value = 0;
2260
   parameter level1_value = 15;
2261
 
2262
   reg  [length:1] qi;
2263
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2264
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
2265
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
2266
   assign q_next = rew ? q_next_rew : q_next_fw;
2267
 
2268
   always @ (posedge clk or posedge rst)
2269
     if (rst)
2270
       qi <= {length{1'b0}};
2271
     else
2272
     if (cke)
2273
       qi <= q_next;
2274
 
2275
   assign q = qi;
2276
 
2277
endmodule
2278 40 unneback
`endif
2279
`ifdef CNT_BIN_CE_REW_L1
2280 6 unneback
//////////////////////////////////////////////////////////////////////
2281
////                                                              ////
2282
////  Versatile counter                                           ////
2283
////                                                              ////
2284
////  Description                                                 ////
2285
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2286
////  counter                                                     ////
2287
////                                                              ////
2288
////  To Do:                                                      ////
2289
////   - add LFSR with more taps                                  ////
2290
////                                                              ////
2291
////  Author(s):                                                  ////
2292
////      - Michael Unneback, unneback@opencores.org              ////
2293
////        ORSoC AB                                              ////
2294
////                                                              ////
2295
//////////////////////////////////////////////////////////////////////
2296
////                                                              ////
2297
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2298
////                                                              ////
2299
//// This source file may be used and distributed without         ////
2300
//// restriction provided that this copyright statement is not    ////
2301
//// removed from the file and that any derivative work contains  ////
2302
//// the original copyright notice and the associated disclaimer. ////
2303
////                                                              ////
2304
//// This source file is free software; you can redistribute it   ////
2305
//// and/or modify it under the terms of the GNU Lesser General   ////
2306
//// Public License as published by the Free Software Foundation; ////
2307
//// either version 2.1 of the License, or (at your option) any   ////
2308
//// later version.                                               ////
2309
////                                                              ////
2310
//// This source is distributed in the hope that it will be       ////
2311
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2312
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2313
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2314
//// details.                                                     ////
2315
////                                                              ////
2316
//// You should have received a copy of the GNU Lesser General    ////
2317
//// Public License along with this source; if not, download it   ////
2318
//// from http://www.opencores.org/lgpl.shtml                     ////
2319
////                                                              ////
2320
//////////////////////////////////////////////////////////////////////
2321
 
2322
// binary counter
2323
 
2324 40 unneback
`define MODULE cnt_bin_ce_rew_l1
2325
module `BASE`MODULE (
2326
`undef MODULE
2327
 cke, rew, level1, rst, clk);
2328
 
2329 6 unneback
   parameter length = 4;
2330
   input cke;
2331
   input rew;
2332
   output reg level1;
2333
   input rst;
2334
   input clk;
2335
 
2336
   parameter clear_value = 0;
2337
   parameter set_value = 1;
2338
   parameter wrap_value = 1;
2339
   parameter level1_value = 15;
2340
 
2341 29 unneback
   wire clear;
2342 30 unneback
   assign clear = 1'b0;
2343 6 unneback
   reg  [length:1] qi;
2344
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2345
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2346
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2347
   assign q_next = rew ? q_next_rew : q_next_fw;
2348
 
2349
   always @ (posedge clk or posedge rst)
2350
     if (rst)
2351
       qi <= {length{1'b0}};
2352
     else
2353
     if (cke)
2354
       qi <= q_next;
2355
 
2356
 
2357
 
2358
    always @ (posedge clk or posedge rst)
2359
    if (rst)
2360
        level1 <= 1'b0;
2361
    else
2362
    if (cke)
2363 29 unneback
    if (clear)
2364
        level1 <= 1'b0;
2365
    else if (q_next == level1_value)
2366 6 unneback
        level1 <= 1'b1;
2367
    else if (qi == level1_value & rew)
2368
        level1 <= 1'b0;
2369
endmodule
2370 40 unneback
`endif
2371
`ifdef CNT_BIN_CE_REW_ZQ_L1
2372 6 unneback
//////////////////////////////////////////////////////////////////////
2373
////                                                              ////
2374
////  Versatile counter                                           ////
2375
////                                                              ////
2376
////  Description                                                 ////
2377
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2378
////  counter                                                     ////
2379
////                                                              ////
2380
////  To Do:                                                      ////
2381
////   - add LFSR with more taps                                  ////
2382
////                                                              ////
2383
////  Author(s):                                                  ////
2384
////      - Michael Unneback, unneback@opencores.org              ////
2385
////        ORSoC AB                                              ////
2386
////                                                              ////
2387
//////////////////////////////////////////////////////////////////////
2388
////                                                              ////
2389
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2390
////                                                              ////
2391
//// This source file may be used and distributed without         ////
2392
//// restriction provided that this copyright statement is not    ////
2393
//// removed from the file and that any derivative work contains  ////
2394
//// the original copyright notice and the associated disclaimer. ////
2395
////                                                              ////
2396
//// This source file is free software; you can redistribute it   ////
2397
//// and/or modify it under the terms of the GNU Lesser General   ////
2398
//// Public License as published by the Free Software Foundation; ////
2399
//// either version 2.1 of the License, or (at your option) any   ////
2400
//// later version.                                               ////
2401
////                                                              ////
2402
//// This source is distributed in the hope that it will be       ////
2403
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2404
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2405
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2406
//// details.                                                     ////
2407
////                                                              ////
2408
//// You should have received a copy of the GNU Lesser General    ////
2409
//// Public License along with this source; if not, download it   ////
2410
//// from http://www.opencores.org/lgpl.shtml                     ////
2411
////                                                              ////
2412
//////////////////////////////////////////////////////////////////////
2413
 
2414 25 unneback
// binary counter
2415
 
2416 40 unneback
`define MODULE cnt_bin_ce_rew_zq_l1
2417
module `BASE`MODULE (
2418
`undef MODULE
2419
 cke, rew, zq, level1, rst, clk);
2420
 
2421 25 unneback
   parameter length = 4;
2422
   input cke;
2423
   input rew;
2424
   output reg zq;
2425
   output reg level1;
2426
   input rst;
2427
   input clk;
2428
 
2429
   parameter clear_value = 0;
2430
   parameter set_value = 1;
2431
   parameter wrap_value = 1;
2432
   parameter level1_value = 15;
2433
 
2434 29 unneback
   wire clear;
2435 30 unneback
   assign clear = 1'b0;
2436 25 unneback
   reg  [length:1] qi;
2437
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2438
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2439
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2440
   assign q_next = rew ? q_next_rew : q_next_fw;
2441
 
2442
   always @ (posedge clk or posedge rst)
2443
     if (rst)
2444
       qi <= {length{1'b0}};
2445
     else
2446
     if (cke)
2447
       qi <= q_next;
2448
 
2449
 
2450
 
2451
   always @ (posedge clk or posedge rst)
2452
     if (rst)
2453
       zq <= 1'b1;
2454
     else
2455
     if (cke)
2456
       zq <= q_next == {length{1'b0}};
2457
 
2458
    always @ (posedge clk or posedge rst)
2459
    if (rst)
2460
        level1 <= 1'b0;
2461
    else
2462
    if (cke)
2463 29 unneback
    if (clear)
2464
        level1 <= 1'b0;
2465
    else if (q_next == level1_value)
2466 25 unneback
        level1 <= 1'b1;
2467
    else if (qi == level1_value & rew)
2468
        level1 <= 1'b0;
2469
endmodule
2470 40 unneback
`endif
2471
`ifdef CNT_BIN_CE_REW_Q_ZQ_L1
2472 25 unneback
//////////////////////////////////////////////////////////////////////
2473
////                                                              ////
2474
////  Versatile counter                                           ////
2475
////                                                              ////
2476
////  Description                                                 ////
2477
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2478
////  counter                                                     ////
2479
////                                                              ////
2480
////  To Do:                                                      ////
2481
////   - add LFSR with more taps                                  ////
2482
////                                                              ////
2483
////  Author(s):                                                  ////
2484
////      - Michael Unneback, unneback@opencores.org              ////
2485
////        ORSoC AB                                              ////
2486
////                                                              ////
2487
//////////////////////////////////////////////////////////////////////
2488
////                                                              ////
2489
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2490
////                                                              ////
2491
//// This source file may be used and distributed without         ////
2492
//// restriction provided that this copyright statement is not    ////
2493
//// removed from the file and that any derivative work contains  ////
2494
//// the original copyright notice and the associated disclaimer. ////
2495
////                                                              ////
2496
//// This source file is free software; you can redistribute it   ////
2497
//// and/or modify it under the terms of the GNU Lesser General   ////
2498
//// Public License as published by the Free Software Foundation; ////
2499
//// either version 2.1 of the License, or (at your option) any   ////
2500
//// later version.                                               ////
2501
////                                                              ////
2502
//// This source is distributed in the hope that it will be       ////
2503
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2504
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2505
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2506
//// details.                                                     ////
2507
////                                                              ////
2508
//// You should have received a copy of the GNU Lesser General    ////
2509
//// Public License along with this source; if not, download it   ////
2510
//// from http://www.opencores.org/lgpl.shtml                     ////
2511
////                                                              ////
2512
//////////////////////////////////////////////////////////////////////
2513
 
2514
// binary counter
2515
 
2516 40 unneback
`define MODULE cnt_bin_ce_rew_q_zq_l1
2517
module `BASE`MODULE (
2518
`undef MODULE
2519
 cke, rew, q, zq, level1, rst, clk);
2520
 
2521 25 unneback
   parameter length = 4;
2522
   input cke;
2523
   input rew;
2524
   output [length:1] q;
2525
   output reg zq;
2526
   output reg level1;
2527
   input rst;
2528
   input clk;
2529
 
2530
   parameter clear_value = 0;
2531
   parameter set_value = 1;
2532
   parameter wrap_value = 1;
2533
   parameter level1_value = 15;
2534
 
2535 29 unneback
   wire clear;
2536 30 unneback
   assign clear = 1'b0;
2537 25 unneback
   reg  [length:1] qi;
2538
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2539
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2540
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2541
   assign q_next = rew ? q_next_rew : q_next_fw;
2542
 
2543
   always @ (posedge clk or posedge rst)
2544
     if (rst)
2545
       qi <= {length{1'b0}};
2546
     else
2547
     if (cke)
2548
       qi <= q_next;
2549
 
2550
   assign q = qi;
2551
 
2552
 
2553
   always @ (posedge clk or posedge rst)
2554
     if (rst)
2555
       zq <= 1'b1;
2556
     else
2557
     if (cke)
2558
       zq <= q_next == {length{1'b0}};
2559
 
2560
    always @ (posedge clk or posedge rst)
2561
    if (rst)
2562
        level1 <= 1'b0;
2563
    else
2564
    if (cke)
2565 29 unneback
    if (clear)
2566
        level1 <= 1'b0;
2567
    else if (q_next == level1_value)
2568 25 unneback
        level1 <= 1'b1;
2569
    else if (qi == level1_value & rew)
2570
        level1 <= 1'b0;
2571
endmodule
2572 40 unneback
`endif
2573
`ifdef CNT_LFSR_ZQ
2574 25 unneback
//////////////////////////////////////////////////////////////////////
2575
////                                                              ////
2576
////  Versatile counter                                           ////
2577
////                                                              ////
2578
////  Description                                                 ////
2579
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2580
////  counter                                                     ////
2581
////                                                              ////
2582
////  To Do:                                                      ////
2583
////   - add LFSR with more taps                                  ////
2584
////                                                              ////
2585
////  Author(s):                                                  ////
2586
////      - Michael Unneback, unneback@opencores.org              ////
2587
////        ORSoC AB                                              ////
2588
////                                                              ////
2589
//////////////////////////////////////////////////////////////////////
2590
////                                                              ////
2591
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2592
////                                                              ////
2593
//// This source file may be used and distributed without         ////
2594
//// restriction provided that this copyright statement is not    ////
2595
//// removed from the file and that any derivative work contains  ////
2596
//// the original copyright notice and the associated disclaimer. ////
2597
////                                                              ////
2598
//// This source file is free software; you can redistribute it   ////
2599
//// and/or modify it under the terms of the GNU Lesser General   ////
2600
//// Public License as published by the Free Software Foundation; ////
2601
//// either version 2.1 of the License, or (at your option) any   ////
2602
//// later version.                                               ////
2603
////                                                              ////
2604
//// This source is distributed in the hope that it will be       ////
2605
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2606
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2607
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2608
//// details.                                                     ////
2609
////                                                              ////
2610
//// You should have received a copy of the GNU Lesser General    ////
2611
//// Public License along with this source; if not, download it   ////
2612
//// from http://www.opencores.org/lgpl.shtml                     ////
2613
////                                                              ////
2614
//////////////////////////////////////////////////////////////////////
2615
 
2616 6 unneback
// LFSR counter
2617
 
2618 40 unneback
`define MODULE cnt_lfsr_zq
2619
module `BASE`MODULE (
2620
`undef MODULE
2621
 zq, rst, clk);
2622
 
2623 6 unneback
   parameter length = 4;
2624
   output reg zq;
2625
   input rst;
2626
   input clk;
2627
 
2628
   parameter clear_value = 0;
2629
   parameter set_value = 1;
2630
   parameter wrap_value = 8;
2631
   parameter level1_value = 15;
2632
 
2633
   reg  [length:1] qi;
2634
   reg lfsr_fb;
2635
   wire [length:1] q_next;
2636
   reg [32:1] polynom;
2637
   integer i;
2638
 
2639
   always @ (qi)
2640
   begin
2641
        case (length)
2642
         2: polynom = 32'b11;                               // 0x3
2643
         3: polynom = 32'b110;                              // 0x6
2644
         4: polynom = 32'b1100;                             // 0xC
2645
         5: polynom = 32'b10100;                            // 0x14
2646
         6: polynom = 32'b110000;                           // 0x30
2647
         7: polynom = 32'b1100000;                          // 0x60
2648
         8: polynom = 32'b10111000;                         // 0xb8
2649
         9: polynom = 32'b100010000;                        // 0x110
2650
        10: polynom = 32'b1001000000;                       // 0x240
2651
        11: polynom = 32'b10100000000;                      // 0x500
2652
        12: polynom = 32'b100000101001;                     // 0x829
2653
        13: polynom = 32'b1000000001100;                    // 0x100C
2654
        14: polynom = 32'b10000000010101;                   // 0x2015
2655
        15: polynom = 32'b110000000000000;                  // 0x6000
2656
        16: polynom = 32'b1101000000001000;                 // 0xD008
2657
        17: polynom = 32'b10010000000000000;                // 0x12000
2658
        18: polynom = 32'b100000010000000000;               // 0x20400
2659
        19: polynom = 32'b1000000000000100011;              // 0x40023
2660 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2661 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2662
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2663
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2664
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2665
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2666
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2667
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2668
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2669
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2670
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2671
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2672
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2673
        default: polynom = 32'b0;
2674
        endcase
2675
        lfsr_fb = qi[length];
2676
        for (i=length-1; i>=1; i=i-1) begin
2677
            if (polynom[i])
2678
                lfsr_fb = lfsr_fb  ~^ qi[i];
2679
        end
2680
    end
2681
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2682
 
2683
   always @ (posedge clk or posedge rst)
2684
     if (rst)
2685
       qi <= {length{1'b0}};
2686
     else
2687
       qi <= q_next;
2688
 
2689
 
2690
 
2691
   always @ (posedge clk or posedge rst)
2692
     if (rst)
2693
       zq <= 1'b1;
2694
     else
2695
       zq <= q_next == {length{1'b0}};
2696
endmodule
2697 40 unneback
`endif
2698 75 unneback
`ifdef CNT_LFSR_CE
2699
//////////////////////////////////////////////////////////////////////
2700
////                                                              ////
2701
////  Versatile counter                                           ////
2702
////                                                              ////
2703
////  Description                                                 ////
2704
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2705
////  counter                                                     ////
2706
////                                                              ////
2707
////  To Do:                                                      ////
2708
////   - add LFSR with more taps                                  ////
2709
////                                                              ////
2710
////  Author(s):                                                  ////
2711
////      - Michael Unneback, unneback@opencores.org              ////
2712
////        ORSoC AB                                              ////
2713
////                                                              ////
2714
//////////////////////////////////////////////////////////////////////
2715
////                                                              ////
2716
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2717
////                                                              ////
2718
//// This source file may be used and distributed without         ////
2719
//// restriction provided that this copyright statement is not    ////
2720
//// removed from the file and that any derivative work contains  ////
2721
//// the original copyright notice and the associated disclaimer. ////
2722
////                                                              ////
2723
//// This source file is free software; you can redistribute it   ////
2724
//// and/or modify it under the terms of the GNU Lesser General   ////
2725
//// Public License as published by the Free Software Foundation; ////
2726
//// either version 2.1 of the License, or (at your option) any   ////
2727
//// later version.                                               ////
2728
////                                                              ////
2729
//// This source is distributed in the hope that it will be       ////
2730
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2731
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2732
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2733
//// details.                                                     ////
2734
////                                                              ////
2735
//// You should have received a copy of the GNU Lesser General    ////
2736
//// Public License along with this source; if not, download it   ////
2737
//// from http://www.opencores.org/lgpl.shtml                     ////
2738
////                                                              ////
2739
//////////////////////////////////////////////////////////////////////
2740
 
2741
// LFSR counter
2742
 
2743
`define MODULE cnt_lfsr_ce
2744
module `BASE`MODULE (
2745
`undef MODULE
2746
 cke, zq, rst, clk);
2747
 
2748
   parameter length = 4;
2749
   input cke;
2750
   output reg zq;
2751
   input rst;
2752
   input clk;
2753
 
2754
   parameter clear_value = 0;
2755
   parameter set_value = 1;
2756
   parameter wrap_value = 0;
2757
   parameter level1_value = 15;
2758
 
2759
   reg  [length:1] qi;
2760
   reg lfsr_fb;
2761
   wire [length:1] q_next;
2762
   reg [32:1] polynom;
2763
   integer i;
2764
 
2765
   always @ (qi)
2766
   begin
2767
        case (length)
2768
         2: polynom = 32'b11;                               // 0x3
2769
         3: polynom = 32'b110;                              // 0x6
2770
         4: polynom = 32'b1100;                             // 0xC
2771
         5: polynom = 32'b10100;                            // 0x14
2772
         6: polynom = 32'b110000;                           // 0x30
2773
         7: polynom = 32'b1100000;                          // 0x60
2774
         8: polynom = 32'b10111000;                         // 0xb8
2775
         9: polynom = 32'b100010000;                        // 0x110
2776
        10: polynom = 32'b1001000000;                       // 0x240
2777
        11: polynom = 32'b10100000000;                      // 0x500
2778
        12: polynom = 32'b100000101001;                     // 0x829
2779
        13: polynom = 32'b1000000001100;                    // 0x100C
2780
        14: polynom = 32'b10000000010101;                   // 0x2015
2781
        15: polynom = 32'b110000000000000;                  // 0x6000
2782
        16: polynom = 32'b1101000000001000;                 // 0xD008
2783
        17: polynom = 32'b10010000000000000;                // 0x12000
2784
        18: polynom = 32'b100000010000000000;               // 0x20400
2785
        19: polynom = 32'b1000000000000100011;              // 0x40023
2786
        20: polynom = 32'b10010000000000000000;             // 0x90000
2787
        21: polynom = 32'b101000000000000000000;            // 0x140000
2788
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2789
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2790
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2791
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2792
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2793
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2794
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2795
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2796
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2797
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2798
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2799
        default: polynom = 32'b0;
2800
        endcase
2801
        lfsr_fb = qi[length];
2802
        for (i=length-1; i>=1; i=i-1) begin
2803
            if (polynom[i])
2804
                lfsr_fb = lfsr_fb  ~^ qi[i];
2805
        end
2806
    end
2807
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2808
 
2809
   always @ (posedge clk or posedge rst)
2810
     if (rst)
2811
       qi <= {length{1'b0}};
2812
     else
2813
     if (cke)
2814
       qi <= q_next;
2815
 
2816
 
2817
 
2818
   always @ (posedge clk or posedge rst)
2819
     if (rst)
2820
       zq <= 1'b1;
2821
     else
2822
     if (cke)
2823
       zq <= q_next == {length{1'b0}};
2824
endmodule
2825
`endif
2826 40 unneback
`ifdef CNT_LFSR_CE_ZQ
2827 6 unneback
//////////////////////////////////////////////////////////////////////
2828
////                                                              ////
2829
////  Versatile counter                                           ////
2830
////                                                              ////
2831
////  Description                                                 ////
2832
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2833
////  counter                                                     ////
2834
////                                                              ////
2835
////  To Do:                                                      ////
2836
////   - add LFSR with more taps                                  ////
2837
////                                                              ////
2838
////  Author(s):                                                  ////
2839
////      - Michael Unneback, unneback@opencores.org              ////
2840
////        ORSoC AB                                              ////
2841
////                                                              ////
2842
//////////////////////////////////////////////////////////////////////
2843
////                                                              ////
2844
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2845
////                                                              ////
2846
//// This source file may be used and distributed without         ////
2847
//// restriction provided that this copyright statement is not    ////
2848
//// removed from the file and that any derivative work contains  ////
2849
//// the original copyright notice and the associated disclaimer. ////
2850
////                                                              ////
2851
//// This source file is free software; you can redistribute it   ////
2852
//// and/or modify it under the terms of the GNU Lesser General   ////
2853
//// Public License as published by the Free Software Foundation; ////
2854
//// either version 2.1 of the License, or (at your option) any   ////
2855
//// later version.                                               ////
2856
////                                                              ////
2857
//// This source is distributed in the hope that it will be       ////
2858
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2859
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2860
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2861
//// details.                                                     ////
2862
////                                                              ////
2863
//// You should have received a copy of the GNU Lesser General    ////
2864
//// Public License along with this source; if not, download it   ////
2865
//// from http://www.opencores.org/lgpl.shtml                     ////
2866
////                                                              ////
2867
//////////////////////////////////////////////////////////////////////
2868
 
2869
// LFSR counter
2870
 
2871 40 unneback
`define MODULE cnt_lfsr_ce_zq
2872
module `BASE`MODULE (
2873
`undef MODULE
2874
 cke, zq, rst, clk);
2875
 
2876 6 unneback
   parameter length = 4;
2877
   input cke;
2878
   output reg zq;
2879
   input rst;
2880
   input clk;
2881
 
2882
   parameter clear_value = 0;
2883
   parameter set_value = 1;
2884
   parameter wrap_value = 8;
2885
   parameter level1_value = 15;
2886
 
2887
   reg  [length:1] qi;
2888
   reg lfsr_fb;
2889
   wire [length:1] q_next;
2890
   reg [32:1] polynom;
2891
   integer i;
2892
 
2893
   always @ (qi)
2894
   begin
2895
        case (length)
2896
         2: polynom = 32'b11;                               // 0x3
2897
         3: polynom = 32'b110;                              // 0x6
2898
         4: polynom = 32'b1100;                             // 0xC
2899
         5: polynom = 32'b10100;                            // 0x14
2900
         6: polynom = 32'b110000;                           // 0x30
2901
         7: polynom = 32'b1100000;                          // 0x60
2902
         8: polynom = 32'b10111000;                         // 0xb8
2903
         9: polynom = 32'b100010000;                        // 0x110
2904
        10: polynom = 32'b1001000000;                       // 0x240
2905
        11: polynom = 32'b10100000000;                      // 0x500
2906
        12: polynom = 32'b100000101001;                     // 0x829
2907
        13: polynom = 32'b1000000001100;                    // 0x100C
2908
        14: polynom = 32'b10000000010101;                   // 0x2015
2909
        15: polynom = 32'b110000000000000;                  // 0x6000
2910
        16: polynom = 32'b1101000000001000;                 // 0xD008
2911
        17: polynom = 32'b10010000000000000;                // 0x12000
2912
        18: polynom = 32'b100000010000000000;               // 0x20400
2913
        19: polynom = 32'b1000000000000100011;              // 0x40023
2914 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2915 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2916
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2917
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2918
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2919
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2920
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2921
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2922
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2923
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2924
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2925
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2926
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2927
        default: polynom = 32'b0;
2928
        endcase
2929
        lfsr_fb = qi[length];
2930
        for (i=length-1; i>=1; i=i-1) begin
2931
            if (polynom[i])
2932
                lfsr_fb = lfsr_fb  ~^ qi[i];
2933
        end
2934
    end
2935
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2936
 
2937
   always @ (posedge clk or posedge rst)
2938
     if (rst)
2939
       qi <= {length{1'b0}};
2940
     else
2941
     if (cke)
2942
       qi <= q_next;
2943
 
2944
 
2945
 
2946
   always @ (posedge clk or posedge rst)
2947
     if (rst)
2948
       zq <= 1'b1;
2949
     else
2950
     if (cke)
2951
       zq <= q_next == {length{1'b0}};
2952
endmodule
2953 40 unneback
`endif
2954
`ifdef CNT_LFSR_CE_Q
2955 6 unneback
//////////////////////////////////////////////////////////////////////
2956
////                                                              ////
2957
////  Versatile counter                                           ////
2958
////                                                              ////
2959
////  Description                                                 ////
2960
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2961
////  counter                                                     ////
2962
////                                                              ////
2963
////  To Do:                                                      ////
2964
////   - add LFSR with more taps                                  ////
2965
////                                                              ////
2966
////  Author(s):                                                  ////
2967
////      - Michael Unneback, unneback@opencores.org              ////
2968
////        ORSoC AB                                              ////
2969
////                                                              ////
2970
//////////////////////////////////////////////////////////////////////
2971
////                                                              ////
2972
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2973
////                                                              ////
2974
//// This source file may be used and distributed without         ////
2975
//// restriction provided that this copyright statement is not    ////
2976
//// removed from the file and that any derivative work contains  ////
2977
//// the original copyright notice and the associated disclaimer. ////
2978
////                                                              ////
2979
//// This source file is free software; you can redistribute it   ////
2980
//// and/or modify it under the terms of the GNU Lesser General   ////
2981
//// Public License as published by the Free Software Foundation; ////
2982
//// either version 2.1 of the License, or (at your option) any   ////
2983
//// later version.                                               ////
2984
////                                                              ////
2985
//// This source is distributed in the hope that it will be       ////
2986
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2987
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2988
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2989
//// details.                                                     ////
2990
////                                                              ////
2991
//// You should have received a copy of the GNU Lesser General    ////
2992
//// Public License along with this source; if not, download it   ////
2993
//// from http://www.opencores.org/lgpl.shtml                     ////
2994
////                                                              ////
2995
//////////////////////////////////////////////////////////////////////
2996 22 unneback
 
2997
// LFSR counter
2998 27 unneback
 
2999 40 unneback
`define MODULE cnt_lfsr_ce_q
3000
module `BASE`MODULE (
3001
`undef MODULE
3002
 cke, q, rst, clk);
3003
 
3004 27 unneback
   parameter length = 4;
3005
   input cke;
3006
   output [length:1] q;
3007
   input rst;
3008
   input clk;
3009
 
3010
   parameter clear_value = 0;
3011
   parameter set_value = 1;
3012
   parameter wrap_value = 8;
3013
   parameter level1_value = 15;
3014
 
3015
   reg  [length:1] qi;
3016
   reg lfsr_fb;
3017
   wire [length:1] q_next;
3018
   reg [32:1] polynom;
3019
   integer i;
3020
 
3021
   always @ (qi)
3022
   begin
3023
        case (length)
3024
         2: polynom = 32'b11;                               // 0x3
3025
         3: polynom = 32'b110;                              // 0x6
3026
         4: polynom = 32'b1100;                             // 0xC
3027
         5: polynom = 32'b10100;                            // 0x14
3028
         6: polynom = 32'b110000;                           // 0x30
3029
         7: polynom = 32'b1100000;                          // 0x60
3030
         8: polynom = 32'b10111000;                         // 0xb8
3031
         9: polynom = 32'b100010000;                        // 0x110
3032
        10: polynom = 32'b1001000000;                       // 0x240
3033
        11: polynom = 32'b10100000000;                      // 0x500
3034
        12: polynom = 32'b100000101001;                     // 0x829
3035
        13: polynom = 32'b1000000001100;                    // 0x100C
3036
        14: polynom = 32'b10000000010101;                   // 0x2015
3037
        15: polynom = 32'b110000000000000;                  // 0x6000
3038
        16: polynom = 32'b1101000000001000;                 // 0xD008
3039
        17: polynom = 32'b10010000000000000;                // 0x12000
3040
        18: polynom = 32'b100000010000000000;               // 0x20400
3041
        19: polynom = 32'b1000000000000100011;              // 0x40023
3042 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
3043 27 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
3044
        22: polynom = 32'b1100000000000000000000;           // 0x300000
3045
        23: polynom = 32'b10000100000000000000000;          // 0x420000
3046
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
3047
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
3048
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
3049
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
3050
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
3051
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
3052
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
3053
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
3054
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
3055
        default: polynom = 32'b0;
3056
        endcase
3057
        lfsr_fb = qi[length];
3058
        for (i=length-1; i>=1; i=i-1) begin
3059
            if (polynom[i])
3060
                lfsr_fb = lfsr_fb  ~^ qi[i];
3061
        end
3062
    end
3063
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
3064
 
3065
   always @ (posedge clk or posedge rst)
3066
     if (rst)
3067
       qi <= {length{1'b0}};
3068
     else
3069
     if (cke)
3070
       qi <= q_next;
3071
 
3072
   assign q = qi;
3073
 
3074
endmodule
3075 40 unneback
`endif
3076
`ifdef CNT_LFSR_CE_CLEAR_Q
3077 27 unneback
//////////////////////////////////////////////////////////////////////
3078
////                                                              ////
3079
////  Versatile counter                                           ////
3080
////                                                              ////
3081
////  Description                                                 ////
3082
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3083
////  counter                                                     ////
3084
////                                                              ////
3085
////  To Do:                                                      ////
3086
////   - add LFSR with more taps                                  ////
3087
////                                                              ////
3088
////  Author(s):                                                  ////
3089
////      - Michael Unneback, unneback@opencores.org              ////
3090
////        ORSoC AB                                              ////
3091
////                                                              ////
3092
//////////////////////////////////////////////////////////////////////
3093
////                                                              ////
3094
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3095
////                                                              ////
3096
//// This source file may be used and distributed without         ////
3097
//// restriction provided that this copyright statement is not    ////
3098
//// removed from the file and that any derivative work contains  ////
3099
//// the original copyright notice and the associated disclaimer. ////
3100
////                                                              ////
3101
//// This source file is free software; you can redistribute it   ////
3102
//// and/or modify it under the terms of the GNU Lesser General   ////
3103
//// Public License as published by the Free Software Foundation; ////
3104
//// either version 2.1 of the License, or (at your option) any   ////
3105
//// later version.                                               ////
3106
////                                                              ////
3107
//// This source is distributed in the hope that it will be       ////
3108
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3109
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3110
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3111
//// details.                                                     ////
3112
////                                                              ////
3113
//// You should have received a copy of the GNU Lesser General    ////
3114
//// Public License along with this source; if not, download it   ////
3115
//// from http://www.opencores.org/lgpl.shtml                     ////
3116
////                                                              ////
3117
//////////////////////////////////////////////////////////////////////
3118
 
3119
// LFSR counter
3120
 
3121 40 unneback
`define MODULE cnt_lfsr_ce_clear_q
3122
module `BASE`MODULE (
3123
`undef MODULE
3124
 clear, cke, q, rst, clk);
3125
 
3126 27 unneback
   parameter length = 4;
3127
   input clear;
3128
   input cke;
3129
   output [length:1] q;
3130
   input rst;
3131
   input clk;
3132
 
3133
   parameter clear_value = 0;
3134
   parameter set_value = 1;
3135
   parameter wrap_value = 8;
3136
   parameter level1_value = 15;
3137
 
3138
   reg  [length:1] qi;
3139
   reg lfsr_fb;
3140
   wire [length:1] q_next;
3141
   reg [32:1] polynom;
3142
   integer i;
3143
 
3144
   always @ (qi)
3145
   begin
3146
        case (length)
3147
         2: polynom = 32'b11;                               // 0x3
3148
         3: polynom = 32'b110;                              // 0x6
3149
         4: polynom = 32'b1100;                             // 0xC
3150
         5: polynom = 32'b10100;                            // 0x14
3151
         6: polynom = 32'b110000;                           // 0x30
3152
         7: polynom = 32'b1100000;                          // 0x60
3153
         8: polynom = 32'b10111000;                         // 0xb8
3154
         9: polynom = 32'b100010000;                        // 0x110
3155
        10: polynom = 32'b1001000000;                       // 0x240
3156
        11: polynom = 32'b10100000000;                      // 0x500
3157
        12: polynom = 32'b100000101001;                     // 0x829
3158
        13: polynom = 32'b1000000001100;                    // 0x100C
3159
        14: polynom = 32'b10000000010101;                   // 0x2015
3160
        15: polynom = 32'b110000000000000;                  // 0x6000
3161
        16: polynom = 32'b1101000000001000;                 // 0xD008
3162
        17: polynom = 32'b10010000000000000;                // 0x12000
3163
        18: polynom = 32'b100000010000000000;               // 0x20400
3164
        19: polynom = 32'b1000000000000100011;              // 0x40023
3165 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
3166 27 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
3167
        22: polynom = 32'b1100000000000000000000;           // 0x300000
3168
        23: polynom = 32'b10000100000000000000000;          // 0x420000
3169
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
3170
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
3171
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
3172
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
3173
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
3174
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
3175
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
3176
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
3177
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
3178
        default: polynom = 32'b0;
3179
        endcase
3180
        lfsr_fb = qi[length];
3181
        for (i=length-1; i>=1; i=i-1) begin
3182
            if (polynom[i])
3183
                lfsr_fb = lfsr_fb  ~^ qi[i];
3184
        end
3185
    end
3186
   assign q_next =  clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
3187
 
3188
   always @ (posedge clk or posedge rst)
3189
     if (rst)
3190
       qi <= {length{1'b0}};
3191
     else
3192
     if (cke)
3193
       qi <= q_next;
3194
 
3195
   assign q = qi;
3196
 
3197
endmodule
3198 40 unneback
`endif
3199
`ifdef CNT_LFSR_CE_Q_ZQ
3200 27 unneback
//////////////////////////////////////////////////////////////////////
3201
////                                                              ////
3202
////  Versatile counter                                           ////
3203
////                                                              ////
3204
////  Description                                                 ////
3205
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3206
////  counter                                                     ////
3207
////                                                              ////
3208
////  To Do:                                                      ////
3209
////   - add LFSR with more taps                                  ////
3210
////                                                              ////
3211
////  Author(s):                                                  ////
3212
////      - Michael Unneback, unneback@opencores.org              ////
3213
////        ORSoC AB                                              ////
3214
////                                                              ////
3215
//////////////////////////////////////////////////////////////////////
3216
////                                                              ////
3217
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3218
////                                                              ////
3219
//// This source file may be used and distributed without         ////
3220
//// restriction provided that this copyright statement is not    ////
3221
//// removed from the file and that any derivative work contains  ////
3222
//// the original copyright notice and the associated disclaimer. ////
3223
////                                                              ////
3224
//// This source file is free software; you can redistribute it   ////
3225
//// and/or modify it under the terms of the GNU Lesser General   ////
3226
//// Public License as published by the Free Software Foundation; ////
3227
//// either version 2.1 of the License, or (at your option) any   ////
3228
//// later version.                                               ////
3229
////                                                              ////
3230
//// This source is distributed in the hope that it will be       ////
3231
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3232
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3233
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3234
//// details.                                                     ////
3235
////                                                              ////
3236
//// You should have received a copy of the GNU Lesser General    ////
3237
//// Public License along with this source; if not, download it   ////
3238
//// from http://www.opencores.org/lgpl.shtml                     ////
3239
////                                                              ////
3240
//////////////////////////////////////////////////////////////////////
3241
 
3242
// LFSR counter
3243 22 unneback
 
3244 40 unneback
`define MODULE cnt_lfsr_ce_q_zq
3245
module `BASE`MODULE (
3246
`undef MODULE
3247
 cke, q, zq, rst, clk);
3248
 
3249 22 unneback
   parameter length = 4;
3250
   input cke;
3251
   output [length:1] q;
3252
   output reg zq;
3253
   input rst;
3254
   input clk;
3255
 
3256
   parameter clear_value = 0;
3257
   parameter set_value = 1;
3258
   parameter wrap_value = 8;
3259
   parameter level1_value = 15;
3260
 
3261
   reg  [length:1] qi;
3262
   reg lfsr_fb;
3263
   wire [length:1] q_next;
3264
   reg [32:1] polynom;
3265
   integer i;
3266
 
3267
   always @ (qi)
3268
   begin
3269
        case (length)
3270
         2: polynom = 32'b11;                               // 0x3
3271
         3: polynom = 32'b110;                              // 0x6
3272
         4: polynom = 32'b1100;                             // 0xC
3273
         5: polynom = 32'b10100;                            // 0x14
3274
         6: polynom = 32'b110000;                           // 0x30
3275
         7: polynom = 32'b1100000;                          // 0x60
3276
         8: polynom = 32'b10111000;                         // 0xb8
3277
         9: polynom = 32'b100010000;                        // 0x110
3278
        10: polynom = 32'b1001000000;                       // 0x240
3279
        11: polynom = 32'b10100000000;                      // 0x500
3280
        12: polynom = 32'b100000101001;                     // 0x829
3281
        13: polynom = 32'b1000000001100;                    // 0x100C
3282
        14: polynom = 32'b10000000010101;                   // 0x2015
3283
        15: polynom = 32'b110000000000000;                  // 0x6000
3284
        16: polynom = 32'b1101000000001000;                 // 0xD008
3285
        17: polynom = 32'b10010000000000000;                // 0x12000
3286
        18: polynom = 32'b100000010000000000;               // 0x20400
3287
        19: polynom = 32'b1000000000000100011;              // 0x40023
3288 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
3289 22 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
3290
        22: polynom = 32'b1100000000000000000000;           // 0x300000
3291
        23: polynom = 32'b10000100000000000000000;          // 0x420000
3292
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
3293
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
3294
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
3295
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
3296
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
3297
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
3298
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
3299
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
3300
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
3301
        default: polynom = 32'b0;
3302
        endcase
3303
        lfsr_fb = qi[length];
3304
        for (i=length-1; i>=1; i=i-1) begin
3305
            if (polynom[i])
3306
                lfsr_fb = lfsr_fb  ~^ qi[i];
3307
        end
3308
    end
3309
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
3310
 
3311
   always @ (posedge clk or posedge rst)
3312
     if (rst)
3313
       qi <= {length{1'b0}};
3314
     else
3315
     if (cke)
3316
       qi <= q_next;
3317
 
3318
   assign q = qi;
3319
 
3320
 
3321
   always @ (posedge clk or posedge rst)
3322
     if (rst)
3323
       zq <= 1'b1;
3324
     else
3325
     if (cke)
3326
       zq <= q_next == {length{1'b0}};
3327
endmodule
3328 40 unneback
`endif
3329
`ifdef CNT_LFSR_CE_REW_L1
3330 22 unneback
//////////////////////////////////////////////////////////////////////
3331
////                                                              ////
3332
////  Versatile counter                                           ////
3333
////                                                              ////
3334
////  Description                                                 ////
3335
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3336
////  counter                                                     ////
3337
////                                                              ////
3338
////  To Do:                                                      ////
3339
////   - add LFSR with more taps                                  ////
3340
////                                                              ////
3341
////  Author(s):                                                  ////
3342
////      - Michael Unneback, unneback@opencores.org              ////
3343
////        ORSoC AB                                              ////
3344
////                                                              ////
3345
//////////////////////////////////////////////////////////////////////
3346
////                                                              ////
3347
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3348
////                                                              ////
3349
//// This source file may be used and distributed without         ////
3350
//// restriction provided that this copyright statement is not    ////
3351
//// removed from the file and that any derivative work contains  ////
3352
//// the original copyright notice and the associated disclaimer. ////
3353
////                                                              ////
3354
//// This source file is free software; you can redistribute it   ////
3355
//// and/or modify it under the terms of the GNU Lesser General   ////
3356
//// Public License as published by the Free Software Foundation; ////
3357
//// either version 2.1 of the License, or (at your option) any   ////
3358
//// later version.                                               ////
3359
////                                                              ////
3360
//// This source is distributed in the hope that it will be       ////
3361
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3362
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3363
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3364
//// details.                                                     ////
3365
////                                                              ////
3366
//// You should have received a copy of the GNU Lesser General    ////
3367
//// Public License along with this source; if not, download it   ////
3368
//// from http://www.opencores.org/lgpl.shtml                     ////
3369
////                                                              ////
3370
//////////////////////////////////////////////////////////////////////
3371 6 unneback
 
3372
// LFSR counter
3373
 
3374 40 unneback
`define MODULE cnt_lfsr_ce_rew_l1
3375
module `BASE`MODULE (
3376
`undef MODULE
3377
 cke, rew, level1, rst, clk);
3378
 
3379 6 unneback
   parameter length = 4;
3380
   input cke;
3381
   input rew;
3382
   output reg level1;
3383
   input rst;
3384
   input clk;
3385
 
3386
   parameter clear_value = 0;
3387
   parameter set_value = 1;
3388
   parameter wrap_value = 8;
3389
   parameter level1_value = 15;
3390
 
3391 29 unneback
   wire clear;
3392 30 unneback
   assign clear = 1'b0;
3393 6 unneback
   reg  [length:1] qi;
3394
   reg lfsr_fb, lfsr_fb_rew;
3395
   wire  [length:1] q_next, q_next_fw, q_next_rew;
3396
   reg [32:1] polynom_rew;
3397
   integer j;
3398
   reg [32:1] polynom;
3399
   integer i;
3400
 
3401
   always @ (qi)
3402
   begin
3403
        case (length)
3404
         2: polynom = 32'b11;                               // 0x3
3405
         3: polynom = 32'b110;                              // 0x6
3406
         4: polynom = 32'b1100;                             // 0xC
3407
         5: polynom = 32'b10100;                            // 0x14
3408
         6: polynom = 32'b110000;                           // 0x30
3409
         7: polynom = 32'b1100000;                          // 0x60
3410
         8: polynom = 32'b10111000;                         // 0xb8
3411
         9: polynom = 32'b100010000;                        // 0x110
3412
        10: polynom = 32'b1001000000;                       // 0x240
3413
        11: polynom = 32'b10100000000;                      // 0x500
3414
        12: polynom = 32'b100000101001;                     // 0x829
3415
        13: polynom = 32'b1000000001100;                    // 0x100C
3416
        14: polynom = 32'b10000000010101;                   // 0x2015
3417
        15: polynom = 32'b110000000000000;                  // 0x6000
3418
        16: polynom = 32'b1101000000001000;                 // 0xD008
3419
        17: polynom = 32'b10010000000000000;                // 0x12000
3420
        18: polynom = 32'b100000010000000000;               // 0x20400
3421
        19: polynom = 32'b1000000000000100011;              // 0x40023
3422 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
3423 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
3424
        22: polynom = 32'b1100000000000000000000;           // 0x300000
3425
        23: polynom = 32'b10000100000000000000000;          // 0x420000
3426
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
3427
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
3428
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
3429
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
3430
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
3431
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
3432
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
3433
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
3434
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
3435
        default: polynom = 32'b0;
3436
        endcase
3437
        lfsr_fb = qi[length];
3438
        for (i=length-1; i>=1; i=i-1) begin
3439
            if (polynom[i])
3440
                lfsr_fb = lfsr_fb  ~^ qi[i];
3441
        end
3442
    end
3443
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
3444
   always @ (qi)
3445
   begin
3446
        case (length)
3447
         2: polynom_rew = 32'b11;
3448
         3: polynom_rew = 32'b110;
3449
         4: polynom_rew = 32'b1100;
3450
         5: polynom_rew = 32'b10100;
3451
         6: polynom_rew = 32'b110000;
3452
         7: polynom_rew = 32'b1100000;
3453
         8: polynom_rew = 32'b10111000;
3454
         9: polynom_rew = 32'b100010000;
3455
        10: polynom_rew = 32'b1001000000;
3456
        11: polynom_rew = 32'b10100000000;
3457
        12: polynom_rew = 32'b100000101001;
3458
        13: polynom_rew = 32'b1000000001100;
3459
        14: polynom_rew = 32'b10000000010101;
3460
        15: polynom_rew = 32'b110000000000000;
3461
        16: polynom_rew = 32'b1101000000001000;
3462
        17: polynom_rew = 32'b10010000000000000;
3463
        18: polynom_rew = 32'b100000010000000000;
3464
        19: polynom_rew = 32'b1000000000000100011;
3465
        20: polynom_rew = 32'b10000010000000000000;
3466
        21: polynom_rew = 32'b101000000000000000000;
3467
        22: polynom_rew = 32'b1100000000000000000000;
3468
        23: polynom_rew = 32'b10000100000000000000000;
3469
        24: polynom_rew = 32'b111000010000000000000000;
3470
        25: polynom_rew = 32'b1001000000000000000000000;
3471
        26: polynom_rew = 32'b10000000000000000000100011;
3472
        27: polynom_rew = 32'b100000000000000000000010011;
3473
        28: polynom_rew = 32'b1100100000000000000000000000;
3474
        29: polynom_rew = 32'b10100000000000000000000000000;
3475
        30: polynom_rew = 32'b100000000000000000000000101001;
3476
        31: polynom_rew = 32'b1001000000000000000000000000000;
3477
        32: polynom_rew = 32'b10000000001000000000000000000011;
3478
        default: polynom_rew = 32'b0;
3479
        endcase
3480
        // rotate left
3481
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
3482
        lfsr_fb_rew = qi[length];
3483
        for (i=length-1; i>=1; i=i-1) begin
3484
            if (polynom_rew[i])
3485
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
3486
        end
3487
    end
3488
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
3489
   assign q_next = rew ? q_next_rew : q_next_fw;
3490
 
3491
   always @ (posedge clk or posedge rst)
3492
     if (rst)
3493
       qi <= {length{1'b0}};
3494
     else
3495
     if (cke)
3496
       qi <= q_next;
3497
 
3498
 
3499
 
3500
    always @ (posedge clk or posedge rst)
3501
    if (rst)
3502
        level1 <= 1'b0;
3503
    else
3504
    if (cke)
3505 29 unneback
    if (clear)
3506
        level1 <= 1'b0;
3507
    else if (q_next == level1_value)
3508 6 unneback
        level1 <= 1'b1;
3509
    else if (qi == level1_value & rew)
3510
        level1 <= 1'b0;
3511
endmodule
3512 40 unneback
`endif
3513
`ifdef CNT_GRAY
3514 6 unneback
//////////////////////////////////////////////////////////////////////
3515
////                                                              ////
3516
////  Versatile counter                                           ////
3517
////                                                              ////
3518
////  Description                                                 ////
3519
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3520
////  counter                                                     ////
3521
////                                                              ////
3522
////  To Do:                                                      ////
3523
////   - add LFSR with more taps                                  ////
3524
////                                                              ////
3525
////  Author(s):                                                  ////
3526
////      - Michael Unneback, unneback@opencores.org              ////
3527
////        ORSoC AB                                              ////
3528
////                                                              ////
3529
//////////////////////////////////////////////////////////////////////
3530
////                                                              ////
3531
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3532
////                                                              ////
3533
//// This source file may be used and distributed without         ////
3534
//// restriction provided that this copyright statement is not    ////
3535
//// removed from the file and that any derivative work contains  ////
3536
//// the original copyright notice and the associated disclaimer. ////
3537
////                                                              ////
3538
//// This source file is free software; you can redistribute it   ////
3539
//// and/or modify it under the terms of the GNU Lesser General   ////
3540
//// Public License as published by the Free Software Foundation; ////
3541
//// either version 2.1 of the License, or (at your option) any   ////
3542
//// later version.                                               ////
3543
////                                                              ////
3544
//// This source is distributed in the hope that it will be       ////
3545
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3546
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3547
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3548
//// details.                                                     ////
3549
////                                                              ////
3550
//// You should have received a copy of the GNU Lesser General    ////
3551
//// Public License along with this source; if not, download it   ////
3552
//// from http://www.opencores.org/lgpl.shtml                     ////
3553
////                                                              ////
3554
//////////////////////////////////////////////////////////////////////
3555
 
3556
// GRAY counter
3557
 
3558 40 unneback
`define MODULE cnt_gray
3559
module `BASE`MODULE (
3560
`undef MODULE
3561
 q, rst, clk);
3562
 
3563 6 unneback
   parameter length = 4;
3564
   output reg [length:1] q;
3565
   input rst;
3566
   input clk;
3567
 
3568
   parameter clear_value = 0;
3569
   parameter set_value = 1;
3570
   parameter wrap_value = 8;
3571
   parameter level1_value = 15;
3572
 
3573
   reg  [length:1] qi;
3574
   wire [length:1] q_next;
3575
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3576
 
3577
   always @ (posedge clk or posedge rst)
3578
     if (rst)
3579
       qi <= {length{1'b0}};
3580
     else
3581
       qi <= q_next;
3582
 
3583
   always @ (posedge clk or posedge rst)
3584
     if (rst)
3585
       q <= {length{1'b0}};
3586
     else
3587
         q <= (q_next>>1) ^ q_next;
3588
 
3589
endmodule
3590 40 unneback
`endif
3591
`ifdef CNT_GRAY_CE
3592 6 unneback
//////////////////////////////////////////////////////////////////////
3593
////                                                              ////
3594
////  Versatile counter                                           ////
3595
////                                                              ////
3596
////  Description                                                 ////
3597
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3598
////  counter                                                     ////
3599
////                                                              ////
3600
////  To Do:                                                      ////
3601
////   - add LFSR with more taps                                  ////
3602
////                                                              ////
3603
////  Author(s):                                                  ////
3604
////      - Michael Unneback, unneback@opencores.org              ////
3605
////        ORSoC AB                                              ////
3606
////                                                              ////
3607
//////////////////////////////////////////////////////////////////////
3608
////                                                              ////
3609
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3610
////                                                              ////
3611
//// This source file may be used and distributed without         ////
3612
//// restriction provided that this copyright statement is not    ////
3613
//// removed from the file and that any derivative work contains  ////
3614
//// the original copyright notice and the associated disclaimer. ////
3615
////                                                              ////
3616
//// This source file is free software; you can redistribute it   ////
3617
//// and/or modify it under the terms of the GNU Lesser General   ////
3618
//// Public License as published by the Free Software Foundation; ////
3619
//// either version 2.1 of the License, or (at your option) any   ////
3620
//// later version.                                               ////
3621
////                                                              ////
3622
//// This source is distributed in the hope that it will be       ////
3623
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3624
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3625
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3626
//// details.                                                     ////
3627
////                                                              ////
3628
//// You should have received a copy of the GNU Lesser General    ////
3629
//// Public License along with this source; if not, download it   ////
3630
//// from http://www.opencores.org/lgpl.shtml                     ////
3631
////                                                              ////
3632
//////////////////////////////////////////////////////////////////////
3633
 
3634
// GRAY counter
3635
 
3636 40 unneback
`define MODULE cnt_gray_ce
3637
module `BASE`MODULE (
3638
`undef MODULE
3639
 cke, q, rst, clk);
3640
 
3641 6 unneback
   parameter length = 4;
3642
   input cke;
3643
   output reg [length:1] q;
3644
   input rst;
3645
   input clk;
3646
 
3647
   parameter clear_value = 0;
3648
   parameter set_value = 1;
3649
   parameter wrap_value = 8;
3650
   parameter level1_value = 15;
3651
 
3652
   reg  [length:1] qi;
3653
   wire [length:1] q_next;
3654
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3655
 
3656
   always @ (posedge clk or posedge rst)
3657
     if (rst)
3658
       qi <= {length{1'b0}};
3659
     else
3660
     if (cke)
3661
       qi <= q_next;
3662
 
3663
   always @ (posedge clk or posedge rst)
3664
     if (rst)
3665
       q <= {length{1'b0}};
3666
     else
3667
       if (cke)
3668
         q <= (q_next>>1) ^ q_next;
3669
 
3670
endmodule
3671 40 unneback
`endif
3672
`ifdef CNT_GRAY_CE_BIN
3673 6 unneback
//////////////////////////////////////////////////////////////////////
3674
////                                                              ////
3675
////  Versatile counter                                           ////
3676
////                                                              ////
3677
////  Description                                                 ////
3678
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3679
////  counter                                                     ////
3680
////                                                              ////
3681
////  To Do:                                                      ////
3682
////   - add LFSR with more taps                                  ////
3683
////                                                              ////
3684
////  Author(s):                                                  ////
3685
////      - Michael Unneback, unneback@opencores.org              ////
3686
////        ORSoC AB                                              ////
3687
////                                                              ////
3688
//////////////////////////////////////////////////////////////////////
3689
////                                                              ////
3690
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3691
////                                                              ////
3692
//// This source file may be used and distributed without         ////
3693
//// restriction provided that this copyright statement is not    ////
3694
//// removed from the file and that any derivative work contains  ////
3695
//// the original copyright notice and the associated disclaimer. ////
3696
////                                                              ////
3697
//// This source file is free software; you can redistribute it   ////
3698
//// and/or modify it under the terms of the GNU Lesser General   ////
3699
//// Public License as published by the Free Software Foundation; ////
3700
//// either version 2.1 of the License, or (at your option) any   ////
3701
//// later version.                                               ////
3702
////                                                              ////
3703
//// This source is distributed in the hope that it will be       ////
3704
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3705
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3706
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3707
//// details.                                                     ////
3708
////                                                              ////
3709
//// You should have received a copy of the GNU Lesser General    ////
3710
//// Public License along with this source; if not, download it   ////
3711
//// from http://www.opencores.org/lgpl.shtml                     ////
3712
////                                                              ////
3713
//////////////////////////////////////////////////////////////////////
3714
 
3715
// GRAY counter
3716
 
3717 40 unneback
`define MODULE cnt_gray_ce_bin
3718
module `BASE`MODULE (
3719
`undef MODULE
3720
 cke, q, q_bin, rst, clk);
3721
 
3722 6 unneback
   parameter length = 4;
3723
   input cke;
3724
   output reg [length:1] q;
3725
   output [length:1] q_bin;
3726
   input rst;
3727
   input clk;
3728
 
3729
   parameter clear_value = 0;
3730
   parameter set_value = 1;
3731
   parameter wrap_value = 8;
3732
   parameter level1_value = 15;
3733
 
3734
   reg  [length:1] qi;
3735
   wire [length:1] q_next;
3736
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3737
 
3738
   always @ (posedge clk or posedge rst)
3739
     if (rst)
3740
       qi <= {length{1'b0}};
3741
     else
3742
     if (cke)
3743
       qi <= q_next;
3744
 
3745
   always @ (posedge clk or posedge rst)
3746
     if (rst)
3747
       q <= {length{1'b0}};
3748
     else
3749
       if (cke)
3750
         q <= (q_next>>1) ^ q_next;
3751
 
3752
   assign q_bin = qi;
3753
 
3754
endmodule
3755 40 unneback
`endif
3756 6 unneback
//////////////////////////////////////////////////////////////////////
3757
////                                                              ////
3758
////  Versatile library, counters                                 ////
3759
////                                                              ////
3760
////  Description                                                 ////
3761
////  counters                                                    ////
3762
////                                                              ////
3763
////                                                              ////
3764
////  To Do:                                                      ////
3765
////   - add more counters                                        ////
3766
////                                                              ////
3767
////  Author(s):                                                  ////
3768
////      - Michael Unneback, unneback@opencores.org              ////
3769
////        ORSoC AB                                              ////
3770
////                                                              ////
3771
//////////////////////////////////////////////////////////////////////
3772
////                                                              ////
3773
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
3774
////                                                              ////
3775
//// This source file may be used and distributed without         ////
3776
//// restriction provided that this copyright statement is not    ////
3777
//// removed from the file and that any derivative work contains  ////
3778
//// the original copyright notice and the associated disclaimer. ////
3779
////                                                              ////
3780
//// This source file is free software; you can redistribute it   ////
3781
//// and/or modify it under the terms of the GNU Lesser General   ////
3782
//// Public License as published by the Free Software Foundation; ////
3783
//// either version 2.1 of the License, or (at your option) any   ////
3784
//// later version.                                               ////
3785
////                                                              ////
3786
//// This source is distributed in the hope that it will be       ////
3787
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3788
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3789
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3790
//// details.                                                     ////
3791
////                                                              ////
3792
//// You should have received a copy of the GNU Lesser General    ////
3793
//// Public License along with this source; if not, download it   ////
3794
//// from http://www.opencores.org/lgpl.shtml                     ////
3795
////                                                              ////
3796
//////////////////////////////////////////////////////////////////////
3797
 
3798 40 unneback
`ifdef CNT_SHREG_WRAP
3799
`define MODULE cnt_shreg_wrap
3800
module `BASE`MODULE ( q, rst, clk);
3801
`undef MODULE
3802 6 unneback
 
3803
   parameter length = 4;
3804
   output reg [0:length-1] q;
3805
   input rst;
3806
   input clk;
3807
 
3808
    always @ (posedge clk or posedge rst)
3809
    if (rst)
3810
        q <= {1'b1,{length-1{1'b0}}};
3811
    else
3812
        q <= {q[length-1],q[0:length-2]};
3813
 
3814
endmodule
3815 40 unneback
`endif
3816 6 unneback
 
3817 40 unneback
`ifdef CNT_SHREG_CE_WRAP
3818
`define MODULE cnt_shreg_ce_wrap
3819
module `BASE`MODULE ( cke, q, rst, clk);
3820
`undef MODULE
3821 6 unneback
 
3822
   parameter length = 4;
3823
   input cke;
3824
   output reg [0:length-1] q;
3825
   input rst;
3826
   input clk;
3827
 
3828
    always @ (posedge clk or posedge rst)
3829
    if (rst)
3830
        q <= {1'b1,{length-1{1'b0}}};
3831
    else
3832
        if (cke)
3833
            q <= {q[length-1],q[0:length-2]};
3834
 
3835
endmodule
3836 40 unneback
`endif
3837 6 unneback
 
3838 105 unneback
`ifdef CNT_SHREG_CLEAR
3839
`define MODULE cnt_shreg_clear
3840
module `BASE`MODULE ( clear, q, rst, clk);
3841
`undef MODULE
3842
 
3843
   parameter length = 4;
3844
   input clear;
3845
   output reg [0:length-1] q;
3846
   input rst;
3847
   input clk;
3848
 
3849
    always @ (posedge clk or posedge rst)
3850
    if (rst)
3851
        q <= {1'b1,{length-1{1'b0}}};
3852
    else
3853
        if (clear)
3854
            q <= {1'b1,{length-1{1'b0}}};
3855
        else
3856
            q <= q >> 1;
3857
 
3858
endmodule
3859
`endif
3860
 
3861 40 unneback
`ifdef CNT_SHREG_CE_CLEAR
3862
`define MODULE cnt_shreg_ce_clear
3863
module `BASE`MODULE ( cke, clear, q, rst, clk);
3864
`undef MODULE
3865 6 unneback
 
3866
   parameter length = 4;
3867
   input cke, clear;
3868
   output reg [0:length-1] q;
3869
   input rst;
3870
   input clk;
3871
 
3872
    always @ (posedge clk or posedge rst)
3873
    if (rst)
3874
        q <= {1'b1,{length-1{1'b0}}};
3875
    else
3876
        if (cke)
3877
            if (clear)
3878
                q <= {1'b1,{length-1{1'b0}}};
3879
            else
3880
                q <= q >> 1;
3881
 
3882
endmodule
3883 40 unneback
`endif
3884 6 unneback
 
3885 40 unneback
`ifdef CNT_SHREG_CE_CLEAR_WRAP
3886
`define MODULE cnt_shreg_ce_clear_wrap
3887
module `BASE`MODULE ( cke, clear, q, rst, clk);
3888
`undef MODULE
3889 6 unneback
 
3890
   parameter length = 4;
3891
   input cke, clear;
3892
   output reg [0:length-1] q;
3893
   input rst;
3894
   input clk;
3895
 
3896
    always @ (posedge clk or posedge rst)
3897
    if (rst)
3898
        q <= {1'b1,{length-1{1'b0}}};
3899
    else
3900
        if (cke)
3901
            if (clear)
3902
                q <= {1'b1,{length-1{1'b0}}};
3903
            else
3904
            q <= {q[length-1],q[0:length-2]};
3905
 
3906
endmodule
3907 40 unneback
`endif
3908 6 unneback
//////////////////////////////////////////////////////////////////////
3909
////                                                              ////
3910
////  Versatile library, memories                                 ////
3911
////                                                              ////
3912
////  Description                                                 ////
3913
////  memories                                                    ////
3914
////                                                              ////
3915
////                                                              ////
3916
////  To Do:                                                      ////
3917
////   - add more memory types                                    ////
3918
////                                                              ////
3919
////  Author(s):                                                  ////
3920
////      - Michael Unneback, unneback@opencores.org              ////
3921
////        ORSoC AB                                              ////
3922
////                                                              ////
3923
//////////////////////////////////////////////////////////////////////
3924
////                                                              ////
3925
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
3926
////                                                              ////
3927
//// This source file may be used and distributed without         ////
3928
//// restriction provided that this copyright statement is not    ////
3929
//// removed from the file and that any derivative work contains  ////
3930
//// the original copyright notice and the associated disclaimer. ////
3931
////                                                              ////
3932
//// This source file is free software; you can redistribute it   ////
3933
//// and/or modify it under the terms of the GNU Lesser General   ////
3934
//// Public License as published by the Free Software Foundation; ////
3935
//// either version 2.1 of the License, or (at your option) any   ////
3936
//// later version.                                               ////
3937
////                                                              ////
3938
//// This source is distributed in the hope that it will be       ////
3939
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3940
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3941
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3942
//// details.                                                     ////
3943
////                                                              ////
3944
//// You should have received a copy of the GNU Lesser General    ////
3945
//// Public License along with this source; if not, download it   ////
3946
//// from http://www.opencores.org/lgpl.shtml                     ////
3947
////                                                              ////
3948
//////////////////////////////////////////////////////////////////////
3949
 
3950 40 unneback
`ifdef ROM_INIT
3951 6 unneback
/// ROM
3952 40 unneback
`define MODULE rom_init
3953
module `BASE`MODULE ( adr, q, clk);
3954
`undef MODULE
3955 6 unneback
 
3956 7 unneback
   parameter data_width = 32;
3957
   parameter addr_width = 8;
3958 75 unneback
   parameter mem_size = 1<<addr_width;
3959 7 unneback
   input [(addr_width-1):0]       adr;
3960
   output reg [(data_width-1):0] q;
3961
   input                         clk;
3962 75 unneback
   reg [data_width-1:0] rom [mem_size-1:0];
3963 7 unneback
   parameter memory_file = "vl_rom.vmem";
3964
   initial
3965
     begin
3966
        $readmemh(memory_file, rom);
3967
     end
3968
 
3969
   always @ (posedge clk)
3970
     q <= rom[adr];
3971 6 unneback
 
3972 7 unneback
endmodule
3973 40 unneback
`endif
3974 7 unneback
 
3975 40 unneback
`ifdef RAM
3976
`define MODULE ram
3977 6 unneback
// Single port RAM
3978 40 unneback
module `BASE`MODULE ( d, adr, we, q, clk);
3979
`undef MODULE
3980 6 unneback
 
3981
   parameter data_width = 32;
3982
   parameter addr_width = 8;
3983 75 unneback
   parameter mem_size = 1<<addr_width;
3984 100 unneback
   parameter debug = 0;
3985 6 unneback
   input [(data_width-1):0]      d;
3986
   input [(addr_width-1):0]       adr;
3987
   input                         we;
3988 7 unneback
   output reg [(data_width-1):0] q;
3989 6 unneback
   input                         clk;
3990 98 unneback
   reg [data_width-1:0] ram [mem_size-1:0];
3991 100 unneback
 
3992
    parameter memory_init = 0;
3993
    parameter memory_file = "vl_ram.vmem";
3994
    generate
3995
    if (memory_init == 1) begin : init_mem
3996
        initial
3997
            $readmemh(memory_file, ram);
3998
   end else if (memory_init == 2) begin : init_zero
3999
        integer k;
4000
        initial
4001
            for (k = 0; k < mem_size; k = k + 1)
4002
                ram[k] = 0;
4003 7 unneback
   end
4004
   endgenerate
4005
 
4006 100 unneback
    generate
4007
    if (debug==1) begin : debug_we
4008
        always @ (posedge clk)
4009
        if (we)
4010
            $display ("Value %h written at address %h : time %t", d, adr, $time);
4011
 
4012
    end
4013
    endgenerate
4014
 
4015 6 unneback
   always @ (posedge clk)
4016
   begin
4017
   if (we)
4018
     ram[adr] <= d;
4019
   q <= ram[adr];
4020
   end
4021
 
4022
endmodule
4023 40 unneback
`endif
4024 6 unneback
 
4025 40 unneback
`ifdef RAM_BE
4026
`define MODULE ram_be
4027 91 unneback
module `BASE`MODULE ( d, adr, be, we, q, clk);
4028 40 unneback
`undef MODULE
4029
 
4030 7 unneback
   parameter data_width = 32;
4031 72 unneback
   parameter addr_width = 6;
4032 75 unneback
   parameter mem_size = 1<<addr_width;
4033 7 unneback
   input [(data_width-1):0]      d;
4034
   input [(addr_width-1):0]       adr;
4035 73 unneback
   input [(data_width/8)-1:0]    be;
4036 7 unneback
   input                         we;
4037
   output reg [(data_width-1):0] q;
4038
   input                         clk;
4039
 
4040 85 unneback
 
4041 65 unneback
`ifdef SYSTEMVERILOG
4042 95 unneback
    // use a multi-dimensional packed array
4043
    //t o model individual bytes within the word
4044
    logic [data_width/8-1:0][7:0] ram [0:mem_size-1];// # words = 1 << address width
4045 65 unneback
`else
4046 85 unneback
    reg [data_width-1:0] ram [mem_size-1:0];
4047
    wire [data_width/8-1:0] cke;
4048 65 unneback
`endif
4049
 
4050 100 unneback
    parameter memory_init = 0;
4051
    parameter memory_file = "vl_ram.vmem";
4052
    generate
4053
    if (memory_init == 1) begin : init_mem
4054
        initial
4055
            $readmemh(memory_file, ram);
4056
    end else if (memory_init == 2) begin : init_zero
4057
        integer k;
4058
        initial
4059
            for (k = 0; k < mem_size; k = k + 1)
4060
                ram[k] = 0;
4061
    end
4062 7 unneback
   endgenerate
4063
 
4064 60 unneback
`ifdef SYSTEMVERILOG
4065
 
4066
always_ff@(posedge clk)
4067
begin
4068 95 unneback
    if(we) begin
4069 86 unneback
        if(be[3]) ram[adr][3] <= d[31:24];
4070
        if(be[2]) ram[adr][2] <= d[23:16];
4071
        if(be[1]) ram[adr][1] <= d[15:8];
4072
        if(be[0]) ram[adr][0] <= d[7:0];
4073 60 unneback
    end
4074 90 unneback
        q <= ram[adr];
4075 60 unneback
end
4076
 
4077
`else
4078
 
4079 85 unneback
assign cke = {data_width/8{we}} & be;
4080 7 unneback
   genvar i;
4081 85 unneback
   generate for (i=0;i<data_width/8;i=i+1) begin : be_ram
4082 7 unneback
      always @ (posedge clk)
4083 85 unneback
      if (cke[i])
4084 7 unneback
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
4085
   end
4086
   endgenerate
4087
 
4088
   always @ (posedge clk)
4089
      q <= ram[adr];
4090
 
4091 60 unneback
`endif
4092
 
4093 93 unneback
`ifdef verilator
4094 85 unneback
   // Function to access RAM (for use by Verilator).
4095
   function [31:0] get_mem;
4096
      // verilator public
4097 90 unneback
      input [addr_width-1:0]             addr;
4098 85 unneback
      get_mem = ram[addr];
4099
   endfunction // get_mem
4100
 
4101
   // Function to write RAM (for use by Verilator).
4102
   function set_mem;
4103
      // verilator public
4104 90 unneback
      input [addr_width-1:0]             addr;
4105
      input [data_width-1:0]             data;
4106 85 unneback
      ram[addr] = data;
4107
   endfunction // set_mem
4108 93 unneback
`endif
4109 85 unneback
 
4110 7 unneback
endmodule
4111 40 unneback
`endif
4112 7 unneback
 
4113 40 unneback
`ifdef DPRAM_1R1W
4114
`define MODULE dpram_1r1w
4115
module `BASE`MODULE ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
4116
`undef MODULE
4117 6 unneback
   parameter data_width = 32;
4118
   parameter addr_width = 8;
4119 75 unneback
   parameter mem_size = 1<<addr_width;
4120 6 unneback
   input [(data_width-1):0]      d_a;
4121
   input [(addr_width-1):0]       adr_a;
4122
   input [(addr_width-1):0]       adr_b;
4123
   input                         we_a;
4124 118 unneback
   output reg [(data_width-1):0]          q_b;
4125 6 unneback
   input                         clk_a, clk_b;
4126 119 unneback
   reg [data_width-1:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
4127 7 unneback
 
4128 100 unneback
    parameter memory_init = 0;
4129
    parameter memory_file = "vl_ram.vmem";
4130
    parameter debug = 0;
4131
 
4132
    generate
4133
    if (memory_init == 1) begin : init_mem
4134
        initial
4135
            $readmemh(memory_file, ram);
4136
    end else if (memory_init == 2) begin : init_zero
4137
        integer k;
4138
        initial
4139
            for (k = 0; k < mem_size; k = k + 1)
4140
                ram[k] = 0;
4141
    end
4142 7 unneback
   endgenerate
4143
 
4144 100 unneback
    generate
4145
    if (debug==1) begin : debug_we
4146
        always @ (posedge clk_a)
4147
        if (we_a)
4148
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
4149
 
4150
    end
4151
    endgenerate
4152
 
4153 6 unneback
   always @ (posedge clk_a)
4154
   if (we_a)
4155
     ram[adr_a] <= d_a;
4156 118 unneback
 
4157 6 unneback
   always @ (posedge clk_b)
4158 118 unneback
      q_b = ram[adr_b];
4159 40 unneback
 
4160 6 unneback
endmodule
4161 40 unneback
`endif
4162 6 unneback
 
4163 40 unneback
`ifdef DPRAM_2R1W
4164
`define MODULE dpram_2r1w
4165
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
4166
`undef MODULE
4167
 
4168 6 unneback
   parameter data_width = 32;
4169
   parameter addr_width = 8;
4170 75 unneback
   parameter mem_size = 1<<addr_width;
4171 6 unneback
   input [(data_width-1):0]      d_a;
4172
   input [(addr_width-1):0]       adr_a;
4173
   input [(addr_width-1):0]       adr_b;
4174
   input                         we_a;
4175
   output [(data_width-1):0]      q_b;
4176
   output reg [(data_width-1):0] q_a;
4177
   input                         clk_a, clk_b;
4178
   reg [(data_width-1):0]         q_b;
4179 119 unneback
   reg [data_width-1:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
4180 7 unneback
 
4181 100 unneback
    parameter memory_init = 0;
4182
    parameter memory_file = "vl_ram.vmem";
4183
    parameter debug = 0;
4184
 
4185
    generate
4186
    if (memory_init == 1) begin : init_mem
4187
        initial
4188
            $readmemh(memory_file, ram);
4189
    end else if (memory_init == 2) begin : init_zero
4190
        integer k;
4191
        initial
4192
            for (k = 0; k < mem_size; k = k + 1)
4193
                ram[k] = 0;
4194
    end
4195 7 unneback
   endgenerate
4196
 
4197 100 unneback
    generate
4198
    if (debug==1) begin : debug_we
4199
        always @ (posedge clk_a)
4200
        if (we_a)
4201
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
4202
 
4203
    end
4204
    endgenerate
4205
 
4206 6 unneback
   always @ (posedge clk_a)
4207
     begin
4208
        q_a <= ram[adr_a];
4209
        if (we_a)
4210
             ram[adr_a] <= d_a;
4211
     end
4212
   always @ (posedge clk_b)
4213
          q_b <= ram[adr_b];
4214
endmodule
4215 40 unneback
`endif
4216 6 unneback
 
4217 100 unneback
`ifdef DPRAM_1R2W
4218
`define MODULE dpram_1r2w
4219
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, adr_b, we_b, clk_b );
4220
`undef MODULE
4221
 
4222
   parameter data_width = 32;
4223
   parameter addr_width = 8;
4224
   parameter mem_size = 1<<addr_width;
4225
   input [(data_width-1):0]      d_a;
4226
   input [(addr_width-1):0]       adr_a;
4227
   input [(addr_width-1):0]       adr_b;
4228
   input                         we_a;
4229
   input [(data_width-1):0]       d_b;
4230
   output reg [(data_width-1):0] q_a;
4231
   input                         we_b;
4232
   input                         clk_a, clk_b;
4233
   reg [(data_width-1):0]         q_b;
4234 119 unneback
   reg [data_width-1:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
4235 100 unneback
 
4236
    parameter memory_init = 0;
4237
    parameter memory_file = "vl_ram.vmem";
4238
    parameter debug = 0;
4239
 
4240
    generate
4241
    if (memory_init == 1) begin : init_mem
4242
        initial
4243
            $readmemh(memory_file, ram);
4244
    end else if (memory_init == 2) begin : init_zero
4245
        integer k;
4246
        initial
4247
            for (k = 0; k < mem_size; k = k + 1)
4248
                ram[k] = 0;
4249
    end
4250
   endgenerate
4251
 
4252
    generate
4253
    if (debug==1) begin : debug_we
4254
        always @ (posedge clk_a)
4255
        if (we_a)
4256
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
4257
        always @ (posedge clk_b)
4258
        if (we_b)
4259
            $display ("Debug: Value %h written at address %h : time %t", d_b, adr_b, $time);
4260
    end
4261
    endgenerate
4262
 
4263
   always @ (posedge clk_a)
4264
     begin
4265
        q_a <= ram[adr_a];
4266
        if (we_a)
4267
             ram[adr_a] <= d_a;
4268
     end
4269
   always @ (posedge clk_b)
4270
     begin
4271
        if (we_b)
4272
          ram[adr_b] <= d_b;
4273
     end
4274
endmodule
4275
`endif
4276
 
4277 40 unneback
`ifdef DPRAM_2R2W
4278
`define MODULE dpram_2r2w
4279
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
4280
`undef MODULE
4281
 
4282 6 unneback
   parameter data_width = 32;
4283
   parameter addr_width = 8;
4284 75 unneback
   parameter mem_size = 1<<addr_width;
4285 6 unneback
   input [(data_width-1):0]      d_a;
4286
   input [(addr_width-1):0]       adr_a;
4287
   input [(addr_width-1):0]       adr_b;
4288
   input                         we_a;
4289
   output [(data_width-1):0]      q_b;
4290
   input [(data_width-1):0]       d_b;
4291
   output reg [(data_width-1):0] q_a;
4292
   input                         we_b;
4293
   input                         clk_a, clk_b;
4294
   reg [(data_width-1):0]         q_b;
4295 119 unneback
   reg [data_width-1:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
4296 7 unneback
 
4297 100 unneback
    parameter memory_init = 0;
4298
    parameter memory_file = "vl_ram.vmem";
4299
    parameter debug = 0;
4300
 
4301
    generate
4302
    if (memory_init) begin : init_mem
4303
        initial
4304
            $readmemh(memory_file, ram);
4305
    end else if (memory_init == 2) begin : init_zero
4306
        integer k;
4307
        initial
4308
            for (k = 0; k < mem_size; k = k + 1)
4309
                ram[k] = 0;
4310
    end
4311 7 unneback
   endgenerate
4312
 
4313 100 unneback
    generate
4314
    if (debug==1) begin : debug_we
4315
        always @ (posedge clk_a)
4316
        if (we_a)
4317
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
4318
        always @ (posedge clk_b)
4319
        if (we_b)
4320
            $display ("Debug: Value %h written at address %h : time %t", d_b, adr_b, $time);
4321
    end
4322
    endgenerate
4323
 
4324 6 unneback
   always @ (posedge clk_a)
4325
     begin
4326
        q_a <= ram[adr_a];
4327
        if (we_a)
4328
             ram[adr_a] <= d_a;
4329
     end
4330
   always @ (posedge clk_b)
4331
     begin
4332
        q_b <= ram[adr_b];
4333
        if (we_b)
4334
          ram[adr_b] <= d_b;
4335
     end
4336
endmodule
4337 40 unneback
`endif
4338 6 unneback
 
4339 83 unneback
 
4340 75 unneback
`ifdef DPRAM_BE_2R2W
4341
`define MODULE dpram_be_2r2w
4342 92 unneback
module `BASE`MODULE ( d_a, q_a, adr_a, be_a, we_a, clk_a, d_b, q_b, adr_b, be_b, we_b, clk_b );
4343 75 unneback
`undef MODULE
4344
 
4345
   parameter a_data_width = 32;
4346
   parameter a_addr_width = 8;
4347 95 unneback
   parameter b_data_width = 64; //a_data_width;
4348 124 unneback
   //localparam b_addr_width = a_data_width * a_addr_width / b_data_width;
4349
   localparam b_addr_width =
4350 125 unneback
        (a_data_width==b_data_width) ? a_addr_width :
4351
        (a_data_width==b_data_width*2) ? a_addr_width+1 :
4352
        (a_data_width==b_data_width*4) ? a_addr_width+2 :
4353
        (a_data_width==b_data_width*8) ? a_addr_width+3 :
4354
        (a_data_width==b_data_width*16) ? a_addr_width+4 :
4355
        (a_data_width==b_data_width*32) ? a_addr_width+5 :
4356
        (a_data_width==b_data_width/2) ? a_addr_width-1 :
4357
        (a_data_width==b_data_width/4) ? a_addr_width-2 :
4358
        (a_data_width==b_data_width/8) ? a_addr_width-3 :
4359
        (a_data_width==b_data_width/16) ? a_addr_width-4 :
4360
        (a_data_width==b_data_width/32) ? a_addr_width-5 : 0;
4361 124 unneback
 
4362 95 unneback
   localparam ratio = (a_addr_width>b_addr_width) ? (a_addr_width/b_addr_width) : (b_addr_width/a_addr_width);
4363
   parameter mem_size = (a_addr_width>b_addr_width) ? (1<<b_addr_width) : (1<<a_addr_width);
4364 91 unneback
 
4365 100 unneback
   parameter memory_init = 0;
4366 95 unneback
   parameter memory_file = "vl_ram.vmem";
4367 100 unneback
   parameter debug = 0;
4368 95 unneback
 
4369 75 unneback
   input [(a_data_width-1):0]      d_a;
4370 91 unneback
   input [(a_addr_width-1):0]       adr_a;
4371
   input [(a_data_width/8-1):0]    be_a;
4372
   input                           we_a;
4373 75 unneback
   output reg [(a_data_width-1):0] q_a;
4374 91 unneback
   input [(b_data_width-1):0]       d_b;
4375
   input [(b_addr_width-1):0]       adr_b;
4376 92 unneback
   input [(b_data_width/8-1):0]    be_b;
4377
   input                           we_b;
4378
   output reg [(b_data_width-1):0]          q_b;
4379 91 unneback
   input                           clk_a, clk_b;
4380 75 unneback
 
4381 100 unneback
    generate
4382
    if (debug==1) begin : debug_we
4383
        always @ (posedge clk_a)
4384
        if (we_a)
4385
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
4386
        always @ (posedge clk_b)
4387
        if (we_b)
4388
            $display ("Debug: Value %h written at address %h : time %t", d_b, adr_b, $time);
4389
    end
4390
    endgenerate
4391
 
4392
 
4393 91 unneback
`ifdef SYSTEMVERILOG
4394
// use a multi-dimensional packed array
4395
//to model individual bytes within the word
4396
 
4397 75 unneback
generate
4398 91 unneback
if (a_data_width==32 & b_data_width==32) begin : dpram_3232
4399 75 unneback
 
4400 98 unneback
    logic [0:3][7:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
4401 95 unneback
 
4402
    initial
4403 100 unneback
        if (memory_init==1)
4404 95 unneback
            $readmemh(memory_file, ram);
4405 100 unneback
 
4406
    integer k;
4407
    initial
4408
        if (memory_init==2)
4409
            for (k = 0; k < mem_size; k = k + 1)
4410
                ram[k] = 0;
4411 91 unneback
 
4412
    always_ff@(posedge clk_a)
4413
    begin
4414
        if(we_a) begin
4415 100 unneback
            if(be_a[3]) ram[adr_a][0] <= d_a[31:24];
4416
            if(be_a[2]) ram[adr_a][1] <= d_a[23:16];
4417
            if(be_a[1]) ram[adr_a][2] <= d_a[15:8];
4418
            if(be_a[0]) ram[adr_a][3] <= d_a[7:0];
4419 91 unneback
        end
4420
    end
4421
 
4422 92 unneback
    always@(posedge clk_a)
4423
        q_a = ram[adr_a];
4424 91 unneback
 
4425
    always_ff@(posedge clk_b)
4426 92 unneback
    begin
4427
        if(we_b) begin
4428 100 unneback
            if(be_b[3]) ram[adr_b][0] <= d_b[31:24];
4429
            if(be_b[2]) ram[adr_b][1] <= d_b[23:16];
4430
            if(be_b[1]) ram[adr_b][2] <= d_b[15:8];
4431
            if(be_b[0]) ram[adr_b][3] <= d_b[7:0];
4432 92 unneback
        end
4433
    end
4434 91 unneback
 
4435 92 unneback
    always@(posedge clk_b)
4436
        q_b = ram[adr_b];
4437 91 unneback
 
4438 75 unneback
end
4439
endgenerate
4440
 
4441 95 unneback
generate
4442
if (a_data_width==64 & b_data_width==64) begin : dpram_6464
4443
 
4444 98 unneback
    logic [0:7][7:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
4445 95 unneback
 
4446
    initial
4447 100 unneback
        if (memory_init==1)
4448 95 unneback
            $readmemh(memory_file, ram);
4449 100 unneback
 
4450
    integer k;
4451
    initial
4452
        if (memory_init==2)
4453
            for (k = 0; k < mem_size; k = k + 1)
4454
                ram[k] = 0;
4455 95 unneback
 
4456
    always_ff@(posedge clk_a)
4457
    begin
4458
        if(we_a) begin
4459
            if(be_a[7]) ram[adr_a][7] <= d_a[63:56];
4460
            if(be_a[6]) ram[adr_a][6] <= d_a[55:48];
4461
            if(be_a[5]) ram[adr_a][5] <= d_a[47:40];
4462
            if(be_a[4]) ram[adr_a][4] <= d_a[39:32];
4463
            if(be_a[3]) ram[adr_a][3] <= d_a[31:24];
4464
            if(be_a[2]) ram[adr_a][2] <= d_a[23:16];
4465
            if(be_a[1]) ram[adr_a][1] <= d_a[15:8];
4466
            if(be_a[0]) ram[adr_a][0] <= d_a[7:0];
4467
        end
4468
    end
4469
 
4470
    always@(posedge clk_a)
4471
        q_a = ram[adr_a];
4472
 
4473
    always_ff@(posedge clk_b)
4474
    begin
4475
        if(we_b) begin
4476
            if(be_b[7]) ram[adr_b][7] <= d_b[63:56];
4477
            if(be_b[6]) ram[adr_b][6] <= d_b[55:48];
4478
            if(be_b[5]) ram[adr_b][5] <= d_b[47:40];
4479
            if(be_b[4]) ram[adr_b][4] <= d_b[39:32];
4480
            if(be_b[3]) ram[adr_b][3] <= d_b[31:24];
4481
            if(be_b[2]) ram[adr_b][2] <= d_b[23:16];
4482
            if(be_b[1]) ram[adr_b][1] <= d_b[15:8];
4483
            if(be_b[0]) ram[adr_b][0] <= d_b[7:0];
4484
        end
4485
    end
4486
 
4487
    always@(posedge clk_b)
4488
        q_b = ram[adr_b];
4489
 
4490
end
4491
endgenerate
4492
 
4493
generate
4494
if (a_data_width==32 & b_data_width==16) begin : dpram_3216
4495
logic [31:0] temp;
4496
`define MODULE dpram_be_2r2w
4497 128 unneback
`BASE`MODULE # (.a_data_width(32), .b_data_width(32), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file))
4498 95 unneback
`undef MODULE
4499 128 unneback
dpram3232 (
4500 95 unneback
    .d_a(d_a),
4501
    .q_a(q_a),
4502
    .adr_a(adr_a),
4503
    .be_a(be_a),
4504
    .we_a(we_a),
4505
    .clk_a(clk_a),
4506
    .d_b({d_b,d_b}),
4507
    .q_b(temp),
4508 128 unneback
    .adr_b(adr_b[b_addr_width-1:1]),
4509 137 unneback
    .be_b({be_b,be_b} & {{2{!adr_b[0]}},{2{adr_b[0]}}}),
4510 95 unneback
    .we_b(we_b),
4511
    .clk_b(clk_b)
4512
);
4513
 
4514 100 unneback
always @ (adr_b[0] or temp)
4515 95 unneback
    if (adr_b[0])
4516
        q_b = temp[31:16];
4517
    else
4518
        q_b = temp[15:0];
4519
 
4520
end
4521
endgenerate
4522
 
4523
generate
4524
if (a_data_width==32 & b_data_width==64) begin : dpram_3264
4525
logic [63:0] temp;
4526
`define MODULE dpram_be_2r2w
4527 128 unneback
`BASE`MODULE # (.a_data_width(32), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file))
4528 95 unneback
`undef MODULE
4529
dpram6464 (
4530
    .d_a({d_a,d_a}),
4531
    .q_a(temp),
4532
    .adr_a(adr_a[a_addr_width-1:1]),
4533
    .be_a({be_a,be_a} & {{4{adr_a[0]}},{4{!adr_a[0]}}}),
4534
    .we_a(we_a),
4535
    .clk_a(clk_a),
4536
    .d_b(d_b),
4537
    .q_b(q_b),
4538
    .adr_b(adr_b),
4539
    .be_b(be_b),
4540
    .we_b(we_b),
4541
    .clk_b(clk_b)
4542
);
4543
 
4544 100 unneback
always @ (adr_a[0] or temp)
4545 95 unneback
    if (adr_a[0])
4546
        q_a = temp[63:32];
4547
    else
4548
        q_a = temp[31:0];
4549
 
4550
end
4551
endgenerate
4552
 
4553 91 unneback
`else
4554 92 unneback
    // This modules requires SystemVerilog
4555 98 unneback
    // at this point anyway
4556 91 unneback
`endif
4557 75 unneback
endmodule
4558
`endif
4559
 
4560 91 unneback
`ifdef CAM
4561 6 unneback
// Content addresable memory, CAM
4562 91 unneback
`endif
4563 6 unneback
 
4564 40 unneback
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
4565 6 unneback
// FIFO
4566 40 unneback
`define MODULE fifo_1r1w_fill_level_sync
4567
module `BASE`MODULE (
4568
`undef MODULE
4569 25 unneback
    d, wr, fifo_full,
4570
    q, rd, fifo_empty,
4571
    fill_level,
4572
    clk, rst
4573
    );
4574
 
4575
parameter data_width = 18;
4576
parameter addr_width = 4;
4577 6 unneback
 
4578 25 unneback
// write side
4579
input  [data_width-1:0] d;
4580
input                   wr;
4581
output                  fifo_full;
4582
// read side
4583
output [data_width-1:0] q;
4584
input                   rd;
4585
output                  fifo_empty;
4586
// common
4587
output [addr_width:0]   fill_level;
4588
input rst, clk;
4589
 
4590
wire [addr_width:1] wadr, radr;
4591
 
4592 40 unneback
`define MODULE cnt_bin_ce
4593
`BASE`MODULE
4594 25 unneback
    # ( .length(addr_width))
4595
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
4596 40 unneback
`BASE`MODULE
4597 25 unneback
    # (.length(addr_width))
4598
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
4599 40 unneback
`undef MODULE
4600 25 unneback
 
4601 40 unneback
`define MODULE dpram_1r1w
4602
`BASE`MODULE
4603 25 unneback
    # (.data_width(data_width), .addr_width(addr_width))
4604
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
4605 40 unneback
`undef MODULE
4606 25 unneback
 
4607 40 unneback
`define MODULE cnt_bin_ce_rew_q_zq_l1
4608
`BASE`MODULE
4609 27 unneback
    # (.length(addr_width+1), .level1_value(1<<addr_width))
4610 25 unneback
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
4611 40 unneback
`undef MODULE
4612 25 unneback
endmodule
4613 40 unneback
`endif
4614 25 unneback
 
4615 40 unneback
`ifdef FIFO_2R2W_SYNC_SIMPLEX
4616 27 unneback
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
4617
// RAM is supposed to be larger than the two FIFOs
4618
// LFSR counters used adr pointers
4619 40 unneback
`define MODULE fifo_2r2w_sync_simplex
4620
module `BASE`MODULE (
4621
`undef MODULE
4622 27 unneback
    // a side
4623
    a_d, a_wr, a_fifo_full,
4624
    a_q, a_rd, a_fifo_empty,
4625
    a_fill_level,
4626
    // b side
4627
    b_d, b_wr, b_fifo_full,
4628
    b_q, b_rd, b_fifo_empty,
4629
    b_fill_level,
4630
    // common
4631
    clk, rst
4632
    );
4633
parameter data_width = 8;
4634
parameter addr_width = 5;
4635
parameter fifo_full_level = (1<<addr_width)-1;
4636
 
4637
// a side
4638
input  [data_width-1:0] a_d;
4639
input                   a_wr;
4640
output                  a_fifo_full;
4641
output [data_width-1:0] a_q;
4642
input                   a_rd;
4643
output                  a_fifo_empty;
4644
output [addr_width-1:0] a_fill_level;
4645
 
4646
// b side
4647
input  [data_width-1:0] b_d;
4648
input                   b_wr;
4649
output                  b_fifo_full;
4650
output [data_width-1:0] b_q;
4651
input                   b_rd;
4652
output                  b_fifo_empty;
4653
output [addr_width-1:0] b_fill_level;
4654
 
4655
input                   clk;
4656
input                   rst;
4657
 
4658
// adr_gen
4659
wire [addr_width:1] a_wadr, a_radr;
4660
wire [addr_width:1] b_wadr, b_radr;
4661
// dpram
4662
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
4663
 
4664 40 unneback
`define MODULE cnt_lfsr_ce
4665
`BASE`MODULE
4666 27 unneback
    # ( .length(addr_width))
4667
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
4668
 
4669 40 unneback
`BASE`MODULE
4670 27 unneback
    # (.length(addr_width))
4671
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
4672
 
4673 40 unneback
`BASE`MODULE
4674 27 unneback
    # ( .length(addr_width))
4675
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
4676
 
4677 40 unneback
`BASE`MODULE
4678 27 unneback
    # (.length(addr_width))
4679
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
4680 40 unneback
`undef MODULE
4681 27 unneback
 
4682
// mux read or write adr to DPRAM
4683
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
4684
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
4685
 
4686 40 unneback
`define MODULE dpram_2r2w
4687
`BASE`MODULE
4688 27 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
4689
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
4690
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
4691 40 unneback
`undef MODULE
4692
 
4693
`define MODULE cnt_bin_ce_rew_zq_l1
4694
`BASE`MODULE
4695 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
4696 27 unneback
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
4697
 
4698 40 unneback
`BASE`MODULE
4699 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
4700 27 unneback
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
4701 40 unneback
`undef MODULE
4702 27 unneback
 
4703
endmodule
4704 40 unneback
`endif
4705 27 unneback
 
4706 40 unneback
`ifdef FIFO_CMP_ASYNC
4707
`define MODULE fifo_cmp_async
4708
module `BASE`MODULE ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
4709
`undef MODULE
4710 6 unneback
 
4711 11 unneback
   parameter addr_width = 4;
4712
   parameter N = addr_width-1;
4713 6 unneback
 
4714
   parameter Q1 = 2'b00;
4715
   parameter Q2 = 2'b01;
4716
   parameter Q3 = 2'b11;
4717
   parameter Q4 = 2'b10;
4718
 
4719
   parameter going_empty = 1'b0;
4720
   parameter going_full  = 1'b1;
4721
 
4722
   input [N:0]  wptr, rptr;
4723 14 unneback
   output       fifo_empty;
4724 6 unneback
   output       fifo_full;
4725
   input        wclk, rclk, rst;
4726
 
4727
`ifndef GENERATE_DIRECTION_AS_LATCH
4728
   wire direction;
4729
`endif
4730
`ifdef GENERATE_DIRECTION_AS_LATCH
4731
   reg direction;
4732
`endif
4733
   reg  direction_set, direction_clr;
4734
 
4735
   wire async_empty, async_full;
4736
   wire fifo_full2;
4737 14 unneback
   wire fifo_empty2;
4738 6 unneback
 
4739
   // direction_set
4740
   always @ (wptr[N:N-1] or rptr[N:N-1])
4741
     case ({wptr[N:N-1],rptr[N:N-1]})
4742
       {Q1,Q2} : direction_set <= 1'b1;
4743
       {Q2,Q3} : direction_set <= 1'b1;
4744
       {Q3,Q4} : direction_set <= 1'b1;
4745
       {Q4,Q1} : direction_set <= 1'b1;
4746
       default : direction_set <= 1'b0;
4747
     endcase
4748
 
4749
   // direction_clear
4750
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
4751
     if (rst)
4752
       direction_clr <= 1'b1;
4753
     else
4754
       case ({wptr[N:N-1],rptr[N:N-1]})
4755
         {Q2,Q1} : direction_clr <= 1'b1;
4756
         {Q3,Q2} : direction_clr <= 1'b1;
4757
         {Q4,Q3} : direction_clr <= 1'b1;
4758
         {Q1,Q4} : direction_clr <= 1'b1;
4759
         default : direction_clr <= 1'b0;
4760
       endcase
4761
 
4762 40 unneback
`define MODULE dff_sr
4763 6 unneback
`ifndef GENERATE_DIRECTION_AS_LATCH
4764 40 unneback
    `BASE`MODULE dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
4765 6 unneback
`endif
4766
 
4767
`ifdef GENERATE_DIRECTION_AS_LATCH
4768
   always @ (posedge direction_set or posedge direction_clr)
4769
     if (direction_clr)
4770
       direction <= going_empty;
4771
     else
4772
       direction <= going_full;
4773
`endif
4774
 
4775
   assign async_empty = (wptr == rptr) && (direction==going_empty);
4776
   assign async_full  = (wptr == rptr) && (direction==going_full);
4777
 
4778 40 unneback
    `BASE`MODULE dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
4779
    `BASE`MODULE dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
4780
`undef MODULE
4781 6 unneback
 
4782
/*
4783
   always @ (posedge wclk or posedge rst or posedge async_full)
4784
     if (rst)
4785
       {fifo_full, fifo_full2} <= 2'b00;
4786
     else if (async_full)
4787
       {fifo_full, fifo_full2} <= 2'b11;
4788
     else
4789
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
4790
*/
4791 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
4792 6 unneback
     if (async_empty)
4793
       {fifo_empty, fifo_empty2} <= 2'b11;
4794
     else
4795 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
4796 40 unneback
`define MODULE dff
4797
    `BASE`MODULE # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
4798
    `BASE`MODULE # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
4799
`undef MODULE
4800 27 unneback
endmodule // async_compb
4801 40 unneback
`endif
4802 6 unneback
 
4803 40 unneback
`ifdef FIFO_1R1W_ASYNC
4804
`define MODULE fifo_1r1w_async
4805
module `BASE`MODULE (
4806
`undef MODULE
4807 6 unneback
    d, wr, fifo_full, wr_clk, wr_rst,
4808
    q, rd, fifo_empty, rd_clk, rd_rst
4809
    );
4810
 
4811
parameter data_width = 18;
4812
parameter addr_width = 4;
4813
 
4814
// write side
4815
input  [data_width-1:0] d;
4816
input                   wr;
4817
output                  fifo_full;
4818
input                   wr_clk;
4819
input                   wr_rst;
4820
// read side
4821
output [data_width-1:0] q;
4822
input                   rd;
4823
output                  fifo_empty;
4824
input                   rd_clk;
4825
input                   rd_rst;
4826
 
4827
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
4828 23 unneback
 
4829 40 unneback
`define MODULE cnt_gray_ce_bin
4830
`BASE`MODULE
4831 6 unneback
    # ( .length(addr_width))
4832
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
4833
 
4834 40 unneback
`BASE`MODULE
4835 6 unneback
    # (.length(addr_width))
4836 23 unneback
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
4837 40 unneback
`undef MODULE
4838 6 unneback
 
4839 40 unneback
`define MODULE dpram_1r1w
4840
`BASE`MODULE
4841 6 unneback
    # (.data_width(data_width), .addr_width(addr_width))
4842
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
4843 40 unneback
`undef MODULE
4844 6 unneback
 
4845 40 unneback
`define MODULE fifo_cmp_async
4846
`BASE`MODULE
4847 6 unneback
    # (.addr_width(addr_width))
4848
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
4849 40 unneback
`undef MODULE
4850 6 unneback
 
4851
endmodule
4852 40 unneback
`endif
4853 6 unneback
 
4854 40 unneback
`ifdef FIFO_2R2W_ASYNC
4855
`define MODULE fifo_2r2w_async
4856
module `BASE`MODULE (
4857
`undef MODULE
4858 6 unneback
    // a side
4859
    a_d, a_wr, a_fifo_full,
4860
    a_q, a_rd, a_fifo_empty,
4861
    a_clk, a_rst,
4862
    // b side
4863
    b_d, b_wr, b_fifo_full,
4864
    b_q, b_rd, b_fifo_empty,
4865
    b_clk, b_rst
4866
    );
4867
 
4868
parameter data_width = 18;
4869
parameter addr_width = 4;
4870
 
4871
// a side
4872
input  [data_width-1:0] a_d;
4873
input                   a_wr;
4874
output                  a_fifo_full;
4875
output [data_width-1:0] a_q;
4876
input                   a_rd;
4877
output                  a_fifo_empty;
4878
input                   a_clk;
4879
input                   a_rst;
4880
 
4881
// b side
4882
input  [data_width-1:0] b_d;
4883
input                   b_wr;
4884
output                  b_fifo_full;
4885
output [data_width-1:0] b_q;
4886
input                   b_rd;
4887
output                  b_fifo_empty;
4888
input                   b_clk;
4889
input                   b_rst;
4890
 
4891 40 unneback
`define MODULE fifo_1r1w_async
4892
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
4893 6 unneback
vl_fifo_1r1w_async_a (
4894
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
4895
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
4896
    );
4897
 
4898 40 unneback
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
4899 6 unneback
vl_fifo_1r1w_async_b (
4900
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
4901
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
4902
    );
4903 40 unneback
`undef MODULE
4904
 
4905 6 unneback
endmodule
4906 40 unneback
`endif
4907 6 unneback
 
4908 40 unneback
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
4909
`define MODULE fifo_2r2w_async_simplex
4910
module `BASE`MODULE (
4911
`undef MODULE
4912 6 unneback
    // a side
4913
    a_d, a_wr, a_fifo_full,
4914
    a_q, a_rd, a_fifo_empty,
4915
    a_clk, a_rst,
4916
    // b side
4917
    b_d, b_wr, b_fifo_full,
4918
    b_q, b_rd, b_fifo_empty,
4919
    b_clk, b_rst
4920
    );
4921
 
4922
parameter data_width = 18;
4923
parameter addr_width = 4;
4924
 
4925
// a side
4926
input  [data_width-1:0] a_d;
4927
input                   a_wr;
4928
output                  a_fifo_full;
4929
output [data_width-1:0] a_q;
4930
input                   a_rd;
4931
output                  a_fifo_empty;
4932
input                   a_clk;
4933
input                   a_rst;
4934
 
4935
// b side
4936
input  [data_width-1:0] b_d;
4937
input                   b_wr;
4938
output                  b_fifo_full;
4939
output [data_width-1:0] b_q;
4940
input                   b_rd;
4941
output                  b_fifo_empty;
4942
input                   b_clk;
4943
input                   b_rst;
4944
 
4945
// adr_gen
4946
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
4947
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
4948
// dpram
4949
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
4950
 
4951 40 unneback
`define MODULE cnt_gray_ce_bin
4952
`BASE`MODULE
4953 6 unneback
    # ( .length(addr_width))
4954
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
4955
 
4956 40 unneback
`BASE`MODULE
4957 6 unneback
    # (.length(addr_width))
4958
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
4959
 
4960 40 unneback
`BASE`MODULE
4961 6 unneback
    # ( .length(addr_width))
4962
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
4963
 
4964 40 unneback
`BASE`MODULE
4965 6 unneback
    # (.length(addr_width))
4966
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
4967 40 unneback
`undef MODULE
4968 6 unneback
 
4969
// mux read or write adr to DPRAM
4970
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
4971
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
4972
 
4973 40 unneback
`define MODULE dpram_2r2w
4974
`BASE`MODULE
4975 6 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
4976
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
4977
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
4978 40 unneback
`undef MODULE
4979 6 unneback
 
4980 40 unneback
`define MODULE fifo_cmp_async
4981
`BASE`MODULE
4982 6 unneback
    # (.addr_width(addr_width))
4983
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
4984
 
4985 40 unneback
`BASE`MODULE
4986 6 unneback
    # (.addr_width(addr_width))
4987
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
4988 40 unneback
`undef MODULE
4989 6 unneback
 
4990
endmodule
4991 40 unneback
`endif
4992 48 unneback
 
4993
`ifdef REG_FILE
4994
`define MODULE reg_file
4995
module `BASE`MODULE (
4996
`undef MODULE
4997
    a1, a2, a3, wd3, we3, rd1, rd2, clk
4998
);
4999
parameter data_width = 32;
5000
parameter addr_width = 5;
5001
input [addr_width-1:0] a1, a2, a3;
5002
input [data_width-1:0] wd3;
5003
input we3;
5004
output [data_width-1:0] rd1, rd2;
5005
input clk;
5006
 
5007
`ifdef ACTEL
5008
reg [data_width-1:0] wd3_reg;
5009
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
5010
reg we3_reg;
5011 98 unneback
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] `SYN_NO_RW_CHECK;
5012
reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] `SYN_NO_RW_CHECK;
5013 48 unneback
always @ (posedge clk or posedge rst)
5014
if (rst)
5015
    {wd3_reg, a3_reg, we3_reg} <= {(data_width+addr_width+1){1'b0}};
5016
else
5017
    {wd3_reg, a3_reg, we3_reg} <= {wd3,a3,wd3};
5018
 
5019
    always @ (negedge clk)
5020
    if (we3_reg)
5021
        ram1[a3_reg] <= wd3;
5022
    always @ (posedge clk)
5023
        a1_reg <= a1;
5024
    assign rd1 = ram1[a1_reg];
5025
 
5026
    always @ (negedge clk)
5027
    if (we3_reg)
5028
        ram2[a3_reg] <= wd3;
5029
    always @ (posedge clk)
5030
        a2_reg <= a2;
5031
    assign rd2 = ram2[a2_reg];
5032
 
5033
`else
5034
 
5035
`define MODULE dpram_1r1w
5036
`BASE`MODULE
5037
    # ( .data_width(data_width), .addr_width(addr_width))
5038
    ram1 (
5039
        .d_a(wd3),
5040
        .adr_a(a3),
5041
        .we_a(we3),
5042
        .clk_a(clk),
5043
        .q_b(rd1),
5044
        .adr_b(a1),
5045
        .clk_b(clk) );
5046
 
5047
`BASE`MODULE
5048
    # ( .data_width(data_width), .addr_width(addr_width))
5049
    ram2 (
5050
        .d_a(wd3),
5051
        .adr_a(a3),
5052
        .we_a(we3),
5053
        .clk_a(clk),
5054
        .q_b(rd2),
5055
        .adr_b(a2),
5056
        .clk_b(clk) );
5057
`undef MODULE
5058
 
5059
`endif
5060
 
5061
endmodule
5062
`endif
5063 12 unneback
//////////////////////////////////////////////////////////////////////
5064
////                                                              ////
5065
////  Versatile library, wishbone stuff                           ////
5066
////                                                              ////
5067
////  Description                                                 ////
5068
////  Wishbone compliant modules                                  ////
5069
////                                                              ////
5070
////                                                              ////
5071
////  To Do:                                                      ////
5072
////   -                                                          ////
5073
////                                                              ////
5074
////  Author(s):                                                  ////
5075
////      - Michael Unneback, unneback@opencores.org              ////
5076
////        ORSoC AB                                              ////
5077
////                                                              ////
5078
//////////////////////////////////////////////////////////////////////
5079
////                                                              ////
5080
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
5081
////                                                              ////
5082
//// This source file may be used and distributed without         ////
5083
//// restriction provided that this copyright statement is not    ////
5084
//// removed from the file and that any derivative work contains  ////
5085
//// the original copyright notice and the associated disclaimer. ////
5086
////                                                              ////
5087
//// This source file is free software; you can redistribute it   ////
5088
//// and/or modify it under the terms of the GNU Lesser General   ////
5089
//// Public License as published by the Free Software Foundation; ////
5090
//// either version 2.1 of the License, or (at your option) any   ////
5091
//// later version.                                               ////
5092
////                                                              ////
5093
//// This source is distributed in the hope that it will be       ////
5094
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
5095
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
5096
//// PURPOSE.  See the GNU Lesser General Public License for more ////
5097
//// details.                                                     ////
5098
////                                                              ////
5099
//// You should have received a copy of the GNU Lesser General    ////
5100
//// Public License along with this source; if not, download it   ////
5101
//// from http://www.opencores.org/lgpl.shtml                     ////
5102
////                                                              ////
5103
//////////////////////////////////////////////////////////////////////
5104
 
5105 75 unneback
`ifdef WB_ADR_INC
5106
`timescale 1ns/1ns
5107
`define MODULE wb_adr_inc
5108 85 unneback
module `BASE`MODULE ( cyc_i, stb_i, cti_i, bte_i, adr_i, we_i, ack_o, adr_o, clk, rst);
5109 75 unneback
`undef MODULE
5110 83 unneback
parameter adr_width = 10;
5111
parameter max_burst_width = 4;
5112 85 unneback
input cyc_i, stb_i, we_i;
5113 83 unneback
input [2:0] cti_i;
5114
input [1:0] bte_i;
5115
input [adr_width-1:0] adr_i;
5116
output [adr_width-1:0] adr_o;
5117
output ack_o;
5118
input clk, rst;
5119 75 unneback
 
5120 83 unneback
reg [adr_width-1:0] adr;
5121 90 unneback
wire [max_burst_width-1:0] to_adr;
5122 91 unneback
reg [max_burst_width-1:0] last_adr;
5123 92 unneback
reg last_cycle;
5124
localparam idle_or_eoc = 1'b0;
5125
localparam cyc_or_ws   = 1'b1;
5126 90 unneback
 
5127 91 unneback
always @ (posedge clk or posedge rst)
5128
if (rst)
5129
    last_adr <= {max_burst_width{1'b0}};
5130
else
5131
    if (stb_i)
5132 92 unneback
        last_adr <=adr_o[max_burst_width-1:0];
5133 91 unneback
 
5134 83 unneback
generate
5135
if (max_burst_width==0) begin : inst_0
5136 97 unneback
 
5137
        reg ack_o;
5138
        assign adr_o = adr_i;
5139
        always @ (posedge clk or posedge rst)
5140
        if (rst)
5141
            ack_o <= 1'b0;
5142
        else
5143
            ack_o <= cyc_i & stb_i & !ack_o;
5144
 
5145 83 unneback
end else begin
5146
 
5147
    always @ (posedge clk or posedge rst)
5148
    if (rst)
5149 92 unneback
        last_cycle <= idle_or_eoc;
5150 83 unneback
    else
5151 92 unneback
        last_cycle <= (!cyc_i) ? idle_or_eoc : //idle
5152
                      (cyc_i & ack_o & (cti_i==3'b000 | cti_i==3'b111)) ? idle_or_eoc : // eoc
5153
                      (cyc_i & !stb_i) ? cyc_or_ws : //ws
5154
                      cyc_or_ws; // cyc
5155
    assign to_adr = (last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
5156 85 unneback
    assign adr_o[max_burst_width-1:0] = (we_i) ? adr_i[max_burst_width-1:0] :
5157 91 unneback
                                        (!stb_i) ? last_adr :
5158 92 unneback
                                        (last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] :
5159 85 unneback
                                        adr[max_burst_width-1:0];
5160 92 unneback
    assign ack_o = (last_cycle==cyc_or_ws) & stb_i;
5161 97 unneback
 
5162 83 unneback
end
5163
endgenerate
5164
 
5165
generate
5166
if (max_burst_width==2) begin : inst_2
5167
    always @ (posedge clk or posedge rst)
5168
    if (rst)
5169
        adr <= 2'h0;
5170
    else
5171
        if (cyc_i & stb_i)
5172
            adr[1:0] <= to_adr[1:0] + 2'd1;
5173 75 unneback
        else
5174 83 unneback
            adr <= to_adr[1:0];
5175
end
5176
endgenerate
5177
 
5178
generate
5179
if (max_burst_width==3) begin : inst_3
5180
    always @ (posedge clk or posedge rst)
5181
    if (rst)
5182
        adr <= 3'h0;
5183
    else
5184
        if (cyc_i & stb_i)
5185
            case (bte_i)
5186
            2'b01: adr[2:0] <= {to_adr[2],to_adr[1:0] + 2'd1};
5187
            default: adr[3:0] <= to_adr[2:0] + 3'd1;
5188 75 unneback
            endcase
5189 83 unneback
        else
5190
            adr <= to_adr[2:0];
5191
end
5192
endgenerate
5193
 
5194
generate
5195
if (max_burst_width==4) begin : inst_4
5196
    always @ (posedge clk or posedge rst)
5197
    if (rst)
5198
        adr <= 4'h0;
5199
    else
5200 91 unneback
        if (stb_i) // | (!stb_i & last_cycle!=ws)) // for !stb_i restart with adr_i +1, only inc once
5201 83 unneback
            case (bte_i)
5202
            2'b01: adr[3:0] <= {to_adr[3:2],to_adr[1:0] + 2'd1};
5203
            2'b10: adr[3:0] <= {to_adr[3],to_adr[2:0] + 3'd1};
5204
            default: adr[3:0] <= to_adr + 4'd1;
5205
            endcase
5206
        else
5207
            adr <= to_adr[3:0];
5208
end
5209
endgenerate
5210
 
5211
generate
5212
if (adr_width > max_burst_width) begin : pass_through
5213
    assign adr_o[adr_width-1:max_burst_width] = adr_i[adr_width-1:max_burst_width];
5214
end
5215
endgenerate
5216
 
5217
endmodule
5218 75 unneback
`endif
5219
 
5220 105 unneback
`ifdef WB_B4_EOC
5221
`define MODULE wb_b4_eoc
5222
module `BASE`MODULE ( cyc_i, stb_i, stall_o, ack_o, busy, eoc, clk, rst);
5223
`undef MODULE
5224
input cyc_i, stb_i, ack_o;
5225
output busy, eoc;
5226
input clk, rst;
5227
 
5228
`define MODULE cnt_bin_ce_rew_zq_l1
5229
`BASE`MODULE # ( .length(4), level1_value(1))
5230
cnt0 (
5231
    .cke(), .rew(), .zq(), .level1(), .rst(), clk);
5232
`undef MODULE
5233
 
5234
endmodule
5235
`endif
5236
 
5237 40 unneback
`ifdef WB3WB3_BRIDGE
5238 12 unneback
// async wb3 - wb3 bridge
5239
`timescale 1ns/1ns
5240 40 unneback
`define MODULE wb3wb3_bridge
5241
module `BASE`MODULE (
5242
`undef MODULE
5243 12 unneback
        // wishbone slave side
5244
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
5245
        // wishbone master side
5246
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
5247
 
5248 95 unneback
parameter style = "FIFO"; // valid: simple, FIFO
5249
parameter addr_width = 4;
5250
 
5251 12 unneback
input [31:0] wbs_dat_i;
5252
input [31:2] wbs_adr_i;
5253
input [3:0]  wbs_sel_i;
5254
input [1:0]  wbs_bte_i;
5255
input [2:0]  wbs_cti_i;
5256
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
5257
output [31:0] wbs_dat_o;
5258 14 unneback
output wbs_ack_o;
5259 12 unneback
input wbs_clk, wbs_rst;
5260
 
5261
output [31:0] wbm_dat_o;
5262
output reg [31:2] wbm_adr_o;
5263
output [3:0]  wbm_sel_o;
5264
output reg [1:0]  wbm_bte_o;
5265
output reg [2:0]  wbm_cti_o;
5266 14 unneback
output reg wbm_we_o;
5267
output wbm_cyc_o;
5268 12 unneback
output wbm_stb_o;
5269
input [31:0]  wbm_dat_i;
5270
input wbm_ack_i;
5271
input wbm_clk, wbm_rst;
5272
 
5273
// bte
5274
parameter linear       = 2'b00;
5275
parameter wrap4        = 2'b01;
5276
parameter wrap8        = 2'b10;
5277
parameter wrap16       = 2'b11;
5278
// cti
5279
parameter classic      = 3'b000;
5280
parameter incburst     = 3'b010;
5281
parameter endofburst   = 3'b111;
5282
 
5283 95 unneback
localparam wbs_adr  = 1'b0;
5284
localparam wbs_data = 1'b1;
5285 12 unneback
 
5286 95 unneback
localparam wbm_adr0      = 2'b00;
5287
localparam wbm_adr1      = 2'b01;
5288
localparam wbm_data      = 2'b10;
5289
localparam wbm_data_wait = 2'b11;
5290 12 unneback
 
5291
reg [1:0] wbs_bte_reg;
5292
reg wbs;
5293
wire wbs_eoc_alert, wbm_eoc_alert;
5294
reg wbs_eoc, wbm_eoc;
5295
reg [1:0] wbm;
5296
 
5297 14 unneback
wire [1:16] wbs_count, wbm_count;
5298 12 unneback
 
5299
wire [35:0] a_d, a_q, b_d, b_q;
5300
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
5301
reg a_rd_reg;
5302
wire b_rd_adr, b_rd_data;
5303 14 unneback
wire b_rd_data_reg;
5304
wire [35:0] temp;
5305 12 unneback
 
5306
`define WE 5
5307
`define BTE 4:3
5308
`define CTI 2:0
5309
 
5310
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
5311
always @ (posedge wbs_clk or posedge wbs_rst)
5312
if (wbs_rst)
5313
        wbs_eoc <= 1'b0;
5314
else
5315
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
5316 78 unneback
                wbs_eoc <= (wbs_bte_i==linear) | (wbs_cti_i==3'b111);
5317 12 unneback
        else if (wbs_eoc_alert & (a_rd | a_wr))
5318
                wbs_eoc <= 1'b1;
5319
 
5320 40 unneback
`define MODULE cnt_shreg_ce_clear
5321
`BASE`MODULE # ( .length(16))
5322
`undef MODULE
5323 12 unneback
    cnt0 (
5324
        .cke(wbs_ack_o),
5325
        .clear(wbs_eoc),
5326
        .q(wbs_count),
5327
        .rst(wbs_rst),
5328
        .clk(wbs_clk));
5329
 
5330
always @ (posedge wbs_clk or posedge wbs_rst)
5331
if (wbs_rst)
5332
        wbs <= wbs_adr;
5333
else
5334 75 unneback
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & a_fifo_empty)
5335 12 unneback
                wbs <= wbs_data;
5336
        else if (wbs_eoc & wbs_ack_o)
5337
                wbs <= wbs_adr;
5338
 
5339
// wbs FIFO
5340 75 unneback
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,((wbs_cti_i==3'b111) ? {2'b00,3'b000} : {wbs_bte_i,wbs_cti_i})} : {wbs_dat_i,wbs_sel_i};
5341
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & a_fifo_empty :
5342 12 unneback
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
5343
              1'b0;
5344
assign a_rd = !a_fifo_empty;
5345
always @ (posedge wbs_clk or posedge wbs_rst)
5346
if (wbs_rst)
5347
        a_rd_reg <= 1'b0;
5348
else
5349
        a_rd_reg <= a_rd;
5350
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
5351
 
5352
assign wbs_dat_o = a_q[35:4];
5353
 
5354
always @ (posedge wbs_clk or posedge wbs_rst)
5355
if (wbs_rst)
5356 13 unneback
        wbs_bte_reg <= 2'b00;
5357 12 unneback
else
5358 13 unneback
        wbs_bte_reg <= wbs_bte_i;
5359 12 unneback
 
5360
// wbm FIFO
5361
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
5362
always @ (posedge wbm_clk or posedge wbm_rst)
5363
if (wbm_rst)
5364
        wbm_eoc <= 1'b0;
5365
else
5366
        if (wbm==wbm_adr0 & !b_fifo_empty)
5367
                wbm_eoc <= b_q[`BTE] == linear;
5368
        else if (wbm_eoc_alert & wbm_ack_i)
5369
                wbm_eoc <= 1'b1;
5370
 
5371
always @ (posedge wbm_clk or posedge wbm_rst)
5372
if (wbm_rst)
5373
        wbm <= wbm_adr0;
5374
else
5375 33 unneback
/*
5376 12 unneback
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
5377
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
5378
        (wbm==wbm_adr1 & !wbm_we_o) |
5379
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
5380
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
5381 33 unneback
*/
5382
    case (wbm)
5383
    wbm_adr0:
5384
        if (!b_fifo_empty)
5385
            wbm <= wbm_adr1;
5386
    wbm_adr1:
5387
        if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
5388
            wbm <= wbm_data;
5389
    wbm_data:
5390
        if (wbm_ack_i & wbm_eoc)
5391
            wbm <= wbm_adr0;
5392
        else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
5393
            wbm <= wbm_data_wait;
5394
    wbm_data_wait:
5395
        if (!b_fifo_empty)
5396
            wbm <= wbm_data;
5397
    endcase
5398 12 unneback
 
5399
assign b_d = {wbm_dat_i,4'b1111};
5400
assign b_wr = !wbm_we_o & wbm_ack_i;
5401
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
5402
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
5403
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
5404 33 unneback
                   (wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
5405 12 unneback
                   1'b0;
5406
assign b_rd = b_rd_adr | b_rd_data;
5407
 
5408 40 unneback
`define MODULE dff
5409
`BASE`MODULE dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
5410
`undef MODULE
5411
`define MODULE dff_ce
5412
`BASE`MODULE # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
5413
`undef MODULE
5414 12 unneback
 
5415
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
5416
 
5417 40 unneback
`define MODULE cnt_shreg_ce_clear
5418 42 unneback
`BASE`MODULE # ( .length(16))
5419 40 unneback
`undef MODULE
5420 12 unneback
    cnt1 (
5421
        .cke(wbm_ack_i),
5422
        .clear(wbm_eoc),
5423
        .q(wbm_count),
5424
        .rst(wbm_rst),
5425
        .clk(wbm_clk));
5426
 
5427 33 unneback
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
5428
assign wbm_stb_o = (wbm==wbm_data);
5429 12 unneback
 
5430
always @ (posedge wbm_clk or posedge wbm_rst)
5431
if (wbm_rst)
5432
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
5433
else begin
5434
        if (wbm==wbm_adr0 & !b_fifo_empty)
5435
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
5436
        else if (wbm_eoc_alert & wbm_ack_i)
5437
                wbm_cti_o <= endofburst;
5438
end
5439
 
5440
//async_fifo_dw_simplex_top
5441 40 unneback
`define MODULE fifo_2r2w_async_simplex
5442
`BASE`MODULE
5443
`undef MODULE
5444 12 unneback
# ( .data_width(36), .addr_width(addr_width))
5445
fifo (
5446
    // a side
5447
    .a_d(a_d),
5448
    .a_wr(a_wr),
5449
    .a_fifo_full(a_fifo_full),
5450
    .a_q(a_q),
5451
    .a_rd(a_rd),
5452
    .a_fifo_empty(a_fifo_empty),
5453
    .a_clk(wbs_clk),
5454
    .a_rst(wbs_rst),
5455
    // b side
5456
    .b_d(b_d),
5457
    .b_wr(b_wr),
5458
    .b_fifo_full(b_fifo_full),
5459
    .b_q(b_q),
5460
    .b_rd(b_rd),
5461
    .b_fifo_empty(b_fifo_empty),
5462
    .b_clk(wbm_clk),
5463
    .b_rst(wbm_rst)
5464
    );
5465
 
5466
endmodule
5467 40 unneback
`undef WE
5468
`undef BTE
5469
`undef CTI
5470
`endif
5471 17 unneback
 
5472 75 unneback
`ifdef WB3AVALON_BRIDGE
5473
`define MODULE wb3avalon_bridge
5474
module `BASE`MODULE (
5475
`undef MODULE
5476
        // wishbone slave side
5477
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
5478 77 unneback
        // avalon master side
5479 75 unneback
        readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst);
5480
 
5481 85 unneback
parameter linewrapburst = 1'b0;
5482
 
5483 75 unneback
input [31:0] wbs_dat_i;
5484
input [31:2] wbs_adr_i;
5485
input [3:0]  wbs_sel_i;
5486
input [1:0]  wbs_bte_i;
5487
input [2:0]  wbs_cti_i;
5488 83 unneback
input wbs_we_i;
5489
input wbs_cyc_i;
5490
input wbs_stb_i;
5491 75 unneback
output [31:0] wbs_dat_o;
5492
output wbs_ack_o;
5493
input wbs_clk, wbs_rst;
5494
 
5495
input [31:0] readdata;
5496
output [31:0] writedata;
5497
output [31:2] address;
5498
output [3:0]  be;
5499
output write;
5500 81 unneback
output read;
5501 75 unneback
output beginbursttransfer;
5502
output [3:0] burstcount;
5503
input readdatavalid;
5504
input waitrequest;
5505
input clk;
5506
input rst;
5507
 
5508
wire [1:0] wbm_bte_o;
5509
wire [2:0] wbm_cti_o;
5510
wire wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_ack_i;
5511
reg last_cyc;
5512 79 unneback
reg [3:0] counter;
5513 82 unneback
reg read_busy;
5514 75 unneback
 
5515
always @ (posedge clk or posedge rst)
5516
if (rst)
5517
    last_cyc <= 1'b0;
5518
else
5519
    last_cyc <= wbm_cyc_o;
5520
 
5521 79 unneback
always @ (posedge clk or posedge rst)
5522
if (rst)
5523 82 unneback
    read_busy <= 1'b0;
5524 79 unneback
else
5525 82 unneback
    if (read & !waitrequest)
5526
        read_busy <= 1'b1;
5527
    else if (wbm_ack_i & wbm_cti_o!=3'b010)
5528
        read_busy <= 1'b0;
5529
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o & !read_busy;
5530 81 unneback
 
5531 75 unneback
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010;
5532
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 :
5533
                    (wbm_bte_o==2'b10) ? 4'd8 :
5534 78 unneback
                    (wbm_bte_o==2'b11) ? 4'd16:
5535
                    4'd1;
5536 82 unneback
assign wbm_ack_i = (readdatavalid) | (write & !waitrequest);
5537 75 unneback
 
5538 79 unneback
always @ (posedge clk or posedge rst)
5539
if (rst) begin
5540
    counter <= 4'd0;
5541
end else
5542 80 unneback
    if (wbm_we_o) begin
5543
        if (!waitrequest & !last_cyc & wbm_cyc_o) begin
5544 85 unneback
            counter <= burstcount -4'd1;
5545 80 unneback
        end else if (waitrequest & !last_cyc & wbm_cyc_o) begin
5546
            counter <= burstcount;
5547
        end else if (!waitrequest & wbm_stb_o) begin
5548
            counter <= counter - 4'd1;
5549
        end
5550 82 unneback
    end
5551 81 unneback
assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o & counter!=4'd0;
5552 79 unneback
 
5553 75 unneback
`define MODULE wb3wb3_bridge
5554 77 unneback
`BASE`MODULE wbwb3inst (
5555 75 unneback
`undef MODULE
5556
    // wishbone slave side
5557
    .wbs_dat_i(wbs_dat_i),
5558
    .wbs_adr_i(wbs_adr_i),
5559
    .wbs_sel_i(wbs_sel_i),
5560
    .wbs_bte_i(wbs_bte_i),
5561
    .wbs_cti_i(wbs_cti_i),
5562
    .wbs_we_i(wbs_we_i),
5563
    .wbs_cyc_i(wbs_cyc_i),
5564
    .wbs_stb_i(wbs_stb_i),
5565
    .wbs_dat_o(wbs_dat_o),
5566
    .wbs_ack_o(wbs_ack_o),
5567
    .wbs_clk(wbs_clk),
5568
    .wbs_rst(wbs_rst),
5569
    // wishbone master side
5570
    .wbm_dat_o(writedata),
5571 78 unneback
    .wbm_adr_o(address),
5572 75 unneback
    .wbm_sel_o(be),
5573
    .wbm_bte_o(wbm_bte_o),
5574
    .wbm_cti_o(wbm_cti_o),
5575
    .wbm_we_o(wbm_we_o),
5576
    .wbm_cyc_o(wbm_cyc_o),
5577
    .wbm_stb_o(wbm_stb_o),
5578
    .wbm_dat_i(readdata),
5579
    .wbm_ack_i(wbm_ack_i),
5580
    .wbm_clk(clk),
5581
    .wbm_rst(rst));
5582
 
5583
 
5584
endmodule
5585
`endif
5586
 
5587 105 unneback
`ifdef WB_ARBITER
5588
`define MODULE wb_arbiter
5589 42 unneback
module `BASE`MODULE (
5590 40 unneback
`undef MODULE
5591 39 unneback
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
5592 105 unneback
    wbm_dat_i, wbm_stall_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
5593 39 unneback
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
5594 105 unneback
    wbs_dat_o, wbs_stall_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
5595 39 unneback
    wb_clk, wb_rst
5596
);
5597
 
5598
parameter nr_of_ports = 3;
5599
parameter adr_size = 26;
5600
parameter adr_lo   = 2;
5601
parameter dat_size = 32;
5602
parameter sel_size = dat_size/8;
5603
 
5604
localparam aw = (adr_size - adr_lo) * nr_of_ports;
5605
localparam dw = dat_size * nr_of_ports;
5606
localparam sw = sel_size * nr_of_ports;
5607
localparam cw = 3 * nr_of_ports;
5608
localparam bw = 2 * nr_of_ports;
5609
 
5610
input  [dw-1:0] wbm_dat_o;
5611
input  [aw-1:0] wbm_adr_o;
5612
input  [sw-1:0] wbm_sel_o;
5613
input  [cw-1:0] wbm_cti_o;
5614
input  [bw-1:0] wbm_bte_o;
5615
input  [nr_of_ports-1:0] wbm_we_o, wbm_stb_o, wbm_cyc_o;
5616
output [dw-1:0] wbm_dat_i;
5617 105 unneback
output [nr_of_ports-1:0] wbm_stall_o, wbm_ack_i, wbm_err_i, wbm_rty_i;
5618 39 unneback
 
5619
output [dat_size-1:0] wbs_dat_i;
5620
output [adr_size-1:adr_lo] wbs_adr_i;
5621
output [sel_size-1:0] wbs_sel_i;
5622
output [2:0] wbs_cti_i;
5623
output [1:0] wbs_bte_i;
5624
output wbs_we_i, wbs_stb_i, wbs_cyc_i;
5625
input  [dat_size-1:0] wbs_dat_o;
5626 105 unneback
input  wbs_stall_o, wbs_ack_o, wbs_err_o, wbs_rty_o;
5627 39 unneback
 
5628
input wb_clk, wb_rst;
5629
 
5630 44 unneback
reg  [nr_of_ports-1:0] select;
5631 39 unneback
wire [nr_of_ports-1:0] state;
5632
wire [nr_of_ports-1:0] eoc; // end-of-cycle
5633
wire [nr_of_ports-1:0] sel;
5634
wire idle;
5635
 
5636
genvar i;
5637
 
5638
assign idle = !(|state);
5639
 
5640
generate
5641
if (nr_of_ports == 2) begin
5642
 
5643
    wire [2:0] wbm1_cti_o, wbm0_cti_o;
5644
 
5645
    assign {wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5646
 
5647 44 unneback
    //assign select = (idle) ? {wbm_cyc_o[1],!wbm_cyc_o[1] & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5648
 
5649
    always @ (idle or wbm_cyc_o)
5650
    if (idle)
5651
        casex (wbm_cyc_o)
5652
        2'b1x : select = 2'b10;
5653
        2'b01 : select = 2'b01;
5654
        default : select = {nr_of_ports{1'b0}};
5655
        endcase
5656
    else
5657
        select = {nr_of_ports{1'b0}};
5658
 
5659 39 unneback
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5660
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5661
 
5662
end
5663
endgenerate
5664
 
5665
generate
5666
if (nr_of_ports == 3) begin
5667
 
5668
    wire [2:0] wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5669
 
5670
    assign {wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5671
 
5672 44 unneback
    always @ (idle or wbm_cyc_o)
5673
    if (idle)
5674
        casex (wbm_cyc_o)
5675
        3'b1xx : select = 3'b100;
5676
        3'b01x : select = 3'b010;
5677
        3'b001 : select = 3'b001;
5678
        default : select = {nr_of_ports{1'b0}};
5679
        endcase
5680
    else
5681
        select = {nr_of_ports{1'b0}};
5682
 
5683
//    assign select = (idle) ? {wbm_cyc_o[2],!wbm_cyc_o[2] & wbm_cyc_o[1],wbm_cyc_o[2:1]==2'b00 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5684 39 unneback
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5685
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5686
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5687
 
5688
end
5689
endgenerate
5690
 
5691
generate
5692 44 unneback
if (nr_of_ports == 4) begin
5693
 
5694
    wire [2:0] wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5695
 
5696
    assign {wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5697
 
5698
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5699
 
5700
    always @ (idle or wbm_cyc_o)
5701
    if (idle)
5702
        casex (wbm_cyc_o)
5703
        4'b1xxx : select = 4'b1000;
5704
        4'b01xx : select = 4'b0100;
5705
        4'b001x : select = 4'b0010;
5706
        4'b0001 : select = 4'b0001;
5707
        default : select = {nr_of_ports{1'b0}};
5708
        endcase
5709
    else
5710
        select = {nr_of_ports{1'b0}};
5711
 
5712
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5713
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5714
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5715
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5716
 
5717
end
5718
endgenerate
5719
 
5720
generate
5721
if (nr_of_ports == 5) begin
5722
 
5723
    wire [2:0] wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5724
 
5725
    assign {wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5726
 
5727
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5728
 
5729
    always @ (idle or wbm_cyc_o)
5730
    if (idle)
5731
        casex (wbm_cyc_o)
5732
        5'b1xxxx : select = 5'b10000;
5733
        5'b01xxx : select = 5'b01000;
5734
        5'b001xx : select = 5'b00100;
5735
        5'b0001x : select = 5'b00010;
5736
        5'b00001 : select = 5'b00001;
5737
        default : select = {nr_of_ports{1'b0}};
5738
        endcase
5739
    else
5740
        select = {nr_of_ports{1'b0}};
5741
 
5742
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
5743
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5744
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5745
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5746
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5747
 
5748
end
5749
endgenerate
5750
 
5751
generate
5752 67 unneback
if (nr_of_ports == 6) begin
5753
 
5754
    wire [2:0] wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5755
 
5756
    assign {wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5757
 
5758
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5759
 
5760
    always @ (idle or wbm_cyc_o)
5761
    if (idle)
5762
        casex (wbm_cyc_o)
5763
        6'b1xxxxx : select = 6'b100000;
5764
        6'b01xxxx : select = 6'b010000;
5765
        6'b001xxx : select = 6'b001000;
5766
        6'b0001xx : select = 6'b000100;
5767
        6'b00001x : select = 6'b000010;
5768
        6'b000001 : select = 6'b000001;
5769
        default : select = {nr_of_ports{1'b0}};
5770
        endcase
5771
    else
5772
        select = {nr_of_ports{1'b0}};
5773
 
5774
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
5775
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
5776
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5777
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5778
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5779
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5780
 
5781
end
5782
endgenerate
5783
 
5784
generate
5785
if (nr_of_ports == 7) begin
5786
 
5787
    wire [2:0] wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5788
 
5789
    assign {wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5790
 
5791
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5792
 
5793
    always @ (idle or wbm_cyc_o)
5794
    if (idle)
5795
        casex (wbm_cyc_o)
5796
        7'b1xxxxxx : select = 7'b1000000;
5797
        7'b01xxxxx : select = 7'b0100000;
5798
        7'b001xxxx : select = 7'b0010000;
5799
        7'b0001xxx : select = 7'b0001000;
5800
        7'b00001xx : select = 7'b0000100;
5801
        7'b000001x : select = 7'b0000010;
5802
        7'b0000001 : select = 7'b0000001;
5803
        default : select = {nr_of_ports{1'b0}};
5804
        endcase
5805
    else
5806
        select = {nr_of_ports{1'b0}};
5807
 
5808
    assign eoc[6] = (wbm_ack_i[6] & (wbm6_cti_o == 3'b000 | wbm6_cti_o == 3'b111)) | !wbm_cyc_o[6];
5809
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
5810
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
5811
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5812
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5813
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5814
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5815
 
5816
end
5817
endgenerate
5818
 
5819
generate
5820
if (nr_of_ports == 8) begin
5821
 
5822
    wire [2:0] wbm7_cti_o, wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5823
 
5824
    assign {wbm7_cti_o, wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5825
 
5826
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5827
 
5828
    always @ (idle or wbm_cyc_o)
5829
    if (idle)
5830
        casex (wbm_cyc_o)
5831
        8'b1xxxxxxx : select = 8'b10000000;
5832
        8'b01xxxxxx : select = 8'b01000000;
5833
        8'b001xxxxx : select = 8'b00100000;
5834
        8'b0001xxxx : select = 8'b00010000;
5835
        8'b00001xxx : select = 8'b00001000;
5836
        8'b000001xx : select = 8'b00000100;
5837
        8'b0000001x : select = 8'b00000010;
5838
        8'b00000001 : select = 8'b00000001;
5839
        default : select = {nr_of_ports{1'b0}};
5840
        endcase
5841
    else
5842
        select = {nr_of_ports{1'b0}};
5843
 
5844
    assign eoc[7] = (wbm_ack_i[7] & (wbm7_cti_o == 3'b000 | wbm7_cti_o == 3'b111)) | !wbm_cyc_o[7];
5845
    assign eoc[6] = (wbm_ack_i[6] & (wbm6_cti_o == 3'b000 | wbm6_cti_o == 3'b111)) | !wbm_cyc_o[6];
5846
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
5847
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
5848
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5849
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5850
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5851
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5852
 
5853
end
5854
endgenerate
5855
 
5856
generate
5857 63 unneback
for (i=0;i<nr_of_ports;i=i+1) begin : spr0
5858 42 unneback
`define MODULE spr
5859
    `BASE`MODULE sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));
5860
`undef MODULE
5861 39 unneback
end
5862
endgenerate
5863
 
5864
    assign sel = select | state;
5865
 
5866 40 unneback
`define MODULE mux_andor
5867
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i));
5868
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(adr_size-adr_lo)) mux1 ( .a(wbm_adr_o), .sel(sel), .dout(wbs_adr_i));
5869
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(sel_size)) mux2 ( .a(wbm_sel_o), .sel(sel), .dout(wbs_sel_i));
5870
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(3)) mux3 ( .a(wbm_cti_o), .sel(sel), .dout(wbs_cti_i));
5871
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(2)) mux4 ( .a(wbm_bte_o), .sel(sel), .dout(wbs_bte_i));
5872
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux5 ( .a(wbm_we_o), .sel(sel), .dout(wbs_we_i));
5873
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux6 ( .a(wbm_stb_o), .sel(sel), .dout(wbs_stb_i));
5874
`undef MODULE
5875 39 unneback
    assign wbs_cyc_i = |sel;
5876
 
5877
    assign wbm_dat_i = {nr_of_ports{wbs_dat_o}};
5878
    assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
5879
    assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
5880
    assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
5881
 
5882
endmodule
5883 40 unneback
`endif
5884 39 unneback
 
5885 101 unneback
`ifdef WB_RAM
5886 49 unneback
// WB RAM with byte enable
5887 101 unneback
`define MODULE wb_ram
5888 59 unneback
module `BASE`MODULE (
5889
`undef MODULE
5890 69 unneback
    wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
5891 101 unneback
    wbs_dat_o, wbs_ack_o, wbs_stall_o, wb_clk, wb_rst);
5892 59 unneback
 
5893 101 unneback
parameter adr_width = 16;
5894
parameter mem_size = 1<<adr_width;
5895
parameter dat_width = 32;
5896
parameter max_burst_width = 4; // only used for B3
5897
parameter mode = "B3"; // valid options: B3, B4
5898 60 unneback
parameter memory_init = 1;
5899
parameter memory_file = "vl_ram.vmem";
5900 59 unneback
 
5901 101 unneback
input [dat_width-1:0] wbs_dat_i;
5902
input [adr_width-1:0] wbs_adr_i;
5903
input [2:0] wbs_cti_i;
5904
input [1:0] wbs_bte_i;
5905
input [dat_width/8-1:0] wbs_sel_i;
5906 70 unneback
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
5907 101 unneback
output [dat_width-1:0] wbs_dat_o;
5908 70 unneback
output wbs_ack_o;
5909 101 unneback
output wbs_stall_o;
5910 71 unneback
input wb_clk, wb_rst;
5911 59 unneback
 
5912 101 unneback
wire [adr_width-1:0] adr;
5913
wire we;
5914 59 unneback
 
5915 101 unneback
generate
5916
if (mode=="B3") begin : B3_inst
5917 83 unneback
`define MODULE wb_adr_inc
5918 101 unneback
`BASE`MODULE # ( .adr_width(adr_width), .max_burst_width(max_burst_width)) adr_inc0 (
5919 83 unneback
    .cyc_i(wbs_cyc_i),
5920
    .stb_i(wbs_stb_i),
5921
    .cti_i(wbs_cti_i),
5922
    .bte_i(wbs_bte_i),
5923
    .adr_i(wbs_adr_i),
5924 85 unneback
    .we_i(wbs_we_i),
5925 83 unneback
    .ack_o(wbs_ack_o),
5926
    .adr_o(adr),
5927
    .clk(wb_clk),
5928
    .rst(wb_rst));
5929
`undef MODULE
5930 101 unneback
assign we = wbs_we_i & wbs_ack_o;
5931
end else if (mode=="B4") begin : B4_inst
5932
reg wbs_ack_o_reg;
5933
always @ (posedge wb_clk or posedge wb_rst)
5934
    if (wb_rst)
5935
        wbs_ack_o_reg <= 1'b0;
5936
    else
5937
        wbs_ack_o_reg <= wbs_stb_i & wbs_cyc_i;
5938
assign wbs_ack_o = wbs_ack_o_reg;
5939
assign wbs_stall_o = 1'b0;
5940
assign adr = wbs_adr_i;
5941
assign we = wbs_we_i & wbs_cyc_i & wbs_stb_i;
5942
end
5943
endgenerate
5944 60 unneback
 
5945 100 unneback
`define MODULE ram_be
5946
`BASE`MODULE # (
5947
    .data_width(dat_width),
5948
    .addr_width(adr_width),
5949
    .mem_size(mem_size),
5950
    .memory_init(memory_init),
5951
    .memory_file(memory_file))
5952
ram0(
5953
`undef MODULE
5954 101 unneback
    .d(wbs_dat_i),
5955
    .adr(adr),
5956
    .be(wbs_sel_i),
5957
    .we(we),
5958
    .q(wbs_dat_o),
5959 100 unneback
    .clk(wb_clk)
5960
);
5961 49 unneback
 
5962
endmodule
5963
`endif
5964
 
5965 103 unneback
`ifdef WB_SHADOW_RAM
5966
// A wishbone compliant RAM module that can be placed in front of other memory controllers
5967
`define MODULE wb_shadow_ram
5968
module `BASE`MODULE (
5969
`undef MODULE
5970
    wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
5971
    wbs_dat_o, wbs_ack_o, wbs_stall_o,
5972
    wbm_dat_o, wbm_adr_o, wbm_cti_o, wbm_bte_o, wbm_sel_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
5973
    wbm_dat_i, wbm_ack_i, wbm_stall_i,
5974
    wb_clk, wb_rst);
5975
 
5976
parameter dat_width = 32;
5977
parameter mode = "B4";
5978
parameter max_burst_width = 4; // only used for B3
5979
 
5980
parameter shadow_mem_adr_width = 10;
5981
parameter shadow_mem_size = 1024;
5982
parameter shadow_mem_init = 2;
5983
parameter shadow_mem_file = "vl_ram.v";
5984
 
5985
parameter main_mem_adr_width = 24;
5986
 
5987
input [dat_width-1:0] wbs_dat_i;
5988
input [main_mem_adr_width-1:0] wbs_adr_i;
5989
input [2:0] wbs_cti_i;
5990
input [1:0] wbs_bte_i;
5991
input [dat_width/8-1:0] wbs_sel_i;
5992
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
5993
output [dat_width-1:0] wbs_dat_o;
5994
output wbs_ack_o;
5995
output wbs_stall_o;
5996
 
5997
output [dat_width-1:0] wbm_dat_o;
5998
output [main_mem_adr_width-1:0] wbm_adr_o;
5999
output [2:0] wbm_cti_o;
6000
output [1:0] wbm_bte_o;
6001
output [dat_width/8-1:0] wbm_sel_o;
6002
output wbm_we_o, wbm_stb_o, wbm_cyc_o;
6003
input [dat_width-1:0] wbm_dat_i;
6004
input wbm_ack_i, wbm_stall_i;
6005
 
6006
input wb_clk, wb_rst;
6007
 
6008
generate
6009
if (shadow_mem_size>0) begin : shadow_ram_inst
6010
 
6011
wire cyc;
6012
wire [dat_width-1:0] dat;
6013
wire stall, ack;
6014
 
6015
assign cyc = wbs_cyc_i & (wbs_adr_i<=shadow_mem_size);
6016
`define MODULE wb_ram
6017
`BASE`MODULE # (
6018
    .dat_width(dat_width),
6019
    .adr_width(shadow_mem_adr_width),
6020
    .mem_size(shadow_mem_size),
6021
    .memory_init(shadow_mem_init),
6022 117 unneback
    .memory_file(shadow_mem_file),
6023 103 unneback
    .mode(mode))
6024
shadow_mem0 (
6025
    .wbs_dat_i(wbs_dat_i),
6026
    .wbs_adr_i(wbs_adr_i[shadow_mem_adr_width-1:0]),
6027
    .wbs_sel_i(wbs_sel_i),
6028
    .wbs_we_i (wbs_we_i),
6029
    .wbs_bte_i(wbs_bte_i),
6030
    .wbs_cti_i(wbs_cti_i),
6031
    .wbs_stb_i(wbs_stb_i),
6032
    .wbs_cyc_i(cyc),
6033
    .wbs_dat_o(dat),
6034
    .wbs_stall_o(stall),
6035
    .wbs_ack_o(ack),
6036
    .wb_clk(wb_clk),
6037
    .wb_rst(wb_rst));
6038
`undef MODULE
6039
 
6040
assign {wbm_dat_o, wbm_adr_o, wbm_cti_o, wbm_bte_o, wbm_sel_o, wbm_we_o, wbm_stb_o} =
6041
       {wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i};
6042
assign wbm_cyc_o = wbs_cyc_i & (wbs_adr_i>shadow_mem_size);
6043
 
6044
assign wbs_dat_o = (dat & {dat_width{cyc}}) | (wbm_dat_i & {dat_width{wbm_cyc_o}});
6045
assign wbs_ack_o = (ack & cyc) | (wbm_ack_i & wbm_cyc_o);
6046
assign wbs_stall_o = (stall & cyc) | (wbm_stall_i & wbm_cyc_o);
6047
 
6048
end else begin : no_shadow_ram_inst
6049
 
6050
assign {wbm_dat_o, wbm_adr_o, wbm_cti_o, wbm_bte_o, wbm_sel_o, wbm_we_o, wbm_stb_o, wbm_cyc_o} =
6051
       {wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i};
6052
assign {wbs_dat_o, wbs_ack_o, wbs_stall_o} = {wbm_dat_i, wbm_ack_i, wbm_stall_i};
6053
 
6054
end
6055
endgenerate
6056
 
6057
endmodule
6058
`endif
6059
 
6060 48 unneback
`ifdef WB_B4_ROM
6061
// WB ROM
6062
`define MODULE wb_b4_rom
6063
module `BASE`MODULE (
6064
`undef MODULE
6065
    wb_adr_i, wb_stb_i, wb_cyc_i,
6066
    wb_dat_o, stall_o, wb_ack_o, wb_clk, wb_rst);
6067
 
6068
    parameter dat_width = 32;
6069
    parameter dat_default = 32'h15000000;
6070
    parameter adr_width = 32;
6071
 
6072
/*
6073
`ifndef ROM
6074
`define ROM "rom.v"
6075
`endif
6076
*/
6077
    input [adr_width-1:2]   wb_adr_i;
6078
    input                   wb_stb_i;
6079
    input                   wb_cyc_i;
6080
    output [dat_width-1:0]  wb_dat_o;
6081
    reg [dat_width-1:0]     wb_dat_o;
6082
    output                  wb_ack_o;
6083
    reg                     wb_ack_o;
6084
    output                  stall_o;
6085
    input                   wb_clk;
6086
    input                   wb_rst;
6087
 
6088
always @ (posedge wb_clk or posedge wb_rst)
6089
    if (wb_rst)
6090
        wb_dat_o <= {dat_width{1'b0}};
6091
    else
6092
         case (wb_adr_i[adr_width-1:2])
6093
`ifdef ROM
6094
`include `ROM
6095
`endif
6096
           default:
6097
             wb_dat_o <= dat_default;
6098
 
6099
         endcase // case (wb_adr_i)
6100
 
6101
 
6102
always @ (posedge wb_clk or posedge wb_rst)
6103
    if (wb_rst)
6104
        wb_ack_o <= 1'b0;
6105
    else
6106
        wb_ack_o <= wb_stb_i & wb_cyc_i;
6107
 
6108
assign stall_o = 1'b0;
6109
 
6110
endmodule
6111
`endif
6112
 
6113
 
6114 40 unneback
`ifdef WB_BOOT_ROM
6115 17 unneback
// WB ROM
6116 40 unneback
`define MODULE wb_boot_rom
6117
module `BASE`MODULE (
6118
`undef MODULE
6119 17 unneback
    wb_adr_i, wb_stb_i, wb_cyc_i,
6120 18 unneback
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
6121 17 unneback
 
6122 18 unneback
    parameter adr_hi = 31;
6123
    parameter adr_lo = 28;
6124
    parameter adr_sel = 4'hf;
6125
    parameter addr_width = 5;
6126 33 unneback
/*
6127 17 unneback
`ifndef BOOT_ROM
6128
`define BOOT_ROM "boot_rom.v"
6129
`endif
6130 33 unneback
*/
6131 18 unneback
    input [adr_hi:2]    wb_adr_i;
6132
    input               wb_stb_i;
6133
    input               wb_cyc_i;
6134
    output [31:0]        wb_dat_o;
6135
    output              wb_ack_o;
6136
    output              hit_o;
6137
    input               wb_clk;
6138
    input               wb_rst;
6139
 
6140
    wire hit;
6141
    reg [31:0] wb_dat;
6142
    reg wb_ack;
6143
 
6144
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
6145 17 unneback
 
6146
always @ (posedge wb_clk or posedge wb_rst)
6147
    if (wb_rst)
6148 18 unneback
        wb_dat <= 32'h15000000;
6149 17 unneback
    else
6150 18 unneback
         case (wb_adr_i[addr_width-1:2])
6151 33 unneback
`ifdef BOOT_ROM
6152 17 unneback
`include `BOOT_ROM
6153 33 unneback
`endif
6154 17 unneback
           /*
6155
            // Zero r0 and jump to 0x00000100
6156 18 unneback
 
6157
            1 : wb_dat <= 32'hA8200000;
6158
            2 : wb_dat <= 32'hA8C00100;
6159
            3 : wb_dat <= 32'h44003000;
6160
            4 : wb_dat <= 32'h15000000;
6161 17 unneback
            */
6162
           default:
6163 18 unneback
             wb_dat <= 32'h00000000;
6164 17 unneback
 
6165
         endcase // case (wb_adr_i)
6166
 
6167
 
6168
always @ (posedge wb_clk or posedge wb_rst)
6169
    if (wb_rst)
6170 18 unneback
        wb_ack <= 1'b0;
6171 17 unneback
    else
6172 18 unneback
        wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
6173 17 unneback
 
6174 18 unneback
assign hit_o = hit;
6175
assign wb_dat_o = wb_dat & {32{wb_ack}};
6176
assign wb_ack_o = wb_ack;
6177
 
6178 17 unneback
endmodule
6179 40 unneback
`endif
6180 32 unneback
 
6181 106 unneback
`ifdef WB_DPRAM
6182
`define MODULE wb_dpram
6183 40 unneback
module `BASE`MODULE (
6184
`undef MODULE
6185 32 unneback
        // wishbone slave side a
6186 106 unneback
        wbsa_dat_i, wbsa_adr_i, wbsa_sel_i, wbsa_cti_i, wbsa_bte_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o, wbsa_stall_o,
6187 32 unneback
        wbsa_clk, wbsa_rst,
6188 92 unneback
        // wishbone slave side b
6189 106 unneback
        wbsb_dat_i, wbsb_adr_i, wbsb_sel_i, wbsb_cti_i, wbsb_bte_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o, wbsb_stall_o,
6190 32 unneback
        wbsb_clk, wbsb_rst);
6191
 
6192 92 unneback
parameter data_width_a = 32;
6193
parameter data_width_b = data_width_a;
6194
parameter addr_width_a = 8;
6195
localparam addr_width_b = data_width_a * addr_width_a / data_width_b;
6196 101 unneback
parameter mem_size = (addr_width_a>addr_width_b) ? (1<<addr_width_a) : (1<<addr_width_b);
6197 92 unneback
parameter max_burst_width_a = 4;
6198
parameter max_burst_width_b = max_burst_width_a;
6199 101 unneback
parameter mode = "B3";
6200 109 unneback
parameter memory_init = 0;
6201
parameter memory_file = "vl_ram.v";
6202 92 unneback
input [data_width_a-1:0] wbsa_dat_i;
6203
input [addr_width_a-1:0] wbsa_adr_i;
6204
input [data_width_a/8-1:0] wbsa_sel_i;
6205
input [2:0] wbsa_cti_i;
6206
input [1:0] wbsa_bte_i;
6207 32 unneback
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
6208 92 unneback
output [data_width_a-1:0] wbsa_dat_o;
6209 109 unneback
output wbsa_ack_o;
6210 106 unneback
output wbsa_stall_o;
6211 32 unneback
input wbsa_clk, wbsa_rst;
6212
 
6213 92 unneback
input [data_width_b-1:0] wbsb_dat_i;
6214
input [addr_width_b-1:0] wbsb_adr_i;
6215
input [data_width_b/8-1:0] wbsb_sel_i;
6216
input [2:0] wbsb_cti_i;
6217
input [1:0] wbsb_bte_i;
6218 32 unneback
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
6219 92 unneback
output [data_width_b-1:0] wbsb_dat_o;
6220 109 unneback
output wbsb_ack_o;
6221 106 unneback
output wbsb_stall_o;
6222 32 unneback
input wbsb_clk, wbsb_rst;
6223
 
6224 92 unneback
wire [addr_width_a-1:0] adr_a;
6225
wire [addr_width_b-1:0] adr_b;
6226 101 unneback
wire we_a, we_b;
6227
generate
6228
if (mode=="B3") begin : b3_inst
6229 92 unneback
`define MODULE wb_adr_inc
6230
`BASE`MODULE # ( .adr_width(addr_width_a), .max_burst_width(max_burst_width_a)) adr_inc0 (
6231
    .cyc_i(wbsa_cyc_i),
6232
    .stb_i(wbsa_stb_i),
6233
    .cti_i(wbsa_cti_i),
6234
    .bte_i(wbsa_bte_i),
6235
    .adr_i(wbsa_adr_i),
6236
    .we_i(wbsa_we_i),
6237
    .ack_o(wbsa_ack_o),
6238
    .adr_o(adr_a),
6239
    .clk(wbsa_clk),
6240
    .rst(wbsa_rst));
6241 101 unneback
assign we_a = wbsa_we_i & wbsa_ack_o;
6242 92 unneback
`BASE`MODULE # ( .adr_width(addr_width_b), .max_burst_width(max_burst_width_b)) adr_inc1 (
6243
    .cyc_i(wbsb_cyc_i),
6244
    .stb_i(wbsb_stb_i),
6245
    .cti_i(wbsb_cti_i),
6246
    .bte_i(wbsb_bte_i),
6247
    .adr_i(wbsb_adr_i),
6248
    .we_i(wbsb_we_i),
6249
    .ack_o(wbsb_ack_o),
6250
    .adr_o(adr_b),
6251
    .clk(wbsb_clk),
6252
    .rst(wbsb_rst));
6253 40 unneback
`undef MODULE
6254 101 unneback
assign we_b = wbsb_we_i & wbsb_ack_o;
6255
end else if (mode=="B4") begin : b4_inst
6256 109 unneback
`define MODULE dff
6257
`BASE`MODULE dffacka ( .d(wbsa_stb_i & wbsa_cyc_i), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
6258 101 unneback
assign wbsa_stall_o = 1'b0;
6259
assign we_a = wbsa_we_i & wbsa_cyc_i & wbsa_stb_i;
6260 109 unneback
`BASE`MODULE dffackb ( .d(wbsb_stb_i & wbsb_cyc_i), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
6261
`undef MODULE
6262 101 unneback
assign wbsb_stall_o = 1'b0;
6263
assign we_b = wbsb_we_i & wbsb_cyc_i & wbsb_stb_i;
6264
end
6265
endgenerate
6266 92 unneback
 
6267
`define MODULE dpram_be_2r2w
6268 109 unneback
`BASE`MODULE # ( .a_data_width(data_width_a), .a_addr_width(addr_width_a), .mem_size(mem_size),
6269 110 unneback
                 .b_data_width(data_width_b),
6270 109 unneback
                 .memory_init(memory_init), .memory_file(memory_file))
6271 92 unneback
`undef MODULE
6272
ram_i (
6273 32 unneback
    .d_a(wbsa_dat_i),
6274 92 unneback
    .q_a(wbsa_dat_o),
6275
    .adr_a(adr_a),
6276
    .be_a(wbsa_sel_i),
6277 101 unneback
    .we_a(we_a),
6278 32 unneback
    .clk_a(wbsa_clk),
6279
    .d_b(wbsb_dat_i),
6280 92 unneback
    .q_b(wbsb_dat_o),
6281
    .adr_b(adr_b),
6282
    .be_b(wbsb_sel_i),
6283 101 unneback
    .we_b(we_b),
6284 32 unneback
    .clk_b(wbsb_clk) );
6285
 
6286
endmodule
6287 40 unneback
`endif
6288 94 unneback
 
6289 101 unneback
`ifdef WB_CACHE
6290
`define MODULE wb_cache
6291 97 unneback
module `BASE`MODULE (
6292 103 unneback
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i, wbs_dat_o, wbs_ack_o, wbs_stall_o, wbs_clk, wbs_rst,
6293 98 unneback
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o, wbm_dat_i, wbm_ack_i, wbm_stall_i, wbm_clk, wbm_rst
6294 97 unneback
);
6295
`undef MODULE
6296
 
6297
parameter dw_s = 32;
6298
parameter aw_s = 24;
6299
parameter dw_m = dw_s;
6300 124 unneback
//localparam aw_m = dw_s * aw_s / dw_m;
6301
localparam aw_m =
6302 126 unneback
        (dw_s==dw_m) ? aw_s :
6303
        (dw_s==dw_m*2) ? aw_s+1 :
6304
        (dw_s==dw_m*4) ? aw_s+2 :
6305
        (dw_s==dw_m*8) ? aw_s+3 :
6306
        (dw_s==dw_m*16) ? aw_s+4 :
6307
        (dw_s==dw_m*32) ? aw_s+5 :
6308
        (dw_s==dw_m/2) ? aw_s-1 :
6309 127 unneback
        (dw_s==dw_m/4) ? aw_s-2 :
6310 126 unneback
        (dw_s==dw_m/8) ? aw_s-3 :
6311
        (dw_s==dw_m/16) ? aw_s-4 :
6312
        (dw_s==dw_m/32) ? aw_s-5 : 0;
6313 124 unneback
 
6314 100 unneback
parameter wbs_max_burst_width = 4;
6315 103 unneback
parameter wbs_mode = "B3";
6316 97 unneback
 
6317
parameter async = 1; // wbs_clk != wbm_clk
6318
 
6319
parameter nr_of_ways = 1;
6320
parameter aw_offset = 4; // 4 => 16 words per cache line
6321
parameter aw_slot = 10;
6322 100 unneback
 
6323
parameter valid_mem = 0;
6324
parameter debug = 0;
6325
 
6326
localparam aw_b_offset = aw_offset * dw_s / dw_m;
6327 98 unneback
localparam aw_tag = aw_s - aw_slot - aw_offset;
6328 97 unneback
parameter wbm_burst_size = 4; // valid options 4,8,16
6329 98 unneback
localparam bte = (wbm_burst_size==4) ? 2'b01 : (wbm_burst_size==8) ? 2'b10 : 2'b11;
6330 97 unneback
`define SIZE2WIDTH wbm_burst_size
6331
localparam wbm_burst_width `SIZE2WIDTH_EXPR
6332
`undef SIZE2WIDTH
6333
localparam nr_of_wbm_burst = ((1<<aw_offset)/wbm_burst_size) * dw_s / dw_m;
6334
`define SIZE2WIDTH nr_of_wbm_burst
6335
localparam nr_of_wbm_burst_width `SIZE2WIDTH_EXPR
6336
`undef SIZE2WIDTH
6337 100 unneback
 
6338 97 unneback
input [dw_s-1:0] wbs_dat_i;
6339
input [aw_s-1:0] wbs_adr_i; // dont include a1,a0
6340 98 unneback
input [dw_s/8-1:0] wbs_sel_i;
6341 97 unneback
input [2:0] wbs_cti_i;
6342
input [1:0] wbs_bte_i;
6343 98 unneback
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
6344 97 unneback
output [dw_s-1:0] wbs_dat_o;
6345
output wbs_ack_o;
6346 103 unneback
output wbs_stall_o;
6347 97 unneback
input wbs_clk, wbs_rst;
6348
 
6349
output [dw_m-1:0] wbm_dat_o;
6350
output [aw_m-1:0] wbm_adr_o;
6351
output [dw_m/8-1:0] wbm_sel_o;
6352
output [2:0] wbm_cti_o;
6353
output [1:0] wbm_bte_o;
6354 98 unneback
output wbm_stb_o, wbm_cyc_o, wbm_we_o;
6355 97 unneback
input [dw_m-1:0] wbm_dat_i;
6356
input wbm_ack_i;
6357
input wbm_stall_i;
6358
input wbm_clk, wbm_rst;
6359
 
6360 100 unneback
wire valid, dirty, hit;
6361 97 unneback
wire [aw_tag-1:0] tag;
6362
wire tag_mem_we;
6363
wire [aw_tag-1:0] wbs_adr_tag;
6364
wire [aw_slot-1:0] wbs_adr_slot;
6365 98 unneback
wire [aw_offset-1:0] wbs_adr_word;
6366
wire [aw_s-1:0] wbs_adr;
6367 97 unneback
 
6368
reg [1:0] state;
6369
localparam idle = 2'h0;
6370
localparam rdwr = 2'h1;
6371
localparam push = 2'h2;
6372
localparam pull = 2'h3;
6373
wire eoc;
6374 103 unneback
wire we;
6375 97 unneback
 
6376
// cdc
6377
wire done, mem_alert, mem_done;
6378
 
6379 98 unneback
// wbm side
6380
reg [aw_m-1:0] wbm_radr;
6381
reg [aw_m-1:0] wbm_wadr;
6382 137 unneback
//wire [aw_slot-1:0] wbm_adr;
6383
wire [aw_m-1:0] wbm_adr;
6384 98 unneback
wire wbm_radr_cke, wbm_wadr_cke;
6385
 
6386 100 unneback
reg [2:0] phase;
6387
// phase = {we,stb,cyc}
6388
localparam wbm_wait     = 3'b000;
6389
localparam wbm_wr       = 3'b111;
6390
localparam wbm_wr_drain = 3'b101;
6391
localparam wbm_rd       = 3'b011;
6392
localparam wbm_rd_drain = 3'b001;
6393 98 unneback
 
6394 97 unneback
assign {wbs_adr_tag, wbs_adr_slot, wbs_adr_word} = wbs_adr_i;
6395
 
6396 100 unneback
generate
6397
if (valid_mem==0) begin : no_valid_mem
6398
assign valid = 1'b1;
6399
end else begin : valid_mem_inst
6400
`define MODULE dpram_1r1w
6401 97 unneback
`BASE`MODULE
6402 100 unneback
    # ( .data_width(1), .addr_width(aw_slot), .memory_init(2), .debug(debug))
6403
    valid_mem ( .d_a(1'b1), .adr_a(wbs_adr_slot), .we_a(mem_done), .clk_a(wbm_clk),
6404
                .q_b(valid), .adr_b(wbs_adr_slot), .clk_b(wbs_clk));
6405 97 unneback
`undef MODULE
6406 100 unneback
end
6407
endgenerate
6408 97 unneback
 
6409 100 unneback
`define MODULE dpram_1r1w
6410
`BASE`MODULE
6411
    # ( .data_width(aw_tag), .addr_width(aw_slot), .memory_init(2), .debug(debug))
6412
    tag_mem ( .d_a(wbs_adr_tag), .adr_a(wbs_adr_slot), .we_a(mem_done), .clk_a(wbm_clk),
6413
              .q_b(tag), .adr_b(wbs_adr_slot), .clk_b(wbs_clk));
6414
assign hit = wbs_adr_tag == tag;
6415
`undef MODULE
6416
 
6417
`define MODULE dpram_1r2w
6418
`BASE`MODULE
6419
    # ( .data_width(1), .addr_width(aw_slot), .memory_init(2), .debug(debug))
6420
    dirty_mem (
6421
        .d_a(1'b1), .q_a(dirty), .adr_a(wbs_adr_slot), .we_a(wbs_cyc_i & wbs_we_i & wbs_ack_o), .clk_a(wbs_clk),
6422
        .d_b(1'b0), .adr_b(wbs_adr_slot), .we_b(mem_done), .clk_b(wbm_clk));
6423
`undef MODULE
6424
 
6425 103 unneback
generate
6426
if (wbs_mode=="B3") begin : inst_b3
6427 97 unneback
`define MODULE wb_adr_inc
6428 100 unneback
`BASE`MODULE # ( .adr_width(aw_s), .max_burst_width(wbs_max_burst_width)) adr_inc0 (
6429
    .cyc_i(wbs_cyc_i & (state==rdwr) & hit & valid),
6430
    .stb_i(wbs_stb_i & (state==rdwr) & hit & valid), // throttle depending on valid
6431 97 unneback
    .cti_i(wbs_cti_i),
6432
    .bte_i(wbs_bte_i),
6433
    .adr_i(wbs_adr_i),
6434
    .we_i (wbs_we_i),
6435
    .ack_o(wbs_ack_o),
6436
    .adr_o(wbs_adr),
6437 100 unneback
    .clk(wbs_clk),
6438
    .rst(wbs_rst));
6439 97 unneback
`undef MODULE
6440 103 unneback
assign eoc = (wbs_cti_i==3'b000 | wbs_cti_i==3'b111) & wbs_ack_o;
6441
assign we = wbs_cyc_i &  wbs_we_i & wbs_ack_o;
6442
end else if (wbs_mode=="B4") begin : inst_b4
6443
end
6444 97 unneback
 
6445 103 unneback
endgenerate
6446 131 unneback
localparam cache_mem_b_aw =
6447
    (dw_s==dw_m) ? aw_slot+aw_offset :
6448 133 unneback
    (dw_s==dw_m/2) ? aw_slot+aw_offset-1 :
6449
    (dw_s==dw_m/4) ? aw_slot+aw_offset-2 :
6450
    (dw_s==dw_m/8) ? aw_slot+aw_offset-3 :
6451
    (dw_s==dw_m/16) ? aw_slot+aw_offset-4 :
6452
    (dw_s==dw_m*2) ? aw_slot+aw_offset+1 :
6453
    (dw_s==dw_m*4) ? aw_slot+aw_offset+2 :
6454
    (dw_s==dw_m*8) ? aw_slot+aw_offset+3 :
6455
    (dw_s==dw_m*16) ? aw_slot+aw_offset+4 : 0;
6456 103 unneback
 
6457 97 unneback
`define MODULE dpram_be_2r2w
6458
`BASE`MODULE
6459 100 unneback
    # ( .a_data_width(dw_s), .a_addr_width(aw_slot+aw_offset), .b_data_width(dw_m), .debug(debug))
6460 103 unneback
    cache_mem ( .d_a(wbs_dat_i), .adr_a(wbs_adr[aw_slot+aw_offset-1:0]),   .be_a(wbs_sel_i), .we_a(we), .q_a(wbs_dat_o), .clk_a(wbs_clk),
6461 136 unneback
                .d_b(wbm_dat_i), .adr_b(wbm_adr[cache_mem_b_aw-1:0]), .be_b(wbm_sel_o), .we_b(wbm_cyc_o & !wbm_we_o & wbm_ack_i), .q_b(wbm_dat_o), .clk_b(wbm_clk));
6462 97 unneback
`undef MODULE
6463
 
6464
always @ (posedge wbs_clk or posedge wbs_rst)
6465
if (wbs_rst)
6466 98 unneback
    state <= idle;
6467 97 unneback
else
6468
    case (state)
6469
    idle:
6470
        if (wbs_cyc_i)
6471
            state <= rdwr;
6472
    rdwr:
6473 100 unneback
        casex ({valid, hit, dirty, eoc})
6474
        4'b0xxx: state <= pull;
6475
        4'b11x1: state <= idle;
6476
        4'b101x: state <= push;
6477
        4'b100x: state <= pull;
6478
        endcase
6479 97 unneback
    push:
6480
        if (done)
6481
            state <= rdwr;
6482
    pull:
6483
        if (done)
6484
            state <= rdwr;
6485
    default: state <= idle;
6486
    endcase
6487
 
6488
// cdc
6489
generate
6490
if (async==1) begin : cdc0
6491
`define MODULE cdc
6492 100 unneback
`BASE`MODULE cdc0 ( .start_pl(state==rdwr & (!valid | !hit)), .take_it_pl(mem_alert), .take_it_grant_pl(mem_done), .got_it_pl(done), .clk_src(wbs_clk), .rst_src(wbs_rst), .clk_dst(wbm_clk), .rst_dst(wbm_rst));
6493 97 unneback
`undef MODULE
6494
end
6495
else begin : nocdc
6496 100 unneback
    assign mem_alert = state==rdwr & (!valid | !hit);
6497 97 unneback
    assign done = mem_done;
6498
end
6499
endgenerate
6500
 
6501 136 unneback
// FSM generating a number of bursts 4 cycles
6502 97 unneback
// actual number depends on data width ratio
6503
// nr_of_wbm_burst
6504 101 unneback
reg [nr_of_wbm_burst_width+wbm_burst_width-1:0]       cnt_rw, cnt_ack;
6505 97 unneback
 
6506
always @ (posedge wbm_clk or posedge wbm_rst)
6507
if (wbm_rst)
6508 100 unneback
    cnt_rw <= {wbm_burst_width{1'b0}};
6509 97 unneback
else
6510 100 unneback
    if (wbm_cyc_o & wbm_stb_o & !wbm_stall_i)
6511
        cnt_rw <= cnt_rw + 1;
6512 97 unneback
 
6513 98 unneback
always @ (posedge wbm_clk or posedge wbm_rst)
6514
if (wbm_rst)
6515 100 unneback
    cnt_ack <= {wbm_burst_width{1'b0}};
6516 98 unneback
else
6517 100 unneback
    if (wbm_ack_i)
6518
        cnt_ack <= cnt_ack + 1;
6519 97 unneback
 
6520 100 unneback
generate
6521 101 unneback
if (nr_of_wbm_burst==1) begin : one_burst
6522 100 unneback
 
6523 98 unneback
always @ (posedge wbm_clk or posedge wbm_rst)
6524
if (wbm_rst)
6525
    phase <= wbm_wait;
6526
else
6527
    case (phase)
6528
    wbm_wait:
6529
        if (mem_alert)
6530 100 unneback
            if (state==push)
6531
                phase <= wbm_wr;
6532
            else
6533
                phase <= wbm_rd;
6534 98 unneback
    wbm_wr:
6535 100 unneback
        if (&cnt_rw)
6536
            phase <= wbm_wr_drain;
6537
    wbm_wr_drain:
6538
        if (&cnt_ack)
6539 98 unneback
            phase <= wbm_rd;
6540
    wbm_rd:
6541 100 unneback
        if (&cnt_rw)
6542
            phase <= wbm_rd_drain;
6543
    wbm_rd_drain:
6544
        if (&cnt_ack)
6545
            phase <= wbm_wait;
6546 98 unneback
    default: phase <= wbm_wait;
6547
    endcase
6548
 
6549 100 unneback
end else begin : multiple_burst
6550
 
6551 101 unneback
always @ (posedge wbm_clk or posedge wbm_rst)
6552
if (wbm_rst)
6553
    phase <= wbm_wait;
6554
else
6555
    case (phase)
6556
    wbm_wait:
6557
        if (mem_alert)
6558
            if (state==push)
6559
                phase <= wbm_wr;
6560
            else
6561
                phase <= wbm_rd;
6562
    wbm_wr:
6563
        if (&cnt_rw[wbm_burst_width-1:0])
6564
            phase <= wbm_wr_drain;
6565
    wbm_wr_drain:
6566
        if (&cnt_ack)
6567
            phase <= wbm_rd;
6568
        else if (&cnt_ack[wbm_burst_width-1:0])
6569
            phase <= wbm_wr;
6570
    wbm_rd:
6571
        if (&cnt_rw[wbm_burst_width-1:0])
6572
            phase <= wbm_rd_drain;
6573
    wbm_rd_drain:
6574
        if (&cnt_ack)
6575
            phase <= wbm_wait;
6576
        else if (&cnt_ack[wbm_burst_width-1:0])
6577
            phase <= wbm_rd;
6578
    default: phase <= wbm_wait;
6579
    endcase
6580 100 unneback
 
6581 101 unneback
 
6582 100 unneback
end
6583
endgenerate
6584
 
6585 101 unneback
assign mem_done = phase==wbm_rd_drain & (&cnt_ack) & wbm_ack_i;
6586 100 unneback
 
6587
assign wbm_adr_o = (phase[2]) ? {tag, wbs_adr_slot, cnt_rw} : {wbs_adr_tag, wbs_adr_slot, cnt_rw};
6588 137 unneback
assign wbm_adr   = (phase[2]) ? {wbs_adr_slot, cnt_rw} : {wbs_adr_slot, cnt_ack};
6589 100 unneback
assign wbm_sel_o = {dw_m/8{1'b1}};
6590
assign wbm_cti_o = (&cnt_rw | !wbm_stb_o) ? 3'b111 : 3'b010;
6591 98 unneback
assign wbm_bte_o = bte;
6592 100 unneback
assign {wbm_we_o, wbm_stb_o, wbm_cyc_o}  = phase;
6593 98 unneback
 
6594 97 unneback
endmodule
6595
`endif
6596 103 unneback
 
6597
`ifdef WB_AVALON_BRIDGE
6598
// Wishbone to avalon bridge supporting one type of burst transfer only
6599
// intended use is together with cache above
6600
// WB B4 -> pipelined avalon
6601
`define MODULE wb_avalon_bridge
6602
module `BASE`MODULE (
6603
`undef MODULE
6604
        // wishbone slave side
6605
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_stall_o,
6606
        // avalon master side
6607
        readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer,
6608 136 unneback
        init_done,
6609 103 unneback
        // common
6610
        clk, rst);
6611
 
6612
parameter adr_width = 30;
6613
parameter dat_width = 32;
6614
parameter burst_size = 4;
6615
 
6616
input [dat_width-1:0] wbs_dat_i;
6617
input [adr_width-1:0] wbs_adr_i;
6618
input [dat_width/8-1:0]  wbs_sel_i;
6619
input [1:0]  wbs_bte_i;
6620
input [2:0]  wbs_cti_i;
6621
input wbs_we_i;
6622
input wbs_cyc_i;
6623
input wbs_stb_i;
6624 130 unneback
output [dat_width-1:0] wbs_dat_o;
6625 103 unneback
output wbs_ack_o;
6626
output wbs_stall_o;
6627
 
6628
input [dat_width-1:0] readdata;
6629
input readdatavalid;
6630
output [dat_width-1:0] writedata;
6631
output [adr_width-1:0] address;
6632
output [dat_width/8-1:0]  be;
6633
output write;
6634
output read;
6635
output beginbursttransfer;
6636
output [3:0] burstcount;
6637
input waitrequest;
6638 136 unneback
input init_done;
6639 103 unneback
input clk, rst;
6640
 
6641 136 unneback
// cnt1 - initiated read or writes
6642
// cnt2 - # of read or writes in pipeline
6643
reg [3:0] cnt1;
6644
reg [3:0] cnt2;
6645 103 unneback
 
6646 136 unneback
reg next_state, state;
6647
localparam s0 = 1'b0;
6648
localparam s1 = 1'b1;
6649
 
6650
wire eoc;
6651
 
6652
always @ *
6653
begin
6654
    case (state)
6655
    s0: if (init_done & wbs_cyc_i) next_state <= s1;
6656
    s1:
6657
    default: next_state <= state;
6658
    end
6659
end
6660
 
6661 103 unneback
always @ (posedge clk or posedge rst)
6662
if (rst)
6663 136 unneback
    state <= s0;
6664 103 unneback
else
6665 136 unneback
    state <= next_state;
6666 103 unneback
 
6667 136 unneback
assign eoc = state==s1 & !(read | write) & (& !waitrequest & cnt2=;
6668
always @ (posedge clk or posedge rst)
6669
if (rst)
6670
    cnt1 <= 4'h0;
6671
else
6672
    if (read & !waitrequest & init_done)
6673
        cnt1 <= burst_size - 1;
6674
    else if (write & !waitrequest & init_done)
6675
        cnt1 <= cnt1 + 4'h1;
6676
    else if (next_state==idle)
6677
        cnt1 <= 4'h0;
6678
 
6679
always @ (posedge clk or posedge rst)
6680
if (rst)
6681
    cnt2 <= 4'h0;
6682
else
6683
    if (read & !waitrequest & init_done)
6684
        cnt2 <= burst_size - 1;
6685
    else if (write & !waitrequest & init_done & )
6686
        cnt2 <= cnt1 + 4'h1;
6687
    else if (next_state==idle)
6688
        cnt2 <= 4'h0;
6689
 
6690 103 unneback
reg wr_ack;
6691
always @ (posedge clk or posedge rst)
6692
if (rst)
6693
    wr_ack <= 1'b0;
6694
else
6695
    wr_ack <=  (wbs_we_i & wbs_cyc_i & wbs_stb_i & !wbs_stall_o);
6696
 
6697
// to avalon
6698
assign writedata = wbs_dat_i;
6699
assign address = wbs_adr_i;
6700
assign be = wbs_sel_i;
6701 136 unneback
assign write = cnt!=4'h0 & wbs_cyc_i &  wbs_we_i;
6702
assign read  = cnt!=4'h0 & wbs_cyc_i & !wbs_we_i;
6703
assign beginbursttransfer = state==s0 & next_state==s1;
6704 103 unneback
assign burstcount = burst_size;
6705
 
6706
// to wishbone
6707
assign wbs_dat_o = readdata;
6708
assign wbs_ack_o = wr_ack | readdatavalid;
6709
assign wbs_stall_o = waitrequest;
6710
 
6711
endmodule
6712
`endif
6713
 
6714
`ifdef WB_AVALON_MEM_CACHE
6715
`define MODULE wb_avalon_mem_cache
6716
module `BASE`MODULE (
6717
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i, wbs_dat_o, wbs_ack_o, wbs_stall_o, wbs_clk, wbs_rst,
6718
    readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst
6719
);
6720
`undef MODULE
6721
 
6722
// wishbone
6723
parameter wb_dat_width = 32;
6724
parameter wb_adr_width = 22;
6725
parameter wb_max_burst_width = 4;
6726
parameter wb_mode = "B4";
6727
// avalon
6728
parameter avalon_dat_width = 32;
6729 121 unneback
//localparam avalon_adr_width = wb_dat_width * wb_adr_width / avalon_dat_width;
6730 122 unneback
localparam avalon_adr_width =
6731
        (wb_dat_width==avalon_dat_width) ? wb_adr_width :
6732
        (wb_dat_width==avalon_dat_width*2) ? wb_adr_width+1 :
6733
        (wb_dat_width==avalon_dat_width*4) ? wb_adr_width+2 :
6734
        (wb_dat_width==avalon_dat_width*8) ? wb_adr_width+3 :
6735
        (wb_dat_width==avalon_dat_width*16) ? wb_adr_width+4 :
6736
        (wb_dat_width==avalon_dat_width*32) ? wb_adr_width+5 :
6737
        (wb_dat_width==avalon_dat_width/2) ? wb_adr_width-1 :
6738
        (wb_dat_width==avalon_dat_width/4) ? wb_adr_width-2 :
6739
        (wb_dat_width==avalon_dat_width/8) ? wb_adr_width-3 :
6740
        (wb_dat_width==avalon_dat_width/16) ? wb_adr_width-4 :
6741 123 unneback
        (wb_dat_width==avalon_dat_width/32) ? wb_adr_width-5 : 0;
6742 103 unneback
parameter avalon_burst_size = 4;
6743
// cache
6744
parameter async = 1;
6745
parameter nr_of_ways = 1;
6746
parameter aw_offset = 4;
6747
parameter aw_slot = 10;
6748
parameter valid_mem = 1;
6749
// shadow RAM
6750
parameter shadow_ram = 0;
6751
parameter shadow_ram_adr_width = 10;
6752
parameter shadow_ram_size = 1024;
6753
parameter shadow_ram_init = 2; // 0: no init, 1: from file, 2: with zero
6754
parameter shadow_ram_file = "vl_ram.v";
6755
 
6756
input [wb_dat_width-1:0] wbs_dat_i;
6757
input [wb_adr_width-1:0] wbs_adr_i; // dont include a1,a0
6758
input [wb_dat_width/8-1:0] wbs_sel_i;
6759
input [2:0] wbs_cti_i;
6760
input [1:0] wbs_bte_i;
6761
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
6762
output [wb_dat_width-1:0] wbs_dat_o;
6763
output wbs_ack_o;
6764
output wbs_stall_o;
6765
input wbs_clk, wbs_rst;
6766
 
6767
input [avalon_dat_width-1:0] readdata;
6768
input readdatavalid;
6769
output [avalon_dat_width-1:0] writedata;
6770
output [avalon_adr_width-1:0] address;
6771
output [avalon_dat_width/8-1:0]  be;
6772
output write;
6773
output read;
6774
output beginbursttransfer;
6775
output [3:0] burstcount;
6776
input waitrequest;
6777
input clk, rst;
6778
 
6779
`define DAT_WIDTH wb_dat_width
6780
`define ADR_WIDTH wb_adr_width
6781
`define WB wb1
6782
`include "wb_wires.v"
6783 129 unneback
`undef DAT_WIDTH
6784
`undef ADR_WIDTH
6785
`define DAT_WIDTH avalon_dat_width
6786
`define ADR_WIDTH avalon_adr_width
6787 103 unneback
`define WB wb2
6788
`include "wb_wires.v"
6789
`undef DAT_WIDTH
6790
`undef ADR_WIDTH
6791
 
6792
`define MODULE wb_shadow_ram
6793
`BASE`MODULE # ( .dat_width(wb_dat_width), .mode(wb_mode), .max_burst_width(wb_max_burst_width),
6794 120 unneback
                 .shadow_mem_adr_width(shadow_ram_adr_width), .shadow_mem_size(shadow_ram_size), .shadow_mem_init(shadow_ram_init), .shadow_mem_file(shadow_ram_file),
6795 103 unneback
                 .main_mem_adr_width(wb_adr_width))
6796
shadow_ram0 (
6797
    .wbs_dat_i(wbs_dat_i), .wbs_adr_i(wbs_adr_i), .wbs_cti_i(wbs_cti_i), .wbs_bte_i(wbs_bte_i), .wbs_sel_i(wbs_sel_i), .wbs_we_i(wbs_we_i), .wbs_stb_i(wbs_stb_i), .wbs_cyc_i(wbs_cyc_i),
6798
    .wbs_dat_o(wbs_dat_o), .wbs_ack_o(wbs_ack_o), .wbs_stall_o(wbs_stall_o),
6799
    .wbm_dat_o(wb1_dat_o), .wbm_adr_o(wb1_adr_o), .wbm_cti_o(wb1_cti_o), .wbm_bte_o(wb1_bte_o), .wbm_sel_o(wb1_sel_o), .wbm_we_o(wb1_we_o), .wbm_stb_o(wb1_stb_o), .wbm_cyc_o(wb1_cyc_o),
6800
    .wbm_dat_i(wb1_dat_i), .wbm_ack_i(wb1_ack_i), .wbm_stall_i(wb1_stall_i),
6801
    .wb_clk(wbs_clk), .wb_rst(wbs_rst));
6802
`undef MODULE
6803
 
6804
`define MODULE wb_cache
6805
`BASE`MODULE
6806
# ( .dw_s(wb_dat_width), .aw_s(wb_adr_width), .dw_m(avalon_dat_width), .wbs_mode(wb_mode), .wbs_max_burst_width(wb_max_burst_width), .async(async), .nr_of_ways(nr_of_ways), .aw_offset(aw_offset), .aw_slot(aw_slot), .valid_mem(valid_mem))
6807
cache0 (
6808
    .wbs_dat_i(wb1_dat_o), .wbs_adr_i(wb1_adr_o), .wbs_sel_i(wb1_sel_o), .wbs_cti_i(wb1_cti_o), .wbs_bte_i(wb1_bte_o), .wbs_we_i(wb1_we_o), .wbs_stb_i(wb1_stb_o), .wbs_cyc_i(wb1_cyc_o),
6809
    .wbs_dat_o(wb1_dat_i), .wbs_ack_o(wb1_ack_i), .wbs_stall_o(wb1_stall_i), .wbs_clk(wbs_clk), .wbs_rst(wbs_rst),
6810
    .wbm_dat_o(wb2_dat_o), .wbm_adr_o(wb2_adr_o), .wbm_sel_o(wb2_sel_o), .wbm_cti_o(wb2_cti_o), .wbm_bte_o(wb2_bte_o), .wbm_we_o(wb2_we_o), .wbm_stb_o(wb2_stb_o), .wbm_cyc_o(wb2_cyc_o),
6811
    .wbm_dat_i(wb2_dat_i), .wbm_ack_i(wb2_ack_i), .wbm_stall_i(wb2_stall_i), .wbm_clk(clk), .wbm_rst(rst));
6812
`undef MODULE
6813
 
6814
`define MODULE wb_avalon_bridge
6815
`BASE`MODULE # ( .adr_width(avalon_adr_width), .dat_width(avalon_dat_width), .burst_size(avalon_burst_size))
6816
bridge0 (
6817
        // wishbone slave side
6818
        .wbs_dat_i(wb2_dat_o), .wbs_adr_i(wb2_adr_o), .wbs_sel_i(wb2_sel_o), .wbs_bte_i(wb2_bte_o), .wbs_cti_i(wb2_cti_o), .wbs_we_i(wb2_we_o), .wbs_cyc_i(wb2_cyc_o), .wbs_stb_i(wb2_stb_o),
6819
        .wbs_dat_o(wb2_dat_i), .wbs_ack_o(wb2_ack_i), .wbs_stall_o(wb2_stall_i),
6820
        // avalon master side
6821
        .readdata(readdata), .readdatavalid(readdatavalid), .address(address), .read(read), .be(be), .write(write), .burstcount(burstcount), .writedata(writedata), .waitrequest(waitrequest), .beginbursttransfer(beginbursttransfer),
6822
        // common
6823
        .clk(clk), .rst(rst));
6824
`undef MODULE
6825
 
6826
endmodule
6827
`endif
6828 105 unneback
 
6829
`ifdef WB_SDR_SDRAM
6830
`define MODULE wb_sdr_sdram
6831
module `BASE`MODULE (
6832
`undef MODULE
6833
    // wisbone i/f
6834 136 unneback
    dat_i, adr_i, sel_i, we_i, cyc_i, stb_i, dat_o, ack_o, stall_o,
6835 105 unneback
    // SDR SDRAM
6836
    ba, a, cmd, cke, cs_n, dqm, dq_i, dq_o, dq_oe,
6837
    // system
6838
    clk, rst);
6839
 
6840
    // external data bus size
6841
    parameter dat_size = 16;
6842
    // memory geometry parameters
6843 136 unneback
    parameter ba_size  = 2;
6844
    parameter row_size = 13;
6845
    parameter col_size = 9;
6846 105 unneback
    parameter cl = 2;
6847
    // memory timing parameters
6848
    parameter tRFC = 9;
6849
    parameter tRP  = 2;
6850
    parameter tRCD = 2;
6851
    parameter tMRD = 2;
6852
 
6853
    // LMR
6854
    // [12:10] reserved
6855
    // [9]     WB, write burst; 0 - programmed burst length, 1 - single location
6856
    // [8:7]   OP Mode, 2'b00
6857
    // [6:4]   CAS Latency; 3'b010 - 2, 3'b011 - 3
6858
    // [3]     BT, Burst Type; 1'b0 - sequential, 1'b1 - interleaved
6859
    // [2:0]   Burst length; 3'b000 - 1, 3'b001 - 2, 3'b010 - 4, 3'b011 - 8, 3'b111 - full page
6860
    localparam init_wb = 1'b1;
6861
    localparam init_cl = (cl==2) ? 3'b010 : 3'b011;
6862
    localparam init_bt = 1'b0;
6863
    localparam init_bl = 3'b000;
6864
 
6865 136 unneback
    input [dat_size-1:0] dat_i;
6866 105 unneback
    input [ba_size+col_size+row_size-1:0] adr_i;
6867
    input [dat_size/8-1:0] sel_i;
6868
    input we_i, cyc_i, stb_i;
6869
    output [dat_size-1:0] dat_o;
6870
    output ack_o;
6871
    output reg stall_o;
6872
 
6873
    output [ba_size-1:0]    ba;
6874
    output reg [12:0]   a;
6875
    output reg [2:0]    cmd; // {ras,cas,we}
6876
    output cke, cs_n;
6877
    output reg [dat_size/8-1:0]    dqm;
6878
    output [dat_size-1:0]       dq_o;
6879
    output reg          dq_oe;
6880
    input  [dat_size-1:0]       dq_i;
6881
 
6882
    input clk, rst;
6883
 
6884
    wire [ba_size-1:0]   bank;
6885
    wire [row_size-1:0] row;
6886
    wire [col_size-1:0] col;
6887
    wire [0:31]  shreg;
6888
    wire                ref_cnt_zero;
6889
    reg                 refresh_req;
6890
 
6891
    wire ack_rd, rd_ack_emptyflag;
6892
    wire ack_wr;
6893
 
6894
    // to keep track of open rows per bank
6895
    reg [row_size-1:0]   open_row[0:3];
6896
    reg [0:3]            open_ba;
6897
    reg                 current_bank_closed, current_row_open;
6898
 
6899
    parameter rfr_length = 10;
6900
    parameter rfr_wrap_value = 1010;
6901
 
6902
    parameter [2:0] cmd_nop = 3'b111,
6903
                    cmd_act = 3'b011,
6904
                    cmd_rd  = 3'b101,
6905
                    cmd_wr  = 3'b100,
6906
                    cmd_pch = 3'b010,
6907
                    cmd_rfr = 3'b001,
6908
                    cmd_lmr = 3'b000;
6909
 
6910
// ctrl FSM
6911
`define FSM_INIT 3'b000
6912
`define FSM_IDLE 3'b001
6913
`define FSM_RFR  3'b010
6914
`define FSM_ADR  3'b011
6915
`define FSM_PCH  3'b100
6916
`define FSM_ACT  3'b101
6917
`define FSM_RW   3'b111
6918
 
6919
    assign cke = 1'b1;
6920
    assign cs_n = 1'b0;
6921
 
6922
    reg [2:0] state, next;
6923
 
6924
    function [12:0] a10_fix;
6925
        input [col_size-1:0] a;
6926
        integer i;
6927
    begin
6928
        for (i=0;i<13;i=i+1) begin
6929
            if (i<10)
6930
              if (i<col_size)
6931
                a10_fix[i] = a[i];
6932
              else
6933
                a10_fix[i] = 1'b0;
6934
            else if (i==10)
6935
              a10_fix[i] = 1'b0;
6936
            else
6937
              if (i<col_size)
6938
                a10_fix[i] = a[i-1];
6939
              else
6940
                a10_fix[i] = 1'b0;
6941
        end
6942
    end
6943
    endfunction
6944
 
6945
    assign {bank,row,col} = adr_i;
6946
 
6947
    always @ (posedge clk or posedge rst)
6948
    if (rst)
6949
       state <= `FSM_INIT;
6950
    else
6951
       state <= next;
6952
 
6953
    always @*
6954
    begin
6955
        next = state;
6956
        case (state)
6957
        `FSM_INIT:
6958
            if (shreg[3+tRP+tRFC+tRFC+tMRD]) next = `FSM_IDLE;
6959
        `FSM_IDLE:
6960
            if (refresh_req) next = `FSM_RFR;
6961
            else if (cyc_i & stb_i & rd_ack_emptyflag) next = `FSM_ADR;
6962
        `FSM_RFR:
6963
            if (shreg[tRP+tRFC-2]) next = `FSM_IDLE; // take away two cycles because no cmd will be issued in idle and adr
6964
        `FSM_ADR:
6965
            if (current_bank_closed) next = `FSM_ACT;
6966
            else if (current_row_open) next = `FSM_RW;
6967
            else next = `FSM_PCH;
6968
        `FSM_PCH:
6969
            if (shreg[tRP]) next = `FSM_ACT;
6970
        `FSM_ACT:
6971
            if (shreg[tRCD]) next = `FSM_RW;
6972
        `FSM_RW:
6973
            if (!stb_i) next = `FSM_IDLE;
6974
        endcase
6975
    end
6976
 
6977
    // counter
6978 136 unneback
`define MODULE cnt_shreg_clear
6979
    `BASE`MODULE # ( .length(32))
6980 105 unneback
`undef MODULE
6981
        cnt0 (
6982
            .clear(state!=next),
6983
            .q(shreg),
6984
            .rst(rst),
6985
            .clk(clk));
6986
 
6987
    // ba, a, cmd
6988
    // outputs dependent on state vector
6989
    always @ (*)
6990
        begin
6991
            {a,cmd} = {13'd0,cmd_nop};
6992
            dqm = 2'b11;
6993
            dq_oe = 1'b0;
6994
            stall_o = 1'b1;
6995
            case (state)
6996
            `FSM_INIT:
6997
                if (shreg[3]) begin
6998
                    {a,cmd} = {13'b0010000000000, cmd_pch};
6999
                end else if (shreg[3+tRP] | shreg[3+tRP+tRFC])
7000
                    {a,cmd} = {13'd0, cmd_rfr};
7001
                else if (shreg[3+tRP+tRFC+tRFC])
7002
                    {a,cmd} = {3'b000,init_wb,2'b00,init_cl,init_bt,init_bl,cmd_lmr};
7003
            `FSM_RFR:
7004
                if (shreg[0])
7005
                    {a,cmd} = {13'b0010000000000, cmd_pch};
7006
                else if (shreg[tRP])
7007
                    {a,cmd} = {13'd0, cmd_rfr};
7008
            `FSM_PCH:
7009
                if (shreg[0])
7010
                    {a,cmd} = {13'd0,cmd_pch};
7011
            `FSM_ACT:
7012
                if (shreg[0])
7013
                    {a[row_size-1:0],cmd} = {row,cmd_act};
7014
            `FSM_RW:
7015
                begin
7016
                    if (we_i)
7017
                        cmd = cmd_wr;
7018
                    else
7019
                        cmd = cmd_rd;
7020
                    if (we_i)
7021
                        dqm = ~sel_i;
7022
                    else
7023
                        dqm = 2'b00;
7024
                    if (we_i)
7025
                        dq_oe = 1'b1;
7026
                    a = a10_fix(col);
7027 136 unneback
                    stall_o = 1'b0;
7028 105 unneback
                end
7029
            endcase
7030
        end
7031
 
7032
    assign ba = bank;
7033
 
7034
    // precharge individual bank A10=0
7035
    // precharge all bank A10=1
7036
    genvar i;
7037
    generate
7038 136 unneback
    for (i=0;i<2<<ba_size-1;i=i+1) begin : open_ba_logic
7039 105 unneback
 
7040
        always @ (posedge clk or posedge rst)
7041
        if (rst)
7042
            {open_ba[i],open_row[i]} <= {1'b0,{row_size{1'b0}}};
7043
        else
7044
            if (cmd==cmd_pch & (a[10] | bank==i))
7045
                open_ba[i] <= 1'b0;
7046
            else if (cmd==cmd_act & bank==i)
7047
                {open_ba[i],open_row[i]} <= {1'b1,row};
7048
 
7049
    end
7050
    endgenerate
7051
 
7052
    // bank and row open ?
7053
    always @ (posedge clk or posedge rst)
7054
    if (rst)
7055
       {current_bank_closed, current_row_open} <= {1'b1, 1'b0};
7056
    else
7057
       {current_bank_closed, current_row_open} <= {!(open_ba[bank]), open_row[bank]==row};
7058
 
7059
    // refresh counter
7060
`define MODULE cnt_lfsr_zq
7061 136 unneback
    `BASE`MODULE # ( .length(rfr_length), .wrap_value (rfr_wrap_value)) ref_counter0( .zq(ref_cnt_zero), .rst(rst), .clk(clk));
7062 105 unneback
`undef MODULE
7063
 
7064
    always @ (posedge clk or posedge rst)
7065
    if (rst)
7066
        refresh_req <= 1'b0;
7067
    else
7068
        if (ref_cnt_zero)
7069
            refresh_req <= 1'b1;
7070
        else if (state==`FSM_RFR)
7071
            refresh_req <= 1'b0;
7072
 
7073
    assign dat_o = dq_i;
7074
 
7075 136 unneback
    assign ack_wr = (state==`FSM_RW & we_i);
7076 105 unneback
`define MODULE delay_emptyflag
7077 136 unneback
    `BASE`MODULE # ( .depth(cl+2)) delay0 ( .d(state==`FSM_RW & stb_i & !we_i), .q(ack_rd), .emptyflag(rd_ack_emptyflag), .clk(clk), .rst(rst));
7078 105 unneback
`undef MODULE
7079
    assign ack_o = ack_rd | ack_wr;
7080
 
7081
    assign dq_o = dat_i;
7082
 
7083
endmodule
7084
`endif
7085 136 unneback
 
7086
`ifdef WB_SDR_SDRAM_CTRL
7087
`define MODULE wb_sdr_sdram_ctrl
7088
module `BASE`MODULE (
7089
    // WB i/f
7090
    wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
7091
    wbs_dat_o, wbs_ack_o, wbs_stall_o,
7092
    // SDR SDRAM
7093
    mem_ba, mem_a, mem_cmd, mem_cke, mem_cs_n, mem_dqm, mem_dq_i, mem_dq_o, mem_dq_oe,
7094
    // system
7095
    wb_clk, wb_rst, mem_clk, mem_rst);
7096
`undef MODULE
7097
 
7098
    // WB slave
7099
    parameter wbs_dat_width = 32;
7100
    parameter wbs_adr_width = 24;
7101
    parameter wbs_mode = "B3";
7102
    parameter wbs_max_burst_width = 4;
7103
 
7104
    // Shadow RAM
7105
    parameter shadow_mem_adr_width = 10;
7106
    parameter shadow_mem_size = 1024;
7107
    parameter shadow_mem_init = 2;
7108
    parameter shadow_mem_file = "vl_ram.v";
7109
 
7110
    // Cache
7111
    parameter cache_async = 1; // wbs_clk != wbm_clk
7112
    parameter cache_nr_of_ways = 1;
7113
    parameter cache_aw_offset = 4; // 4 => 16 words per cache line
7114
    parameter cache_aw_slot = 10;
7115
    parameter cache_valid_mem = 0;
7116
    parameter cache_debug = 0;
7117
 
7118
    // SDRAM parameters
7119
    parameter mem_dat_size = 16;
7120
    parameter mem_ba_size  = 2;
7121
    parameter mem_row_size = 13;
7122
    parameter mem_col_size = 9;
7123
    parameter mem_cl = 2;
7124
    parameter mem_tRFC = 9;
7125
    parameter mem_tRP  = 2;
7126
    parameter mem_tRCD = 2;
7127
    parameter mem_tMRD = 2;
7128
    parameter mem_rfr_length = 10;
7129
    parameter mem_rfr_wrap_value = 1010;
7130
 
7131
    input [wbs_dat_width-1:0] wbs_dat_i;
7132
    input [wbs_adr_width-1:0] wbs_adr_i;
7133
    input [2:0] wbs_cti_i;
7134
    input [1:0] wbs_bte_i;
7135
    input [wbs_dat_width/8-1:0] wbs_sel_i;
7136
    input wbs_we_i, wbs_stb_i, wbs_cyc_i;
7137
    output [wbs_dat_width-1:0] wbs_dat_o;
7138
    output wbs_ack_o;
7139
    output wbs_stall_o;
7140
 
7141
    output [mem_ba_size-1:0]    mem_ba;
7142
    output reg [12:0]           mem_a;
7143
    output reg [2:0]            mem_cmd; // {ras,cas,we}
7144
    output                      mem_cke, mem_cs_n;
7145
    output reg [mem_dat_size/8-1:0] mem_dqm;
7146
    output [mem_dat_size-1:0]       mem_dq_o;
7147
    output reg                  mem_dq_oe;
7148
    input  [mem_dat_size-1:0]       mem_dq_i;
7149
 
7150
    input wb_clk, wb_rst, mem_clk, mem_rst;
7151
 
7152
    // wbm1
7153
    wire [wbs_dat_width-1:0] wbm1_dat_o;
7154
    wire [wbs_adr_width-1:0] wbm1_adr_o;
7155
    wire [2:0] wbm1_cti_o;
7156
    wire [1:0] wbm1_bte_o;
7157
    wire [wbs_dat_width/8-1:0] wbm1_sel_o;
7158
    wire wbm1_we_o, wbm1_stb_o, wbm1_cyc_o;
7159
    wire [wbs_dat_width-1:0] wbm1_dat_i;
7160
    wire wbm1_ack_i, wbm1_stall_i;
7161
    // wbm2
7162
    wire [mem_dat_size-1:0] wbm2_dat_o;
7163
    wire [mem_ba_size+mem_row_size+mem_col_size-1:0] wbm2_adr_o;
7164
    wire [2:0] wbm2_cti_o;
7165
    wire [1:0] wbm2_bte_o;
7166
    wire [mem_dat_size/8-1:0] wbm2_sel_o;
7167
    wire wbm2_we_o, wbm2_stb_o, wbm2_cyc_o;
7168
    wire [mem_dat_size-1:0] wbm2_dat_i;
7169
    wire wbm2_ack_i, wbm2_stall_i;
7170
 
7171
`define MODULE wb_shadow_ram
7172
`BASE`MODULE # (
7173
    .shadow_mem_adr_width(shadow_mem_adr_width), .shadow_mem_size(shadow_mem_size), .shadow_mem_init(shadow_mem_init), .shadow_mem_file(shadow_mem_file), .main_mem_adr_width(wbs_adr_width), .dat_width(wbs_dat_width), .mode(wbs_mode), .max_burst_width(wbs_max_burst_width) )
7174
shadow_ram0 (
7175
    .wbs_dat_i(wbs_dat_i),
7176
    .wbs_adr_i(wbs_adr_i),
7177
    .wbs_cti_i(wbs_cti_i),
7178
    .wbs_bte_i(wbs_bte_i),
7179
    .wbs_sel_i(wbs_sel_i),
7180
    .wbs_we_i (wbs_we_i),
7181
    .wbs_stb_i(wbs_stb_i),
7182
    .wbs_cyc_i(wbs_cyc_i),
7183
    .wbs_dat_o(wbs_dat_o),
7184
    .wbs_ack_o(wbs_ack_o),
7185
    .wbs_stall_o(wbs_stall_o),
7186
    .wbm_dat_o(wbm1_dat_o),
7187
    .wbm_adr_o(wbm1_adr_o),
7188
    .wbm_cti_o(wbm1_cti_o),
7189
    .wbm_bte_o(wbm1_bte_o),
7190
    .wbm_sel_o(wbm1_sel_o),
7191
    .wbm_we_o(wbm1_we_o),
7192
    .wbm_stb_o(wbm1_stb_o),
7193
    .wbm_cyc_o(wbm1_cyc_o),
7194
    .wbm_dat_i(wbm1_dat_i),
7195
    .wbm_ack_i(wbm1_ack_i),
7196
    .wbm_stall_i(wbm1_stall_i),
7197
    .wb_clk(wb_clk),
7198
    .wb_rst(wb_rst) );
7199
`undef MODULE
7200
 
7201
`define MODULE wb_cache
7202
`BASE`MODULE # (
7203
    .dw_s(wbs_dat_width), .aw_s(wbs_adr_width), .dw_m(mem_dat_size), .wbs_max_burst_width(cache_aw_offset), .wbs_mode(wbs_mode), .async(cache_async), .nr_of_ways(cache_nr_of_ways), .aw_offset(cache_aw_offset), .aw_slot(cache_aw_slot), .valid_mem(cache_valid_mem) )
7204
cache0 (
7205
    .wbs_dat_i(wbm1_dat_o),
7206
    .wbs_adr_i(wbm1_adr_o),
7207
    .wbs_sel_i(wbm1_sel_o),
7208
    .wbs_cti_i(wbm1_cti_o),
7209
    .wbs_bte_i(wbm1_bte_o),
7210
    .wbs_we_i (wbm1_we_o),
7211
    .wbs_stb_i(wbm1_stb_o),
7212
    .wbs_cyc_i(wbm1_cyc_o),
7213
    .wbs_dat_o(wbm1_dat_i),
7214
    .wbs_ack_o(wbm1_ack_i),
7215
    .wbs_stall_o(wbm1_stall_i),
7216
    .wbs_clk(wb_clk),
7217
    .wbs_rst(wb_rst),
7218
    .wbm_dat_o(wbm2_dat_o),
7219
    .wbm_adr_o(wbm2_adr_o),
7220
    .wbm_sel_o(wbm2_sel_o),
7221
    .wbm_cti_o(wbm2_cti_o),
7222
    .wbm_bte_o(wbm2_bte_o),
7223
    .wbm_we_o (wbm2_we_o),
7224
    .wbm_stb_o(wbm2_stb_o),
7225
    .wbm_cyc_o(wbm2_cyc_o),
7226
    .wbm_dat_i(wbm2_dat_i),
7227
    .wbm_ack_i(wbm2_ack_i),
7228
    .wbm_stall_i(wbm2_stall_i),
7229
    .wbm_clk(mem_clk),
7230
    .wbm_rst(mem_rst) );
7231
`undef MODULE
7232
 
7233
`define MODULE wb_sdr_sdram
7234
`BASE`MODULE # (
7235
    .dat_size(mem_dat_size), .ba_size(mem_ba_size), .row_size(mem_row_size), .col_size(mem_col_size), .cl(mem_cl), .tRFC(mem_tRFC), .tRP(mem_tRP), .tRCD(mem_tRCD), .tMRD(mem_tMRD), .rfr_length(mem_rfr_length), .rfr_wrap_value(mem_rfr_wrap_value) )
7236
ctrl0(
7237
    // wisbone i/f
7238
    .dat_i(wbm2_dat_o),
7239
    .adr_i(wbm2_adr_o),
7240
    .sel_i(wbm2_sel_o),
7241
    .we_i (wbm2_we_o),
7242
    .cyc_i(wbm2_cyc_o),
7243
    .stb_i(wbm2_stb_o),
7244
    .dat_o(wbm2_dat_i),
7245
    .ack_o(wbm2_ack_i),
7246
    .stall_o(wbm2_stall_i),
7247
    // SDR SDRAM
7248
    .ba(mem_ba),
7249
    .a(mem_a),
7250
    .cmd(mem_cmd),
7251
    .cke(mem_cke),
7252
    .cs_n(mem_cs_n),
7253
    .dqm(mem_dqm),
7254
    .dq_i(mem_dq_i),
7255
    .dq_o(mem_dq_o),
7256
    .dq_oe(mem_dq_oe),
7257
    // system
7258
    .clk(mem_clk),
7259
    .rst(mem_rst) );
7260
`undef MODULE
7261
 
7262
endmodule
7263
`endif
7264 18 unneback
//////////////////////////////////////////////////////////////////////
7265
////                                                              ////
7266
////  Arithmetic functions                                        ////
7267
////                                                              ////
7268
////  Description                                                 ////
7269
////  Arithmetic functions for ALU and DSP                        ////
7270
////                                                              ////
7271
////                                                              ////
7272
////  To Do:                                                      ////
7273
////   -                                                          ////
7274
////                                                              ////
7275
////  Author(s):                                                  ////
7276
////      - Michael Unneback, unneback@opencores.org              ////
7277
////        ORSoC AB                                              ////
7278
////                                                              ////
7279
//////////////////////////////////////////////////////////////////////
7280
////                                                              ////
7281
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
7282
////                                                              ////
7283
//// This source file may be used and distributed without         ////
7284
//// restriction provided that this copyright statement is not    ////
7285
//// removed from the file and that any derivative work contains  ////
7286
//// the original copyright notice and the associated disclaimer. ////
7287
////                                                              ////
7288
//// This source file is free software; you can redistribute it   ////
7289
//// and/or modify it under the terms of the GNU Lesser General   ////
7290
//// Public License as published by the Free Software Foundation; ////
7291
//// either version 2.1 of the License, or (at your option) any   ////
7292
//// later version.                                               ////
7293
////                                                              ////
7294
//// This source is distributed in the hope that it will be       ////
7295
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
7296
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
7297
//// PURPOSE.  See the GNU Lesser General Public License for more ////
7298
//// details.                                                     ////
7299
////                                                              ////
7300
//// You should have received a copy of the GNU Lesser General    ////
7301
//// Public License along with this source; if not, download it   ////
7302
//// from http://www.opencores.org/lgpl.shtml                     ////
7303
////                                                              ////
7304
//////////////////////////////////////////////////////////////////////
7305
 
7306 40 unneback
`ifdef MULTS
7307 18 unneback
// signed multiplication
7308 40 unneback
`define MODULE mults
7309
module `BASE`MODULE (a,b,p);
7310
`undef MODULE
7311 18 unneback
parameter operand_a_width = 18;
7312
parameter operand_b_width = 18;
7313
parameter result_hi = 35;
7314
parameter result_lo = 0;
7315
input [operand_a_width-1:0] a;
7316
input [operand_b_width-1:0] b;
7317
output [result_hi:result_lo] p;
7318
wire signed [operand_a_width-1:0] ai;
7319
wire signed [operand_b_width-1:0] bi;
7320
wire signed [operand_a_width+operand_b_width-1:0] result;
7321
 
7322
    assign ai = a;
7323
    assign bi = b;
7324
    assign result = ai * bi;
7325
    assign p = result[result_hi:result_lo];
7326
 
7327
endmodule
7328 40 unneback
`endif
7329
`ifdef MULTS18X18
7330
`define MODULE mults18x18
7331
module `BASE`MODULE (a,b,p);
7332
`undef MODULE
7333 18 unneback
input [17:0] a,b;
7334
output [35:0] p;
7335
vl_mult
7336
    # (.operand_a_width(18), .operand_b_width(18))
7337
    mult0 (.a(a), .b(b), .p(p));
7338
endmodule
7339 40 unneback
`endif
7340 18 unneback
 
7341 40 unneback
`ifdef MULT
7342
`define MODULE mult
7343 18 unneback
// unsigned multiplication
7344 40 unneback
module `BASE`MODULE (a,b,p);
7345
`undef MODULE
7346 18 unneback
parameter operand_a_width = 18;
7347
parameter operand_b_width = 18;
7348
parameter result_hi = 35;
7349
parameter result_lo = 0;
7350
input [operand_a_width-1:0] a;
7351
input [operand_b_width-1:0] b;
7352
output [result_hi:result_hi] p;
7353
 
7354
wire [operand_a_width+operand_b_width-1:0] result;
7355
 
7356
    assign result = a * b;
7357
    assign p = result[result_hi:result_lo];
7358
 
7359
endmodule
7360 40 unneback
`endif
7361 18 unneback
 
7362 40 unneback
`ifdef SHIFT_UNIT_32
7363
`define MODULE shift_unit_32
7364 18 unneback
// shift unit
7365
// supporting the following shift functions
7366
//   SLL
7367
//   SRL
7368
//   SRA
7369
`define SHIFT_UNIT_MULT # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7))
7370 40 unneback
module `BASE`MODULE( din, s, dout, opcode);
7371
`undef MODULE
7372 18 unneback
input [31:0] din; // data in operand
7373
input [4:0] s; // shift operand
7374
input [1:0] opcode;
7375
output [31:0] dout;
7376
 
7377
parameter opcode_sll = 2'b00;
7378
//parameter opcode_srl = 2'b01;
7379
parameter opcode_sra = 2'b10;
7380
//parameter opcode_ror = 2'b11;
7381
 
7382
wire sll, sra;
7383
assign sll = opcode == opcode_sll;
7384
assign sra = opcode == opcode_sra;
7385
 
7386
wire [15:1] s1;
7387
wire [3:0] sign;
7388
wire [7:0] tmp [0:3];
7389
 
7390
// first stage is multiplier based
7391
// shift operand as fractional 8.7
7392
assign s1[15] = sll & s[2:0]==3'd7;
7393
assign s1[14] = sll & s[2:0]==3'd6;
7394
assign s1[13] = sll & s[2:0]==3'd5;
7395
assign s1[12] = sll & s[2:0]==3'd4;
7396
assign s1[11] = sll & s[2:0]==3'd3;
7397
assign s1[10] = sll & s[2:0]==3'd2;
7398
assign s1[ 9] = sll & s[2:0]==3'd1;
7399
assign s1[ 8] = s[2:0]==3'd0;
7400
assign s1[ 7] = !sll & s[2:0]==3'd1;
7401
assign s1[ 6] = !sll & s[2:0]==3'd2;
7402
assign s1[ 5] = !sll & s[2:0]==3'd3;
7403
assign s1[ 4] = !sll & s[2:0]==3'd4;
7404
assign s1[ 3] = !sll & s[2:0]==3'd5;
7405
assign s1[ 2] = !sll & s[2:0]==3'd6;
7406
assign s1[ 1] = !sll & s[2:0]==3'd7;
7407
 
7408
assign sign[3] = din[31] & sra;
7409
assign sign[2] = sign[3] & (&din[31:24]);
7410
assign sign[1] = sign[2] & (&din[23:16]);
7411
assign sign[0] = sign[1] & (&din[15:8]);
7412 40 unneback
`define MODULE mults
7413
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte3 ( .a({sign[3], {8{sign[3]}},din[31:24], din[23:16]}), .b({1'b0,s1}), .p(tmp[3]));
7414
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte2 ( .a({sign[2], din[31:24]  ,din[23:16],  din[15:8]}), .b({1'b0,s1}), .p(tmp[2]));
7415
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte1 ( .a({sign[1], din[23:16]  ,din[15:8],   din[7:0]}), .b({1'b0,s1}), .p(tmp[1]));
7416
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte0 ( .a({sign[0], din[15:8]   ,din[7:0],    8'h00}),      .b({1'b0,s1}), .p(tmp[0]));
7417
`undef MODULE
7418 18 unneback
// second stage is multiplexer based
7419
// shift on byte level
7420
 
7421
// mux byte 3
7422
assign dout[31:24] = (s[4:3]==2'b00) ? tmp[3] :
7423
                     (sll & s[4:3]==2'b01) ? tmp[2] :
7424
                     (sll & s[4:3]==2'b10) ? tmp[1] :
7425
                     (sll & s[4:3]==2'b11) ? tmp[0] :
7426
                     {8{sign[3]}};
7427
 
7428
// mux byte 2
7429
assign dout[23:16] = (s[4:3]==2'b00) ? tmp[2] :
7430
                     (sll & s[4:3]==2'b01) ? tmp[1] :
7431
                     (sll & s[4:3]==2'b10) ? tmp[0] :
7432
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
7433
                     (s[4:3]==2'b01) ? tmp[3] :
7434
                     {8{sign[3]}};
7435
 
7436
// mux byte 1
7437
assign dout[15:8]  = (s[4:3]==2'b00) ? tmp[1] :
7438
                     (sll & s[4:3]==2'b01) ? tmp[0] :
7439
                     (sll & s[4:3]==2'b10) ? {8{1'b0}} :
7440
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
7441
                     (s[4:3]==2'b01) ? tmp[2] :
7442
                     (s[4:3]==2'b10) ? tmp[3] :
7443
                     {8{sign[3]}};
7444
 
7445
// mux byte 0
7446
assign dout[7:0]   = (s[4:3]==2'b00) ? tmp[0] :
7447
                     (sll) ?  {8{1'b0}}:
7448
                     (s[4:3]==2'b01) ? tmp[1] :
7449
                     (s[4:3]==2'b10) ? tmp[2] :
7450
                     tmp[3];
7451
 
7452
endmodule
7453 40 unneback
`endif
7454 18 unneback
 
7455 40 unneback
`ifdef LOGIC_UNIT
7456 18 unneback
// logic unit
7457
// supporting the following logic functions
7458
//    a and b
7459
//    a or  b
7460
//    a xor b
7461
//    not b
7462 40 unneback
`define MODULE logic_unit
7463
module `BASE`MODULE( a, b, result, opcode);
7464
`undef MODULE
7465 18 unneback
parameter width = 32;
7466
parameter opcode_and = 2'b00;
7467
parameter opcode_or  = 2'b01;
7468
parameter opcode_xor = 2'b10;
7469
input [width-1:0] a,b;
7470
output [width-1:0] result;
7471
input [1:0] opcode;
7472
 
7473
assign result = (opcode==opcode_and) ? a & b :
7474
                (opcode==opcode_or)  ? a | b :
7475
                (opcode==opcode_xor) ? a ^ b :
7476
                b;
7477
 
7478
endmodule
7479 48 unneback
`endif
7480 18 unneback
 
7481 48 unneback
`ifdef ARITH_UNIT
7482
`define MODULE arith_unit
7483
module `BASE`MODULE ( a, b, c_in, add_sub, sign, result, c_out, z, ovfl);
7484
`undef MODULE
7485 18 unneback
parameter width = 32;
7486
parameter opcode_add = 1'b0;
7487
parameter opcode_sub = 1'b1;
7488
input [width-1:0] a,b;
7489
input c_in, add_sub, sign;
7490
output [width-1:0] result;
7491
output c_out, z, ovfl;
7492
 
7493
assign {c_out,result} = {(a[width-1] & sign),a} + ({a[width-1] & sign,b} ^ {(width+1){(add_sub==opcode_sub)}}) + {{(width-1){1'b0}},(c_in | (add_sub==opcode_sub))};
7494
assign z = (result=={width{1'b0}});
7495
assign ovfl = ( a[width-1] &  b[width-1] & ~result[width-1]) |
7496
               (~a[width-1] & ~b[width-1] &  result[width-1]);
7497
endmodule
7498 40 unneback
`endif
7499 48 unneback
 
7500
`ifdef COUNT_UNIT
7501
`define MODULE count_unit
7502
module `BASE`MODULE (din, dout, opcode);
7503
`undef MODULE
7504
parameter width = 32;
7505
input [width-1:0] din;
7506
output [width-1:0] dout;
7507
input opcode;
7508
 
7509
integer i;
7510 58 unneback
wire [width/32+4:0] ff1, fl1;
7511 48 unneback
 
7512 57 unneback
/*
7513 48 unneback
always @(din) begin
7514
    ff1 = 0; i = 0;
7515
    while (din[i] == 0 && i < width) begin // complex condition
7516
        ff1 = ff1 + 1;
7517
        i = i + 1;
7518
    end
7519
end
7520
 
7521
always @(din) begin
7522
    fl1 = width; i = width-1;
7523
    while (din[i] == 0 && i >= width) begin // complex condition
7524
        fl1 = fl1 - 1;
7525
        i = i - 1;
7526
    end
7527
end
7528 57 unneback
*/
7529 48 unneback
 
7530
generate
7531
if (width==32) begin
7532 57 unneback
 
7533
    assign ff1 = din[0] ? 6'd1 :
7534
                 din[1] ? 6'd2 :
7535
                 din[2] ? 6'd3 :
7536
                 din[3] ? 6'd4 :
7537
                 din[4] ? 6'd5 :
7538
                 din[5] ? 6'd6 :
7539
                 din[6] ? 6'd7 :
7540
                 din[7] ? 6'd8 :
7541
                 din[8] ? 6'd9 :
7542
                 din[9] ? 6'd10 :
7543
                 din[10] ? 6'd11 :
7544
                 din[11] ? 6'd12 :
7545
                 din[12] ? 6'd13 :
7546
                 din[13] ? 6'd14 :
7547
                 din[14] ? 6'd15 :
7548
                 din[15] ? 6'd16 :
7549
                 din[16] ? 6'd17 :
7550
                 din[17] ? 6'd18 :
7551
                 din[18] ? 6'd19 :
7552
                 din[19] ? 6'd20 :
7553
                 din[20] ? 6'd21 :
7554
                 din[21] ? 6'd22 :
7555
                 din[22] ? 6'd23 :
7556
                 din[23] ? 6'd24 :
7557
                 din[24] ? 6'd25 :
7558
                 din[25] ? 6'd26 :
7559
                 din[26] ? 6'd27 :
7560
                 din[27] ? 6'd28 :
7561
                 din[28] ? 6'd29 :
7562
                 din[29] ? 6'd30 :
7563
                 din[30] ? 6'd31 :
7564
                 din[31] ? 6'd32 :
7565
                 6'd0;
7566
 
7567
    assign fl1 = din[31] ? 6'd32 :
7568
                 din[30] ? 6'd31 :
7569
                 din[29] ? 6'd30 :
7570
                 din[28] ? 6'd29 :
7571
                 din[27] ? 6'd28 :
7572
                 din[26] ? 6'd27 :
7573
                 din[25] ? 6'd26 :
7574
                 din[24] ? 6'd25 :
7575
                 din[23] ? 6'd24 :
7576
                 din[22] ? 6'd23 :
7577
                 din[21] ? 6'd22 :
7578
                 din[20] ? 6'd21 :
7579
                 din[19] ? 6'd20 :
7580
                 din[18] ? 6'd19 :
7581
                 din[17] ? 6'd18 :
7582
                 din[16] ? 6'd17 :
7583
                 din[15] ? 6'd16 :
7584
                 din[14] ? 6'd15 :
7585
                 din[13] ? 6'd14 :
7586
                 din[12] ? 6'd13 :
7587
                 din[11] ? 6'd12 :
7588
                 din[10] ? 6'd11 :
7589
                 din[9] ? 6'd10 :
7590
                 din[8] ? 6'd9 :
7591
                 din[7] ? 6'd8 :
7592
                 din[6] ? 6'd7 :
7593
                 din[5] ? 6'd6 :
7594
                 din[4] ? 6'd5 :
7595
                 din[3] ? 6'd4 :
7596
                 din[2] ? 6'd3 :
7597
                 din[1] ? 6'd2 :
7598
                 din[0] ? 6'd1 :
7599
                 6'd0;
7600
 
7601
    assign dout = (!opcode) ? {{26{1'b0}}, ff1} : {{26{1'b0}}, fl1};
7602 48 unneback
end
7603
endgenerate
7604 57 unneback
 
7605 48 unneback
generate
7606
if (width==64) begin
7607 57 unneback
    assign ff1 = 7'd0;
7608
    assign fl1 = 7'd0;
7609
    assign dout = (!opcode) ? {{57{1'b0}}, ff1} : {{57{1'b0}}, fl1};
7610 48 unneback
end
7611
endgenerate
7612
 
7613
endmodule
7614
`endif
7615
 
7616
`ifdef EXT_UNIT
7617
`define MODULE ext_unit
7618
module `BASE`MODULE ( a, b, F, result, opcode);
7619
`undef MODULE
7620
parameter width = 32;
7621
input [width-1:0] a, b;
7622
input F;
7623
output reg [width-1:0] result;
7624
input [2:0] opcode;
7625
 
7626
generate
7627
if (width==32) begin
7628
always @ (a or b or F or opcode)
7629
begin
7630
    case (opcode)
7631
    3'b000: result = {{24{1'b0}},a[7:0]};
7632
    3'b001: result = {{24{a[7]}},a[7:0]};
7633
    3'b010: result = {{16{1'b0}},a[7:0]};
7634
    3'b011: result = {{16{a[15]}},a[15:0]};
7635
    3'b110: result = (F) ? a : b;
7636
    default: result = {b[15:0],16'h0000};
7637
    endcase
7638
end
7639
end
7640
endgenerate
7641
 
7642
generate
7643
if (width==64) begin
7644
always @ (a or b or F or opcode)
7645
begin
7646
    case (opcode)
7647
    3'b000: result = {{56{1'b0}},a[7:0]};
7648
    3'b001: result = {{56{a[7]}},a[7:0]};
7649
    3'b010: result = {{48{1'b0}},a[7:0]};
7650
    3'b011: result = {{48{a[15]}},a[15:0]};
7651 57 unneback
    3'b110: result = (F) ? a : b;
7652 48 unneback
    default: result = {32'h00000000,b[15:0],16'h0000};
7653
    endcase
7654
end
7655
end
7656
endgenerate
7657
endmodule
7658
`endif

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