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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Blame information for rev 141

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Line No. Rev Author Line
1 40 unneback
`ifndef BASE
2
`define BASE vl_
3
`endif
4
 
5 60 unneback
// default SYN_KEEP definition
6
`define SYN_KEEP /*synthesis syn_keep = 1*/
7
 
8 44 unneback
`ifdef ACTEL
9 60 unneback
`undef SYN_KEEP
10 44 unneback
`define SYN_KEEP /*synthesis syn_keep = 1*/
11
`endif
12
 
13 98 unneback
`ifdef ACTEL
14
    // ACTEL FPGA should not use logic to handle rw collision
15
    `define SYN_NO_RW_CHECK /*synthesis syn_ramstyle = "no_rw_check"*/
16
`else
17
    `define SYN_NO_RW_CHECK
18
`endif
19
 
20 40 unneback
`ifdef ALL
21
 
22
`define GBUF
23
`define SYNC_RST
24
`define PLL
25
 
26
`define MULTS
27
`define MULTS18X18
28
`define MULT
29 140 unneback
`define ARITH_UNIT
30 40 unneback
`define SHIFT_UNIT_32
31
`define LOGIC_UNIT
32 140 unneback
`define COUNT_UNIT
33
`define EXT_UNIT
34 40 unneback
 
35
`define CNT_SHREG_WRAP
36
`define CNT_SHREG_CE_WRAP
37 105 unneback
`define CNT_SHREG_CLEAR
38 40 unneback
`define CNT_SHREG_CE_CLEAR
39
`define CNT_SHREG_CE_CLEAR_WRAP
40
 
41 139 unneback
`define CNT_BIN
42
`define CNT_BIN_CE
43
`define CNT_BIN_CLEAR
44
`define CNT_BIN_CE_CLEAR
45
`define CNT_BIN_CE_CLEAR_L1_L2
46
`define CNT_BIN_CE_CLEAR_SET_REW
47
`define CNT_BIN_CE_REW_L1
48
`define CNT_BIN_CE_REW_ZQ_L1
49
`define CNT_BIN_CE_REW_Q_ZQ_L1
50
`define CNT_GRAY
51
`define CNT_GRAY_CE
52
`define CNT_GRAY_CE_BIN
53
`define CNT_LFSR_ZQ
54
`define CNT_LFSR_CE
55
`define CNT_LFSR_CE_CLEAR_Q
56
`define CNT_LFSR_CE_Q
57
`define CNT_LFSR_CE_ZQ
58
`define CNT_LFSR_CE_Q_ZQ
59
`define CNT_LFSR_CE_REW_L1
60
 
61 40 unneback
`define MUX_ANDOR
62
`define MUX2_ANDOR
63
`define MUX3_ANDOR
64
`define MUX4_ANDOR
65
`define MUX5_ANDOR
66
`define MUX6_ANDOR
67 43 unneback
`define PARITY
68 40 unneback
 
69
`define ROM_INIT
70
`define RAM
71
`define RAM_BE
72
`define DPRAM_1R1W
73
`define DPRAM_2R1W
74 100 unneback
`define DPRAM_1R2W
75 40 unneback
`define DPRAM_2R2W
76 75 unneback
`define DPRAM_BE_2R2W
77 40 unneback
`define FIFO_1R1W_FILL_LEVEL_SYNC
78
`define FIFO_2R2W_SYNC_SIMPLEX
79
`define FIFO_CMP_ASYNC
80
`define FIFO_1R1W_ASYNC
81
`define FIFO_2R2W_ASYNC
82
`define FIFO_2R2W_ASYNC_SIMPLEX
83 48 unneback
`define REG_FILE
84 40 unneback
 
85
`define DFF
86
`define DFF_ARRAY
87
`define DFF_CE
88
`define DFF_CE_CLEAR
89
`define DF_CE_SET
90
`define SPR
91
`define SRP
92
`define DFF_SR
93
`define LATCH
94
`define SHREG
95
`define SHREG_CE
96
`define DELAY
97
`define DELAY_EMPTYFLAG
98 94 unneback
`define PULSE2TOGGLE
99
`define TOGGLE2PULSE
100
`define SYNCHRONIZER
101
`define CDC
102 40 unneback
 
103 75 unneback
`define WB3AVALON_BRIDGE
104 40 unneback
`define WB3WB3_BRIDGE
105
`define WB3_ARBITER_TYPE1
106 83 unneback
`define WB_ADR_INC
107 101 unneback
`define WB_RAM
108 103 unneback
`define WB_SHADOW_RAM
109 48 unneback
`define WB_B4_ROM
110 40 unneback
`define WB_BOOT_ROM
111
`define WB_DPRAM
112 101 unneback
`define WB_CACHE
113 103 unneback
`define WB_AVALON_BRIDGE
114
`define WB_AVALON_MEM_CACHE
115 136 unneback
`define WB_SDR_SDRAM_CTRL
116 40 unneback
 
117 44 unneback
`define IO_DFF_OE
118
`define O_DFF
119 136 unneback
`define O_DDR
120
`define O_CLK
121 44 unneback
 
122 40 unneback
`endif
123
 
124 136 unneback
///////////////////////////////////////
125
// dependencies
126
///////////////////////////////////////
127
 
128 40 unneback
`ifdef PLL
129
`ifndef SYNC_RST
130
`define SYNC_RST
131
`endif
132
`endif
133
 
134
`ifdef SYNC_RST
135
`ifndef GBUF
136
`define GBUF
137
`endif
138
`endif
139
 
140 136 unneback
`ifdef WB_SDR_SDRAM_CTRL
141
`ifndef WB_SHADOW_RAM
142
`define WB_SHADOW_RAM
143
`endif
144
`ifndef WB_CACHE
145
`define WB_CACHE
146
`endif
147
`ifndef WB_SDR_SDRAM
148
`define WB_SDR_SDRAM
149
`endif
150
`ifndef IO_DFF_OE
151
`define IO_DFF_OE
152
`endif
153
`ifndef O_DFF
154
`define O_DFF
155
`endif
156
`ifndef O_CLK
157
`define O_CLK
158
`endif
159
`endif
160
 
161
`ifdef WB_SDR_SDRAM
162
`ifndef CNT_SHREG_CLEAR
163
`define CNT_SHREG_CLEAR
164
`endif
165
`ifndef CNT_LFSR_ZQ
166
`define CNT_LFSR_ZQ
167
`endif
168
`ifndef DELAY_EMPTYFLAG
169
`define DELAY_EMPTYFLAG
170
`endif
171
`endif
172
 
173 108 unneback
`ifdef WB_DPRAM
174 92 unneback
`ifndef WB_ADR_INC
175
`define WB_ADR_INC
176 40 unneback
`endif
177 141 unneback
`ifndef DFF
178
`define DFF
179
`endif
180 92 unneback
`ifndef DPRAM_BE_2R2W
181
`define DPRAM_BE_2R2W
182 40 unneback
`endif
183
`endif
184
 
185
`ifdef WB3_ARBITER_TYPE1
186 42 unneback
`ifndef SPR
187
`define SPR
188
`endif
189 40 unneback
`ifndef MUX_ANDOR
190
`define MUX_ANDOR
191
`endif
192
`endif
193
 
194 76 unneback
`ifdef WB3AVALON_BRIDGE
195
`ifndef WB3WB3_BRIDGE
196
`define WB3WB3_BRIDGE
197
`endif
198
`endif
199
 
200 40 unneback
`ifdef WB3WB3_BRIDGE
201
`ifndef CNT_SHREG_CE_CLEAR
202
`define CNT_SHREG_CE_CLEAR
203
`endif
204
`ifndef DFF
205
`define DFF
206
`endif
207
`ifndef DFF_CE
208
`define DFF_CE
209
`endif
210
`ifndef CNT_SHREG_CE_CLEAR
211
`define CNT_SHREG_CE_CLEAR
212
`endif
213
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
214
`define FIFO_2R2W_ASYNC_SIMPLEX
215
`endif
216
`endif
217
 
218 103 unneback
 
219
`ifdef WB_AVALON_MEM_CACHE
220
`ifndef WB_SHADOW_RAM
221
`define WB_SHADOW_RAM
222
`endif
223
`ifndef WB_CACHE
224
`define WB_CACHE
225
`endif
226
`ifndef WB_AVALON_BRIDGE
227
`define WB_AVALON_BRIDGE
228
`endif
229
`endif
230
 
231 101 unneback
`ifdef WB_CACHE
232 100 unneback
`ifndef RAM
233
`define RAM
234
`endif
235
`ifndef WB_ADR_INC
236
`define WB_ADR_INC
237
`endif
238
`ifndef DPRAM_1R1W
239
`define DPRAM_1R1W
240
`endif
241
`ifndef DPRAM_1R2W
242
`define DPRAM_1R2W
243
`endif
244
`ifndef DPRAM_BE_2R2W
245
`define DPRAM_BE_2R2W
246
`endif
247
`ifndef CDC
248
`define CDC
249
`endif
250 136 unneback
`ifndef O_DFF
251
`define O_DFF
252 100 unneback
`endif
253 136 unneback
`ifndef O_CLK
254
`define O_CLK
255
`endif
256
`endif
257 103 unneback
 
258
`ifdef WB_SHADOW_RAM
259 115 unneback
`ifndef WB_RAM
260
`define WB_RAM
261 103 unneback
`endif
262
`endif
263
 
264
`ifdef WB_RAM
265
`ifndef WB_ADR_INC
266
`define WB_ADR_INC
267
`endif
268 114 unneback
`ifndef RAM_BE
269
`define RAM_BE
270 103 unneback
`endif
271 114 unneback
`endif
272
 
273 40 unneback
`ifdef MULTS18X18
274
`ifndef MULTS
275
`define MULTS
276
`endif
277
`endif
278
 
279
`ifdef SHIFT_UNIT_32
280
`ifndef MULTS
281
`define MULTS
282
`endif
283
`endif
284
 
285
`ifdef MUX2_ANDOR
286
`ifndef MUX_ANDOR
287
`define MUX_ANDOR
288
`endif
289
`endif
290
 
291
`ifdef MUX3_ANDOR
292
`ifndef MUX_ANDOR
293
`define MUX_ANDOR
294
`endif
295
`endif
296
 
297
`ifdef MUX4_ANDOR
298
`ifndef MUX_ANDOR
299
`define MUX_ANDOR
300
`endif
301
`endif
302
 
303
`ifdef MUX5_ANDOR
304
`ifndef MUX_ANDOR
305
`define MUX_ANDOR
306
`endif
307
`endif
308
 
309
`ifdef MUX6_ANDOR
310
`ifndef MUX_ANDOR
311
`define MUX_ANDOR
312
`endif
313
`endif
314
 
315
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
316
`ifndef CNT_BIN_CE
317
`define CNT_BIN_CE
318
`endif
319
`ifndef DPRAM_1R1W
320
`define DPRAM_1R1W
321
`endif
322
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
323
`define CNT_BIN_CE_REW_Q_ZQ_L1
324
`endif
325
`endif
326
 
327
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
328
`ifndef CNT_LFSR_CE
329
`define CNT_LFSR_CE
330
`endif
331
`ifndef DPRAM_2R2W
332
`define DPRAM_2R2W
333
`endif
334
`ifndef CNT_BIN_CE_REW_ZQ_L1
335
`define CNT_BIN_CE_REW_ZQ_L1
336
`endif
337
`endif
338
 
339
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
340
`ifndef CNT_GRAY_CE_BIN
341
`define CNT_GRAY_CE_BIN
342
`endif
343
`ifndef DPRAM_2R2W
344
`define DPRAM_2R2W
345
`endif
346
`ifndef FIFO_CMP_ASYNC
347
`define FIFO_CMP_ASYNC
348
`endif
349
`endif
350
 
351
`ifdef FIFO_2R2W_ASYNC
352
`ifndef FIFO_1R1W_ASYNC
353
`define FIFO_1R1W_ASYNC
354
`endif
355
`endif
356
 
357
`ifdef FIFO_1R1W_ASYNC
358
`ifndef CNT_GRAY_CE_BIN
359
`define CNT_GRAY_CE_BIN
360
`endif
361
`ifndef DPRAM_1R1W
362
`define DPRAM_1R1W
363
`endif
364
`ifndef FIFO_CMP_ASYNC
365
`define FIFO_CMP_ASYNC
366
`endif
367
`endif
368
 
369
`ifdef FIFO_CMP_ASYNC
370
`ifndef DFF_SR
371
`define DFF_SR
372
`endif
373
`ifndef DFF
374
`define DFF
375
`endif
376
`endif
377 48 unneback
 
378
`ifdef REG_FILE
379
`ifndef DPRAM_1R1W
380
`define DPRAM_1R1W
381
`endif
382
`endif
383 97 unneback
 
384 98 unneback
`ifdef CDC
385
`ifndef PULSE2TOGGLE
386
`define PULSE2TOGGLE
387
`endif
388
`ifndef TOGGLE2PULSE
389
`define TOGGLE2PULSE
390
`endif
391
`ifndef SYNCHRONIZER
392
`define SYNCHRONIZER
393
`endif
394
`endif
395
 
396 136 unneback
`ifdef O_CLK
397
`ifndef O_DDR
398
`define O_DDR
399
`endif
400
`endif
401
 
402 97 unneback
// size to width
403 100 unneback
`define SIZE2WIDTH_EXPR = (`SIZE2WIDTH==1) ? 0 : (`SIZE2WIDTH==2) ? 1 : (`SIZE2WIDTH==4) ? 2 : (`SIZE2WIDTH==8) ? 3 : (`SIZE2WIDTH==16) ? 4 : (`SIZE2WIDTH==32) ? 5 : (`SIZE2WIDTH==64) ? 6 : (`SIZE2WIDTH==128) ? 7 : 8;
404 62 unneback
//////////////////////////////////////////////////////////////////////
405 6 unneback
////                                                              ////
406
////  Versatile library, clock and reset                          ////
407
////                                                              ////
408
////  Description                                                 ////
409
////  Logic related to clock and reset                            ////
410
////                                                              ////
411
////                                                              ////
412
////  To Do:                                                      ////
413
////   - add more different registers                             ////
414
////                                                              ////
415
////  Author(s):                                                  ////
416
////      - Michael Unneback, unneback@opencores.org              ////
417
////        ORSoC AB                                              ////
418
////                                                              ////
419
//////////////////////////////////////////////////////////////////////
420
////                                                              ////
421
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
422
////                                                              ////
423
//// This source file may be used and distributed without         ////
424
//// restriction provided that this copyright statement is not    ////
425
//// removed from the file and that any derivative work contains  ////
426
//// the original copyright notice and the associated disclaimer. ////
427
////                                                              ////
428
//// This source file is free software; you can redistribute it   ////
429
//// and/or modify it under the terms of the GNU Lesser General   ////
430
//// Public License as published by the Free Software Foundation; ////
431
//// either version 2.1 of the License, or (at your option) any   ////
432
//// later version.                                               ////
433
////                                                              ////
434
//// This source is distributed in the hope that it will be       ////
435
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
436
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
437
//// PURPOSE.  See the GNU Lesser General Public License for more ////
438
//// details.                                                     ////
439
////                                                              ////
440
//// You should have received a copy of the GNU Lesser General    ////
441
//// Public License along with this source; if not, download it   ////
442
//// from http://www.opencores.org/lgpl.shtml                     ////
443
////                                                              ////
444
//////////////////////////////////////////////////////////////////////
445
 
446 48 unneback
`ifdef ACTEL
447
`ifdef GBUF
448
`timescale 1 ns/100 ps
449 6 unneback
// Global buffer
450
// usage:
451
// use to enable global buffers for high fan out signals such as clock and reset
452
// Version: 8.4 8.4.0.33
453
module gbuf(GL,CLK);
454
output GL;
455
input  CLK;
456
 
457
    wire GND;
458
 
459
    GND GND_1_net(.Y(GND));
460
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
461
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
462
 
463
endmodule
464
`timescale 1 ns/1 ns
465 40 unneback
`define MODULE gbuf
466
module `BASE`MODULE ( i, o);
467
`undef MODULE
468 6 unneback
input i;
469
output o;
470
`ifdef SIM_GBUF
471
assign o=i;
472
`else
473
gbuf gbuf_i0 ( .CLK(i), .GL(o));
474
`endif
475
endmodule
476 40 unneback
`endif
477 33 unneback
 
478 6 unneback
`else
479 33 unneback
 
480 40 unneback
`ifdef ALTERA
481
`ifdef GBUF
482 21 unneback
//altera
483 40 unneback
`define MODULE gbuf
484
module `BASE`MODULE ( i, o);
485
`undef MODULE
486 33 unneback
input i;
487
output o;
488
assign o = i;
489
endmodule
490 40 unneback
`endif
491 33 unneback
 
492 6 unneback
`else
493
 
494 40 unneback
`ifdef GBUF
495 6 unneback
`timescale 1 ns/100 ps
496 40 unneback
`define MODULE
497
module `BASE`MODULE ( i, o);
498
`undef MODULE
499 6 unneback
input i;
500
output o;
501
assign o = i;
502
endmodule
503 40 unneback
`endif
504 6 unneback
`endif // ALTERA
505
`endif //ACTEL
506
 
507 40 unneback
`ifdef SYNC_RST
508 6 unneback
// sync reset
509 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
510 6 unneback
// output active high global reset sync with two DFFs 
511
`timescale 1 ns/100 ps
512 40 unneback
`define MODULE sync_rst
513
module `BASE`MODULE ( rst_n_i, rst_o, clk);
514
`undef MODULE
515 6 unneback
input rst_n_i, clk;
516
output rst_o;
517 18 unneback
reg [1:0] tmp;
518 6 unneback
always @ (posedge clk or negedge rst_n_i)
519
if (!rst_n_i)
520 17 unneback
        tmp <= 2'b11;
521 6 unneback
else
522 33 unneback
        tmp <= {1'b0,tmp[1]};
523 40 unneback
`define MODULE gbuf
524
`BASE`MODULE buf_i0( .i(tmp[0]), .o(rst_o));
525
`undef MODULE
526 6 unneback
endmodule
527 40 unneback
`endif
528 6 unneback
 
529 40 unneback
`ifdef PLL
530 6 unneback
// vl_pll
531
`ifdef ACTEL
532 32 unneback
///////////////////////////////////////////////////////////////////////////////
533 17 unneback
`timescale 1 ps/1 ps
534 40 unneback
`define MODULE pll
535
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
536
`undef MODULE
537 6 unneback
parameter index = 0;
538
parameter number_of_clk = 1;
539 17 unneback
parameter period_time_0 = 20000;
540
parameter period_time_1 = 20000;
541
parameter period_time_2 = 20000;
542
parameter lock_delay = 2000000;
543 6 unneback
input clk_i, rst_n_i;
544
output lock;
545
output reg [0:number_of_clk-1] clk_o;
546
output [0:number_of_clk-1] rst_o;
547
 
548
`ifdef SIM_PLL
549
 
550
always
551
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
552
 
553
generate if (number_of_clk > 1)
554
always
555
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
556
endgenerate
557
 
558
generate if (number_of_clk > 2)
559
always
560
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
561
endgenerate
562
 
563
genvar i;
564
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
565
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
566
end
567
endgenerate
568
 
569
assign #lock_delay lock = rst_n_i;
570
 
571
endmodule
572
`else
573
generate if (number_of_clk==1 & index==0) begin
574
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
575
end
576
endgenerate // index==0
577
generate if (number_of_clk==1 & index==1) begin
578
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
579
end
580
endgenerate // index==1
581
generate if (number_of_clk==1 & index==2) begin
582
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
583
end
584
endgenerate // index==2
585
generate if (number_of_clk==1 & index==3) begin
586
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
587
end
588
endgenerate // index==0
589
 
590
generate if (number_of_clk==2 & index==0) begin
591
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
592
end
593
endgenerate // index==0
594
generate if (number_of_clk==2 & index==1) begin
595
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
596
end
597
endgenerate // index==1
598
generate if (number_of_clk==2 & index==2) begin
599
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
600
end
601
endgenerate // index==2
602
generate if (number_of_clk==2 & index==3) begin
603
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
604
end
605
endgenerate // index==0
606
 
607
generate if (number_of_clk==3 & index==0) begin
608
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
609
end
610
endgenerate // index==0
611
generate if (number_of_clk==3 & index==1) begin
612
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
613
end
614
endgenerate // index==1
615
generate if (number_of_clk==3 & index==2) begin
616
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
617
end
618
endgenerate // index==2
619
generate if (number_of_clk==3 & index==3) begin
620
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
621
end
622
endgenerate // index==0
623
 
624
genvar i;
625
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
626 40 unneback
`define MODULE sync_rst
627
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
628
`undef MODULE
629 6 unneback
end
630
endgenerate
631
endmodule
632
`endif
633 32 unneback
///////////////////////////////////////////////////////////////////////////////
634 6 unneback
 
635
`else
636
 
637 32 unneback
///////////////////////////////////////////////////////////////////////////////
638 6 unneback
`ifdef ALTERA
639
 
640 32 unneback
`timescale 1 ps/1 ps
641 40 unneback
`define MODULE pll
642
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
643
`undef MODULE
644 32 unneback
parameter index = 0;
645
parameter number_of_clk = 1;
646
parameter period_time_0 = 20000;
647
parameter period_time_1 = 20000;
648
parameter period_time_2 = 20000;
649
parameter period_time_3 = 20000;
650
parameter period_time_4 = 20000;
651
parameter lock_delay = 2000000;
652
input clk_i, rst_n_i;
653
output lock;
654
output reg [0:number_of_clk-1] clk_o;
655
output [0:number_of_clk-1] rst_o;
656
 
657
`ifdef SIM_PLL
658
 
659
always
660
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
661
 
662
generate if (number_of_clk > 1)
663
always
664
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
665
endgenerate
666
 
667
generate if (number_of_clk > 2)
668
always
669
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
670
endgenerate
671
 
672 33 unneback
generate if (number_of_clk > 3)
673 32 unneback
always
674
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
675
endgenerate
676
 
677 33 unneback
generate if (number_of_clk > 4)
678 32 unneback
always
679
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
680
endgenerate
681
 
682
genvar i;
683
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
684
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
685
end
686
endgenerate
687
 
688 33 unneback
//assign #lock_delay lock = rst_n_i;
689
assign lock = rst_n_i;
690 32 unneback
 
691
endmodule
692 6 unneback
`else
693
 
694 33 unneback
`ifdef VL_PLL0
695
`ifdef VL_PLL0_CLK1
696
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
697
`endif
698
`ifdef VL_PLL0_CLK2
699
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
700
`endif
701
`ifdef VL_PLL0_CLK3
702
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
703
`endif
704
`ifdef VL_PLL0_CLK4
705
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
706
`endif
707
`ifdef VL_PLL0_CLK5
708
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
709
`endif
710
`endif
711 32 unneback
 
712 33 unneback
`ifdef VL_PLL1
713
`ifdef VL_PLL1_CLK1
714
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
715
`endif
716
`ifdef VL_PLL1_CLK2
717
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
718
`endif
719
`ifdef VL_PLL1_CLK3
720
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
721
`endif
722
`ifdef VL_PLL1_CLK4
723
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
724
`endif
725
`ifdef VL_PLL1_CLK5
726
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
727
`endif
728
`endif
729 32 unneback
 
730 33 unneback
`ifdef VL_PLL2
731
`ifdef VL_PLL2_CLK1
732
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
733
`endif
734
`ifdef VL_PLL2_CLK2
735
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
736
`endif
737
`ifdef VL_PLL2_CLK3
738
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
739
`endif
740
`ifdef VL_PLL2_CLK4
741
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
742
`endif
743
`ifdef VL_PLL2_CLK5
744
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
745
`endif
746
`endif
747 32 unneback
 
748 33 unneback
`ifdef VL_PLL3
749
`ifdef VL_PLL3_CLK1
750
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
751
`endif
752
`ifdef VL_PLL3_CLK2
753
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
754
`endif
755
`ifdef VL_PLL3_CLK3
756
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
757
`endif
758
`ifdef VL_PLL3_CLK4
759
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
760
`endif
761
`ifdef VL_PLL3_CLK5
762
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
763
`endif
764
`endif
765 32 unneback
 
766
genvar i;
767
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
768 40 unneback
`define MODULE sync_rst
769
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
770
`undef MODULE
771 32 unneback
end
772
endgenerate
773
endmodule
774
`endif
775
///////////////////////////////////////////////////////////////////////////////
776
 
777
`else
778
 
779 6 unneback
// generic PLL
780 17 unneback
`timescale 1 ps/1 ps
781 40 unneback
`define MODULE pll
782
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
783
`undef MODULE
784 6 unneback
parameter index = 0;
785
parameter number_of_clk = 1;
786 140 unneback
parameter period_time = 20000;
787
parameter clk0_mult_by = 1;
788
parameter clk0_div_by  = 1;
789
parameter clk1_mult_by = 1;
790
parameter clk1_div_by  = 1;
791
parameter clk2_mult_by = 1;
792
parameter clk3_div_by  = 1;
793
parameter clk3_mult_by = 1;
794
parameter clk3_div_by  = 1;
795
parameter clk4_mult_by = 1;
796
parameter clk4_div_by  = 1;
797 6 unneback
input clk_i, rst_n_i;
798
output lock;
799
output reg [0:number_of_clk-1] clk_o;
800
 
801 140 unneback
initial
802
    clk_o = {number_of_clk{1'b0}};
803
 
804 6 unneback
always
805 140 unneback
    #((period_time*clk0_div_by/clk0_mult_by)/2) clk_o[0] <=  (!rst_n_i) ? 1'b0 : ~clk_o[0];
806 6 unneback
 
807
generate if (number_of_clk > 1)
808
always
809 140 unneback
    #((period_time*clk1_div_by/clk1_mult_by)/2) clk_o[1] <=  (!rst_n_i) ? 1'b0 : ~clk_o[1];
810 6 unneback
endgenerate
811
 
812
generate if (number_of_clk > 2)
813
always
814 140 unneback
    #((period_time*clk2_div_by/clk2_mult_by)/2) clk_o[2] <=  (!rst_n_i) ? 1'b0 : ~clk_o[2];
815 6 unneback
endgenerate
816
 
817 140 unneback
generate if (number_of_clk > 3)
818
always
819
    #((period_time*clk3_div_by/clk3_mult_by)/2) clk_o[3] <=  (!rst_n_i) ? 1'b0 : ~clk_o[3];
820 6 unneback
endgenerate
821
 
822 140 unneback
generate if (number_of_clk > 4)
823
always
824
    #((period_time*clk4_div_by/clk4_mult_by)/2) clk_o[4] <=  (!rst_n_i) ? 1'b0 : ~clk_o[4];
825
endgenerate
826
 
827 6 unneback
assign #lock_delay lock = rst_n_i;
828
 
829
endmodule
830
 
831
`endif //altera
832 17 unneback
`endif //actel
833 40 unneback
`undef MODULE
834
`endif//////////////////////////////////////////////////////////////////////
835 6 unneback
////                                                              ////
836
////  Versatile library, registers                                ////
837
////                                                              ////
838
////  Description                                                 ////
839
////  Different type of registers                                 ////
840
////                                                              ////
841
////                                                              ////
842
////  To Do:                                                      ////
843
////   - add more different registers                             ////
844
////                                                              ////
845
////  Author(s):                                                  ////
846
////      - Michael Unneback, unneback@opencores.org              ////
847
////        ORSoC AB                                              ////
848
////                                                              ////
849
//////////////////////////////////////////////////////////////////////
850
////                                                              ////
851
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
852
////                                                              ////
853
//// This source file may be used and distributed without         ////
854
//// restriction provided that this copyright statement is not    ////
855
//// removed from the file and that any derivative work contains  ////
856
//// the original copyright notice and the associated disclaimer. ////
857
////                                                              ////
858
//// This source file is free software; you can redistribute it   ////
859
//// and/or modify it under the terms of the GNU Lesser General   ////
860
//// Public License as published by the Free Software Foundation; ////
861
//// either version 2.1 of the License, or (at your option) any   ////
862
//// later version.                                               ////
863
////                                                              ////
864
//// This source is distributed in the hope that it will be       ////
865
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
866
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
867
//// PURPOSE.  See the GNU Lesser General Public License for more ////
868
//// details.                                                     ////
869
////                                                              ////
870
//// You should have received a copy of the GNU Lesser General    ////
871
//// Public License along with this source; if not, download it   ////
872
//// from http://www.opencores.org/lgpl.shtml                     ////
873
////                                                              ////
874
//////////////////////////////////////////////////////////////////////
875
 
876 40 unneback
`ifdef DFF
877
`define MODULE dff
878
module `BASE`MODULE ( d, q, clk, rst);
879
`undef MODULE
880 6 unneback
        parameter width = 1;
881 139 unneback
        parameter reset_value = {width{1'b0}};
882 6 unneback
 
883
        input [width-1:0] d;
884
        input clk, rst;
885
        output reg [width-1:0] q;
886
 
887
        always @ (posedge clk or posedge rst)
888
        if (rst)
889
                q <= reset_value;
890
        else
891
                q <= d;
892
 
893
endmodule
894 40 unneback
`endif
895 6 unneback
 
896 40 unneback
`ifdef DFF_ARRAY
897
`define MODULE dff_array
898
module `BASE`MODULE ( d, q, clk, rst);
899
`undef MODULE
900 6 unneback
 
901
        parameter width = 1;
902
        parameter depth = 2;
903
        parameter reset_value = 1'b0;
904
 
905
        input [width-1:0] d;
906
        input clk, rst;
907
        output [width-1:0] q;
908
        reg  [0:depth-1] q_tmp [width-1:0];
909
        integer i;
910
        always @ (posedge clk or posedge rst)
911
        if (rst) begin
912
            for (i=0;i<depth;i=i+1)
913
                q_tmp[i] <= {width{reset_value}};
914
        end else begin
915
            q_tmp[0] <= d;
916
            for (i=1;i<depth;i=i+1)
917
                q_tmp[i] <= q_tmp[i-1];
918
        end
919
 
920
    assign q = q_tmp[depth-1];
921
 
922
endmodule
923 40 unneback
`endif
924 6 unneback
 
925 40 unneback
`ifdef DFF_CE
926
`define MODULE dff_ce
927
module `BASE`MODULE ( d, ce, q, clk, rst);
928
`undef MODULE
929 6 unneback
 
930
        parameter width = 1;
931 139 unneback
        parameter reset_value = {width{1'b0}};
932 6 unneback
 
933
        input [width-1:0] d;
934
        input ce, clk, rst;
935
        output reg [width-1:0] q;
936
 
937
        always @ (posedge clk or posedge rst)
938
        if (rst)
939
                q <= reset_value;
940
        else
941
                if (ce)
942
                        q <= d;
943
 
944
endmodule
945 40 unneback
`endif
946 6 unneback
 
947 40 unneback
`ifdef DFF_CE_CLEAR
948
`define MODULE dff_ce_clear
949
module `BASE`MODULE ( d, ce, clear, q, clk, rst);
950
`undef MODULE
951 8 unneback
 
952
        parameter width = 1;
953 139 unneback
        parameter reset_value = {width{1'b0}};
954 8 unneback
 
955
        input [width-1:0] d;
956 10 unneback
        input ce, clear, clk, rst;
957 8 unneback
        output reg [width-1:0] q;
958
 
959
        always @ (posedge clk or posedge rst)
960
        if (rst)
961
            q <= reset_value;
962
        else
963
            if (ce)
964
                if (clear)
965
                    q <= {width{1'b0}};
966
                else
967
                    q <= d;
968
 
969
endmodule
970 40 unneback
`endif
971 8 unneback
 
972 40 unneback
`ifdef DF_CE_SET
973
`define MODULE dff_ce_set
974
module `BASE`MODULE ( d, ce, set, q, clk, rst);
975
`undef MODULE
976 24 unneback
 
977
        parameter width = 1;
978 139 unneback
        parameter reset_value = {width{1'b0}};
979 24 unneback
 
980
        input [width-1:0] d;
981
        input ce, set, clk, rst;
982
        output reg [width-1:0] q;
983
 
984
        always @ (posedge clk or posedge rst)
985
        if (rst)
986
            q <= reset_value;
987
        else
988
            if (ce)
989
                if (set)
990
                    q <= {width{1'b1}};
991
                else
992
                    q <= d;
993
 
994
endmodule
995 40 unneback
`endif
996 24 unneback
 
997 40 unneback
`ifdef SPR
998
`define MODULE spr
999
module `BASE`MODULE ( sp, r, q, clk, rst);
1000
`undef MODULE
1001
 
1002 64 unneback
        //parameter width = 1;
1003
        parameter reset_value = 1'b0;
1004 29 unneback
 
1005
        input sp, r;
1006
        output reg q;
1007
        input clk, rst;
1008
 
1009
        always @ (posedge clk or posedge rst)
1010
        if (rst)
1011
            q <= reset_value;
1012
        else
1013
            if (sp)
1014
                q <= 1'b1;
1015
            else if (r)
1016
                q <= 1'b0;
1017
 
1018
endmodule
1019 40 unneback
`endif
1020 29 unneback
 
1021 40 unneback
`ifdef SRP
1022
`define MODULE srp
1023
module `BASE`MODULE ( s, rp, q, clk, rst);
1024
`undef MODULE
1025
 
1026 29 unneback
        parameter width = 1;
1027
        parameter reset_value = 0;
1028
 
1029
        input s, rp;
1030
        output reg q;
1031
        input clk, rst;
1032
 
1033
        always @ (posedge clk or posedge rst)
1034
        if (rst)
1035
            q <= reset_value;
1036
        else
1037
            if (rp)
1038
                q <= 1'b0;
1039
            else if (s)
1040
                q <= 1'b1;
1041
 
1042
endmodule
1043 40 unneback
`endif
1044 29 unneback
 
1045 40 unneback
`ifdef ALTERA
1046 29 unneback
 
1047 40 unneback
`ifdef DFF_SR
1048 6 unneback
// megafunction wizard: %LPM_FF%
1049
// GENERATION: STANDARD
1050
// VERSION: WM1.0
1051
// MODULE: lpm_ff 
1052
 
1053
// ============================================================
1054
// File Name: dff_sr.v
1055
// Megafunction Name(s):
1056
//                      lpm_ff
1057
//
1058
// Simulation Library Files(s):
1059
//                      lpm
1060
// ============================================================
1061
// ************************************************************
1062
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
1063
//
1064
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
1065
// ************************************************************
1066
 
1067
 
1068
//Copyright (C) 1991-2010 Altera Corporation
1069
//Your use of Altera Corporation's design tools, logic functions 
1070
//and other software and tools, and its AMPP partner logic 
1071
//functions, and any output files from any of the foregoing 
1072
//(including device programming or simulation files), and any 
1073
//associated documentation or information are expressly subject 
1074
//to the terms and conditions of the Altera Program License 
1075
//Subscription Agreement, Altera MegaCore Function License 
1076
//Agreement, or other applicable license agreement, including, 
1077
//without limitation, that your use is for the sole purpose of 
1078
//programming logic devices manufactured by Altera and sold by 
1079
//Altera or its authorized distributors.  Please refer to the 
1080
//applicable agreement for further details.
1081
 
1082
 
1083
// synopsys translate_off
1084
`timescale 1 ps / 1 ps
1085
// synopsys translate_on
1086 40 unneback
`define MODULE dff_sr
1087
module `BASE`MODULE (
1088
`undef MODULE
1089
 
1090 6 unneback
        aclr,
1091
        aset,
1092
        clock,
1093
        data,
1094
        q);
1095
 
1096
        input     aclr;
1097
        input     aset;
1098
        input     clock;
1099
        input     data;
1100
        output    q;
1101
 
1102
        wire [0:0] sub_wire0;
1103
        wire [0:0] sub_wire1 = sub_wire0[0:0];
1104
        wire  q = sub_wire1;
1105
        wire  sub_wire2 = data;
1106
        wire  sub_wire3 = sub_wire2;
1107
 
1108
        lpm_ff  lpm_ff_component (
1109
                                .aclr (aclr),
1110
                                .clock (clock),
1111
                                .data (sub_wire3),
1112
                                .aset (aset),
1113
                                .q (sub_wire0)
1114
                                // synopsys translate_off
1115
                                ,
1116
                                .aload (),
1117
                                .enable (),
1118
                                .sclr (),
1119
                                .sload (),
1120
                                .sset ()
1121
                                // synopsys translate_on
1122
                                );
1123
        defparam
1124
                lpm_ff_component.lpm_fftype = "DFF",
1125
                lpm_ff_component.lpm_type = "LPM_FF",
1126
                lpm_ff_component.lpm_width = 1;
1127
 
1128
 
1129
endmodule
1130
 
1131
// ============================================================
1132
// CNX file retrieval info
1133
// ============================================================
1134
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
1135
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
1136
// Retrieval info: PRIVATE: ASET NUMERIC "1"
1137
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
1138
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
1139
// Retrieval info: PRIVATE: DFF NUMERIC "1"
1140
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
1141
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
1142
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
1143
// Retrieval info: PRIVATE: SSET NUMERIC "0"
1144
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
1145
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
1146
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
1147
// Retrieval info: PRIVATE: nBit NUMERIC "1"
1148
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
1149
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
1150
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
1151
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
1152
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
1153
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
1154
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
1155
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
1156
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
1157
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
1158
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
1159
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
1160
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
1161
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
1162
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
1163
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
1164
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
1165
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
1166
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
1167
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
1168
// Retrieval info: LIB_FILE: lpm
1169 40 unneback
`endif
1170 6 unneback
 
1171
`else
1172
 
1173 40 unneback
`ifdef DFF_SR
1174
`define MODULE dff_sr
1175
module `BASE`MODULE ( aclr, aset, clock, data, q);
1176
`undef MODULE
1177 6 unneback
 
1178
    input         aclr;
1179
    input         aset;
1180
    input         clock;
1181
    input         data;
1182
    output reg    q;
1183
 
1184
   always @ (posedge clock or posedge aclr or posedge aset)
1185
     if (aclr)
1186
       q <= 1'b0;
1187
     else if (aset)
1188
       q <= 1'b1;
1189
     else
1190
       q <= data;
1191
 
1192
endmodule
1193 40 unneback
`endif
1194 6 unneback
 
1195
`endif
1196
 
1197
// LATCH
1198
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
1199
`ifdef ALTERA
1200 40 unneback
 
1201
`ifdef LATCH
1202
`define MODULE latch
1203
module `BASE`MODULE ( d, le, q, clk);
1204
`undef MODULE
1205 6 unneback
input d, le;
1206
output q;
1207
input clk;
1208
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
1209
endmodule
1210 40 unneback
`endif
1211
 
1212 6 unneback
`else
1213 40 unneback
 
1214
`ifdef LATCH
1215
`define MODULE latch
1216
module `BASE`MODULE ( d, le, q, clk);
1217
`undef MODULE
1218 6 unneback
input d, le;
1219 48 unneback
input clk;
1220
always @ (le or d)
1221 60 unneback
if (le)
1222 48 unneback
    d <= q;
1223 6 unneback
endmodule
1224 15 unneback
`endif
1225
 
1226 40 unneback
`endif
1227
 
1228
`ifdef SHREG
1229
`define MODULE shreg
1230
module `BASE`MODULE ( d, q, clk, rst);
1231
`undef MODULE
1232
 
1233 17 unneback
parameter depth = 10;
1234
input d;
1235
output q;
1236
input clk, rst;
1237
 
1238
reg [1:depth] dffs;
1239
 
1240
always @ (posedge clk or posedge rst)
1241
if (rst)
1242
    dffs <= {depth{1'b0}};
1243
else
1244
    dffs <= {d,dffs[1:depth-1]};
1245
assign q = dffs[depth];
1246
endmodule
1247 40 unneback
`endif
1248 17 unneback
 
1249 40 unneback
`ifdef SHREG_CE
1250
`define MODULE shreg_ce
1251
module `BASE`MODULE ( d, ce, q, clk, rst);
1252
`undef MODULE
1253 17 unneback
parameter depth = 10;
1254
input d, ce;
1255
output q;
1256
input clk, rst;
1257
 
1258
reg [1:depth] dffs;
1259
 
1260
always @ (posedge clk or posedge rst)
1261
if (rst)
1262
    dffs <= {depth{1'b0}};
1263
else
1264
    if (ce)
1265
        dffs <= {d,dffs[1:depth-1]};
1266
assign q = dffs[depth];
1267
endmodule
1268 40 unneback
`endif
1269 17 unneback
 
1270 40 unneback
`ifdef DELAY
1271
`define MODULE delay
1272
module `BASE`MODULE ( d, q, clk, rst);
1273
`undef MODULE
1274 15 unneback
parameter depth = 10;
1275
input d;
1276
output q;
1277
input clk, rst;
1278
 
1279
reg [1:depth] dffs;
1280
 
1281
always @ (posedge clk or posedge rst)
1282
if (rst)
1283
    dffs <= {depth{1'b0}};
1284
else
1285
    dffs <= {d,dffs[1:depth-1]};
1286
assign q = dffs[depth];
1287 17 unneback
endmodule
1288 40 unneback
`endif
1289 17 unneback
 
1290 40 unneback
`ifdef DELAY_EMPTYFLAG
1291
`define MODULE delay_emptyflag
1292 41 unneback
module `BASE`MODULE ( d, q, emptyflag, clk, rst);
1293 40 unneback
`undef MODULE
1294 17 unneback
parameter depth = 10;
1295
input d;
1296
output q, emptyflag;
1297
input clk, rst;
1298
 
1299
reg [1:depth] dffs;
1300
 
1301
always @ (posedge clk or posedge rst)
1302
if (rst)
1303
    dffs <= {depth{1'b0}};
1304
else
1305
    dffs <= {d,dffs[1:depth-1]};
1306
assign q = dffs[depth];
1307
assign emptyflag = !(|dffs);
1308
endmodule
1309 40 unneback
`endif
1310 75 unneback
 
1311 94 unneback
`ifdef PULSE2TOGGLE
1312 98 unneback
`define MODULE pulse2toggle
1313
module `BASE`MODULE ( pl, q, clk, rst);
1314 75 unneback
`undef MODULE
1315 94 unneback
input pl;
1316 98 unneback
output reg q;
1317 94 unneback
input clk, rst;
1318
always @ (posedge clk or posedge rst)
1319 75 unneback
if (rst)
1320 94 unneback
    q <= 1'b0;
1321 75 unneback
else
1322 94 unneback
    q <= pl ^ q;
1323
endmodule
1324
`endif
1325 75 unneback
 
1326 94 unneback
`ifdef TOGGLE2PULSE
1327 98 unneback
`define MODULE toggle2pulse
1328 94 unneback
module `BASE`MODULE (d, pl, clk, rst);
1329 97 unneback
`undef MODULE
1330 94 unneback
input d;
1331
output pl;
1332
input clk, rst;
1333
reg dff;
1334
always @ (posedge clk or posedge rst)
1335
if (rst)
1336
    dff <= 1'b0;
1337 75 unneback
else
1338 94 unneback
    dff <= d;
1339 98 unneback
assign pl = d ^ dff;
1340 94 unneback
endmodule
1341
`endif
1342 75 unneback
 
1343 94 unneback
`ifdef SYNCHRONIZER
1344
`define MODULE synchronizer
1345
module `BASE`MODULE (d, q, clk, rst);
1346
`undef MODULE
1347
input d;
1348
output reg q;
1349 116 unneback
input clk, rst;
1350 94 unneback
reg dff;
1351
always @ (posedge clk or posedge rst)
1352
if (rst)
1353 100 unneback
    {q,dff} <= 2'b00;
1354 75 unneback
else
1355 100 unneback
    {q,dff} <= {dff,d};
1356 94 unneback
endmodule
1357
`endif
1358 75 unneback
 
1359 94 unneback
`ifdef CDC
1360
`define MODULE cdc
1361 97 unneback
module `BASE`MODULE ( start_pl, take_it_pl, take_it_grant_pl, got_it_pl, clk_src, rst_src, clk_dst, rst_dst);
1362 94 unneback
`undef MODULE
1363
input start_pl;
1364
output take_it_pl;
1365
input take_it_grant_pl; // note: connect to take_it_pl to generate automatic ack
1366
output got_it_pl;
1367
input clk_src, rst_src;
1368
input clk_dst, rst_dst;
1369
wire take_it_tg, take_it_tg_sync;
1370
wire got_it_tg, got_it_tg_sync;
1371
// src -> dst
1372
`define MODULE pulse2toggle
1373
`BASE`MODULE p2t0 (
1374
`undef MODULE
1375
    .pl(start_pl),
1376
    .q(take_it_tg),
1377
    .clk(clk_src),
1378
    .rst(rst_src));
1379 75 unneback
 
1380 94 unneback
`define MODULE synchronizer
1381
`BASE`MODULE sync0 (
1382
`undef MODULE
1383
    .d(take_it_tg),
1384
    .q(take_it_tg_sync),
1385
    .clk(clk_dst),
1386
    .rst(rst_dst));
1387
 
1388
`define MODULE toggle2pulse
1389
`BASE`MODULE t2p0 (
1390
`undef MODULE
1391 100 unneback
    .d(take_it_tg_sync),
1392 94 unneback
    .pl(take_it_pl),
1393
    .clk(clk_dst),
1394
    .rst(rst_dst));
1395
 
1396
// dst -> src
1397
`define MODULE pulse2toggle
1398 98 unneback
`BASE`MODULE p2t1 (
1399 94 unneback
`undef MODULE
1400
    .pl(take_it_grant_pl),
1401
    .q(got_it_tg),
1402
    .clk(clk_dst),
1403
    .rst(rst_dst));
1404
 
1405
`define MODULE synchronizer
1406
`BASE`MODULE sync1 (
1407
`undef MODULE
1408
    .d(got_it_tg),
1409
    .q(got_it_tg_sync),
1410
    .clk(clk_src),
1411
    .rst(rst_src));
1412
 
1413
`define MODULE toggle2pulse
1414
`BASE`MODULE t2p1 (
1415
`undef MODULE
1416 100 unneback
    .d(got_it_tg_sync),
1417 94 unneback
    .pl(got_it_pl),
1418
    .clk(clk_src),
1419
    .rst(rst_src));
1420
 
1421 75 unneback
endmodule
1422
`endif
1423 17 unneback
//////////////////////////////////////////////////////////////////////
1424 6 unneback
////                                                              ////
1425 18 unneback
////  Logic functions                                             ////
1426
////                                                              ////
1427
////  Description                                                 ////
1428
////  Logic functions such as multiplexers                        ////
1429
////                                                              ////
1430
////                                                              ////
1431
////  To Do:                                                      ////
1432
////   -                                                          ////
1433
////                                                              ////
1434
////  Author(s):                                                  ////
1435
////      - Michael Unneback, unneback@opencores.org              ////
1436
////        ORSoC AB                                              ////
1437
////                                                              ////
1438
//////////////////////////////////////////////////////////////////////
1439
////                                                              ////
1440
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1441
////                                                              ////
1442
//// This source file may be used and distributed without         ////
1443
//// restriction provided that this copyright statement is not    ////
1444
//// removed from the file and that any derivative work contains  ////
1445
//// the original copyright notice and the associated disclaimer. ////
1446
////                                                              ////
1447
//// This source file is free software; you can redistribute it   ////
1448
//// and/or modify it under the terms of the GNU Lesser General   ////
1449
//// Public License as published by the Free Software Foundation; ////
1450
//// either version 2.1 of the License, or (at your option) any   ////
1451
//// later version.                                               ////
1452
////                                                              ////
1453
//// This source is distributed in the hope that it will be       ////
1454
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1455
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1456
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1457
//// details.                                                     ////
1458
////                                                              ////
1459
//// You should have received a copy of the GNU Lesser General    ////
1460
//// Public License along with this source; if not, download it   ////
1461
//// from http://www.opencores.org/lgpl.shtml                     ////
1462
////                                                              ////
1463
//////////////////////////////////////////////////////////////////////
1464 40 unneback
`ifdef MUX_ANDOR
1465
`define MODULE mux_andor
1466
module `BASE`MODULE ( a, sel, dout);
1467
`undef MODULE
1468 36 unneback
 
1469
parameter width = 32;
1470
parameter nr_of_ports = 4;
1471
 
1472
input [nr_of_ports*width-1:0] a;
1473
input [nr_of_ports-1:0] sel;
1474
output reg [width-1:0] dout;
1475
 
1476 38 unneback
integer i,j;
1477
 
1478 36 unneback
always @ (a, sel)
1479
begin
1480
    dout = a[width-1:0] & {width{sel[0]}};
1481 42 unneback
    for (i=1;i<nr_of_ports;i=i+1)
1482
        for (j=0;j<width;j=j+1)
1483
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
1484 36 unneback
end
1485
 
1486
endmodule
1487 40 unneback
`endif
1488 36 unneback
 
1489 40 unneback
`ifdef MUX2_ANDOR
1490
`define MODULE mux2_andor
1491
module `BASE`MODULE ( a1, a0, sel, dout);
1492
`undef MODULE
1493 18 unneback
 
1494 34 unneback
parameter width = 32;
1495 35 unneback
localparam nr_of_ports = 2;
1496 34 unneback
input [width-1:0] a1, a0;
1497
input [nr_of_ports-1:0] sel;
1498
output [width-1:0] dout;
1499
 
1500 40 unneback
`define MODULE mux_andor
1501
`BASE`MODULE
1502 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1503 36 unneback
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
1504 40 unneback
`undef MODULE
1505
 
1506 34 unneback
endmodule
1507 40 unneback
`endif
1508 34 unneback
 
1509 40 unneback
`ifdef MUX3_ANDOR
1510
`define MODULE mux3_andor
1511
module `BASE`MODULE ( a2, a1, a0, sel, dout);
1512
`undef MODULE
1513 34 unneback
 
1514
parameter width = 32;
1515 35 unneback
localparam nr_of_ports = 3;
1516 34 unneback
input [width-1:0] a2, a1, a0;
1517
input [nr_of_ports-1:0] sel;
1518
output [width-1:0] dout;
1519
 
1520 40 unneback
`define MODULE mux_andor
1521
`BASE`MODULE
1522 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1523 36 unneback
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
1524 40 unneback
`undef MODULE
1525 34 unneback
endmodule
1526 40 unneback
`endif
1527 34 unneback
 
1528 40 unneback
`ifdef MUX4_ANDOR
1529
`define MODULE mux4_andor
1530
module `BASE`MODULE ( a3, a2, a1, a0, sel, dout);
1531
`undef MODULE
1532 18 unneback
 
1533
parameter width = 32;
1534 35 unneback
localparam nr_of_ports = 4;
1535 18 unneback
input [width-1:0] a3, a2, a1, a0;
1536
input [nr_of_ports-1:0] sel;
1537 22 unneback
output [width-1:0] dout;
1538 18 unneback
 
1539 40 unneback
`define MODULE mux_andor
1540
`BASE`MODULE
1541 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1542 36 unneback
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
1543 40 unneback
`undef MODULE
1544 18 unneback
 
1545
endmodule
1546 40 unneback
`endif
1547 18 unneback
 
1548 40 unneback
`ifdef MUX5_ANDOR
1549
`define MODULE mux5_andor
1550
module `BASE`MODULE ( a4, a3, a2, a1, a0, sel, dout);
1551
`undef MODULE
1552 18 unneback
 
1553
parameter width = 32;
1554 35 unneback
localparam nr_of_ports = 5;
1555 18 unneback
input [width-1:0] a4, a3, a2, a1, a0;
1556
input [nr_of_ports-1:0] sel;
1557 22 unneback
output [width-1:0] dout;
1558 18 unneback
 
1559 40 unneback
`define MODULE mux_andor
1560
`BASE`MODULE
1561 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1562 36 unneback
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1563 40 unneback
`undef MODULE
1564 18 unneback
 
1565
endmodule
1566 40 unneback
`endif
1567 18 unneback
 
1568 40 unneback
`ifdef MUX6_ANDOR
1569
`define MODULE mux6_andor
1570
module `BASE`MODULE ( a5, a4, a3, a2, a1, a0, sel, dout);
1571
`undef MODULE
1572 18 unneback
 
1573
parameter width = 32;
1574 35 unneback
localparam nr_of_ports = 6;
1575 18 unneback
input [width-1:0] a5, a4, a3, a2, a1, a0;
1576
input [nr_of_ports-1:0] sel;
1577 22 unneback
output [width-1:0] dout;
1578 18 unneback
 
1579 40 unneback
`define MODULE mux_andor
1580
`BASE`MODULE
1581 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1582 36 unneback
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1583 40 unneback
`undef MODULE
1584 18 unneback
 
1585
endmodule
1586 40 unneback
`endif
1587 43 unneback
 
1588
`ifdef PARITY
1589
 
1590
`define MODULE parity_generate
1591
module `BASE`MODULE (data, parity);
1592
`undef MODULE
1593
parameter word_size = 32;
1594
parameter chunk_size = 8;
1595
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1596
input [word_size-1:0] data;
1597
output reg [word_size/chunk_size-1:0] parity;
1598
integer i,j;
1599
always @ (data)
1600
for (i=0;i<word_size/chunk_size;i=i+1) begin
1601
    parity[i] = parity_type;
1602
    for (j=0;j<chunk_size;j=j+1) begin
1603 46 unneback
        parity[i] = data[i*chunk_size+j] ^ parity[i];
1604 43 unneback
    end
1605
end
1606
endmodule
1607
 
1608
`define MODULE parity_check
1609
module `BASE`MODULE( data, parity, parity_error);
1610
`undef MODULE
1611
parameter word_size = 32;
1612
parameter chunk_size = 8;
1613
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1614
input [word_size-1:0] data;
1615
input [word_size/chunk_size-1:0] parity;
1616
output parity_error;
1617 44 unneback
reg [word_size/chunk_size-1:0] error_flag;
1618 43 unneback
integer i,j;
1619
always @ (data or parity)
1620
for (i=0;i<word_size/chunk_size;i=i+1) begin
1621
    error_flag[i] = parity[i] ^ parity_type;
1622
    for (j=0;j<chunk_size;j=j+1) begin
1623 46 unneback
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
1624 43 unneback
    end
1625
end
1626
assign parity_error = |error_flag;
1627
endmodule
1628
 
1629 44 unneback
`endif//////////////////////////////////////////////////////////////////////
1630
////                                                              ////
1631
////  IO functions                                                ////
1632
////                                                              ////
1633
////  Description                                                 ////
1634
////  IO functions such as IOB flip-flops                         ////
1635
////                                                              ////
1636
////                                                              ////
1637
////  To Do:                                                      ////
1638
////   -                                                          ////
1639
////                                                              ////
1640
////  Author(s):                                                  ////
1641
////      - Michael Unneback, unneback@opencores.org              ////
1642
////        ORSoC AB                                              ////
1643
////                                                              ////
1644 18 unneback
//////////////////////////////////////////////////////////////////////
1645
////                                                              ////
1646 44 unneback
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1647
////                                                              ////
1648
//// This source file may be used and distributed without         ////
1649
//// restriction provided that this copyright statement is not    ////
1650
//// removed from the file and that any derivative work contains  ////
1651
//// the original copyright notice and the associated disclaimer. ////
1652
////                                                              ////
1653
//// This source file is free software; you can redistribute it   ////
1654
//// and/or modify it under the terms of the GNU Lesser General   ////
1655
//// Public License as published by the Free Software Foundation; ////
1656
//// either version 2.1 of the License, or (at your option) any   ////
1657
//// later version.                                               ////
1658
////                                                              ////
1659
//// This source is distributed in the hope that it will be       ////
1660
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1661
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1662
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1663
//// details.                                                     ////
1664
////                                                              ////
1665
//// You should have received a copy of the GNU Lesser General    ////
1666
//// Public License along with this source; if not, download it   ////
1667
//// from http://www.opencores.org/lgpl.shtml                     ////
1668
////                                                              ////
1669
//////////////////////////////////////////////////////////////////////
1670 136 unneback
`ifdef O_DFF
1671 45 unneback
`timescale 1ns/1ns
1672 44 unneback
`define MODULE o_dff
1673
module `BASE`MODULE (d_i, o_pad, clk, rst);
1674
`undef MODULE
1675
parameter width = 1;
1676 45 unneback
parameter reset_value = {width{1'b0}};
1677
input  [width-1:0]  d_i;
1678 44 unneback
output [width-1:0] o_pad;
1679
input clk, rst;
1680
wire [width-1:0] d_i_int `SYN_KEEP;
1681 45 unneback
reg  [width-1:0] o_pad_int;
1682 44 unneback
assign d_i_int = d_i;
1683
genvar i;
1684 45 unneback
generate
1685 136 unneback
for (i=0;i<width;i=i+1) begin : dffs
1686 44 unneback
    always @ (posedge clk or posedge rst)
1687
    if (rst)
1688 45 unneback
        o_pad_int[i] <= reset_value[i];
1689 44 unneback
    else
1690 45 unneback
        o_pad_int[i] <= d_i_int[i];
1691
    assign #1 o_pad[i] = o_pad_int[i];
1692 44 unneback
end
1693
endgenerate
1694
endmodule
1695
`endif
1696
 
1697 136 unneback
`ifdef IO_DFF_OE
1698 45 unneback
`timescale 1ns/1ns
1699 44 unneback
`define MODULE io_dff_oe
1700
module `BASE`MODULE ( d_i, d_o, oe, io_pad, clk, rst);
1701
`undef MODULE
1702
parameter width = 1;
1703 140 unneback
parameter reset_value = 1'b0;
1704 44 unneback
input  [width-1:0] d_o;
1705
output reg [width-1:0] d_i;
1706
input oe;
1707
inout [width-1:0] io_pad;
1708
input clk, rst;
1709
wire [width-1:0] oe_d `SYN_KEEP;
1710
reg [width-1:0] oe_q;
1711
reg [width-1:0] d_o_q;
1712
assign oe_d = {width{oe}};
1713
genvar i;
1714
generate
1715 136 unneback
for (i=0;i<width;i=i+1) begin : dffs
1716 44 unneback
    always @ (posedge clk or posedge rst)
1717
    if (rst)
1718
        oe_q[i] <= 1'b0;
1719
    else
1720
        oe_q[i] <= oe_d[i];
1721
    always @ (posedge clk or posedge rst)
1722
    if (rst)
1723 140 unneback
        d_o_q[i] <= reset_value;
1724 44 unneback
    else
1725
        d_o_q[i] <= d_o[i];
1726
    always @ (posedge clk or posedge rst)
1727
    if (rst)
1728 140 unneback
        d_i[i] <= reset_value;
1729 44 unneback
    else
1730
        d_i[i] <= io_pad[i];
1731 45 unneback
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
1732 44 unneback
end
1733
endgenerate
1734
endmodule
1735
`endif
1736 136 unneback
 
1737
`ifdef O_DDR
1738
`ifdef ALTERA
1739
`define MODULE o_ddr
1740
module `BASE`MODULE (d_h_i, d_l_i, o_pad, clk, rst);
1741
`undef MODULE
1742
parameter width = 1;
1743
input  [width-1:0] d_h_i, d_l_i;
1744
output [width-1:0] o_pad;
1745
input clk, rst;
1746
genvar i;
1747
generate
1748
for (i=0;i<width;i=i+1) begin : ddr
1749
    ddio_out ddio_out0( .aclr(rst), .datain_h(d_h_i[i]), .datain_l(d_l_i[i]), .outclock(clk), .dataout(o_pad[i]) );
1750
end
1751
endgenerate
1752
endmodule
1753
`else
1754
`define MODULE o_ddr
1755
module `BASE`MODULE (d_h_i, d_l_i, o_pad, clk, rst);
1756
`undef MODULE
1757
parameter width = 1;
1758
input  [width-1:0] d_h_i, d_l_i;
1759
output [width-1:0] o_pad;
1760
input clk, rst;
1761
reg [width-1:0] ff1;
1762
reg [width-1:0] ff2;
1763
genvar i;
1764
generate
1765
for (i=0;i<width;i=i+1) begin : ddr
1766
    always @ (posedge clk or posedge rst)
1767
    if (rst)
1768
        ff1[i] <= 1'b0;
1769
    else
1770
        ff1[i] <= d_h_i[i];
1771
    always @ (posedge clk or posedge rst)
1772
    if (rst)
1773
        ff2[i] <= 1'b0;
1774
    else
1775
        ff2[i] <= d_l_i[i];
1776
    assign o_pad = (clk) ? ff1 : ff2;
1777
end
1778
endgenerate
1779
endmodule
1780
`endif
1781
`endif
1782
 
1783
`ifdef O_CLK
1784
`define MODULE o_clk
1785
module `BASE`MODULE ( clk_o_pad, clk, rst);
1786
`undef MODULE
1787
input clk, rst;
1788
output clk_o_pad;
1789
`define MODULE o_ddr
1790
`BASE`MODULE o_ddr0( .d_h_i(1'b1), .d_l_i(1'b0), .o_pad(clk_o_pad), .clk(clk), .rst(rst));
1791
`undef MODULE
1792
endmodule
1793
`endif`ifdef CNT_BIN
1794 44 unneback
//////////////////////////////////////////////////////////////////////
1795
////                                                              ////
1796 6 unneback
////  Versatile counter                                           ////
1797
////                                                              ////
1798
////  Description                                                 ////
1799
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1800
////  counter                                                     ////
1801
////                                                              ////
1802
////  To Do:                                                      ////
1803
////   - add LFSR with more taps                                  ////
1804
////                                                              ////
1805
////  Author(s):                                                  ////
1806
////      - Michael Unneback, unneback@opencores.org              ////
1807
////        ORSoC AB                                              ////
1808
////                                                              ////
1809
//////////////////////////////////////////////////////////////////////
1810
////                                                              ////
1811
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1812
////                                                              ////
1813
//// This source file may be used and distributed without         ////
1814
//// restriction provided that this copyright statement is not    ////
1815
//// removed from the file and that any derivative work contains  ////
1816
//// the original copyright notice and the associated disclaimer. ////
1817
////                                                              ////
1818
//// This source file is free software; you can redistribute it   ////
1819
//// and/or modify it under the terms of the GNU Lesser General   ////
1820
//// Public License as published by the Free Software Foundation; ////
1821
//// either version 2.1 of the License, or (at your option) any   ////
1822
//// later version.                                               ////
1823
////                                                              ////
1824
//// This source is distributed in the hope that it will be       ////
1825
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1826
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1827
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1828
//// details.                                                     ////
1829
////                                                              ////
1830
//// You should have received a copy of the GNU Lesser General    ////
1831
//// Public License along with this source; if not, download it   ////
1832
//// from http://www.opencores.org/lgpl.shtml                     ////
1833
////                                                              ////
1834
//////////////////////////////////////////////////////////////////////
1835
 
1836
// binary counter
1837 22 unneback
 
1838 40 unneback
`define MODULE cnt_bin
1839
module `BASE`MODULE (
1840
`undef MODULE
1841
 q, rst, clk);
1842
 
1843 22 unneback
   parameter length = 4;
1844
   output [length:1] q;
1845
   input rst;
1846
   input clk;
1847
 
1848
   parameter clear_value = 0;
1849
   parameter set_value = 1;
1850
   parameter wrap_value = 0;
1851
   parameter level1_value = 15;
1852
 
1853
   reg  [length:1] qi;
1854
   wire [length:1] q_next;
1855
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1856
 
1857
   always @ (posedge clk or posedge rst)
1858
     if (rst)
1859
       qi <= {length{1'b0}};
1860
     else
1861
       qi <= q_next;
1862
 
1863
   assign q = qi;
1864
 
1865
endmodule
1866 40 unneback
`endif
1867
`ifdef CNT_BIN_CLEAR
1868 22 unneback
//////////////////////////////////////////////////////////////////////
1869
////                                                              ////
1870
////  Versatile counter                                           ////
1871
////                                                              ////
1872
////  Description                                                 ////
1873
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1874
////  counter                                                     ////
1875
////                                                              ////
1876
////  To Do:                                                      ////
1877
////   - add LFSR with more taps                                  ////
1878
////                                                              ////
1879
////  Author(s):                                                  ////
1880
////      - Michael Unneback, unneback@opencores.org              ////
1881
////        ORSoC AB                                              ////
1882
////                                                              ////
1883
//////////////////////////////////////////////////////////////////////
1884
////                                                              ////
1885
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1886
////                                                              ////
1887
//// This source file may be used and distributed without         ////
1888
//// restriction provided that this copyright statement is not    ////
1889
//// removed from the file and that any derivative work contains  ////
1890
//// the original copyright notice and the associated disclaimer. ////
1891
////                                                              ////
1892
//// This source file is free software; you can redistribute it   ////
1893
//// and/or modify it under the terms of the GNU Lesser General   ////
1894
//// Public License as published by the Free Software Foundation; ////
1895
//// either version 2.1 of the License, or (at your option) any   ////
1896
//// later version.                                               ////
1897
////                                                              ////
1898
//// This source is distributed in the hope that it will be       ////
1899
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1900
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1901
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1902
//// details.                                                     ////
1903
////                                                              ////
1904
//// You should have received a copy of the GNU Lesser General    ////
1905
//// Public License along with this source; if not, download it   ////
1906
//// from http://www.opencores.org/lgpl.shtml                     ////
1907
////                                                              ////
1908
//////////////////////////////////////////////////////////////////////
1909
 
1910
// binary counter
1911
 
1912 40 unneback
`define MODULE cnt_bin_clear
1913
module `BASE`MODULE (
1914
`undef MODULE
1915
 clear, q, rst, clk);
1916
 
1917 22 unneback
   parameter length = 4;
1918
   input clear;
1919
   output [length:1] q;
1920
   input rst;
1921
   input clk;
1922
 
1923
   parameter clear_value = 0;
1924
   parameter set_value = 1;
1925
   parameter wrap_value = 0;
1926
   parameter level1_value = 15;
1927
 
1928
   reg  [length:1] qi;
1929
   wire [length:1] q_next;
1930
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1931
 
1932
   always @ (posedge clk or posedge rst)
1933
     if (rst)
1934
       qi <= {length{1'b0}};
1935
     else
1936
       qi <= q_next;
1937
 
1938
   assign q = qi;
1939
 
1940
endmodule
1941 40 unneback
`endif
1942
`ifdef CNT_BIN_CE
1943 22 unneback
//////////////////////////////////////////////////////////////////////
1944
////                                                              ////
1945
////  Versatile counter                                           ////
1946
////                                                              ////
1947
////  Description                                                 ////
1948
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1949
////  counter                                                     ////
1950
////                                                              ////
1951
////  To Do:                                                      ////
1952
////   - add LFSR with more taps                                  ////
1953
////                                                              ////
1954
////  Author(s):                                                  ////
1955
////      - Michael Unneback, unneback@opencores.org              ////
1956
////        ORSoC AB                                              ////
1957
////                                                              ////
1958
//////////////////////////////////////////////////////////////////////
1959
////                                                              ////
1960
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1961
////                                                              ////
1962
//// This source file may be used and distributed without         ////
1963
//// restriction provided that this copyright statement is not    ////
1964
//// removed from the file and that any derivative work contains  ////
1965
//// the original copyright notice and the associated disclaimer. ////
1966
////                                                              ////
1967
//// This source file is free software; you can redistribute it   ////
1968
//// and/or modify it under the terms of the GNU Lesser General   ////
1969
//// Public License as published by the Free Software Foundation; ////
1970
//// either version 2.1 of the License, or (at your option) any   ////
1971
//// later version.                                               ////
1972
////                                                              ////
1973
//// This source is distributed in the hope that it will be       ////
1974
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1975
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1976
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1977
//// details.                                                     ////
1978
////                                                              ////
1979
//// You should have received a copy of the GNU Lesser General    ////
1980
//// Public License along with this source; if not, download it   ////
1981
//// from http://www.opencores.org/lgpl.shtml                     ////
1982
////                                                              ////
1983
//////////////////////////////////////////////////////////////////////
1984
 
1985
// binary counter
1986 6 unneback
 
1987 40 unneback
`define MODULE cnt_bin_ce
1988
module `BASE`MODULE (
1989
`undef MODULE
1990
 cke, q, rst, clk);
1991
 
1992 6 unneback
   parameter length = 4;
1993
   input cke;
1994
   output [length:1] q;
1995
   input rst;
1996
   input clk;
1997
 
1998
   parameter clear_value = 0;
1999
   parameter set_value = 1;
2000
   parameter wrap_value = 0;
2001
   parameter level1_value = 15;
2002
 
2003
   reg  [length:1] qi;
2004
   wire [length:1] q_next;
2005
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2006
 
2007
   always @ (posedge clk or posedge rst)
2008
     if (rst)
2009
       qi <= {length{1'b0}};
2010
     else
2011
     if (cke)
2012
       qi <= q_next;
2013
 
2014
   assign q = qi;
2015
 
2016
endmodule
2017 40 unneback
`endif
2018
`ifdef CNT_BIN_CE_CLEAR
2019 6 unneback
//////////////////////////////////////////////////////////////////////
2020
////                                                              ////
2021
////  Versatile counter                                           ////
2022
////                                                              ////
2023
////  Description                                                 ////
2024
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2025
////  counter                                                     ////
2026
////                                                              ////
2027
////  To Do:                                                      ////
2028
////   - add LFSR with more taps                                  ////
2029
////                                                              ////
2030
////  Author(s):                                                  ////
2031
////      - Michael Unneback, unneback@opencores.org              ////
2032
////        ORSoC AB                                              ////
2033
////                                                              ////
2034
//////////////////////////////////////////////////////////////////////
2035
////                                                              ////
2036
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2037
////                                                              ////
2038
//// This source file may be used and distributed without         ////
2039
//// restriction provided that this copyright statement is not    ////
2040
//// removed from the file and that any derivative work contains  ////
2041
//// the original copyright notice and the associated disclaimer. ////
2042
////                                                              ////
2043
//// This source file is free software; you can redistribute it   ////
2044
//// and/or modify it under the terms of the GNU Lesser General   ////
2045
//// Public License as published by the Free Software Foundation; ////
2046
//// either version 2.1 of the License, or (at your option) any   ////
2047
//// later version.                                               ////
2048
////                                                              ////
2049
//// This source is distributed in the hope that it will be       ////
2050
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2051
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2052
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2053
//// details.                                                     ////
2054
////                                                              ////
2055
//// You should have received a copy of the GNU Lesser General    ////
2056
//// Public License along with this source; if not, download it   ////
2057
//// from http://www.opencores.org/lgpl.shtml                     ////
2058
////                                                              ////
2059
//////////////////////////////////////////////////////////////////////
2060
 
2061
// binary counter
2062
 
2063 40 unneback
`define MODULE cnt_bin_ce_clear
2064
module `BASE`MODULE (
2065
`undef MODULE
2066
 clear, cke, q, rst, clk);
2067
 
2068 6 unneback
   parameter length = 4;
2069
   input clear;
2070
   input cke;
2071
   output [length:1] q;
2072
   input rst;
2073
   input clk;
2074
 
2075
   parameter clear_value = 0;
2076
   parameter set_value = 1;
2077
   parameter wrap_value = 0;
2078
   parameter level1_value = 15;
2079
 
2080
   reg  [length:1] qi;
2081
   wire [length:1] q_next;
2082
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
2083
 
2084
   always @ (posedge clk or posedge rst)
2085
     if (rst)
2086
       qi <= {length{1'b0}};
2087
     else
2088
     if (cke)
2089
       qi <= q_next;
2090
 
2091
   assign q = qi;
2092
 
2093
endmodule
2094 40 unneback
`endif
2095
`ifdef CNT_BIN_CE_CLEAR_L1_L2
2096 6 unneback
//////////////////////////////////////////////////////////////////////
2097
////                                                              ////
2098
////  Versatile counter                                           ////
2099
////                                                              ////
2100
////  Description                                                 ////
2101
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2102
////  counter                                                     ////
2103
////                                                              ////
2104
////  To Do:                                                      ////
2105
////   - add LFSR with more taps                                  ////
2106
////                                                              ////
2107
////  Author(s):                                                  ////
2108
////      - Michael Unneback, unneback@opencores.org              ////
2109
////        ORSoC AB                                              ////
2110
////                                                              ////
2111
//////////////////////////////////////////////////////////////////////
2112
////                                                              ////
2113
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2114
////                                                              ////
2115
//// This source file may be used and distributed without         ////
2116
//// restriction provided that this copyright statement is not    ////
2117
//// removed from the file and that any derivative work contains  ////
2118
//// the original copyright notice and the associated disclaimer. ////
2119
////                                                              ////
2120
//// This source file is free software; you can redistribute it   ////
2121
//// and/or modify it under the terms of the GNU Lesser General   ////
2122
//// Public License as published by the Free Software Foundation; ////
2123
//// either version 2.1 of the License, or (at your option) any   ////
2124
//// later version.                                               ////
2125
////                                                              ////
2126
//// This source is distributed in the hope that it will be       ////
2127
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2128
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2129
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2130
//// details.                                                     ////
2131
////                                                              ////
2132
//// You should have received a copy of the GNU Lesser General    ////
2133
//// Public License along with this source; if not, download it   ////
2134
//// from http://www.opencores.org/lgpl.shtml                     ////
2135
////                                                              ////
2136
//////////////////////////////////////////////////////////////////////
2137
 
2138
// binary counter
2139 29 unneback
 
2140 40 unneback
`define MODULE cnt_bin_ce_clear_l1_l2
2141
module `BASE`MODULE (
2142
`undef MODULE
2143
 clear, cke, q, level1, level2, rst, clk);
2144
 
2145 29 unneback
   parameter length = 4;
2146
   input clear;
2147
   input cke;
2148
   output [length:1] q;
2149
   output reg level1;
2150
   output reg level2;
2151
   input rst;
2152
   input clk;
2153
 
2154
   parameter clear_value = 0;
2155
   parameter set_value = 1;
2156 30 unneback
   parameter wrap_value = 15;
2157
   parameter level1_value = 8;
2158
   parameter level2_value = 15;
2159 29 unneback
 
2160
   wire rew;
2161 30 unneback
   assign rew = 1'b0;
2162 29 unneback
   reg  [length:1] qi;
2163
   wire [length:1] q_next;
2164
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
2165
 
2166
   always @ (posedge clk or posedge rst)
2167
     if (rst)
2168
       qi <= {length{1'b0}};
2169
     else
2170
     if (cke)
2171
       qi <= q_next;
2172
 
2173
   assign q = qi;
2174
 
2175
 
2176
    always @ (posedge clk or posedge rst)
2177
    if (rst)
2178
        level1 <= 1'b0;
2179
    else
2180
    if (cke)
2181
    if (clear)
2182
        level1 <= 1'b0;
2183
    else if (q_next == level1_value)
2184
        level1 <= 1'b1;
2185
    else if (qi == level1_value & rew)
2186
        level1 <= 1'b0;
2187
 
2188
    always @ (posedge clk or posedge rst)
2189
    if (rst)
2190
        level2 <= 1'b0;
2191
    else
2192
    if (cke)
2193
    if (clear)
2194
        level2 <= 1'b0;
2195
    else if (q_next == level2_value)
2196
        level2 <= 1'b1;
2197
    else if (qi == level2_value & rew)
2198
        level2 <= 1'b0;
2199
endmodule
2200 40 unneback
`endif
2201
`ifdef CNT_BIN_CE_CLEAR_SET_REW
2202 29 unneback
//////////////////////////////////////////////////////////////////////
2203
////                                                              ////
2204
////  Versatile counter                                           ////
2205
////                                                              ////
2206
////  Description                                                 ////
2207
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2208
////  counter                                                     ////
2209
////                                                              ////
2210
////  To Do:                                                      ////
2211
////   - add LFSR with more taps                                  ////
2212
////                                                              ////
2213
////  Author(s):                                                  ////
2214
////      - Michael Unneback, unneback@opencores.org              ////
2215
////        ORSoC AB                                              ////
2216
////                                                              ////
2217
//////////////////////////////////////////////////////////////////////
2218
////                                                              ////
2219
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2220
////                                                              ////
2221
//// This source file may be used and distributed without         ////
2222
//// restriction provided that this copyright statement is not    ////
2223
//// removed from the file and that any derivative work contains  ////
2224
//// the original copyright notice and the associated disclaimer. ////
2225
////                                                              ////
2226
//// This source file is free software; you can redistribute it   ////
2227
//// and/or modify it under the terms of the GNU Lesser General   ////
2228
//// Public License as published by the Free Software Foundation; ////
2229
//// either version 2.1 of the License, or (at your option) any   ////
2230
//// later version.                                               ////
2231
////                                                              ////
2232
//// This source is distributed in the hope that it will be       ////
2233
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2234
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2235
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2236
//// details.                                                     ////
2237
////                                                              ////
2238
//// You should have received a copy of the GNU Lesser General    ////
2239
//// Public License along with this source; if not, download it   ////
2240
//// from http://www.opencores.org/lgpl.shtml                     ////
2241
////                                                              ////
2242
//////////////////////////////////////////////////////////////////////
2243
 
2244
// binary counter
2245 6 unneback
 
2246 40 unneback
`define MODULE cnt_bin_ce_clear_set_rew
2247
module `BASE`MODULE (
2248
`undef MODULE
2249
 clear, set, cke, rew, q, rst, clk);
2250
 
2251 6 unneback
   parameter length = 4;
2252
   input clear;
2253
   input set;
2254
   input cke;
2255
   input rew;
2256
   output [length:1] q;
2257
   input rst;
2258
   input clk;
2259
 
2260
   parameter clear_value = 0;
2261
   parameter set_value = 1;
2262
   parameter wrap_value = 0;
2263
   parameter level1_value = 15;
2264
 
2265
   reg  [length:1] qi;
2266
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2267
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
2268
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
2269
   assign q_next = rew ? q_next_rew : q_next_fw;
2270
 
2271
   always @ (posedge clk or posedge rst)
2272
     if (rst)
2273
       qi <= {length{1'b0}};
2274
     else
2275
     if (cke)
2276
       qi <= q_next;
2277
 
2278
   assign q = qi;
2279
 
2280
endmodule
2281 40 unneback
`endif
2282
`ifdef CNT_BIN_CE_REW_L1
2283 6 unneback
//////////////////////////////////////////////////////////////////////
2284
////                                                              ////
2285
////  Versatile counter                                           ////
2286
////                                                              ////
2287
////  Description                                                 ////
2288
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2289
////  counter                                                     ////
2290
////                                                              ////
2291
////  To Do:                                                      ////
2292
////   - add LFSR with more taps                                  ////
2293
////                                                              ////
2294
////  Author(s):                                                  ////
2295
////      - Michael Unneback, unneback@opencores.org              ////
2296
////        ORSoC AB                                              ////
2297
////                                                              ////
2298
//////////////////////////////////////////////////////////////////////
2299
////                                                              ////
2300
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2301
////                                                              ////
2302
//// This source file may be used and distributed without         ////
2303
//// restriction provided that this copyright statement is not    ////
2304
//// removed from the file and that any derivative work contains  ////
2305
//// the original copyright notice and the associated disclaimer. ////
2306
////                                                              ////
2307
//// This source file is free software; you can redistribute it   ////
2308
//// and/or modify it under the terms of the GNU Lesser General   ////
2309
//// Public License as published by the Free Software Foundation; ////
2310
//// either version 2.1 of the License, or (at your option) any   ////
2311
//// later version.                                               ////
2312
////                                                              ////
2313
//// This source is distributed in the hope that it will be       ////
2314
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2315
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2316
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2317
//// details.                                                     ////
2318
////                                                              ////
2319
//// You should have received a copy of the GNU Lesser General    ////
2320
//// Public License along with this source; if not, download it   ////
2321
//// from http://www.opencores.org/lgpl.shtml                     ////
2322
////                                                              ////
2323
//////////////////////////////////////////////////////////////////////
2324
 
2325
// binary counter
2326
 
2327 40 unneback
`define MODULE cnt_bin_ce_rew_l1
2328
module `BASE`MODULE (
2329
`undef MODULE
2330
 cke, rew, level1, rst, clk);
2331
 
2332 6 unneback
   parameter length = 4;
2333
   input cke;
2334
   input rew;
2335
   output reg level1;
2336
   input rst;
2337
   input clk;
2338
 
2339
   parameter clear_value = 0;
2340
   parameter set_value = 1;
2341
   parameter wrap_value = 1;
2342
   parameter level1_value = 15;
2343
 
2344 29 unneback
   wire clear;
2345 30 unneback
   assign clear = 1'b0;
2346 6 unneback
   reg  [length:1] qi;
2347
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2348
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2349
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2350
   assign q_next = rew ? q_next_rew : q_next_fw;
2351
 
2352
   always @ (posedge clk or posedge rst)
2353
     if (rst)
2354
       qi <= {length{1'b0}};
2355
     else
2356
     if (cke)
2357
       qi <= q_next;
2358
 
2359
 
2360
 
2361
    always @ (posedge clk or posedge rst)
2362
    if (rst)
2363
        level1 <= 1'b0;
2364
    else
2365
    if (cke)
2366 29 unneback
    if (clear)
2367
        level1 <= 1'b0;
2368
    else if (q_next == level1_value)
2369 6 unneback
        level1 <= 1'b1;
2370
    else if (qi == level1_value & rew)
2371
        level1 <= 1'b0;
2372
endmodule
2373 40 unneback
`endif
2374
`ifdef CNT_BIN_CE_REW_ZQ_L1
2375 6 unneback
//////////////////////////////////////////////////////////////////////
2376
////                                                              ////
2377
////  Versatile counter                                           ////
2378
////                                                              ////
2379
////  Description                                                 ////
2380
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2381
////  counter                                                     ////
2382
////                                                              ////
2383
////  To Do:                                                      ////
2384
////   - add LFSR with more taps                                  ////
2385
////                                                              ////
2386
////  Author(s):                                                  ////
2387
////      - Michael Unneback, unneback@opencores.org              ////
2388
////        ORSoC AB                                              ////
2389
////                                                              ////
2390
//////////////////////////////////////////////////////////////////////
2391
////                                                              ////
2392
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2393
////                                                              ////
2394
//// This source file may be used and distributed without         ////
2395
//// restriction provided that this copyright statement is not    ////
2396
//// removed from the file and that any derivative work contains  ////
2397
//// the original copyright notice and the associated disclaimer. ////
2398
////                                                              ////
2399
//// This source file is free software; you can redistribute it   ////
2400
//// and/or modify it under the terms of the GNU Lesser General   ////
2401
//// Public License as published by the Free Software Foundation; ////
2402
//// either version 2.1 of the License, or (at your option) any   ////
2403
//// later version.                                               ////
2404
////                                                              ////
2405
//// This source is distributed in the hope that it will be       ////
2406
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2407
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2408
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2409
//// details.                                                     ////
2410
////                                                              ////
2411
//// You should have received a copy of the GNU Lesser General    ////
2412
//// Public License along with this source; if not, download it   ////
2413
//// from http://www.opencores.org/lgpl.shtml                     ////
2414
////                                                              ////
2415
//////////////////////////////////////////////////////////////////////
2416
 
2417 25 unneback
// binary counter
2418
 
2419 40 unneback
`define MODULE cnt_bin_ce_rew_zq_l1
2420
module `BASE`MODULE (
2421
`undef MODULE
2422
 cke, rew, zq, level1, rst, clk);
2423
 
2424 25 unneback
   parameter length = 4;
2425
   input cke;
2426
   input rew;
2427
   output reg zq;
2428
   output reg level1;
2429
   input rst;
2430
   input clk;
2431
 
2432
   parameter clear_value = 0;
2433
   parameter set_value = 1;
2434
   parameter wrap_value = 1;
2435
   parameter level1_value = 15;
2436
 
2437 29 unneback
   wire clear;
2438 30 unneback
   assign clear = 1'b0;
2439 25 unneback
   reg  [length:1] qi;
2440
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2441
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2442
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2443
   assign q_next = rew ? q_next_rew : q_next_fw;
2444
 
2445
   always @ (posedge clk or posedge rst)
2446
     if (rst)
2447
       qi <= {length{1'b0}};
2448
     else
2449
     if (cke)
2450
       qi <= q_next;
2451
 
2452
 
2453
 
2454
   always @ (posedge clk or posedge rst)
2455
     if (rst)
2456
       zq <= 1'b1;
2457
     else
2458
     if (cke)
2459
       zq <= q_next == {length{1'b0}};
2460
 
2461
    always @ (posedge clk or posedge rst)
2462
    if (rst)
2463
        level1 <= 1'b0;
2464
    else
2465
    if (cke)
2466 29 unneback
    if (clear)
2467
        level1 <= 1'b0;
2468
    else if (q_next == level1_value)
2469 25 unneback
        level1 <= 1'b1;
2470
    else if (qi == level1_value & rew)
2471
        level1 <= 1'b0;
2472
endmodule
2473 40 unneback
`endif
2474
`ifdef CNT_BIN_CE_REW_Q_ZQ_L1
2475 25 unneback
//////////////////////////////////////////////////////////////////////
2476
////                                                              ////
2477
////  Versatile counter                                           ////
2478
////                                                              ////
2479
////  Description                                                 ////
2480
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2481
////  counter                                                     ////
2482
////                                                              ////
2483
////  To Do:                                                      ////
2484
////   - add LFSR with more taps                                  ////
2485
////                                                              ////
2486
////  Author(s):                                                  ////
2487
////      - Michael Unneback, unneback@opencores.org              ////
2488
////        ORSoC AB                                              ////
2489
////                                                              ////
2490
//////////////////////////////////////////////////////////////////////
2491
////                                                              ////
2492
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2493
////                                                              ////
2494
//// This source file may be used and distributed without         ////
2495
//// restriction provided that this copyright statement is not    ////
2496
//// removed from the file and that any derivative work contains  ////
2497
//// the original copyright notice and the associated disclaimer. ////
2498
////                                                              ////
2499
//// This source file is free software; you can redistribute it   ////
2500
//// and/or modify it under the terms of the GNU Lesser General   ////
2501
//// Public License as published by the Free Software Foundation; ////
2502
//// either version 2.1 of the License, or (at your option) any   ////
2503
//// later version.                                               ////
2504
////                                                              ////
2505
//// This source is distributed in the hope that it will be       ////
2506
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2507
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2508
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2509
//// details.                                                     ////
2510
////                                                              ////
2511
//// You should have received a copy of the GNU Lesser General    ////
2512
//// Public License along with this source; if not, download it   ////
2513
//// from http://www.opencores.org/lgpl.shtml                     ////
2514
////                                                              ////
2515
//////////////////////////////////////////////////////////////////////
2516
 
2517
// binary counter
2518
 
2519 40 unneback
`define MODULE cnt_bin_ce_rew_q_zq_l1
2520
module `BASE`MODULE (
2521
`undef MODULE
2522
 cke, rew, q, zq, level1, rst, clk);
2523
 
2524 25 unneback
   parameter length = 4;
2525
   input cke;
2526
   input rew;
2527
   output [length:1] q;
2528
   output reg zq;
2529
   output reg level1;
2530
   input rst;
2531
   input clk;
2532
 
2533
   parameter clear_value = 0;
2534
   parameter set_value = 1;
2535
   parameter wrap_value = 1;
2536
   parameter level1_value = 15;
2537
 
2538 29 unneback
   wire clear;
2539 30 unneback
   assign clear = 1'b0;
2540 25 unneback
   reg  [length:1] qi;
2541
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2542
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2543
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2544
   assign q_next = rew ? q_next_rew : q_next_fw;
2545
 
2546
   always @ (posedge clk or posedge rst)
2547
     if (rst)
2548
       qi <= {length{1'b0}};
2549
     else
2550
     if (cke)
2551
       qi <= q_next;
2552
 
2553
   assign q = qi;
2554
 
2555
 
2556
   always @ (posedge clk or posedge rst)
2557
     if (rst)
2558
       zq <= 1'b1;
2559
     else
2560
     if (cke)
2561
       zq <= q_next == {length{1'b0}};
2562
 
2563
    always @ (posedge clk or posedge rst)
2564
    if (rst)
2565
        level1 <= 1'b0;
2566
    else
2567
    if (cke)
2568 29 unneback
    if (clear)
2569
        level1 <= 1'b0;
2570
    else if (q_next == level1_value)
2571 25 unneback
        level1 <= 1'b1;
2572
    else if (qi == level1_value & rew)
2573
        level1 <= 1'b0;
2574
endmodule
2575 40 unneback
`endif
2576
`ifdef CNT_LFSR_ZQ
2577 25 unneback
//////////////////////////////////////////////////////////////////////
2578
////                                                              ////
2579
////  Versatile counter                                           ////
2580
////                                                              ////
2581
////  Description                                                 ////
2582
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2583
////  counter                                                     ////
2584
////                                                              ////
2585
////  To Do:                                                      ////
2586
////   - add LFSR with more taps                                  ////
2587
////                                                              ////
2588
////  Author(s):                                                  ////
2589
////      - Michael Unneback, unneback@opencores.org              ////
2590
////        ORSoC AB                                              ////
2591
////                                                              ////
2592
//////////////////////////////////////////////////////////////////////
2593
////                                                              ////
2594
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2595
////                                                              ////
2596
//// This source file may be used and distributed without         ////
2597
//// restriction provided that this copyright statement is not    ////
2598
//// removed from the file and that any derivative work contains  ////
2599
//// the original copyright notice and the associated disclaimer. ////
2600
////                                                              ////
2601
//// This source file is free software; you can redistribute it   ////
2602
//// and/or modify it under the terms of the GNU Lesser General   ////
2603
//// Public License as published by the Free Software Foundation; ////
2604
//// either version 2.1 of the License, or (at your option) any   ////
2605
//// later version.                                               ////
2606
////                                                              ////
2607
//// This source is distributed in the hope that it will be       ////
2608
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2609
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2610
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2611
//// details.                                                     ////
2612
////                                                              ////
2613
//// You should have received a copy of the GNU Lesser General    ////
2614
//// Public License along with this source; if not, download it   ////
2615
//// from http://www.opencores.org/lgpl.shtml                     ////
2616
////                                                              ////
2617
//////////////////////////////////////////////////////////////////////
2618
 
2619 6 unneback
// LFSR counter
2620
 
2621 40 unneback
`define MODULE cnt_lfsr_zq
2622
module `BASE`MODULE (
2623
`undef MODULE
2624
 zq, rst, clk);
2625
 
2626 6 unneback
   parameter length = 4;
2627
   output reg zq;
2628
   input rst;
2629
   input clk;
2630
 
2631
   parameter clear_value = 0;
2632
   parameter set_value = 1;
2633
   parameter wrap_value = 8;
2634
   parameter level1_value = 15;
2635
 
2636
   reg  [length:1] qi;
2637
   reg lfsr_fb;
2638
   wire [length:1] q_next;
2639
   reg [32:1] polynom;
2640
   integer i;
2641
 
2642
   always @ (qi)
2643
   begin
2644
        case (length)
2645
         2: polynom = 32'b11;                               // 0x3
2646
         3: polynom = 32'b110;                              // 0x6
2647
         4: polynom = 32'b1100;                             // 0xC
2648
         5: polynom = 32'b10100;                            // 0x14
2649
         6: polynom = 32'b110000;                           // 0x30
2650
         7: polynom = 32'b1100000;                          // 0x60
2651
         8: polynom = 32'b10111000;                         // 0xb8
2652
         9: polynom = 32'b100010000;                        // 0x110
2653
        10: polynom = 32'b1001000000;                       // 0x240
2654
        11: polynom = 32'b10100000000;                      // 0x500
2655
        12: polynom = 32'b100000101001;                     // 0x829
2656
        13: polynom = 32'b1000000001100;                    // 0x100C
2657
        14: polynom = 32'b10000000010101;                   // 0x2015
2658
        15: polynom = 32'b110000000000000;                  // 0x6000
2659
        16: polynom = 32'b1101000000001000;                 // 0xD008
2660
        17: polynom = 32'b10010000000000000;                // 0x12000
2661
        18: polynom = 32'b100000010000000000;               // 0x20400
2662
        19: polynom = 32'b1000000000000100011;              // 0x40023
2663 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2664 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2665
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2666
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2667
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2668
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2669
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2670
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2671
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2672
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2673
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2674
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2675
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2676
        default: polynom = 32'b0;
2677
        endcase
2678
        lfsr_fb = qi[length];
2679
        for (i=length-1; i>=1; i=i-1) begin
2680
            if (polynom[i])
2681
                lfsr_fb = lfsr_fb  ~^ qi[i];
2682
        end
2683
    end
2684
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2685
 
2686
   always @ (posedge clk or posedge rst)
2687
     if (rst)
2688
       qi <= {length{1'b0}};
2689
     else
2690
       qi <= q_next;
2691
 
2692
 
2693
 
2694
   always @ (posedge clk or posedge rst)
2695
     if (rst)
2696
       zq <= 1'b1;
2697
     else
2698
       zq <= q_next == {length{1'b0}};
2699
endmodule
2700 40 unneback
`endif
2701 75 unneback
`ifdef CNT_LFSR_CE
2702
//////////////////////////////////////////////////////////////////////
2703
////                                                              ////
2704
////  Versatile counter                                           ////
2705
////                                                              ////
2706
////  Description                                                 ////
2707
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2708
////  counter                                                     ////
2709
////                                                              ////
2710
////  To Do:                                                      ////
2711
////   - add LFSR with more taps                                  ////
2712
////                                                              ////
2713
////  Author(s):                                                  ////
2714
////      - Michael Unneback, unneback@opencores.org              ////
2715
////        ORSoC AB                                              ////
2716
////                                                              ////
2717
//////////////////////////////////////////////////////////////////////
2718
////                                                              ////
2719
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2720
////                                                              ////
2721
//// This source file may be used and distributed without         ////
2722
//// restriction provided that this copyright statement is not    ////
2723
//// removed from the file and that any derivative work contains  ////
2724
//// the original copyright notice and the associated disclaimer. ////
2725
////                                                              ////
2726
//// This source file is free software; you can redistribute it   ////
2727
//// and/or modify it under the terms of the GNU Lesser General   ////
2728
//// Public License as published by the Free Software Foundation; ////
2729
//// either version 2.1 of the License, or (at your option) any   ////
2730
//// later version.                                               ////
2731
////                                                              ////
2732
//// This source is distributed in the hope that it will be       ////
2733
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2734
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2735
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2736
//// details.                                                     ////
2737
////                                                              ////
2738
//// You should have received a copy of the GNU Lesser General    ////
2739
//// Public License along with this source; if not, download it   ////
2740
//// from http://www.opencores.org/lgpl.shtml                     ////
2741
////                                                              ////
2742
//////////////////////////////////////////////////////////////////////
2743
 
2744
// LFSR counter
2745
 
2746
`define MODULE cnt_lfsr_ce
2747
module `BASE`MODULE (
2748
`undef MODULE
2749
 cke, zq, rst, clk);
2750
 
2751
   parameter length = 4;
2752
   input cke;
2753
   output reg zq;
2754
   input rst;
2755
   input clk;
2756
 
2757
   parameter clear_value = 0;
2758
   parameter set_value = 1;
2759
   parameter wrap_value = 0;
2760
   parameter level1_value = 15;
2761
 
2762
   reg  [length:1] qi;
2763
   reg lfsr_fb;
2764
   wire [length:1] q_next;
2765
   reg [32:1] polynom;
2766
   integer i;
2767
 
2768
   always @ (qi)
2769
   begin
2770
        case (length)
2771
         2: polynom = 32'b11;                               // 0x3
2772
         3: polynom = 32'b110;                              // 0x6
2773
         4: polynom = 32'b1100;                             // 0xC
2774
         5: polynom = 32'b10100;                            // 0x14
2775
         6: polynom = 32'b110000;                           // 0x30
2776
         7: polynom = 32'b1100000;                          // 0x60
2777
         8: polynom = 32'b10111000;                         // 0xb8
2778
         9: polynom = 32'b100010000;                        // 0x110
2779
        10: polynom = 32'b1001000000;                       // 0x240
2780
        11: polynom = 32'b10100000000;                      // 0x500
2781
        12: polynom = 32'b100000101001;                     // 0x829
2782
        13: polynom = 32'b1000000001100;                    // 0x100C
2783
        14: polynom = 32'b10000000010101;                   // 0x2015
2784
        15: polynom = 32'b110000000000000;                  // 0x6000
2785
        16: polynom = 32'b1101000000001000;                 // 0xD008
2786
        17: polynom = 32'b10010000000000000;                // 0x12000
2787
        18: polynom = 32'b100000010000000000;               // 0x20400
2788
        19: polynom = 32'b1000000000000100011;              // 0x40023
2789
        20: polynom = 32'b10010000000000000000;             // 0x90000
2790
        21: polynom = 32'b101000000000000000000;            // 0x140000
2791
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2792
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2793
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2794
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2795
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2796
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2797
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2798
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2799
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2800
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2801
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2802
        default: polynom = 32'b0;
2803
        endcase
2804
        lfsr_fb = qi[length];
2805
        for (i=length-1; i>=1; i=i-1) begin
2806
            if (polynom[i])
2807
                lfsr_fb = lfsr_fb  ~^ qi[i];
2808
        end
2809
    end
2810
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2811
 
2812
   always @ (posedge clk or posedge rst)
2813
     if (rst)
2814
       qi <= {length{1'b0}};
2815
     else
2816
     if (cke)
2817
       qi <= q_next;
2818
 
2819
 
2820
 
2821
   always @ (posedge clk or posedge rst)
2822
     if (rst)
2823
       zq <= 1'b1;
2824
     else
2825
     if (cke)
2826
       zq <= q_next == {length{1'b0}};
2827
endmodule
2828
`endif
2829 40 unneback
`ifdef CNT_LFSR_CE_ZQ
2830 6 unneback
//////////////////////////////////////////////////////////////////////
2831
////                                                              ////
2832
////  Versatile counter                                           ////
2833
////                                                              ////
2834
////  Description                                                 ////
2835
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2836
////  counter                                                     ////
2837
////                                                              ////
2838
////  To Do:                                                      ////
2839
////   - add LFSR with more taps                                  ////
2840
////                                                              ////
2841
////  Author(s):                                                  ////
2842
////      - Michael Unneback, unneback@opencores.org              ////
2843
////        ORSoC AB                                              ////
2844
////                                                              ////
2845
//////////////////////////////////////////////////////////////////////
2846
////                                                              ////
2847
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2848
////                                                              ////
2849
//// This source file may be used and distributed without         ////
2850
//// restriction provided that this copyright statement is not    ////
2851
//// removed from the file and that any derivative work contains  ////
2852
//// the original copyright notice and the associated disclaimer. ////
2853
////                                                              ////
2854
//// This source file is free software; you can redistribute it   ////
2855
//// and/or modify it under the terms of the GNU Lesser General   ////
2856
//// Public License as published by the Free Software Foundation; ////
2857
//// either version 2.1 of the License, or (at your option) any   ////
2858
//// later version.                                               ////
2859
////                                                              ////
2860
//// This source is distributed in the hope that it will be       ////
2861
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2862
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2863
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2864
//// details.                                                     ////
2865
////                                                              ////
2866
//// You should have received a copy of the GNU Lesser General    ////
2867
//// Public License along with this source; if not, download it   ////
2868
//// from http://www.opencores.org/lgpl.shtml                     ////
2869
////                                                              ////
2870
//////////////////////////////////////////////////////////////////////
2871
 
2872
// LFSR counter
2873
 
2874 40 unneback
`define MODULE cnt_lfsr_ce_zq
2875
module `BASE`MODULE (
2876
`undef MODULE
2877
 cke, zq, rst, clk);
2878
 
2879 6 unneback
   parameter length = 4;
2880
   input cke;
2881
   output reg zq;
2882
   input rst;
2883
   input clk;
2884
 
2885
   parameter clear_value = 0;
2886
   parameter set_value = 1;
2887
   parameter wrap_value = 8;
2888
   parameter level1_value = 15;
2889
 
2890
   reg  [length:1] qi;
2891
   reg lfsr_fb;
2892
   wire [length:1] q_next;
2893
   reg [32:1] polynom;
2894
   integer i;
2895
 
2896
   always @ (qi)
2897
   begin
2898
        case (length)
2899
         2: polynom = 32'b11;                               // 0x3
2900
         3: polynom = 32'b110;                              // 0x6
2901
         4: polynom = 32'b1100;                             // 0xC
2902
         5: polynom = 32'b10100;                            // 0x14
2903
         6: polynom = 32'b110000;                           // 0x30
2904
         7: polynom = 32'b1100000;                          // 0x60
2905
         8: polynom = 32'b10111000;                         // 0xb8
2906
         9: polynom = 32'b100010000;                        // 0x110
2907
        10: polynom = 32'b1001000000;                       // 0x240
2908
        11: polynom = 32'b10100000000;                      // 0x500
2909
        12: polynom = 32'b100000101001;                     // 0x829
2910
        13: polynom = 32'b1000000001100;                    // 0x100C
2911
        14: polynom = 32'b10000000010101;                   // 0x2015
2912
        15: polynom = 32'b110000000000000;                  // 0x6000
2913
        16: polynom = 32'b1101000000001000;                 // 0xD008
2914
        17: polynom = 32'b10010000000000000;                // 0x12000
2915
        18: polynom = 32'b100000010000000000;               // 0x20400
2916
        19: polynom = 32'b1000000000000100011;              // 0x40023
2917 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2918 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2919
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2920
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2921
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2922
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2923
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2924
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2925
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2926
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2927
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2928
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2929
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2930
        default: polynom = 32'b0;
2931
        endcase
2932
        lfsr_fb = qi[length];
2933
        for (i=length-1; i>=1; i=i-1) begin
2934
            if (polynom[i])
2935
                lfsr_fb = lfsr_fb  ~^ qi[i];
2936
        end
2937
    end
2938
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2939
 
2940
   always @ (posedge clk or posedge rst)
2941
     if (rst)
2942
       qi <= {length{1'b0}};
2943
     else
2944
     if (cke)
2945
       qi <= q_next;
2946
 
2947
 
2948
 
2949
   always @ (posedge clk or posedge rst)
2950
     if (rst)
2951
       zq <= 1'b1;
2952
     else
2953
     if (cke)
2954
       zq <= q_next == {length{1'b0}};
2955
endmodule
2956 40 unneback
`endif
2957
`ifdef CNT_LFSR_CE_Q
2958 6 unneback
//////////////////////////////////////////////////////////////////////
2959
////                                                              ////
2960
////  Versatile counter                                           ////
2961
////                                                              ////
2962
////  Description                                                 ////
2963
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2964
////  counter                                                     ////
2965
////                                                              ////
2966
////  To Do:                                                      ////
2967
////   - add LFSR with more taps                                  ////
2968
////                                                              ////
2969
////  Author(s):                                                  ////
2970
////      - Michael Unneback, unneback@opencores.org              ////
2971
////        ORSoC AB                                              ////
2972
////                                                              ////
2973
//////////////////////////////////////////////////////////////////////
2974
////                                                              ////
2975
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2976
////                                                              ////
2977
//// This source file may be used and distributed without         ////
2978
//// restriction provided that this copyright statement is not    ////
2979
//// removed from the file and that any derivative work contains  ////
2980
//// the original copyright notice and the associated disclaimer. ////
2981
////                                                              ////
2982
//// This source file is free software; you can redistribute it   ////
2983
//// and/or modify it under the terms of the GNU Lesser General   ////
2984
//// Public License as published by the Free Software Foundation; ////
2985
//// either version 2.1 of the License, or (at your option) any   ////
2986
//// later version.                                               ////
2987
////                                                              ////
2988
//// This source is distributed in the hope that it will be       ////
2989
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2990
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2991
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2992
//// details.                                                     ////
2993
////                                                              ////
2994
//// You should have received a copy of the GNU Lesser General    ////
2995
//// Public License along with this source; if not, download it   ////
2996
//// from http://www.opencores.org/lgpl.shtml                     ////
2997
////                                                              ////
2998
//////////////////////////////////////////////////////////////////////
2999 22 unneback
 
3000
// LFSR counter
3001 27 unneback
 
3002 40 unneback
`define MODULE cnt_lfsr_ce_q
3003
module `BASE`MODULE (
3004
`undef MODULE
3005
 cke, q, rst, clk);
3006
 
3007 27 unneback
   parameter length = 4;
3008
   input cke;
3009
   output [length:1] q;
3010
   input rst;
3011
   input clk;
3012
 
3013
   parameter clear_value = 0;
3014
   parameter set_value = 1;
3015
   parameter wrap_value = 8;
3016
   parameter level1_value = 15;
3017
 
3018
   reg  [length:1] qi;
3019
   reg lfsr_fb;
3020
   wire [length:1] q_next;
3021
   reg [32:1] polynom;
3022
   integer i;
3023
 
3024
   always @ (qi)
3025
   begin
3026
        case (length)
3027
         2: polynom = 32'b11;                               // 0x3
3028
         3: polynom = 32'b110;                              // 0x6
3029
         4: polynom = 32'b1100;                             // 0xC
3030
         5: polynom = 32'b10100;                            // 0x14
3031
         6: polynom = 32'b110000;                           // 0x30
3032
         7: polynom = 32'b1100000;                          // 0x60
3033
         8: polynom = 32'b10111000;                         // 0xb8
3034
         9: polynom = 32'b100010000;                        // 0x110
3035
        10: polynom = 32'b1001000000;                       // 0x240
3036
        11: polynom = 32'b10100000000;                      // 0x500
3037
        12: polynom = 32'b100000101001;                     // 0x829
3038
        13: polynom = 32'b1000000001100;                    // 0x100C
3039
        14: polynom = 32'b10000000010101;                   // 0x2015
3040
        15: polynom = 32'b110000000000000;                  // 0x6000
3041
        16: polynom = 32'b1101000000001000;                 // 0xD008
3042
        17: polynom = 32'b10010000000000000;                // 0x12000
3043
        18: polynom = 32'b100000010000000000;               // 0x20400
3044
        19: polynom = 32'b1000000000000100011;              // 0x40023
3045 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
3046 27 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
3047
        22: polynom = 32'b1100000000000000000000;           // 0x300000
3048
        23: polynom = 32'b10000100000000000000000;          // 0x420000
3049
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
3050
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
3051
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
3052
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
3053
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
3054
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
3055
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
3056
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
3057
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
3058
        default: polynom = 32'b0;
3059
        endcase
3060
        lfsr_fb = qi[length];
3061
        for (i=length-1; i>=1; i=i-1) begin
3062
            if (polynom[i])
3063
                lfsr_fb = lfsr_fb  ~^ qi[i];
3064
        end
3065
    end
3066
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
3067
 
3068
   always @ (posedge clk or posedge rst)
3069
     if (rst)
3070
       qi <= {length{1'b0}};
3071
     else
3072
     if (cke)
3073
       qi <= q_next;
3074
 
3075
   assign q = qi;
3076
 
3077
endmodule
3078 40 unneback
`endif
3079
`ifdef CNT_LFSR_CE_CLEAR_Q
3080 27 unneback
//////////////////////////////////////////////////////////////////////
3081
////                                                              ////
3082
////  Versatile counter                                           ////
3083
////                                                              ////
3084
////  Description                                                 ////
3085
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3086
////  counter                                                     ////
3087
////                                                              ////
3088
////  To Do:                                                      ////
3089
////   - add LFSR with more taps                                  ////
3090
////                                                              ////
3091
////  Author(s):                                                  ////
3092
////      - Michael Unneback, unneback@opencores.org              ////
3093
////        ORSoC AB                                              ////
3094
////                                                              ////
3095
//////////////////////////////////////////////////////////////////////
3096
////                                                              ////
3097
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3098
////                                                              ////
3099
//// This source file may be used and distributed without         ////
3100
//// restriction provided that this copyright statement is not    ////
3101
//// removed from the file and that any derivative work contains  ////
3102
//// the original copyright notice and the associated disclaimer. ////
3103
////                                                              ////
3104
//// This source file is free software; you can redistribute it   ////
3105
//// and/or modify it under the terms of the GNU Lesser General   ////
3106
//// Public License as published by the Free Software Foundation; ////
3107
//// either version 2.1 of the License, or (at your option) any   ////
3108
//// later version.                                               ////
3109
////                                                              ////
3110
//// This source is distributed in the hope that it will be       ////
3111
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3112
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3113
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3114
//// details.                                                     ////
3115
////                                                              ////
3116
//// You should have received a copy of the GNU Lesser General    ////
3117
//// Public License along with this source; if not, download it   ////
3118
//// from http://www.opencores.org/lgpl.shtml                     ////
3119
////                                                              ////
3120
//////////////////////////////////////////////////////////////////////
3121
 
3122
// LFSR counter
3123
 
3124 40 unneback
`define MODULE cnt_lfsr_ce_clear_q
3125
module `BASE`MODULE (
3126
`undef MODULE
3127
 clear, cke, q, rst, clk);
3128
 
3129 27 unneback
   parameter length = 4;
3130
   input clear;
3131
   input cke;
3132
   output [length:1] q;
3133
   input rst;
3134
   input clk;
3135
 
3136
   parameter clear_value = 0;
3137
   parameter set_value = 1;
3138
   parameter wrap_value = 8;
3139
   parameter level1_value = 15;
3140
 
3141
   reg  [length:1] qi;
3142
   reg lfsr_fb;
3143
   wire [length:1] q_next;
3144
   reg [32:1] polynom;
3145
   integer i;
3146
 
3147
   always @ (qi)
3148
   begin
3149
        case (length)
3150
         2: polynom = 32'b11;                               // 0x3
3151
         3: polynom = 32'b110;                              // 0x6
3152
         4: polynom = 32'b1100;                             // 0xC
3153
         5: polynom = 32'b10100;                            // 0x14
3154
         6: polynom = 32'b110000;                           // 0x30
3155
         7: polynom = 32'b1100000;                          // 0x60
3156
         8: polynom = 32'b10111000;                         // 0xb8
3157
         9: polynom = 32'b100010000;                        // 0x110
3158
        10: polynom = 32'b1001000000;                       // 0x240
3159
        11: polynom = 32'b10100000000;                      // 0x500
3160
        12: polynom = 32'b100000101001;                     // 0x829
3161
        13: polynom = 32'b1000000001100;                    // 0x100C
3162
        14: polynom = 32'b10000000010101;                   // 0x2015
3163
        15: polynom = 32'b110000000000000;                  // 0x6000
3164
        16: polynom = 32'b1101000000001000;                 // 0xD008
3165
        17: polynom = 32'b10010000000000000;                // 0x12000
3166
        18: polynom = 32'b100000010000000000;               // 0x20400
3167
        19: polynom = 32'b1000000000000100011;              // 0x40023
3168 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
3169 27 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
3170
        22: polynom = 32'b1100000000000000000000;           // 0x300000
3171
        23: polynom = 32'b10000100000000000000000;          // 0x420000
3172
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
3173
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
3174
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
3175
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
3176
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
3177
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
3178
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
3179
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
3180
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
3181
        default: polynom = 32'b0;
3182
        endcase
3183
        lfsr_fb = qi[length];
3184
        for (i=length-1; i>=1; i=i-1) begin
3185
            if (polynom[i])
3186
                lfsr_fb = lfsr_fb  ~^ qi[i];
3187
        end
3188
    end
3189
   assign q_next =  clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
3190
 
3191
   always @ (posedge clk or posedge rst)
3192
     if (rst)
3193
       qi <= {length{1'b0}};
3194
     else
3195
     if (cke)
3196
       qi <= q_next;
3197
 
3198
   assign q = qi;
3199
 
3200
endmodule
3201 40 unneback
`endif
3202
`ifdef CNT_LFSR_CE_Q_ZQ
3203 27 unneback
//////////////////////////////////////////////////////////////////////
3204
////                                                              ////
3205
////  Versatile counter                                           ////
3206
////                                                              ////
3207
////  Description                                                 ////
3208
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3209
////  counter                                                     ////
3210
////                                                              ////
3211
////  To Do:                                                      ////
3212
////   - add LFSR with more taps                                  ////
3213
////                                                              ////
3214
////  Author(s):                                                  ////
3215
////      - Michael Unneback, unneback@opencores.org              ////
3216
////        ORSoC AB                                              ////
3217
////                                                              ////
3218
//////////////////////////////////////////////////////////////////////
3219
////                                                              ////
3220
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3221
////                                                              ////
3222
//// This source file may be used and distributed without         ////
3223
//// restriction provided that this copyright statement is not    ////
3224
//// removed from the file and that any derivative work contains  ////
3225
//// the original copyright notice and the associated disclaimer. ////
3226
////                                                              ////
3227
//// This source file is free software; you can redistribute it   ////
3228
//// and/or modify it under the terms of the GNU Lesser General   ////
3229
//// Public License as published by the Free Software Foundation; ////
3230
//// either version 2.1 of the License, or (at your option) any   ////
3231
//// later version.                                               ////
3232
////                                                              ////
3233
//// This source is distributed in the hope that it will be       ////
3234
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3235
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3236
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3237
//// details.                                                     ////
3238
////                                                              ////
3239
//// You should have received a copy of the GNU Lesser General    ////
3240
//// Public License along with this source; if not, download it   ////
3241
//// from http://www.opencores.org/lgpl.shtml                     ////
3242
////                                                              ////
3243
//////////////////////////////////////////////////////////////////////
3244
 
3245
// LFSR counter
3246 22 unneback
 
3247 40 unneback
`define MODULE cnt_lfsr_ce_q_zq
3248
module `BASE`MODULE (
3249
`undef MODULE
3250
 cke, q, zq, rst, clk);
3251
 
3252 22 unneback
   parameter length = 4;
3253
   input cke;
3254
   output [length:1] q;
3255
   output reg zq;
3256
   input rst;
3257
   input clk;
3258
 
3259
   parameter clear_value = 0;
3260
   parameter set_value = 1;
3261
   parameter wrap_value = 8;
3262
   parameter level1_value = 15;
3263
 
3264
   reg  [length:1] qi;
3265
   reg lfsr_fb;
3266
   wire [length:1] q_next;
3267
   reg [32:1] polynom;
3268
   integer i;
3269
 
3270
   always @ (qi)
3271
   begin
3272
        case (length)
3273
         2: polynom = 32'b11;                               // 0x3
3274
         3: polynom = 32'b110;                              // 0x6
3275
         4: polynom = 32'b1100;                             // 0xC
3276
         5: polynom = 32'b10100;                            // 0x14
3277
         6: polynom = 32'b110000;                           // 0x30
3278
         7: polynom = 32'b1100000;                          // 0x60
3279
         8: polynom = 32'b10111000;                         // 0xb8
3280
         9: polynom = 32'b100010000;                        // 0x110
3281
        10: polynom = 32'b1001000000;                       // 0x240
3282
        11: polynom = 32'b10100000000;                      // 0x500
3283
        12: polynom = 32'b100000101001;                     // 0x829
3284
        13: polynom = 32'b1000000001100;                    // 0x100C
3285
        14: polynom = 32'b10000000010101;                   // 0x2015
3286
        15: polynom = 32'b110000000000000;                  // 0x6000
3287
        16: polynom = 32'b1101000000001000;                 // 0xD008
3288
        17: polynom = 32'b10010000000000000;                // 0x12000
3289
        18: polynom = 32'b100000010000000000;               // 0x20400
3290
        19: polynom = 32'b1000000000000100011;              // 0x40023
3291 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
3292 22 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
3293
        22: polynom = 32'b1100000000000000000000;           // 0x300000
3294
        23: polynom = 32'b10000100000000000000000;          // 0x420000
3295
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
3296
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
3297
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
3298
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
3299
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
3300
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
3301
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
3302
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
3303
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
3304
        default: polynom = 32'b0;
3305
        endcase
3306
        lfsr_fb = qi[length];
3307
        for (i=length-1; i>=1; i=i-1) begin
3308
            if (polynom[i])
3309
                lfsr_fb = lfsr_fb  ~^ qi[i];
3310
        end
3311
    end
3312
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
3313
 
3314
   always @ (posedge clk or posedge rst)
3315
     if (rst)
3316
       qi <= {length{1'b0}};
3317
     else
3318
     if (cke)
3319
       qi <= q_next;
3320
 
3321
   assign q = qi;
3322
 
3323
 
3324
   always @ (posedge clk or posedge rst)
3325
     if (rst)
3326
       zq <= 1'b1;
3327
     else
3328
     if (cke)
3329
       zq <= q_next == {length{1'b0}};
3330
endmodule
3331 40 unneback
`endif
3332
`ifdef CNT_LFSR_CE_REW_L1
3333 22 unneback
//////////////////////////////////////////////////////////////////////
3334
////                                                              ////
3335
////  Versatile counter                                           ////
3336
////                                                              ////
3337
////  Description                                                 ////
3338
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3339
////  counter                                                     ////
3340
////                                                              ////
3341
////  To Do:                                                      ////
3342
////   - add LFSR with more taps                                  ////
3343
////                                                              ////
3344
////  Author(s):                                                  ////
3345
////      - Michael Unneback, unneback@opencores.org              ////
3346
////        ORSoC AB                                              ////
3347
////                                                              ////
3348
//////////////////////////////////////////////////////////////////////
3349
////                                                              ////
3350
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3351
////                                                              ////
3352
//// This source file may be used and distributed without         ////
3353
//// restriction provided that this copyright statement is not    ////
3354
//// removed from the file and that any derivative work contains  ////
3355
//// the original copyright notice and the associated disclaimer. ////
3356
////                                                              ////
3357
//// This source file is free software; you can redistribute it   ////
3358
//// and/or modify it under the terms of the GNU Lesser General   ////
3359
//// Public License as published by the Free Software Foundation; ////
3360
//// either version 2.1 of the License, or (at your option) any   ////
3361
//// later version.                                               ////
3362
////                                                              ////
3363
//// This source is distributed in the hope that it will be       ////
3364
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3365
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3366
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3367
//// details.                                                     ////
3368
////                                                              ////
3369
//// You should have received a copy of the GNU Lesser General    ////
3370
//// Public License along with this source; if not, download it   ////
3371
//// from http://www.opencores.org/lgpl.shtml                     ////
3372
////                                                              ////
3373
//////////////////////////////////////////////////////////////////////
3374 6 unneback
 
3375
// LFSR counter
3376
 
3377 40 unneback
`define MODULE cnt_lfsr_ce_rew_l1
3378
module `BASE`MODULE (
3379
`undef MODULE
3380
 cke, rew, level1, rst, clk);
3381
 
3382 6 unneback
   parameter length = 4;
3383
   input cke;
3384
   input rew;
3385
   output reg level1;
3386
   input rst;
3387
   input clk;
3388
 
3389
   parameter clear_value = 0;
3390
   parameter set_value = 1;
3391
   parameter wrap_value = 8;
3392
   parameter level1_value = 15;
3393
 
3394 29 unneback
   wire clear;
3395 30 unneback
   assign clear = 1'b0;
3396 6 unneback
   reg  [length:1] qi;
3397
   reg lfsr_fb, lfsr_fb_rew;
3398
   wire  [length:1] q_next, q_next_fw, q_next_rew;
3399
   reg [32:1] polynom_rew;
3400
   integer j;
3401
   reg [32:1] polynom;
3402
   integer i;
3403
 
3404
   always @ (qi)
3405
   begin
3406
        case (length)
3407
         2: polynom = 32'b11;                               // 0x3
3408
         3: polynom = 32'b110;                              // 0x6
3409
         4: polynom = 32'b1100;                             // 0xC
3410
         5: polynom = 32'b10100;                            // 0x14
3411
         6: polynom = 32'b110000;                           // 0x30
3412
         7: polynom = 32'b1100000;                          // 0x60
3413
         8: polynom = 32'b10111000;                         // 0xb8
3414
         9: polynom = 32'b100010000;                        // 0x110
3415
        10: polynom = 32'b1001000000;                       // 0x240
3416
        11: polynom = 32'b10100000000;                      // 0x500
3417
        12: polynom = 32'b100000101001;                     // 0x829
3418
        13: polynom = 32'b1000000001100;                    // 0x100C
3419
        14: polynom = 32'b10000000010101;                   // 0x2015
3420
        15: polynom = 32'b110000000000000;                  // 0x6000
3421
        16: polynom = 32'b1101000000001000;                 // 0xD008
3422
        17: polynom = 32'b10010000000000000;                // 0x12000
3423
        18: polynom = 32'b100000010000000000;               // 0x20400
3424
        19: polynom = 32'b1000000000000100011;              // 0x40023
3425 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
3426 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
3427
        22: polynom = 32'b1100000000000000000000;           // 0x300000
3428
        23: polynom = 32'b10000100000000000000000;          // 0x420000
3429
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
3430
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
3431
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
3432
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
3433
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
3434
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
3435
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
3436
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
3437
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
3438
        default: polynom = 32'b0;
3439
        endcase
3440
        lfsr_fb = qi[length];
3441
        for (i=length-1; i>=1; i=i-1) begin
3442
            if (polynom[i])
3443
                lfsr_fb = lfsr_fb  ~^ qi[i];
3444
        end
3445
    end
3446
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
3447
   always @ (qi)
3448
   begin
3449
        case (length)
3450
         2: polynom_rew = 32'b11;
3451
         3: polynom_rew = 32'b110;
3452
         4: polynom_rew = 32'b1100;
3453
         5: polynom_rew = 32'b10100;
3454
         6: polynom_rew = 32'b110000;
3455
         7: polynom_rew = 32'b1100000;
3456
         8: polynom_rew = 32'b10111000;
3457
         9: polynom_rew = 32'b100010000;
3458
        10: polynom_rew = 32'b1001000000;
3459
        11: polynom_rew = 32'b10100000000;
3460
        12: polynom_rew = 32'b100000101001;
3461
        13: polynom_rew = 32'b1000000001100;
3462
        14: polynom_rew = 32'b10000000010101;
3463
        15: polynom_rew = 32'b110000000000000;
3464
        16: polynom_rew = 32'b1101000000001000;
3465
        17: polynom_rew = 32'b10010000000000000;
3466
        18: polynom_rew = 32'b100000010000000000;
3467
        19: polynom_rew = 32'b1000000000000100011;
3468
        20: polynom_rew = 32'b10000010000000000000;
3469
        21: polynom_rew = 32'b101000000000000000000;
3470
        22: polynom_rew = 32'b1100000000000000000000;
3471
        23: polynom_rew = 32'b10000100000000000000000;
3472
        24: polynom_rew = 32'b111000010000000000000000;
3473
        25: polynom_rew = 32'b1001000000000000000000000;
3474
        26: polynom_rew = 32'b10000000000000000000100011;
3475
        27: polynom_rew = 32'b100000000000000000000010011;
3476
        28: polynom_rew = 32'b1100100000000000000000000000;
3477
        29: polynom_rew = 32'b10100000000000000000000000000;
3478
        30: polynom_rew = 32'b100000000000000000000000101001;
3479
        31: polynom_rew = 32'b1001000000000000000000000000000;
3480
        32: polynom_rew = 32'b10000000001000000000000000000011;
3481
        default: polynom_rew = 32'b0;
3482
        endcase
3483
        // rotate left
3484
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
3485
        lfsr_fb_rew = qi[length];
3486
        for (i=length-1; i>=1; i=i-1) begin
3487
            if (polynom_rew[i])
3488
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
3489
        end
3490
    end
3491
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
3492
   assign q_next = rew ? q_next_rew : q_next_fw;
3493
 
3494
   always @ (posedge clk or posedge rst)
3495
     if (rst)
3496
       qi <= {length{1'b0}};
3497
     else
3498
     if (cke)
3499
       qi <= q_next;
3500
 
3501
 
3502
 
3503
    always @ (posedge clk or posedge rst)
3504
    if (rst)
3505
        level1 <= 1'b0;
3506
    else
3507
    if (cke)
3508 29 unneback
    if (clear)
3509
        level1 <= 1'b0;
3510
    else if (q_next == level1_value)
3511 6 unneback
        level1 <= 1'b1;
3512
    else if (qi == level1_value & rew)
3513
        level1 <= 1'b0;
3514
endmodule
3515 40 unneback
`endif
3516
`ifdef CNT_GRAY
3517 6 unneback
//////////////////////////////////////////////////////////////////////
3518
////                                                              ////
3519
////  Versatile counter                                           ////
3520
////                                                              ////
3521
////  Description                                                 ////
3522
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3523
////  counter                                                     ////
3524
////                                                              ////
3525
////  To Do:                                                      ////
3526
////   - add LFSR with more taps                                  ////
3527
////                                                              ////
3528
////  Author(s):                                                  ////
3529
////      - Michael Unneback, unneback@opencores.org              ////
3530
////        ORSoC AB                                              ////
3531
////                                                              ////
3532
//////////////////////////////////////////////////////////////////////
3533
////                                                              ////
3534
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3535
////                                                              ////
3536
//// This source file may be used and distributed without         ////
3537
//// restriction provided that this copyright statement is not    ////
3538
//// removed from the file and that any derivative work contains  ////
3539
//// the original copyright notice and the associated disclaimer. ////
3540
////                                                              ////
3541
//// This source file is free software; you can redistribute it   ////
3542
//// and/or modify it under the terms of the GNU Lesser General   ////
3543
//// Public License as published by the Free Software Foundation; ////
3544
//// either version 2.1 of the License, or (at your option) any   ////
3545
//// later version.                                               ////
3546
////                                                              ////
3547
//// This source is distributed in the hope that it will be       ////
3548
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3549
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3550
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3551
//// details.                                                     ////
3552
////                                                              ////
3553
//// You should have received a copy of the GNU Lesser General    ////
3554
//// Public License along with this source; if not, download it   ////
3555
//// from http://www.opencores.org/lgpl.shtml                     ////
3556
////                                                              ////
3557
//////////////////////////////////////////////////////////////////////
3558
 
3559
// GRAY counter
3560
 
3561 40 unneback
`define MODULE cnt_gray
3562
module `BASE`MODULE (
3563
`undef MODULE
3564
 q, rst, clk);
3565
 
3566 6 unneback
   parameter length = 4;
3567
   output reg [length:1] q;
3568
   input rst;
3569
   input clk;
3570
 
3571
   parameter clear_value = 0;
3572
   parameter set_value = 1;
3573
   parameter wrap_value = 8;
3574
   parameter level1_value = 15;
3575
 
3576
   reg  [length:1] qi;
3577
   wire [length:1] q_next;
3578
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3579
 
3580
   always @ (posedge clk or posedge rst)
3581
     if (rst)
3582
       qi <= {length{1'b0}};
3583
     else
3584
       qi <= q_next;
3585
 
3586
   always @ (posedge clk or posedge rst)
3587
     if (rst)
3588
       q <= {length{1'b0}};
3589
     else
3590
         q <= (q_next>>1) ^ q_next;
3591
 
3592
endmodule
3593 40 unneback
`endif
3594
`ifdef CNT_GRAY_CE
3595 6 unneback
//////////////////////////////////////////////////////////////////////
3596
////                                                              ////
3597
////  Versatile counter                                           ////
3598
////                                                              ////
3599
////  Description                                                 ////
3600
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3601
////  counter                                                     ////
3602
////                                                              ////
3603
////  To Do:                                                      ////
3604
////   - add LFSR with more taps                                  ////
3605
////                                                              ////
3606
////  Author(s):                                                  ////
3607
////      - Michael Unneback, unneback@opencores.org              ////
3608
////        ORSoC AB                                              ////
3609
////                                                              ////
3610
//////////////////////////////////////////////////////////////////////
3611
////                                                              ////
3612
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3613
////                                                              ////
3614
//// This source file may be used and distributed without         ////
3615
//// restriction provided that this copyright statement is not    ////
3616
//// removed from the file and that any derivative work contains  ////
3617
//// the original copyright notice and the associated disclaimer. ////
3618
////                                                              ////
3619
//// This source file is free software; you can redistribute it   ////
3620
//// and/or modify it under the terms of the GNU Lesser General   ////
3621
//// Public License as published by the Free Software Foundation; ////
3622
//// either version 2.1 of the License, or (at your option) any   ////
3623
//// later version.                                               ////
3624
////                                                              ////
3625
//// This source is distributed in the hope that it will be       ////
3626
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3627
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3628
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3629
//// details.                                                     ////
3630
////                                                              ////
3631
//// You should have received a copy of the GNU Lesser General    ////
3632
//// Public License along with this source; if not, download it   ////
3633
//// from http://www.opencores.org/lgpl.shtml                     ////
3634
////                                                              ////
3635
//////////////////////////////////////////////////////////////////////
3636
 
3637
// GRAY counter
3638
 
3639 40 unneback
`define MODULE cnt_gray_ce
3640
module `BASE`MODULE (
3641
`undef MODULE
3642
 cke, q, rst, clk);
3643
 
3644 6 unneback
   parameter length = 4;
3645
   input cke;
3646
   output reg [length:1] q;
3647
   input rst;
3648
   input clk;
3649
 
3650
   parameter clear_value = 0;
3651
   parameter set_value = 1;
3652
   parameter wrap_value = 8;
3653
   parameter level1_value = 15;
3654
 
3655
   reg  [length:1] qi;
3656
   wire [length:1] q_next;
3657
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3658
 
3659
   always @ (posedge clk or posedge rst)
3660
     if (rst)
3661
       qi <= {length{1'b0}};
3662
     else
3663
     if (cke)
3664
       qi <= q_next;
3665
 
3666
   always @ (posedge clk or posedge rst)
3667
     if (rst)
3668
       q <= {length{1'b0}};
3669
     else
3670
       if (cke)
3671
         q <= (q_next>>1) ^ q_next;
3672
 
3673
endmodule
3674 40 unneback
`endif
3675
`ifdef CNT_GRAY_CE_BIN
3676 6 unneback
//////////////////////////////////////////////////////////////////////
3677
////                                                              ////
3678
////  Versatile counter                                           ////
3679
////                                                              ////
3680
////  Description                                                 ////
3681
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3682
////  counter                                                     ////
3683
////                                                              ////
3684
////  To Do:                                                      ////
3685
////   - add LFSR with more taps                                  ////
3686
////                                                              ////
3687
////  Author(s):                                                  ////
3688
////      - Michael Unneback, unneback@opencores.org              ////
3689
////        ORSoC AB                                              ////
3690
////                                                              ////
3691
//////////////////////////////////////////////////////////////////////
3692
////                                                              ////
3693
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3694
////                                                              ////
3695
//// This source file may be used and distributed without         ////
3696
//// restriction provided that this copyright statement is not    ////
3697
//// removed from the file and that any derivative work contains  ////
3698
//// the original copyright notice and the associated disclaimer. ////
3699
////                                                              ////
3700
//// This source file is free software; you can redistribute it   ////
3701
//// and/or modify it under the terms of the GNU Lesser General   ////
3702
//// Public License as published by the Free Software Foundation; ////
3703
//// either version 2.1 of the License, or (at your option) any   ////
3704
//// later version.                                               ////
3705
////                                                              ////
3706
//// This source is distributed in the hope that it will be       ////
3707
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3708
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3709
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3710
//// details.                                                     ////
3711
////                                                              ////
3712
//// You should have received a copy of the GNU Lesser General    ////
3713
//// Public License along with this source; if not, download it   ////
3714
//// from http://www.opencores.org/lgpl.shtml                     ////
3715
////                                                              ////
3716
//////////////////////////////////////////////////////////////////////
3717
 
3718
// GRAY counter
3719
 
3720 40 unneback
`define MODULE cnt_gray_ce_bin
3721
module `BASE`MODULE (
3722
`undef MODULE
3723
 cke, q, q_bin, rst, clk);
3724
 
3725 6 unneback
   parameter length = 4;
3726
   input cke;
3727
   output reg [length:1] q;
3728
   output [length:1] q_bin;
3729
   input rst;
3730
   input clk;
3731
 
3732
   parameter clear_value = 0;
3733
   parameter set_value = 1;
3734
   parameter wrap_value = 8;
3735
   parameter level1_value = 15;
3736
 
3737
   reg  [length:1] qi;
3738
   wire [length:1] q_next;
3739
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3740
 
3741
   always @ (posedge clk or posedge rst)
3742
     if (rst)
3743
       qi <= {length{1'b0}};
3744
     else
3745
     if (cke)
3746
       qi <= q_next;
3747
 
3748
   always @ (posedge clk or posedge rst)
3749
     if (rst)
3750
       q <= {length{1'b0}};
3751
     else
3752
       if (cke)
3753
         q <= (q_next>>1) ^ q_next;
3754
 
3755
   assign q_bin = qi;
3756
 
3757
endmodule
3758 40 unneback
`endif
3759 6 unneback
//////////////////////////////////////////////////////////////////////
3760
////                                                              ////
3761
////  Versatile library, counters                                 ////
3762
////                                                              ////
3763
////  Description                                                 ////
3764
////  counters                                                    ////
3765
////                                                              ////
3766
////                                                              ////
3767
////  To Do:                                                      ////
3768
////   - add more counters                                        ////
3769
////                                                              ////
3770
////  Author(s):                                                  ////
3771
////      - Michael Unneback, unneback@opencores.org              ////
3772
////        ORSoC AB                                              ////
3773
////                                                              ////
3774
//////////////////////////////////////////////////////////////////////
3775
////                                                              ////
3776
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
3777
////                                                              ////
3778
//// This source file may be used and distributed without         ////
3779
//// restriction provided that this copyright statement is not    ////
3780
//// removed from the file and that any derivative work contains  ////
3781
//// the original copyright notice and the associated disclaimer. ////
3782
////                                                              ////
3783
//// This source file is free software; you can redistribute it   ////
3784
//// and/or modify it under the terms of the GNU Lesser General   ////
3785
//// Public License as published by the Free Software Foundation; ////
3786
//// either version 2.1 of the License, or (at your option) any   ////
3787
//// later version.                                               ////
3788
////                                                              ////
3789
//// This source is distributed in the hope that it will be       ////
3790
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3791
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3792
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3793
//// details.                                                     ////
3794
////                                                              ////
3795
//// You should have received a copy of the GNU Lesser General    ////
3796
//// Public License along with this source; if not, download it   ////
3797
//// from http://www.opencores.org/lgpl.shtml                     ////
3798
////                                                              ////
3799
//////////////////////////////////////////////////////////////////////
3800
 
3801 40 unneback
`ifdef CNT_SHREG_WRAP
3802
`define MODULE cnt_shreg_wrap
3803
module `BASE`MODULE ( q, rst, clk);
3804
`undef MODULE
3805 6 unneback
 
3806
   parameter length = 4;
3807
   output reg [0:length-1] q;
3808
   input rst;
3809
   input clk;
3810
 
3811
    always @ (posedge clk or posedge rst)
3812
    if (rst)
3813
        q <= {1'b1,{length-1{1'b0}}};
3814
    else
3815
        q <= {q[length-1],q[0:length-2]};
3816
 
3817
endmodule
3818 40 unneback
`endif
3819 6 unneback
 
3820 40 unneback
`ifdef CNT_SHREG_CE_WRAP
3821
`define MODULE cnt_shreg_ce_wrap
3822
module `BASE`MODULE ( cke, q, rst, clk);
3823
`undef MODULE
3824 6 unneback
 
3825
   parameter length = 4;
3826
   input cke;
3827
   output reg [0:length-1] q;
3828
   input rst;
3829
   input clk;
3830
 
3831
    always @ (posedge clk or posedge rst)
3832
    if (rst)
3833
        q <= {1'b1,{length-1{1'b0}}};
3834
    else
3835
        if (cke)
3836
            q <= {q[length-1],q[0:length-2]};
3837
 
3838
endmodule
3839 40 unneback
`endif
3840 6 unneback
 
3841 105 unneback
`ifdef CNT_SHREG_CLEAR
3842
`define MODULE cnt_shreg_clear
3843
module `BASE`MODULE ( clear, q, rst, clk);
3844
`undef MODULE
3845
 
3846
   parameter length = 4;
3847
   input clear;
3848
   output reg [0:length-1] q;
3849
   input rst;
3850
   input clk;
3851
 
3852
    always @ (posedge clk or posedge rst)
3853
    if (rst)
3854
        q <= {1'b1,{length-1{1'b0}}};
3855
    else
3856
        if (clear)
3857
            q <= {1'b1,{length-1{1'b0}}};
3858
        else
3859
            q <= q >> 1;
3860
 
3861
endmodule
3862
`endif
3863
 
3864 40 unneback
`ifdef CNT_SHREG_CE_CLEAR
3865
`define MODULE cnt_shreg_ce_clear
3866
module `BASE`MODULE ( cke, clear, q, rst, clk);
3867
`undef MODULE
3868 6 unneback
 
3869
   parameter length = 4;
3870
   input cke, clear;
3871
   output reg [0:length-1] q;
3872
   input rst;
3873
   input clk;
3874
 
3875
    always @ (posedge clk or posedge rst)
3876
    if (rst)
3877
        q <= {1'b1,{length-1{1'b0}}};
3878
    else
3879
        if (cke)
3880
            if (clear)
3881
                q <= {1'b1,{length-1{1'b0}}};
3882
            else
3883
                q <= q >> 1;
3884
 
3885
endmodule
3886 40 unneback
`endif
3887 6 unneback
 
3888 40 unneback
`ifdef CNT_SHREG_CE_CLEAR_WRAP
3889
`define MODULE cnt_shreg_ce_clear_wrap
3890
module `BASE`MODULE ( cke, clear, q, rst, clk);
3891
`undef MODULE
3892 6 unneback
 
3893
   parameter length = 4;
3894
   input cke, clear;
3895
   output reg [0:length-1] q;
3896
   input rst;
3897
   input clk;
3898
 
3899
    always @ (posedge clk or posedge rst)
3900
    if (rst)
3901
        q <= {1'b1,{length-1{1'b0}}};
3902
    else
3903
        if (cke)
3904
            if (clear)
3905
                q <= {1'b1,{length-1{1'b0}}};
3906
            else
3907
            q <= {q[length-1],q[0:length-2]};
3908
 
3909
endmodule
3910 40 unneback
`endif
3911 6 unneback
//////////////////////////////////////////////////////////////////////
3912
////                                                              ////
3913
////  Versatile library, memories                                 ////
3914
////                                                              ////
3915
////  Description                                                 ////
3916
////  memories                                                    ////
3917
////                                                              ////
3918
////                                                              ////
3919
////  To Do:                                                      ////
3920
////   - add more memory types                                    ////
3921
////                                                              ////
3922
////  Author(s):                                                  ////
3923
////      - Michael Unneback, unneback@opencores.org              ////
3924
////        ORSoC AB                                              ////
3925
////                                                              ////
3926
//////////////////////////////////////////////////////////////////////
3927
////                                                              ////
3928
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
3929
////                                                              ////
3930
//// This source file may be used and distributed without         ////
3931
//// restriction provided that this copyright statement is not    ////
3932
//// removed from the file and that any derivative work contains  ////
3933
//// the original copyright notice and the associated disclaimer. ////
3934
////                                                              ////
3935
//// This source file is free software; you can redistribute it   ////
3936
//// and/or modify it under the terms of the GNU Lesser General   ////
3937
//// Public License as published by the Free Software Foundation; ////
3938
//// either version 2.1 of the License, or (at your option) any   ////
3939
//// later version.                                               ////
3940
////                                                              ////
3941
//// This source is distributed in the hope that it will be       ////
3942
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3943
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3944
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3945
//// details.                                                     ////
3946
////                                                              ////
3947
//// You should have received a copy of the GNU Lesser General    ////
3948
//// Public License along with this source; if not, download it   ////
3949
//// from http://www.opencores.org/lgpl.shtml                     ////
3950
////                                                              ////
3951
//////////////////////////////////////////////////////////////////////
3952
 
3953 40 unneback
`ifdef ROM_INIT
3954 6 unneback
/// ROM
3955 40 unneback
`define MODULE rom_init
3956
module `BASE`MODULE ( adr, q, clk);
3957
`undef MODULE
3958 6 unneback
 
3959 7 unneback
   parameter data_width = 32;
3960
   parameter addr_width = 8;
3961 75 unneback
   parameter mem_size = 1<<addr_width;
3962 7 unneback
   input [(addr_width-1):0]       adr;
3963
   output reg [(data_width-1):0] q;
3964
   input                         clk;
3965 75 unneback
   reg [data_width-1:0] rom [mem_size-1:0];
3966 7 unneback
   parameter memory_file = "vl_rom.vmem";
3967
   initial
3968
     begin
3969
        $readmemh(memory_file, rom);
3970
     end
3971
 
3972
   always @ (posedge clk)
3973
     q <= rom[adr];
3974 6 unneback
 
3975 7 unneback
endmodule
3976 40 unneback
`endif
3977 7 unneback
 
3978 40 unneback
`ifdef RAM
3979
`define MODULE ram
3980 6 unneback
// Single port RAM
3981 40 unneback
module `BASE`MODULE ( d, adr, we, q, clk);
3982
`undef MODULE
3983 6 unneback
 
3984
   parameter data_width = 32;
3985
   parameter addr_width = 8;
3986 75 unneback
   parameter mem_size = 1<<addr_width;
3987 100 unneback
   parameter debug = 0;
3988 6 unneback
   input [(data_width-1):0]      d;
3989
   input [(addr_width-1):0]       adr;
3990
   input                         we;
3991 7 unneback
   output reg [(data_width-1):0] q;
3992 6 unneback
   input                         clk;
3993 98 unneback
   reg [data_width-1:0] ram [mem_size-1:0];
3994 100 unneback
 
3995
    parameter memory_init = 0;
3996
    parameter memory_file = "vl_ram.vmem";
3997
    generate
3998
    if (memory_init == 1) begin : init_mem
3999
        initial
4000
            $readmemh(memory_file, ram);
4001
   end else if (memory_init == 2) begin : init_zero
4002
        integer k;
4003
        initial
4004
            for (k = 0; k < mem_size; k = k + 1)
4005
                ram[k] = 0;
4006 7 unneback
   end
4007
   endgenerate
4008
 
4009 100 unneback
    generate
4010
    if (debug==1) begin : debug_we
4011
        always @ (posedge clk)
4012
        if (we)
4013
            $display ("Value %h written at address %h : time %t", d, adr, $time);
4014
 
4015
    end
4016
    endgenerate
4017
 
4018 6 unneback
   always @ (posedge clk)
4019
   begin
4020
   if (we)
4021
     ram[adr] <= d;
4022
   q <= ram[adr];
4023
   end
4024
 
4025
endmodule
4026 40 unneback
`endif
4027 6 unneback
 
4028 40 unneback
`ifdef RAM_BE
4029
`define MODULE ram_be
4030 91 unneback
module `BASE`MODULE ( d, adr, be, we, q, clk);
4031 40 unneback
`undef MODULE
4032
 
4033 7 unneback
   parameter data_width = 32;
4034 72 unneback
   parameter addr_width = 6;
4035 75 unneback
   parameter mem_size = 1<<addr_width;
4036 7 unneback
   input [(data_width-1):0]      d;
4037
   input [(addr_width-1):0]       adr;
4038 73 unneback
   input [(data_width/8)-1:0]    be;
4039 7 unneback
   input                         we;
4040
   output reg [(data_width-1):0] q;
4041
   input                         clk;
4042
 
4043 85 unneback
 
4044 65 unneback
`ifdef SYSTEMVERILOG
4045 95 unneback
    // use a multi-dimensional packed array
4046
    //t o model individual bytes within the word
4047
    logic [data_width/8-1:0][7:0] ram [0:mem_size-1];// # words = 1 << address width
4048 65 unneback
`else
4049 85 unneback
    reg [data_width-1:0] ram [mem_size-1:0];
4050
    wire [data_width/8-1:0] cke;
4051 65 unneback
`endif
4052
 
4053 100 unneback
    parameter memory_init = 0;
4054
    parameter memory_file = "vl_ram.vmem";
4055
    generate
4056
    if (memory_init == 1) begin : init_mem
4057
        initial
4058
            $readmemh(memory_file, ram);
4059
    end else if (memory_init == 2) begin : init_zero
4060
        integer k;
4061
        initial
4062
            for (k = 0; k < mem_size; k = k + 1)
4063
                ram[k] = 0;
4064
    end
4065 7 unneback
   endgenerate
4066
 
4067 60 unneback
`ifdef SYSTEMVERILOG
4068
 
4069
always_ff@(posedge clk)
4070
begin
4071 95 unneback
    if(we) begin
4072 86 unneback
        if(be[3]) ram[adr][3] <= d[31:24];
4073
        if(be[2]) ram[adr][2] <= d[23:16];
4074
        if(be[1]) ram[adr][1] <= d[15:8];
4075
        if(be[0]) ram[adr][0] <= d[7:0];
4076 60 unneback
    end
4077 90 unneback
        q <= ram[adr];
4078 60 unneback
end
4079
 
4080
`else
4081
 
4082 85 unneback
assign cke = {data_width/8{we}} & be;
4083 7 unneback
   genvar i;
4084 85 unneback
   generate for (i=0;i<data_width/8;i=i+1) begin : be_ram
4085 7 unneback
      always @ (posedge clk)
4086 85 unneback
      if (cke[i])
4087 7 unneback
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
4088
   end
4089
   endgenerate
4090
 
4091
   always @ (posedge clk)
4092
      q <= ram[adr];
4093
 
4094 60 unneback
`endif
4095
 
4096 93 unneback
`ifdef verilator
4097 85 unneback
   // Function to access RAM (for use by Verilator).
4098
   function [31:0] get_mem;
4099
      // verilator public
4100 90 unneback
      input [addr_width-1:0]             addr;
4101 85 unneback
      get_mem = ram[addr];
4102
   endfunction // get_mem
4103
 
4104
   // Function to write RAM (for use by Verilator).
4105
   function set_mem;
4106
      // verilator public
4107 90 unneback
      input [addr_width-1:0]             addr;
4108
      input [data_width-1:0]             data;
4109 85 unneback
      ram[addr] = data;
4110
   endfunction // set_mem
4111 93 unneback
`endif
4112 85 unneback
 
4113 7 unneback
endmodule
4114 40 unneback
`endif
4115 7 unneback
 
4116 40 unneback
`ifdef DPRAM_1R1W
4117
`define MODULE dpram_1r1w
4118
module `BASE`MODULE ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
4119
`undef MODULE
4120 6 unneback
   parameter data_width = 32;
4121
   parameter addr_width = 8;
4122 75 unneback
   parameter mem_size = 1<<addr_width;
4123 6 unneback
   input [(data_width-1):0]      d_a;
4124
   input [(addr_width-1):0]       adr_a;
4125
   input [(addr_width-1):0]       adr_b;
4126
   input                         we_a;
4127 118 unneback
   output reg [(data_width-1):0]          q_b;
4128 6 unneback
   input                         clk_a, clk_b;
4129 119 unneback
   reg [data_width-1:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
4130 7 unneback
 
4131 100 unneback
    parameter memory_init = 0;
4132
    parameter memory_file = "vl_ram.vmem";
4133
    parameter debug = 0;
4134
 
4135
    generate
4136
    if (memory_init == 1) begin : init_mem
4137
        initial
4138
            $readmemh(memory_file, ram);
4139
    end else if (memory_init == 2) begin : init_zero
4140
        integer k;
4141
        initial
4142
            for (k = 0; k < mem_size; k = k + 1)
4143
                ram[k] = 0;
4144
    end
4145 7 unneback
   endgenerate
4146
 
4147 100 unneback
    generate
4148
    if (debug==1) begin : debug_we
4149
        always @ (posedge clk_a)
4150
        if (we_a)
4151
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
4152
 
4153
    end
4154
    endgenerate
4155
 
4156 6 unneback
   always @ (posedge clk_a)
4157
   if (we_a)
4158
     ram[adr_a] <= d_a;
4159 118 unneback
 
4160 6 unneback
   always @ (posedge clk_b)
4161 118 unneback
      q_b = ram[adr_b];
4162 40 unneback
 
4163 6 unneback
endmodule
4164 40 unneback
`endif
4165 6 unneback
 
4166 40 unneback
`ifdef DPRAM_2R1W
4167
`define MODULE dpram_2r1w
4168
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
4169
`undef MODULE
4170
 
4171 6 unneback
   parameter data_width = 32;
4172
   parameter addr_width = 8;
4173 75 unneback
   parameter mem_size = 1<<addr_width;
4174 6 unneback
   input [(data_width-1):0]      d_a;
4175
   input [(addr_width-1):0]       adr_a;
4176
   input [(addr_width-1):0]       adr_b;
4177
   input                         we_a;
4178
   output [(data_width-1):0]      q_b;
4179
   output reg [(data_width-1):0] q_a;
4180
   input                         clk_a, clk_b;
4181
   reg [(data_width-1):0]         q_b;
4182 119 unneback
   reg [data_width-1:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
4183 7 unneback
 
4184 100 unneback
    parameter memory_init = 0;
4185
    parameter memory_file = "vl_ram.vmem";
4186
    parameter debug = 0;
4187
 
4188
    generate
4189
    if (memory_init == 1) begin : init_mem
4190
        initial
4191
            $readmemh(memory_file, ram);
4192
    end else if (memory_init == 2) begin : init_zero
4193
        integer k;
4194
        initial
4195
            for (k = 0; k < mem_size; k = k + 1)
4196
                ram[k] = 0;
4197
    end
4198 7 unneback
   endgenerate
4199
 
4200 100 unneback
    generate
4201
    if (debug==1) begin : debug_we
4202
        always @ (posedge clk_a)
4203
        if (we_a)
4204
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
4205
 
4206
    end
4207
    endgenerate
4208
 
4209 6 unneback
   always @ (posedge clk_a)
4210
     begin
4211
        q_a <= ram[adr_a];
4212
        if (we_a)
4213
             ram[adr_a] <= d_a;
4214
     end
4215
   always @ (posedge clk_b)
4216
          q_b <= ram[adr_b];
4217
endmodule
4218 40 unneback
`endif
4219 6 unneback
 
4220 100 unneback
`ifdef DPRAM_1R2W
4221
`define MODULE dpram_1r2w
4222
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, adr_b, we_b, clk_b );
4223
`undef MODULE
4224
 
4225
   parameter data_width = 32;
4226
   parameter addr_width = 8;
4227
   parameter mem_size = 1<<addr_width;
4228
   input [(data_width-1):0]      d_a;
4229
   input [(addr_width-1):0]       adr_a;
4230
   input [(addr_width-1):0]       adr_b;
4231
   input                         we_a;
4232
   input [(data_width-1):0]       d_b;
4233
   output reg [(data_width-1):0] q_a;
4234
   input                         we_b;
4235
   input                         clk_a, clk_b;
4236
   reg [(data_width-1):0]         q_b;
4237 119 unneback
   reg [data_width-1:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
4238 100 unneback
 
4239
    parameter memory_init = 0;
4240
    parameter memory_file = "vl_ram.vmem";
4241
    parameter debug = 0;
4242
 
4243
    generate
4244
    if (memory_init == 1) begin : init_mem
4245
        initial
4246
            $readmemh(memory_file, ram);
4247
    end else if (memory_init == 2) begin : init_zero
4248
        integer k;
4249
        initial
4250
            for (k = 0; k < mem_size; k = k + 1)
4251
                ram[k] = 0;
4252
    end
4253
   endgenerate
4254
 
4255
    generate
4256
    if (debug==1) begin : debug_we
4257
        always @ (posedge clk_a)
4258
        if (we_a)
4259
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
4260
        always @ (posedge clk_b)
4261
        if (we_b)
4262
            $display ("Debug: Value %h written at address %h : time %t", d_b, adr_b, $time);
4263
    end
4264
    endgenerate
4265
 
4266
   always @ (posedge clk_a)
4267
     begin
4268
        q_a <= ram[adr_a];
4269
        if (we_a)
4270
             ram[adr_a] <= d_a;
4271
     end
4272
   always @ (posedge clk_b)
4273
     begin
4274
        if (we_b)
4275
          ram[adr_b] <= d_b;
4276
     end
4277
endmodule
4278
`endif
4279
 
4280 40 unneback
`ifdef DPRAM_2R2W
4281
`define MODULE dpram_2r2w
4282
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
4283
`undef MODULE
4284
 
4285 6 unneback
   parameter data_width = 32;
4286
   parameter addr_width = 8;
4287 75 unneback
   parameter mem_size = 1<<addr_width;
4288 6 unneback
   input [(data_width-1):0]      d_a;
4289
   input [(addr_width-1):0]       adr_a;
4290
   input [(addr_width-1):0]       adr_b;
4291
   input                         we_a;
4292
   output [(data_width-1):0]      q_b;
4293
   input [(data_width-1):0]       d_b;
4294
   output reg [(data_width-1):0] q_a;
4295
   input                         we_b;
4296
   input                         clk_a, clk_b;
4297
   reg [(data_width-1):0]         q_b;
4298 119 unneback
   reg [data_width-1:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
4299 7 unneback
 
4300 100 unneback
    parameter memory_init = 0;
4301
    parameter memory_file = "vl_ram.vmem";
4302
    parameter debug = 0;
4303
 
4304
    generate
4305
    if (memory_init) begin : init_mem
4306
        initial
4307
            $readmemh(memory_file, ram);
4308
    end else if (memory_init == 2) begin : init_zero
4309
        integer k;
4310
        initial
4311
            for (k = 0; k < mem_size; k = k + 1)
4312
                ram[k] = 0;
4313
    end
4314 7 unneback
   endgenerate
4315
 
4316 100 unneback
    generate
4317
    if (debug==1) begin : debug_we
4318
        always @ (posedge clk_a)
4319
        if (we_a)
4320
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
4321
        always @ (posedge clk_b)
4322
        if (we_b)
4323
            $display ("Debug: Value %h written at address %h : time %t", d_b, adr_b, $time);
4324
    end
4325
    endgenerate
4326
 
4327 6 unneback
   always @ (posedge clk_a)
4328
     begin
4329
        q_a <= ram[adr_a];
4330
        if (we_a)
4331
             ram[adr_a] <= d_a;
4332
     end
4333
   always @ (posedge clk_b)
4334
     begin
4335
        q_b <= ram[adr_b];
4336
        if (we_b)
4337
          ram[adr_b] <= d_b;
4338
     end
4339
endmodule
4340 40 unneback
`endif
4341 6 unneback
 
4342 83 unneback
 
4343 75 unneback
`ifdef DPRAM_BE_2R2W
4344
`define MODULE dpram_be_2r2w
4345 92 unneback
module `BASE`MODULE ( d_a, q_a, adr_a, be_a, we_a, clk_a, d_b, q_b, adr_b, be_b, we_b, clk_b );
4346 75 unneback
`undef MODULE
4347
 
4348
   parameter a_data_width = 32;
4349
   parameter a_addr_width = 8;
4350 95 unneback
   parameter b_data_width = 64; //a_data_width;
4351 124 unneback
   //localparam b_addr_width = a_data_width * a_addr_width / b_data_width;
4352
   localparam b_addr_width =
4353 125 unneback
        (a_data_width==b_data_width) ? a_addr_width :
4354
        (a_data_width==b_data_width*2) ? a_addr_width+1 :
4355
        (a_data_width==b_data_width*4) ? a_addr_width+2 :
4356
        (a_data_width==b_data_width*8) ? a_addr_width+3 :
4357
        (a_data_width==b_data_width*16) ? a_addr_width+4 :
4358
        (a_data_width==b_data_width*32) ? a_addr_width+5 :
4359
        (a_data_width==b_data_width/2) ? a_addr_width-1 :
4360
        (a_data_width==b_data_width/4) ? a_addr_width-2 :
4361
        (a_data_width==b_data_width/8) ? a_addr_width-3 :
4362
        (a_data_width==b_data_width/16) ? a_addr_width-4 :
4363
        (a_data_width==b_data_width/32) ? a_addr_width-5 : 0;
4364 124 unneback
 
4365 95 unneback
   localparam ratio = (a_addr_width>b_addr_width) ? (a_addr_width/b_addr_width) : (b_addr_width/a_addr_width);
4366
   parameter mem_size = (a_addr_width>b_addr_width) ? (1<<b_addr_width) : (1<<a_addr_width);
4367 91 unneback
 
4368 100 unneback
   parameter memory_init = 0;
4369 95 unneback
   parameter memory_file = "vl_ram.vmem";
4370 100 unneback
   parameter debug = 0;
4371 95 unneback
 
4372 75 unneback
   input [(a_data_width-1):0]      d_a;
4373 91 unneback
   input [(a_addr_width-1):0]       adr_a;
4374
   input [(a_data_width/8-1):0]    be_a;
4375
   input                           we_a;
4376 75 unneback
   output reg [(a_data_width-1):0] q_a;
4377 91 unneback
   input [(b_data_width-1):0]       d_b;
4378
   input [(b_addr_width-1):0]       adr_b;
4379 92 unneback
   input [(b_data_width/8-1):0]    be_b;
4380
   input                           we_b;
4381
   output reg [(b_data_width-1):0]          q_b;
4382 91 unneback
   input                           clk_a, clk_b;
4383 75 unneback
 
4384 100 unneback
    generate
4385
    if (debug==1) begin : debug_we
4386
        always @ (posedge clk_a)
4387
        if (we_a)
4388 141 unneback
            $display ("Debug: Value %h written on port A at address %h : time %t", d_a, adr_a, $time);
4389 100 unneback
        always @ (posedge clk_b)
4390
        if (we_b)
4391 141 unneback
            $display ("Debug: Value %h written on port B at address %h : time %t", d_b, adr_b, $time);
4392 100 unneback
    end
4393
    endgenerate
4394
 
4395
 
4396 91 unneback
`ifdef SYSTEMVERILOG
4397
// use a multi-dimensional packed array
4398
//to model individual bytes within the word
4399
 
4400 75 unneback
generate
4401 91 unneback
if (a_data_width==32 & b_data_width==32) begin : dpram_3232
4402 75 unneback
 
4403 98 unneback
    logic [0:3][7:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
4404 95 unneback
 
4405
    initial
4406 100 unneback
        if (memory_init==1)
4407 95 unneback
            $readmemh(memory_file, ram);
4408 100 unneback
 
4409
    integer k;
4410
    initial
4411
        if (memory_init==2)
4412
            for (k = 0; k < mem_size; k = k + 1)
4413
                ram[k] = 0;
4414 91 unneback
 
4415
    always_ff@(posedge clk_a)
4416
    begin
4417
        if(we_a) begin
4418 100 unneback
            if(be_a[3]) ram[adr_a][0] <= d_a[31:24];
4419
            if(be_a[2]) ram[adr_a][1] <= d_a[23:16];
4420
            if(be_a[1]) ram[adr_a][2] <= d_a[15:8];
4421
            if(be_a[0]) ram[adr_a][3] <= d_a[7:0];
4422 91 unneback
        end
4423
    end
4424
 
4425 92 unneback
    always@(posedge clk_a)
4426
        q_a = ram[adr_a];
4427 91 unneback
 
4428
    always_ff@(posedge clk_b)
4429 92 unneback
    begin
4430
        if(we_b) begin
4431 100 unneback
            if(be_b[3]) ram[adr_b][0] <= d_b[31:24];
4432
            if(be_b[2]) ram[adr_b][1] <= d_b[23:16];
4433
            if(be_b[1]) ram[adr_b][2] <= d_b[15:8];
4434
            if(be_b[0]) ram[adr_b][3] <= d_b[7:0];
4435 92 unneback
        end
4436
    end
4437 91 unneback
 
4438 92 unneback
    always@(posedge clk_b)
4439
        q_b = ram[adr_b];
4440 91 unneback
 
4441 75 unneback
end
4442
endgenerate
4443
 
4444 95 unneback
generate
4445
if (a_data_width==64 & b_data_width==64) begin : dpram_6464
4446
 
4447 98 unneback
    logic [0:7][7:0] ram [0:mem_size-1] `SYN_NO_RW_CHECK;
4448 95 unneback
 
4449
    initial
4450 100 unneback
        if (memory_init==1)
4451 95 unneback
            $readmemh(memory_file, ram);
4452 100 unneback
 
4453
    integer k;
4454
    initial
4455
        if (memory_init==2)
4456
            for (k = 0; k < mem_size; k = k + 1)
4457
                ram[k] = 0;
4458 95 unneback
 
4459
    always_ff@(posedge clk_a)
4460
    begin
4461
        if(we_a) begin
4462
            if(be_a[7]) ram[adr_a][7] <= d_a[63:56];
4463
            if(be_a[6]) ram[adr_a][6] <= d_a[55:48];
4464
            if(be_a[5]) ram[adr_a][5] <= d_a[47:40];
4465
            if(be_a[4]) ram[adr_a][4] <= d_a[39:32];
4466
            if(be_a[3]) ram[adr_a][3] <= d_a[31:24];
4467
            if(be_a[2]) ram[adr_a][2] <= d_a[23:16];
4468
            if(be_a[1]) ram[adr_a][1] <= d_a[15:8];
4469
            if(be_a[0]) ram[adr_a][0] <= d_a[7:0];
4470
        end
4471
    end
4472
 
4473
    always@(posedge clk_a)
4474
        q_a = ram[adr_a];
4475
 
4476
    always_ff@(posedge clk_b)
4477
    begin
4478
        if(we_b) begin
4479
            if(be_b[7]) ram[adr_b][7] <= d_b[63:56];
4480
            if(be_b[6]) ram[adr_b][6] <= d_b[55:48];
4481
            if(be_b[5]) ram[adr_b][5] <= d_b[47:40];
4482
            if(be_b[4]) ram[adr_b][4] <= d_b[39:32];
4483
            if(be_b[3]) ram[adr_b][3] <= d_b[31:24];
4484
            if(be_b[2]) ram[adr_b][2] <= d_b[23:16];
4485
            if(be_b[1]) ram[adr_b][1] <= d_b[15:8];
4486
            if(be_b[0]) ram[adr_b][0] <= d_b[7:0];
4487
        end
4488
    end
4489
 
4490
    always@(posedge clk_b)
4491
        q_b = ram[adr_b];
4492
 
4493
end
4494
endgenerate
4495
 
4496
generate
4497
if (a_data_width==32 & b_data_width==16) begin : dpram_3216
4498
logic [31:0] temp;
4499
`define MODULE dpram_be_2r2w
4500 128 unneback
`BASE`MODULE # (.a_data_width(32), .b_data_width(32), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file))
4501 95 unneback
`undef MODULE
4502 128 unneback
dpram3232 (
4503 95 unneback
    .d_a(d_a),
4504
    .q_a(q_a),
4505
    .adr_a(adr_a),
4506
    .be_a(be_a),
4507
    .we_a(we_a),
4508
    .clk_a(clk_a),
4509
    .d_b({d_b,d_b}),
4510
    .q_b(temp),
4511 128 unneback
    .adr_b(adr_b[b_addr_width-1:1]),
4512 137 unneback
    .be_b({be_b,be_b} & {{2{!adr_b[0]}},{2{adr_b[0]}}}),
4513 95 unneback
    .we_b(we_b),
4514
    .clk_b(clk_b)
4515
);
4516
 
4517 100 unneback
always @ (adr_b[0] or temp)
4518 95 unneback
    if (adr_b[0])
4519
        q_b = temp[31:16];
4520
    else
4521
        q_b = temp[15:0];
4522
 
4523
end
4524
endgenerate
4525
 
4526
generate
4527
if (a_data_width==32 & b_data_width==64) begin : dpram_3264
4528
logic [63:0] temp;
4529
`define MODULE dpram_be_2r2w
4530 128 unneback
`BASE`MODULE # (.a_data_width(32), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file))
4531 95 unneback
`undef MODULE
4532
dpram6464 (
4533
    .d_a({d_a,d_a}),
4534
    .q_a(temp),
4535
    .adr_a(adr_a[a_addr_width-1:1]),
4536
    .be_a({be_a,be_a} & {{4{adr_a[0]}},{4{!adr_a[0]}}}),
4537
    .we_a(we_a),
4538
    .clk_a(clk_a),
4539
    .d_b(d_b),
4540
    .q_b(q_b),
4541
    .adr_b(adr_b),
4542
    .be_b(be_b),
4543
    .we_b(we_b),
4544
    .clk_b(clk_b)
4545
);
4546
 
4547 100 unneback
always @ (adr_a[0] or temp)
4548 95 unneback
    if (adr_a[0])
4549
        q_a = temp[63:32];
4550
    else
4551
        q_a = temp[31:0];
4552
 
4553
end
4554
endgenerate
4555
 
4556 91 unneback
`else
4557 92 unneback
    // This modules requires SystemVerilog
4558 98 unneback
    // at this point anyway
4559 91 unneback
`endif
4560 75 unneback
endmodule
4561
`endif
4562
 
4563 91 unneback
`ifdef CAM
4564 6 unneback
// Content addresable memory, CAM
4565 91 unneback
`endif
4566 6 unneback
 
4567 40 unneback
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
4568 6 unneback
// FIFO
4569 40 unneback
`define MODULE fifo_1r1w_fill_level_sync
4570
module `BASE`MODULE (
4571
`undef MODULE
4572 25 unneback
    d, wr, fifo_full,
4573
    q, rd, fifo_empty,
4574
    fill_level,
4575
    clk, rst
4576
    );
4577
 
4578
parameter data_width = 18;
4579
parameter addr_width = 4;
4580 6 unneback
 
4581 25 unneback
// write side
4582
input  [data_width-1:0] d;
4583
input                   wr;
4584
output                  fifo_full;
4585
// read side
4586
output [data_width-1:0] q;
4587
input                   rd;
4588
output                  fifo_empty;
4589
// common
4590
output [addr_width:0]   fill_level;
4591
input rst, clk;
4592
 
4593
wire [addr_width:1] wadr, radr;
4594
 
4595 40 unneback
`define MODULE cnt_bin_ce
4596
`BASE`MODULE
4597 25 unneback
    # ( .length(addr_width))
4598
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
4599 40 unneback
`BASE`MODULE
4600 25 unneback
    # (.length(addr_width))
4601
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
4602 40 unneback
`undef MODULE
4603 25 unneback
 
4604 40 unneback
`define MODULE dpram_1r1w
4605
`BASE`MODULE
4606 25 unneback
    # (.data_width(data_width), .addr_width(addr_width))
4607
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
4608 40 unneback
`undef MODULE
4609 25 unneback
 
4610 40 unneback
`define MODULE cnt_bin_ce_rew_q_zq_l1
4611
`BASE`MODULE
4612 27 unneback
    # (.length(addr_width+1), .level1_value(1<<addr_width))
4613 25 unneback
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
4614 40 unneback
`undef MODULE
4615 25 unneback
endmodule
4616 40 unneback
`endif
4617 25 unneback
 
4618 40 unneback
`ifdef FIFO_2R2W_SYNC_SIMPLEX
4619 27 unneback
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
4620
// RAM is supposed to be larger than the two FIFOs
4621
// LFSR counters used adr pointers
4622 40 unneback
`define MODULE fifo_2r2w_sync_simplex
4623
module `BASE`MODULE (
4624
`undef MODULE
4625 27 unneback
    // a side
4626
    a_d, a_wr, a_fifo_full,
4627
    a_q, a_rd, a_fifo_empty,
4628
    a_fill_level,
4629
    // b side
4630
    b_d, b_wr, b_fifo_full,
4631
    b_q, b_rd, b_fifo_empty,
4632
    b_fill_level,
4633
    // common
4634
    clk, rst
4635
    );
4636
parameter data_width = 8;
4637
parameter addr_width = 5;
4638
parameter fifo_full_level = (1<<addr_width)-1;
4639
 
4640
// a side
4641
input  [data_width-1:0] a_d;
4642
input                   a_wr;
4643
output                  a_fifo_full;
4644
output [data_width-1:0] a_q;
4645
input                   a_rd;
4646
output                  a_fifo_empty;
4647
output [addr_width-1:0] a_fill_level;
4648
 
4649
// b side
4650
input  [data_width-1:0] b_d;
4651
input                   b_wr;
4652
output                  b_fifo_full;
4653
output [data_width-1:0] b_q;
4654
input                   b_rd;
4655
output                  b_fifo_empty;
4656
output [addr_width-1:0] b_fill_level;
4657
 
4658
input                   clk;
4659
input                   rst;
4660
 
4661
// adr_gen
4662
wire [addr_width:1] a_wadr, a_radr;
4663
wire [addr_width:1] b_wadr, b_radr;
4664
// dpram
4665
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
4666
 
4667 40 unneback
`define MODULE cnt_lfsr_ce
4668
`BASE`MODULE
4669 27 unneback
    # ( .length(addr_width))
4670
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
4671
 
4672 40 unneback
`BASE`MODULE
4673 27 unneback
    # (.length(addr_width))
4674
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
4675
 
4676 40 unneback
`BASE`MODULE
4677 27 unneback
    # ( .length(addr_width))
4678
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
4679
 
4680 40 unneback
`BASE`MODULE
4681 27 unneback
    # (.length(addr_width))
4682
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
4683 40 unneback
`undef MODULE
4684 27 unneback
 
4685
// mux read or write adr to DPRAM
4686
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
4687
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
4688
 
4689 40 unneback
`define MODULE dpram_2r2w
4690
`BASE`MODULE
4691 27 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
4692
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
4693
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
4694 40 unneback
`undef MODULE
4695
 
4696
`define MODULE cnt_bin_ce_rew_zq_l1
4697
`BASE`MODULE
4698 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
4699 27 unneback
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
4700
 
4701 40 unneback
`BASE`MODULE
4702 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
4703 27 unneback
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
4704 40 unneback
`undef MODULE
4705 27 unneback
 
4706
endmodule
4707 40 unneback
`endif
4708 27 unneback
 
4709 40 unneback
`ifdef FIFO_CMP_ASYNC
4710
`define MODULE fifo_cmp_async
4711
module `BASE`MODULE ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
4712
`undef MODULE
4713 6 unneback
 
4714 11 unneback
   parameter addr_width = 4;
4715
   parameter N = addr_width-1;
4716 6 unneback
 
4717
   parameter Q1 = 2'b00;
4718
   parameter Q2 = 2'b01;
4719
   parameter Q3 = 2'b11;
4720
   parameter Q4 = 2'b10;
4721
 
4722
   parameter going_empty = 1'b0;
4723
   parameter going_full  = 1'b1;
4724
 
4725
   input [N:0]  wptr, rptr;
4726 14 unneback
   output       fifo_empty;
4727 6 unneback
   output       fifo_full;
4728
   input        wclk, rclk, rst;
4729
 
4730
`ifndef GENERATE_DIRECTION_AS_LATCH
4731
   wire direction;
4732
`endif
4733
`ifdef GENERATE_DIRECTION_AS_LATCH
4734
   reg direction;
4735
`endif
4736
   reg  direction_set, direction_clr;
4737
 
4738
   wire async_empty, async_full;
4739
   wire fifo_full2;
4740 14 unneback
   wire fifo_empty2;
4741 6 unneback
 
4742
   // direction_set
4743
   always @ (wptr[N:N-1] or rptr[N:N-1])
4744
     case ({wptr[N:N-1],rptr[N:N-1]})
4745
       {Q1,Q2} : direction_set <= 1'b1;
4746
       {Q2,Q3} : direction_set <= 1'b1;
4747
       {Q3,Q4} : direction_set <= 1'b1;
4748
       {Q4,Q1} : direction_set <= 1'b1;
4749
       default : direction_set <= 1'b0;
4750
     endcase
4751
 
4752
   // direction_clear
4753
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
4754
     if (rst)
4755
       direction_clr <= 1'b1;
4756
     else
4757
       case ({wptr[N:N-1],rptr[N:N-1]})
4758
         {Q2,Q1} : direction_clr <= 1'b1;
4759
         {Q3,Q2} : direction_clr <= 1'b1;
4760
         {Q4,Q3} : direction_clr <= 1'b1;
4761
         {Q1,Q4} : direction_clr <= 1'b1;
4762
         default : direction_clr <= 1'b0;
4763
       endcase
4764
 
4765 40 unneback
`define MODULE dff_sr
4766 6 unneback
`ifndef GENERATE_DIRECTION_AS_LATCH
4767 40 unneback
    `BASE`MODULE dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
4768 6 unneback
`endif
4769
 
4770
`ifdef GENERATE_DIRECTION_AS_LATCH
4771
   always @ (posedge direction_set or posedge direction_clr)
4772
     if (direction_clr)
4773
       direction <= going_empty;
4774
     else
4775
       direction <= going_full;
4776
`endif
4777
 
4778
   assign async_empty = (wptr == rptr) && (direction==going_empty);
4779
   assign async_full  = (wptr == rptr) && (direction==going_full);
4780
 
4781 40 unneback
    `BASE`MODULE dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
4782
    `BASE`MODULE dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
4783
`undef MODULE
4784 6 unneback
 
4785
/*
4786
   always @ (posedge wclk or posedge rst or posedge async_full)
4787
     if (rst)
4788
       {fifo_full, fifo_full2} <= 2'b00;
4789
     else if (async_full)
4790
       {fifo_full, fifo_full2} <= 2'b11;
4791
     else
4792
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
4793
*/
4794 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
4795 6 unneback
     if (async_empty)
4796
       {fifo_empty, fifo_empty2} <= 2'b11;
4797
     else
4798 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
4799 40 unneback
`define MODULE dff
4800
    `BASE`MODULE # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
4801
    `BASE`MODULE # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
4802
`undef MODULE
4803 27 unneback
endmodule // async_compb
4804 40 unneback
`endif
4805 6 unneback
 
4806 40 unneback
`ifdef FIFO_1R1W_ASYNC
4807
`define MODULE fifo_1r1w_async
4808
module `BASE`MODULE (
4809
`undef MODULE
4810 6 unneback
    d, wr, fifo_full, wr_clk, wr_rst,
4811
    q, rd, fifo_empty, rd_clk, rd_rst
4812
    );
4813
 
4814
parameter data_width = 18;
4815
parameter addr_width = 4;
4816
 
4817
// write side
4818
input  [data_width-1:0] d;
4819
input                   wr;
4820
output                  fifo_full;
4821
input                   wr_clk;
4822
input                   wr_rst;
4823
// read side
4824
output [data_width-1:0] q;
4825
input                   rd;
4826
output                  fifo_empty;
4827
input                   rd_clk;
4828
input                   rd_rst;
4829
 
4830
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
4831 23 unneback
 
4832 40 unneback
`define MODULE cnt_gray_ce_bin
4833
`BASE`MODULE
4834 6 unneback
    # ( .length(addr_width))
4835
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
4836
 
4837 40 unneback
`BASE`MODULE
4838 6 unneback
    # (.length(addr_width))
4839 23 unneback
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
4840 40 unneback
`undef MODULE
4841 6 unneback
 
4842 40 unneback
`define MODULE dpram_1r1w
4843
`BASE`MODULE
4844 6 unneback
    # (.data_width(data_width), .addr_width(addr_width))
4845
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
4846 40 unneback
`undef MODULE
4847 6 unneback
 
4848 40 unneback
`define MODULE fifo_cmp_async
4849
`BASE`MODULE
4850 6 unneback
    # (.addr_width(addr_width))
4851
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
4852 40 unneback
`undef MODULE
4853 6 unneback
 
4854
endmodule
4855 40 unneback
`endif
4856 6 unneback
 
4857 40 unneback
`ifdef FIFO_2R2W_ASYNC
4858
`define MODULE fifo_2r2w_async
4859
module `BASE`MODULE (
4860
`undef MODULE
4861 6 unneback
    // a side
4862
    a_d, a_wr, a_fifo_full,
4863
    a_q, a_rd, a_fifo_empty,
4864
    a_clk, a_rst,
4865
    // b side
4866
    b_d, b_wr, b_fifo_full,
4867
    b_q, b_rd, b_fifo_empty,
4868
    b_clk, b_rst
4869
    );
4870
 
4871
parameter data_width = 18;
4872
parameter addr_width = 4;
4873
 
4874
// a side
4875
input  [data_width-1:0] a_d;
4876
input                   a_wr;
4877
output                  a_fifo_full;
4878
output [data_width-1:0] a_q;
4879
input                   a_rd;
4880
output                  a_fifo_empty;
4881
input                   a_clk;
4882
input                   a_rst;
4883
 
4884
// b side
4885
input  [data_width-1:0] b_d;
4886
input                   b_wr;
4887
output                  b_fifo_full;
4888
output [data_width-1:0] b_q;
4889
input                   b_rd;
4890
output                  b_fifo_empty;
4891
input                   b_clk;
4892
input                   b_rst;
4893
 
4894 40 unneback
`define MODULE fifo_1r1w_async
4895
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
4896 6 unneback
vl_fifo_1r1w_async_a (
4897
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
4898
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
4899
    );
4900
 
4901 40 unneback
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
4902 6 unneback
vl_fifo_1r1w_async_b (
4903
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
4904
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
4905
    );
4906 40 unneback
`undef MODULE
4907
 
4908 6 unneback
endmodule
4909 40 unneback
`endif
4910 6 unneback
 
4911 40 unneback
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
4912
`define MODULE fifo_2r2w_async_simplex
4913
module `BASE`MODULE (
4914
`undef MODULE
4915 6 unneback
    // a side
4916
    a_d, a_wr, a_fifo_full,
4917
    a_q, a_rd, a_fifo_empty,
4918
    a_clk, a_rst,
4919
    // b side
4920
    b_d, b_wr, b_fifo_full,
4921
    b_q, b_rd, b_fifo_empty,
4922
    b_clk, b_rst
4923
    );
4924
 
4925
parameter data_width = 18;
4926
parameter addr_width = 4;
4927
 
4928
// a side
4929
input  [data_width-1:0] a_d;
4930
input                   a_wr;
4931
output                  a_fifo_full;
4932
output [data_width-1:0] a_q;
4933
input                   a_rd;
4934
output                  a_fifo_empty;
4935
input                   a_clk;
4936
input                   a_rst;
4937
 
4938
// b side
4939
input  [data_width-1:0] b_d;
4940
input                   b_wr;
4941
output                  b_fifo_full;
4942
output [data_width-1:0] b_q;
4943
input                   b_rd;
4944
output                  b_fifo_empty;
4945
input                   b_clk;
4946
input                   b_rst;
4947
 
4948
// adr_gen
4949
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
4950
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
4951
// dpram
4952
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
4953
 
4954 40 unneback
`define MODULE cnt_gray_ce_bin
4955
`BASE`MODULE
4956 6 unneback
    # ( .length(addr_width))
4957
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
4958
 
4959 40 unneback
`BASE`MODULE
4960 6 unneback
    # (.length(addr_width))
4961
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
4962
 
4963 40 unneback
`BASE`MODULE
4964 6 unneback
    # ( .length(addr_width))
4965
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
4966
 
4967 40 unneback
`BASE`MODULE
4968 6 unneback
    # (.length(addr_width))
4969
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
4970 40 unneback
`undef MODULE
4971 6 unneback
 
4972
// mux read or write adr to DPRAM
4973
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
4974
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
4975
 
4976 40 unneback
`define MODULE dpram_2r2w
4977
`BASE`MODULE
4978 6 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
4979
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
4980
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
4981 40 unneback
`undef MODULE
4982 6 unneback
 
4983 40 unneback
`define MODULE fifo_cmp_async
4984
`BASE`MODULE
4985 6 unneback
    # (.addr_width(addr_width))
4986
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
4987
 
4988 40 unneback
`BASE`MODULE
4989 6 unneback
    # (.addr_width(addr_width))
4990
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
4991 40 unneback
`undef MODULE
4992 6 unneback
 
4993
endmodule
4994 40 unneback
`endif
4995 48 unneback
 
4996
`ifdef REG_FILE
4997
`define MODULE reg_file
4998
module `BASE`MODULE (
4999
`undef MODULE
5000
    a1, a2, a3, wd3, we3, rd1, rd2, clk
5001
);
5002
parameter data_width = 32;
5003
parameter addr_width = 5;
5004
input [addr_width-1:0] a1, a2, a3;
5005
input [data_width-1:0] wd3;
5006
input we3;
5007
output [data_width-1:0] rd1, rd2;
5008
input clk;
5009
 
5010
`ifdef ACTEL
5011
reg [data_width-1:0] wd3_reg;
5012
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
5013
reg we3_reg;
5014 98 unneback
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] `SYN_NO_RW_CHECK;
5015
reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] `SYN_NO_RW_CHECK;
5016 48 unneback
always @ (posedge clk or posedge rst)
5017
if (rst)
5018
    {wd3_reg, a3_reg, we3_reg} <= {(data_width+addr_width+1){1'b0}};
5019
else
5020
    {wd3_reg, a3_reg, we3_reg} <= {wd3,a3,wd3};
5021
 
5022
    always @ (negedge clk)
5023
    if (we3_reg)
5024
        ram1[a3_reg] <= wd3;
5025
    always @ (posedge clk)
5026
        a1_reg <= a1;
5027
    assign rd1 = ram1[a1_reg];
5028
 
5029
    always @ (negedge clk)
5030
    if (we3_reg)
5031
        ram2[a3_reg] <= wd3;
5032
    always @ (posedge clk)
5033
        a2_reg <= a2;
5034
    assign rd2 = ram2[a2_reg];
5035
 
5036
`else
5037
 
5038
`define MODULE dpram_1r1w
5039
`BASE`MODULE
5040
    # ( .data_width(data_width), .addr_width(addr_width))
5041
    ram1 (
5042
        .d_a(wd3),
5043
        .adr_a(a3),
5044
        .we_a(we3),
5045
        .clk_a(clk),
5046
        .q_b(rd1),
5047
        .adr_b(a1),
5048
        .clk_b(clk) );
5049
 
5050
`BASE`MODULE
5051
    # ( .data_width(data_width), .addr_width(addr_width))
5052
    ram2 (
5053
        .d_a(wd3),
5054
        .adr_a(a3),
5055
        .we_a(we3),
5056
        .clk_a(clk),
5057
        .q_b(rd2),
5058
        .adr_b(a2),
5059
        .clk_b(clk) );
5060
`undef MODULE
5061
 
5062
`endif
5063
 
5064
endmodule
5065
`endif
5066 12 unneback
//////////////////////////////////////////////////////////////////////
5067
////                                                              ////
5068
////  Versatile library, wishbone stuff                           ////
5069
////                                                              ////
5070
////  Description                                                 ////
5071
////  Wishbone compliant modules                                  ////
5072
////                                                              ////
5073
////                                                              ////
5074
////  To Do:                                                      ////
5075
////   -                                                          ////
5076
////                                                              ////
5077
////  Author(s):                                                  ////
5078
////      - Michael Unneback, unneback@opencores.org              ////
5079
////        ORSoC AB                                              ////
5080
////                                                              ////
5081
//////////////////////////////////////////////////////////////////////
5082
////                                                              ////
5083
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
5084
////                                                              ////
5085
//// This source file may be used and distributed without         ////
5086
//// restriction provided that this copyright statement is not    ////
5087
//// removed from the file and that any derivative work contains  ////
5088
//// the original copyright notice and the associated disclaimer. ////
5089
////                                                              ////
5090
//// This source file is free software; you can redistribute it   ////
5091
//// and/or modify it under the terms of the GNU Lesser General   ////
5092
//// Public License as published by the Free Software Foundation; ////
5093
//// either version 2.1 of the License, or (at your option) any   ////
5094
//// later version.                                               ////
5095
////                                                              ////
5096
//// This source is distributed in the hope that it will be       ////
5097
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
5098
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
5099
//// PURPOSE.  See the GNU Lesser General Public License for more ////
5100
//// details.                                                     ////
5101
////                                                              ////
5102
//// You should have received a copy of the GNU Lesser General    ////
5103
//// Public License along with this source; if not, download it   ////
5104
//// from http://www.opencores.org/lgpl.shtml                     ////
5105
////                                                              ////
5106
//////////////////////////////////////////////////////////////////////
5107
 
5108 75 unneback
`ifdef WB_ADR_INC
5109
`timescale 1ns/1ns
5110
`define MODULE wb_adr_inc
5111 85 unneback
module `BASE`MODULE ( cyc_i, stb_i, cti_i, bte_i, adr_i, we_i, ack_o, adr_o, clk, rst);
5112 75 unneback
`undef MODULE
5113 83 unneback
parameter adr_width = 10;
5114
parameter max_burst_width = 4;
5115 85 unneback
input cyc_i, stb_i, we_i;
5116 83 unneback
input [2:0] cti_i;
5117
input [1:0] bte_i;
5118
input [adr_width-1:0] adr_i;
5119
output [adr_width-1:0] adr_o;
5120
output ack_o;
5121
input clk, rst;
5122 75 unneback
 
5123 83 unneback
reg [adr_width-1:0] adr;
5124 90 unneback
wire [max_burst_width-1:0] to_adr;
5125 91 unneback
reg [max_burst_width-1:0] last_adr;
5126 92 unneback
reg last_cycle;
5127
localparam idle_or_eoc = 1'b0;
5128
localparam cyc_or_ws   = 1'b1;
5129 90 unneback
 
5130 91 unneback
always @ (posedge clk or posedge rst)
5131
if (rst)
5132
    last_adr <= {max_burst_width{1'b0}};
5133
else
5134
    if (stb_i)
5135 92 unneback
        last_adr <=adr_o[max_burst_width-1:0];
5136 91 unneback
 
5137 83 unneback
generate
5138
if (max_burst_width==0) begin : inst_0
5139 97 unneback
 
5140
        reg ack_o;
5141
        assign adr_o = adr_i;
5142
        always @ (posedge clk or posedge rst)
5143
        if (rst)
5144
            ack_o <= 1'b0;
5145
        else
5146
            ack_o <= cyc_i & stb_i & !ack_o;
5147
 
5148 83 unneback
end else begin
5149
 
5150
    always @ (posedge clk or posedge rst)
5151
    if (rst)
5152 92 unneback
        last_cycle <= idle_or_eoc;
5153 83 unneback
    else
5154 92 unneback
        last_cycle <= (!cyc_i) ? idle_or_eoc : //idle
5155
                      (cyc_i & ack_o & (cti_i==3'b000 | cti_i==3'b111)) ? idle_or_eoc : // eoc
5156
                      (cyc_i & !stb_i) ? cyc_or_ws : //ws
5157
                      cyc_or_ws; // cyc
5158
    assign to_adr = (last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
5159 85 unneback
    assign adr_o[max_burst_width-1:0] = (we_i) ? adr_i[max_burst_width-1:0] :
5160 91 unneback
                                        (!stb_i) ? last_adr :
5161 92 unneback
                                        (last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] :
5162 85 unneback
                                        adr[max_burst_width-1:0];
5163 92 unneback
    assign ack_o = (last_cycle==cyc_or_ws) & stb_i;
5164 97 unneback
 
5165 83 unneback
end
5166
endgenerate
5167
 
5168
generate
5169
if (max_burst_width==2) begin : inst_2
5170
    always @ (posedge clk or posedge rst)
5171
    if (rst)
5172
        adr <= 2'h0;
5173
    else
5174
        if (cyc_i & stb_i)
5175
            adr[1:0] <= to_adr[1:0] + 2'd1;
5176 75 unneback
        else
5177 83 unneback
            adr <= to_adr[1:0];
5178
end
5179
endgenerate
5180
 
5181
generate
5182
if (max_burst_width==3) begin : inst_3
5183
    always @ (posedge clk or posedge rst)
5184
    if (rst)
5185
        adr <= 3'h0;
5186
    else
5187
        if (cyc_i & stb_i)
5188
            case (bte_i)
5189
            2'b01: adr[2:0] <= {to_adr[2],to_adr[1:0] + 2'd1};
5190
            default: adr[3:0] <= to_adr[2:0] + 3'd1;
5191 75 unneback
            endcase
5192 83 unneback
        else
5193
            adr <= to_adr[2:0];
5194
end
5195
endgenerate
5196
 
5197
generate
5198
if (max_burst_width==4) begin : inst_4
5199
    always @ (posedge clk or posedge rst)
5200
    if (rst)
5201
        adr <= 4'h0;
5202
    else
5203 91 unneback
        if (stb_i) // | (!stb_i & last_cycle!=ws)) // for !stb_i restart with adr_i +1, only inc once
5204 83 unneback
            case (bte_i)
5205
            2'b01: adr[3:0] <= {to_adr[3:2],to_adr[1:0] + 2'd1};
5206
            2'b10: adr[3:0] <= {to_adr[3],to_adr[2:0] + 3'd1};
5207
            default: adr[3:0] <= to_adr + 4'd1;
5208
            endcase
5209
        else
5210
            adr <= to_adr[3:0];
5211
end
5212
endgenerate
5213
 
5214
generate
5215
if (adr_width > max_burst_width) begin : pass_through
5216
    assign adr_o[adr_width-1:max_burst_width] = adr_i[adr_width-1:max_burst_width];
5217
end
5218
endgenerate
5219
 
5220
endmodule
5221 75 unneback
`endif
5222
 
5223 105 unneback
`ifdef WB_B4_EOC
5224
`define MODULE wb_b4_eoc
5225
module `BASE`MODULE ( cyc_i, stb_i, stall_o, ack_o, busy, eoc, clk, rst);
5226
`undef MODULE
5227
input cyc_i, stb_i, ack_o;
5228
output busy, eoc;
5229
input clk, rst;
5230
 
5231
`define MODULE cnt_bin_ce_rew_zq_l1
5232
`BASE`MODULE # ( .length(4), level1_value(1))
5233
cnt0 (
5234
    .cke(), .rew(), .zq(), .level1(), .rst(), clk);
5235
`undef MODULE
5236
 
5237
endmodule
5238
`endif
5239
 
5240 40 unneback
`ifdef WB3WB3_BRIDGE
5241 12 unneback
// async wb3 - wb3 bridge
5242
`timescale 1ns/1ns
5243 40 unneback
`define MODULE wb3wb3_bridge
5244
module `BASE`MODULE (
5245
`undef MODULE
5246 12 unneback
        // wishbone slave side
5247
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
5248
        // wishbone master side
5249
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
5250
 
5251 95 unneback
parameter style = "FIFO"; // valid: simple, FIFO
5252
parameter addr_width = 4;
5253
 
5254 12 unneback
input [31:0] wbs_dat_i;
5255
input [31:2] wbs_adr_i;
5256
input [3:0]  wbs_sel_i;
5257
input [1:0]  wbs_bte_i;
5258
input [2:0]  wbs_cti_i;
5259
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
5260
output [31:0] wbs_dat_o;
5261 14 unneback
output wbs_ack_o;
5262 12 unneback
input wbs_clk, wbs_rst;
5263
 
5264
output [31:0] wbm_dat_o;
5265
output reg [31:2] wbm_adr_o;
5266
output [3:0]  wbm_sel_o;
5267
output reg [1:0]  wbm_bte_o;
5268
output reg [2:0]  wbm_cti_o;
5269 14 unneback
output reg wbm_we_o;
5270
output wbm_cyc_o;
5271 12 unneback
output wbm_stb_o;
5272
input [31:0]  wbm_dat_i;
5273
input wbm_ack_i;
5274
input wbm_clk, wbm_rst;
5275
 
5276
// bte
5277
parameter linear       = 2'b00;
5278
parameter wrap4        = 2'b01;
5279
parameter wrap8        = 2'b10;
5280
parameter wrap16       = 2'b11;
5281
// cti
5282
parameter classic      = 3'b000;
5283
parameter incburst     = 3'b010;
5284
parameter endofburst   = 3'b111;
5285
 
5286 95 unneback
localparam wbs_adr  = 1'b0;
5287
localparam wbs_data = 1'b1;
5288 12 unneback
 
5289 95 unneback
localparam wbm_adr0      = 2'b00;
5290
localparam wbm_adr1      = 2'b01;
5291
localparam wbm_data      = 2'b10;
5292
localparam wbm_data_wait = 2'b11;
5293 12 unneback
 
5294
reg [1:0] wbs_bte_reg;
5295
reg wbs;
5296
wire wbs_eoc_alert, wbm_eoc_alert;
5297
reg wbs_eoc, wbm_eoc;
5298
reg [1:0] wbm;
5299
 
5300 14 unneback
wire [1:16] wbs_count, wbm_count;
5301 12 unneback
 
5302
wire [35:0] a_d, a_q, b_d, b_q;
5303
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
5304
reg a_rd_reg;
5305
wire b_rd_adr, b_rd_data;
5306 14 unneback
wire b_rd_data_reg;
5307
wire [35:0] temp;
5308 12 unneback
 
5309
`define WE 5
5310
`define BTE 4:3
5311
`define CTI 2:0
5312
 
5313
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
5314
always @ (posedge wbs_clk or posedge wbs_rst)
5315
if (wbs_rst)
5316
        wbs_eoc <= 1'b0;
5317
else
5318
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
5319 78 unneback
                wbs_eoc <= (wbs_bte_i==linear) | (wbs_cti_i==3'b111);
5320 12 unneback
        else if (wbs_eoc_alert & (a_rd | a_wr))
5321
                wbs_eoc <= 1'b1;
5322
 
5323 40 unneback
`define MODULE cnt_shreg_ce_clear
5324
`BASE`MODULE # ( .length(16))
5325
`undef MODULE
5326 12 unneback
    cnt0 (
5327
        .cke(wbs_ack_o),
5328
        .clear(wbs_eoc),
5329
        .q(wbs_count),
5330
        .rst(wbs_rst),
5331
        .clk(wbs_clk));
5332
 
5333
always @ (posedge wbs_clk or posedge wbs_rst)
5334
if (wbs_rst)
5335
        wbs <= wbs_adr;
5336
else
5337 75 unneback
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & a_fifo_empty)
5338 12 unneback
                wbs <= wbs_data;
5339
        else if (wbs_eoc & wbs_ack_o)
5340
                wbs <= wbs_adr;
5341
 
5342
// wbs FIFO
5343 75 unneback
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,((wbs_cti_i==3'b111) ? {2'b00,3'b000} : {wbs_bte_i,wbs_cti_i})} : {wbs_dat_i,wbs_sel_i};
5344
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & a_fifo_empty :
5345 12 unneback
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
5346
              1'b0;
5347
assign a_rd = !a_fifo_empty;
5348
always @ (posedge wbs_clk or posedge wbs_rst)
5349
if (wbs_rst)
5350
        a_rd_reg <= 1'b0;
5351
else
5352
        a_rd_reg <= a_rd;
5353
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
5354
 
5355
assign wbs_dat_o = a_q[35:4];
5356
 
5357
always @ (posedge wbs_clk or posedge wbs_rst)
5358
if (wbs_rst)
5359 13 unneback
        wbs_bte_reg <= 2'b00;
5360 12 unneback
else
5361 13 unneback
        wbs_bte_reg <= wbs_bte_i;
5362 12 unneback
 
5363
// wbm FIFO
5364
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
5365
always @ (posedge wbm_clk or posedge wbm_rst)
5366
if (wbm_rst)
5367
        wbm_eoc <= 1'b0;
5368
else
5369
        if (wbm==wbm_adr0 & !b_fifo_empty)
5370
                wbm_eoc <= b_q[`BTE] == linear;
5371
        else if (wbm_eoc_alert & wbm_ack_i)
5372
                wbm_eoc <= 1'b1;
5373
 
5374
always @ (posedge wbm_clk or posedge wbm_rst)
5375
if (wbm_rst)
5376
        wbm <= wbm_adr0;
5377
else
5378 33 unneback
/*
5379 12 unneback
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
5380
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
5381
        (wbm==wbm_adr1 & !wbm_we_o) |
5382
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
5383
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
5384 33 unneback
*/
5385
    case (wbm)
5386
    wbm_adr0:
5387
        if (!b_fifo_empty)
5388
            wbm <= wbm_adr1;
5389
    wbm_adr1:
5390
        if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
5391
            wbm <= wbm_data;
5392
    wbm_data:
5393
        if (wbm_ack_i & wbm_eoc)
5394
            wbm <= wbm_adr0;
5395
        else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
5396
            wbm <= wbm_data_wait;
5397
    wbm_data_wait:
5398
        if (!b_fifo_empty)
5399
            wbm <= wbm_data;
5400
    endcase
5401 12 unneback
 
5402
assign b_d = {wbm_dat_i,4'b1111};
5403
assign b_wr = !wbm_we_o & wbm_ack_i;
5404
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
5405
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
5406
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
5407 33 unneback
                   (wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
5408 12 unneback
                   1'b0;
5409
assign b_rd = b_rd_adr | b_rd_data;
5410
 
5411 40 unneback
`define MODULE dff
5412
`BASE`MODULE dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
5413
`undef MODULE
5414
`define MODULE dff_ce
5415
`BASE`MODULE # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
5416
`undef MODULE
5417 12 unneback
 
5418
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
5419
 
5420 40 unneback
`define MODULE cnt_shreg_ce_clear
5421 42 unneback
`BASE`MODULE # ( .length(16))
5422 40 unneback
`undef MODULE
5423 12 unneback
    cnt1 (
5424
        .cke(wbm_ack_i),
5425
        .clear(wbm_eoc),
5426
        .q(wbm_count),
5427
        .rst(wbm_rst),
5428
        .clk(wbm_clk));
5429
 
5430 33 unneback
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
5431
assign wbm_stb_o = (wbm==wbm_data);
5432 12 unneback
 
5433
always @ (posedge wbm_clk or posedge wbm_rst)
5434
if (wbm_rst)
5435
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
5436
else begin
5437
        if (wbm==wbm_adr0 & !b_fifo_empty)
5438
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
5439
        else if (wbm_eoc_alert & wbm_ack_i)
5440
                wbm_cti_o <= endofburst;
5441
end
5442
 
5443
//async_fifo_dw_simplex_top
5444 40 unneback
`define MODULE fifo_2r2w_async_simplex
5445
`BASE`MODULE
5446
`undef MODULE
5447 12 unneback
# ( .data_width(36), .addr_width(addr_width))
5448
fifo (
5449
    // a side
5450
    .a_d(a_d),
5451
    .a_wr(a_wr),
5452
    .a_fifo_full(a_fifo_full),
5453
    .a_q(a_q),
5454
    .a_rd(a_rd),
5455
    .a_fifo_empty(a_fifo_empty),
5456
    .a_clk(wbs_clk),
5457
    .a_rst(wbs_rst),
5458
    // b side
5459
    .b_d(b_d),
5460
    .b_wr(b_wr),
5461
    .b_fifo_full(b_fifo_full),
5462
    .b_q(b_q),
5463
    .b_rd(b_rd),
5464
    .b_fifo_empty(b_fifo_empty),
5465
    .b_clk(wbm_clk),
5466
    .b_rst(wbm_rst)
5467
    );
5468
 
5469
endmodule
5470 40 unneback
`undef WE
5471
`undef BTE
5472
`undef CTI
5473
`endif
5474 17 unneback
 
5475 75 unneback
`ifdef WB3AVALON_BRIDGE
5476
`define MODULE wb3avalon_bridge
5477
module `BASE`MODULE (
5478
`undef MODULE
5479
        // wishbone slave side
5480
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
5481 77 unneback
        // avalon master side
5482 75 unneback
        readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst);
5483
 
5484 85 unneback
parameter linewrapburst = 1'b0;
5485
 
5486 75 unneback
input [31:0] wbs_dat_i;
5487
input [31:2] wbs_adr_i;
5488
input [3:0]  wbs_sel_i;
5489
input [1:0]  wbs_bte_i;
5490
input [2:0]  wbs_cti_i;
5491 83 unneback
input wbs_we_i;
5492
input wbs_cyc_i;
5493
input wbs_stb_i;
5494 75 unneback
output [31:0] wbs_dat_o;
5495
output wbs_ack_o;
5496
input wbs_clk, wbs_rst;
5497
 
5498
input [31:0] readdata;
5499
output [31:0] writedata;
5500
output [31:2] address;
5501
output [3:0]  be;
5502
output write;
5503 81 unneback
output read;
5504 75 unneback
output beginbursttransfer;
5505
output [3:0] burstcount;
5506
input readdatavalid;
5507
input waitrequest;
5508
input clk;
5509
input rst;
5510
 
5511
wire [1:0] wbm_bte_o;
5512
wire [2:0] wbm_cti_o;
5513
wire wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_ack_i;
5514
reg last_cyc;
5515 79 unneback
reg [3:0] counter;
5516 82 unneback
reg read_busy;
5517 75 unneback
 
5518
always @ (posedge clk or posedge rst)
5519
if (rst)
5520
    last_cyc <= 1'b0;
5521
else
5522
    last_cyc <= wbm_cyc_o;
5523
 
5524 79 unneback
always @ (posedge clk or posedge rst)
5525
if (rst)
5526 82 unneback
    read_busy <= 1'b0;
5527 79 unneback
else
5528 82 unneback
    if (read & !waitrequest)
5529
        read_busy <= 1'b1;
5530
    else if (wbm_ack_i & wbm_cti_o!=3'b010)
5531
        read_busy <= 1'b0;
5532
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o & !read_busy;
5533 81 unneback
 
5534 75 unneback
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010;
5535
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 :
5536
                    (wbm_bte_o==2'b10) ? 4'd8 :
5537 78 unneback
                    (wbm_bte_o==2'b11) ? 4'd16:
5538
                    4'd1;
5539 82 unneback
assign wbm_ack_i = (readdatavalid) | (write & !waitrequest);
5540 75 unneback
 
5541 79 unneback
always @ (posedge clk or posedge rst)
5542
if (rst) begin
5543
    counter <= 4'd0;
5544
end else
5545 80 unneback
    if (wbm_we_o) begin
5546
        if (!waitrequest & !last_cyc & wbm_cyc_o) begin
5547 85 unneback
            counter <= burstcount -4'd1;
5548 80 unneback
        end else if (waitrequest & !last_cyc & wbm_cyc_o) begin
5549
            counter <= burstcount;
5550
        end else if (!waitrequest & wbm_stb_o) begin
5551
            counter <= counter - 4'd1;
5552
        end
5553 82 unneback
    end
5554 81 unneback
assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o & counter!=4'd0;
5555 79 unneback
 
5556 75 unneback
`define MODULE wb3wb3_bridge
5557 77 unneback
`BASE`MODULE wbwb3inst (
5558 75 unneback
`undef MODULE
5559
    // wishbone slave side
5560
    .wbs_dat_i(wbs_dat_i),
5561
    .wbs_adr_i(wbs_adr_i),
5562
    .wbs_sel_i(wbs_sel_i),
5563
    .wbs_bte_i(wbs_bte_i),
5564
    .wbs_cti_i(wbs_cti_i),
5565
    .wbs_we_i(wbs_we_i),
5566
    .wbs_cyc_i(wbs_cyc_i),
5567
    .wbs_stb_i(wbs_stb_i),
5568
    .wbs_dat_o(wbs_dat_o),
5569
    .wbs_ack_o(wbs_ack_o),
5570
    .wbs_clk(wbs_clk),
5571
    .wbs_rst(wbs_rst),
5572
    // wishbone master side
5573
    .wbm_dat_o(writedata),
5574 78 unneback
    .wbm_adr_o(address),
5575 75 unneback
    .wbm_sel_o(be),
5576
    .wbm_bte_o(wbm_bte_o),
5577
    .wbm_cti_o(wbm_cti_o),
5578
    .wbm_we_o(wbm_we_o),
5579
    .wbm_cyc_o(wbm_cyc_o),
5580
    .wbm_stb_o(wbm_stb_o),
5581
    .wbm_dat_i(readdata),
5582
    .wbm_ack_i(wbm_ack_i),
5583
    .wbm_clk(clk),
5584
    .wbm_rst(rst));
5585
 
5586
 
5587
endmodule
5588
`endif
5589
 
5590 105 unneback
`ifdef WB_ARBITER
5591
`define MODULE wb_arbiter
5592 42 unneback
module `BASE`MODULE (
5593 40 unneback
`undef MODULE
5594 39 unneback
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
5595 105 unneback
    wbm_dat_i, wbm_stall_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
5596 39 unneback
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
5597 105 unneback
    wbs_dat_o, wbs_stall_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
5598 39 unneback
    wb_clk, wb_rst
5599
);
5600
 
5601
parameter nr_of_ports = 3;
5602
parameter adr_size = 26;
5603
parameter adr_lo   = 2;
5604
parameter dat_size = 32;
5605
parameter sel_size = dat_size/8;
5606
 
5607
localparam aw = (adr_size - adr_lo) * nr_of_ports;
5608
localparam dw = dat_size * nr_of_ports;
5609
localparam sw = sel_size * nr_of_ports;
5610
localparam cw = 3 * nr_of_ports;
5611
localparam bw = 2 * nr_of_ports;
5612
 
5613
input  [dw-1:0] wbm_dat_o;
5614
input  [aw-1:0] wbm_adr_o;
5615
input  [sw-1:0] wbm_sel_o;
5616
input  [cw-1:0] wbm_cti_o;
5617
input  [bw-1:0] wbm_bte_o;
5618
input  [nr_of_ports-1:0] wbm_we_o, wbm_stb_o, wbm_cyc_o;
5619
output [dw-1:0] wbm_dat_i;
5620 105 unneback
output [nr_of_ports-1:0] wbm_stall_o, wbm_ack_i, wbm_err_i, wbm_rty_i;
5621 39 unneback
 
5622
output [dat_size-1:0] wbs_dat_i;
5623
output [adr_size-1:adr_lo] wbs_adr_i;
5624
output [sel_size-1:0] wbs_sel_i;
5625
output [2:0] wbs_cti_i;
5626
output [1:0] wbs_bte_i;
5627
output wbs_we_i, wbs_stb_i, wbs_cyc_i;
5628
input  [dat_size-1:0] wbs_dat_o;
5629 105 unneback
input  wbs_stall_o, wbs_ack_o, wbs_err_o, wbs_rty_o;
5630 39 unneback
 
5631
input wb_clk, wb_rst;
5632
 
5633 44 unneback
reg  [nr_of_ports-1:0] select;
5634 39 unneback
wire [nr_of_ports-1:0] state;
5635
wire [nr_of_ports-1:0] eoc; // end-of-cycle
5636
wire [nr_of_ports-1:0] sel;
5637
wire idle;
5638
 
5639
genvar i;
5640
 
5641
assign idle = !(|state);
5642
 
5643
generate
5644
if (nr_of_ports == 2) begin
5645
 
5646
    wire [2:0] wbm1_cti_o, wbm0_cti_o;
5647
 
5648
    assign {wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5649
 
5650 44 unneback
    //assign select = (idle) ? {wbm_cyc_o[1],!wbm_cyc_o[1] & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5651
 
5652
    always @ (idle or wbm_cyc_o)
5653
    if (idle)
5654
        casex (wbm_cyc_o)
5655
        2'b1x : select = 2'b10;
5656
        2'b01 : select = 2'b01;
5657
        default : select = {nr_of_ports{1'b0}};
5658
        endcase
5659
    else
5660
        select = {nr_of_ports{1'b0}};
5661
 
5662 39 unneback
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5663
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5664
 
5665
end
5666
endgenerate
5667
 
5668
generate
5669
if (nr_of_ports == 3) begin
5670
 
5671
    wire [2:0] wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5672
 
5673
    assign {wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5674
 
5675 44 unneback
    always @ (idle or wbm_cyc_o)
5676
    if (idle)
5677
        casex (wbm_cyc_o)
5678
        3'b1xx : select = 3'b100;
5679
        3'b01x : select = 3'b010;
5680
        3'b001 : select = 3'b001;
5681
        default : select = {nr_of_ports{1'b0}};
5682
        endcase
5683
    else
5684
        select = {nr_of_ports{1'b0}};
5685
 
5686
//    assign select = (idle) ? {wbm_cyc_o[2],!wbm_cyc_o[2] & wbm_cyc_o[1],wbm_cyc_o[2:1]==2'b00 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5687 39 unneback
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5688
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5689
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5690
 
5691
end
5692
endgenerate
5693
 
5694
generate
5695 44 unneback
if (nr_of_ports == 4) begin
5696
 
5697
    wire [2:0] wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5698
 
5699
    assign {wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5700
 
5701
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5702
 
5703
    always @ (idle or wbm_cyc_o)
5704
    if (idle)
5705
        casex (wbm_cyc_o)
5706
        4'b1xxx : select = 4'b1000;
5707
        4'b01xx : select = 4'b0100;
5708
        4'b001x : select = 4'b0010;
5709
        4'b0001 : select = 4'b0001;
5710
        default : select = {nr_of_ports{1'b0}};
5711
        endcase
5712
    else
5713
        select = {nr_of_ports{1'b0}};
5714
 
5715
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5716
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5717
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5718
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5719
 
5720
end
5721
endgenerate
5722
 
5723
generate
5724
if (nr_of_ports == 5) begin
5725
 
5726
    wire [2:0] wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5727
 
5728
    assign {wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5729
 
5730
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5731
 
5732
    always @ (idle or wbm_cyc_o)
5733
    if (idle)
5734
        casex (wbm_cyc_o)
5735
        5'b1xxxx : select = 5'b10000;
5736
        5'b01xxx : select = 5'b01000;
5737
        5'b001xx : select = 5'b00100;
5738
        5'b0001x : select = 5'b00010;
5739
        5'b00001 : select = 5'b00001;
5740
        default : select = {nr_of_ports{1'b0}};
5741
        endcase
5742
    else
5743
        select = {nr_of_ports{1'b0}};
5744
 
5745
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
5746
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5747
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5748
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5749
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5750
 
5751
end
5752
endgenerate
5753
 
5754
generate
5755 67 unneback
if (nr_of_ports == 6) begin
5756
 
5757
    wire [2:0] wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5758
 
5759
    assign {wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5760
 
5761
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5762
 
5763
    always @ (idle or wbm_cyc_o)
5764
    if (idle)
5765
        casex (wbm_cyc_o)
5766
        6'b1xxxxx : select = 6'b100000;
5767
        6'b01xxxx : select = 6'b010000;
5768
        6'b001xxx : select = 6'b001000;
5769
        6'b0001xx : select = 6'b000100;
5770
        6'b00001x : select = 6'b000010;
5771
        6'b000001 : select = 6'b000001;
5772
        default : select = {nr_of_ports{1'b0}};
5773
        endcase
5774
    else
5775
        select = {nr_of_ports{1'b0}};
5776
 
5777
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
5778
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
5779
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5780
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5781
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5782
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5783
 
5784
end
5785
endgenerate
5786
 
5787
generate
5788
if (nr_of_ports == 7) begin
5789
 
5790
    wire [2:0] wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5791
 
5792
    assign {wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5793
 
5794
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5795
 
5796
    always @ (idle or wbm_cyc_o)
5797
    if (idle)
5798
        casex (wbm_cyc_o)
5799
        7'b1xxxxxx : select = 7'b1000000;
5800
        7'b01xxxxx : select = 7'b0100000;
5801
        7'b001xxxx : select = 7'b0010000;
5802
        7'b0001xxx : select = 7'b0001000;
5803
        7'b00001xx : select = 7'b0000100;
5804
        7'b000001x : select = 7'b0000010;
5805
        7'b0000001 : select = 7'b0000001;
5806
        default : select = {nr_of_ports{1'b0}};
5807
        endcase
5808
    else
5809
        select = {nr_of_ports{1'b0}};
5810
 
5811
    assign eoc[6] = (wbm_ack_i[6] & (wbm6_cti_o == 3'b000 | wbm6_cti_o == 3'b111)) | !wbm_cyc_o[6];
5812
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
5813
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
5814
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5815
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5816
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5817
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5818
 
5819
end
5820
endgenerate
5821
 
5822
generate
5823
if (nr_of_ports == 8) begin
5824
 
5825
    wire [2:0] wbm7_cti_o, wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5826
 
5827
    assign {wbm7_cti_o, wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5828
 
5829
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5830
 
5831
    always @ (idle or wbm_cyc_o)
5832
    if (idle)
5833
        casex (wbm_cyc_o)
5834
        8'b1xxxxxxx : select = 8'b10000000;
5835
        8'b01xxxxxx : select = 8'b01000000;
5836
        8'b001xxxxx : select = 8'b00100000;
5837
        8'b0001xxxx : select = 8'b00010000;
5838
        8'b00001xxx : select = 8'b00001000;
5839
        8'b000001xx : select = 8'b00000100;
5840
        8'b0000001x : select = 8'b00000010;
5841
        8'b00000001 : select = 8'b00000001;
5842
        default : select = {nr_of_ports{1'b0}};
5843
        endcase
5844
    else
5845
        select = {nr_of_ports{1'b0}};
5846
 
5847
    assign eoc[7] = (wbm_ack_i[7] & (wbm7_cti_o == 3'b000 | wbm7_cti_o == 3'b111)) | !wbm_cyc_o[7];
5848
    assign eoc[6] = (wbm_ack_i[6] & (wbm6_cti_o == 3'b000 | wbm6_cti_o == 3'b111)) | !wbm_cyc_o[6];
5849
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
5850
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
5851
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5852
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5853
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5854
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5855
 
5856
end
5857
endgenerate
5858
 
5859
generate
5860 63 unneback
for (i=0;i<nr_of_ports;i=i+1) begin : spr0
5861 42 unneback
`define MODULE spr
5862
    `BASE`MODULE sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));
5863
`undef MODULE
5864 39 unneback
end
5865
endgenerate
5866
 
5867
    assign sel = select | state;
5868
 
5869 40 unneback
`define MODULE mux_andor
5870
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i));
5871
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(adr_size-adr_lo)) mux1 ( .a(wbm_adr_o), .sel(sel), .dout(wbs_adr_i));
5872
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(sel_size)) mux2 ( .a(wbm_sel_o), .sel(sel), .dout(wbs_sel_i));
5873
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(3)) mux3 ( .a(wbm_cti_o), .sel(sel), .dout(wbs_cti_i));
5874
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(2)) mux4 ( .a(wbm_bte_o), .sel(sel), .dout(wbs_bte_i));
5875
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux5 ( .a(wbm_we_o), .sel(sel), .dout(wbs_we_i));
5876
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux6 ( .a(wbm_stb_o), .sel(sel), .dout(wbs_stb_i));
5877
`undef MODULE
5878 39 unneback
    assign wbs_cyc_i = |sel;
5879
 
5880
    assign wbm_dat_i = {nr_of_ports{wbs_dat_o}};
5881
    assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
5882
    assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
5883
    assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
5884
 
5885
endmodule
5886 40 unneback
`endif
5887 39 unneback
 
5888 101 unneback
`ifdef WB_RAM
5889 49 unneback
// WB RAM with byte enable
5890 101 unneback
`define MODULE wb_ram
5891 59 unneback
module `BASE`MODULE (
5892
`undef MODULE
5893 69 unneback
    wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
5894 101 unneback
    wbs_dat_o, wbs_ack_o, wbs_stall_o, wb_clk, wb_rst);
5895 59 unneback
 
5896 101 unneback
parameter adr_width = 16;
5897
parameter mem_size = 1<<adr_width;
5898
parameter dat_width = 32;
5899
parameter max_burst_width = 4; // only used for B3
5900
parameter mode = "B3"; // valid options: B3, B4
5901 60 unneback
parameter memory_init = 1;
5902
parameter memory_file = "vl_ram.vmem";
5903 59 unneback
 
5904 101 unneback
input [dat_width-1:0] wbs_dat_i;
5905
input [adr_width-1:0] wbs_adr_i;
5906
input [2:0] wbs_cti_i;
5907
input [1:0] wbs_bte_i;
5908
input [dat_width/8-1:0] wbs_sel_i;
5909 70 unneback
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
5910 101 unneback
output [dat_width-1:0] wbs_dat_o;
5911 70 unneback
output wbs_ack_o;
5912 101 unneback
output wbs_stall_o;
5913 71 unneback
input wb_clk, wb_rst;
5914 59 unneback
 
5915 101 unneback
wire [adr_width-1:0] adr;
5916
wire we;
5917 59 unneback
 
5918 101 unneback
generate
5919
if (mode=="B3") begin : B3_inst
5920 83 unneback
`define MODULE wb_adr_inc
5921 101 unneback
`BASE`MODULE # ( .adr_width(adr_width), .max_burst_width(max_burst_width)) adr_inc0 (
5922 83 unneback
    .cyc_i(wbs_cyc_i),
5923
    .stb_i(wbs_stb_i),
5924
    .cti_i(wbs_cti_i),
5925
    .bte_i(wbs_bte_i),
5926
    .adr_i(wbs_adr_i),
5927 85 unneback
    .we_i(wbs_we_i),
5928 83 unneback
    .ack_o(wbs_ack_o),
5929
    .adr_o(adr),
5930
    .clk(wb_clk),
5931
    .rst(wb_rst));
5932
`undef MODULE
5933 101 unneback
assign we = wbs_we_i & wbs_ack_o;
5934
end else if (mode=="B4") begin : B4_inst
5935
reg wbs_ack_o_reg;
5936
always @ (posedge wb_clk or posedge wb_rst)
5937
    if (wb_rst)
5938
        wbs_ack_o_reg <= 1'b0;
5939
    else
5940
        wbs_ack_o_reg <= wbs_stb_i & wbs_cyc_i;
5941
assign wbs_ack_o = wbs_ack_o_reg;
5942
assign wbs_stall_o = 1'b0;
5943
assign adr = wbs_adr_i;
5944
assign we = wbs_we_i & wbs_cyc_i & wbs_stb_i;
5945
end
5946
endgenerate
5947 60 unneback
 
5948 100 unneback
`define MODULE ram_be
5949
`BASE`MODULE # (
5950
    .data_width(dat_width),
5951
    .addr_width(adr_width),
5952
    .mem_size(mem_size),
5953
    .memory_init(memory_init),
5954
    .memory_file(memory_file))
5955
ram0(
5956
`undef MODULE
5957 101 unneback
    .d(wbs_dat_i),
5958
    .adr(adr),
5959
    .be(wbs_sel_i),
5960
    .we(we),
5961
    .q(wbs_dat_o),
5962 100 unneback
    .clk(wb_clk)
5963
);
5964 49 unneback
 
5965
endmodule
5966
`endif
5967
 
5968 103 unneback
`ifdef WB_SHADOW_RAM
5969
// A wishbone compliant RAM module that can be placed in front of other memory controllers
5970
`define MODULE wb_shadow_ram
5971
module `BASE`MODULE (
5972
`undef MODULE
5973
    wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
5974
    wbs_dat_o, wbs_ack_o, wbs_stall_o,
5975
    wbm_dat_o, wbm_adr_o, wbm_cti_o, wbm_bte_o, wbm_sel_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
5976
    wbm_dat_i, wbm_ack_i, wbm_stall_i,
5977
    wb_clk, wb_rst);
5978
 
5979
parameter dat_width = 32;
5980
parameter mode = "B4";
5981
parameter max_burst_width = 4; // only used for B3
5982
 
5983
parameter shadow_mem_adr_width = 10;
5984
parameter shadow_mem_size = 1024;
5985
parameter shadow_mem_init = 2;
5986
parameter shadow_mem_file = "vl_ram.v";
5987
 
5988
parameter main_mem_adr_width = 24;
5989
 
5990
input [dat_width-1:0] wbs_dat_i;
5991
input [main_mem_adr_width-1:0] wbs_adr_i;
5992
input [2:0] wbs_cti_i;
5993
input [1:0] wbs_bte_i;
5994
input [dat_width/8-1:0] wbs_sel_i;
5995
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
5996
output [dat_width-1:0] wbs_dat_o;
5997
output wbs_ack_o;
5998
output wbs_stall_o;
5999
 
6000
output [dat_width-1:0] wbm_dat_o;
6001
output [main_mem_adr_width-1:0] wbm_adr_o;
6002
output [2:0] wbm_cti_o;
6003
output [1:0] wbm_bte_o;
6004
output [dat_width/8-1:0] wbm_sel_o;
6005
output wbm_we_o, wbm_stb_o, wbm_cyc_o;
6006
input [dat_width-1:0] wbm_dat_i;
6007
input wbm_ack_i, wbm_stall_i;
6008
 
6009
input wb_clk, wb_rst;
6010
 
6011
generate
6012
if (shadow_mem_size>0) begin : shadow_ram_inst
6013
 
6014
wire cyc;
6015
wire [dat_width-1:0] dat;
6016
wire stall, ack;
6017
 
6018
assign cyc = wbs_cyc_i & (wbs_adr_i<=shadow_mem_size);
6019
`define MODULE wb_ram
6020
`BASE`MODULE # (
6021
    .dat_width(dat_width),
6022
    .adr_width(shadow_mem_adr_width),
6023
    .mem_size(shadow_mem_size),
6024
    .memory_init(shadow_mem_init),
6025 117 unneback
    .memory_file(shadow_mem_file),
6026 103 unneback
    .mode(mode))
6027
shadow_mem0 (
6028
    .wbs_dat_i(wbs_dat_i),
6029
    .wbs_adr_i(wbs_adr_i[shadow_mem_adr_width-1:0]),
6030
    .wbs_sel_i(wbs_sel_i),
6031
    .wbs_we_i (wbs_we_i),
6032
    .wbs_bte_i(wbs_bte_i),
6033
    .wbs_cti_i(wbs_cti_i),
6034
    .wbs_stb_i(wbs_stb_i),
6035
    .wbs_cyc_i(cyc),
6036
    .wbs_dat_o(dat),
6037
    .wbs_stall_o(stall),
6038
    .wbs_ack_o(ack),
6039
    .wb_clk(wb_clk),
6040
    .wb_rst(wb_rst));
6041
`undef MODULE
6042
 
6043
assign {wbm_dat_o, wbm_adr_o, wbm_cti_o, wbm_bte_o, wbm_sel_o, wbm_we_o, wbm_stb_o} =
6044
       {wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i};
6045
assign wbm_cyc_o = wbs_cyc_i & (wbs_adr_i>shadow_mem_size);
6046
 
6047
assign wbs_dat_o = (dat & {dat_width{cyc}}) | (wbm_dat_i & {dat_width{wbm_cyc_o}});
6048
assign wbs_ack_o = (ack & cyc) | (wbm_ack_i & wbm_cyc_o);
6049
assign wbs_stall_o = (stall & cyc) | (wbm_stall_i & wbm_cyc_o);
6050
 
6051
end else begin : no_shadow_ram_inst
6052
 
6053
assign {wbm_dat_o, wbm_adr_o, wbm_cti_o, wbm_bte_o, wbm_sel_o, wbm_we_o, wbm_stb_o, wbm_cyc_o} =
6054
       {wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i};
6055
assign {wbs_dat_o, wbs_ack_o, wbs_stall_o} = {wbm_dat_i, wbm_ack_i, wbm_stall_i};
6056
 
6057
end
6058
endgenerate
6059
 
6060
endmodule
6061
`endif
6062
 
6063 48 unneback
`ifdef WB_B4_ROM
6064
// WB ROM
6065
`define MODULE wb_b4_rom
6066
module `BASE`MODULE (
6067
`undef MODULE
6068
    wb_adr_i, wb_stb_i, wb_cyc_i,
6069
    wb_dat_o, stall_o, wb_ack_o, wb_clk, wb_rst);
6070
 
6071
    parameter dat_width = 32;
6072
    parameter dat_default = 32'h15000000;
6073
    parameter adr_width = 32;
6074
 
6075
/*
6076
`ifndef ROM
6077
`define ROM "rom.v"
6078
`endif
6079
*/
6080
    input [adr_width-1:2]   wb_adr_i;
6081
    input                   wb_stb_i;
6082
    input                   wb_cyc_i;
6083
    output [dat_width-1:0]  wb_dat_o;
6084
    reg [dat_width-1:0]     wb_dat_o;
6085
    output                  wb_ack_o;
6086
    reg                     wb_ack_o;
6087
    output                  stall_o;
6088
    input                   wb_clk;
6089
    input                   wb_rst;
6090
 
6091
always @ (posedge wb_clk or posedge wb_rst)
6092
    if (wb_rst)
6093
        wb_dat_o <= {dat_width{1'b0}};
6094
    else
6095
         case (wb_adr_i[adr_width-1:2])
6096
`ifdef ROM
6097
`include `ROM
6098
`endif
6099
           default:
6100
             wb_dat_o <= dat_default;
6101
 
6102
         endcase // case (wb_adr_i)
6103
 
6104
 
6105
always @ (posedge wb_clk or posedge wb_rst)
6106
    if (wb_rst)
6107
        wb_ack_o <= 1'b0;
6108
    else
6109
        wb_ack_o <= wb_stb_i & wb_cyc_i;
6110
 
6111
assign stall_o = 1'b0;
6112
 
6113
endmodule
6114
`endif
6115
 
6116
 
6117 40 unneback
`ifdef WB_BOOT_ROM
6118 17 unneback
// WB ROM
6119 40 unneback
`define MODULE wb_boot_rom
6120
module `BASE`MODULE (
6121
`undef MODULE
6122 17 unneback
    wb_adr_i, wb_stb_i, wb_cyc_i,
6123 18 unneback
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
6124 17 unneback
 
6125 18 unneback
    parameter adr_hi = 31;
6126
    parameter adr_lo = 28;
6127
    parameter adr_sel = 4'hf;
6128
    parameter addr_width = 5;
6129 33 unneback
/*
6130 17 unneback
`ifndef BOOT_ROM
6131
`define BOOT_ROM "boot_rom.v"
6132
`endif
6133 33 unneback
*/
6134 18 unneback
    input [adr_hi:2]    wb_adr_i;
6135
    input               wb_stb_i;
6136
    input               wb_cyc_i;
6137
    output [31:0]        wb_dat_o;
6138
    output              wb_ack_o;
6139
    output              hit_o;
6140
    input               wb_clk;
6141
    input               wb_rst;
6142
 
6143
    wire hit;
6144
    reg [31:0] wb_dat;
6145
    reg wb_ack;
6146
 
6147
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
6148 17 unneback
 
6149
always @ (posedge wb_clk or posedge wb_rst)
6150
    if (wb_rst)
6151 18 unneback
        wb_dat <= 32'h15000000;
6152 17 unneback
    else
6153 18 unneback
         case (wb_adr_i[addr_width-1:2])
6154 33 unneback
`ifdef BOOT_ROM
6155 17 unneback
`include `BOOT_ROM
6156 33 unneback
`endif
6157 17 unneback
           /*
6158
            // Zero r0 and jump to 0x00000100
6159 18 unneback
 
6160
            1 : wb_dat <= 32'hA8200000;
6161
            2 : wb_dat <= 32'hA8C00100;
6162
            3 : wb_dat <= 32'h44003000;
6163
            4 : wb_dat <= 32'h15000000;
6164 17 unneback
            */
6165
           default:
6166 18 unneback
             wb_dat <= 32'h00000000;
6167 17 unneback
 
6168
         endcase // case (wb_adr_i)
6169
 
6170
 
6171
always @ (posedge wb_clk or posedge wb_rst)
6172
    if (wb_rst)
6173 18 unneback
        wb_ack <= 1'b0;
6174 17 unneback
    else
6175 18 unneback
        wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
6176 17 unneback
 
6177 18 unneback
assign hit_o = hit;
6178
assign wb_dat_o = wb_dat & {32{wb_ack}};
6179
assign wb_ack_o = wb_ack;
6180
 
6181 17 unneback
endmodule
6182 40 unneback
`endif
6183 32 unneback
 
6184 106 unneback
`ifdef WB_DPRAM
6185
`define MODULE wb_dpram
6186 40 unneback
module `BASE`MODULE (
6187
`undef MODULE
6188 32 unneback
        // wishbone slave side a
6189 106 unneback
        wbsa_dat_i, wbsa_adr_i, wbsa_sel_i, wbsa_cti_i, wbsa_bte_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o, wbsa_stall_o,
6190 32 unneback
        wbsa_clk, wbsa_rst,
6191 92 unneback
        // wishbone slave side b
6192 106 unneback
        wbsb_dat_i, wbsb_adr_i, wbsb_sel_i, wbsb_cti_i, wbsb_bte_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o, wbsb_stall_o,
6193 32 unneback
        wbsb_clk, wbsb_rst);
6194
 
6195 92 unneback
parameter data_width_a = 32;
6196
parameter data_width_b = data_width_a;
6197
parameter addr_width_a = 8;
6198
localparam addr_width_b = data_width_a * addr_width_a / data_width_b;
6199 101 unneback
parameter mem_size = (addr_width_a>addr_width_b) ? (1<<addr_width_a) : (1<<addr_width_b);
6200 92 unneback
parameter max_burst_width_a = 4;
6201
parameter max_burst_width_b = max_burst_width_a;
6202 101 unneback
parameter mode = "B3";
6203 109 unneback
parameter memory_init = 0;
6204
parameter memory_file = "vl_ram.v";
6205 92 unneback
input [data_width_a-1:0] wbsa_dat_i;
6206
input [addr_width_a-1:0] wbsa_adr_i;
6207
input [data_width_a/8-1:0] wbsa_sel_i;
6208
input [2:0] wbsa_cti_i;
6209
input [1:0] wbsa_bte_i;
6210 32 unneback
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
6211 92 unneback
output [data_width_a-1:0] wbsa_dat_o;
6212 109 unneback
output wbsa_ack_o;
6213 106 unneback
output wbsa_stall_o;
6214 32 unneback
input wbsa_clk, wbsa_rst;
6215
 
6216 92 unneback
input [data_width_b-1:0] wbsb_dat_i;
6217
input [addr_width_b-1:0] wbsb_adr_i;
6218
input [data_width_b/8-1:0] wbsb_sel_i;
6219
input [2:0] wbsb_cti_i;
6220
input [1:0] wbsb_bte_i;
6221 32 unneback
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
6222 92 unneback
output [data_width_b-1:0] wbsb_dat_o;
6223 109 unneback
output wbsb_ack_o;
6224 106 unneback
output wbsb_stall_o;
6225 32 unneback
input wbsb_clk, wbsb_rst;
6226
 
6227 92 unneback
wire [addr_width_a-1:0] adr_a;
6228
wire [addr_width_b-1:0] adr_b;
6229 101 unneback
wire we_a, we_b;
6230
generate
6231
if (mode=="B3") begin : b3_inst
6232 92 unneback
`define MODULE wb_adr_inc
6233
`BASE`MODULE # ( .adr_width(addr_width_a), .max_burst_width(max_burst_width_a)) adr_inc0 (
6234
    .cyc_i(wbsa_cyc_i),
6235
    .stb_i(wbsa_stb_i),
6236
    .cti_i(wbsa_cti_i),
6237
    .bte_i(wbsa_bte_i),
6238
    .adr_i(wbsa_adr_i),
6239
    .we_i(wbsa_we_i),
6240
    .ack_o(wbsa_ack_o),
6241
    .adr_o(adr_a),
6242
    .clk(wbsa_clk),
6243
    .rst(wbsa_rst));
6244 101 unneback
assign we_a = wbsa_we_i & wbsa_ack_o;
6245 92 unneback
`BASE`MODULE # ( .adr_width(addr_width_b), .max_burst_width(max_burst_width_b)) adr_inc1 (
6246
    .cyc_i(wbsb_cyc_i),
6247
    .stb_i(wbsb_stb_i),
6248
    .cti_i(wbsb_cti_i),
6249
    .bte_i(wbsb_bte_i),
6250
    .adr_i(wbsb_adr_i),
6251
    .we_i(wbsb_we_i),
6252
    .ack_o(wbsb_ack_o),
6253
    .adr_o(adr_b),
6254
    .clk(wbsb_clk),
6255
    .rst(wbsb_rst));
6256 40 unneback
`undef MODULE
6257 101 unneback
assign we_b = wbsb_we_i & wbsb_ack_o;
6258
end else if (mode=="B4") begin : b4_inst
6259 109 unneback
`define MODULE dff
6260
`BASE`MODULE dffacka ( .d(wbsa_stb_i & wbsa_cyc_i), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
6261 101 unneback
assign wbsa_stall_o = 1'b0;
6262
assign we_a = wbsa_we_i & wbsa_cyc_i & wbsa_stb_i;
6263 109 unneback
`BASE`MODULE dffackb ( .d(wbsb_stb_i & wbsb_cyc_i), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
6264
`undef MODULE
6265 101 unneback
assign wbsb_stall_o = 1'b0;
6266
assign we_b = wbsb_we_i & wbsb_cyc_i & wbsb_stb_i;
6267
end
6268
endgenerate
6269 92 unneback
 
6270
`define MODULE dpram_be_2r2w
6271 109 unneback
`BASE`MODULE # ( .a_data_width(data_width_a), .a_addr_width(addr_width_a), .mem_size(mem_size),
6272 110 unneback
                 .b_data_width(data_width_b),
6273 109 unneback
                 .memory_init(memory_init), .memory_file(memory_file))
6274 92 unneback
`undef MODULE
6275
ram_i (
6276 32 unneback
    .d_a(wbsa_dat_i),
6277 92 unneback
    .q_a(wbsa_dat_o),
6278
    .adr_a(adr_a),
6279
    .be_a(wbsa_sel_i),
6280 101 unneback
    .we_a(we_a),
6281 32 unneback
    .clk_a(wbsa_clk),
6282
    .d_b(wbsb_dat_i),
6283 92 unneback
    .q_b(wbsb_dat_o),
6284
    .adr_b(adr_b),
6285
    .be_b(wbsb_sel_i),
6286 101 unneback
    .we_b(we_b),
6287 32 unneback
    .clk_b(wbsb_clk) );
6288
 
6289
endmodule
6290 40 unneback
`endif
6291 94 unneback
 
6292 101 unneback
`ifdef WB_CACHE
6293
`define MODULE wb_cache
6294 97 unneback
module `BASE`MODULE (
6295 103 unneback
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i, wbs_dat_o, wbs_ack_o, wbs_stall_o, wbs_clk, wbs_rst,
6296 98 unneback
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o, wbm_dat_i, wbm_ack_i, wbm_stall_i, wbm_clk, wbm_rst
6297 97 unneback
);
6298
`undef MODULE
6299
 
6300
parameter dw_s = 32;
6301
parameter aw_s = 24;
6302
parameter dw_m = dw_s;
6303 124 unneback
//localparam aw_m = dw_s * aw_s / dw_m;
6304
localparam aw_m =
6305 126 unneback
        (dw_s==dw_m) ? aw_s :
6306
        (dw_s==dw_m*2) ? aw_s+1 :
6307
        (dw_s==dw_m*4) ? aw_s+2 :
6308
        (dw_s==dw_m*8) ? aw_s+3 :
6309
        (dw_s==dw_m*16) ? aw_s+4 :
6310
        (dw_s==dw_m*32) ? aw_s+5 :
6311
        (dw_s==dw_m/2) ? aw_s-1 :
6312 127 unneback
        (dw_s==dw_m/4) ? aw_s-2 :
6313 126 unneback
        (dw_s==dw_m/8) ? aw_s-3 :
6314
        (dw_s==dw_m/16) ? aw_s-4 :
6315
        (dw_s==dw_m/32) ? aw_s-5 : 0;
6316 124 unneback
 
6317 100 unneback
parameter wbs_max_burst_width = 4;
6318 103 unneback
parameter wbs_mode = "B3";
6319 97 unneback
 
6320
parameter async = 1; // wbs_clk != wbm_clk
6321
 
6322
parameter nr_of_ways = 1;
6323
parameter aw_offset = 4; // 4 => 16 words per cache line
6324
parameter aw_slot = 10;
6325 100 unneback
 
6326
parameter valid_mem = 0;
6327
parameter debug = 0;
6328
 
6329
localparam aw_b_offset = aw_offset * dw_s / dw_m;
6330 98 unneback
localparam aw_tag = aw_s - aw_slot - aw_offset;
6331 97 unneback
parameter wbm_burst_size = 4; // valid options 4,8,16
6332 98 unneback
localparam bte = (wbm_burst_size==4) ? 2'b01 : (wbm_burst_size==8) ? 2'b10 : 2'b11;
6333 97 unneback
`define SIZE2WIDTH wbm_burst_size
6334
localparam wbm_burst_width `SIZE2WIDTH_EXPR
6335
`undef SIZE2WIDTH
6336
localparam nr_of_wbm_burst = ((1<<aw_offset)/wbm_burst_size) * dw_s / dw_m;
6337
`define SIZE2WIDTH nr_of_wbm_burst
6338
localparam nr_of_wbm_burst_width `SIZE2WIDTH_EXPR
6339
`undef SIZE2WIDTH
6340 100 unneback
 
6341 97 unneback
input [dw_s-1:0] wbs_dat_i;
6342
input [aw_s-1:0] wbs_adr_i; // dont include a1,a0
6343 98 unneback
input [dw_s/8-1:0] wbs_sel_i;
6344 97 unneback
input [2:0] wbs_cti_i;
6345
input [1:0] wbs_bte_i;
6346 98 unneback
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
6347 97 unneback
output [dw_s-1:0] wbs_dat_o;
6348
output wbs_ack_o;
6349 103 unneback
output wbs_stall_o;
6350 97 unneback
input wbs_clk, wbs_rst;
6351
 
6352
output [dw_m-1:0] wbm_dat_o;
6353
output [aw_m-1:0] wbm_adr_o;
6354
output [dw_m/8-1:0] wbm_sel_o;
6355
output [2:0] wbm_cti_o;
6356
output [1:0] wbm_bte_o;
6357 98 unneback
output wbm_stb_o, wbm_cyc_o, wbm_we_o;
6358 97 unneback
input [dw_m-1:0] wbm_dat_i;
6359
input wbm_ack_i;
6360
input wbm_stall_i;
6361
input wbm_clk, wbm_rst;
6362
 
6363 100 unneback
wire valid, dirty, hit;
6364 97 unneback
wire [aw_tag-1:0] tag;
6365
wire tag_mem_we;
6366
wire [aw_tag-1:0] wbs_adr_tag;
6367
wire [aw_slot-1:0] wbs_adr_slot;
6368 98 unneback
wire [aw_offset-1:0] wbs_adr_word;
6369
wire [aw_s-1:0] wbs_adr;
6370 97 unneback
 
6371
reg [1:0] state;
6372
localparam idle = 2'h0;
6373
localparam rdwr = 2'h1;
6374
localparam push = 2'h2;
6375
localparam pull = 2'h3;
6376
wire eoc;
6377 103 unneback
wire we;
6378 97 unneback
 
6379
// cdc
6380
wire done, mem_alert, mem_done;
6381
 
6382 98 unneback
// wbm side
6383
reg [aw_m-1:0] wbm_radr;
6384
reg [aw_m-1:0] wbm_wadr;
6385 137 unneback
//wire [aw_slot-1:0] wbm_adr;
6386
wire [aw_m-1:0] wbm_adr;
6387 98 unneback
wire wbm_radr_cke, wbm_wadr_cke;
6388
 
6389 100 unneback
reg [2:0] phase;
6390
// phase = {we,stb,cyc}
6391
localparam wbm_wait     = 3'b000;
6392
localparam wbm_wr       = 3'b111;
6393
localparam wbm_wr_drain = 3'b101;
6394
localparam wbm_rd       = 3'b011;
6395
localparam wbm_rd_drain = 3'b001;
6396 98 unneback
 
6397 97 unneback
assign {wbs_adr_tag, wbs_adr_slot, wbs_adr_word} = wbs_adr_i;
6398
 
6399 100 unneback
generate
6400
if (valid_mem==0) begin : no_valid_mem
6401
assign valid = 1'b1;
6402
end else begin : valid_mem_inst
6403
`define MODULE dpram_1r1w
6404 97 unneback
`BASE`MODULE
6405 100 unneback
    # ( .data_width(1), .addr_width(aw_slot), .memory_init(2), .debug(debug))
6406
    valid_mem ( .d_a(1'b1), .adr_a(wbs_adr_slot), .we_a(mem_done), .clk_a(wbm_clk),
6407
                .q_b(valid), .adr_b(wbs_adr_slot), .clk_b(wbs_clk));
6408 97 unneback
`undef MODULE
6409 100 unneback
end
6410
endgenerate
6411 97 unneback
 
6412 100 unneback
`define MODULE dpram_1r1w
6413
`BASE`MODULE
6414
    # ( .data_width(aw_tag), .addr_width(aw_slot), .memory_init(2), .debug(debug))
6415
    tag_mem ( .d_a(wbs_adr_tag), .adr_a(wbs_adr_slot), .we_a(mem_done), .clk_a(wbm_clk),
6416
              .q_b(tag), .adr_b(wbs_adr_slot), .clk_b(wbs_clk));
6417
assign hit = wbs_adr_tag == tag;
6418
`undef MODULE
6419
 
6420
`define MODULE dpram_1r2w
6421
`BASE`MODULE
6422
    # ( .data_width(1), .addr_width(aw_slot), .memory_init(2), .debug(debug))
6423
    dirty_mem (
6424
        .d_a(1'b1), .q_a(dirty), .adr_a(wbs_adr_slot), .we_a(wbs_cyc_i & wbs_we_i & wbs_ack_o), .clk_a(wbs_clk),
6425
        .d_b(1'b0), .adr_b(wbs_adr_slot), .we_b(mem_done), .clk_b(wbm_clk));
6426
`undef MODULE
6427
 
6428 103 unneback
generate
6429
if (wbs_mode=="B3") begin : inst_b3
6430 97 unneback
`define MODULE wb_adr_inc
6431 100 unneback
`BASE`MODULE # ( .adr_width(aw_s), .max_burst_width(wbs_max_burst_width)) adr_inc0 (
6432
    .cyc_i(wbs_cyc_i & (state==rdwr) & hit & valid),
6433
    .stb_i(wbs_stb_i & (state==rdwr) & hit & valid), // throttle depending on valid
6434 97 unneback
    .cti_i(wbs_cti_i),
6435
    .bte_i(wbs_bte_i),
6436
    .adr_i(wbs_adr_i),
6437
    .we_i (wbs_we_i),
6438
    .ack_o(wbs_ack_o),
6439
    .adr_o(wbs_adr),
6440 100 unneback
    .clk(wbs_clk),
6441
    .rst(wbs_rst));
6442 97 unneback
`undef MODULE
6443 103 unneback
assign eoc = (wbs_cti_i==3'b000 | wbs_cti_i==3'b111) & wbs_ack_o;
6444
assign we = wbs_cyc_i &  wbs_we_i & wbs_ack_o;
6445
end else if (wbs_mode=="B4") begin : inst_b4
6446
end
6447 97 unneback
 
6448 103 unneback
endgenerate
6449 131 unneback
localparam cache_mem_b_aw =
6450
    (dw_s==dw_m) ? aw_slot+aw_offset :
6451 133 unneback
    (dw_s==dw_m/2) ? aw_slot+aw_offset-1 :
6452
    (dw_s==dw_m/4) ? aw_slot+aw_offset-2 :
6453
    (dw_s==dw_m/8) ? aw_slot+aw_offset-3 :
6454
    (dw_s==dw_m/16) ? aw_slot+aw_offset-4 :
6455
    (dw_s==dw_m*2) ? aw_slot+aw_offset+1 :
6456
    (dw_s==dw_m*4) ? aw_slot+aw_offset+2 :
6457
    (dw_s==dw_m*8) ? aw_slot+aw_offset+3 :
6458
    (dw_s==dw_m*16) ? aw_slot+aw_offset+4 : 0;
6459 103 unneback
 
6460 97 unneback
`define MODULE dpram_be_2r2w
6461
`BASE`MODULE
6462 100 unneback
    # ( .a_data_width(dw_s), .a_addr_width(aw_slot+aw_offset), .b_data_width(dw_m), .debug(debug))
6463 103 unneback
    cache_mem ( .d_a(wbs_dat_i), .adr_a(wbs_adr[aw_slot+aw_offset-1:0]),   .be_a(wbs_sel_i), .we_a(we), .q_a(wbs_dat_o), .clk_a(wbs_clk),
6464 136 unneback
                .d_b(wbm_dat_i), .adr_b(wbm_adr[cache_mem_b_aw-1:0]), .be_b(wbm_sel_o), .we_b(wbm_cyc_o & !wbm_we_o & wbm_ack_i), .q_b(wbm_dat_o), .clk_b(wbm_clk));
6465 97 unneback
`undef MODULE
6466
 
6467
always @ (posedge wbs_clk or posedge wbs_rst)
6468
if (wbs_rst)
6469 98 unneback
    state <= idle;
6470 97 unneback
else
6471
    case (state)
6472
    idle:
6473
        if (wbs_cyc_i)
6474
            state <= rdwr;
6475
    rdwr:
6476 100 unneback
        casex ({valid, hit, dirty, eoc})
6477
        4'b0xxx: state <= pull;
6478
        4'b11x1: state <= idle;
6479
        4'b101x: state <= push;
6480
        4'b100x: state <= pull;
6481
        endcase
6482 97 unneback
    push:
6483
        if (done)
6484
            state <= rdwr;
6485
    pull:
6486
        if (done)
6487
            state <= rdwr;
6488
    default: state <= idle;
6489
    endcase
6490
 
6491
// cdc
6492
generate
6493
if (async==1) begin : cdc0
6494
`define MODULE cdc
6495 100 unneback
`BASE`MODULE cdc0 ( .start_pl(state==rdwr & (!valid | !hit)), .take_it_pl(mem_alert), .take_it_grant_pl(mem_done), .got_it_pl(done), .clk_src(wbs_clk), .rst_src(wbs_rst), .clk_dst(wbm_clk), .rst_dst(wbm_rst));
6496 97 unneback
`undef MODULE
6497
end
6498
else begin : nocdc
6499 100 unneback
    assign mem_alert = state==rdwr & (!valid | !hit);
6500 97 unneback
    assign done = mem_done;
6501
end
6502
endgenerate
6503
 
6504 136 unneback
// FSM generating a number of bursts 4 cycles
6505 97 unneback
// actual number depends on data width ratio
6506
// nr_of_wbm_burst
6507 101 unneback
reg [nr_of_wbm_burst_width+wbm_burst_width-1:0]       cnt_rw, cnt_ack;
6508 97 unneback
 
6509
always @ (posedge wbm_clk or posedge wbm_rst)
6510
if (wbm_rst)
6511 100 unneback
    cnt_rw <= {wbm_burst_width{1'b0}};
6512 97 unneback
else
6513 100 unneback
    if (wbm_cyc_o & wbm_stb_o & !wbm_stall_i)
6514
        cnt_rw <= cnt_rw + 1;
6515 97 unneback
 
6516 98 unneback
always @ (posedge wbm_clk or posedge wbm_rst)
6517
if (wbm_rst)
6518 100 unneback
    cnt_ack <= {wbm_burst_width{1'b0}};
6519 98 unneback
else
6520 100 unneback
    if (wbm_ack_i)
6521
        cnt_ack <= cnt_ack + 1;
6522 97 unneback
 
6523 100 unneback
generate
6524 101 unneback
if (nr_of_wbm_burst==1) begin : one_burst
6525 100 unneback
 
6526 98 unneback
always @ (posedge wbm_clk or posedge wbm_rst)
6527
if (wbm_rst)
6528
    phase <= wbm_wait;
6529
else
6530
    case (phase)
6531
    wbm_wait:
6532
        if (mem_alert)
6533 100 unneback
            if (state==push)
6534
                phase <= wbm_wr;
6535
            else
6536
                phase <= wbm_rd;
6537 98 unneback
    wbm_wr:
6538 100 unneback
        if (&cnt_rw)
6539
            phase <= wbm_wr_drain;
6540
    wbm_wr_drain:
6541
        if (&cnt_ack)
6542 98 unneback
            phase <= wbm_rd;
6543
    wbm_rd:
6544 100 unneback
        if (&cnt_rw)
6545
            phase <= wbm_rd_drain;
6546
    wbm_rd_drain:
6547
        if (&cnt_ack)
6548
            phase <= wbm_wait;
6549 98 unneback
    default: phase <= wbm_wait;
6550
    endcase
6551
 
6552 100 unneback
end else begin : multiple_burst
6553
 
6554 101 unneback
always @ (posedge wbm_clk or posedge wbm_rst)
6555
if (wbm_rst)
6556
    phase <= wbm_wait;
6557
else
6558
    case (phase)
6559
    wbm_wait:
6560
        if (mem_alert)
6561
            if (state==push)
6562
                phase <= wbm_wr;
6563
            else
6564
                phase <= wbm_rd;
6565
    wbm_wr:
6566
        if (&cnt_rw[wbm_burst_width-1:0])
6567
            phase <= wbm_wr_drain;
6568
    wbm_wr_drain:
6569
        if (&cnt_ack)
6570
            phase <= wbm_rd;
6571
        else if (&cnt_ack[wbm_burst_width-1:0])
6572
            phase <= wbm_wr;
6573
    wbm_rd:
6574
        if (&cnt_rw[wbm_burst_width-1:0])
6575
            phase <= wbm_rd_drain;
6576
    wbm_rd_drain:
6577
        if (&cnt_ack)
6578
            phase <= wbm_wait;
6579
        else if (&cnt_ack[wbm_burst_width-1:0])
6580
            phase <= wbm_rd;
6581
    default: phase <= wbm_wait;
6582
    endcase
6583 100 unneback
 
6584 101 unneback
 
6585 100 unneback
end
6586
endgenerate
6587
 
6588 101 unneback
assign mem_done = phase==wbm_rd_drain & (&cnt_ack) & wbm_ack_i;
6589 100 unneback
 
6590
assign wbm_adr_o = (phase[2]) ? {tag, wbs_adr_slot, cnt_rw} : {wbs_adr_tag, wbs_adr_slot, cnt_rw};
6591 137 unneback
assign wbm_adr   = (phase[2]) ? {wbs_adr_slot, cnt_rw} : {wbs_adr_slot, cnt_ack};
6592 100 unneback
assign wbm_sel_o = {dw_m/8{1'b1}};
6593
assign wbm_cti_o = (&cnt_rw | !wbm_stb_o) ? 3'b111 : 3'b010;
6594 98 unneback
assign wbm_bte_o = bte;
6595 100 unneback
assign {wbm_we_o, wbm_stb_o, wbm_cyc_o}  = phase;
6596 98 unneback
 
6597 97 unneback
endmodule
6598
`endif
6599 103 unneback
 
6600
`ifdef WB_AVALON_BRIDGE
6601
// Wishbone to avalon bridge supporting one type of burst transfer only
6602
// intended use is together with cache above
6603
// WB B4 -> pipelined avalon
6604
`define MODULE wb_avalon_bridge
6605
module `BASE`MODULE (
6606
`undef MODULE
6607
        // wishbone slave side
6608
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_stall_o,
6609
        // avalon master side
6610
        readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer,
6611 136 unneback
        init_done,
6612 103 unneback
        // common
6613
        clk, rst);
6614
 
6615
parameter adr_width = 30;
6616
parameter dat_width = 32;
6617
parameter burst_size = 4;
6618
 
6619
input [dat_width-1:0] wbs_dat_i;
6620
input [adr_width-1:0] wbs_adr_i;
6621
input [dat_width/8-1:0]  wbs_sel_i;
6622
input [1:0]  wbs_bte_i;
6623
input [2:0]  wbs_cti_i;
6624
input wbs_we_i;
6625
input wbs_cyc_i;
6626
input wbs_stb_i;
6627 130 unneback
output [dat_width-1:0] wbs_dat_o;
6628 103 unneback
output wbs_ack_o;
6629
output wbs_stall_o;
6630
 
6631
input [dat_width-1:0] readdata;
6632
input readdatavalid;
6633
output [dat_width-1:0] writedata;
6634
output [adr_width-1:0] address;
6635
output [dat_width/8-1:0]  be;
6636
output write;
6637
output read;
6638
output beginbursttransfer;
6639
output [3:0] burstcount;
6640
input waitrequest;
6641 136 unneback
input init_done;
6642 103 unneback
input clk, rst;
6643
 
6644 136 unneback
// cnt1 - initiated read or writes
6645
// cnt2 - # of read or writes in pipeline
6646
reg [3:0] cnt1;
6647
reg [3:0] cnt2;
6648 103 unneback
 
6649 136 unneback
reg next_state, state;
6650
localparam s0 = 1'b0;
6651
localparam s1 = 1'b1;
6652
 
6653
wire eoc;
6654
 
6655
always @ *
6656
begin
6657
    case (state)
6658
    s0: if (init_done & wbs_cyc_i) next_state <= s1;
6659
    s1:
6660
    default: next_state <= state;
6661
    end
6662
end
6663
 
6664 103 unneback
always @ (posedge clk or posedge rst)
6665
if (rst)
6666 136 unneback
    state <= s0;
6667 103 unneback
else
6668 136 unneback
    state <= next_state;
6669 103 unneback
 
6670 136 unneback
assign eoc = state==s1 & !(read | write) & (& !waitrequest & cnt2=;
6671
always @ (posedge clk or posedge rst)
6672
if (rst)
6673
    cnt1 <= 4'h0;
6674
else
6675
    if (read & !waitrequest & init_done)
6676
        cnt1 <= burst_size - 1;
6677
    else if (write & !waitrequest & init_done)
6678
        cnt1 <= cnt1 + 4'h1;
6679
    else if (next_state==idle)
6680
        cnt1 <= 4'h0;
6681
 
6682
always @ (posedge clk or posedge rst)
6683
if (rst)
6684
    cnt2 <= 4'h0;
6685
else
6686
    if (read & !waitrequest & init_done)
6687
        cnt2 <= burst_size - 1;
6688
    else if (write & !waitrequest & init_done & )
6689
        cnt2 <= cnt1 + 4'h1;
6690
    else if (next_state==idle)
6691
        cnt2 <= 4'h0;
6692
 
6693 103 unneback
reg wr_ack;
6694
always @ (posedge clk or posedge rst)
6695
if (rst)
6696
    wr_ack <= 1'b0;
6697
else
6698
    wr_ack <=  (wbs_we_i & wbs_cyc_i & wbs_stb_i & !wbs_stall_o);
6699
 
6700
// to avalon
6701
assign writedata = wbs_dat_i;
6702
assign address = wbs_adr_i;
6703
assign be = wbs_sel_i;
6704 136 unneback
assign write = cnt!=4'h0 & wbs_cyc_i &  wbs_we_i;
6705
assign read  = cnt!=4'h0 & wbs_cyc_i & !wbs_we_i;
6706
assign beginbursttransfer = state==s0 & next_state==s1;
6707 103 unneback
assign burstcount = burst_size;
6708
 
6709
// to wishbone
6710
assign wbs_dat_o = readdata;
6711
assign wbs_ack_o = wr_ack | readdatavalid;
6712
assign wbs_stall_o = waitrequest;
6713
 
6714
endmodule
6715
`endif
6716
 
6717
`ifdef WB_AVALON_MEM_CACHE
6718
`define MODULE wb_avalon_mem_cache
6719
module `BASE`MODULE (
6720
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i, wbs_dat_o, wbs_ack_o, wbs_stall_o, wbs_clk, wbs_rst,
6721
    readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst
6722
);
6723
`undef MODULE
6724
 
6725
// wishbone
6726
parameter wb_dat_width = 32;
6727
parameter wb_adr_width = 22;
6728
parameter wb_max_burst_width = 4;
6729
parameter wb_mode = "B4";
6730
// avalon
6731
parameter avalon_dat_width = 32;
6732 121 unneback
//localparam avalon_adr_width = wb_dat_width * wb_adr_width / avalon_dat_width;
6733 122 unneback
localparam avalon_adr_width =
6734
        (wb_dat_width==avalon_dat_width) ? wb_adr_width :
6735
        (wb_dat_width==avalon_dat_width*2) ? wb_adr_width+1 :
6736
        (wb_dat_width==avalon_dat_width*4) ? wb_adr_width+2 :
6737
        (wb_dat_width==avalon_dat_width*8) ? wb_adr_width+3 :
6738
        (wb_dat_width==avalon_dat_width*16) ? wb_adr_width+4 :
6739
        (wb_dat_width==avalon_dat_width*32) ? wb_adr_width+5 :
6740
        (wb_dat_width==avalon_dat_width/2) ? wb_adr_width-1 :
6741
        (wb_dat_width==avalon_dat_width/4) ? wb_adr_width-2 :
6742
        (wb_dat_width==avalon_dat_width/8) ? wb_adr_width-3 :
6743
        (wb_dat_width==avalon_dat_width/16) ? wb_adr_width-4 :
6744 123 unneback
        (wb_dat_width==avalon_dat_width/32) ? wb_adr_width-5 : 0;
6745 103 unneback
parameter avalon_burst_size = 4;
6746
// cache
6747
parameter async = 1;
6748
parameter nr_of_ways = 1;
6749
parameter aw_offset = 4;
6750
parameter aw_slot = 10;
6751
parameter valid_mem = 1;
6752
// shadow RAM
6753
parameter shadow_ram = 0;
6754
parameter shadow_ram_adr_width = 10;
6755
parameter shadow_ram_size = 1024;
6756
parameter shadow_ram_init = 2; // 0: no init, 1: from file, 2: with zero
6757
parameter shadow_ram_file = "vl_ram.v";
6758
 
6759
input [wb_dat_width-1:0] wbs_dat_i;
6760
input [wb_adr_width-1:0] wbs_adr_i; // dont include a1,a0
6761
input [wb_dat_width/8-1:0] wbs_sel_i;
6762
input [2:0] wbs_cti_i;
6763
input [1:0] wbs_bte_i;
6764
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
6765
output [wb_dat_width-1:0] wbs_dat_o;
6766
output wbs_ack_o;
6767
output wbs_stall_o;
6768
input wbs_clk, wbs_rst;
6769
 
6770
input [avalon_dat_width-1:0] readdata;
6771
input readdatavalid;
6772
output [avalon_dat_width-1:0] writedata;
6773
output [avalon_adr_width-1:0] address;
6774
output [avalon_dat_width/8-1:0]  be;
6775
output write;
6776
output read;
6777
output beginbursttransfer;
6778
output [3:0] burstcount;
6779
input waitrequest;
6780
input clk, rst;
6781
 
6782
`define DAT_WIDTH wb_dat_width
6783
`define ADR_WIDTH wb_adr_width
6784
`define WB wb1
6785
`include "wb_wires.v"
6786 129 unneback
`undef DAT_WIDTH
6787
`undef ADR_WIDTH
6788
`define DAT_WIDTH avalon_dat_width
6789
`define ADR_WIDTH avalon_adr_width
6790 103 unneback
`define WB wb2
6791
`include "wb_wires.v"
6792
`undef DAT_WIDTH
6793
`undef ADR_WIDTH
6794
 
6795
`define MODULE wb_shadow_ram
6796
`BASE`MODULE # ( .dat_width(wb_dat_width), .mode(wb_mode), .max_burst_width(wb_max_burst_width),
6797 120 unneback
                 .shadow_mem_adr_width(shadow_ram_adr_width), .shadow_mem_size(shadow_ram_size), .shadow_mem_init(shadow_ram_init), .shadow_mem_file(shadow_ram_file),
6798 103 unneback
                 .main_mem_adr_width(wb_adr_width))
6799
shadow_ram0 (
6800
    .wbs_dat_i(wbs_dat_i), .wbs_adr_i(wbs_adr_i), .wbs_cti_i(wbs_cti_i), .wbs_bte_i(wbs_bte_i), .wbs_sel_i(wbs_sel_i), .wbs_we_i(wbs_we_i), .wbs_stb_i(wbs_stb_i), .wbs_cyc_i(wbs_cyc_i),
6801
    .wbs_dat_o(wbs_dat_o), .wbs_ack_o(wbs_ack_o), .wbs_stall_o(wbs_stall_o),
6802
    .wbm_dat_o(wb1_dat_o), .wbm_adr_o(wb1_adr_o), .wbm_cti_o(wb1_cti_o), .wbm_bte_o(wb1_bte_o), .wbm_sel_o(wb1_sel_o), .wbm_we_o(wb1_we_o), .wbm_stb_o(wb1_stb_o), .wbm_cyc_o(wb1_cyc_o),
6803
    .wbm_dat_i(wb1_dat_i), .wbm_ack_i(wb1_ack_i), .wbm_stall_i(wb1_stall_i),
6804
    .wb_clk(wbs_clk), .wb_rst(wbs_rst));
6805
`undef MODULE
6806
 
6807
`define MODULE wb_cache
6808
`BASE`MODULE
6809
# ( .dw_s(wb_dat_width), .aw_s(wb_adr_width), .dw_m(avalon_dat_width), .wbs_mode(wb_mode), .wbs_max_burst_width(wb_max_burst_width), .async(async), .nr_of_ways(nr_of_ways), .aw_offset(aw_offset), .aw_slot(aw_slot), .valid_mem(valid_mem))
6810
cache0 (
6811
    .wbs_dat_i(wb1_dat_o), .wbs_adr_i(wb1_adr_o), .wbs_sel_i(wb1_sel_o), .wbs_cti_i(wb1_cti_o), .wbs_bte_i(wb1_bte_o), .wbs_we_i(wb1_we_o), .wbs_stb_i(wb1_stb_o), .wbs_cyc_i(wb1_cyc_o),
6812
    .wbs_dat_o(wb1_dat_i), .wbs_ack_o(wb1_ack_i), .wbs_stall_o(wb1_stall_i), .wbs_clk(wbs_clk), .wbs_rst(wbs_rst),
6813
    .wbm_dat_o(wb2_dat_o), .wbm_adr_o(wb2_adr_o), .wbm_sel_o(wb2_sel_o), .wbm_cti_o(wb2_cti_o), .wbm_bte_o(wb2_bte_o), .wbm_we_o(wb2_we_o), .wbm_stb_o(wb2_stb_o), .wbm_cyc_o(wb2_cyc_o),
6814
    .wbm_dat_i(wb2_dat_i), .wbm_ack_i(wb2_ack_i), .wbm_stall_i(wb2_stall_i), .wbm_clk(clk), .wbm_rst(rst));
6815
`undef MODULE
6816
 
6817
`define MODULE wb_avalon_bridge
6818
`BASE`MODULE # ( .adr_width(avalon_adr_width), .dat_width(avalon_dat_width), .burst_size(avalon_burst_size))
6819
bridge0 (
6820
        // wishbone slave side
6821
        .wbs_dat_i(wb2_dat_o), .wbs_adr_i(wb2_adr_o), .wbs_sel_i(wb2_sel_o), .wbs_bte_i(wb2_bte_o), .wbs_cti_i(wb2_cti_o), .wbs_we_i(wb2_we_o), .wbs_cyc_i(wb2_cyc_o), .wbs_stb_i(wb2_stb_o),
6822
        .wbs_dat_o(wb2_dat_i), .wbs_ack_o(wb2_ack_i), .wbs_stall_o(wb2_stall_i),
6823
        // avalon master side
6824
        .readdata(readdata), .readdatavalid(readdatavalid), .address(address), .read(read), .be(be), .write(write), .burstcount(burstcount), .writedata(writedata), .waitrequest(waitrequest), .beginbursttransfer(beginbursttransfer),
6825
        // common
6826
        .clk(clk), .rst(rst));
6827
`undef MODULE
6828
 
6829
endmodule
6830
`endif
6831 105 unneback
 
6832
`ifdef WB_SDR_SDRAM
6833
`define MODULE wb_sdr_sdram
6834
module `BASE`MODULE (
6835
`undef MODULE
6836
    // wisbone i/f
6837 136 unneback
    dat_i, adr_i, sel_i, we_i, cyc_i, stb_i, dat_o, ack_o, stall_o,
6838 105 unneback
    // SDR SDRAM
6839
    ba, a, cmd, cke, cs_n, dqm, dq_i, dq_o, dq_oe,
6840
    // system
6841
    clk, rst);
6842
 
6843
    // external data bus size
6844
    parameter dat_size = 16;
6845
    // memory geometry parameters
6846 136 unneback
    parameter ba_size  = 2;
6847
    parameter row_size = 13;
6848
    parameter col_size = 9;
6849 105 unneback
    parameter cl = 2;
6850
    // memory timing parameters
6851
    parameter tRFC = 9;
6852
    parameter tRP  = 2;
6853
    parameter tRCD = 2;
6854
    parameter tMRD = 2;
6855
 
6856
    // LMR
6857
    // [12:10] reserved
6858
    // [9]     WB, write burst; 0 - programmed burst length, 1 - single location
6859
    // [8:7]   OP Mode, 2'b00
6860
    // [6:4]   CAS Latency; 3'b010 - 2, 3'b011 - 3
6861
    // [3]     BT, Burst Type; 1'b0 - sequential, 1'b1 - interleaved
6862
    // [2:0]   Burst length; 3'b000 - 1, 3'b001 - 2, 3'b010 - 4, 3'b011 - 8, 3'b111 - full page
6863
    localparam init_wb = 1'b1;
6864
    localparam init_cl = (cl==2) ? 3'b010 : 3'b011;
6865
    localparam init_bt = 1'b0;
6866
    localparam init_bl = 3'b000;
6867
 
6868 136 unneback
    input [dat_size-1:0] dat_i;
6869 105 unneback
    input [ba_size+col_size+row_size-1:0] adr_i;
6870
    input [dat_size/8-1:0] sel_i;
6871
    input we_i, cyc_i, stb_i;
6872
    output [dat_size-1:0] dat_o;
6873
    output ack_o;
6874
    output reg stall_o;
6875
 
6876
    output [ba_size-1:0]    ba;
6877
    output reg [12:0]   a;
6878
    output reg [2:0]    cmd; // {ras,cas,we}
6879
    output cke, cs_n;
6880
    output reg [dat_size/8-1:0]    dqm;
6881
    output [dat_size-1:0]       dq_o;
6882
    output reg          dq_oe;
6883
    input  [dat_size-1:0]       dq_i;
6884
 
6885
    input clk, rst;
6886
 
6887
    wire [ba_size-1:0]   bank;
6888
    wire [row_size-1:0] row;
6889
    wire [col_size-1:0] col;
6890
    wire [0:31]  shreg;
6891
    wire                ref_cnt_zero;
6892
    reg                 refresh_req;
6893
 
6894
    wire ack_rd, rd_ack_emptyflag;
6895
    wire ack_wr;
6896
 
6897
    // to keep track of open rows per bank
6898
    reg [row_size-1:0]   open_row[0:3];
6899
    reg [0:3]            open_ba;
6900
    reg                 current_bank_closed, current_row_open;
6901
 
6902
    parameter rfr_length = 10;
6903
    parameter rfr_wrap_value = 1010;
6904
 
6905
    parameter [2:0] cmd_nop = 3'b111,
6906
                    cmd_act = 3'b011,
6907
                    cmd_rd  = 3'b101,
6908
                    cmd_wr  = 3'b100,
6909
                    cmd_pch = 3'b010,
6910
                    cmd_rfr = 3'b001,
6911
                    cmd_lmr = 3'b000;
6912
 
6913
// ctrl FSM
6914
`define FSM_INIT 3'b000
6915
`define FSM_IDLE 3'b001
6916
`define FSM_RFR  3'b010
6917
`define FSM_ADR  3'b011
6918
`define FSM_PCH  3'b100
6919
`define FSM_ACT  3'b101
6920
`define FSM_RW   3'b111
6921
 
6922
    assign cke = 1'b1;
6923
    assign cs_n = 1'b0;
6924
 
6925
    reg [2:0] state, next;
6926
 
6927
    function [12:0] a10_fix;
6928
        input [col_size-1:0] a;
6929
        integer i;
6930
    begin
6931
        for (i=0;i<13;i=i+1) begin
6932
            if (i<10)
6933
              if (i<col_size)
6934
                a10_fix[i] = a[i];
6935
              else
6936
                a10_fix[i] = 1'b0;
6937
            else if (i==10)
6938
              a10_fix[i] = 1'b0;
6939
            else
6940
              if (i<col_size)
6941
                a10_fix[i] = a[i-1];
6942
              else
6943
                a10_fix[i] = 1'b0;
6944
        end
6945
    end
6946
    endfunction
6947
 
6948
    assign {bank,row,col} = adr_i;
6949
 
6950
    always @ (posedge clk or posedge rst)
6951
    if (rst)
6952
       state <= `FSM_INIT;
6953
    else
6954
       state <= next;
6955
 
6956
    always @*
6957
    begin
6958
        next = state;
6959
        case (state)
6960
        `FSM_INIT:
6961
            if (shreg[3+tRP+tRFC+tRFC+tMRD]) next = `FSM_IDLE;
6962
        `FSM_IDLE:
6963
            if (refresh_req) next = `FSM_RFR;
6964
            else if (cyc_i & stb_i & rd_ack_emptyflag) next = `FSM_ADR;
6965
        `FSM_RFR:
6966
            if (shreg[tRP+tRFC-2]) next = `FSM_IDLE; // take away two cycles because no cmd will be issued in idle and adr
6967
        `FSM_ADR:
6968
            if (current_bank_closed) next = `FSM_ACT;
6969
            else if (current_row_open) next = `FSM_RW;
6970
            else next = `FSM_PCH;
6971
        `FSM_PCH:
6972
            if (shreg[tRP]) next = `FSM_ACT;
6973
        `FSM_ACT:
6974
            if (shreg[tRCD]) next = `FSM_RW;
6975
        `FSM_RW:
6976
            if (!stb_i) next = `FSM_IDLE;
6977
        endcase
6978
    end
6979
 
6980
    // counter
6981 136 unneback
`define MODULE cnt_shreg_clear
6982
    `BASE`MODULE # ( .length(32))
6983 105 unneback
`undef MODULE
6984
        cnt0 (
6985
            .clear(state!=next),
6986
            .q(shreg),
6987
            .rst(rst),
6988
            .clk(clk));
6989
 
6990
    // ba, a, cmd
6991
    // outputs dependent on state vector
6992
    always @ (*)
6993
        begin
6994
            {a,cmd} = {13'd0,cmd_nop};
6995
            dqm = 2'b11;
6996
            dq_oe = 1'b0;
6997
            stall_o = 1'b1;
6998
            case (state)
6999
            `FSM_INIT:
7000
                if (shreg[3]) begin
7001
                    {a,cmd} = {13'b0010000000000, cmd_pch};
7002
                end else if (shreg[3+tRP] | shreg[3+tRP+tRFC])
7003
                    {a,cmd} = {13'd0, cmd_rfr};
7004
                else if (shreg[3+tRP+tRFC+tRFC])
7005
                    {a,cmd} = {3'b000,init_wb,2'b00,init_cl,init_bt,init_bl,cmd_lmr};
7006
            `FSM_RFR:
7007
                if (shreg[0])
7008
                    {a,cmd} = {13'b0010000000000, cmd_pch};
7009
                else if (shreg[tRP])
7010
                    {a,cmd} = {13'd0, cmd_rfr};
7011
            `FSM_PCH:
7012
                if (shreg[0])
7013
                    {a,cmd} = {13'd0,cmd_pch};
7014
            `FSM_ACT:
7015
                if (shreg[0])
7016
                    {a[row_size-1:0],cmd} = {row,cmd_act};
7017
            `FSM_RW:
7018
                begin
7019
                    if (we_i)
7020
                        cmd = cmd_wr;
7021
                    else
7022
                        cmd = cmd_rd;
7023
                    if (we_i)
7024
                        dqm = ~sel_i;
7025
                    else
7026
                        dqm = 2'b00;
7027
                    if (we_i)
7028
                        dq_oe = 1'b1;
7029
                    a = a10_fix(col);
7030 136 unneback
                    stall_o = 1'b0;
7031 105 unneback
                end
7032
            endcase
7033
        end
7034
 
7035
    assign ba = bank;
7036
 
7037
    // precharge individual bank A10=0
7038
    // precharge all bank A10=1
7039
    genvar i;
7040
    generate
7041 136 unneback
    for (i=0;i<2<<ba_size-1;i=i+1) begin : open_ba_logic
7042 105 unneback
 
7043
        always @ (posedge clk or posedge rst)
7044
        if (rst)
7045
            {open_ba[i],open_row[i]} <= {1'b0,{row_size{1'b0}}};
7046
        else
7047
            if (cmd==cmd_pch & (a[10] | bank==i))
7048
                open_ba[i] <= 1'b0;
7049
            else if (cmd==cmd_act & bank==i)
7050
                {open_ba[i],open_row[i]} <= {1'b1,row};
7051
 
7052
    end
7053
    endgenerate
7054
 
7055
    // bank and row open ?
7056
    always @ (posedge clk or posedge rst)
7057
    if (rst)
7058
       {current_bank_closed, current_row_open} <= {1'b1, 1'b0};
7059
    else
7060
       {current_bank_closed, current_row_open} <= {!(open_ba[bank]), open_row[bank]==row};
7061
 
7062
    // refresh counter
7063
`define MODULE cnt_lfsr_zq
7064 136 unneback
    `BASE`MODULE # ( .length(rfr_length), .wrap_value (rfr_wrap_value)) ref_counter0( .zq(ref_cnt_zero), .rst(rst), .clk(clk));
7065 105 unneback
`undef MODULE
7066
 
7067
    always @ (posedge clk or posedge rst)
7068
    if (rst)
7069
        refresh_req <= 1'b0;
7070
    else
7071
        if (ref_cnt_zero)
7072
            refresh_req <= 1'b1;
7073
        else if (state==`FSM_RFR)
7074
            refresh_req <= 1'b0;
7075
 
7076
    assign dat_o = dq_i;
7077
 
7078 136 unneback
    assign ack_wr = (state==`FSM_RW & we_i);
7079 105 unneback
`define MODULE delay_emptyflag
7080 136 unneback
    `BASE`MODULE # ( .depth(cl+2)) delay0 ( .d(state==`FSM_RW & stb_i & !we_i), .q(ack_rd), .emptyflag(rd_ack_emptyflag), .clk(clk), .rst(rst));
7081 105 unneback
`undef MODULE
7082
    assign ack_o = ack_rd | ack_wr;
7083
 
7084
    assign dq_o = dat_i;
7085
 
7086
endmodule
7087
`endif
7088 136 unneback
 
7089
`ifdef WB_SDR_SDRAM_CTRL
7090
`define MODULE wb_sdr_sdram_ctrl
7091
module `BASE`MODULE (
7092
    // WB i/f
7093
    wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
7094
    wbs_dat_o, wbs_ack_o, wbs_stall_o,
7095
    // SDR SDRAM
7096
    mem_ba, mem_a, mem_cmd, mem_cke, mem_cs_n, mem_dqm, mem_dq_i, mem_dq_o, mem_dq_oe,
7097
    // system
7098
    wb_clk, wb_rst, mem_clk, mem_rst);
7099
`undef MODULE
7100
 
7101
    // WB slave
7102
    parameter wbs_dat_width = 32;
7103
    parameter wbs_adr_width = 24;
7104
    parameter wbs_mode = "B3";
7105
    parameter wbs_max_burst_width = 4;
7106
 
7107
    // Shadow RAM
7108
    parameter shadow_mem_adr_width = 10;
7109
    parameter shadow_mem_size = 1024;
7110
    parameter shadow_mem_init = 2;
7111
    parameter shadow_mem_file = "vl_ram.v";
7112
 
7113
    // Cache
7114
    parameter cache_async = 1; // wbs_clk != wbm_clk
7115
    parameter cache_nr_of_ways = 1;
7116
    parameter cache_aw_offset = 4; // 4 => 16 words per cache line
7117
    parameter cache_aw_slot = 10;
7118
    parameter cache_valid_mem = 0;
7119
    parameter cache_debug = 0;
7120
 
7121
    // SDRAM parameters
7122
    parameter mem_dat_size = 16;
7123
    parameter mem_ba_size  = 2;
7124
    parameter mem_row_size = 13;
7125
    parameter mem_col_size = 9;
7126
    parameter mem_cl = 2;
7127
    parameter mem_tRFC = 9;
7128
    parameter mem_tRP  = 2;
7129
    parameter mem_tRCD = 2;
7130
    parameter mem_tMRD = 2;
7131
    parameter mem_rfr_length = 10;
7132
    parameter mem_rfr_wrap_value = 1010;
7133
 
7134
    input [wbs_dat_width-1:0] wbs_dat_i;
7135
    input [wbs_adr_width-1:0] wbs_adr_i;
7136
    input [2:0] wbs_cti_i;
7137
    input [1:0] wbs_bte_i;
7138
    input [wbs_dat_width/8-1:0] wbs_sel_i;
7139
    input wbs_we_i, wbs_stb_i, wbs_cyc_i;
7140
    output [wbs_dat_width-1:0] wbs_dat_o;
7141
    output wbs_ack_o;
7142
    output wbs_stall_o;
7143
 
7144
    output [mem_ba_size-1:0]    mem_ba;
7145
    output reg [12:0]           mem_a;
7146
    output reg [2:0]            mem_cmd; // {ras,cas,we}
7147
    output                      mem_cke, mem_cs_n;
7148
    output reg [mem_dat_size/8-1:0] mem_dqm;
7149
    output [mem_dat_size-1:0]       mem_dq_o;
7150
    output reg                  mem_dq_oe;
7151
    input  [mem_dat_size-1:0]       mem_dq_i;
7152
 
7153
    input wb_clk, wb_rst, mem_clk, mem_rst;
7154
 
7155
    // wbm1
7156
    wire [wbs_dat_width-1:0] wbm1_dat_o;
7157
    wire [wbs_adr_width-1:0] wbm1_adr_o;
7158
    wire [2:0] wbm1_cti_o;
7159
    wire [1:0] wbm1_bte_o;
7160
    wire [wbs_dat_width/8-1:0] wbm1_sel_o;
7161
    wire wbm1_we_o, wbm1_stb_o, wbm1_cyc_o;
7162
    wire [wbs_dat_width-1:0] wbm1_dat_i;
7163
    wire wbm1_ack_i, wbm1_stall_i;
7164
    // wbm2
7165
    wire [mem_dat_size-1:0] wbm2_dat_o;
7166
    wire [mem_ba_size+mem_row_size+mem_col_size-1:0] wbm2_adr_o;
7167
    wire [2:0] wbm2_cti_o;
7168
    wire [1:0] wbm2_bte_o;
7169
    wire [mem_dat_size/8-1:0] wbm2_sel_o;
7170
    wire wbm2_we_o, wbm2_stb_o, wbm2_cyc_o;
7171
    wire [mem_dat_size-1:0] wbm2_dat_i;
7172
    wire wbm2_ack_i, wbm2_stall_i;
7173
 
7174
`define MODULE wb_shadow_ram
7175
`BASE`MODULE # (
7176
    .shadow_mem_adr_width(shadow_mem_adr_width), .shadow_mem_size(shadow_mem_size), .shadow_mem_init(shadow_mem_init), .shadow_mem_file(shadow_mem_file), .main_mem_adr_width(wbs_adr_width), .dat_width(wbs_dat_width), .mode(wbs_mode), .max_burst_width(wbs_max_burst_width) )
7177
shadow_ram0 (
7178
    .wbs_dat_i(wbs_dat_i),
7179
    .wbs_adr_i(wbs_adr_i),
7180
    .wbs_cti_i(wbs_cti_i),
7181
    .wbs_bte_i(wbs_bte_i),
7182
    .wbs_sel_i(wbs_sel_i),
7183
    .wbs_we_i (wbs_we_i),
7184
    .wbs_stb_i(wbs_stb_i),
7185
    .wbs_cyc_i(wbs_cyc_i),
7186
    .wbs_dat_o(wbs_dat_o),
7187
    .wbs_ack_o(wbs_ack_o),
7188
    .wbs_stall_o(wbs_stall_o),
7189
    .wbm_dat_o(wbm1_dat_o),
7190
    .wbm_adr_o(wbm1_adr_o),
7191
    .wbm_cti_o(wbm1_cti_o),
7192
    .wbm_bte_o(wbm1_bte_o),
7193
    .wbm_sel_o(wbm1_sel_o),
7194
    .wbm_we_o(wbm1_we_o),
7195
    .wbm_stb_o(wbm1_stb_o),
7196
    .wbm_cyc_o(wbm1_cyc_o),
7197
    .wbm_dat_i(wbm1_dat_i),
7198
    .wbm_ack_i(wbm1_ack_i),
7199
    .wbm_stall_i(wbm1_stall_i),
7200
    .wb_clk(wb_clk),
7201
    .wb_rst(wb_rst) );
7202
`undef MODULE
7203
 
7204
`define MODULE wb_cache
7205
`BASE`MODULE # (
7206
    .dw_s(wbs_dat_width), .aw_s(wbs_adr_width), .dw_m(mem_dat_size), .wbs_max_burst_width(cache_aw_offset), .wbs_mode(wbs_mode), .async(cache_async), .nr_of_ways(cache_nr_of_ways), .aw_offset(cache_aw_offset), .aw_slot(cache_aw_slot), .valid_mem(cache_valid_mem) )
7207
cache0 (
7208
    .wbs_dat_i(wbm1_dat_o),
7209
    .wbs_adr_i(wbm1_adr_o),
7210
    .wbs_sel_i(wbm1_sel_o),
7211
    .wbs_cti_i(wbm1_cti_o),
7212
    .wbs_bte_i(wbm1_bte_o),
7213
    .wbs_we_i (wbm1_we_o),
7214
    .wbs_stb_i(wbm1_stb_o),
7215
    .wbs_cyc_i(wbm1_cyc_o),
7216
    .wbs_dat_o(wbm1_dat_i),
7217
    .wbs_ack_o(wbm1_ack_i),
7218
    .wbs_stall_o(wbm1_stall_i),
7219
    .wbs_clk(wb_clk),
7220
    .wbs_rst(wb_rst),
7221
    .wbm_dat_o(wbm2_dat_o),
7222
    .wbm_adr_o(wbm2_adr_o),
7223
    .wbm_sel_o(wbm2_sel_o),
7224
    .wbm_cti_o(wbm2_cti_o),
7225
    .wbm_bte_o(wbm2_bte_o),
7226
    .wbm_we_o (wbm2_we_o),
7227
    .wbm_stb_o(wbm2_stb_o),
7228
    .wbm_cyc_o(wbm2_cyc_o),
7229
    .wbm_dat_i(wbm2_dat_i),
7230
    .wbm_ack_i(wbm2_ack_i),
7231
    .wbm_stall_i(wbm2_stall_i),
7232
    .wbm_clk(mem_clk),
7233
    .wbm_rst(mem_rst) );
7234
`undef MODULE
7235
 
7236
`define MODULE wb_sdr_sdram
7237
`BASE`MODULE # (
7238
    .dat_size(mem_dat_size), .ba_size(mem_ba_size), .row_size(mem_row_size), .col_size(mem_col_size), .cl(mem_cl), .tRFC(mem_tRFC), .tRP(mem_tRP), .tRCD(mem_tRCD), .tMRD(mem_tMRD), .rfr_length(mem_rfr_length), .rfr_wrap_value(mem_rfr_wrap_value) )
7239
ctrl0(
7240
    // wisbone i/f
7241
    .dat_i(wbm2_dat_o),
7242
    .adr_i(wbm2_adr_o),
7243
    .sel_i(wbm2_sel_o),
7244
    .we_i (wbm2_we_o),
7245
    .cyc_i(wbm2_cyc_o),
7246
    .stb_i(wbm2_stb_o),
7247
    .dat_o(wbm2_dat_i),
7248
    .ack_o(wbm2_ack_i),
7249
    .stall_o(wbm2_stall_i),
7250
    // SDR SDRAM
7251
    .ba(mem_ba),
7252
    .a(mem_a),
7253
    .cmd(mem_cmd),
7254
    .cke(mem_cke),
7255
    .cs_n(mem_cs_n),
7256
    .dqm(mem_dqm),
7257
    .dq_i(mem_dq_i),
7258
    .dq_o(mem_dq_o),
7259
    .dq_oe(mem_dq_oe),
7260
    // system
7261
    .clk(mem_clk),
7262
    .rst(mem_rst) );
7263
`undef MODULE
7264
 
7265
endmodule
7266
`endif
7267 18 unneback
//////////////////////////////////////////////////////////////////////
7268
////                                                              ////
7269
////  Arithmetic functions                                        ////
7270
////                                                              ////
7271
////  Description                                                 ////
7272
////  Arithmetic functions for ALU and DSP                        ////
7273
////                                                              ////
7274
////                                                              ////
7275
////  To Do:                                                      ////
7276
////   -                                                          ////
7277
////                                                              ////
7278
////  Author(s):                                                  ////
7279
////      - Michael Unneback, unneback@opencores.org              ////
7280
////        ORSoC AB                                              ////
7281
////                                                              ////
7282
//////////////////////////////////////////////////////////////////////
7283
////                                                              ////
7284
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
7285
////                                                              ////
7286
//// This source file may be used and distributed without         ////
7287
//// restriction provided that this copyright statement is not    ////
7288
//// removed from the file and that any derivative work contains  ////
7289
//// the original copyright notice and the associated disclaimer. ////
7290
////                                                              ////
7291
//// This source file is free software; you can redistribute it   ////
7292
//// and/or modify it under the terms of the GNU Lesser General   ////
7293
//// Public License as published by the Free Software Foundation; ////
7294
//// either version 2.1 of the License, or (at your option) any   ////
7295
//// later version.                                               ////
7296
////                                                              ////
7297
//// This source is distributed in the hope that it will be       ////
7298
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
7299
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
7300
//// PURPOSE.  See the GNU Lesser General Public License for more ////
7301
//// details.                                                     ////
7302
////                                                              ////
7303
//// You should have received a copy of the GNU Lesser General    ////
7304
//// Public License along with this source; if not, download it   ////
7305
//// from http://www.opencores.org/lgpl.shtml                     ////
7306
////                                                              ////
7307
//////////////////////////////////////////////////////////////////////
7308
 
7309 40 unneback
`ifdef MULTS
7310 18 unneback
// signed multiplication
7311 40 unneback
`define MODULE mults
7312
module `BASE`MODULE (a,b,p);
7313
`undef MODULE
7314 18 unneback
parameter operand_a_width = 18;
7315
parameter operand_b_width = 18;
7316
parameter result_hi = 35;
7317
parameter result_lo = 0;
7318
input [operand_a_width-1:0] a;
7319
input [operand_b_width-1:0] b;
7320
output [result_hi:result_lo] p;
7321
wire signed [operand_a_width-1:0] ai;
7322
wire signed [operand_b_width-1:0] bi;
7323
wire signed [operand_a_width+operand_b_width-1:0] result;
7324
 
7325
    assign ai = a;
7326
    assign bi = b;
7327
    assign result = ai * bi;
7328
    assign p = result[result_hi:result_lo];
7329
 
7330
endmodule
7331 40 unneback
`endif
7332
`ifdef MULTS18X18
7333
`define MODULE mults18x18
7334
module `BASE`MODULE (a,b,p);
7335
`undef MODULE
7336 18 unneback
input [17:0] a,b;
7337
output [35:0] p;
7338
vl_mult
7339
    # (.operand_a_width(18), .operand_b_width(18))
7340
    mult0 (.a(a), .b(b), .p(p));
7341
endmodule
7342 40 unneback
`endif
7343 18 unneback
 
7344 40 unneback
`ifdef MULT
7345
`define MODULE mult
7346 18 unneback
// unsigned multiplication
7347 40 unneback
module `BASE`MODULE (a,b,p);
7348
`undef MODULE
7349 18 unneback
parameter operand_a_width = 18;
7350
parameter operand_b_width = 18;
7351
parameter result_hi = 35;
7352
parameter result_lo = 0;
7353
input [operand_a_width-1:0] a;
7354
input [operand_b_width-1:0] b;
7355
output [result_hi:result_hi] p;
7356
 
7357
wire [operand_a_width+operand_b_width-1:0] result;
7358
 
7359
    assign result = a * b;
7360
    assign p = result[result_hi:result_lo];
7361
 
7362
endmodule
7363 40 unneback
`endif
7364 18 unneback
 
7365 40 unneback
`ifdef SHIFT_UNIT_32
7366
`define MODULE shift_unit_32
7367 18 unneback
// shift unit
7368
// supporting the following shift functions
7369
//   SLL
7370
//   SRL
7371
//   SRA
7372
`define SHIFT_UNIT_MULT # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7))
7373 40 unneback
module `BASE`MODULE( din, s, dout, opcode);
7374
`undef MODULE
7375 18 unneback
input [31:0] din; // data in operand
7376
input [4:0] s; // shift operand
7377
input [1:0] opcode;
7378
output [31:0] dout;
7379
 
7380
parameter opcode_sll = 2'b00;
7381
//parameter opcode_srl = 2'b01;
7382
parameter opcode_sra = 2'b10;
7383
//parameter opcode_ror = 2'b11;
7384
 
7385
wire sll, sra;
7386
assign sll = opcode == opcode_sll;
7387
assign sra = opcode == opcode_sra;
7388
 
7389
wire [15:1] s1;
7390
wire [3:0] sign;
7391
wire [7:0] tmp [0:3];
7392
 
7393
// first stage is multiplier based
7394
// shift operand as fractional 8.7
7395
assign s1[15] = sll & s[2:0]==3'd7;
7396
assign s1[14] = sll & s[2:0]==3'd6;
7397
assign s1[13] = sll & s[2:0]==3'd5;
7398
assign s1[12] = sll & s[2:0]==3'd4;
7399
assign s1[11] = sll & s[2:0]==3'd3;
7400
assign s1[10] = sll & s[2:0]==3'd2;
7401
assign s1[ 9] = sll & s[2:0]==3'd1;
7402
assign s1[ 8] = s[2:0]==3'd0;
7403
assign s1[ 7] = !sll & s[2:0]==3'd1;
7404
assign s1[ 6] = !sll & s[2:0]==3'd2;
7405
assign s1[ 5] = !sll & s[2:0]==3'd3;
7406
assign s1[ 4] = !sll & s[2:0]==3'd4;
7407
assign s1[ 3] = !sll & s[2:0]==3'd5;
7408
assign s1[ 2] = !sll & s[2:0]==3'd6;
7409
assign s1[ 1] = !sll & s[2:0]==3'd7;
7410
 
7411
assign sign[3] = din[31] & sra;
7412
assign sign[2] = sign[3] & (&din[31:24]);
7413
assign sign[1] = sign[2] & (&din[23:16]);
7414
assign sign[0] = sign[1] & (&din[15:8]);
7415 40 unneback
`define MODULE mults
7416
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte3 ( .a({sign[3], {8{sign[3]}},din[31:24], din[23:16]}), .b({1'b0,s1}), .p(tmp[3]));
7417
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte2 ( .a({sign[2], din[31:24]  ,din[23:16],  din[15:8]}), .b({1'b0,s1}), .p(tmp[2]));
7418
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte1 ( .a({sign[1], din[23:16]  ,din[15:8],   din[7:0]}), .b({1'b0,s1}), .p(tmp[1]));
7419
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte0 ( .a({sign[0], din[15:8]   ,din[7:0],    8'h00}),      .b({1'b0,s1}), .p(tmp[0]));
7420
`undef MODULE
7421 18 unneback
// second stage is multiplexer based
7422
// shift on byte level
7423
 
7424
// mux byte 3
7425
assign dout[31:24] = (s[4:3]==2'b00) ? tmp[3] :
7426
                     (sll & s[4:3]==2'b01) ? tmp[2] :
7427
                     (sll & s[4:3]==2'b10) ? tmp[1] :
7428
                     (sll & s[4:3]==2'b11) ? tmp[0] :
7429
                     {8{sign[3]}};
7430
 
7431
// mux byte 2
7432
assign dout[23:16] = (s[4:3]==2'b00) ? tmp[2] :
7433
                     (sll & s[4:3]==2'b01) ? tmp[1] :
7434
                     (sll & s[4:3]==2'b10) ? tmp[0] :
7435
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
7436
                     (s[4:3]==2'b01) ? tmp[3] :
7437
                     {8{sign[3]}};
7438
 
7439
// mux byte 1
7440
assign dout[15:8]  = (s[4:3]==2'b00) ? tmp[1] :
7441
                     (sll & s[4:3]==2'b01) ? tmp[0] :
7442
                     (sll & s[4:3]==2'b10) ? {8{1'b0}} :
7443
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
7444
                     (s[4:3]==2'b01) ? tmp[2] :
7445
                     (s[4:3]==2'b10) ? tmp[3] :
7446
                     {8{sign[3]}};
7447
 
7448
// mux byte 0
7449
assign dout[7:0]   = (s[4:3]==2'b00) ? tmp[0] :
7450
                     (sll) ?  {8{1'b0}}:
7451
                     (s[4:3]==2'b01) ? tmp[1] :
7452
                     (s[4:3]==2'b10) ? tmp[2] :
7453
                     tmp[3];
7454
 
7455
endmodule
7456 40 unneback
`endif
7457 18 unneback
 
7458 40 unneback
`ifdef LOGIC_UNIT
7459 18 unneback
// logic unit
7460
// supporting the following logic functions
7461
//    a and b
7462
//    a or  b
7463
//    a xor b
7464
//    not b
7465 40 unneback
`define MODULE logic_unit
7466
module `BASE`MODULE( a, b, result, opcode);
7467
`undef MODULE
7468 18 unneback
parameter width = 32;
7469
parameter opcode_and = 2'b00;
7470
parameter opcode_or  = 2'b01;
7471
parameter opcode_xor = 2'b10;
7472
input [width-1:0] a,b;
7473
output [width-1:0] result;
7474
input [1:0] opcode;
7475
 
7476
assign result = (opcode==opcode_and) ? a & b :
7477
                (opcode==opcode_or)  ? a | b :
7478
                (opcode==opcode_xor) ? a ^ b :
7479
                b;
7480
 
7481
endmodule
7482 48 unneback
`endif
7483 18 unneback
 
7484 48 unneback
`ifdef ARITH_UNIT
7485
`define MODULE arith_unit
7486
module `BASE`MODULE ( a, b, c_in, add_sub, sign, result, c_out, z, ovfl);
7487
`undef MODULE
7488 18 unneback
parameter width = 32;
7489
parameter opcode_add = 1'b0;
7490
parameter opcode_sub = 1'b1;
7491
input [width-1:0] a,b;
7492
input c_in, add_sub, sign;
7493
output [width-1:0] result;
7494
output c_out, z, ovfl;
7495
 
7496
assign {c_out,result} = {(a[width-1] & sign),a} + ({a[width-1] & sign,b} ^ {(width+1){(add_sub==opcode_sub)}}) + {{(width-1){1'b0}},(c_in | (add_sub==opcode_sub))};
7497
assign z = (result=={width{1'b0}});
7498
assign ovfl = ( a[width-1] &  b[width-1] & ~result[width-1]) |
7499
               (~a[width-1] & ~b[width-1] &  result[width-1]);
7500
endmodule
7501 40 unneback
`endif
7502 48 unneback
 
7503
`ifdef COUNT_UNIT
7504
`define MODULE count_unit
7505
module `BASE`MODULE (din, dout, opcode);
7506
`undef MODULE
7507
parameter width = 32;
7508
input [width-1:0] din;
7509
output [width-1:0] dout;
7510
input opcode;
7511
 
7512
integer i;
7513 58 unneback
wire [width/32+4:0] ff1, fl1;
7514 48 unneback
 
7515 57 unneback
/*
7516 48 unneback
always @(din) begin
7517
    ff1 = 0; i = 0;
7518
    while (din[i] == 0 && i < width) begin // complex condition
7519
        ff1 = ff1 + 1;
7520
        i = i + 1;
7521
    end
7522
end
7523
 
7524
always @(din) begin
7525
    fl1 = width; i = width-1;
7526
    while (din[i] == 0 && i >= width) begin // complex condition
7527
        fl1 = fl1 - 1;
7528
        i = i - 1;
7529
    end
7530
end
7531 57 unneback
*/
7532 48 unneback
 
7533
generate
7534
if (width==32) begin
7535 57 unneback
 
7536
    assign ff1 = din[0] ? 6'd1 :
7537
                 din[1] ? 6'd2 :
7538
                 din[2] ? 6'd3 :
7539
                 din[3] ? 6'd4 :
7540
                 din[4] ? 6'd5 :
7541
                 din[5] ? 6'd6 :
7542
                 din[6] ? 6'd7 :
7543
                 din[7] ? 6'd8 :
7544
                 din[8] ? 6'd9 :
7545
                 din[9] ? 6'd10 :
7546
                 din[10] ? 6'd11 :
7547
                 din[11] ? 6'd12 :
7548
                 din[12] ? 6'd13 :
7549
                 din[13] ? 6'd14 :
7550
                 din[14] ? 6'd15 :
7551
                 din[15] ? 6'd16 :
7552
                 din[16] ? 6'd17 :
7553
                 din[17] ? 6'd18 :
7554
                 din[18] ? 6'd19 :
7555
                 din[19] ? 6'd20 :
7556
                 din[20] ? 6'd21 :
7557
                 din[21] ? 6'd22 :
7558
                 din[22] ? 6'd23 :
7559
                 din[23] ? 6'd24 :
7560
                 din[24] ? 6'd25 :
7561
                 din[25] ? 6'd26 :
7562
                 din[26] ? 6'd27 :
7563
                 din[27] ? 6'd28 :
7564
                 din[28] ? 6'd29 :
7565
                 din[29] ? 6'd30 :
7566
                 din[30] ? 6'd31 :
7567
                 din[31] ? 6'd32 :
7568
                 6'd0;
7569
 
7570
    assign fl1 = din[31] ? 6'd32 :
7571
                 din[30] ? 6'd31 :
7572
                 din[29] ? 6'd30 :
7573
                 din[28] ? 6'd29 :
7574
                 din[27] ? 6'd28 :
7575
                 din[26] ? 6'd27 :
7576
                 din[25] ? 6'd26 :
7577
                 din[24] ? 6'd25 :
7578
                 din[23] ? 6'd24 :
7579
                 din[22] ? 6'd23 :
7580
                 din[21] ? 6'd22 :
7581
                 din[20] ? 6'd21 :
7582
                 din[19] ? 6'd20 :
7583
                 din[18] ? 6'd19 :
7584
                 din[17] ? 6'd18 :
7585
                 din[16] ? 6'd17 :
7586
                 din[15] ? 6'd16 :
7587
                 din[14] ? 6'd15 :
7588
                 din[13] ? 6'd14 :
7589
                 din[12] ? 6'd13 :
7590
                 din[11] ? 6'd12 :
7591
                 din[10] ? 6'd11 :
7592
                 din[9] ? 6'd10 :
7593
                 din[8] ? 6'd9 :
7594
                 din[7] ? 6'd8 :
7595
                 din[6] ? 6'd7 :
7596
                 din[5] ? 6'd6 :
7597
                 din[4] ? 6'd5 :
7598
                 din[3] ? 6'd4 :
7599
                 din[2] ? 6'd3 :
7600
                 din[1] ? 6'd2 :
7601
                 din[0] ? 6'd1 :
7602
                 6'd0;
7603
 
7604
    assign dout = (!opcode) ? {{26{1'b0}}, ff1} : {{26{1'b0}}, fl1};
7605 48 unneback
end
7606
endgenerate
7607 57 unneback
 
7608 48 unneback
generate
7609
if (width==64) begin
7610 57 unneback
    assign ff1 = 7'd0;
7611
    assign fl1 = 7'd0;
7612
    assign dout = (!opcode) ? {{57{1'b0}}, ff1} : {{57{1'b0}}, fl1};
7613 48 unneback
end
7614
endgenerate
7615
 
7616
endmodule
7617
`endif
7618
 
7619
`ifdef EXT_UNIT
7620
`define MODULE ext_unit
7621
module `BASE`MODULE ( a, b, F, result, opcode);
7622
`undef MODULE
7623
parameter width = 32;
7624
input [width-1:0] a, b;
7625
input F;
7626
output reg [width-1:0] result;
7627
input [2:0] opcode;
7628
 
7629
generate
7630
if (width==32) begin
7631
always @ (a or b or F or opcode)
7632
begin
7633
    case (opcode)
7634
    3'b000: result = {{24{1'b0}},a[7:0]};
7635
    3'b001: result = {{24{a[7]}},a[7:0]};
7636
    3'b010: result = {{16{1'b0}},a[7:0]};
7637
    3'b011: result = {{16{a[15]}},a[15:0]};
7638
    3'b110: result = (F) ? a : b;
7639
    default: result = {b[15:0],16'h0000};
7640
    endcase
7641
end
7642
end
7643
endgenerate
7644
 
7645
generate
7646
if (width==64) begin
7647
always @ (a or b or F or opcode)
7648
begin
7649
    case (opcode)
7650
    3'b000: result = {{56{1'b0}},a[7:0]};
7651
    3'b001: result = {{56{a[7]}},a[7:0]};
7652
    3'b010: result = {{48{1'b0}},a[7:0]};
7653
    3'b011: result = {{48{a[15]}},a[15:0]};
7654 57 unneback
    3'b110: result = (F) ? a : b;
7655 48 unneback
    default: result = {32'h00000000,b[15:0],16'h0000};
7656
    endcase
7657
end
7658
end
7659
endgenerate
7660
endmodule
7661
`endif

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