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1 6 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  Versatile library, clock and reset                          ////
4
////                                                              ////
5
////  Description                                                 ////
6
////  Logic related to clock and reset                            ////
7
////                                                              ////
8
////                                                              ////
9
////  To Do:                                                      ////
10
////   - add more different registers                             ////
11
////                                                              ////
12
////  Author(s):                                                  ////
13
////      - Michael Unneback, unneback@opencores.org              ////
14
////        ORSoC AB                                              ////
15
////                                                              ////
16
//////////////////////////////////////////////////////////////////////
17
////                                                              ////
18
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
19
////                                                              ////
20
//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
36
////                                                              ////
37
//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
 
43
// Global buffer
44
// usage:
45
// use to enable global buffers for high fan out signals such as clock and reset
46
 
47
`ifdef ACTEL
48
 
49
`timescale 1 ns/100 ps
50
// Version: 8.4 8.4.0.33
51
module gbuf(GL,CLK);
52
output GL;
53
input  CLK;
54
 
55
    wire GND;
56
 
57
    GND GND_1_net(.Y(GND));
58
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
59
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
60
 
61
endmodule
62
`timescale 1 ns/1 ns
63
module vl_gbuf ( i, o);
64
input i;
65
output o;
66
`ifdef SIM_GBUF
67
assign o=i;
68
`else
69
gbuf gbuf_i0 ( .CLK(i), .GL(o));
70
`endif
71
endmodule
72
`else
73
`ifdef ALTERA
74
altera
75
`else
76
 
77
`timescale 1 ns/100 ps
78
module vl_gbuf ( i, o);
79
input i;
80
output o;
81
assign o = i;
82
endmodule
83
`endif // ALTERA
84
`endif //ACTEL
85
 
86
// sync reset
87
// input active lo async reset, normally from external reset generetaor and/or switch
88
// output active high global reset sync with two DFFs 
89
`timescale 1 ns/100 ps
90
module vl_sync_rst ( rst_n_i, rst_o, clk);
91
input rst_n_i, clk;
92
output rst_o;
93
reg [0:1] tmp;
94
always @ (posedge clk or negedge rst_n_i)
95
if (!rst_n_i)
96
        tmp <= 2'b00;
97
else
98
        tmp <= {1'b1,tmp[0]};
99
vl_gbuf buf_i0( .i(tmp[1]), .o(rst_o));
100
endmodule
101
 
102
// vl_pll
103
`ifdef ACTEL
104
`timescale 1 ns/100 ps
105
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
106
parameter index = 0;
107
parameter number_of_clk = 1;
108
parameter period_time_0 = 20;
109
parameter period_time_1 = 20;
110
parameter period_time_2 = 20;
111
parameter lock_delay = 2000;
112
input clk_i, rst_n_i;
113
output lock;
114
output reg [0:number_of_clk-1] clk_o;
115
output [0:number_of_clk-1] rst_o;
116
 
117
`ifdef SIM_PLL
118
 
119
always
120
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
121
 
122
generate if (number_of_clk > 1)
123
always
124
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
125
endgenerate
126
 
127
generate if (number_of_clk > 2)
128
always
129
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
130
endgenerate
131
 
132
genvar i;
133
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
134
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
135
end
136
endgenerate
137
 
138
assign #lock_delay lock = rst_n_i;
139
 
140
endmodule
141
`else
142
generate if (number_of_clk==1 & index==0) begin
143
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
144
end
145
endgenerate // index==0
146
generate if (number_of_clk==1 & index==1) begin
147
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
148
end
149
endgenerate // index==1
150
generate if (number_of_clk==1 & index==2) begin
151
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
152
end
153
endgenerate // index==2
154
generate if (number_of_clk==1 & index==3) begin
155
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
156
end
157
endgenerate // index==0
158
 
159
generate if (number_of_clk==2 & index==0) begin
160
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
161
end
162
endgenerate // index==0
163
generate if (number_of_clk==2 & index==1) begin
164
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
165
end
166
endgenerate // index==1
167
generate if (number_of_clk==2 & index==2) begin
168
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
169
end
170
endgenerate // index==2
171
generate if (number_of_clk==2 & index==3) begin
172
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
173
end
174
endgenerate // index==0
175
 
176
generate if (number_of_clk==3 & index==0) begin
177
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
178
end
179
endgenerate // index==0
180
generate if (number_of_clk==3 & index==1) begin
181
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
182
end
183
endgenerate // index==1
184
generate if (number_of_clk==3 & index==2) begin
185
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
186
end
187
endgenerate // index==2
188
generate if (number_of_clk==3 & index==3) begin
189
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
190
end
191
endgenerate // index==0
192
 
193
genvar i;
194
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
195
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
196
end
197
endgenerate
198
endmodule
199
`endif
200
 
201
`else
202
 
203
`ifdef ALTERA
204
 
205
`else
206
 
207
// generic PLL
208
`timescale 1 ns/100 ps
209
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
210
parameter index = 0;
211
parameter number_of_clk = 1;
212
parameter period_time_0 = 20;
213
parameter period_time_1 = 20;
214
parameter period_time_2 = 20;
215
parameter lock_delay = 2000;
216
input clk_i, rst_n_i;
217
output lock;
218
output reg [0:number_of_clk-1] clk_o;
219
output [0:number_of_clk-1] rst_o;
220
 
221
always
222
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
223
 
224
generate if (number_of_clk > 1)
225
always
226
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
227
endgenerate
228
 
229
generate if (number_of_clk > 2)
230
always
231
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
232
endgenerate
233
 
234
genvar i;
235
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
236
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
237
end
238
endgenerate
239
 
240
assign #lock_delay lock = rst_n_i;
241
 
242
endmodule
243
 
244
`endif //altera
245
`endif //actel//////////////////////////////////////////////////////////////////////
246
////                                                              ////
247
////  Versatile library, registers                                ////
248
////                                                              ////
249
////  Description                                                 ////
250
////  Different type of registers                                 ////
251
////                                                              ////
252
////                                                              ////
253
////  To Do:                                                      ////
254
////   - add more different registers                             ////
255
////                                                              ////
256
////  Author(s):                                                  ////
257
////      - Michael Unneback, unneback@opencores.org              ////
258
////        ORSoC AB                                              ////
259
////                                                              ////
260
//////////////////////////////////////////////////////////////////////
261
////                                                              ////
262
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
263
////                                                              ////
264
//// This source file may be used and distributed without         ////
265
//// restriction provided that this copyright statement is not    ////
266
//// removed from the file and that any derivative work contains  ////
267
//// the original copyright notice and the associated disclaimer. ////
268
////                                                              ////
269
//// This source file is free software; you can redistribute it   ////
270
//// and/or modify it under the terms of the GNU Lesser General   ////
271
//// Public License as published by the Free Software Foundation; ////
272
//// either version 2.1 of the License, or (at your option) any   ////
273
//// later version.                                               ////
274
////                                                              ////
275
//// This source is distributed in the hope that it will be       ////
276
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
277
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
278
//// PURPOSE.  See the GNU Lesser General Public License for more ////
279
//// details.                                                     ////
280
////                                                              ////
281
//// You should have received a copy of the GNU Lesser General    ////
282
//// Public License along with this source; if not, download it   ////
283
//// from http://www.opencores.org/lgpl.shtml                     ////
284
////                                                              ////
285
//////////////////////////////////////////////////////////////////////
286
 
287
module dff ( d, q, clk, rst);
288
 
289
        parameter width = 1;
290
        parameter reset_value = 0;
291
 
292
        input [width-1:0] d;
293
        input clk, rst;
294
        output reg [width-1:0] q;
295
 
296
        always @ (posedge clk or posedge rst)
297
        if (rst)
298
                q <= reset_value;
299
        else
300
                q <= d;
301
 
302
endmodule
303
 
304
module dff_array ( d, q, clk, rst);
305
 
306
        parameter width = 1;
307
        parameter depth = 2;
308
        parameter reset_value = 1'b0;
309
 
310
        input [width-1:0] d;
311
        input clk, rst;
312
        output [width-1:0] q;
313
        reg  [0:depth-1] q_tmp [width-1:0];
314
        integer i;
315
        always @ (posedge clk or posedge rst)
316
        if (rst) begin
317
            for (i=0;i<depth;i=i+1)
318
                q_tmp[i] <= {width{reset_value}};
319
        end else begin
320
            q_tmp[0] <= d;
321
            for (i=1;i<depth;i=i+1)
322
                q_tmp[i] <= q_tmp[i-1];
323
        end
324
 
325
    assign q = q_tmp[depth-1];
326
 
327
endmodule
328
 
329
module dff_ce ( d, ce, q, clk, rst);
330
 
331
        parameter width = 1;
332
        parameter reset_value = 0;
333
 
334
        input [width-1:0] d;
335
        input ce, clk, rst;
336
        output reg [width-1:0] q;
337
 
338
        always @ (posedge clk or posedge rst)
339
        if (rst)
340
                q <= reset_value;
341
        else
342
                if (ce)
343
                        q <= d;
344
 
345
endmodule
346
 
347 8 unneback
module dff_ce_clear ( d, ce, clear, q, clk, rst);
348
 
349
        parameter width = 1;
350
        parameter reset_value = 0;
351
 
352
        input [width-1:0] d;
353 10 unneback
        input ce, clear, clk, rst;
354 8 unneback
        output reg [width-1:0] q;
355
 
356
        always @ (posedge clk or posedge rst)
357
        if (rst)
358
            q <= reset_value;
359
        else
360
            if (ce)
361
                if (clear)
362
                    q <= {width{1'b0}};
363
                else
364
                    q <= d;
365
 
366
endmodule
367
 
368 6 unneback
`ifdef ALTERA
369
// megafunction wizard: %LPM_FF%
370
// GENERATION: STANDARD
371
// VERSION: WM1.0
372
// MODULE: lpm_ff 
373
 
374
// ============================================================
375
// File Name: dff_sr.v
376
// Megafunction Name(s):
377
//                      lpm_ff
378
//
379
// Simulation Library Files(s):
380
//                      lpm
381
// ============================================================
382
// ************************************************************
383
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
384
//
385
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
386
// ************************************************************
387
 
388
 
389
//Copyright (C) 1991-2010 Altera Corporation
390
//Your use of Altera Corporation's design tools, logic functions 
391
//and other software and tools, and its AMPP partner logic 
392
//functions, and any output files from any of the foregoing 
393
//(including device programming or simulation files), and any 
394
//associated documentation or information are expressly subject 
395
//to the terms and conditions of the Altera Program License 
396
//Subscription Agreement, Altera MegaCore Function License 
397
//Agreement, or other applicable license agreement, including, 
398
//without limitation, that your use is for the sole purpose of 
399
//programming logic devices manufactured by Altera and sold by 
400
//Altera or its authorized distributors.  Please refer to the 
401
//applicable agreement for further details.
402
 
403
 
404
// synopsys translate_off
405
`timescale 1 ps / 1 ps
406
// synopsys translate_on
407
module dff_sr (
408
        aclr,
409
        aset,
410
        clock,
411
        data,
412
        q);
413
 
414
        input     aclr;
415
        input     aset;
416
        input     clock;
417
        input     data;
418
        output    q;
419
 
420
        wire [0:0] sub_wire0;
421
        wire [0:0] sub_wire1 = sub_wire0[0:0];
422
        wire  q = sub_wire1;
423
        wire  sub_wire2 = data;
424
        wire  sub_wire3 = sub_wire2;
425
 
426
        lpm_ff  lpm_ff_component (
427
                                .aclr (aclr),
428
                                .clock (clock),
429
                                .data (sub_wire3),
430
                                .aset (aset),
431
                                .q (sub_wire0)
432
                                // synopsys translate_off
433
                                ,
434
                                .aload (),
435
                                .enable (),
436
                                .sclr (),
437
                                .sload (),
438
                                .sset ()
439
                                // synopsys translate_on
440
                                );
441
        defparam
442
                lpm_ff_component.lpm_fftype = "DFF",
443
                lpm_ff_component.lpm_type = "LPM_FF",
444
                lpm_ff_component.lpm_width = 1;
445
 
446
 
447
endmodule
448
 
449
// ============================================================
450
// CNX file retrieval info
451
// ============================================================
452
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
453
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
454
// Retrieval info: PRIVATE: ASET NUMERIC "1"
455
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
456
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
457
// Retrieval info: PRIVATE: DFF NUMERIC "1"
458
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
459
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
460
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
461
// Retrieval info: PRIVATE: SSET NUMERIC "0"
462
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
463
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
464
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
465
// Retrieval info: PRIVATE: nBit NUMERIC "1"
466
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
467
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
468
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
469
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
470
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
471
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
472
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
473
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
474
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
475
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
476
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
477
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
478
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
479
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
480
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
481
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
482
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
483
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
484
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
485
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
486
// Retrieval info: LIB_FILE: lpm
487
 
488
 
489
`else
490
 
491
 
492
module dff_sr ( aclr, aset, clock, data, q);
493
 
494
    input         aclr;
495
    input         aset;
496
    input         clock;
497
    input         data;
498
    output reg    q;
499
 
500
   always @ (posedge clock or posedge aclr or posedge aset)
501
     if (aclr)
502
       q <= 1'b0;
503
     else if (aset)
504
       q <= 1'b1;
505
     else
506
       q <= data;
507
 
508
endmodule
509
 
510
`endif
511
 
512
// LATCH
513
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
514
`ifdef ALTERA
515
module latch ( d, le, q, clk);
516
input d, le;
517
output q;
518
input clk;
519
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
520
endmodule
521
`else
522
module latch ( d, le, q, clk);
523
input d, le;
524
output q;
525
input clk;/*
526
   always @ (posedge direction_set or posedge direction_clr)
527
     if (direction_clr)
528
       direction <= going_empty;
529
     else
530
       direction <= going_full;*/
531
endmodule
532 15 unneback
`endif
533
 
534
module delay ( d, q, clk, rst);
535
parameter depth = 10;
536
input d;
537
output q;
538
input clk, rst;
539
 
540
reg [1:depth] dffs;
541
 
542
always @ (posedge clk or posedge rst)
543
if (rst)
544
    dffs <= {depth{1'b0}};
545
else
546
    dffs <= {d,dffs[1:depth-1]};
547
assign q = dffs[depth];
548
endmodule//////////////////////////////////////////////////////////////////////
549 6 unneback
////                                                              ////
550
////  Versatile counter                                           ////
551
////                                                              ////
552
////  Description                                                 ////
553
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
554
////  counter                                                     ////
555
////                                                              ////
556
////  To Do:                                                      ////
557
////   - add LFSR with more taps                                  ////
558
////                                                              ////
559
////  Author(s):                                                  ////
560
////      - Michael Unneback, unneback@opencores.org              ////
561
////        ORSoC AB                                              ////
562
////                                                              ////
563
//////////////////////////////////////////////////////////////////////
564
////                                                              ////
565
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
566
////                                                              ////
567
//// This source file may be used and distributed without         ////
568
//// restriction provided that this copyright statement is not    ////
569
//// removed from the file and that any derivative work contains  ////
570
//// the original copyright notice and the associated disclaimer. ////
571
////                                                              ////
572
//// This source file is free software; you can redistribute it   ////
573
//// and/or modify it under the terms of the GNU Lesser General   ////
574
//// Public License as published by the Free Software Foundation; ////
575
//// either version 2.1 of the License, or (at your option) any   ////
576
//// later version.                                               ////
577
////                                                              ////
578
//// This source is distributed in the hope that it will be       ////
579
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
580
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
581
//// PURPOSE.  See the GNU Lesser General Public License for more ////
582
//// details.                                                     ////
583
////                                                              ////
584
//// You should have received a copy of the GNU Lesser General    ////
585
//// Public License along with this source; if not, download it   ////
586
//// from http://www.opencores.org/lgpl.shtml                     ////
587
////                                                              ////
588
//////////////////////////////////////////////////////////////////////
589
 
590
// binary counter
591
module cnt_bin_ce ( cke, q, rst, clk);
592
 
593
   parameter length = 4;
594
   input cke;
595
   output [length:1] q;
596
   input rst;
597
   input clk;
598
 
599
   parameter clear_value = 0;
600
   parameter set_value = 1;
601
   parameter wrap_value = 0;
602
   parameter level1_value = 15;
603
 
604
   reg  [length:1] qi;
605
   wire [length:1] q_next;
606
   assign q_next = qi + {{length-1{1'b0}},1'b1};
607
 
608
   always @ (posedge clk or posedge rst)
609
     if (rst)
610
       qi <= {length{1'b0}};
611
     else
612
     if (cke)
613
       qi <= q_next;
614
 
615
   assign q = qi;
616
 
617
endmodule
618
//////////////////////////////////////////////////////////////////////
619
////                                                              ////
620
////  Versatile counter                                           ////
621
////                                                              ////
622
////  Description                                                 ////
623
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
624
////  counter                                                     ////
625
////                                                              ////
626
////  To Do:                                                      ////
627
////   - add LFSR with more taps                                  ////
628
////                                                              ////
629
////  Author(s):                                                  ////
630
////      - Michael Unneback, unneback@opencores.org              ////
631
////        ORSoC AB                                              ////
632
////                                                              ////
633
//////////////////////////////////////////////////////////////////////
634
////                                                              ////
635
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
636
////                                                              ////
637
//// This source file may be used and distributed without         ////
638
//// restriction provided that this copyright statement is not    ////
639
//// removed from the file and that any derivative work contains  ////
640
//// the original copyright notice and the associated disclaimer. ////
641
////                                                              ////
642
//// This source file is free software; you can redistribute it   ////
643
//// and/or modify it under the terms of the GNU Lesser General   ////
644
//// Public License as published by the Free Software Foundation; ////
645
//// either version 2.1 of the License, or (at your option) any   ////
646
//// later version.                                               ////
647
////                                                              ////
648
//// This source is distributed in the hope that it will be       ////
649
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
650
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
651
//// PURPOSE.  See the GNU Lesser General Public License for more ////
652
//// details.                                                     ////
653
////                                                              ////
654
//// You should have received a copy of the GNU Lesser General    ////
655
//// Public License along with this source; if not, download it   ////
656
//// from http://www.opencores.org/lgpl.shtml                     ////
657
////                                                              ////
658
//////////////////////////////////////////////////////////////////////
659
 
660
// binary counter
661
module cnt_bin_ce_clear ( clear, cke, q, rst, clk);
662
 
663
   parameter length = 4;
664
   input clear;
665
   input cke;
666
   output [length:1] q;
667
   input rst;
668
   input clk;
669
 
670
   parameter clear_value = 0;
671
   parameter set_value = 1;
672
   parameter wrap_value = 0;
673
   parameter level1_value = 15;
674
 
675
   reg  [length:1] qi;
676
   wire [length:1] q_next;
677
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
678
 
679
   always @ (posedge clk or posedge rst)
680
     if (rst)
681
       qi <= {length{1'b0}};
682
     else
683
     if (cke)
684
       qi <= q_next;
685
 
686
   assign q = qi;
687
 
688
endmodule
689
//////////////////////////////////////////////////////////////////////
690
////                                                              ////
691
////  Versatile counter                                           ////
692
////                                                              ////
693
////  Description                                                 ////
694
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
695
////  counter                                                     ////
696
////                                                              ////
697
////  To Do:                                                      ////
698
////   - add LFSR with more taps                                  ////
699
////                                                              ////
700
////  Author(s):                                                  ////
701
////      - Michael Unneback, unneback@opencores.org              ////
702
////        ORSoC AB                                              ////
703
////                                                              ////
704
//////////////////////////////////////////////////////////////////////
705
////                                                              ////
706
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
707
////                                                              ////
708
//// This source file may be used and distributed without         ////
709
//// restriction provided that this copyright statement is not    ////
710
//// removed from the file and that any derivative work contains  ////
711
//// the original copyright notice and the associated disclaimer. ////
712
////                                                              ////
713
//// This source file is free software; you can redistribute it   ////
714
//// and/or modify it under the terms of the GNU Lesser General   ////
715
//// Public License as published by the Free Software Foundation; ////
716
//// either version 2.1 of the License, or (at your option) any   ////
717
//// later version.                                               ////
718
////                                                              ////
719
//// This source is distributed in the hope that it will be       ////
720
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
721
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
722
//// PURPOSE.  See the GNU Lesser General Public License for more ////
723
//// details.                                                     ////
724
////                                                              ////
725
//// You should have received a copy of the GNU Lesser General    ////
726
//// Public License along with this source; if not, download it   ////
727
//// from http://www.opencores.org/lgpl.shtml                     ////
728
////                                                              ////
729
//////////////////////////////////////////////////////////////////////
730
 
731
// binary counter
732
module cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk);
733
 
734
   parameter length = 4;
735
   input clear;
736
   input set;
737
   input cke;
738
   input rew;
739
   output [length:1] q;
740
   input rst;
741
   input clk;
742
 
743
   parameter clear_value = 0;
744
   parameter set_value = 1;
745
   parameter wrap_value = 0;
746
   parameter level1_value = 15;
747
 
748
   reg  [length:1] qi;
749
   wire  [length:1] q_next, q_next_fw, q_next_rew;
750
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
751
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
752
   assign q_next = rew ? q_next_rew : q_next_fw;
753
 
754
   always @ (posedge clk or posedge rst)
755
     if (rst)
756
       qi <= {length{1'b0}};
757
     else
758
     if (cke)
759
       qi <= q_next;
760
 
761
   assign q = qi;
762
 
763
endmodule
764
//////////////////////////////////////////////////////////////////////
765
////                                                              ////
766
////  Versatile counter                                           ////
767
////                                                              ////
768
////  Description                                                 ////
769
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
770
////  counter                                                     ////
771
////                                                              ////
772
////  To Do:                                                      ////
773
////   - add LFSR with more taps                                  ////
774
////                                                              ////
775
////  Author(s):                                                  ////
776
////      - Michael Unneback, unneback@opencores.org              ////
777
////        ORSoC AB                                              ////
778
////                                                              ////
779
//////////////////////////////////////////////////////////////////////
780
////                                                              ////
781
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
782
////                                                              ////
783
//// This source file may be used and distributed without         ////
784
//// restriction provided that this copyright statement is not    ////
785
//// removed from the file and that any derivative work contains  ////
786
//// the original copyright notice and the associated disclaimer. ////
787
////                                                              ////
788
//// This source file is free software; you can redistribute it   ////
789
//// and/or modify it under the terms of the GNU Lesser General   ////
790
//// Public License as published by the Free Software Foundation; ////
791
//// either version 2.1 of the License, or (at your option) any   ////
792
//// later version.                                               ////
793
////                                                              ////
794
//// This source is distributed in the hope that it will be       ////
795
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
796
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
797
//// PURPOSE.  See the GNU Lesser General Public License for more ////
798
//// details.                                                     ////
799
////                                                              ////
800
//// You should have received a copy of the GNU Lesser General    ////
801
//// Public License along with this source; if not, download it   ////
802
//// from http://www.opencores.org/lgpl.shtml                     ////
803
////                                                              ////
804
//////////////////////////////////////////////////////////////////////
805
 
806
// binary counter
807
module cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk);
808
 
809
   parameter length = 4;
810
   input cke;
811
   input rew;
812
   output reg level1;
813
   input rst;
814
   input clk;
815
 
816
   parameter clear_value = 0;
817
   parameter set_value = 1;
818
   parameter wrap_value = 1;
819
   parameter level1_value = 15;
820
 
821
   reg  [length:1] qi;
822
   wire  [length:1] q_next, q_next_fw, q_next_rew;
823
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
824
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
825
   assign q_next = rew ? q_next_rew : q_next_fw;
826
 
827
   always @ (posedge clk or posedge rst)
828
     if (rst)
829
       qi <= {length{1'b0}};
830
     else
831
     if (cke)
832
       qi <= q_next;
833
 
834
 
835
 
836
    always @ (posedge clk or posedge rst)
837
    if (rst)
838
        level1 <= 1'b0;
839
    else
840
    if (cke)
841
    if (q_next == level1_value)
842
        level1 <= 1'b1;
843
    else if (qi == level1_value & rew)
844
        level1 <= 1'b0;
845
endmodule
846
//////////////////////////////////////////////////////////////////////
847
////                                                              ////
848
////  Versatile counter                                           ////
849
////                                                              ////
850
////  Description                                                 ////
851
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
852
////  counter                                                     ////
853
////                                                              ////
854
////  To Do:                                                      ////
855
////   - add LFSR with more taps                                  ////
856
////                                                              ////
857
////  Author(s):                                                  ////
858
////      - Michael Unneback, unneback@opencores.org              ////
859
////        ORSoC AB                                              ////
860
////                                                              ////
861
//////////////////////////////////////////////////////////////////////
862
////                                                              ////
863
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
864
////                                                              ////
865
//// This source file may be used and distributed without         ////
866
//// restriction provided that this copyright statement is not    ////
867
//// removed from the file and that any derivative work contains  ////
868
//// the original copyright notice and the associated disclaimer. ////
869
////                                                              ////
870
//// This source file is free software; you can redistribute it   ////
871
//// and/or modify it under the terms of the GNU Lesser General   ////
872
//// Public License as published by the Free Software Foundation; ////
873
//// either version 2.1 of the License, or (at your option) any   ////
874
//// later version.                                               ////
875
////                                                              ////
876
//// This source is distributed in the hope that it will be       ////
877
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
878
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
879
//// PURPOSE.  See the GNU Lesser General Public License for more ////
880
//// details.                                                     ////
881
////                                                              ////
882
//// You should have received a copy of the GNU Lesser General    ////
883
//// Public License along with this source; if not, download it   ////
884
//// from http://www.opencores.org/lgpl.shtml                     ////
885
////                                                              ////
886
//////////////////////////////////////////////////////////////////////
887
 
888
// LFSR counter
889
module cnt_lfsr_zq ( zq, rst, clk);
890
 
891
   parameter length = 4;
892
   output reg zq;
893
   input rst;
894
   input clk;
895
 
896
   parameter clear_value = 0;
897
   parameter set_value = 1;
898
   parameter wrap_value = 8;
899
   parameter level1_value = 15;
900
 
901
   reg  [length:1] qi;
902
   reg lfsr_fb;
903
   wire [length:1] q_next;
904
   reg [32:1] polynom;
905
   integer i;
906
 
907
   always @ (qi)
908
   begin
909
        case (length)
910
         2: polynom = 32'b11;                               // 0x3
911
         3: polynom = 32'b110;                              // 0x6
912
         4: polynom = 32'b1100;                             // 0xC
913
         5: polynom = 32'b10100;                            // 0x14
914
         6: polynom = 32'b110000;                           // 0x30
915
         7: polynom = 32'b1100000;                          // 0x60
916
         8: polynom = 32'b10111000;                         // 0xb8
917
         9: polynom = 32'b100010000;                        // 0x110
918
        10: polynom = 32'b1001000000;                       // 0x240
919
        11: polynom = 32'b10100000000;                      // 0x500
920
        12: polynom = 32'b100000101001;                     // 0x829
921
        13: polynom = 32'b1000000001100;                    // 0x100C
922
        14: polynom = 32'b10000000010101;                   // 0x2015
923
        15: polynom = 32'b110000000000000;                  // 0x6000
924
        16: polynom = 32'b1101000000001000;                 // 0xD008
925
        17: polynom = 32'b10010000000000000;                // 0x12000
926
        18: polynom = 32'b100000010000000000;               // 0x20400
927
        19: polynom = 32'b1000000000000100011;              // 0x40023
928
        20: polynom = 32'b10000010000000000000;             // 0x82000
929
        21: polynom = 32'b101000000000000000000;            // 0x140000
930
        22: polynom = 32'b1100000000000000000000;           // 0x300000
931
        23: polynom = 32'b10000100000000000000000;          // 0x420000
932
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
933
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
934
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
935
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
936
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
937
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
938
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
939
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
940
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
941
        default: polynom = 32'b0;
942
        endcase
943
        lfsr_fb = qi[length];
944
        for (i=length-1; i>=1; i=i-1) begin
945
            if (polynom[i])
946
                lfsr_fb = lfsr_fb  ~^ qi[i];
947
        end
948
    end
949
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
950
 
951
   always @ (posedge clk or posedge rst)
952
     if (rst)
953
       qi <= {length{1'b0}};
954
     else
955
       qi <= q_next;
956
 
957
 
958
 
959
   always @ (posedge clk or posedge rst)
960
     if (rst)
961
       zq <= 1'b1;
962
     else
963
       zq <= q_next == {length{1'b0}};
964
endmodule
965
//////////////////////////////////////////////////////////////////////
966
////                                                              ////
967
////  Versatile counter                                           ////
968
////                                                              ////
969
////  Description                                                 ////
970
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
971
////  counter                                                     ////
972
////                                                              ////
973
////  To Do:                                                      ////
974
////   - add LFSR with more taps                                  ////
975
////                                                              ////
976
////  Author(s):                                                  ////
977
////      - Michael Unneback, unneback@opencores.org              ////
978
////        ORSoC AB                                              ////
979
////                                                              ////
980
//////////////////////////////////////////////////////////////////////
981
////                                                              ////
982
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
983
////                                                              ////
984
//// This source file may be used and distributed without         ////
985
//// restriction provided that this copyright statement is not    ////
986
//// removed from the file and that any derivative work contains  ////
987
//// the original copyright notice and the associated disclaimer. ////
988
////                                                              ////
989
//// This source file is free software; you can redistribute it   ////
990
//// and/or modify it under the terms of the GNU Lesser General   ////
991
//// Public License as published by the Free Software Foundation; ////
992
//// either version 2.1 of the License, or (at your option) any   ////
993
//// later version.                                               ////
994
////                                                              ////
995
//// This source is distributed in the hope that it will be       ////
996
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
997
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
998
//// PURPOSE.  See the GNU Lesser General Public License for more ////
999
//// details.                                                     ////
1000
////                                                              ////
1001
//// You should have received a copy of the GNU Lesser General    ////
1002
//// Public License along with this source; if not, download it   ////
1003
//// from http://www.opencores.org/lgpl.shtml                     ////
1004
////                                                              ////
1005
//////////////////////////////////////////////////////////////////////
1006
 
1007
// LFSR counter
1008
module cnt_lfsr_ce_zq ( cke, zq, rst, clk);
1009
 
1010
   parameter length = 4;
1011
   input cke;
1012
   output reg zq;
1013
   input rst;
1014
   input clk;
1015
 
1016
   parameter clear_value = 0;
1017
   parameter set_value = 1;
1018
   parameter wrap_value = 8;
1019
   parameter level1_value = 15;
1020
 
1021
   reg  [length:1] qi;
1022
   reg lfsr_fb;
1023
   wire [length:1] q_next;
1024
   reg [32:1] polynom;
1025
   integer i;
1026
 
1027
   always @ (qi)
1028
   begin
1029
        case (length)
1030
         2: polynom = 32'b11;                               // 0x3
1031
         3: polynom = 32'b110;                              // 0x6
1032
         4: polynom = 32'b1100;                             // 0xC
1033
         5: polynom = 32'b10100;                            // 0x14
1034
         6: polynom = 32'b110000;                           // 0x30
1035
         7: polynom = 32'b1100000;                          // 0x60
1036
         8: polynom = 32'b10111000;                         // 0xb8
1037
         9: polynom = 32'b100010000;                        // 0x110
1038
        10: polynom = 32'b1001000000;                       // 0x240
1039
        11: polynom = 32'b10100000000;                      // 0x500
1040
        12: polynom = 32'b100000101001;                     // 0x829
1041
        13: polynom = 32'b1000000001100;                    // 0x100C
1042
        14: polynom = 32'b10000000010101;                   // 0x2015
1043
        15: polynom = 32'b110000000000000;                  // 0x6000
1044
        16: polynom = 32'b1101000000001000;                 // 0xD008
1045
        17: polynom = 32'b10010000000000000;                // 0x12000
1046
        18: polynom = 32'b100000010000000000;               // 0x20400
1047
        19: polynom = 32'b1000000000000100011;              // 0x40023
1048
        20: polynom = 32'b10000010000000000000;             // 0x82000
1049
        21: polynom = 32'b101000000000000000000;            // 0x140000
1050
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1051
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1052
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1053
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1054
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1055
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1056
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1057
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1058
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1059
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1060
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1061
        default: polynom = 32'b0;
1062
        endcase
1063
        lfsr_fb = qi[length];
1064
        for (i=length-1; i>=1; i=i-1) begin
1065
            if (polynom[i])
1066
                lfsr_fb = lfsr_fb  ~^ qi[i];
1067
        end
1068
    end
1069
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1070
 
1071
   always @ (posedge clk or posedge rst)
1072
     if (rst)
1073
       qi <= {length{1'b0}};
1074
     else
1075
     if (cke)
1076
       qi <= q_next;
1077
 
1078
 
1079
 
1080
   always @ (posedge clk or posedge rst)
1081
     if (rst)
1082
       zq <= 1'b1;
1083
     else
1084
     if (cke)
1085
       zq <= q_next == {length{1'b0}};
1086
endmodule
1087
//////////////////////////////////////////////////////////////////////
1088
////                                                              ////
1089
////  Versatile counter                                           ////
1090
////                                                              ////
1091
////  Description                                                 ////
1092
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1093
////  counter                                                     ////
1094
////                                                              ////
1095
////  To Do:                                                      ////
1096
////   - add LFSR with more taps                                  ////
1097
////                                                              ////
1098
////  Author(s):                                                  ////
1099
////      - Michael Unneback, unneback@opencores.org              ////
1100
////        ORSoC AB                                              ////
1101
////                                                              ////
1102
//////////////////////////////////////////////////////////////////////
1103
////                                                              ////
1104
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1105
////                                                              ////
1106
//// This source file may be used and distributed without         ////
1107
//// restriction provided that this copyright statement is not    ////
1108
//// removed from the file and that any derivative work contains  ////
1109
//// the original copyright notice and the associated disclaimer. ////
1110
////                                                              ////
1111
//// This source file is free software; you can redistribute it   ////
1112
//// and/or modify it under the terms of the GNU Lesser General   ////
1113
//// Public License as published by the Free Software Foundation; ////
1114
//// either version 2.1 of the License, or (at your option) any   ////
1115
//// later version.                                               ////
1116
////                                                              ////
1117
//// This source is distributed in the hope that it will be       ////
1118
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1119
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1120
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1121
//// details.                                                     ////
1122
////                                                              ////
1123
//// You should have received a copy of the GNU Lesser General    ////
1124
//// Public License along with this source; if not, download it   ////
1125
//// from http://www.opencores.org/lgpl.shtml                     ////
1126
////                                                              ////
1127
//////////////////////////////////////////////////////////////////////
1128
 
1129
// LFSR counter
1130
module cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk);
1131
 
1132
   parameter length = 4;
1133
   input cke;
1134
   input rew;
1135
   output reg level1;
1136
   input rst;
1137
   input clk;
1138
 
1139
   parameter clear_value = 0;
1140
   parameter set_value = 1;
1141
   parameter wrap_value = 8;
1142
   parameter level1_value = 15;
1143
 
1144
   reg  [length:1] qi;
1145
   reg lfsr_fb, lfsr_fb_rew;
1146
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1147
   reg [32:1] polynom_rew;
1148
   integer j;
1149
   reg [32:1] polynom;
1150
   integer i;
1151
 
1152
   always @ (qi)
1153
   begin
1154
        case (length)
1155
         2: polynom = 32'b11;                               // 0x3
1156
         3: polynom = 32'b110;                              // 0x6
1157
         4: polynom = 32'b1100;                             // 0xC
1158
         5: polynom = 32'b10100;                            // 0x14
1159
         6: polynom = 32'b110000;                           // 0x30
1160
         7: polynom = 32'b1100000;                          // 0x60
1161
         8: polynom = 32'b10111000;                         // 0xb8
1162
         9: polynom = 32'b100010000;                        // 0x110
1163
        10: polynom = 32'b1001000000;                       // 0x240
1164
        11: polynom = 32'b10100000000;                      // 0x500
1165
        12: polynom = 32'b100000101001;                     // 0x829
1166
        13: polynom = 32'b1000000001100;                    // 0x100C
1167
        14: polynom = 32'b10000000010101;                   // 0x2015
1168
        15: polynom = 32'b110000000000000;                  // 0x6000
1169
        16: polynom = 32'b1101000000001000;                 // 0xD008
1170
        17: polynom = 32'b10010000000000000;                // 0x12000
1171
        18: polynom = 32'b100000010000000000;               // 0x20400
1172
        19: polynom = 32'b1000000000000100011;              // 0x40023
1173
        20: polynom = 32'b10000010000000000000;             // 0x82000
1174
        21: polynom = 32'b101000000000000000000;            // 0x140000
1175
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1176
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1177
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1178
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1179
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1180
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1181
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1182
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1183
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1184
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1185
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1186
        default: polynom = 32'b0;
1187
        endcase
1188
        lfsr_fb = qi[length];
1189
        for (i=length-1; i>=1; i=i-1) begin
1190
            if (polynom[i])
1191
                lfsr_fb = lfsr_fb  ~^ qi[i];
1192
        end
1193
    end
1194
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1195
   always @ (qi)
1196
   begin
1197
        case (length)
1198
         2: polynom_rew = 32'b11;
1199
         3: polynom_rew = 32'b110;
1200
         4: polynom_rew = 32'b1100;
1201
         5: polynom_rew = 32'b10100;
1202
         6: polynom_rew = 32'b110000;
1203
         7: polynom_rew = 32'b1100000;
1204
         8: polynom_rew = 32'b10111000;
1205
         9: polynom_rew = 32'b100010000;
1206
        10: polynom_rew = 32'b1001000000;
1207
        11: polynom_rew = 32'b10100000000;
1208
        12: polynom_rew = 32'b100000101001;
1209
        13: polynom_rew = 32'b1000000001100;
1210
        14: polynom_rew = 32'b10000000010101;
1211
        15: polynom_rew = 32'b110000000000000;
1212
        16: polynom_rew = 32'b1101000000001000;
1213
        17: polynom_rew = 32'b10010000000000000;
1214
        18: polynom_rew = 32'b100000010000000000;
1215
        19: polynom_rew = 32'b1000000000000100011;
1216
        20: polynom_rew = 32'b10000010000000000000;
1217
        21: polynom_rew = 32'b101000000000000000000;
1218
        22: polynom_rew = 32'b1100000000000000000000;
1219
        23: polynom_rew = 32'b10000100000000000000000;
1220
        24: polynom_rew = 32'b111000010000000000000000;
1221
        25: polynom_rew = 32'b1001000000000000000000000;
1222
        26: polynom_rew = 32'b10000000000000000000100011;
1223
        27: polynom_rew = 32'b100000000000000000000010011;
1224
        28: polynom_rew = 32'b1100100000000000000000000000;
1225
        29: polynom_rew = 32'b10100000000000000000000000000;
1226
        30: polynom_rew = 32'b100000000000000000000000101001;
1227
        31: polynom_rew = 32'b1001000000000000000000000000000;
1228
        32: polynom_rew = 32'b10000000001000000000000000000011;
1229
        default: polynom_rew = 32'b0;
1230
        endcase
1231
        // rotate left
1232
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
1233
        lfsr_fb_rew = qi[length];
1234
        for (i=length-1; i>=1; i=i-1) begin
1235
            if (polynom_rew[i])
1236
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
1237
        end
1238
    end
1239
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
1240
   assign q_next = rew ? q_next_rew : q_next_fw;
1241
 
1242
   always @ (posedge clk or posedge rst)
1243
     if (rst)
1244
       qi <= {length{1'b0}};
1245
     else
1246
     if (cke)
1247
       qi <= q_next;
1248
 
1249
 
1250
 
1251
    always @ (posedge clk or posedge rst)
1252
    if (rst)
1253
        level1 <= 1'b0;
1254
    else
1255
    if (cke)
1256
    if (q_next == level1_value)
1257
        level1 <= 1'b1;
1258
    else if (qi == level1_value & rew)
1259
        level1 <= 1'b0;
1260
endmodule
1261
//////////////////////////////////////////////////////////////////////
1262
////                                                              ////
1263
////  Versatile counter                                           ////
1264
////                                                              ////
1265
////  Description                                                 ////
1266
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1267
////  counter                                                     ////
1268
////                                                              ////
1269
////  To Do:                                                      ////
1270
////   - add LFSR with more taps                                  ////
1271
////                                                              ////
1272
////  Author(s):                                                  ////
1273
////      - Michael Unneback, unneback@opencores.org              ////
1274
////        ORSoC AB                                              ////
1275
////                                                              ////
1276
//////////////////////////////////////////////////////////////////////
1277
////                                                              ////
1278
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1279
////                                                              ////
1280
//// This source file may be used and distributed without         ////
1281
//// restriction provided that this copyright statement is not    ////
1282
//// removed from the file and that any derivative work contains  ////
1283
//// the original copyright notice and the associated disclaimer. ////
1284
////                                                              ////
1285
//// This source file is free software; you can redistribute it   ////
1286
//// and/or modify it under the terms of the GNU Lesser General   ////
1287
//// Public License as published by the Free Software Foundation; ////
1288
//// either version 2.1 of the License, or (at your option) any   ////
1289
//// later version.                                               ////
1290
////                                                              ////
1291
//// This source is distributed in the hope that it will be       ////
1292
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1293
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1294
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1295
//// details.                                                     ////
1296
////                                                              ////
1297
//// You should have received a copy of the GNU Lesser General    ////
1298
//// Public License along with this source; if not, download it   ////
1299
//// from http://www.opencores.org/lgpl.shtml                     ////
1300
////                                                              ////
1301
//////////////////////////////////////////////////////////////////////
1302
 
1303
// GRAY counter
1304
module cnt_gray ( q, rst, clk);
1305
 
1306
   parameter length = 4;
1307
   output reg [length:1] q;
1308
   input rst;
1309
   input clk;
1310
 
1311
   parameter clear_value = 0;
1312
   parameter set_value = 1;
1313
   parameter wrap_value = 8;
1314
   parameter level1_value = 15;
1315
 
1316
   reg  [length:1] qi;
1317
   wire [length:1] q_next;
1318
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1319
 
1320
   always @ (posedge clk or posedge rst)
1321
     if (rst)
1322
       qi <= {length{1'b0}};
1323
     else
1324
       qi <= q_next;
1325
 
1326
   always @ (posedge clk or posedge rst)
1327
     if (rst)
1328
       q <= {length{1'b0}};
1329
     else
1330
         q <= (q_next>>1) ^ q_next;
1331
 
1332
endmodule
1333
//////////////////////////////////////////////////////////////////////
1334
////                                                              ////
1335
////  Versatile counter                                           ////
1336
////                                                              ////
1337
////  Description                                                 ////
1338
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1339
////  counter                                                     ////
1340
////                                                              ////
1341
////  To Do:                                                      ////
1342
////   - add LFSR with more taps                                  ////
1343
////                                                              ////
1344
////  Author(s):                                                  ////
1345
////      - Michael Unneback, unneback@opencores.org              ////
1346
////        ORSoC AB                                              ////
1347
////                                                              ////
1348
//////////////////////////////////////////////////////////////////////
1349
////                                                              ////
1350
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1351
////                                                              ////
1352
//// This source file may be used and distributed without         ////
1353
//// restriction provided that this copyright statement is not    ////
1354
//// removed from the file and that any derivative work contains  ////
1355
//// the original copyright notice and the associated disclaimer. ////
1356
////                                                              ////
1357
//// This source file is free software; you can redistribute it   ////
1358
//// and/or modify it under the terms of the GNU Lesser General   ////
1359
//// Public License as published by the Free Software Foundation; ////
1360
//// either version 2.1 of the License, or (at your option) any   ////
1361
//// later version.                                               ////
1362
////                                                              ////
1363
//// This source is distributed in the hope that it will be       ////
1364
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1365
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1366
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1367
//// details.                                                     ////
1368
////                                                              ////
1369
//// You should have received a copy of the GNU Lesser General    ////
1370
//// Public License along with this source; if not, download it   ////
1371
//// from http://www.opencores.org/lgpl.shtml                     ////
1372
////                                                              ////
1373
//////////////////////////////////////////////////////////////////////
1374
 
1375
// GRAY counter
1376
module cnt_gray_ce ( cke, q, rst, clk);
1377
 
1378
   parameter length = 4;
1379
   input cke;
1380
   output reg [length:1] q;
1381
   input rst;
1382
   input clk;
1383
 
1384
   parameter clear_value = 0;
1385
   parameter set_value = 1;
1386
   parameter wrap_value = 8;
1387
   parameter level1_value = 15;
1388
 
1389
   reg  [length:1] qi;
1390
   wire [length:1] q_next;
1391
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1392
 
1393
   always @ (posedge clk or posedge rst)
1394
     if (rst)
1395
       qi <= {length{1'b0}};
1396
     else
1397
     if (cke)
1398
       qi <= q_next;
1399
 
1400
   always @ (posedge clk or posedge rst)
1401
     if (rst)
1402
       q <= {length{1'b0}};
1403
     else
1404
       if (cke)
1405
         q <= (q_next>>1) ^ q_next;
1406
 
1407
endmodule
1408
//////////////////////////////////////////////////////////////////////
1409
////                                                              ////
1410
////  Versatile counter                                           ////
1411
////                                                              ////
1412
////  Description                                                 ////
1413
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1414
////  counter                                                     ////
1415
////                                                              ////
1416
////  To Do:                                                      ////
1417
////   - add LFSR with more taps                                  ////
1418
////                                                              ////
1419
////  Author(s):                                                  ////
1420
////      - Michael Unneback, unneback@opencores.org              ////
1421
////        ORSoC AB                                              ////
1422
////                                                              ////
1423
//////////////////////////////////////////////////////////////////////
1424
////                                                              ////
1425
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1426
////                                                              ////
1427
//// This source file may be used and distributed without         ////
1428
//// restriction provided that this copyright statement is not    ////
1429
//// removed from the file and that any derivative work contains  ////
1430
//// the original copyright notice and the associated disclaimer. ////
1431
////                                                              ////
1432
//// This source file is free software; you can redistribute it   ////
1433
//// and/or modify it under the terms of the GNU Lesser General   ////
1434
//// Public License as published by the Free Software Foundation; ////
1435
//// either version 2.1 of the License, or (at your option) any   ////
1436
//// later version.                                               ////
1437
////                                                              ////
1438
//// This source is distributed in the hope that it will be       ////
1439
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1440
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1441
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1442
//// details.                                                     ////
1443
////                                                              ////
1444
//// You should have received a copy of the GNU Lesser General    ////
1445
//// Public License along with this source; if not, download it   ////
1446
//// from http://www.opencores.org/lgpl.shtml                     ////
1447
////                                                              ////
1448
//////////////////////////////////////////////////////////////////////
1449
 
1450
// GRAY counter
1451
module cnt_gray_ce_bin ( cke, q, q_bin, rst, clk);
1452
 
1453
   parameter length = 4;
1454
   input cke;
1455
   output reg [length:1] q;
1456
   output [length:1] q_bin;
1457
   input rst;
1458
   input clk;
1459
 
1460
   parameter clear_value = 0;
1461
   parameter set_value = 1;
1462
   parameter wrap_value = 8;
1463
   parameter level1_value = 15;
1464
 
1465
   reg  [length:1] qi;
1466
   wire [length:1] q_next;
1467
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1468
 
1469
   always @ (posedge clk or posedge rst)
1470
     if (rst)
1471
       qi <= {length{1'b0}};
1472
     else
1473
     if (cke)
1474
       qi <= q_next;
1475
 
1476
   always @ (posedge clk or posedge rst)
1477
     if (rst)
1478
       q <= {length{1'b0}};
1479
     else
1480
       if (cke)
1481
         q <= (q_next>>1) ^ q_next;
1482
 
1483
   assign q_bin = qi;
1484
 
1485
endmodule
1486
//////////////////////////////////////////////////////////////////////
1487
////                                                              ////
1488
////  Versatile library, counters                                 ////
1489
////                                                              ////
1490
////  Description                                                 ////
1491
////  counters                                                    ////
1492
////                                                              ////
1493
////                                                              ////
1494
////  To Do:                                                      ////
1495
////   - add more counters                                        ////
1496
////                                                              ////
1497
////  Author(s):                                                  ////
1498
////      - Michael Unneback, unneback@opencores.org              ////
1499
////        ORSoC AB                                              ////
1500
////                                                              ////
1501
//////////////////////////////////////////////////////////////////////
1502
////                                                              ////
1503
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1504
////                                                              ////
1505
//// This source file may be used and distributed without         ////
1506
//// restriction provided that this copyright statement is not    ////
1507
//// removed from the file and that any derivative work contains  ////
1508
//// the original copyright notice and the associated disclaimer. ////
1509
////                                                              ////
1510
//// This source file is free software; you can redistribute it   ////
1511
//// and/or modify it under the terms of the GNU Lesser General   ////
1512
//// Public License as published by the Free Software Foundation; ////
1513
//// either version 2.1 of the License, or (at your option) any   ////
1514
//// later version.                                               ////
1515
////                                                              ////
1516
//// This source is distributed in the hope that it will be       ////
1517
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1518
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1519
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1520
//// details.                                                     ////
1521
////                                                              ////
1522
//// You should have received a copy of the GNU Lesser General    ////
1523
//// Public License along with this source; if not, download it   ////
1524
//// from http://www.opencores.org/lgpl.shtml                     ////
1525
////                                                              ////
1526
//////////////////////////////////////////////////////////////////////
1527
 
1528
module cnt_shreg_wrap ( q, rst, clk);
1529
 
1530
   parameter length = 4;
1531
   output reg [0:length-1] q;
1532
   input rst;
1533
   input clk;
1534
 
1535
    always @ (posedge clk or posedge rst)
1536
    if (rst)
1537
        q <= {1'b1,{length-1{1'b0}}};
1538
    else
1539
        q <= {q[length-1],q[0:length-2]};
1540
 
1541
endmodule
1542
 
1543
module cnt_shreg_ce_wrap ( cke, q, rst, clk);
1544
 
1545
   parameter length = 4;
1546
   input cke;
1547
   output reg [0:length-1] q;
1548
   input rst;
1549
   input clk;
1550
 
1551
    always @ (posedge clk or posedge rst)
1552
    if (rst)
1553
        q <= {1'b1,{length-1{1'b0}}};
1554
    else
1555
        if (cke)
1556
            q <= {q[length-1],q[0:length-2]};
1557
 
1558
endmodule
1559
 
1560
module cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
1561
 
1562
   parameter length = 4;
1563
   input cke, clear;
1564
   output reg [0:length-1] q;
1565
   input rst;
1566
   input clk;
1567
 
1568
    always @ (posedge clk or posedge rst)
1569
    if (rst)
1570
        q <= {1'b1,{length-1{1'b0}}};
1571
    else
1572
        if (cke)
1573
            if (clear)
1574
                q <= {1'b1,{length-1{1'b0}}};
1575
            else
1576
                q <= q >> 1;
1577
 
1578
endmodule
1579
 
1580
module cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
1581
 
1582
   parameter length = 4;
1583
   input cke, clear;
1584
   output reg [0:length-1] q;
1585
   input rst;
1586
   input clk;
1587
 
1588
    always @ (posedge clk or posedge rst)
1589
    if (rst)
1590
        q <= {1'b1,{length-1{1'b0}}};
1591
    else
1592
        if (cke)
1593
            if (clear)
1594
                q <= {1'b1,{length-1{1'b0}}};
1595
            else
1596
            q <= {q[length-1],q[0:length-2]};
1597
 
1598
endmodule
1599
//////////////////////////////////////////////////////////////////////
1600
////                                                              ////
1601
////  Versatile library, memories                                 ////
1602
////                                                              ////
1603
////  Description                                                 ////
1604
////  memories                                                    ////
1605
////                                                              ////
1606
////                                                              ////
1607
////  To Do:                                                      ////
1608
////   - add more memory types                                    ////
1609
////                                                              ////
1610
////  Author(s):                                                  ////
1611
////      - Michael Unneback, unneback@opencores.org              ////
1612
////        ORSoC AB                                              ////
1613
////                                                              ////
1614
//////////////////////////////////////////////////////////////////////
1615
////                                                              ////
1616
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1617
////                                                              ////
1618
//// This source file may be used and distributed without         ////
1619
//// restriction provided that this copyright statement is not    ////
1620
//// removed from the file and that any derivative work contains  ////
1621
//// the original copyright notice and the associated disclaimer. ////
1622
////                                                              ////
1623
//// This source file is free software; you can redistribute it   ////
1624
//// and/or modify it under the terms of the GNU Lesser General   ////
1625
//// Public License as published by the Free Software Foundation; ////
1626
//// either version 2.1 of the License, or (at your option) any   ////
1627
//// later version.                                               ////
1628
////                                                              ////
1629
//// This source is distributed in the hope that it will be       ////
1630
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1631
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1632
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1633
//// details.                                                     ////
1634
////                                                              ////
1635
//// You should have received a copy of the GNU Lesser General    ////
1636
//// Public License along with this source; if not, download it   ////
1637
//// from http://www.opencores.org/lgpl.shtml                     ////
1638
////                                                              ////
1639
//////////////////////////////////////////////////////////////////////
1640
 
1641
/// ROM
1642
 
1643 7 unneback
module vl_rom_init ( adr, q, clk);
1644
   parameter data_width = 32;
1645
   parameter addr_width = 8;
1646
   input [(addr_width-1):0]       adr;
1647
   output reg [(data_width-1):0] q;
1648
   input                         clk;
1649
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
1650
   parameter memory_file = "vl_rom.vmem";
1651
   initial
1652
     begin
1653
        $readmemh(memory_file, rom);
1654
     end
1655
 
1656
   always @ (posedge clk)
1657
     q <= rom[adr];
1658 6 unneback
 
1659 7 unneback
endmodule
1660
 
1661 14 unneback
/*
1662 7 unneback
module vl_rom ( adr, q, clk);
1663
 
1664 6 unneback
parameter data_width = 32;
1665
parameter addr_width = 4;
1666
 
1667
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
1668
    {32'h18000000},
1669
    {32'hA8200000},
1670
    {32'hA8200000},
1671
    {32'hA8200000},
1672
    {32'h44003000},
1673
    {32'h15000000},
1674
    {32'h15000000},
1675
    {32'h15000000},
1676
    {32'h15000000},
1677
    {32'h15000000},
1678
    {32'h15000000},
1679
    {32'h15000000},
1680
    {32'h15000000},
1681
    {32'h15000000},
1682
    {32'h15000000},
1683
    {32'h15000000}};
1684
 
1685 7 unneback
input [addr_width-1:0] adr;
1686 6 unneback
output reg [data_width-1:0] q;
1687
input clk;
1688
 
1689
always @ (posedge clk)
1690 7 unneback
    q <= data[adr];
1691 6 unneback
 
1692
endmodule
1693 14 unneback
*/
1694 6 unneback
// Single port RAM
1695
 
1696
module vl_ram ( d, adr, we, q, clk);
1697
   parameter data_width = 32;
1698
   parameter addr_width = 8;
1699
   input [(data_width-1):0]      d;
1700
   input [(addr_width-1):0]       adr;
1701
   input                         we;
1702 7 unneback
   output reg [(data_width-1):0] q;
1703 6 unneback
   input                         clk;
1704
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
1705 7 unneback
   parameter init = 0;
1706
   parameter memory_file = "vl_ram.vmem";
1707
   generate if (init) begin : init_mem
1708
   initial
1709
     begin
1710
        $readmemh(memory_file, ram);
1711
     end
1712
   end
1713
   endgenerate
1714
 
1715 6 unneback
   always @ (posedge clk)
1716
   begin
1717
   if (we)
1718
     ram[adr] <= d;
1719
   q <= ram[adr];
1720
   end
1721
 
1722
endmodule
1723
 
1724 7 unneback
module vl_ram_be ( d, adr, be, we, q, clk);
1725
   parameter data_width = 32;
1726
   parameter addr_width = 8;
1727
   input [(data_width-1):0]      d;
1728
   input [(addr_width-1):0]       adr;
1729
   input [(addr_width/4)-1:0]    be;
1730
   input                         we;
1731
   output reg [(data_width-1):0] q;
1732
   input                         clk;
1733
 
1734
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
1735
 
1736
   parameter init = 0;
1737
   parameter memory_file = "vl_ram.vmem";
1738
   generate if (init) begin : init_mem
1739
   initial
1740
     begin
1741
        $readmemh(memory_file, ram);
1742
     end
1743
   end
1744
   endgenerate
1745
 
1746
   genvar i;
1747
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
1748
      always @ (posedge clk)
1749
      if (we & be[i])
1750
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
1751
   end
1752
   endgenerate
1753
 
1754
   always @ (posedge clk)
1755
      q <= ram[adr];
1756
 
1757
endmodule
1758
 
1759
 
1760 6 unneback
// Dual port RAM
1761
 
1762
// ACTEL FPGA should not use logic to handle rw collision
1763
`ifdef ACTEL
1764
        `define SYN /*synthesis syn_ramstyle = "no_rw_check"*/
1765
`else
1766
        `define SYN
1767
`endif
1768
 
1769 7 unneback
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1770 6 unneback
   parameter data_width = 32;
1771
   parameter addr_width = 8;
1772
   input [(data_width-1):0]      d_a;
1773
   input [(addr_width-1):0]       adr_a;
1774
   input [(addr_width-1):0]       adr_b;
1775
   input                         we_a;
1776
   output [(data_width-1):0]      q_b;
1777
   input                         clk_a, clk_b;
1778
   reg [(addr_width-1):0]         adr_b_reg;
1779
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
1780 7 unneback
 
1781
   parameter init = 0;
1782
   parameter memory_file = "vl_ram.vmem";
1783
   generate if (init) begin : init_mem
1784
   initial
1785
     begin
1786
        $readmemh(memory_file, ram);
1787
     end
1788
   end
1789
   endgenerate
1790
 
1791 6 unneback
   always @ (posedge clk_a)
1792
   if (we_a)
1793
     ram[adr_a] <= d_a;
1794
   always @ (posedge clk_b)
1795
   adr_b_reg <= adr_b;
1796
   assign q_b = ram[adr_b_reg];
1797
endmodule
1798
 
1799 7 unneback
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1800 6 unneback
   parameter data_width = 32;
1801
   parameter addr_width = 8;
1802
   input [(data_width-1):0]      d_a;
1803
   input [(addr_width-1):0]       adr_a;
1804
   input [(addr_width-1):0]       adr_b;
1805
   input                         we_a;
1806
   output [(data_width-1):0]      q_b;
1807
   output reg [(data_width-1):0] q_a;
1808
   input                         clk_a, clk_b;
1809
   reg [(data_width-1):0]         q_b;
1810
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
1811 7 unneback
 
1812
   parameter init = 0;
1813
   parameter memory_file = "vl_ram.vmem";
1814
   generate if (init) begin : init_mem
1815
   initial
1816
     begin
1817
        $readmemh(memory_file, ram);
1818
     end
1819
   end
1820
   endgenerate
1821
 
1822 6 unneback
   always @ (posedge clk_a)
1823
     begin
1824
        q_a <= ram[adr_a];
1825
        if (we_a)
1826
             ram[adr_a] <= d_a;
1827
     end
1828
   always @ (posedge clk_b)
1829
          q_b <= ram[adr_b];
1830
endmodule
1831
 
1832 7 unneback
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
1833 6 unneback
   parameter data_width = 32;
1834
   parameter addr_width = 8;
1835
   input [(data_width-1):0]      d_a;
1836
   input [(addr_width-1):0]       adr_a;
1837
   input [(addr_width-1):0]       adr_b;
1838
   input                         we_a;
1839
   output [(data_width-1):0]      q_b;
1840
   input [(data_width-1):0]       d_b;
1841
   output reg [(data_width-1):0] q_a;
1842
   input                         we_b;
1843
   input                         clk_a, clk_b;
1844
   reg [(data_width-1):0]         q_b;
1845
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
1846 7 unneback
 
1847
   parameter init = 0;
1848
   parameter memory_file = "vl_ram.vmem";
1849
   generate if (init) begin : init_mem
1850
   initial
1851
     begin
1852
        $readmemh(memory_file, ram);
1853
     end
1854
   end
1855
   endgenerate
1856
 
1857 6 unneback
   always @ (posedge clk_a)
1858
     begin
1859
        q_a <= ram[adr_a];
1860
        if (we_a)
1861
             ram[adr_a] <= d_a;
1862
     end
1863
   always @ (posedge clk_b)
1864
     begin
1865
        q_b <= ram[adr_b];
1866
        if (we_b)
1867
          ram[adr_b] <= d_b;
1868
     end
1869
endmodule
1870
 
1871
// Content addresable memory, CAM
1872
 
1873
// FIFO
1874
 
1875
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
1876
 
1877 11 unneback
   parameter addr_width = 4;
1878
   parameter N = addr_width-1;
1879 6 unneback
 
1880
   parameter Q1 = 2'b00;
1881
   parameter Q2 = 2'b01;
1882
   parameter Q3 = 2'b11;
1883
   parameter Q4 = 2'b10;
1884
 
1885
   parameter going_empty = 1'b0;
1886
   parameter going_full  = 1'b1;
1887
 
1888
   input [N:0]  wptr, rptr;
1889 14 unneback
   output       fifo_empty;
1890 6 unneback
   output       fifo_full;
1891
   input        wclk, rclk, rst;
1892
 
1893
`ifndef GENERATE_DIRECTION_AS_LATCH
1894
   wire direction;
1895
`endif
1896
`ifdef GENERATE_DIRECTION_AS_LATCH
1897
   reg direction;
1898
`endif
1899
   reg  direction_set, direction_clr;
1900
 
1901
   wire async_empty, async_full;
1902
   wire fifo_full2;
1903 14 unneback
   wire fifo_empty2;
1904 6 unneback
 
1905
   // direction_set
1906
   always @ (wptr[N:N-1] or rptr[N:N-1])
1907
     case ({wptr[N:N-1],rptr[N:N-1]})
1908
       {Q1,Q2} : direction_set <= 1'b1;
1909
       {Q2,Q3} : direction_set <= 1'b1;
1910
       {Q3,Q4} : direction_set <= 1'b1;
1911
       {Q4,Q1} : direction_set <= 1'b1;
1912
       default : direction_set <= 1'b0;
1913
     endcase
1914
 
1915
   // direction_clear
1916
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
1917
     if (rst)
1918
       direction_clr <= 1'b1;
1919
     else
1920
       case ({wptr[N:N-1],rptr[N:N-1]})
1921
         {Q2,Q1} : direction_clr <= 1'b1;
1922
         {Q3,Q2} : direction_clr <= 1'b1;
1923
         {Q4,Q3} : direction_clr <= 1'b1;
1924
         {Q1,Q4} : direction_clr <= 1'b1;
1925
         default : direction_clr <= 1'b0;
1926
       endcase
1927
 
1928
`ifndef GENERATE_DIRECTION_AS_LATCH
1929
    dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
1930
`endif
1931
 
1932
`ifdef GENERATE_DIRECTION_AS_LATCH
1933
   always @ (posedge direction_set or posedge direction_clr)
1934
     if (direction_clr)
1935
       direction <= going_empty;
1936
     else
1937
       direction <= going_full;
1938
`endif
1939
 
1940
   assign async_empty = (wptr == rptr) && (direction==going_empty);
1941
   assign async_full  = (wptr == rptr) && (direction==going_full);
1942
 
1943
    dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
1944
    dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
1945
 
1946
/*
1947
   always @ (posedge wclk or posedge rst or posedge async_full)
1948
     if (rst)
1949
       {fifo_full, fifo_full2} <= 2'b00;
1950
     else if (async_full)
1951
       {fifo_full, fifo_full2} <= 2'b11;
1952
     else
1953
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
1954
*/
1955 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
1956 6 unneback
     if (async_empty)
1957
       {fifo_empty, fifo_empty2} <= 2'b11;
1958
     else
1959 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
1960
    dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
1961
    dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
1962 6 unneback
 
1963
endmodule // async_comp
1964
 
1965
module vl_fifo_1r1w_async (
1966
    d, wr, fifo_full, wr_clk, wr_rst,
1967
    q, rd, fifo_empty, rd_clk, rd_rst
1968
    );
1969
 
1970
parameter data_width = 18;
1971
parameter addr_width = 4;
1972
 
1973
// write side
1974
input  [data_width-1:0] d;
1975
input                   wr;
1976
output                  fifo_full;
1977
input                   wr_clk;
1978
input                   wr_rst;
1979
// read side
1980
output [data_width-1:0] q;
1981
input                   rd;
1982
output                  fifo_empty;
1983
input                   rd_clk;
1984
input                   rd_rst;
1985
 
1986
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
1987
 
1988
vl_fifo_1r1w_async (
1989
    d, wr, fifo_full, wr_clk, wr_rst,
1990
    q, rd, fifo_empty, rd_clk, rd_rst
1991
    );
1992
 
1993 7 unneback
cnt_gray_ce_bin
1994 6 unneback
    # ( .length(addr_width))
1995
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
1996
 
1997 7 unneback
cnt_gray_ce_bin
1998 6 unneback
    # (.length(addr_width))
1999
    fifo_rd_adr( .cke(wr), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_rst));
2000
 
2001 7 unneback
vl_dpram_1r1w
2002 6 unneback
    # (.data_width(data_width), .addr_width(addr_width))
2003
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
2004
 
2005
vl_fifo_cmp_async
2006
    # (.addr_width(addr_width))
2007
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
2008
 
2009
endmodule
2010
 
2011 8 unneback
module vl_fifo_2r2w_async (
2012 6 unneback
    // a side
2013
    a_d, a_wr, a_fifo_full,
2014
    a_q, a_rd, a_fifo_empty,
2015
    a_clk, a_rst,
2016
    // b side
2017
    b_d, b_wr, b_fifo_full,
2018
    b_q, b_rd, b_fifo_empty,
2019
    b_clk, b_rst
2020
    );
2021
 
2022
parameter data_width = 18;
2023
parameter addr_width = 4;
2024
 
2025
// a side
2026
input  [data_width-1:0] a_d;
2027
input                   a_wr;
2028
output                  a_fifo_full;
2029
output [data_width-1:0] a_q;
2030
input                   a_rd;
2031
output                  a_fifo_empty;
2032
input                   a_clk;
2033
input                   a_rst;
2034
 
2035
// b side
2036
input  [data_width-1:0] b_d;
2037
input                   b_wr;
2038
output                  b_fifo_full;
2039
output [data_width-1:0] b_q;
2040
input                   b_rd;
2041
output                  b_fifo_empty;
2042
input                   b_clk;
2043
input                   b_rst;
2044
 
2045
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
2046
vl_fifo_1r1w_async_a (
2047
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
2048
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
2049
    );
2050
 
2051
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
2052
vl_fifo_1r1w_async_b (
2053
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
2054
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
2055
    );
2056
 
2057
endmodule
2058
 
2059 8 unneback
module vl_fifo_2r2w_async_simplex (
2060 6 unneback
    // a side
2061
    a_d, a_wr, a_fifo_full,
2062
    a_q, a_rd, a_fifo_empty,
2063
    a_clk, a_rst,
2064
    // b side
2065
    b_d, b_wr, b_fifo_full,
2066
    b_q, b_rd, b_fifo_empty,
2067
    b_clk, b_rst
2068
    );
2069
 
2070
parameter data_width = 18;
2071
parameter addr_width = 4;
2072
 
2073
// a side
2074
input  [data_width-1:0] a_d;
2075
input                   a_wr;
2076
output                  a_fifo_full;
2077
output [data_width-1:0] a_q;
2078
input                   a_rd;
2079
output                  a_fifo_empty;
2080
input                   a_clk;
2081
input                   a_rst;
2082
 
2083
// b side
2084
input  [data_width-1:0] b_d;
2085
input                   b_wr;
2086
output                  b_fifo_full;
2087
output [data_width-1:0] b_q;
2088
input                   b_rd;
2089
output                  b_fifo_empty;
2090
input                   b_clk;
2091
input                   b_rst;
2092
 
2093
// adr_gen
2094
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
2095
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
2096
// dpram
2097
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
2098
 
2099 7 unneback
cnt_gray_ce_bin
2100 6 unneback
    # ( .length(addr_width))
2101
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
2102
 
2103 7 unneback
cnt_gray_ce_bin
2104 6 unneback
    # (.length(addr_width))
2105
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
2106
 
2107 7 unneback
cnt_gray_ce_bin
2108 6 unneback
    # ( .length(addr_width))
2109
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
2110
 
2111 7 unneback
cnt_gray_ce_bin
2112 6 unneback
    # (.length(addr_width))
2113
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
2114
 
2115
// mux read or write adr to DPRAM
2116
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
2117
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
2118
 
2119 11 unneback
vl_dpram_2r2w
2120 6 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
2121
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
2122
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
2123
 
2124 11 unneback
vl_fifo_cmp_async
2125 6 unneback
    # (.addr_width(addr_width))
2126
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
2127
 
2128 11 unneback
vl_fifo_cmp_async
2129 6 unneback
    # (.addr_width(addr_width))
2130
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
2131
 
2132
endmodule
2133 12 unneback
//////////////////////////////////////////////////////////////////////
2134
////                                                              ////
2135
////  Versatile library, wishbone stuff                           ////
2136
////                                                              ////
2137
////  Description                                                 ////
2138
////  Wishbone compliant modules                                  ////
2139
////                                                              ////
2140
////                                                              ////
2141
////  To Do:                                                      ////
2142
////   -                                                          ////
2143
////                                                              ////
2144
////  Author(s):                                                  ////
2145
////      - Michael Unneback, unneback@opencores.org              ////
2146
////        ORSoC AB                                              ////
2147
////                                                              ////
2148
//////////////////////////////////////////////////////////////////////
2149
////                                                              ////
2150
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2151
////                                                              ////
2152
//// This source file may be used and distributed without         ////
2153
//// restriction provided that this copyright statement is not    ////
2154
//// removed from the file and that any derivative work contains  ////
2155
//// the original copyright notice and the associated disclaimer. ////
2156
////                                                              ////
2157
//// This source file is free software; you can redistribute it   ////
2158
//// and/or modify it under the terms of the GNU Lesser General   ////
2159
//// Public License as published by the Free Software Foundation; ////
2160
//// either version 2.1 of the License, or (at your option) any   ////
2161
//// later version.                                               ////
2162
////                                                              ////
2163
//// This source is distributed in the hope that it will be       ////
2164
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2165
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2166
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2167
//// details.                                                     ////
2168
////                                                              ////
2169
//// You should have received a copy of the GNU Lesser General    ////
2170
//// Public License along with this source; if not, download it   ////
2171
//// from http://www.opencores.org/lgpl.shtml                     ////
2172
////                                                              ////
2173
//////////////////////////////////////////////////////////////////////
2174
 
2175
// async wb3 - wb3 bridge
2176
`timescale 1ns/1ns
2177
module wb3wb3_bridge (
2178
        // wishbone slave side
2179
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
2180
        // wishbone master side
2181
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
2182
 
2183
input [31:0] wbs_dat_i;
2184
input [31:2] wbs_adr_i;
2185
input [3:0]  wbs_sel_i;
2186
input [1:0]  wbs_bte_i;
2187
input [2:0]  wbs_cti_i;
2188
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
2189
output [31:0] wbs_dat_o;
2190 14 unneback
output wbs_ack_o;
2191 12 unneback
input wbs_clk, wbs_rst;
2192
 
2193
output [31:0] wbm_dat_o;
2194
output reg [31:2] wbm_adr_o;
2195
output [3:0]  wbm_sel_o;
2196
output reg [1:0]  wbm_bte_o;
2197
output reg [2:0]  wbm_cti_o;
2198 14 unneback
output reg wbm_we_o;
2199
output wbm_cyc_o;
2200 12 unneback
output wbm_stb_o;
2201
input [31:0]  wbm_dat_i;
2202
input wbm_ack_i;
2203
input wbm_clk, wbm_rst;
2204
 
2205
parameter addr_width = 4;
2206
 
2207
// bte
2208
parameter linear       = 2'b00;
2209
parameter wrap4        = 2'b01;
2210
parameter wrap8        = 2'b10;
2211
parameter wrap16       = 2'b11;
2212
// cti
2213
parameter classic      = 3'b000;
2214
parameter incburst     = 3'b010;
2215
parameter endofburst   = 3'b111;
2216
 
2217
parameter wbs_adr  = 1'b0;
2218
parameter wbs_data = 1'b1;
2219
 
2220
parameter wbm_adr0 = 2'b00;
2221
parameter wbm_adr1 = 2'b01;
2222
parameter wbm_data = 2'b10;
2223
 
2224
reg [1:0] wbs_bte_reg;
2225
reg wbs;
2226
wire wbs_eoc_alert, wbm_eoc_alert;
2227
reg wbs_eoc, wbm_eoc;
2228
reg [1:0] wbm;
2229
 
2230 14 unneback
wire [1:16] wbs_count, wbm_count;
2231 12 unneback
 
2232
wire [35:0] a_d, a_q, b_d, b_q;
2233
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
2234
reg a_rd_reg;
2235
wire b_rd_adr, b_rd_data;
2236 14 unneback
wire b_rd_data_reg;
2237
wire [35:0] temp;
2238 12 unneback
 
2239
`define WE 5
2240
`define BTE 4:3
2241
`define CTI 2:0
2242
 
2243
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
2244
always @ (posedge wbs_clk or posedge wbs_rst)
2245
if (wbs_rst)
2246
        wbs_eoc <= 1'b0;
2247
else
2248
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
2249
                wbs_eoc <= wbs_bte_i==linear;
2250
        else if (wbs_eoc_alert & (a_rd | a_wr))
2251
                wbs_eoc <= 1'b1;
2252
 
2253
cnt_shreg_ce_clear # ( .length(16))
2254
    cnt0 (
2255
        .cke(wbs_ack_o),
2256
        .clear(wbs_eoc),
2257
        .q(wbs_count),
2258
        .rst(wbs_rst),
2259
        .clk(wbs_clk));
2260
 
2261
always @ (posedge wbs_clk or posedge wbs_rst)
2262
if (wbs_rst)
2263
        wbs <= wbs_adr;
2264
else
2265
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & !a_fifo_full)
2266
                wbs <= wbs_data;
2267
        else if (wbs_eoc & wbs_ack_o)
2268
                wbs <= wbs_adr;
2269
 
2270
// wbs FIFO
2271
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,wbs_bte_i,wbs_cti_i} : {wbs_dat_i,wbs_sel_i};
2272
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & !a_fifo_full :
2273
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
2274
              1'b0;
2275
assign a_rd = !a_fifo_empty;
2276
always @ (posedge wbs_clk or posedge wbs_rst)
2277
if (wbs_rst)
2278
        a_rd_reg <= 1'b0;
2279
else
2280
        a_rd_reg <= a_rd;
2281
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
2282
 
2283
assign wbs_dat_o = a_q[35:4];
2284
 
2285
always @ (posedge wbs_clk or posedge wbs_rst)
2286
if (wbs_rst)
2287 13 unneback
        wbs_bte_reg <= 2'b00;
2288 12 unneback
else
2289 13 unneback
        wbs_bte_reg <= wbs_bte_i;
2290 12 unneback
 
2291
// wbm FIFO
2292
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
2293
always @ (posedge wbm_clk or posedge wbm_rst)
2294
if (wbm_rst)
2295
        wbm_eoc <= 1'b0;
2296
else
2297
        if (wbm==wbm_adr0 & !b_fifo_empty)
2298
                wbm_eoc <= b_q[`BTE] == linear;
2299
        else if (wbm_eoc_alert & wbm_ack_i)
2300
                wbm_eoc <= 1'b1;
2301
 
2302
always @ (posedge wbm_clk or posedge wbm_rst)
2303
if (wbm_rst)
2304
        wbm <= wbm_adr0;
2305
else
2306
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
2307
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
2308
        (wbm==wbm_adr1 & !wbm_we_o) |
2309
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
2310
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
2311
 
2312
assign b_d = {wbm_dat_i,4'b1111};
2313
assign b_wr = !wbm_we_o & wbm_ack_i;
2314
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
2315
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
2316
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
2317
                   1'b0;
2318
assign b_rd = b_rd_adr | b_rd_data;
2319
 
2320
dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
2321
dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
2322
 
2323
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
2324
 
2325
cnt_shreg_ce_clear # ( .length(16))
2326
    cnt1 (
2327
        .cke(wbm_ack_i),
2328
        .clear(wbm_eoc),
2329
        .q(wbm_count),
2330
        .rst(wbm_rst),
2331
        .clk(wbm_clk));
2332
 
2333
assign wbm_cyc_o = wbm==wbm_data;
2334
assign wbm_stb_o = (wbm==wbm_data & wbm_we_o) ? !b_fifo_empty :
2335
                   (wbm==wbm_data) ? 1'b1 :
2336
                   1'b0;
2337
 
2338
always @ (posedge wbm_clk or posedge wbm_rst)
2339
if (wbm_rst)
2340
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
2341
else begin
2342
        if (wbm==wbm_adr0 & !b_fifo_empty)
2343
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
2344
        else if (wbm_eoc_alert & wbm_ack_i)
2345
                wbm_cti_o <= endofburst;
2346
end
2347
 
2348
//async_fifo_dw_simplex_top
2349
vl_fifo_2r2w_async_simplex
2350
# ( .data_width(36), .addr_width(addr_width))
2351
fifo (
2352
    // a side
2353
    .a_d(a_d),
2354
    .a_wr(a_wr),
2355
    .a_fifo_full(a_fifo_full),
2356
    .a_q(a_q),
2357
    .a_rd(a_rd),
2358
    .a_fifo_empty(a_fifo_empty),
2359
    .a_clk(wbs_clk),
2360
    .a_rst(wbs_rst),
2361
    // b side
2362
    .b_d(b_d),
2363
    .b_wr(b_wr),
2364
    .b_fifo_full(b_fifo_full),
2365
    .b_q(b_q),
2366
    .b_rd(b_rd),
2367
    .b_fifo_empty(b_fifo_empty),
2368
    .b_clk(wbm_clk),
2369
    .b_rst(wbm_rst)
2370
    );
2371
 
2372
endmodule

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