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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Blame information for rev 153

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Line No. Rev Author Line
1 40 unneback
`ifndef BASE
2
`define BASE vl_
3
`endif
4
 
5 60 unneback
// default SYN_KEEP definition
6
`define SYN_KEEP /*synthesis syn_keep = 1*/
7
 
8 44 unneback
`ifdef ACTEL
9 60 unneback
`undef SYN_KEEP
10 44 unneback
`define SYN_KEEP /*synthesis syn_keep = 1*/
11
`endif
12
 
13 98 unneback
`ifdef ACTEL
14
    // ACTEL FPGA should not use logic to handle rw collision
15
    `define SYN_NO_RW_CHECK /*synthesis syn_ramstyle = "no_rw_check"*/
16
`else
17
    `define SYN_NO_RW_CHECK
18
`endif
19
 
20 40 unneback
`ifdef ALL
21
 
22
`define GBUF
23
`define SYNC_RST
24
`define PLL
25
 
26
`define MULTS
27
`define MULTS18X18
28
`define MULT
29 140 unneback
`define ARITH_UNIT
30 40 unneback
`define SHIFT_UNIT_32
31
`define LOGIC_UNIT
32 140 unneback
`define COUNT_UNIT
33
`define EXT_UNIT
34 40 unneback
 
35
`define CNT_SHREG_WRAP
36
`define CNT_SHREG_CE_WRAP
37 105 unneback
`define CNT_SHREG_CLEAR
38 40 unneback
`define CNT_SHREG_CE_CLEAR
39
`define CNT_SHREG_CE_CLEAR_WRAP
40
 
41 139 unneback
`define CNT_BIN
42
`define CNT_BIN_CE
43
`define CNT_BIN_CLEAR
44
`define CNT_BIN_CE_CLEAR
45
`define CNT_BIN_CE_CLEAR_L1_L2
46
`define CNT_BIN_CE_CLEAR_SET_REW
47
`define CNT_BIN_CE_REW_L1
48
`define CNT_BIN_CE_REW_ZQ_L1
49
`define CNT_BIN_CE_REW_Q_ZQ_L1
50
`define CNT_GRAY
51
`define CNT_GRAY_CE
52
`define CNT_GRAY_CE_BIN
53
`define CNT_LFSR_ZQ
54
`define CNT_LFSR_CE
55
`define CNT_LFSR_CE_CLEAR_Q
56
`define CNT_LFSR_CE_Q
57
`define CNT_LFSR_CE_ZQ
58
`define CNT_LFSR_CE_Q_ZQ
59
`define CNT_LFSR_CE_REW_L1
60
 
61 40 unneback
`define MUX_ANDOR
62
`define MUX2_ANDOR
63
`define MUX3_ANDOR
64
`define MUX4_ANDOR
65
`define MUX5_ANDOR
66
`define MUX6_ANDOR
67 43 unneback
`define PARITY
68 40 unneback
 
69
`define ROM_INIT
70
`define RAM
71
`define RAM_BE
72
`define DPRAM_1R1W
73
`define DPRAM_2R1W
74 100 unneback
`define DPRAM_1R2W
75 40 unneback
`define DPRAM_2R2W
76 75 unneback
`define DPRAM_BE_2R2W
77 40 unneback
`define FIFO_1R1W_FILL_LEVEL_SYNC
78
`define FIFO_2R2W_SYNC_SIMPLEX
79
`define FIFO_CMP_ASYNC
80
`define FIFO_1R1W_ASYNC
81
`define FIFO_2R2W_ASYNC
82
`define FIFO_2R2W_ASYNC_SIMPLEX
83 48 unneback
`define REG_FILE
84 40 unneback
 
85
`define DFF
86
`define DFF_ARRAY
87
`define DFF_CE
88
`define DFF_CE_CLEAR
89
`define DF_CE_SET
90
`define SPR
91
`define SRP
92
`define DFF_SR
93
`define LATCH
94
`define SHREG
95
`define SHREG_CE
96
`define DELAY
97
`define DELAY_EMPTYFLAG
98 94 unneback
`define PULSE2TOGGLE
99
`define TOGGLE2PULSE
100
`define SYNCHRONIZER
101
`define CDC
102 40 unneback
 
103 75 unneback
`define WB3AVALON_BRIDGE
104 40 unneback
`define WB3WB3_BRIDGE
105
`define WB3_ARBITER_TYPE1
106 83 unneback
`define WB_ADR_INC
107 101 unneback
`define WB_RAM
108 103 unneback
`define WB_SHADOW_RAM
109 48 unneback
`define WB_B4_ROM
110 40 unneback
`define WB_BOOT_ROM
111
`define WB_DPRAM
112 101 unneback
`define WB_CACHE
113 103 unneback
`define WB_AVALON_BRIDGE
114
`define WB_AVALON_MEM_CACHE
115 136 unneback
`define WB_SDR_SDRAM_CTRL
116 40 unneback
 
117 44 unneback
`define IO_DFF_OE
118
`define O_DFF
119 136 unneback
`define O_DDR
120
`define O_CLK
121 44 unneback
 
122 40 unneback
`endif
123
 
124 136 unneback
///////////////////////////////////////
125
// dependencies
126
///////////////////////////////////////
127
 
128 40 unneback
`ifdef PLL
129
`ifndef SYNC_RST
130
`define SYNC_RST
131
`endif
132
`endif
133
 
134
`ifdef SYNC_RST
135
`ifndef GBUF
136
`define GBUF
137
`endif
138
`endif
139
 
140 136 unneback
`ifdef WB_SDR_SDRAM_CTRL
141
`ifndef WB_SHADOW_RAM
142
`define WB_SHADOW_RAM
143
`endif
144
`ifndef WB_CACHE
145
`define WB_CACHE
146
`endif
147
`ifndef WB_SDR_SDRAM
148
`define WB_SDR_SDRAM
149
`endif
150
`ifndef IO_DFF_OE
151
`define IO_DFF_OE
152
`endif
153
`ifndef O_DFF
154
`define O_DFF
155
`endif
156
`ifndef O_CLK
157
`define O_CLK
158
`endif
159
`endif
160
 
161
`ifdef WB_SDR_SDRAM
162
`ifndef CNT_SHREG_CLEAR
163
`define CNT_SHREG_CLEAR
164
`endif
165
`ifndef CNT_LFSR_ZQ
166
`define CNT_LFSR_ZQ
167
`endif
168
`ifndef DELAY_EMPTYFLAG
169
`define DELAY_EMPTYFLAG
170
`endif
171
`endif
172
 
173 108 unneback
`ifdef WB_DPRAM
174 92 unneback
`ifndef WB_ADR_INC
175
`define WB_ADR_INC
176 40 unneback
`endif
177 141 unneback
`ifndef DFF
178
`define DFF
179
`endif
180 92 unneback
`ifndef DPRAM_BE_2R2W
181
`define DPRAM_BE_2R2W
182 40 unneback
`endif
183
`endif
184
 
185
`ifdef WB3_ARBITER_TYPE1
186 42 unneback
`ifndef SPR
187
`define SPR
188
`endif
189 40 unneback
`ifndef MUX_ANDOR
190
`define MUX_ANDOR
191
`endif
192
`endif
193
 
194 76 unneback
`ifdef WB3AVALON_BRIDGE
195
`ifndef WB3WB3_BRIDGE
196
`define WB3WB3_BRIDGE
197
`endif
198
`endif
199
 
200 40 unneback
`ifdef WB3WB3_BRIDGE
201
`ifndef CNT_SHREG_CE_CLEAR
202
`define CNT_SHREG_CE_CLEAR
203
`endif
204
`ifndef DFF
205
`define DFF
206
`endif
207
`ifndef DFF_CE
208
`define DFF_CE
209
`endif
210
`ifndef CNT_SHREG_CE_CLEAR
211
`define CNT_SHREG_CE_CLEAR
212
`endif
213
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
214
`define FIFO_2R2W_ASYNC_SIMPLEX
215
`endif
216
`endif
217
 
218 103 unneback
 
219
`ifdef WB_AVALON_MEM_CACHE
220
`ifndef WB_SHADOW_RAM
221
`define WB_SHADOW_RAM
222
`endif
223
`ifndef WB_CACHE
224
`define WB_CACHE
225
`endif
226
`ifndef WB_AVALON_BRIDGE
227
`define WB_AVALON_BRIDGE
228
`endif
229
`endif
230
 
231 101 unneback
`ifdef WB_CACHE
232 100 unneback
`ifndef RAM
233
`define RAM
234
`endif
235
`ifndef WB_ADR_INC
236
`define WB_ADR_INC
237
`endif
238
`ifndef DPRAM_1R1W
239
`define DPRAM_1R1W
240
`endif
241
`ifndef DPRAM_1R2W
242
`define DPRAM_1R2W
243
`endif
244
`ifndef DPRAM_BE_2R2W
245
`define DPRAM_BE_2R2W
246
`endif
247
`ifndef CDC
248
`define CDC
249
`endif
250 136 unneback
`ifndef O_DFF
251
`define O_DFF
252 100 unneback
`endif
253 136 unneback
`ifndef O_CLK
254
`define O_CLK
255
`endif
256
`endif
257 103 unneback
 
258
`ifdef WB_SHADOW_RAM
259 115 unneback
`ifndef WB_RAM
260
`define WB_RAM
261 103 unneback
`endif
262
`endif
263
 
264
`ifdef WB_RAM
265
`ifndef WB_ADR_INC
266
`define WB_ADR_INC
267
`endif
268 114 unneback
`ifndef RAM_BE
269
`define RAM_BE
270 103 unneback
`endif
271 114 unneback
`endif
272
 
273 40 unneback
`ifdef MULTS18X18
274
`ifndef MULTS
275
`define MULTS
276
`endif
277
`endif
278
 
279
`ifdef SHIFT_UNIT_32
280
`ifndef MULTS
281
`define MULTS
282
`endif
283
`endif
284
 
285
`ifdef MUX2_ANDOR
286
`ifndef MUX_ANDOR
287
`define MUX_ANDOR
288
`endif
289
`endif
290
 
291
`ifdef MUX3_ANDOR
292
`ifndef MUX_ANDOR
293
`define MUX_ANDOR
294
`endif
295
`endif
296
 
297
`ifdef MUX4_ANDOR
298
`ifndef MUX_ANDOR
299
`define MUX_ANDOR
300
`endif
301
`endif
302
 
303
`ifdef MUX5_ANDOR
304
`ifndef MUX_ANDOR
305
`define MUX_ANDOR
306
`endif
307
`endif
308
 
309
`ifdef MUX6_ANDOR
310
`ifndef MUX_ANDOR
311
`define MUX_ANDOR
312
`endif
313
`endif
314
 
315
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
316
`ifndef CNT_BIN_CE
317
`define CNT_BIN_CE
318
`endif
319
`ifndef DPRAM_1R1W
320
`define DPRAM_1R1W
321
`endif
322
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
323
`define CNT_BIN_CE_REW_Q_ZQ_L1
324
`endif
325
`endif
326
 
327
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
328
`ifndef CNT_LFSR_CE
329
`define CNT_LFSR_CE
330
`endif
331
`ifndef DPRAM_2R2W
332
`define DPRAM_2R2W
333
`endif
334
`ifndef CNT_BIN_CE_REW_ZQ_L1
335
`define CNT_BIN_CE_REW_ZQ_L1
336
`endif
337
`endif
338
 
339
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
340
`ifndef CNT_GRAY_CE_BIN
341
`define CNT_GRAY_CE_BIN
342
`endif
343
`ifndef DPRAM_2R2W
344
`define DPRAM_2R2W
345
`endif
346
`ifndef FIFO_CMP_ASYNC
347
`define FIFO_CMP_ASYNC
348
`endif
349
`endif
350
 
351
`ifdef FIFO_2R2W_ASYNC
352
`ifndef FIFO_1R1W_ASYNC
353
`define FIFO_1R1W_ASYNC
354
`endif
355
`endif
356
 
357
`ifdef FIFO_1R1W_ASYNC
358
`ifndef CNT_GRAY_CE_BIN
359
`define CNT_GRAY_CE_BIN
360
`endif
361
`ifndef DPRAM_1R1W
362
`define DPRAM_1R1W
363
`endif
364
`ifndef FIFO_CMP_ASYNC
365
`define FIFO_CMP_ASYNC
366
`endif
367
`endif
368
 
369
`ifdef FIFO_CMP_ASYNC
370
`ifndef DFF_SR
371
`define DFF_SR
372
`endif
373
`ifndef DFF
374
`define DFF
375
`endif
376
`endif
377 48 unneback
 
378
`ifdef REG_FILE
379
`ifndef DPRAM_1R1W
380
`define DPRAM_1R1W
381
`endif
382
`endif
383 97 unneback
 
384 98 unneback
`ifdef CDC
385
`ifndef PULSE2TOGGLE
386
`define PULSE2TOGGLE
387
`endif
388
`ifndef TOGGLE2PULSE
389
`define TOGGLE2PULSE
390
`endif
391
`ifndef SYNCHRONIZER
392
`define SYNCHRONIZER
393
`endif
394
`endif
395
 
396 136 unneback
`ifdef O_CLK
397
`ifndef O_DDR
398
`define O_DDR
399
`endif
400
`endif
401
 
402 97 unneback
// size to width
403 100 unneback
`define SIZE2WIDTH_EXPR = (`SIZE2WIDTH==1) ? 0 : (`SIZE2WIDTH==2) ? 1 : (`SIZE2WIDTH==4) ? 2 : (`SIZE2WIDTH==8) ? 3 : (`SIZE2WIDTH==16) ? 4 : (`SIZE2WIDTH==32) ? 5 : (`SIZE2WIDTH==64) ? 6 : (`SIZE2WIDTH==128) ? 7 : 8;
404 62 unneback
//////////////////////////////////////////////////////////////////////
405 6 unneback
////                                                              ////
406
////  Versatile library, clock and reset                          ////
407
////                                                              ////
408
////  Description                                                 ////
409
////  Logic related to clock and reset                            ////
410
////                                                              ////
411
////                                                              ////
412
////  To Do:                                                      ////
413
////   - add more different registers                             ////
414
////                                                              ////
415
////  Author(s):                                                  ////
416
////      - Michael Unneback, unneback@opencores.org              ////
417
////        ORSoC AB                                              ////
418
////                                                              ////
419
//////////////////////////////////////////////////////////////////////
420
////                                                              ////
421
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
422
////                                                              ////
423
//// This source file may be used and distributed without         ////
424
//// restriction provided that this copyright statement is not    ////
425
//// removed from the file and that any derivative work contains  ////
426
//// the original copyright notice and the associated disclaimer. ////
427
////                                                              ////
428
//// This source file is free software; you can redistribute it   ////
429
//// and/or modify it under the terms of the GNU Lesser General   ////
430
//// Public License as published by the Free Software Foundation; ////
431
//// either version 2.1 of the License, or (at your option) any   ////
432
//// later version.                                               ////
433
////                                                              ////
434
//// This source is distributed in the hope that it will be       ////
435
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
436
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
437
//// PURPOSE.  See the GNU Lesser General Public License for more ////
438
//// details.                                                     ////
439
////                                                              ////
440
//// You should have received a copy of the GNU Lesser General    ////
441
//// Public License along with this source; if not, download it   ////
442
//// from http://www.opencores.org/lgpl.shtml                     ////
443
////                                                              ////
444
//////////////////////////////////////////////////////////////////////
445
 
446 48 unneback
`ifdef ACTEL
447
`ifdef GBUF
448
`timescale 1 ns/100 ps
449 6 unneback
// Global buffer
450
// usage:
451
// use to enable global buffers for high fan out signals such as clock and reset
452
// Version: 8.4 8.4.0.33
453
module gbuf(GL,CLK);
454
output GL;
455
input  CLK;
456
 
457
    wire GND;
458
 
459
    GND GND_1_net(.Y(GND));
460
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
461
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
462
 
463
endmodule
464
`timescale 1 ns/1 ns
465 40 unneback
`define MODULE gbuf
466
module `BASE`MODULE ( i, o);
467
`undef MODULE
468 6 unneback
input i;
469
output o;
470
`ifdef SIM_GBUF
471
assign o=i;
472
`else
473
gbuf gbuf_i0 ( .CLK(i), .GL(o));
474
`endif
475
endmodule
476 40 unneback
`endif
477 33 unneback
 
478 6 unneback
`else
479 33 unneback
 
480 40 unneback
`ifdef ALTERA
481
`ifdef GBUF
482 21 unneback
//altera
483 40 unneback
`define MODULE gbuf
484
module `BASE`MODULE ( i, o);
485
`undef MODULE
486 33 unneback
input i;
487
output o;
488
assign o = i;
489
endmodule
490 40 unneback
`endif
491 33 unneback
 
492 6 unneback
`else
493
 
494 40 unneback
`ifdef GBUF
495 6 unneback
`timescale 1 ns/100 ps
496 40 unneback
`define MODULE
497
module `BASE`MODULE ( i, o);
498
`undef MODULE
499 6 unneback
input i;
500
output o;
501
assign o = i;
502
endmodule
503 40 unneback
`endif
504 6 unneback
`endif // ALTERA
505
`endif //ACTEL
506
 
507 40 unneback
`ifdef SYNC_RST
508 6 unneback
// sync reset
509 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
510 6 unneback
// output active high global reset sync with two DFFs 
511
`timescale 1 ns/100 ps
512 40 unneback
`define MODULE sync_rst
513
module `BASE`MODULE ( rst_n_i, rst_o, clk);
514
`undef MODULE
515 6 unneback
input rst_n_i, clk;
516
output rst_o;
517 18 unneback
reg [1:0] tmp;
518 6 unneback
always @ (posedge clk or negedge rst_n_i)
519
if (!rst_n_i)
520 17 unneback
        tmp <= 2'b11;
521 6 unneback
else
522 33 unneback
        tmp <= {1'b0,tmp[1]};
523 40 unneback
`define MODULE gbuf
524
`BASE`MODULE buf_i0( .i(tmp[0]), .o(rst_o));
525
`undef MODULE
526 6 unneback
endmodule
527 40 unneback
`endif
528 6 unneback
 
529 40 unneback
`ifdef PLL
530 6 unneback
// vl_pll
531
`ifdef ACTEL
532 32 unneback
///////////////////////////////////////////////////////////////////////////////
533 17 unneback
`timescale 1 ps/1 ps
534 40 unneback
`define MODULE pll
535
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
536
`undef MODULE
537 6 unneback
parameter index = 0;
538
parameter number_of_clk = 1;
539 17 unneback
parameter period_time_0 = 20000;
540
parameter period_time_1 = 20000;
541
parameter period_time_2 = 20000;
542
parameter lock_delay = 2000000;
543 6 unneback
input clk_i, rst_n_i;
544
output lock;
545
output reg [0:number_of_clk-1] clk_o;
546
output [0:number_of_clk-1] rst_o;
547
 
548
`ifdef SIM_PLL
549
 
550
always
551
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
552
 
553
generate if (number_of_clk > 1)
554
always
555
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
556
endgenerate
557
 
558
generate if (number_of_clk > 2)
559
always
560
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
561
endgenerate
562
 
563
genvar i;
564
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
565
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
566
end
567
endgenerate
568
 
569
assign #lock_delay lock = rst_n_i;
570
 
571
endmodule
572
`else
573
generate if (number_of_clk==1 & index==0) begin
574
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
575
end
576
endgenerate // index==0
577
generate if (number_of_clk==1 & index==1) begin
578
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
579
end
580
endgenerate // index==1
581
generate if (number_of_clk==1 & index==2) begin
582
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
583
end
584
endgenerate // index==2
585
generate if (number_of_clk==1 & index==3) begin
586
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
587
end
588
endgenerate // index==0
589
 
590
generate if (number_of_clk==2 & index==0) begin
591
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
592
end
593
endgenerate // index==0
594
generate if (number_of_clk==2 & index==1) begin
595
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
596
end
597
endgenerate // index==1
598
generate if (number_of_clk==2 & index==2) begin
599
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
600
end
601
endgenerate // index==2
602
generate if (number_of_clk==2 & index==3) begin
603
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
604
end
605
endgenerate // index==0
606
 
607
generate if (number_of_clk==3 & index==0) begin
608
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
609
end
610
endgenerate // index==0
611
generate if (number_of_clk==3 & index==1) begin
612
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
613
end
614
endgenerate // index==1
615
generate if (number_of_clk==3 & index==2) begin
616
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
617
end
618
endgenerate // index==2
619
generate if (number_of_clk==3 & index==3) begin
620
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
621
end
622
endgenerate // index==0
623
 
624
genvar i;
625
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
626 40 unneback
`define MODULE sync_rst
627
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
628
`undef MODULE
629 6 unneback
end
630
endgenerate
631
endmodule
632
`endif
633 32 unneback
///////////////////////////////////////////////////////////////////////////////
634 6 unneback
 
635
`else
636
 
637 32 unneback
///////////////////////////////////////////////////////////////////////////////
638 6 unneback
`ifdef ALTERA
639
 
640 32 unneback
`timescale 1 ps/1 ps
641 40 unneback
`define MODULE pll
642
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
643
`undef MODULE
644 32 unneback
parameter index = 0;
645
parameter number_of_clk = 1;
646
parameter period_time_0 = 20000;
647
parameter period_time_1 = 20000;
648
parameter period_time_2 = 20000;
649
parameter period_time_3 = 20000;
650
parameter period_time_4 = 20000;
651
parameter lock_delay = 2000000;
652
input clk_i, rst_n_i;
653
output lock;
654
output reg [0:number_of_clk-1] clk_o;
655
output [0:number_of_clk-1] rst_o;
656
 
657
`ifdef SIM_PLL
658
 
659
always
660
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
661
 
662
generate if (number_of_clk > 1)
663
always
664
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
665
endgenerate
666
 
667
generate if (number_of_clk > 2)
668
always
669
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
670
endgenerate
671
 
672 33 unneback
generate if (number_of_clk > 3)
673 32 unneback
always
674
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
675
endgenerate
676
 
677 33 unneback
generate if (number_of_clk > 4)
678 32 unneback
always
679
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
680
endgenerate
681
 
682
genvar i;
683
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
684
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
685
end
686
endgenerate
687
 
688 33 unneback
//assign #lock_delay lock = rst_n_i;
689
assign lock = rst_n_i;
690 32 unneback
 
691
endmodule
692 6 unneback
`else
693
 
694 33 unneback
`ifdef VL_PLL0
695
`ifdef VL_PLL0_CLK1
696
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
697
`endif
698
`ifdef VL_PLL0_CLK2
699
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
700
`endif
701
`ifdef VL_PLL0_CLK3
702
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
703
`endif
704
`ifdef VL_PLL0_CLK4
705
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
706
`endif
707
`ifdef VL_PLL0_CLK5
708
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
709
`endif
710
`endif
711 32 unneback
 
712 33 unneback
`ifdef VL_PLL1
713
`ifdef VL_PLL1_CLK1
714
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
715
`endif
716
`ifdef VL_PLL1_CLK2
717
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
718
`endif
719
`ifdef VL_PLL1_CLK3
720
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
721
`endif
722
`ifdef VL_PLL1_CLK4
723
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
724
`endif
725
`ifdef VL_PLL1_CLK5
726
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
727
`endif
728
`endif
729 32 unneback
 
730 33 unneback
`ifdef VL_PLL2
731
`ifdef VL_PLL2_CLK1
732
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
733
`endif
734
`ifdef VL_PLL2_CLK2
735
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
736
`endif
737
`ifdef VL_PLL2_CLK3
738
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
739
`endif
740
`ifdef VL_PLL2_CLK4
741
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
742
`endif
743
`ifdef VL_PLL2_CLK5
744
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
745
`endif
746
`endif
747 32 unneback
 
748 33 unneback
`ifdef VL_PLL3
749
`ifdef VL_PLL3_CLK1
750
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
751
`endif
752
`ifdef VL_PLL3_CLK2
753
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
754
`endif
755
`ifdef VL_PLL3_CLK3
756
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
757
`endif
758
`ifdef VL_PLL3_CLK4
759
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
760
`endif
761
`ifdef VL_PLL3_CLK5
762
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
763
`endif
764
`endif
765 32 unneback
 
766
genvar i;
767
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
768 40 unneback
`define MODULE sync_rst
769
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
770
`undef MODULE
771 32 unneback
end
772
endgenerate
773
endmodule
774
`endif
775
///////////////////////////////////////////////////////////////////////////////
776
 
777
`else
778
 
779 6 unneback
// generic PLL
780 17 unneback
`timescale 1 ps/1 ps
781 40 unneback
`define MODULE pll
782
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
783
`undef MODULE
784 6 unneback
parameter index = 0;
785
parameter number_of_clk = 1;
786 140 unneback
parameter period_time = 20000;
787
parameter clk0_mult_by = 1;
788
parameter clk0_div_by  = 1;
789
parameter clk1_mult_by = 1;
790
parameter clk1_div_by  = 1;
791
parameter clk2_mult_by = 1;
792
parameter clk3_div_by  = 1;
793
parameter clk3_mult_by = 1;
794
parameter clk3_div_by  = 1;
795
parameter clk4_mult_by = 1;
796
parameter clk4_div_by  = 1;
797 6 unneback
input clk_i, rst_n_i;
798
output lock;
799
output reg [0:number_of_clk-1] clk_o;
800
 
801 140 unneback
initial
802
    clk_o = {number_of_clk{1'b0}};
803
 
804 6 unneback
always
805 140 unneback
    #((period_time*clk0_div_by/clk0_mult_by)/2) clk_o[0] <=  (!rst_n_i) ? 1'b0 : ~clk_o[0];
806 6 unneback
 
807
generate if (number_of_clk > 1)
808
always
809 140 unneback
    #((period_time*clk1_div_by/clk1_mult_by)/2) clk_o[1] <=  (!rst_n_i) ? 1'b0 : ~clk_o[1];
810 6 unneback
endgenerate
811
 
812
generate if (number_of_clk > 2)
813
always
814 140 unneback
    #((period_time*clk2_div_by/clk2_mult_by)/2) clk_o[2] <=  (!rst_n_i) ? 1'b0 : ~clk_o[2];
815 6 unneback
endgenerate
816
 
817 140 unneback
generate if (number_of_clk > 3)
818
always
819
    #((period_time*clk3_div_by/clk3_mult_by)/2) clk_o[3] <=  (!rst_n_i) ? 1'b0 : ~clk_o[3];
820 6 unneback
endgenerate
821
 
822 140 unneback
generate if (number_of_clk > 4)
823
always
824
    #((period_time*clk4_div_by/clk4_mult_by)/2) clk_o[4] <=  (!rst_n_i) ? 1'b0 : ~clk_o[4];
825
endgenerate
826
 
827 6 unneback
assign #lock_delay lock = rst_n_i;
828
 
829
endmodule
830
 
831
`endif //altera
832 17 unneback
`endif //actel
833 40 unneback
`undef MODULE
834
`endif//////////////////////////////////////////////////////////////////////
835 6 unneback
////                                                              ////
836
////  Versatile library, registers                                ////
837
////                                                              ////
838
////  Description                                                 ////
839
////  Different type of registers                                 ////
840
////                                                              ////
841
////                                                              ////
842
////  To Do:                                                      ////
843
////   - add more different registers                             ////
844
////                                                              ////
845
////  Author(s):                                                  ////
846
////      - Michael Unneback, unneback@opencores.org              ////
847
////        ORSoC AB                                              ////
848
////                                                              ////
849
//////////////////////////////////////////////////////////////////////
850
////                                                              ////
851
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
852
////                                                              ////
853
//// This source file may be used and distributed without         ////
854
//// restriction provided that this copyright statement is not    ////
855
//// removed from the file and that any derivative work contains  ////
856
//// the original copyright notice and the associated disclaimer. ////
857
////                                                              ////
858
//// This source file is free software; you can redistribute it   ////
859
//// and/or modify it under the terms of the GNU Lesser General   ////
860
//// Public License as published by the Free Software Foundation; ////
861
//// either version 2.1 of the License, or (at your option) any   ////
862
//// later version.                                               ////
863
////                                                              ////
864
//// This source is distributed in the hope that it will be       ////
865
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
866
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
867
//// PURPOSE.  See the GNU Lesser General Public License for more ////
868
//// details.                                                     ////
869
////                                                              ////
870
//// You should have received a copy of the GNU Lesser General    ////
871
//// Public License along with this source; if not, download it   ////
872
//// from http://www.opencores.org/lgpl.shtml                     ////
873
////                                                              ////
874
//////////////////////////////////////////////////////////////////////
875
 
876 40 unneback
`ifdef DFF
877
`define MODULE dff
878
module `BASE`MODULE ( d, q, clk, rst);
879
`undef MODULE
880 6 unneback
        parameter width = 1;
881 139 unneback
        parameter reset_value = {width{1'b0}};
882 6 unneback
 
883
        input [width-1:0] d;
884
        input clk, rst;
885
        output reg [width-1:0] q;
886
 
887
        always @ (posedge clk or posedge rst)
888
        if (rst)
889
                q <= reset_value;
890
        else
891
                q <= d;
892
 
893
endmodule
894 40 unneback
`endif
895 6 unneback
 
896 40 unneback
`ifdef DFF_ARRAY
897
`define MODULE dff_array
898
module `BASE`MODULE ( d, q, clk, rst);
899
`undef MODULE
900 6 unneback
 
901
        parameter width = 1;
902
        parameter depth = 2;
903
        parameter reset_value = 1'b0;
904
 
905
        input [width-1:0] d;
906
        input clk, rst;
907
        output [width-1:0] q;
908
        reg  [0:depth-1] q_tmp [width-1:0];
909
        integer i;
910
        always @ (posedge clk or posedge rst)
911
        if (rst) begin
912
            for (i=0;i<depth;i=i+1)
913
                q_tmp[i] <= {width{reset_value}};
914
        end else begin
915
            q_tmp[0] <= d;
916
            for (i=1;i<depth;i=i+1)
917
                q_tmp[i] <= q_tmp[i-1];
918
        end
919
 
920
    assign q = q_tmp[depth-1];
921
 
922
endmodule
923 40 unneback
`endif
924 6 unneback
 
925 40 unneback
`ifdef DFF_CE
926
`define MODULE dff_ce
927
module `BASE`MODULE ( d, ce, q, clk, rst);
928
`undef MODULE
929 6 unneback
 
930
        parameter width = 1;
931 139 unneback
        parameter reset_value = {width{1'b0}};
932 6 unneback
 
933
        input [width-1:0] d;
934
        input ce, clk, rst;
935
        output reg [width-1:0] q;
936
 
937
        always @ (posedge clk or posedge rst)
938
        if (rst)
939
                q <= reset_value;
940
        else
941
                if (ce)
942
                        q <= d;
943
 
944
endmodule
945 40 unneback
`endif
946 6 unneback
 
947 40 unneback
`ifdef DFF_CE_CLEAR
948
`define MODULE dff_ce_clear
949
module `BASE`MODULE ( d, ce, clear, q, clk, rst);
950
`undef MODULE
951 8 unneback
 
952
        parameter width = 1;
953 139 unneback
        parameter reset_value = {width{1'b0}};
954 8 unneback
 
955
        input [width-1:0] d;
956 10 unneback
        input ce, clear, clk, rst;
957 8 unneback
        output reg [width-1:0] q;
958
 
959
        always @ (posedge clk or posedge rst)
960
        if (rst)
961
            q <= reset_value;
962
        else
963
            if (ce)
964
                if (clear)
965
                    q <= {width{1'b0}};
966
                else
967
                    q <= d;
968
 
969
endmodule
970 40 unneback
`endif
971 8 unneback
 
972 40 unneback
`ifdef DF_CE_SET
973
`define MODULE dff_ce_set
974
module `BASE`MODULE ( d, ce, set, q, clk, rst);
975
`undef MODULE
976 24 unneback
 
977
        parameter width = 1;
978 139 unneback
        parameter reset_value = {width{1'b0}};
979 24 unneback
 
980
        input [width-1:0] d;
981
        input ce, set, clk, rst;
982
        output reg [width-1:0] q;
983
 
984
        always @ (posedge clk or posedge rst)
985
        if (rst)
986
            q <= reset_value;
987
        else
988
            if (ce)
989
                if (set)
990
                    q <= {width{1'b1}};
991
                else
992
                    q <= d;
993
 
994
endmodule
995 40 unneback
`endif
996 24 unneback
 
997 40 unneback
`ifdef SPR
998
`define MODULE spr
999
module `BASE`MODULE ( sp, r, q, clk, rst);
1000
`undef MODULE
1001
 
1002 64 unneback
        //parameter width = 1;
1003
        parameter reset_value = 1'b0;
1004 29 unneback
 
1005
        input sp, r;
1006
        output reg q;
1007
        input clk, rst;
1008
 
1009
        always @ (posedge clk or posedge rst)
1010
        if (rst)
1011
            q <= reset_value;
1012
        else
1013
            if (sp)
1014
                q <= 1'b1;
1015
            else if (r)
1016
                q <= 1'b0;
1017
 
1018
endmodule
1019 40 unneback
`endif
1020 29 unneback
 
1021 40 unneback
`ifdef SRP
1022
`define MODULE srp
1023
module `BASE`MODULE ( s, rp, q, clk, rst);
1024
`undef MODULE
1025
 
1026 29 unneback
        parameter width = 1;
1027
        parameter reset_value = 0;
1028
 
1029
        input s, rp;
1030
        output reg q;
1031
        input clk, rst;
1032
 
1033
        always @ (posedge clk or posedge rst)
1034
        if (rst)
1035
            q <= reset_value;
1036
        else
1037
            if (rp)
1038
                q <= 1'b0;
1039
            else if (s)
1040
                q <= 1'b1;
1041
 
1042
endmodule
1043 40 unneback
`endif
1044 29 unneback
 
1045 40 unneback
`ifdef ALTERA
1046 29 unneback
 
1047 40 unneback
`ifdef DFF_SR
1048 6 unneback
// megafunction wizard: %LPM_FF%
1049
// GENERATION: STANDARD
1050
// VERSION: WM1.0
1051
// MODULE: lpm_ff 
1052
 
1053
// ============================================================
1054
// File Name: dff_sr.v
1055
// Megafunction Name(s):
1056
//                      lpm_ff
1057
//
1058
// Simulation Library Files(s):
1059
//                      lpm
1060
// ============================================================
1061
// ************************************************************
1062
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
1063
//
1064
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
1065
// ************************************************************
1066
 
1067
 
1068
//Copyright (C) 1991-2010 Altera Corporation
1069
//Your use of Altera Corporation's design tools, logic functions 
1070
//and other software and tools, and its AMPP partner logic 
1071
//functions, and any output files from any of the foregoing 
1072
//(including device programming or simulation files), and any 
1073
//associated documentation or information are expressly subject 
1074
//to the terms and conditions of the Altera Program License 
1075
//Subscription Agreement, Altera MegaCore Function License 
1076
//Agreement, or other applicable license agreement, including, 
1077
//without limitation, that your use is for the sole purpose of 
1078
//programming logic devices manufactured by Altera and sold by 
1079
//Altera or its authorized distributors.  Please refer to the 
1080
//applicable agreement for further details.
1081
 
1082
 
1083
// synopsys translate_off
1084
`timescale 1 ps / 1 ps
1085
// synopsys translate_on
1086 40 unneback
`define MODULE dff_sr
1087
module `BASE`MODULE (
1088
`undef MODULE
1089
 
1090 6 unneback
        aclr,
1091
        aset,
1092
        clock,
1093
        data,
1094
        q);
1095
 
1096
        input     aclr;
1097
        input     aset;
1098
        input     clock;
1099
        input     data;
1100
        output    q;
1101
 
1102
        wire [0:0] sub_wire0;
1103
        wire [0:0] sub_wire1 = sub_wire0[0:0];
1104
        wire  q = sub_wire1;
1105
        wire  sub_wire2 = data;
1106
        wire  sub_wire3 = sub_wire2;
1107
 
1108
        lpm_ff  lpm_ff_component (
1109
                                .aclr (aclr),
1110
                                .clock (clock),
1111
                                .data (sub_wire3),
1112
                                .aset (aset),
1113
                                .q (sub_wire0)
1114
                                // synopsys translate_off
1115
                                ,
1116
                                .aload (),
1117
                                .enable (),
1118
                                .sclr (),
1119
                                .sload (),
1120
                                .sset ()
1121
                                // synopsys translate_on
1122
                                );
1123
        defparam
1124
                lpm_ff_component.lpm_fftype = "DFF",
1125
                lpm_ff_component.lpm_type = "LPM_FF",
1126
                lpm_ff_component.lpm_width = 1;
1127
 
1128
 
1129
endmodule
1130
 
1131
// ============================================================
1132
// CNX file retrieval info
1133
// ============================================================
1134
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
1135
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
1136
// Retrieval info: PRIVATE: ASET NUMERIC "1"
1137
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
1138
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
1139
// Retrieval info: PRIVATE: DFF NUMERIC "1"
1140
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
1141
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
1142
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
1143
// Retrieval info: PRIVATE: SSET NUMERIC "0"
1144
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
1145
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
1146
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
1147
// Retrieval info: PRIVATE: nBit NUMERIC "1"
1148
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
1149
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
1150
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
1151
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
1152
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
1153
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
1154
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
1155
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
1156
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
1157
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
1158
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
1159
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
1160
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
1161
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
1162
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
1163
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
1164
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
1165
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
1166
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
1167
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
1168
// Retrieval info: LIB_FILE: lpm
1169 40 unneback
`endif
1170 6 unneback
 
1171
`else
1172
 
1173 40 unneback
`ifdef DFF_SR
1174
`define MODULE dff_sr
1175
module `BASE`MODULE ( aclr, aset, clock, data, q);
1176
`undef MODULE
1177 6 unneback
 
1178
    input         aclr;
1179
    input         aset;
1180
    input         clock;
1181
    input         data;
1182
    output reg    q;
1183
 
1184
   always @ (posedge clock or posedge aclr or posedge aset)
1185
     if (aclr)
1186
       q <= 1'b0;
1187
     else if (aset)
1188
       q <= 1'b1;
1189
     else
1190
       q <= data;
1191
 
1192
endmodule
1193 40 unneback
`endif
1194 6 unneback
 
1195
`endif
1196
 
1197
// LATCH
1198
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
1199
`ifdef ALTERA
1200 40 unneback
 
1201
`ifdef LATCH
1202
`define MODULE latch
1203
module `BASE`MODULE ( d, le, q, clk);
1204
`undef MODULE
1205 6 unneback
input d, le;
1206
output q;
1207
input clk;
1208
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
1209
endmodule
1210 40 unneback
`endif
1211
 
1212 6 unneback
`else
1213 40 unneback
 
1214
`ifdef LATCH
1215
`define MODULE latch
1216
module `BASE`MODULE ( d, le, q, clk);
1217
`undef MODULE
1218 6 unneback
input d, le;
1219 48 unneback
input clk;
1220
always @ (le or d)
1221 60 unneback
if (le)
1222 48 unneback
    d <= q;
1223 6 unneback
endmodule
1224 15 unneback
`endif
1225
 
1226 40 unneback
`endif
1227
 
1228
`ifdef SHREG
1229
`define MODULE shreg
1230
module `BASE`MODULE ( d, q, clk, rst);
1231
`undef MODULE
1232
 
1233 17 unneback
parameter depth = 10;
1234
input d;
1235
output q;
1236
input clk, rst;
1237
 
1238
reg [1:depth] dffs;
1239
 
1240
always @ (posedge clk or posedge rst)
1241
if (rst)
1242
    dffs <= {depth{1'b0}};
1243
else
1244
    dffs <= {d,dffs[1:depth-1]};
1245
assign q = dffs[depth];
1246
endmodule
1247 40 unneback
`endif
1248 17 unneback
 
1249 40 unneback
`ifdef SHREG_CE
1250
`define MODULE shreg_ce
1251
module `BASE`MODULE ( d, ce, q, clk, rst);
1252
`undef MODULE
1253 17 unneback
parameter depth = 10;
1254
input d, ce;
1255
output q;
1256
input clk, rst;
1257
 
1258
reg [1:depth] dffs;
1259
 
1260
always @ (posedge clk or posedge rst)
1261
if (rst)
1262
    dffs <= {depth{1'b0}};
1263
else
1264
    if (ce)
1265
        dffs <= {d,dffs[1:depth-1]};
1266
assign q = dffs[depth];
1267
endmodule
1268 40 unneback
`endif
1269 17 unneback
 
1270 40 unneback
`ifdef DELAY
1271
`define MODULE delay
1272
module `BASE`MODULE ( d, q, clk, rst);
1273
`undef MODULE
1274 15 unneback
parameter depth = 10;
1275
input d;
1276
output q;
1277
input clk, rst;
1278
 
1279
reg [1:depth] dffs;
1280
 
1281
always @ (posedge clk or posedge rst)
1282
if (rst)
1283
    dffs <= {depth{1'b0}};
1284
else
1285
    dffs <= {d,dffs[1:depth-1]};
1286
assign q = dffs[depth];
1287 17 unneback
endmodule
1288 40 unneback
`endif
1289 17 unneback
 
1290 40 unneback
`ifdef DELAY_EMPTYFLAG
1291
`define MODULE delay_emptyflag
1292 41 unneback
module `BASE`MODULE ( d, q, emptyflag, clk, rst);
1293 40 unneback
`undef MODULE
1294 17 unneback
parameter depth = 10;
1295
input d;
1296
output q, emptyflag;
1297
input clk, rst;
1298
 
1299
reg [1:depth] dffs;
1300
 
1301
always @ (posedge clk or posedge rst)
1302
if (rst)
1303
    dffs <= {depth{1'b0}};
1304
else
1305
    dffs <= {d,dffs[1:depth-1]};
1306
assign q = dffs[depth];
1307
assign emptyflag = !(|dffs);
1308
endmodule
1309 40 unneback
`endif
1310 75 unneback
 
1311 94 unneback
`ifdef PULSE2TOGGLE
1312 98 unneback
`define MODULE pulse2toggle
1313
module `BASE`MODULE ( pl, q, clk, rst);
1314 75 unneback
`undef MODULE
1315 94 unneback
input pl;
1316 98 unneback
output reg q;
1317 94 unneback
input clk, rst;
1318
always @ (posedge clk or posedge rst)
1319 75 unneback
if (rst)
1320 94 unneback
    q <= 1'b0;
1321 75 unneback
else
1322 94 unneback
    q <= pl ^ q;
1323
endmodule
1324
`endif
1325 75 unneback
 
1326 94 unneback
`ifdef TOGGLE2PULSE
1327 98 unneback
`define MODULE toggle2pulse
1328 94 unneback
module `BASE`MODULE (d, pl, clk, rst);
1329 97 unneback
`undef MODULE
1330 94 unneback
input d;
1331
output pl;
1332
input clk, rst;
1333
reg dff;
1334
always @ (posedge clk or posedge rst)
1335
if (rst)
1336
    dff <= 1'b0;
1337 75 unneback
else
1338 94 unneback
    dff <= d;
1339 98 unneback
assign pl = d ^ dff;
1340 94 unneback
endmodule
1341
`endif
1342 75 unneback
 
1343 94 unneback
`ifdef SYNCHRONIZER
1344
`define MODULE synchronizer
1345
module `BASE`MODULE (d, q, clk, rst);
1346
`undef MODULE
1347
input d;
1348
output reg q;
1349 116 unneback
input clk, rst;
1350 94 unneback
reg dff;
1351
always @ (posedge clk or posedge rst)
1352
if (rst)
1353 100 unneback
    {q,dff} <= 2'b00;
1354 75 unneback
else
1355 100 unneback
    {q,dff} <= {dff,d};
1356 94 unneback
endmodule
1357
`endif
1358 75 unneback
 
1359 94 unneback
`ifdef CDC
1360
`define MODULE cdc
1361 97 unneback
module `BASE`MODULE ( start_pl, take_it_pl, take_it_grant_pl, got_it_pl, clk_src, rst_src, clk_dst, rst_dst);
1362 94 unneback
`undef MODULE
1363
input start_pl;
1364
output take_it_pl;
1365
input take_it_grant_pl; // note: connect to take_it_pl to generate automatic ack
1366
output got_it_pl;
1367
input clk_src, rst_src;
1368
input clk_dst, rst_dst;
1369
wire take_it_tg, take_it_tg_sync;
1370
wire got_it_tg, got_it_tg_sync;
1371
// src -> dst
1372
`define MODULE pulse2toggle
1373
`BASE`MODULE p2t0 (
1374
`undef MODULE
1375
    .pl(start_pl),
1376
    .q(take_it_tg),
1377
    .clk(clk_src),
1378
    .rst(rst_src));
1379 75 unneback
 
1380 94 unneback
`define MODULE synchronizer
1381
`BASE`MODULE sync0 (
1382
`undef MODULE
1383
    .d(take_it_tg),
1384
    .q(take_it_tg_sync),
1385
    .clk(clk_dst),
1386
    .rst(rst_dst));
1387
 
1388
`define MODULE toggle2pulse
1389
`BASE`MODULE t2p0 (
1390
`undef MODULE
1391 100 unneback
    .d(take_it_tg_sync),
1392 94 unneback
    .pl(take_it_pl),
1393
    .clk(clk_dst),
1394
    .rst(rst_dst));
1395
 
1396
// dst -> src
1397
`define MODULE pulse2toggle
1398 98 unneback
`BASE`MODULE p2t1 (
1399 94 unneback
`undef MODULE
1400
    .pl(take_it_grant_pl),
1401
    .q(got_it_tg),
1402
    .clk(clk_dst),
1403
    .rst(rst_dst));
1404
 
1405
`define MODULE synchronizer
1406
`BASE`MODULE sync1 (
1407
`undef MODULE
1408
    .d(got_it_tg),
1409
    .q(got_it_tg_sync),
1410
    .clk(clk_src),
1411
    .rst(rst_src));
1412
 
1413
`define MODULE toggle2pulse
1414
`BASE`MODULE t2p1 (
1415
`undef MODULE
1416 100 unneback
    .d(got_it_tg_sync),
1417 94 unneback
    .pl(got_it_pl),
1418
    .clk(clk_src),
1419
    .rst(rst_src));
1420
 
1421 75 unneback
endmodule
1422
`endif
1423 17 unneback
//////////////////////////////////////////////////////////////////////
1424 6 unneback
////                                                              ////
1425 18 unneback
////  Logic functions                                             ////
1426
////                                                              ////
1427
////  Description                                                 ////
1428
////  Logic functions such as multiplexers                        ////
1429
////                                                              ////
1430
////                                                              ////
1431
////  To Do:                                                      ////
1432
////   -                                                          ////
1433
////                                                              ////
1434
////  Author(s):                                                  ////
1435
////      - Michael Unneback, unneback@opencores.org              ////
1436
////        ORSoC AB                                              ////
1437
////                                                              ////
1438
//////////////////////////////////////////////////////////////////////
1439
////                                                              ////
1440
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1441
////                                                              ////
1442
//// This source file may be used and distributed without         ////
1443
//// restriction provided that this copyright statement is not    ////
1444
//// removed from the file and that any derivative work contains  ////
1445
//// the original copyright notice and the associated disclaimer. ////
1446
////                                                              ////
1447
//// This source file is free software; you can redistribute it   ////
1448
//// and/or modify it under the terms of the GNU Lesser General   ////
1449
//// Public License as published by the Free Software Foundation; ////
1450
//// either version 2.1 of the License, or (at your option) any   ////
1451
//// later version.                                               ////
1452
////                                                              ////
1453
//// This source is distributed in the hope that it will be       ////
1454
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1455
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1456
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1457
//// details.                                                     ////
1458
////                                                              ////
1459
//// You should have received a copy of the GNU Lesser General    ////
1460
//// Public License along with this source; if not, download it   ////
1461
//// from http://www.opencores.org/lgpl.shtml                     ////
1462
////                                                              ////
1463
//////////////////////////////////////////////////////////////////////
1464 40 unneback
`ifdef MUX_ANDOR
1465
`define MODULE mux_andor
1466
module `BASE`MODULE ( a, sel, dout);
1467
`undef MODULE
1468 36 unneback
 
1469
parameter width = 32;
1470
parameter nr_of_ports = 4;
1471
 
1472
input [nr_of_ports*width-1:0] a;
1473
input [nr_of_ports-1:0] sel;
1474
output reg [width-1:0] dout;
1475
 
1476 38 unneback
integer i,j;
1477
 
1478 36 unneback
always @ (a, sel)
1479
begin
1480
    dout = a[width-1:0] & {width{sel[0]}};
1481 42 unneback
    for (i=1;i<nr_of_ports;i=i+1)
1482
        for (j=0;j<width;j=j+1)
1483
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
1484 36 unneback
end
1485
 
1486
endmodule
1487 40 unneback
`endif
1488 36 unneback
 
1489 40 unneback
`ifdef MUX2_ANDOR
1490
`define MODULE mux2_andor
1491
module `BASE`MODULE ( a1, a0, sel, dout);
1492
`undef MODULE
1493 18 unneback
 
1494 34 unneback
parameter width = 32;
1495 35 unneback
localparam nr_of_ports = 2;
1496 34 unneback
input [width-1:0] a1, a0;
1497
input [nr_of_ports-1:0] sel;
1498
output [width-1:0] dout;
1499
 
1500 40 unneback
`define MODULE mux_andor
1501
`BASE`MODULE
1502 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1503 36 unneback
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
1504 40 unneback
`undef MODULE
1505
 
1506 34 unneback
endmodule
1507 40 unneback
`endif
1508 34 unneback
 
1509 40 unneback
`ifdef MUX3_ANDOR
1510
`define MODULE mux3_andor
1511
module `BASE`MODULE ( a2, a1, a0, sel, dout);
1512
`undef MODULE
1513 34 unneback
 
1514
parameter width = 32;
1515 35 unneback
localparam nr_of_ports = 3;
1516 34 unneback
input [width-1:0] a2, a1, a0;
1517
input [nr_of_ports-1:0] sel;
1518
output [width-1:0] dout;
1519
 
1520 40 unneback
`define MODULE mux_andor
1521
`BASE`MODULE
1522 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1523 36 unneback
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
1524 40 unneback
`undef MODULE
1525 34 unneback
endmodule
1526 40 unneback
`endif
1527 34 unneback
 
1528 40 unneback
`ifdef MUX4_ANDOR
1529
`define MODULE mux4_andor
1530
module `BASE`MODULE ( a3, a2, a1, a0, sel, dout);
1531
`undef MODULE
1532 18 unneback
 
1533
parameter width = 32;
1534 35 unneback
localparam nr_of_ports = 4;
1535 18 unneback
input [width-1:0] a3, a2, a1, a0;
1536
input [nr_of_ports-1:0] sel;
1537 22 unneback
output [width-1:0] dout;
1538 18 unneback
 
1539 40 unneback
`define MODULE mux_andor
1540
`BASE`MODULE
1541 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1542 36 unneback
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
1543 40 unneback
`undef MODULE
1544 18 unneback
 
1545
endmodule
1546 40 unneback
`endif
1547 18 unneback
 
1548 40 unneback
`ifdef MUX5_ANDOR
1549
`define MODULE mux5_andor
1550
module `BASE`MODULE ( a4, a3, a2, a1, a0, sel, dout);
1551
`undef MODULE
1552 18 unneback
 
1553
parameter width = 32;
1554 35 unneback
localparam nr_of_ports = 5;
1555 18 unneback
input [width-1:0] a4, a3, a2, a1, a0;
1556
input [nr_of_ports-1:0] sel;
1557 22 unneback
output [width-1:0] dout;
1558 18 unneback
 
1559 40 unneback
`define MODULE mux_andor
1560
`BASE`MODULE
1561 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1562 36 unneback
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1563 40 unneback
`undef MODULE
1564 18 unneback
 
1565
endmodule
1566 40 unneback
`endif
1567 18 unneback
 
1568 40 unneback
`ifdef MUX6_ANDOR
1569
`define MODULE mux6_andor
1570
module `BASE`MODULE ( a5, a4, a3, a2, a1, a0, sel, dout);
1571
`undef MODULE
1572 18 unneback
 
1573
parameter width = 32;
1574 35 unneback
localparam nr_of_ports = 6;
1575 18 unneback
input [width-1:0] a5, a4, a3, a2, a1, a0;
1576
input [nr_of_ports-1:0] sel;
1577 22 unneback
output [width-1:0] dout;
1578 18 unneback
 
1579 40 unneback
`define MODULE mux_andor
1580
`BASE`MODULE
1581 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1582 36 unneback
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1583 40 unneback
`undef MODULE
1584 18 unneback
 
1585
endmodule
1586 40 unneback
`endif
1587 43 unneback
 
1588
`ifdef PARITY
1589
 
1590
`define MODULE parity_generate
1591
module `BASE`MODULE (data, parity);
1592
`undef MODULE
1593
parameter word_size = 32;
1594
parameter chunk_size = 8;
1595
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1596
input [word_size-1:0] data;
1597
output reg [word_size/chunk_size-1:0] parity;
1598
integer i,j;
1599
always @ (data)
1600
for (i=0;i<word_size/chunk_size;i=i+1) begin
1601
    parity[i] = parity_type;
1602
    for (j=0;j<chunk_size;j=j+1) begin
1603 46 unneback
        parity[i] = data[i*chunk_size+j] ^ parity[i];
1604 43 unneback
    end
1605
end
1606
endmodule
1607
 
1608
`define MODULE parity_check
1609
module `BASE`MODULE( data, parity, parity_error);
1610
`undef MODULE
1611
parameter word_size = 32;
1612
parameter chunk_size = 8;
1613
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1614
input [word_size-1:0] data;
1615
input [word_size/chunk_size-1:0] parity;
1616
output parity_error;
1617 44 unneback
reg [word_size/chunk_size-1:0] error_flag;
1618 43 unneback
integer i,j;
1619
always @ (data or parity)
1620
for (i=0;i<word_size/chunk_size;i=i+1) begin
1621
    error_flag[i] = parity[i] ^ parity_type;
1622
    for (j=0;j<chunk_size;j=j+1) begin
1623 46 unneback
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
1624 43 unneback
    end
1625
end
1626
assign parity_error = |error_flag;
1627
endmodule
1628
 
1629 44 unneback
`endif//////////////////////////////////////////////////////////////////////
1630
////                                                              ////
1631
////  IO functions                                                ////
1632
////                                                              ////
1633
////  Description                                                 ////
1634
////  IO functions such as IOB flip-flops                         ////
1635
////                                                              ////
1636
////                                                              ////
1637
////  To Do:                                                      ////
1638
////   -                                                          ////
1639
////                                                              ////
1640
////  Author(s):                                                  ////
1641
////      - Michael Unneback, unneback@opencores.org              ////
1642
////        ORSoC AB                                              ////
1643
////                                                              ////
1644 18 unneback
//////////////////////////////////////////////////////////////////////
1645
////                                                              ////
1646 44 unneback
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1647
////                                                              ////
1648
//// This source file may be used and distributed without         ////
1649
//// restriction provided that this copyright statement is not    ////
1650
//// removed from the file and that any derivative work contains  ////
1651
//// the original copyright notice and the associated disclaimer. ////
1652
////                                                              ////
1653
//// This source file is free software; you can redistribute it   ////
1654
//// and/or modify it under the terms of the GNU Lesser General   ////
1655
//// Public License as published by the Free Software Foundation; ////
1656
//// either version 2.1 of the License, or (at your option) any   ////
1657
//// later version.                                               ////
1658
////                                                              ////
1659
//// This source is distributed in the hope that it will be       ////
1660
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1661
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1662
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1663
//// details.                                                     ////
1664
////                                                              ////
1665
//// You should have received a copy of the GNU Lesser General    ////
1666
//// Public License along with this source; if not, download it   ////
1667
//// from http://www.opencores.org/lgpl.shtml                     ////
1668
////                                                              ////
1669
//////////////////////////////////////////////////////////////////////
1670 136 unneback
`ifdef O_DFF
1671 45 unneback
`timescale 1ns/1ns
1672 44 unneback
`define MODULE o_dff
1673
module `BASE`MODULE (d_i, o_pad, clk, rst);
1674
`undef MODULE
1675
parameter width = 1;
1676 45 unneback
parameter reset_value = {width{1'b0}};
1677
input  [width-1:0]  d_i;
1678 44 unneback
output [width-1:0] o_pad;
1679
input clk, rst;
1680
wire [width-1:0] d_i_int `SYN_KEEP;
1681 45 unneback
reg  [width-1:0] o_pad_int;
1682 44 unneback
assign d_i_int = d_i;
1683
genvar i;
1684 45 unneback
generate
1685 136 unneback
for (i=0;i<width;i=i+1) begin : dffs
1686 44 unneback
    always @ (posedge clk or posedge rst)
1687
    if (rst)
1688 45 unneback
        o_pad_int[i] <= reset_value[i];
1689 44 unneback
    else
1690 45 unneback
        o_pad_int[i] <= d_i_int[i];
1691
    assign #1 o_pad[i] = o_pad_int[i];
1692 44 unneback
end
1693
endgenerate
1694
endmodule
1695
`endif
1696
 
1697 136 unneback
`ifdef IO_DFF_OE
1698 45 unneback
`timescale 1ns/1ns
1699 44 unneback
`define MODULE io_dff_oe
1700
module `BASE`MODULE ( d_i, d_o, oe, io_pad, clk, rst);
1701
`undef MODULE
1702
parameter width = 1;
1703 140 unneback
parameter reset_value = 1'b0;
1704 44 unneback
input  [width-1:0] d_o;
1705
output reg [width-1:0] d_i;
1706
input oe;
1707
inout [width-1:0] io_pad;
1708
input clk, rst;
1709
wire [width-1:0] oe_d `SYN_KEEP;
1710
reg [width-1:0] oe_q;
1711
reg [width-1:0] d_o_q;
1712
assign oe_d = {width{oe}};
1713
genvar i;
1714
generate
1715 136 unneback
for (i=0;i<width;i=i+1) begin : dffs
1716 44 unneback
    always @ (posedge clk or posedge rst)
1717
    if (rst)
1718
        oe_q[i] <= 1'b0;
1719
    else
1720
        oe_q[i] <= oe_d[i];
1721
    always @ (posedge clk or posedge rst)
1722
    if (rst)
1723 140 unneback
        d_o_q[i] <= reset_value;
1724 44 unneback
    else
1725
        d_o_q[i] <= d_o[i];
1726
    always @ (posedge clk or posedge rst)
1727
    if (rst)
1728 140 unneback
        d_i[i] <= reset_value;
1729 44 unneback
    else
1730
        d_i[i] <= io_pad[i];
1731 45 unneback
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
1732 44 unneback
end
1733
endgenerate
1734
endmodule
1735
`endif
1736 136 unneback
 
1737
`ifdef O_DDR
1738
`ifdef ALTERA
1739
`define MODULE o_ddr
1740
module `BASE`MODULE (d_h_i, d_l_i, o_pad, clk, rst);
1741
`undef MODULE
1742
parameter width = 1;
1743
input  [width-1:0] d_h_i, d_l_i;
1744
output [width-1:0] o_pad;
1745
input clk, rst;
1746
genvar i;
1747
generate
1748
for (i=0;i<width;i=i+1) begin : ddr
1749
    ddio_out ddio_out0( .aclr(rst), .datain_h(d_h_i[i]), .datain_l(d_l_i[i]), .outclock(clk), .dataout(o_pad[i]) );
1750
end
1751
endgenerate
1752
endmodule
1753
`else
1754
`define MODULE o_ddr
1755
module `BASE`MODULE (d_h_i, d_l_i, o_pad, clk, rst);
1756
`undef MODULE
1757
parameter width = 1;
1758
input  [width-1:0] d_h_i, d_l_i;
1759
output [width-1:0] o_pad;
1760
input clk, rst;
1761
reg [width-1:0] ff1;
1762
reg [width-1:0] ff2;
1763
genvar i;
1764
generate
1765
for (i=0;i<width;i=i+1) begin : ddr
1766
    always @ (posedge clk or posedge rst)
1767
    if (rst)
1768
        ff1[i] <= 1'b0;
1769
    else
1770
        ff1[i] <= d_h_i[i];
1771
    always @ (posedge clk or posedge rst)
1772
    if (rst)
1773
        ff2[i] <= 1'b0;
1774
    else
1775
        ff2[i] <= d_l_i[i];
1776
    assign o_pad = (clk) ? ff1 : ff2;
1777
end
1778
endgenerate
1779
endmodule
1780
`endif
1781
`endif
1782
 
1783
`ifdef O_CLK
1784
`define MODULE o_clk
1785
module `BASE`MODULE ( clk_o_pad, clk, rst);
1786
`undef MODULE
1787
input clk, rst;
1788
output clk_o_pad;
1789
`define MODULE o_ddr
1790
`BASE`MODULE o_ddr0( .d_h_i(1'b1), .d_l_i(1'b0), .o_pad(clk_o_pad), .clk(clk), .rst(rst));
1791
`undef MODULE
1792
endmodule
1793
`endif`ifdef CNT_BIN
1794 44 unneback
//////////////////////////////////////////////////////////////////////
1795
////                                                              ////
1796 6 unneback
////  Versatile counter                                           ////
1797
////                                                              ////
1798
////  Description                                                 ////
1799
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1800
////  counter                                                     ////
1801
////                                                              ////
1802
////  To Do:                                                      ////
1803
////   - add LFSR with more taps                                  ////
1804
////                                                              ////
1805
////  Author(s):                                                  ////
1806
////      - Michael Unneback, unneback@opencores.org              ////
1807
////        ORSoC AB                                              ////
1808
////                                                              ////
1809
//////////////////////////////////////////////////////////////////////
1810
////                                                              ////
1811
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1812
////                                                              ////
1813
//// This source file may be used and distributed without         ////
1814
//// restriction provided that this copyright statement is not    ////
1815
//// removed from the file and that any derivative work contains  ////
1816
//// the original copyright notice and the associated disclaimer. ////
1817
////                                                              ////
1818
//// This source file is free software; you can redistribute it   ////
1819
//// and/or modify it under the terms of the GNU Lesser General   ////
1820
//// Public License as published by the Free Software Foundation; ////
1821
//// either version 2.1 of the License, or (at your option) any   ////
1822
//// later version.                                               ////
1823
////                                                              ////
1824
//// This source is distributed in the hope that it will be       ////
1825
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1826
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1827
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1828
//// details.                                                     ////
1829
////                                                              ////
1830
//// You should have received a copy of the GNU Lesser General    ////
1831
//// Public License along with this source; if not, download it   ////
1832
//// from http://www.opencores.org/lgpl.shtml                     ////
1833
////                                                              ////
1834
//////////////////////////////////////////////////////////////////////
1835
 
1836
// binary counter
1837 22 unneback
 
1838 40 unneback
`define MODULE cnt_bin
1839
module `BASE`MODULE (
1840
`undef MODULE
1841
 q, rst, clk);
1842
 
1843 22 unneback
   parameter length = 4;
1844
   output [length:1] q;
1845
   input rst;
1846
   input clk;
1847
 
1848
   parameter clear_value = 0;
1849
   parameter set_value = 1;
1850
   parameter wrap_value = 0;
1851
   parameter level1_value = 15;
1852
 
1853
   reg  [length:1] qi;
1854
   wire [length:1] q_next;
1855
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1856
 
1857
   always @ (posedge clk or posedge rst)
1858
     if (rst)
1859
       qi <= {length{1'b0}};
1860
     else
1861
       qi <= q_next;
1862
 
1863
   assign q = qi;
1864
 
1865
endmodule
1866 40 unneback
`endif
1867
`ifdef CNT_BIN_CLEAR
1868 22 unneback
//////////////////////////////////////////////////////////////////////
1869
////                                                              ////
1870
////  Versatile counter                                           ////
1871
////                                                              ////
1872
////  Description                                                 ////
1873
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1874
////  counter                                                     ////
1875
////                                                              ////
1876
////  To Do:                                                      ////
1877
////   - add LFSR with more taps                                  ////
1878
////                                                              ////
1879
////  Author(s):                                                  ////
1880
////      - Michael Unneback, unneback@opencores.org              ////
1881
////        ORSoC AB                                              ////
1882
////                                                              ////
1883
//////////////////////////////////////////////////////////////////////
1884
////                                                              ////
1885
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1886
////                                                              ////
1887
//// This source file may be used and distributed without         ////
1888
//// restriction provided that this copyright statement is not    ////
1889
//// removed from the file and that any derivative work contains  ////
1890
//// the original copyright notice and the associated disclaimer. ////
1891
////                                                              ////
1892
//// This source file is free software; you can redistribute it   ////
1893
//// and/or modify it under the terms of the GNU Lesser General   ////
1894
//// Public License as published by the Free Software Foundation; ////
1895
//// either version 2.1 of the License, or (at your option) any   ////
1896
//// later version.                                               ////
1897
////                                                              ////
1898
//// This source is distributed in the hope that it will be       ////
1899
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1900
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1901
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1902
//// details.                                                     ////
1903
////                                                              ////
1904
//// You should have received a copy of the GNU Lesser General    ////
1905
//// Public License along with this source; if not, download it   ////
1906
//// from http://www.opencores.org/lgpl.shtml                     ////
1907
////                                                              ////
1908
//////////////////////////////////////////////////////////////////////
1909
 
1910
// binary counter
1911
 
1912 40 unneback
`define MODULE cnt_bin_clear
1913
module `BASE`MODULE (
1914
`undef MODULE
1915
 clear, q, rst, clk);
1916
 
1917 22 unneback
   parameter length = 4;
1918
   input clear;
1919
   output [length:1] q;
1920
   input rst;
1921
   input clk;
1922
 
1923
   parameter clear_value = 0;
1924
   parameter set_value = 1;
1925
   parameter wrap_value = 0;
1926
   parameter level1_value = 15;
1927
 
1928
   reg  [length:1] qi;
1929
   wire [length:1] q_next;
1930
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1931
 
1932
   always @ (posedge clk or posedge rst)
1933
     if (rst)
1934
       qi <= {length{1'b0}};
1935
     else
1936
       qi <= q_next;
1937
 
1938
   assign q = qi;
1939
 
1940
endmodule
1941 40 unneback
`endif
1942
`ifdef CNT_BIN_CE
1943 22 unneback
//////////////////////////////////////////////////////////////////////
1944
////                                                              ////
1945
////  Versatile counter                                           ////
1946
////                                                              ////
1947
////  Description                                                 ////
1948
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1949
////  counter                                                     ////
1950
////                                                              ////
1951
////  To Do:                                                      ////
1952
////   - add LFSR with more taps                                  ////
1953
////                                                              ////
1954
////  Author(s):                                                  ////
1955
////      - Michael Unneback, unneback@opencores.org              ////
1956
////        ORSoC AB                                              ////
1957
////                                                              ////
1958
//////////////////////////////////////////////////////////////////////
1959
////                                                              ////
1960
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1961
////                                                              ////
1962
//// This source file may be used and distributed without         ////
1963
//// restriction provided that this copyright statement is not    ////
1964
//// removed from the file and that any derivative work contains  ////
1965
//// the original copyright notice and the associated disclaimer. ////
1966
////                                                              ////
1967
//// This source file is free software; you can redistribute it   ////
1968
//// and/or modify it under the terms of the GNU Lesser General   ////
1969
//// Public License as published by the Free Software Foundation; ////
1970
//// either version 2.1 of the License, or (at your option) any   ////
1971
//// later version.                                               ////
1972
////                                                              ////
1973
//// This source is distributed in the hope that it will be       ////
1974
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1975
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1976
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1977
//// details.                                                     ////
1978
////                                                              ////
1979
//// You should have received a copy of the GNU Lesser General    ////
1980
//// Public License along with this source; if not, download it   ////
1981
//// from http://www.opencores.org/lgpl.shtml                     ////
1982
////                                                              ////
1983
//////////////////////////////////////////////////////////////////////
1984
 
1985
// binary counter
1986 6 unneback
 
1987 40 unneback
`define MODULE cnt_bin_ce
1988
module `BASE`MODULE (
1989
`undef MODULE
1990
 cke, q, rst, clk);
1991
 
1992 6 unneback
   parameter length = 4;
1993
   input cke;
1994
   output [length:1] q;
1995
   input rst;
1996
   input clk;
1997
 
1998
   parameter clear_value = 0;
1999
   parameter set_value = 1;
2000
   parameter wrap_value = 0;
2001
   parameter level1_value = 15;
2002
 
2003
   reg  [length:1] qi;
2004
   wire [length:1] q_next;
2005
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2006
 
2007
   always @ (posedge clk or posedge rst)
2008
     if (rst)
2009
       qi <= {length{1'b0}};
2010
     else
2011
     if (cke)
2012
       qi <= q_next;
2013
 
2014
   assign q = qi;
2015
 
2016
endmodule
2017 40 unneback
`endif
2018
`ifdef CNT_BIN_CE_CLEAR
2019 6 unneback
//////////////////////////////////////////////////////////////////////
2020
////                                                              ////
2021
////  Versatile counter                                           ////
2022
////                                                              ////
2023
////  Description                                                 ////
2024
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2025
////  counter                                                     ////
2026
////                                                              ////
2027
////  To Do:                                                      ////
2028
////   - add LFSR with more taps                                  ////
2029
////                                                              ////
2030
////  Author(s):                                                  ////
2031
////      - Michael Unneback, unneback@opencores.org              ////
2032
////        ORSoC AB                                              ////
2033
////                                                              ////
2034
//////////////////////////////////////////////////////////////////////
2035
////                                                              ////
2036
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2037
////                                                              ////
2038
//// This source file may be used and distributed without         ////
2039
//// restriction provided that this copyright statement is not    ////
2040
//// removed from the file and that any derivative work contains  ////
2041
//// the original copyright notice and the associated disclaimer. ////
2042
////                                                              ////
2043
//// This source file is free software; you can redistribute it   ////
2044
//// and/or modify it under the terms of the GNU Lesser General   ////
2045
//// Public License as published by the Free Software Foundation; ////
2046
//// either version 2.1 of the License, or (at your option) any   ////
2047
//// later version.                                               ////
2048
////                                                              ////
2049
//// This source is distributed in the hope that it will be       ////
2050
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2051
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2052
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2053
//// details.                                                     ////
2054
////                                                              ////
2055
//// You should have received a copy of the GNU Lesser General    ////
2056
//// Public License along with this source; if not, download it   ////
2057
//// from http://www.opencores.org/lgpl.shtml                     ////
2058
////                                                              ////
2059
//////////////////////////////////////////////////////////////////////
2060
 
2061
// binary counter
2062
 
2063 40 unneback
`define MODULE cnt_bin_ce_clear
2064
module `BASE`MODULE (
2065
`undef MODULE
2066
 clear, cke, q, rst, clk);
2067
 
2068 6 unneback
   parameter length = 4;
2069
   input clear;
2070
   input cke;
2071
   output [length:1] q;
2072
   input rst;
2073
   input clk;
2074
 
2075
   parameter clear_value = 0;
2076
   parameter set_value = 1;
2077
   parameter wrap_value = 0;
2078
   parameter level1_value = 15;
2079
 
2080
   reg  [length:1] qi;
2081
   wire [length:1] q_next;
2082
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
2083
 
2084
   always @ (posedge clk or posedge rst)
2085
     if (rst)
2086
       qi <= {length{1'b0}};
2087
     else
2088
     if (cke)
2089
       qi <= q_next;
2090
 
2091
   assign q = qi;
2092
 
2093
endmodule
2094 40 unneback
`endif
2095
`ifdef CNT_BIN_CE_CLEAR_L1_L2
2096 6 unneback
//////////////////////////////////////////////////////////////////////
2097
////                                                              ////
2098
////  Versatile counter                                           ////
2099
////                                                              ////
2100
////  Description                                                 ////
2101
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2102
////  counter                                                     ////
2103
////                                                              ////
2104
////  To Do:                                                      ////
2105
////   - add LFSR with more taps                                  ////
2106
////                                                              ////
2107
////  Author(s):                                                  ////
2108
////      - Michael Unneback, unneback@opencores.org              ////
2109
////        ORSoC AB                                              ////
2110
////                                                              ////
2111
//////////////////////////////////////////////////////////////////////
2112
////                                                              ////
2113
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2114
////                                                              ////
2115
//// This source file may be used and distributed without         ////
2116
//// restriction provided that this copyright statement is not    ////
2117
//// removed from the file and that any derivative work contains  ////
2118
//// the original copyright notice and the associated disclaimer. ////
2119
////                                                              ////
2120
//// This source file is free software; you can redistribute it   ////
2121
//// and/or modify it under the terms of the GNU Lesser General   ////
2122
//// Public License as published by the Free Software Foundation; ////
2123
//// either version 2.1 of the License, or (at your option) any   ////
2124
//// later version.                                               ////
2125
////                                                              ////
2126
//// This source is distributed in the hope that it will be       ////
2127
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2128
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2129
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2130
//// details.                                                     ////
2131
////                                                              ////
2132
//// You should have received a copy of the GNU Lesser General    ////
2133
//// Public License along with this source; if not, download it   ////
2134
//// from http://www.opencores.org/lgpl.shtml                     ////
2135
////                                                              ////
2136
//////////////////////////////////////////////////////////////////////
2137
 
2138
// binary counter
2139 29 unneback
 
2140 40 unneback
`define MODULE cnt_bin_ce_clear_l1_l2
2141
module `BASE`MODULE (
2142
`undef MODULE
2143
 clear, cke, q, level1, level2, rst, clk);
2144
 
2145 29 unneback
   parameter length = 4;
2146
   input clear;
2147
   input cke;
2148
   output [length:1] q;
2149
   output reg level1;
2150
   output reg level2;
2151
   input rst;
2152
   input clk;
2153
 
2154
   parameter clear_value = 0;
2155
   parameter set_value = 1;
2156 30 unneback
   parameter wrap_value = 15;
2157
   parameter level1_value = 8;
2158
   parameter level2_value = 15;
2159 29 unneback
 
2160
   wire rew;
2161 30 unneback
   assign rew = 1'b0;
2162 29 unneback
   reg  [length:1] qi;
2163
   wire [length:1] q_next;
2164
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
2165
 
2166
   always @ (posedge clk or posedge rst)
2167
     if (rst)
2168
       qi <= {length{1'b0}};
2169
     else
2170
     if (cke)
2171
       qi <= q_next;
2172
 
2173
   assign q = qi;
2174
 
2175
 
2176
    always @ (posedge clk or posedge rst)
2177
    if (rst)
2178
        level1 <= 1'b0;
2179
    else
2180
    if (cke)
2181
    if (clear)
2182
        level1 <= 1'b0;
2183
    else if (q_next == level1_value)
2184
        level1 <= 1'b1;
2185
    else if (qi == level1_value & rew)
2186
        level1 <= 1'b0;
2187
 
2188
    always @ (posedge clk or posedge rst)
2189
    if (rst)
2190
        level2 <= 1'b0;
2191
    else
2192
    if (cke)
2193
    if (clear)
2194
        level2 <= 1'b0;
2195
    else if (q_next == level2_value)
2196
        level2 <= 1'b1;
2197
    else if (qi == level2_value & rew)
2198
        level2 <= 1'b0;
2199
endmodule
2200 40 unneback
`endif
2201
`ifdef CNT_BIN_CE_CLEAR_SET_REW
2202 29 unneback
//////////////////////////////////////////////////////////////////////
2203
////                                                              ////
2204
////  Versatile counter                                           ////
2205
////                                                              ////
2206
////  Description                                                 ////
2207
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2208
////  counter                                                     ////
2209
////                                                              ////
2210
////  To Do:                                                      ////
2211
////   - add LFSR with more taps                                  ////
2212
////                                                              ////
2213
////  Author(s):                                                  ////
2214
////      - Michael Unneback, unneback@opencores.org              ////
2215
////        ORSoC AB                                              ////
2216
////                                                              ////
2217
//////////////////////////////////////////////////////////////////////
2218
////                                                              ////
2219
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2220
////                                                              ////
2221
//// This source file may be used and distributed without         ////
2222
//// restriction provided that this copyright statement is not    ////
2223
//// removed from the file and that any derivative work contains  ////
2224
//// the original copyright notice and the associated disclaimer. ////
2225
////                                                              ////
2226
//// This source file is free software; you can redistribute it   ////
2227
//// and/or modify it under the terms of the GNU Lesser General   ////
2228
//// Public License as published by the Free Software Foundation; ////
2229
//// either version 2.1 of the License, or (at your option) any   ////
2230
//// later version.                                               ////
2231
////                                                              ////
2232
//// This source is distributed in the hope that it will be       ////
2233
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2234
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2235
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2236
//// details.                                                     ////
2237
////                                                              ////
2238
//// You should have received a copy of the GNU Lesser General    ////
2239
//// Public License along with this source; if not, download it   ////
2240
//// from http://www.opencores.org/lgpl.shtml                     ////
2241
////                                                              ////
2242
//////////////////////////////////////////////////////////////////////
2243
 
2244
// binary counter
2245 6 unneback
 
2246 40 unneback
`define MODULE cnt_bin_ce_clear_set_rew
2247
module `BASE`MODULE (
2248
`undef MODULE
2249
 clear, set, cke, rew, q, rst, clk);
2250
 
2251 6 unneback
   parameter length = 4;
2252
   input clear;
2253
   input set;
2254
   input cke;
2255
   input rew;
2256
   output [length:1] q;
2257
   input rst;
2258
   input clk;
2259
 
2260
   parameter clear_value = 0;
2261
   parameter set_value = 1;
2262
   parameter wrap_value = 0;
2263
   parameter level1_value = 15;
2264
 
2265
   reg  [length:1] qi;
2266
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2267
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
2268
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
2269
   assign q_next = rew ? q_next_rew : q_next_fw;
2270
 
2271
   always @ (posedge clk or posedge rst)
2272
     if (rst)
2273
       qi <= {length{1'b0}};
2274
     else
2275
     if (cke)
2276
       qi <= q_next;
2277
 
2278
   assign q = qi;
2279
 
2280
endmodule
2281 40 unneback
`endif
2282
`ifdef CNT_BIN_CE_REW_L1
2283 6 unneback
//////////////////////////////////////////////////////////////////////
2284
////                                                              ////
2285
////  Versatile counter                                           ////
2286
////                                                              ////
2287
////  Description                                                 ////
2288
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2289
////  counter                                                     ////
2290
////                                                              ////
2291
////  To Do:                                                      ////
2292
////   - add LFSR with more taps                                  ////
2293
////                                                              ////
2294
////  Author(s):                                                  ////
2295
////      - Michael Unneback, unneback@opencores.org              ////
2296
////        ORSoC AB                                              ////
2297
////                                                              ////
2298
//////////////////////////////////////////////////////////////////////
2299
////                                                              ////
2300
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2301
////                                                              ////
2302
//// This source file may be used and distributed without         ////
2303
//// restriction provided that this copyright statement is not    ////
2304
//// removed from the file and that any derivative work contains  ////
2305
//// the original copyright notice and the associated disclaimer. ////
2306
////                                                              ////
2307
//// This source file is free software; you can redistribute it   ////
2308
//// and/or modify it under the terms of the GNU Lesser General   ////
2309
//// Public License as published by the Free Software Foundation; ////
2310
//// either version 2.1 of the License, or (at your option) any   ////
2311
//// later version.                                               ////
2312
////                                                              ////
2313
//// This source is distributed in the hope that it will be       ////
2314
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2315
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2316
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2317
//// details.                                                     ////
2318
////                                                              ////
2319
//// You should have received a copy of the GNU Lesser General    ////
2320
//// Public License along with this source; if not, download it   ////
2321
//// from http://www.opencores.org/lgpl.shtml                     ////
2322
////                                                              ////
2323
//////////////////////////////////////////////////////////////////////
2324
 
2325
// binary counter
2326
 
2327 40 unneback
`define MODULE cnt_bin_ce_rew_l1
2328
module `BASE`MODULE (
2329
`undef MODULE
2330
 cke, rew, level1, rst, clk);
2331
 
2332 6 unneback
   parameter length = 4;
2333
   input cke;
2334
   input rew;
2335
   output reg level1;
2336
   input rst;
2337
   input clk;
2338
 
2339
   parameter clear_value = 0;
2340
   parameter set_value = 1;
2341
   parameter wrap_value = 1;
2342
   parameter level1_value = 15;
2343
 
2344 29 unneback
   wire clear;
2345 30 unneback
   assign clear = 1'b0;
2346 6 unneback
   reg  [length:1] qi;
2347
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2348
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2349
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2350
   assign q_next = rew ? q_next_rew : q_next_fw;
2351
 
2352
   always @ (posedge clk or posedge rst)
2353
     if (rst)
2354
       qi <= {length{1'b0}};
2355
     else
2356
     if (cke)
2357
       qi <= q_next;
2358
 
2359
 
2360
 
2361
    always @ (posedge clk or posedge rst)
2362
    if (rst)
2363
        level1 <= 1'b0;
2364
    else
2365
    if (cke)
2366 29 unneback
    if (clear)
2367
        level1 <= 1'b0;
2368
    else if (q_next == level1_value)
2369 6 unneback
        level1 <= 1'b1;
2370
    else if (qi == level1_value & rew)
2371
        level1 <= 1'b0;
2372
endmodule
2373 40 unneback
`endif
2374
`ifdef CNT_BIN_CE_REW_ZQ_L1
2375 6 unneback
//////////////////////////////////////////////////////////////////////
2376
////                                                              ////
2377
////  Versatile counter                                           ////
2378
////                                                              ////
2379
////  Description                                                 ////
2380
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2381
////  counter                                                     ////
2382
////                                                              ////
2383
////  To Do:                                                      ////
2384
////   - add LFSR with more taps                                  ////
2385
////                                                              ////
2386
////  Author(s):                                                  ////
2387
////      - Michael Unneback, unneback@opencores.org              ////
2388
////        ORSoC AB                                              ////
2389
////                                                              ////
2390
//////////////////////////////////////////////////////////////////////
2391
////                                                              ////
2392
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2393
////                                                              ////
2394
//// This source file may be used and distributed without         ////
2395
//// restriction provided that this copyright statement is not    ////
2396
//// removed from the file and that any derivative work contains  ////
2397
//// the original copyright notice and the associated disclaimer. ////
2398
////                                                              ////
2399
//// This source file is free software; you can redistribute it   ////
2400
//// and/or modify it under the terms of the GNU Lesser General   ////
2401
//// Public License as published by the Free Software Foundation; ////
2402
//// either version 2.1 of the License, or (at your option) any   ////
2403
//// later version.                                               ////
2404
////                                                              ////
2405
//// This source is distributed in the hope that it will be       ////
2406
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2407
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2408
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2409
//// details.                                                     ////
2410
////                                                              ////
2411
//// You should have received a copy of the GNU Lesser General    ////
2412
//// Public License along with this source; if not, download it   ////
2413
//// from http://www.opencores.org/lgpl.shtml                     ////
2414
////                                                              ////
2415
//////////////////////////////////////////////////////////////////////
2416
 
2417 25 unneback
// binary counter
2418
 
2419 40 unneback
`define MODULE cnt_bin_ce_rew_zq_l1
2420
module `BASE`MODULE (
2421
`undef MODULE
2422
 cke, rew, zq, level1, rst, clk);
2423
 
2424 25 unneback
   parameter length = 4;
2425
   input cke;
2426
   input rew;
2427
   output reg zq;
2428
   output reg level1;
2429
   input rst;
2430
   input clk;
2431
 
2432
   parameter clear_value = 0;
2433
   parameter set_value = 1;
2434
   parameter wrap_value = 1;
2435
   parameter level1_value = 15;
2436
 
2437 29 unneback
   wire clear;
2438 30 unneback
   assign clear = 1'b0;
2439 25 unneback
   reg  [length:1] qi;
2440
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2441
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2442
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2443
   assign q_next = rew ? q_next_rew : q_next_fw;
2444
 
2445
   always @ (posedge clk or posedge rst)
2446
     if (rst)
2447
       qi <= {length{1'b0}};
2448
     else
2449
     if (cke)
2450
       qi <= q_next;
2451
 
2452
 
2453
 
2454
   always @ (posedge clk or posedge rst)
2455
     if (rst)
2456
       zq <= 1'b1;
2457
     else
2458
     if (cke)
2459
       zq <= q_next == {length{1'b0}};
2460
 
2461
    always @ (posedge clk or posedge rst)
2462
    if (rst)
2463
        level1 <= 1'b0;
2464
    else
2465
    if (cke)
2466 29 unneback
    if (clear)
2467
        level1 <= 1'b0;
2468
    else if (q_next == level1_value)
2469 25 unneback
        level1 <= 1'b1;
2470
    else if (qi == level1_value & rew)
2471
        level1 <= 1'b0;
2472
endmodule
2473 40 unneback
`endif
2474
`ifdef CNT_BIN_CE_REW_Q_ZQ_L1
2475 25 unneback
//////////////////////////////////////////////////////////////////////
2476
////                                                              ////
2477
////  Versatile counter                                           ////
2478
////                                                              ////
2479
////  Description                                                 ////
2480
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2481
////  counter                                                     ////
2482
////                                                              ////
2483
////  To Do:                                                      ////
2484
////   - add LFSR with more taps                                  ////
2485
////                                                              ////
2486
////  Author(s):                                                  ////
2487
////      - Michael Unneback, unneback@opencores.org              ////
2488
////        ORSoC AB                                              ////
2489
////                                                              ////
2490
//////////////////////////////////////////////////////////////////////
2491
////                                                              ////
2492
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2493
////                                                              ////
2494
//// This source file may be used and distributed without         ////
2495
//// restriction provided that this copyright statement is not    ////
2496
//// removed from the file and that any derivative work contains  ////
2497
//// the original copyright notice and the associated disclaimer. ////
2498
////                                                              ////
2499
//// This source file is free software; you can redistribute it   ////
2500
//// and/or modify it under the terms of the GNU Lesser General   ////
2501
//// Public License as published by the Free Software Foundation; ////
2502
//// either version 2.1 of the License, or (at your option) any   ////
2503
//// later version.                                               ////
2504
////                                                              ////
2505
//// This source is distributed in the hope that it will be       ////
2506
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2507
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2508
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2509
//// details.                                                     ////
2510
////                                                              ////
2511
//// You should have received a copy of the GNU Lesser General    ////
2512
//// Public License along with this source; if not, download it   ////
2513
//// from http://www.opencores.org/lgpl.shtml                     ////
2514
////                                                              ////
2515
//////////////////////////////////////////////////////////////////////
2516
 
2517
// binary counter
2518
 
2519 40 unneback
`define MODULE cnt_bin_ce_rew_q_zq_l1
2520
module `BASE`MODULE (
2521
`undef MODULE
2522
 cke, rew, q, zq, level1, rst, clk);
2523
 
2524 25 unneback
   parameter length = 4;
2525
   input cke;
2526
   input rew;
2527
   output [length:1] q;
2528
   output reg zq;
2529
   output reg level1;
2530
   input rst;
2531
   input clk;
2532
 
2533
   parameter clear_value = 0;
2534
   parameter set_value = 1;
2535
   parameter wrap_value = 1;
2536
   parameter level1_value = 15;
2537
 
2538 29 unneback
   wire clear;
2539 30 unneback
   assign clear = 1'b0;
2540 25 unneback
   reg  [length:1] qi;
2541
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2542
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2543
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2544
   assign q_next = rew ? q_next_rew : q_next_fw;
2545
 
2546
   always @ (posedge clk or posedge rst)
2547
     if (rst)
2548
       qi <= {length{1'b0}};
2549
     else
2550
     if (cke)
2551
       qi <= q_next;
2552
 
2553
   assign q = qi;
2554
 
2555
 
2556
   always @ (posedge clk or posedge rst)
2557
     if (rst)
2558
       zq <= 1'b1;
2559
     else
2560
     if (cke)
2561
       zq <= q_next == {length{1'b0}};
2562
 
2563
    always @ (posedge clk or posedge rst)
2564
    if (rst)
2565
        level1 <= 1'b0;
2566
    else
2567
    if (cke)
2568 29 unneback
    if (clear)
2569
        level1 <= 1'b0;
2570
    else if (q_next == level1_value)
2571 25 unneback
        level1 <= 1'b1;
2572
    else if (qi == level1_value & rew)
2573
        level1 <= 1'b0;
2574
endmodule
2575 40 unneback
`endif
2576
`ifdef CNT_LFSR_ZQ
2577 25 unneback
//////////////////////////////////////////////////////////////////////
2578
////                                                              ////
2579
////  Versatile counter                                           ////
2580
////                                                              ////
2581
////  Description                                                 ////
2582
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2583
////  counter                                                     ////
2584
////                                                              ////
2585
////  To Do:                                                      ////
2586
////   - add LFSR with more taps                                  ////
2587
////                                                              ////
2588
////  Author(s):                                                  ////
2589
////      - Michael Unneback, unneback@opencores.org              ////
2590
////        ORSoC AB                                              ////
2591
////                                                              ////
2592
//////////////////////////////////////////////////////////////////////
2593
////                                                              ////
2594
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2595
////                                                              ////
2596
//// This source file may be used and distributed without         ////
2597
//// restriction provided that this copyright statement is not    ////
2598
//// removed from the file and that any derivative work contains  ////
2599
//// the original copyright notice and the associated disclaimer. ////
2600
////                                                              ////
2601
//// This source file is free software; you can redistribute it   ////
2602
//// and/or modify it under the terms of the GNU Lesser General   ////
2603
//// Public License as published by the Free Software Foundation; ////
2604
//// either version 2.1 of the License, or (at your option) any   ////
2605
//// later version.                                               ////
2606
////                                                              ////
2607
//// This source is distributed in the hope that it will be       ////
2608
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2609
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2610
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2611
//// details.                                                     ////
2612
////                                                              ////
2613
//// You should have received a copy of the GNU Lesser General    ////
2614
//// Public License along with this source; if not, download it   ////
2615
//// from http://www.opencores.org/lgpl.shtml                     ////
2616
////                                                              ////
2617
//////////////////////////////////////////////////////////////////////
2618
 
2619 6 unneback
// LFSR counter
2620
 
2621 40 unneback
`define MODULE cnt_lfsr_zq
2622
module `BASE`MODULE (
2623
`undef MODULE
2624
 zq, rst, clk);
2625
 
2626 6 unneback
   parameter length = 4;
2627
   output reg zq;
2628
   input rst;
2629
   input clk;
2630
 
2631
   parameter clear_value = 0;
2632
   parameter set_value = 1;
2633
   parameter wrap_value = 8;
2634
   parameter level1_value = 15;
2635
 
2636
   reg  [length:1] qi;
2637
   reg lfsr_fb;
2638
   wire [length:1] q_next;
2639
   reg [32:1] polynom;
2640
   integer i;
2641
 
2642
   always @ (qi)
2643
   begin
2644
        case (length)
2645
         2: polynom = 32'b11;                               // 0x3
2646
         3: polynom = 32'b110;                              // 0x6
2647
         4: polynom = 32'b1100;                             // 0xC
2648
         5: polynom = 32'b10100;                            // 0x14
2649
         6: polynom = 32'b110000;                           // 0x30
2650
         7: polynom = 32'b1100000;                          // 0x60
2651
         8: polynom = 32'b10111000;                         // 0xb8
2652
         9: polynom = 32'b100010000;                        // 0x110
2653
        10: polynom = 32'b1001000000;                       // 0x240
2654
        11: polynom = 32'b10100000000;                      // 0x500
2655
        12: polynom = 32'b100000101001;                     // 0x829
2656
        13: polynom = 32'b1000000001100;                    // 0x100C
2657
        14: polynom = 32'b10000000010101;                   // 0x2015
2658
        15: polynom = 32'b110000000000000;                  // 0x6000
2659
        16: polynom = 32'b1101000000001000;                 // 0xD008
2660
        17: polynom = 32'b10010000000000000;                // 0x12000
2661
        18: polynom = 32'b100000010000000000;               // 0x20400
2662
        19: polynom = 32'b1000000000000100011;              // 0x40023
2663 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2664 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2665
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2666
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2667
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2668
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2669
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2670
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2671
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2672
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2673
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2674
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2675
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2676
        default: polynom = 32'b0;
2677
        endcase
2678
        lfsr_fb = qi[length];
2679
        for (i=length-1; i>=1; i=i-1) begin
2680
            if (polynom[i])
2681
                lfsr_fb = lfsr_fb  ~^ qi[i];
2682
        end
2683
    end
2684
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2685
 
2686
   always @ (posedge clk or posedge rst)
2687
     if (rst)
2688
       qi <= {length{1'b0}};
2689
     else
2690
       qi <= q_next;
2691
 
2692
 
2693
 
2694
   always @ (posedge clk or posedge rst)
2695
     if (rst)
2696
       zq <= 1'b1;
2697
     else
2698
       zq <= q_next == {length{1'b0}};
2699
endmodule
2700 40 unneback
`endif
2701 75 unneback
`ifdef CNT_LFSR_CE
2702
//////////////////////////////////////////////////////////////////////
2703
////                                                              ////
2704
////  Versatile counter                                           ////
2705
////                                                              ////
2706
////  Description                                                 ////
2707
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2708
////  counter                                                     ////
2709
////                                                              ////
2710
////  To Do:                                                      ////
2711
////   - add LFSR with more taps                                  ////
2712
////                                                              ////
2713
////  Author(s):                                                  ////
2714
////      - Michael Unneback, unneback@opencores.org              ////
2715
////        ORSoC AB                                              ////
2716
////                                                              ////
2717
//////////////////////////////////////////////////////////////////////
2718
////                                                              ////
2719
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2720
////                                                              ////
2721
//// This source file may be used and distributed without         ////
2722
//// restriction provided that this copyright statement is not    ////
2723
//// removed from the file and that any derivative work contains  ////
2724
//// the original copyright notice and the associated disclaimer. ////
2725
////                                                              ////
2726
//// This source file is free software; you can redistribute it   ////
2727
//// and/or modify it under the terms of the GNU Lesser General   ////
2728
//// Public License as published by the Free Software Foundation; ////
2729
//// either version 2.1 of the License, or (at your option) any   ////
2730
//// later version.                                               ////
2731
////                                                              ////
2732
//// This source is distributed in the hope that it will be       ////
2733
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2734
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2735
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2736
//// details.                                                     ////
2737
////                                                              ////
2738
//// You should have received a copy of the GNU Lesser General    ////
2739
//// Public License along with this source; if not, download it   ////
2740
//// from http://www.opencores.org/lgpl.shtml                     ////
2741
////                                                              ////
2742
//////////////////////////////////////////////////////////////////////
2743
 
2744
// LFSR counter
2745
 
2746
`define MODULE cnt_lfsr_ce
2747
module `BASE`MODULE (
2748
`undef MODULE
2749
 cke, zq, rst, clk);
2750
 
2751
   parameter length = 4;
2752
   input cke;
2753
   output reg zq;
2754
   input rst;
2755
   input clk;
2756
 
2757
   parameter clear_value = 0;
2758
   parameter set_value = 1;
2759
   parameter wrap_value = 0;
2760
   parameter level1_value = 15;
2761
 
2762
   reg  [length:1] qi;
2763
   reg lfsr_fb;
2764
   wire [length:1] q_next;
2765
   reg [32:1] polynom;
2766
   integer i;
2767
 
2768
   always @ (qi)
2769
   begin
2770
        case (length)
2771
         2: polynom = 32'b11;                               // 0x3
2772
         3: polynom = 32'b110;                              // 0x6
2773
         4: polynom = 32'b1100;                             // 0xC
2774
         5: polynom = 32'b10100;                            // 0x14
2775
         6: polynom = 32'b110000;                           // 0x30
2776
         7: polynom = 32'b1100000;                          // 0x60
2777
         8: polynom = 32'b10111000;                         // 0xb8
2778
         9: polynom = 32'b100010000;                        // 0x110
2779
        10: polynom = 32'b1001000000;                       // 0x240
2780
        11: polynom = 32'b10100000000;                      // 0x500
2781
        12: polynom = 32'b100000101001;                     // 0x829
2782
        13: polynom = 32'b1000000001100;                    // 0x100C
2783
        14: polynom = 32'b10000000010101;                   // 0x2015
2784
        15: polynom = 32'b110000000000000;                  // 0x6000
2785
        16: polynom = 32'b1101000000001000;                 // 0xD008
2786
        17: polynom = 32'b10010000000000000;                // 0x12000
2787
        18: polynom = 32'b100000010000000000;               // 0x20400
2788
        19: polynom = 32'b1000000000000100011;              // 0x40023
2789
        20: polynom = 32'b10010000000000000000;             // 0x90000
2790
        21: polynom = 32'b101000000000000000000;            // 0x140000
2791
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2792
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2793
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2794
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2795
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2796
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2797
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2798
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2799
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2800
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2801
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2802
        default: polynom = 32'b0;
2803
        endcase
2804
        lfsr_fb = qi[length];
2805
        for (i=length-1; i>=1; i=i-1) begin
2806
            if (polynom[i])
2807
                lfsr_fb = lfsr_fb  ~^ qi[i];
2808
        end
2809
    end
2810
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2811
 
2812
   always @ (posedge clk or posedge rst)
2813
     if (rst)
2814
       qi <= {length{1'b0}};
2815
     else
2816
     if (cke)
2817
       qi <= q_next;
2818
 
2819
 
2820
 
2821
   always @ (posedge clk or posedge rst)
2822
     if (rst)
2823
       zq <= 1'b1;
2824
     else
2825
     if (cke)
2826
       zq <= q_next == {length{1'b0}};
2827
endmodule
2828
`endif
2829 40 unneback
`ifdef CNT_LFSR_CE_ZQ
2830 6 unneback
//////////////////////////////////////////////////////////////////////
2831
////                                                              ////
2832
////  Versatile counter                                           ////
2833
////                                                              ////
2834
////  Description                                                 ////
2835
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2836
////  counter                                                     ////
2837
////                                                              ////
2838
////  To Do:                                                      ////
2839
////   - add LFSR with more taps                                  ////
2840
////                                                              ////
2841
////  Author(s):                                                  ////
2842
////      - Michael Unneback, unneback@opencores.org              ////
2843
////        ORSoC AB                                              ////
2844
////                                                              ////
2845