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1 6 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  Versatile library, clock and reset                          ////
4
////                                                              ////
5
////  Description                                                 ////
6
////  Logic related to clock and reset                            ////
7
////                                                              ////
8
////                                                              ////
9
////  To Do:                                                      ////
10
////   - add more different registers                             ////
11
////                                                              ////
12
////  Author(s):                                                  ////
13
////      - Michael Unneback, unneback@opencores.org              ////
14
////        ORSoC AB                                              ////
15
////                                                              ////
16
//////////////////////////////////////////////////////////////////////
17
////                                                              ////
18
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
19
////                                                              ////
20
//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
36
////                                                              ////
37
//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
 
43
// Global buffer
44
// usage:
45
// use to enable global buffers for high fan out signals such as clock and reset
46
 
47
`ifdef ACTEL
48
 
49
`timescale 1 ns/100 ps
50
// Version: 8.4 8.4.0.33
51
module gbuf(GL,CLK);
52
output GL;
53
input  CLK;
54
 
55
    wire GND;
56
 
57
    GND GND_1_net(.Y(GND));
58
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
59
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
60
 
61
endmodule
62
`timescale 1 ns/1 ns
63
module vl_gbuf ( i, o);
64
input i;
65
output o;
66
`ifdef SIM_GBUF
67
assign o=i;
68
`else
69
gbuf gbuf_i0 ( .CLK(i), .GL(o));
70
`endif
71
endmodule
72
`else
73
`ifdef ALTERA
74
altera
75
`else
76
 
77
`timescale 1 ns/100 ps
78
module vl_gbuf ( i, o);
79
input i;
80
output o;
81
assign o = i;
82
endmodule
83
`endif // ALTERA
84
`endif //ACTEL
85
 
86
// sync reset
87 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
88 6 unneback
// output active high global reset sync with two DFFs 
89
`timescale 1 ns/100 ps
90
module vl_sync_rst ( rst_n_i, rst_o, clk);
91
input rst_n_i, clk;
92
output rst_o;
93
reg [0:1] tmp;
94
always @ (posedge clk or negedge rst_n_i)
95
if (!rst_n_i)
96 17 unneback
        tmp <= 2'b11;
97 6 unneback
else
98 17 unneback
        tmp <= {1'b0,tmp[0]};
99
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
100 6 unneback
endmodule
101
 
102
// vl_pll
103
`ifdef ACTEL
104 17 unneback
`timescale 1 ps/1 ps
105 6 unneback
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
106
parameter index = 0;
107
parameter number_of_clk = 1;
108 17 unneback
parameter period_time_0 = 20000;
109
parameter period_time_1 = 20000;
110
parameter period_time_2 = 20000;
111
parameter lock_delay = 2000000;
112 6 unneback
input clk_i, rst_n_i;
113
output lock;
114
output reg [0:number_of_clk-1] clk_o;
115
output [0:number_of_clk-1] rst_o;
116
 
117
`ifdef SIM_PLL
118
 
119
always
120
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
121
 
122
generate if (number_of_clk > 1)
123
always
124
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
125
endgenerate
126
 
127
generate if (number_of_clk > 2)
128
always
129
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
130
endgenerate
131
 
132
genvar i;
133
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
134
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
135
end
136
endgenerate
137
 
138
assign #lock_delay lock = rst_n_i;
139
 
140
endmodule
141
`else
142
generate if (number_of_clk==1 & index==0) begin
143
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
144
end
145
endgenerate // index==0
146
generate if (number_of_clk==1 & index==1) begin
147
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
148
end
149
endgenerate // index==1
150
generate if (number_of_clk==1 & index==2) begin
151
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
152
end
153
endgenerate // index==2
154
generate if (number_of_clk==1 & index==3) begin
155
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
156
end
157
endgenerate // index==0
158
 
159
generate if (number_of_clk==2 & index==0) begin
160
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
161
end
162
endgenerate // index==0
163
generate if (number_of_clk==2 & index==1) begin
164
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
165
end
166
endgenerate // index==1
167
generate if (number_of_clk==2 & index==2) begin
168
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
169
end
170
endgenerate // index==2
171
generate if (number_of_clk==2 & index==3) begin
172
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
173
end
174
endgenerate // index==0
175
 
176
generate if (number_of_clk==3 & index==0) begin
177
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
178
end
179
endgenerate // index==0
180
generate if (number_of_clk==3 & index==1) begin
181
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
182
end
183
endgenerate // index==1
184
generate if (number_of_clk==3 & index==2) begin
185
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
186
end
187
endgenerate // index==2
188
generate if (number_of_clk==3 & index==3) begin
189
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
190
end
191
endgenerate // index==0
192
 
193
genvar i;
194
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
195
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
196
end
197
endgenerate
198
endmodule
199
`endif
200
 
201
`else
202
 
203
`ifdef ALTERA
204
 
205
`else
206
 
207
// generic PLL
208 17 unneback
`timescale 1 ps/1 ps
209 6 unneback
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
210
parameter index = 0;
211
parameter number_of_clk = 1;
212 17 unneback
parameter period_time_0 = 20000;
213
parameter period_time_1 = 20000;
214
parameter period_time_2 = 20000;
215 6 unneback
parameter lock_delay = 2000;
216
input clk_i, rst_n_i;
217
output lock;
218
output reg [0:number_of_clk-1] clk_o;
219
output [0:number_of_clk-1] rst_o;
220
 
221
always
222
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
223
 
224
generate if (number_of_clk > 1)
225
always
226
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
227
endgenerate
228
 
229
generate if (number_of_clk > 2)
230
always
231
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
232
endgenerate
233
 
234
genvar i;
235
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
236
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
237
end
238
endgenerate
239
 
240
assign #lock_delay lock = rst_n_i;
241
 
242
endmodule
243
 
244
`endif //altera
245 17 unneback
`endif //actel
246
//////////////////////////////////////////////////////////////////////
247 6 unneback
////                                                              ////
248
////  Versatile library, registers                                ////
249
////                                                              ////
250
////  Description                                                 ////
251
////  Different type of registers                                 ////
252
////                                                              ////
253
////                                                              ////
254
////  To Do:                                                      ////
255
////   - add more different registers                             ////
256
////                                                              ////
257
////  Author(s):                                                  ////
258
////      - Michael Unneback, unneback@opencores.org              ////
259
////        ORSoC AB                                              ////
260
////                                                              ////
261
//////////////////////////////////////////////////////////////////////
262
////                                                              ////
263
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
264
////                                                              ////
265
//// This source file may be used and distributed without         ////
266
//// restriction provided that this copyright statement is not    ////
267
//// removed from the file and that any derivative work contains  ////
268
//// the original copyright notice and the associated disclaimer. ////
269
////                                                              ////
270
//// This source file is free software; you can redistribute it   ////
271
//// and/or modify it under the terms of the GNU Lesser General   ////
272
//// Public License as published by the Free Software Foundation; ////
273
//// either version 2.1 of the License, or (at your option) any   ////
274
//// later version.                                               ////
275
////                                                              ////
276
//// This source is distributed in the hope that it will be       ////
277
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
278
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
279
//// PURPOSE.  See the GNU Lesser General Public License for more ////
280
//// details.                                                     ////
281
////                                                              ////
282
//// You should have received a copy of the GNU Lesser General    ////
283
//// Public License along with this source; if not, download it   ////
284
//// from http://www.opencores.org/lgpl.shtml                     ////
285
////                                                              ////
286
//////////////////////////////////////////////////////////////////////
287
 
288
module dff ( d, q, clk, rst);
289
 
290
        parameter width = 1;
291
        parameter reset_value = 0;
292
 
293
        input [width-1:0] d;
294
        input clk, rst;
295
        output reg [width-1:0] q;
296
 
297
        always @ (posedge clk or posedge rst)
298
        if (rst)
299
                q <= reset_value;
300
        else
301
                q <= d;
302
 
303
endmodule
304
 
305
module dff_array ( d, q, clk, rst);
306
 
307
        parameter width = 1;
308
        parameter depth = 2;
309
        parameter reset_value = 1'b0;
310
 
311
        input [width-1:0] d;
312
        input clk, rst;
313
        output [width-1:0] q;
314
        reg  [0:depth-1] q_tmp [width-1:0];
315
        integer i;
316
        always @ (posedge clk or posedge rst)
317
        if (rst) begin
318
            for (i=0;i<depth;i=i+1)
319
                q_tmp[i] <= {width{reset_value}};
320
        end else begin
321
            q_tmp[0] <= d;
322
            for (i=1;i<depth;i=i+1)
323
                q_tmp[i] <= q_tmp[i-1];
324
        end
325
 
326
    assign q = q_tmp[depth-1];
327
 
328
endmodule
329
 
330
module dff_ce ( d, ce, q, clk, rst);
331
 
332
        parameter width = 1;
333
        parameter reset_value = 0;
334
 
335
        input [width-1:0] d;
336
        input ce, clk, rst;
337
        output reg [width-1:0] q;
338
 
339
        always @ (posedge clk or posedge rst)
340
        if (rst)
341
                q <= reset_value;
342
        else
343
                if (ce)
344
                        q <= d;
345
 
346
endmodule
347
 
348 8 unneback
module dff_ce_clear ( d, ce, clear, q, clk, rst);
349
 
350
        parameter width = 1;
351
        parameter reset_value = 0;
352
 
353
        input [width-1:0] d;
354 10 unneback
        input ce, clear, clk, rst;
355 8 unneback
        output reg [width-1:0] q;
356
 
357
        always @ (posedge clk or posedge rst)
358
        if (rst)
359
            q <= reset_value;
360
        else
361
            if (ce)
362
                if (clear)
363
                    q <= {width{1'b0}};
364
                else
365
                    q <= d;
366
 
367
endmodule
368
 
369 6 unneback
`ifdef ALTERA
370
// megafunction wizard: %LPM_FF%
371
// GENERATION: STANDARD
372
// VERSION: WM1.0
373
// MODULE: lpm_ff 
374
 
375
// ============================================================
376
// File Name: dff_sr.v
377
// Megafunction Name(s):
378
//                      lpm_ff
379
//
380
// Simulation Library Files(s):
381
//                      lpm
382
// ============================================================
383
// ************************************************************
384
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
385
//
386
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
387
// ************************************************************
388
 
389
 
390
//Copyright (C) 1991-2010 Altera Corporation
391
//Your use of Altera Corporation's design tools, logic functions 
392
//and other software and tools, and its AMPP partner logic 
393
//functions, and any output files from any of the foregoing 
394
//(including device programming or simulation files), and any 
395
//associated documentation or information are expressly subject 
396
//to the terms and conditions of the Altera Program License 
397
//Subscription Agreement, Altera MegaCore Function License 
398
//Agreement, or other applicable license agreement, including, 
399
//without limitation, that your use is for the sole purpose of 
400
//programming logic devices manufactured by Altera and sold by 
401
//Altera or its authorized distributors.  Please refer to the 
402
//applicable agreement for further details.
403
 
404
 
405
// synopsys translate_off
406
`timescale 1 ps / 1 ps
407
// synopsys translate_on
408
module dff_sr (
409
        aclr,
410
        aset,
411
        clock,
412
        data,
413
        q);
414
 
415
        input     aclr;
416
        input     aset;
417
        input     clock;
418
        input     data;
419
        output    q;
420
 
421
        wire [0:0] sub_wire0;
422
        wire [0:0] sub_wire1 = sub_wire0[0:0];
423
        wire  q = sub_wire1;
424
        wire  sub_wire2 = data;
425
        wire  sub_wire3 = sub_wire2;
426
 
427
        lpm_ff  lpm_ff_component (
428
                                .aclr (aclr),
429
                                .clock (clock),
430
                                .data (sub_wire3),
431
                                .aset (aset),
432
                                .q (sub_wire0)
433
                                // synopsys translate_off
434
                                ,
435
                                .aload (),
436
                                .enable (),
437
                                .sclr (),
438
                                .sload (),
439
                                .sset ()
440
                                // synopsys translate_on
441
                                );
442
        defparam
443
                lpm_ff_component.lpm_fftype = "DFF",
444
                lpm_ff_component.lpm_type = "LPM_FF",
445
                lpm_ff_component.lpm_width = 1;
446
 
447
 
448
endmodule
449
 
450
// ============================================================
451
// CNX file retrieval info
452
// ============================================================
453
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
454
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
455
// Retrieval info: PRIVATE: ASET NUMERIC "1"
456
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
457
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
458
// Retrieval info: PRIVATE: DFF NUMERIC "1"
459
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
460
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
461
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
462
// Retrieval info: PRIVATE: SSET NUMERIC "0"
463
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
464
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
465
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
466
// Retrieval info: PRIVATE: nBit NUMERIC "1"
467
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
468
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
469
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
470
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
471
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
472
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
473
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
474
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
475
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
476
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
477
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
478
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
479
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
480
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
481
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
482
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
483
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
484
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
485
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
486
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
487
// Retrieval info: LIB_FILE: lpm
488
 
489
 
490
`else
491
 
492
 
493
module dff_sr ( aclr, aset, clock, data, q);
494
 
495
    input         aclr;
496
    input         aset;
497
    input         clock;
498
    input         data;
499
    output reg    q;
500
 
501
   always @ (posedge clock or posedge aclr or posedge aset)
502
     if (aclr)
503
       q <= 1'b0;
504
     else if (aset)
505
       q <= 1'b1;
506
     else
507
       q <= data;
508
 
509
endmodule
510
 
511
`endif
512
 
513
// LATCH
514
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
515
`ifdef ALTERA
516
module latch ( d, le, q, clk);
517
input d, le;
518
output q;
519
input clk;
520
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
521
endmodule
522
`else
523
module latch ( d, le, q, clk);
524
input d, le;
525
output q;
526
input clk;/*
527
   always @ (posedge direction_set or posedge direction_clr)
528
     if (direction_clr)
529
       direction <= going_empty;
530
     else
531
       direction <= going_full;*/
532
endmodule
533 15 unneback
`endif
534
 
535 17 unneback
module shreg ( d, q, clk, rst);
536
parameter depth = 10;
537
input d;
538
output q;
539
input clk, rst;
540
 
541
reg [1:depth] dffs;
542
 
543
always @ (posedge clk or posedge rst)
544
if (rst)
545
    dffs <= {depth{1'b0}};
546
else
547
    dffs <= {d,dffs[1:depth-1]};
548
assign q = dffs[depth];
549
endmodule
550
 
551
module shreg_ce ( d, ce, q, clk, rst);
552
parameter depth = 10;
553
input d, ce;
554
output q;
555
input clk, rst;
556
 
557
reg [1:depth] dffs;
558
 
559
always @ (posedge clk or posedge rst)
560
if (rst)
561
    dffs <= {depth{1'b0}};
562
else
563
    if (ce)
564
        dffs <= {d,dffs[1:depth-1]};
565
assign q = dffs[depth];
566
endmodule
567
 
568 15 unneback
module delay ( d, q, clk, rst);
569
parameter depth = 10;
570
input d;
571
output q;
572
input clk, rst;
573
 
574
reg [1:depth] dffs;
575
 
576
always @ (posedge clk or posedge rst)
577
if (rst)
578
    dffs <= {depth{1'b0}};
579
else
580
    dffs <= {d,dffs[1:depth-1]};
581
assign q = dffs[depth];
582 17 unneback
endmodule
583
 
584
module delay_emptyflag ( d, q, emptyflag, clk, rst);
585
parameter depth = 10;
586
input d;
587
output q, emptyflag;
588
input clk, rst;
589
 
590
reg [1:depth] dffs;
591
 
592
always @ (posedge clk or posedge rst)
593
if (rst)
594
    dffs <= {depth{1'b0}};
595
else
596
    dffs <= {d,dffs[1:depth-1]};
597
assign q = dffs[depth];
598
assign emptyflag = !(|dffs);
599
endmodule
600
//////////////////////////////////////////////////////////////////////
601 6 unneback
////                                                              ////
602
////  Versatile counter                                           ////
603
////                                                              ////
604
////  Description                                                 ////
605
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
606
////  counter                                                     ////
607
////                                                              ////
608
////  To Do:                                                      ////
609
////   - add LFSR with more taps                                  ////
610
////                                                              ////
611
////  Author(s):                                                  ////
612
////      - Michael Unneback, unneback@opencores.org              ////
613
////        ORSoC AB                                              ////
614
////                                                              ////
615
//////////////////////////////////////////////////////////////////////
616
////                                                              ////
617
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
618
////                                                              ////
619
//// This source file may be used and distributed without         ////
620
//// restriction provided that this copyright statement is not    ////
621
//// removed from the file and that any derivative work contains  ////
622
//// the original copyright notice and the associated disclaimer. ////
623
////                                                              ////
624
//// This source file is free software; you can redistribute it   ////
625
//// and/or modify it under the terms of the GNU Lesser General   ////
626
//// Public License as published by the Free Software Foundation; ////
627
//// either version 2.1 of the License, or (at your option) any   ////
628
//// later version.                                               ////
629
////                                                              ////
630
//// This source is distributed in the hope that it will be       ////
631
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
632
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
633
//// PURPOSE.  See the GNU Lesser General Public License for more ////
634
//// details.                                                     ////
635
////                                                              ////
636
//// You should have received a copy of the GNU Lesser General    ////
637
//// Public License along with this source; if not, download it   ////
638
//// from http://www.opencores.org/lgpl.shtml                     ////
639
////                                                              ////
640
//////////////////////////////////////////////////////////////////////
641
 
642
// binary counter
643
module cnt_bin_ce ( cke, q, rst, clk);
644
 
645
   parameter length = 4;
646
   input cke;
647
   output [length:1] q;
648
   input rst;
649
   input clk;
650
 
651
   parameter clear_value = 0;
652
   parameter set_value = 1;
653
   parameter wrap_value = 0;
654
   parameter level1_value = 15;
655
 
656
   reg  [length:1] qi;
657
   wire [length:1] q_next;
658
   assign q_next = qi + {{length-1{1'b0}},1'b1};
659
 
660
   always @ (posedge clk or posedge rst)
661
     if (rst)
662
       qi <= {length{1'b0}};
663
     else
664
     if (cke)
665
       qi <= q_next;
666
 
667
   assign q = qi;
668
 
669
endmodule
670
//////////////////////////////////////////////////////////////////////
671
////                                                              ////
672
////  Versatile counter                                           ////
673
////                                                              ////
674
////  Description                                                 ////
675
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
676
////  counter                                                     ////
677
////                                                              ////
678
////  To Do:                                                      ////
679
////   - add LFSR with more taps                                  ////
680
////                                                              ////
681
////  Author(s):                                                  ////
682
////      - Michael Unneback, unneback@opencores.org              ////
683
////        ORSoC AB                                              ////
684
////                                                              ////
685
//////////////////////////////////////////////////////////////////////
686
////                                                              ////
687
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
688
////                                                              ////
689
//// This source file may be used and distributed without         ////
690
//// restriction provided that this copyright statement is not    ////
691
//// removed from the file and that any derivative work contains  ////
692
//// the original copyright notice and the associated disclaimer. ////
693
////                                                              ////
694
//// This source file is free software; you can redistribute it   ////
695
//// and/or modify it under the terms of the GNU Lesser General   ////
696
//// Public License as published by the Free Software Foundation; ////
697
//// either version 2.1 of the License, or (at your option) any   ////
698
//// later version.                                               ////
699
////                                                              ////
700
//// This source is distributed in the hope that it will be       ////
701
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
702
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
703
//// PURPOSE.  See the GNU Lesser General Public License for more ////
704
//// details.                                                     ////
705
////                                                              ////
706
//// You should have received a copy of the GNU Lesser General    ////
707
//// Public License along with this source; if not, download it   ////
708
//// from http://www.opencores.org/lgpl.shtml                     ////
709
////                                                              ////
710
//////////////////////////////////////////////////////////////////////
711
 
712
// binary counter
713
module cnt_bin_ce_clear ( clear, cke, q, rst, clk);
714
 
715
   parameter length = 4;
716
   input clear;
717
   input cke;
718
   output [length:1] q;
719
   input rst;
720
   input clk;
721
 
722
   parameter clear_value = 0;
723
   parameter set_value = 1;
724
   parameter wrap_value = 0;
725
   parameter level1_value = 15;
726
 
727
   reg  [length:1] qi;
728
   wire [length:1] q_next;
729
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
730
 
731
   always @ (posedge clk or posedge rst)
732
     if (rst)
733
       qi <= {length{1'b0}};
734
     else
735
     if (cke)
736
       qi <= q_next;
737
 
738
   assign q = qi;
739
 
740
endmodule
741
//////////////////////////////////////////////////////////////////////
742
////                                                              ////
743
////  Versatile counter                                           ////
744
////                                                              ////
745
////  Description                                                 ////
746
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
747
////  counter                                                     ////
748
////                                                              ////
749
////  To Do:                                                      ////
750
////   - add LFSR with more taps                                  ////
751
////                                                              ////
752
////  Author(s):                                                  ////
753
////      - Michael Unneback, unneback@opencores.org              ////
754
////        ORSoC AB                                              ////
755
////                                                              ////
756
//////////////////////////////////////////////////////////////////////
757
////                                                              ////
758
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
759
////                                                              ////
760
//// This source file may be used and distributed without         ////
761
//// restriction provided that this copyright statement is not    ////
762
//// removed from the file and that any derivative work contains  ////
763
//// the original copyright notice and the associated disclaimer. ////
764
////                                                              ////
765
//// This source file is free software; you can redistribute it   ////
766
//// and/or modify it under the terms of the GNU Lesser General   ////
767
//// Public License as published by the Free Software Foundation; ////
768
//// either version 2.1 of the License, or (at your option) any   ////
769
//// later version.                                               ////
770
////                                                              ////
771
//// This source is distributed in the hope that it will be       ////
772
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
773
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
774
//// PURPOSE.  See the GNU Lesser General Public License for more ////
775
//// details.                                                     ////
776
////                                                              ////
777
//// You should have received a copy of the GNU Lesser General    ////
778
//// Public License along with this source; if not, download it   ////
779
//// from http://www.opencores.org/lgpl.shtml                     ////
780
////                                                              ////
781
//////////////////////////////////////////////////////////////////////
782
 
783
// binary counter
784
module cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk);
785
 
786
   parameter length = 4;
787
   input clear;
788
   input set;
789
   input cke;
790
   input rew;
791
   output [length:1] q;
792
   input rst;
793
   input clk;
794
 
795
   parameter clear_value = 0;
796
   parameter set_value = 1;
797
   parameter wrap_value = 0;
798
   parameter level1_value = 15;
799
 
800
   reg  [length:1] qi;
801
   wire  [length:1] q_next, q_next_fw, q_next_rew;
802
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
803
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
804
   assign q_next = rew ? q_next_rew : q_next_fw;
805
 
806
   always @ (posedge clk or posedge rst)
807
     if (rst)
808
       qi <= {length{1'b0}};
809
     else
810
     if (cke)
811
       qi <= q_next;
812
 
813
   assign q = qi;
814
 
815
endmodule
816
//////////////////////////////////////////////////////////////////////
817
////                                                              ////
818
////  Versatile counter                                           ////
819
////                                                              ////
820
////  Description                                                 ////
821
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
822
////  counter                                                     ////
823
////                                                              ////
824
////  To Do:                                                      ////
825
////   - add LFSR with more taps                                  ////
826
////                                                              ////
827
////  Author(s):                                                  ////
828
////      - Michael Unneback, unneback@opencores.org              ////
829
////        ORSoC AB                                              ////
830
////                                                              ////
831
//////////////////////////////////////////////////////////////////////
832
////                                                              ////
833
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
834
////                                                              ////
835
//// This source file may be used and distributed without         ////
836
//// restriction provided that this copyright statement is not    ////
837
//// removed from the file and that any derivative work contains  ////
838
//// the original copyright notice and the associated disclaimer. ////
839
////                                                              ////
840
//// This source file is free software; you can redistribute it   ////
841
//// and/or modify it under the terms of the GNU Lesser General   ////
842
//// Public License as published by the Free Software Foundation; ////
843
//// either version 2.1 of the License, or (at your option) any   ////
844
//// later version.                                               ////
845
////                                                              ////
846
//// This source is distributed in the hope that it will be       ////
847
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
848
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
849
//// PURPOSE.  See the GNU Lesser General Public License for more ////
850
//// details.                                                     ////
851
////                                                              ////
852
//// You should have received a copy of the GNU Lesser General    ////
853
//// Public License along with this source; if not, download it   ////
854
//// from http://www.opencores.org/lgpl.shtml                     ////
855
////                                                              ////
856
//////////////////////////////////////////////////////////////////////
857
 
858
// binary counter
859
module cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk);
860
 
861
   parameter length = 4;
862
   input cke;
863
   input rew;
864
   output reg level1;
865
   input rst;
866
   input clk;
867
 
868
   parameter clear_value = 0;
869
   parameter set_value = 1;
870
   parameter wrap_value = 1;
871
   parameter level1_value = 15;
872
 
873
   reg  [length:1] qi;
874
   wire  [length:1] q_next, q_next_fw, q_next_rew;
875
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
876
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
877
   assign q_next = rew ? q_next_rew : q_next_fw;
878
 
879
   always @ (posedge clk or posedge rst)
880
     if (rst)
881
       qi <= {length{1'b0}};
882
     else
883
     if (cke)
884
       qi <= q_next;
885
 
886
 
887
 
888
    always @ (posedge clk or posedge rst)
889
    if (rst)
890
        level1 <= 1'b0;
891
    else
892
    if (cke)
893
    if (q_next == level1_value)
894
        level1 <= 1'b1;
895
    else if (qi == level1_value & rew)
896
        level1 <= 1'b0;
897
endmodule
898
//////////////////////////////////////////////////////////////////////
899
////                                                              ////
900
////  Versatile counter                                           ////
901
////                                                              ////
902
////  Description                                                 ////
903
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
904
////  counter                                                     ////
905
////                                                              ////
906
////  To Do:                                                      ////
907
////   - add LFSR with more taps                                  ////
908
////                                                              ////
909
////  Author(s):                                                  ////
910
////      - Michael Unneback, unneback@opencores.org              ////
911
////        ORSoC AB                                              ////
912
////                                                              ////
913
//////////////////////////////////////////////////////////////////////
914
////                                                              ////
915
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
916
////                                                              ////
917
//// This source file may be used and distributed without         ////
918
//// restriction provided that this copyright statement is not    ////
919
//// removed from the file and that any derivative work contains  ////
920
//// the original copyright notice and the associated disclaimer. ////
921
////                                                              ////
922
//// This source file is free software; you can redistribute it   ////
923
//// and/or modify it under the terms of the GNU Lesser General   ////
924
//// Public License as published by the Free Software Foundation; ////
925
//// either version 2.1 of the License, or (at your option) any   ////
926
//// later version.                                               ////
927
////                                                              ////
928
//// This source is distributed in the hope that it will be       ////
929
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
930
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
931
//// PURPOSE.  See the GNU Lesser General Public License for more ////
932
//// details.                                                     ////
933
////                                                              ////
934
//// You should have received a copy of the GNU Lesser General    ////
935
//// Public License along with this source; if not, download it   ////
936
//// from http://www.opencores.org/lgpl.shtml                     ////
937
////                                                              ////
938
//////////////////////////////////////////////////////////////////////
939
 
940
// LFSR counter
941
module cnt_lfsr_zq ( zq, rst, clk);
942
 
943
   parameter length = 4;
944
   output reg zq;
945
   input rst;
946
   input clk;
947
 
948
   parameter clear_value = 0;
949
   parameter set_value = 1;
950
   parameter wrap_value = 8;
951
   parameter level1_value = 15;
952
 
953
   reg  [length:1] qi;
954
   reg lfsr_fb;
955
   wire [length:1] q_next;
956
   reg [32:1] polynom;
957
   integer i;
958
 
959
   always @ (qi)
960
   begin
961
        case (length)
962
         2: polynom = 32'b11;                               // 0x3
963
         3: polynom = 32'b110;                              // 0x6
964
         4: polynom = 32'b1100;                             // 0xC
965
         5: polynom = 32'b10100;                            // 0x14
966
         6: polynom = 32'b110000;                           // 0x30
967
         7: polynom = 32'b1100000;                          // 0x60
968
         8: polynom = 32'b10111000;                         // 0xb8
969
         9: polynom = 32'b100010000;                        // 0x110
970
        10: polynom = 32'b1001000000;                       // 0x240
971
        11: polynom = 32'b10100000000;                      // 0x500
972
        12: polynom = 32'b100000101001;                     // 0x829
973
        13: polynom = 32'b1000000001100;                    // 0x100C
974
        14: polynom = 32'b10000000010101;                   // 0x2015
975
        15: polynom = 32'b110000000000000;                  // 0x6000
976
        16: polynom = 32'b1101000000001000;                 // 0xD008
977
        17: polynom = 32'b10010000000000000;                // 0x12000
978
        18: polynom = 32'b100000010000000000;               // 0x20400
979
        19: polynom = 32'b1000000000000100011;              // 0x40023
980
        20: polynom = 32'b10000010000000000000;             // 0x82000
981
        21: polynom = 32'b101000000000000000000;            // 0x140000
982
        22: polynom = 32'b1100000000000000000000;           // 0x300000
983
        23: polynom = 32'b10000100000000000000000;          // 0x420000
984
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
985
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
986
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
987
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
988
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
989
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
990
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
991
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
992
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
993
        default: polynom = 32'b0;
994
        endcase
995
        lfsr_fb = qi[length];
996
        for (i=length-1; i>=1; i=i-1) begin
997
            if (polynom[i])
998
                lfsr_fb = lfsr_fb  ~^ qi[i];
999
        end
1000
    end
1001
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1002
 
1003
   always @ (posedge clk or posedge rst)
1004
     if (rst)
1005
       qi <= {length{1'b0}};
1006
     else
1007
       qi <= q_next;
1008
 
1009
 
1010
 
1011
   always @ (posedge clk or posedge rst)
1012
     if (rst)
1013
       zq <= 1'b1;
1014
     else
1015
       zq <= q_next == {length{1'b0}};
1016
endmodule
1017
//////////////////////////////////////////////////////////////////////
1018
////                                                              ////
1019
////  Versatile counter                                           ////
1020
////                                                              ////
1021
////  Description                                                 ////
1022
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1023
////  counter                                                     ////
1024
////                                                              ////
1025
////  To Do:                                                      ////
1026
////   - add LFSR with more taps                                  ////
1027
////                                                              ////
1028
////  Author(s):                                                  ////
1029
////      - Michael Unneback, unneback@opencores.org              ////
1030
////        ORSoC AB                                              ////
1031
////                                                              ////
1032
//////////////////////////////////////////////////////////////////////
1033
////                                                              ////
1034
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1035
////                                                              ////
1036
//// This source file may be used and distributed without         ////
1037
//// restriction provided that this copyright statement is not    ////
1038
//// removed from the file and that any derivative work contains  ////
1039
//// the original copyright notice and the associated disclaimer. ////
1040
////                                                              ////
1041
//// This source file is free software; you can redistribute it   ////
1042
//// and/or modify it under the terms of the GNU Lesser General   ////
1043
//// Public License as published by the Free Software Foundation; ////
1044
//// either version 2.1 of the License, or (at your option) any   ////
1045
//// later version.                                               ////
1046
////                                                              ////
1047
//// This source is distributed in the hope that it will be       ////
1048
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1049
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1050
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1051
//// details.                                                     ////
1052
////                                                              ////
1053
//// You should have received a copy of the GNU Lesser General    ////
1054
//// Public License along with this source; if not, download it   ////
1055
//// from http://www.opencores.org/lgpl.shtml                     ////
1056
////                                                              ////
1057
//////////////////////////////////////////////////////////////////////
1058
 
1059
// LFSR counter
1060
module cnt_lfsr_ce_zq ( cke, zq, rst, clk);
1061
 
1062
   parameter length = 4;
1063
   input cke;
1064
   output reg zq;
1065
   input rst;
1066
   input clk;
1067
 
1068
   parameter clear_value = 0;
1069
   parameter set_value = 1;
1070
   parameter wrap_value = 8;
1071
   parameter level1_value = 15;
1072
 
1073
   reg  [length:1] qi;
1074
   reg lfsr_fb;
1075
   wire [length:1] q_next;
1076
   reg [32:1] polynom;
1077
   integer i;
1078
 
1079
   always @ (qi)
1080
   begin
1081
        case (length)
1082
         2: polynom = 32'b11;                               // 0x3
1083
         3: polynom = 32'b110;                              // 0x6
1084
         4: polynom = 32'b1100;                             // 0xC
1085
         5: polynom = 32'b10100;                            // 0x14
1086
         6: polynom = 32'b110000;                           // 0x30
1087
         7: polynom = 32'b1100000;                          // 0x60
1088
         8: polynom = 32'b10111000;                         // 0xb8
1089
         9: polynom = 32'b100010000;                        // 0x110
1090
        10: polynom = 32'b1001000000;                       // 0x240
1091
        11: polynom = 32'b10100000000;                      // 0x500
1092
        12: polynom = 32'b100000101001;                     // 0x829
1093
        13: polynom = 32'b1000000001100;                    // 0x100C
1094
        14: polynom = 32'b10000000010101;                   // 0x2015
1095
        15: polynom = 32'b110000000000000;                  // 0x6000
1096
        16: polynom = 32'b1101000000001000;                 // 0xD008
1097
        17: polynom = 32'b10010000000000000;                // 0x12000
1098
        18: polynom = 32'b100000010000000000;               // 0x20400
1099
        19: polynom = 32'b1000000000000100011;              // 0x40023
1100
        20: polynom = 32'b10000010000000000000;             // 0x82000
1101
        21: polynom = 32'b101000000000000000000;            // 0x140000
1102
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1103
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1104
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1105
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1106
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1107
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1108
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1109
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1110
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1111
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1112
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1113
        default: polynom = 32'b0;
1114
        endcase
1115
        lfsr_fb = qi[length];
1116
        for (i=length-1; i>=1; i=i-1) begin
1117
            if (polynom[i])
1118
                lfsr_fb = lfsr_fb  ~^ qi[i];
1119
        end
1120
    end
1121
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1122
 
1123
   always @ (posedge clk or posedge rst)
1124
     if (rst)
1125
       qi <= {length{1'b0}};
1126
     else
1127
     if (cke)
1128
       qi <= q_next;
1129
 
1130
 
1131
 
1132
   always @ (posedge clk or posedge rst)
1133
     if (rst)
1134
       zq <= 1'b1;
1135
     else
1136
     if (cke)
1137
       zq <= q_next == {length{1'b0}};
1138
endmodule
1139
//////////////////////////////////////////////////////////////////////
1140
////                                                              ////
1141
////  Versatile counter                                           ////
1142
////                                                              ////
1143
////  Description                                                 ////
1144
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1145
////  counter                                                     ////
1146
////                                                              ////
1147
////  To Do:                                                      ////
1148
////   - add LFSR with more taps                                  ////
1149
////                                                              ////
1150
////  Author(s):                                                  ////
1151
////      - Michael Unneback, unneback@opencores.org              ////
1152
////        ORSoC AB                                              ////
1153
////                                                              ////
1154
//////////////////////////////////////////////////////////////////////
1155
////                                                              ////
1156
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1157
////                                                              ////
1158
//// This source file may be used and distributed without         ////
1159
//// restriction provided that this copyright statement is not    ////
1160
//// removed from the file and that any derivative work contains  ////
1161
//// the original copyright notice and the associated disclaimer. ////
1162
////                                                              ////
1163
//// This source file is free software; you can redistribute it   ////
1164
//// and/or modify it under the terms of the GNU Lesser General   ////
1165
//// Public License as published by the Free Software Foundation; ////
1166
//// either version 2.1 of the License, or (at your option) any   ////
1167
//// later version.                                               ////
1168
////                                                              ////
1169
//// This source is distributed in the hope that it will be       ////
1170
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1171
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1172
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1173
//// details.                                                     ////
1174
////                                                              ////
1175
//// You should have received a copy of the GNU Lesser General    ////
1176
//// Public License along with this source; if not, download it   ////
1177
//// from http://www.opencores.org/lgpl.shtml                     ////
1178
////                                                              ////
1179
//////////////////////////////////////////////////////////////////////
1180
 
1181
// LFSR counter
1182
module cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk);
1183
 
1184
   parameter length = 4;
1185
   input cke;
1186
   input rew;
1187
   output reg level1;
1188
   input rst;
1189
   input clk;
1190
 
1191
   parameter clear_value = 0;
1192
   parameter set_value = 1;
1193
   parameter wrap_value = 8;
1194
   parameter level1_value = 15;
1195
 
1196
   reg  [length:1] qi;
1197
   reg lfsr_fb, lfsr_fb_rew;
1198
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1199
   reg [32:1] polynom_rew;
1200
   integer j;
1201
   reg [32:1] polynom;
1202
   integer i;
1203
 
1204
   always @ (qi)
1205
   begin
1206
        case (length)
1207
         2: polynom = 32'b11;                               // 0x3
1208
         3: polynom = 32'b110;                              // 0x6
1209
         4: polynom = 32'b1100;                             // 0xC
1210
         5: polynom = 32'b10100;                            // 0x14
1211
         6: polynom = 32'b110000;                           // 0x30
1212
         7: polynom = 32'b1100000;                          // 0x60
1213
         8: polynom = 32'b10111000;                         // 0xb8
1214
         9: polynom = 32'b100010000;                        // 0x110
1215
        10: polynom = 32'b1001000000;                       // 0x240
1216
        11: polynom = 32'b10100000000;                      // 0x500
1217
        12: polynom = 32'b100000101001;                     // 0x829
1218
        13: polynom = 32'b1000000001100;                    // 0x100C
1219
        14: polynom = 32'b10000000010101;                   // 0x2015
1220
        15: polynom = 32'b110000000000000;                  // 0x6000
1221
        16: polynom = 32'b1101000000001000;                 // 0xD008
1222
        17: polynom = 32'b10010000000000000;                // 0x12000
1223
        18: polynom = 32'b100000010000000000;               // 0x20400
1224
        19: polynom = 32'b1000000000000100011;              // 0x40023
1225
        20: polynom = 32'b10000010000000000000;             // 0x82000
1226
        21: polynom = 32'b101000000000000000000;            // 0x140000
1227
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1228
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1229
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1230
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1231
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1232
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1233
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1234
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1235
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1236
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1237
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1238
        default: polynom = 32'b0;
1239
        endcase
1240
        lfsr_fb = qi[length];
1241
        for (i=length-1; i>=1; i=i-1) begin
1242
            if (polynom[i])
1243
                lfsr_fb = lfsr_fb  ~^ qi[i];
1244
        end
1245
    end
1246
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1247
   always @ (qi)
1248
   begin
1249
        case (length)
1250
         2: polynom_rew = 32'b11;
1251
         3: polynom_rew = 32'b110;
1252
         4: polynom_rew = 32'b1100;
1253
         5: polynom_rew = 32'b10100;
1254
         6: polynom_rew = 32'b110000;
1255
         7: polynom_rew = 32'b1100000;
1256
         8: polynom_rew = 32'b10111000;
1257
         9: polynom_rew = 32'b100010000;
1258
        10: polynom_rew = 32'b1001000000;
1259
        11: polynom_rew = 32'b10100000000;
1260
        12: polynom_rew = 32'b100000101001;
1261
        13: polynom_rew = 32'b1000000001100;
1262
        14: polynom_rew = 32'b10000000010101;
1263
        15: polynom_rew = 32'b110000000000000;
1264
        16: polynom_rew = 32'b1101000000001000;
1265
        17: polynom_rew = 32'b10010000000000000;
1266
        18: polynom_rew = 32'b100000010000000000;
1267
        19: polynom_rew = 32'b1000000000000100011;
1268
        20: polynom_rew = 32'b10000010000000000000;
1269
        21: polynom_rew = 32'b101000000000000000000;
1270
        22: polynom_rew = 32'b1100000000000000000000;
1271
        23: polynom_rew = 32'b10000100000000000000000;
1272
        24: polynom_rew = 32'b111000010000000000000000;
1273
        25: polynom_rew = 32'b1001000000000000000000000;
1274
        26: polynom_rew = 32'b10000000000000000000100011;
1275
        27: polynom_rew = 32'b100000000000000000000010011;
1276
        28: polynom_rew = 32'b1100100000000000000000000000;
1277
        29: polynom_rew = 32'b10100000000000000000000000000;
1278
        30: polynom_rew = 32'b100000000000000000000000101001;
1279
        31: polynom_rew = 32'b1001000000000000000000000000000;
1280
        32: polynom_rew = 32'b10000000001000000000000000000011;
1281
        default: polynom_rew = 32'b0;
1282
        endcase
1283
        // rotate left
1284
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
1285
        lfsr_fb_rew = qi[length];
1286
        for (i=length-1; i>=1; i=i-1) begin
1287
            if (polynom_rew[i])
1288
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
1289
        end
1290
    end
1291
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
1292
   assign q_next = rew ? q_next_rew : q_next_fw;
1293
 
1294
   always @ (posedge clk or posedge rst)
1295
     if (rst)
1296
       qi <= {length{1'b0}};
1297
     else
1298
     if (cke)
1299
       qi <= q_next;
1300
 
1301
 
1302
 
1303
    always @ (posedge clk or posedge rst)
1304
    if (rst)
1305
        level1 <= 1'b0;
1306
    else
1307
    if (cke)
1308
    if (q_next == level1_value)
1309
        level1 <= 1'b1;
1310
    else if (qi == level1_value & rew)
1311
        level1 <= 1'b0;
1312
endmodule
1313
//////////////////////////////////////////////////////////////////////
1314
////                                                              ////
1315
////  Versatile counter                                           ////
1316
////                                                              ////
1317
////  Description                                                 ////
1318
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1319
////  counter                                                     ////
1320
////                                                              ////
1321
////  To Do:                                                      ////
1322
////   - add LFSR with more taps                                  ////
1323
////                                                              ////
1324
////  Author(s):                                                  ////
1325
////      - Michael Unneback, unneback@opencores.org              ////
1326
////        ORSoC AB                                              ////
1327
////                                                              ////
1328
//////////////////////////////////////////////////////////////////////
1329
////                                                              ////
1330
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1331
////                                                              ////
1332
//// This source file may be used and distributed without         ////
1333
//// restriction provided that this copyright statement is not    ////
1334
//// removed from the file and that any derivative work contains  ////
1335
//// the original copyright notice and the associated disclaimer. ////
1336
////                                                              ////
1337
//// This source file is free software; you can redistribute it   ////
1338
//// and/or modify it under the terms of the GNU Lesser General   ////
1339
//// Public License as published by the Free Software Foundation; ////
1340
//// either version 2.1 of the License, or (at your option) any   ////
1341
//// later version.                                               ////
1342
////                                                              ////
1343
//// This source is distributed in the hope that it will be       ////
1344
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1345
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1346
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1347
//// details.                                                     ////
1348
////                                                              ////
1349
//// You should have received a copy of the GNU Lesser General    ////
1350
//// Public License along with this source; if not, download it   ////
1351
//// from http://www.opencores.org/lgpl.shtml                     ////
1352
////                                                              ////
1353
//////////////////////////////////////////////////////////////////////
1354
 
1355
// GRAY counter
1356
module cnt_gray ( q, rst, clk);
1357
 
1358
   parameter length = 4;
1359
   output reg [length:1] q;
1360
   input rst;
1361
   input clk;
1362
 
1363
   parameter clear_value = 0;
1364
   parameter set_value = 1;
1365
   parameter wrap_value = 8;
1366
   parameter level1_value = 15;
1367
 
1368
   reg  [length:1] qi;
1369
   wire [length:1] q_next;
1370
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1371
 
1372
   always @ (posedge clk or posedge rst)
1373
     if (rst)
1374
       qi <= {length{1'b0}};
1375
     else
1376
       qi <= q_next;
1377
 
1378
   always @ (posedge clk or posedge rst)
1379
     if (rst)
1380
       q <= {length{1'b0}};
1381
     else
1382
         q <= (q_next>>1) ^ q_next;
1383
 
1384
endmodule
1385
//////////////////////////////////////////////////////////////////////
1386
////                                                              ////
1387
////  Versatile counter                                           ////
1388
////                                                              ////
1389
////  Description                                                 ////
1390
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1391
////  counter                                                     ////
1392
////                                                              ////
1393
////  To Do:                                                      ////
1394
////   - add LFSR with more taps                                  ////
1395
////                                                              ////
1396
////  Author(s):                                                  ////
1397
////      - Michael Unneback, unneback@opencores.org              ////
1398
////        ORSoC AB                                              ////
1399
////                                                              ////
1400
//////////////////////////////////////////////////////////////////////
1401
////                                                              ////
1402
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1403
////                                                              ////
1404
//// This source file may be used and distributed without         ////
1405
//// restriction provided that this copyright statement is not    ////
1406
//// removed from the file and that any derivative work contains  ////
1407
//// the original copyright notice and the associated disclaimer. ////
1408
////                                                              ////
1409
//// This source file is free software; you can redistribute it   ////
1410
//// and/or modify it under the terms of the GNU Lesser General   ////
1411
//// Public License as published by the Free Software Foundation; ////
1412
//// either version 2.1 of the License, or (at your option) any   ////
1413
//// later version.                                               ////
1414
////                                                              ////
1415
//// This source is distributed in the hope that it will be       ////
1416
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1417
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1418
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1419
//// details.                                                     ////
1420
////                                                              ////
1421
//// You should have received a copy of the GNU Lesser General    ////
1422
//// Public License along with this source; if not, download it   ////
1423
//// from http://www.opencores.org/lgpl.shtml                     ////
1424
////                                                              ////
1425
//////////////////////////////////////////////////////////////////////
1426
 
1427
// GRAY counter
1428
module cnt_gray_ce ( cke, q, rst, clk);
1429
 
1430
   parameter length = 4;
1431
   input cke;
1432
   output reg [length:1] q;
1433
   input rst;
1434
   input clk;
1435
 
1436
   parameter clear_value = 0;
1437
   parameter set_value = 1;
1438
   parameter wrap_value = 8;
1439
   parameter level1_value = 15;
1440
 
1441
   reg  [length:1] qi;
1442
   wire [length:1] q_next;
1443
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1444
 
1445
   always @ (posedge clk or posedge rst)
1446
     if (rst)
1447
       qi <= {length{1'b0}};
1448
     else
1449
     if (cke)
1450
       qi <= q_next;
1451
 
1452
   always @ (posedge clk or posedge rst)
1453
     if (rst)
1454
       q <= {length{1'b0}};
1455
     else
1456
       if (cke)
1457
         q <= (q_next>>1) ^ q_next;
1458
 
1459
endmodule
1460
//////////////////////////////////////////////////////////////////////
1461
////                                                              ////
1462
////  Versatile counter                                           ////
1463
////                                                              ////
1464
////  Description                                                 ////
1465
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1466
////  counter                                                     ////
1467
////                                                              ////
1468
////  To Do:                                                      ////
1469
////   - add LFSR with more taps                                  ////
1470
////                                                              ////
1471
////  Author(s):                                                  ////
1472
////      - Michael Unneback, unneback@opencores.org              ////
1473
////        ORSoC AB                                              ////
1474
////                                                              ////
1475
//////////////////////////////////////////////////////////////////////
1476
////                                                              ////
1477
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1478
////                                                              ////
1479
//// This source file may be used and distributed without         ////
1480
//// restriction provided that this copyright statement is not    ////
1481
//// removed from the file and that any derivative work contains  ////
1482
//// the original copyright notice and the associated disclaimer. ////
1483
////                                                              ////
1484
//// This source file is free software; you can redistribute it   ////
1485
//// and/or modify it under the terms of the GNU Lesser General   ////
1486
//// Public License as published by the Free Software Foundation; ////
1487
//// either version 2.1 of the License, or (at your option) any   ////
1488
//// later version.                                               ////
1489
////                                                              ////
1490
//// This source is distributed in the hope that it will be       ////
1491
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1492
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1493
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1494
//// details.                                                     ////
1495
////                                                              ////
1496
//// You should have received a copy of the GNU Lesser General    ////
1497
//// Public License along with this source; if not, download it   ////
1498
//// from http://www.opencores.org/lgpl.shtml                     ////
1499
////                                                              ////
1500
//////////////////////////////////////////////////////////////////////
1501
 
1502
// GRAY counter
1503
module cnt_gray_ce_bin ( cke, q, q_bin, rst, clk);
1504
 
1505
   parameter length = 4;
1506
   input cke;
1507
   output reg [length:1] q;
1508
   output [length:1] q_bin;
1509
   input rst;
1510
   input clk;
1511
 
1512
   parameter clear_value = 0;
1513
   parameter set_value = 1;
1514
   parameter wrap_value = 8;
1515
   parameter level1_value = 15;
1516
 
1517
   reg  [length:1] qi;
1518
   wire [length:1] q_next;
1519
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1520
 
1521
   always @ (posedge clk or posedge rst)
1522
     if (rst)
1523
       qi <= {length{1'b0}};
1524
     else
1525
     if (cke)
1526
       qi <= q_next;
1527
 
1528
   always @ (posedge clk or posedge rst)
1529
     if (rst)
1530
       q <= {length{1'b0}};
1531
     else
1532
       if (cke)
1533
         q <= (q_next>>1) ^ q_next;
1534
 
1535
   assign q_bin = qi;
1536
 
1537
endmodule
1538
//////////////////////////////////////////////////////////////////////
1539
////                                                              ////
1540
////  Versatile library, counters                                 ////
1541
////                                                              ////
1542
////  Description                                                 ////
1543
////  counters                                                    ////
1544
////                                                              ////
1545
////                                                              ////
1546
////  To Do:                                                      ////
1547
////   - add more counters                                        ////
1548
////                                                              ////
1549
////  Author(s):                                                  ////
1550
////      - Michael Unneback, unneback@opencores.org              ////
1551
////        ORSoC AB                                              ////
1552
////                                                              ////
1553
//////////////////////////////////////////////////////////////////////
1554
////                                                              ////
1555
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1556
////                                                              ////
1557
//// This source file may be used and distributed without         ////
1558
//// restriction provided that this copyright statement is not    ////
1559
//// removed from the file and that any derivative work contains  ////
1560
//// the original copyright notice and the associated disclaimer. ////
1561
////                                                              ////
1562
//// This source file is free software; you can redistribute it   ////
1563
//// and/or modify it under the terms of the GNU Lesser General   ////
1564
//// Public License as published by the Free Software Foundation; ////
1565
//// either version 2.1 of the License, or (at your option) any   ////
1566
//// later version.                                               ////
1567
////                                                              ////
1568
//// This source is distributed in the hope that it will be       ////
1569
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1570
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1571
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1572
//// details.                                                     ////
1573
////                                                              ////
1574
//// You should have received a copy of the GNU Lesser General    ////
1575
//// Public License along with this source; if not, download it   ////
1576
//// from http://www.opencores.org/lgpl.shtml                     ////
1577
////                                                              ////
1578
//////////////////////////////////////////////////////////////////////
1579
 
1580
module cnt_shreg_wrap ( q, rst, clk);
1581
 
1582
   parameter length = 4;
1583
   output reg [0:length-1] q;
1584
   input rst;
1585
   input clk;
1586
 
1587
    always @ (posedge clk or posedge rst)
1588
    if (rst)
1589
        q <= {1'b1,{length-1{1'b0}}};
1590
    else
1591
        q <= {q[length-1],q[0:length-2]};
1592
 
1593
endmodule
1594
 
1595
module cnt_shreg_ce_wrap ( cke, q, rst, clk);
1596
 
1597
   parameter length = 4;
1598
   input cke;
1599
   output reg [0:length-1] q;
1600
   input rst;
1601
   input clk;
1602
 
1603
    always @ (posedge clk or posedge rst)
1604
    if (rst)
1605
        q <= {1'b1,{length-1{1'b0}}};
1606
    else
1607
        if (cke)
1608
            q <= {q[length-1],q[0:length-2]};
1609
 
1610
endmodule
1611
 
1612
module cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
1613
 
1614
   parameter length = 4;
1615
   input cke, clear;
1616
   output reg [0:length-1] q;
1617
   input rst;
1618
   input clk;
1619
 
1620
    always @ (posedge clk or posedge rst)
1621
    if (rst)
1622
        q <= {1'b1,{length-1{1'b0}}};
1623
    else
1624
        if (cke)
1625
            if (clear)
1626
                q <= {1'b1,{length-1{1'b0}}};
1627
            else
1628
                q <= q >> 1;
1629
 
1630
endmodule
1631
 
1632
module cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
1633
 
1634
   parameter length = 4;
1635
   input cke, clear;
1636
   output reg [0:length-1] q;
1637
   input rst;
1638
   input clk;
1639
 
1640
    always @ (posedge clk or posedge rst)
1641
    if (rst)
1642
        q <= {1'b1,{length-1{1'b0}}};
1643
    else
1644
        if (cke)
1645
            if (clear)
1646
                q <= {1'b1,{length-1{1'b0}}};
1647
            else
1648
            q <= {q[length-1],q[0:length-2]};
1649
 
1650
endmodule
1651
//////////////////////////////////////////////////////////////////////
1652
////                                                              ////
1653
////  Versatile library, memories                                 ////
1654
////                                                              ////
1655
////  Description                                                 ////
1656
////  memories                                                    ////
1657
////                                                              ////
1658
////                                                              ////
1659
////  To Do:                                                      ////
1660
////   - add more memory types                                    ////
1661
////                                                              ////
1662
////  Author(s):                                                  ////
1663
////      - Michael Unneback, unneback@opencores.org              ////
1664
////        ORSoC AB                                              ////
1665
////                                                              ////
1666
//////////////////////////////////////////////////////////////////////
1667
////                                                              ////
1668
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1669
////                                                              ////
1670
//// This source file may be used and distributed without         ////
1671
//// restriction provided that this copyright statement is not    ////
1672
//// removed from the file and that any derivative work contains  ////
1673
//// the original copyright notice and the associated disclaimer. ////
1674
////                                                              ////
1675
//// This source file is free software; you can redistribute it   ////
1676
//// and/or modify it under the terms of the GNU Lesser General   ////
1677
//// Public License as published by the Free Software Foundation; ////
1678
//// either version 2.1 of the License, or (at your option) any   ////
1679
//// later version.                                               ////
1680
////                                                              ////
1681
//// This source is distributed in the hope that it will be       ////
1682
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1683
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1684
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1685
//// details.                                                     ////
1686
////                                                              ////
1687
//// You should have received a copy of the GNU Lesser General    ////
1688
//// Public License along with this source; if not, download it   ////
1689
//// from http://www.opencores.org/lgpl.shtml                     ////
1690
////                                                              ////
1691
//////////////////////////////////////////////////////////////////////
1692
 
1693
/// ROM
1694
 
1695 7 unneback
module vl_rom_init ( adr, q, clk);
1696
   parameter data_width = 32;
1697
   parameter addr_width = 8;
1698
   input [(addr_width-1):0]       adr;
1699
   output reg [(data_width-1):0] q;
1700
   input                         clk;
1701
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
1702
   parameter memory_file = "vl_rom.vmem";
1703
   initial
1704
     begin
1705
        $readmemh(memory_file, rom);
1706
     end
1707
 
1708
   always @ (posedge clk)
1709
     q <= rom[adr];
1710 6 unneback
 
1711 7 unneback
endmodule
1712
 
1713 14 unneback
/*
1714 7 unneback
module vl_rom ( adr, q, clk);
1715
 
1716 6 unneback
parameter data_width = 32;
1717
parameter addr_width = 4;
1718
 
1719
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
1720
    {32'h18000000},
1721
    {32'hA8200000},
1722
    {32'hA8200000},
1723
    {32'hA8200000},
1724
    {32'h44003000},
1725
    {32'h15000000},
1726
    {32'h15000000},
1727
    {32'h15000000},
1728
    {32'h15000000},
1729
    {32'h15000000},
1730
    {32'h15000000},
1731
    {32'h15000000},
1732
    {32'h15000000},
1733
    {32'h15000000},
1734
    {32'h15000000},
1735
    {32'h15000000}};
1736
 
1737 7 unneback
input [addr_width-1:0] adr;
1738 6 unneback
output reg [data_width-1:0] q;
1739
input clk;
1740
 
1741
always @ (posedge clk)
1742 7 unneback
    q <= data[adr];
1743 6 unneback
 
1744
endmodule
1745 14 unneback
*/
1746 6 unneback
// Single port RAM
1747
 
1748
module vl_ram ( d, adr, we, q, clk);
1749
   parameter data_width = 32;
1750
   parameter addr_width = 8;
1751
   input [(data_width-1):0]      d;
1752
   input [(addr_width-1):0]       adr;
1753
   input                         we;
1754 7 unneback
   output reg [(data_width-1):0] q;
1755 6 unneback
   input                         clk;
1756
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
1757 7 unneback
   parameter init = 0;
1758
   parameter memory_file = "vl_ram.vmem";
1759
   generate if (init) begin : init_mem
1760
   initial
1761
     begin
1762
        $readmemh(memory_file, ram);
1763
     end
1764
   end
1765
   endgenerate
1766
 
1767 6 unneback
   always @ (posedge clk)
1768
   begin
1769
   if (we)
1770
     ram[adr] <= d;
1771
   q <= ram[adr];
1772
   end
1773
 
1774
endmodule
1775
 
1776 7 unneback
module vl_ram_be ( d, adr, be, we, q, clk);
1777
   parameter data_width = 32;
1778
   parameter addr_width = 8;
1779
   input [(data_width-1):0]      d;
1780
   input [(addr_width-1):0]       adr;
1781
   input [(addr_width/4)-1:0]    be;
1782
   input                         we;
1783
   output reg [(data_width-1):0] q;
1784
   input                         clk;
1785
 
1786
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
1787
 
1788
   parameter init = 0;
1789
   parameter memory_file = "vl_ram.vmem";
1790
   generate if (init) begin : init_mem
1791
   initial
1792
     begin
1793
        $readmemh(memory_file, ram);
1794
     end
1795
   end
1796
   endgenerate
1797
 
1798
   genvar i;
1799
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
1800
      always @ (posedge clk)
1801
      if (we & be[i])
1802
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
1803
   end
1804
   endgenerate
1805
 
1806
   always @ (posedge clk)
1807
      q <= ram[adr];
1808
 
1809
endmodule
1810
 
1811
 
1812 6 unneback
// Dual port RAM
1813
 
1814
// ACTEL FPGA should not use logic to handle rw collision
1815
`ifdef ACTEL
1816
        `define SYN /*synthesis syn_ramstyle = "no_rw_check"*/
1817
`else
1818
        `define SYN
1819
`endif
1820
 
1821 7 unneback
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1822 6 unneback
   parameter data_width = 32;
1823
   parameter addr_width = 8;
1824
   input [(data_width-1):0]      d_a;
1825
   input [(addr_width-1):0]       adr_a;
1826
   input [(addr_width-1):0]       adr_b;
1827
   input                         we_a;
1828
   output [(data_width-1):0]      q_b;
1829
   input                         clk_a, clk_b;
1830
   reg [(addr_width-1):0]         adr_b_reg;
1831
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
1832 7 unneback
 
1833
   parameter init = 0;
1834
   parameter memory_file = "vl_ram.vmem";
1835
   generate if (init) begin : init_mem
1836
   initial
1837
     begin
1838
        $readmemh(memory_file, ram);
1839
     end
1840
   end
1841
   endgenerate
1842
 
1843 6 unneback
   always @ (posedge clk_a)
1844
   if (we_a)
1845
     ram[adr_a] <= d_a;
1846
   always @ (posedge clk_b)
1847
   adr_b_reg <= adr_b;
1848
   assign q_b = ram[adr_b_reg];
1849
endmodule
1850
 
1851 7 unneback
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1852 6 unneback
   parameter data_width = 32;
1853
   parameter addr_width = 8;
1854
   input [(data_width-1):0]      d_a;
1855
   input [(addr_width-1):0]       adr_a;
1856
   input [(addr_width-1):0]       adr_b;
1857
   input                         we_a;
1858
   output [(data_width-1):0]      q_b;
1859
   output reg [(data_width-1):0] q_a;
1860
   input                         clk_a, clk_b;
1861
   reg [(data_width-1):0]         q_b;
1862
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
1863 7 unneback
 
1864
   parameter init = 0;
1865
   parameter memory_file = "vl_ram.vmem";
1866
   generate if (init) begin : init_mem
1867
   initial
1868
     begin
1869
        $readmemh(memory_file, ram);
1870
     end
1871
   end
1872
   endgenerate
1873
 
1874 6 unneback
   always @ (posedge clk_a)
1875
     begin
1876
        q_a <= ram[adr_a];
1877
        if (we_a)
1878
             ram[adr_a] <= d_a;
1879
     end
1880
   always @ (posedge clk_b)
1881
          q_b <= ram[adr_b];
1882
endmodule
1883
 
1884 7 unneback
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
1885 6 unneback
   parameter data_width = 32;
1886
   parameter addr_width = 8;
1887
   input [(data_width-1):0]      d_a;
1888
   input [(addr_width-1):0]       adr_a;
1889
   input [(addr_width-1):0]       adr_b;
1890
   input                         we_a;
1891
   output [(data_width-1):0]      q_b;
1892
   input [(data_width-1):0]       d_b;
1893
   output reg [(data_width-1):0] q_a;
1894
   input                         we_b;
1895
   input                         clk_a, clk_b;
1896
   reg [(data_width-1):0]         q_b;
1897
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
1898 7 unneback
 
1899
   parameter init = 0;
1900
   parameter memory_file = "vl_ram.vmem";
1901
   generate if (init) begin : init_mem
1902
   initial
1903
     begin
1904
        $readmemh(memory_file, ram);
1905
     end
1906
   end
1907
   endgenerate
1908
 
1909 6 unneback
   always @ (posedge clk_a)
1910
     begin
1911
        q_a <= ram[adr_a];
1912
        if (we_a)
1913
             ram[adr_a] <= d_a;
1914
     end
1915
   always @ (posedge clk_b)
1916
     begin
1917
        q_b <= ram[adr_b];
1918
        if (we_b)
1919
          ram[adr_b] <= d_b;
1920
     end
1921
endmodule
1922
 
1923
// Content addresable memory, CAM
1924
 
1925
// FIFO
1926
 
1927
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
1928
 
1929 11 unneback
   parameter addr_width = 4;
1930
   parameter N = addr_width-1;
1931 6 unneback
 
1932
   parameter Q1 = 2'b00;
1933
   parameter Q2 = 2'b01;
1934
   parameter Q3 = 2'b11;
1935
   parameter Q4 = 2'b10;
1936
 
1937
   parameter going_empty = 1'b0;
1938
   parameter going_full  = 1'b1;
1939
 
1940
   input [N:0]  wptr, rptr;
1941 14 unneback
   output       fifo_empty;
1942 6 unneback
   output       fifo_full;
1943
   input        wclk, rclk, rst;
1944
 
1945
`ifndef GENERATE_DIRECTION_AS_LATCH
1946
   wire direction;
1947
`endif
1948
`ifdef GENERATE_DIRECTION_AS_LATCH
1949
   reg direction;
1950
`endif
1951
   reg  direction_set, direction_clr;
1952
 
1953
   wire async_empty, async_full;
1954
   wire fifo_full2;
1955 14 unneback
   wire fifo_empty2;
1956 6 unneback
 
1957
   // direction_set
1958
   always @ (wptr[N:N-1] or rptr[N:N-1])
1959
     case ({wptr[N:N-1],rptr[N:N-1]})
1960
       {Q1,Q2} : direction_set <= 1'b1;
1961
       {Q2,Q3} : direction_set <= 1'b1;
1962
       {Q3,Q4} : direction_set <= 1'b1;
1963
       {Q4,Q1} : direction_set <= 1'b1;
1964
       default : direction_set <= 1'b0;
1965
     endcase
1966
 
1967
   // direction_clear
1968
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
1969
     if (rst)
1970
       direction_clr <= 1'b1;
1971
     else
1972
       case ({wptr[N:N-1],rptr[N:N-1]})
1973
         {Q2,Q1} : direction_clr <= 1'b1;
1974
         {Q3,Q2} : direction_clr <= 1'b1;
1975
         {Q4,Q3} : direction_clr <= 1'b1;
1976
         {Q1,Q4} : direction_clr <= 1'b1;
1977
         default : direction_clr <= 1'b0;
1978
       endcase
1979
 
1980
`ifndef GENERATE_DIRECTION_AS_LATCH
1981
    dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
1982
`endif
1983
 
1984
`ifdef GENERATE_DIRECTION_AS_LATCH
1985
   always @ (posedge direction_set or posedge direction_clr)
1986
     if (direction_clr)
1987
       direction <= going_empty;
1988
     else
1989
       direction <= going_full;
1990
`endif
1991
 
1992
   assign async_empty = (wptr == rptr) && (direction==going_empty);
1993
   assign async_full  = (wptr == rptr) && (direction==going_full);
1994
 
1995
    dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
1996
    dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
1997
 
1998
/*
1999
   always @ (posedge wclk or posedge rst or posedge async_full)
2000
     if (rst)
2001
       {fifo_full, fifo_full2} <= 2'b00;
2002
     else if (async_full)
2003
       {fifo_full, fifo_full2} <= 2'b11;
2004
     else
2005
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
2006
*/
2007 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
2008 6 unneback
     if (async_empty)
2009
       {fifo_empty, fifo_empty2} <= 2'b11;
2010
     else
2011 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
2012
    dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
2013
    dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
2014 6 unneback
 
2015
endmodule // async_comp
2016
 
2017
module vl_fifo_1r1w_async (
2018
    d, wr, fifo_full, wr_clk, wr_rst,
2019
    q, rd, fifo_empty, rd_clk, rd_rst
2020
    );
2021
 
2022
parameter data_width = 18;
2023
parameter addr_width = 4;
2024
 
2025
// write side
2026
input  [data_width-1:0] d;
2027
input                   wr;
2028
output                  fifo_full;
2029
input                   wr_clk;
2030
input                   wr_rst;
2031
// read side
2032
output [data_width-1:0] q;
2033
input                   rd;
2034
output                  fifo_empty;
2035
input                   rd_clk;
2036
input                   rd_rst;
2037
 
2038
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
2039
 
2040
vl_fifo_1r1w_async (
2041
    d, wr, fifo_full, wr_clk, wr_rst,
2042
    q, rd, fifo_empty, rd_clk, rd_rst
2043
    );
2044
 
2045 7 unneback
cnt_gray_ce_bin
2046 6 unneback
    # ( .length(addr_width))
2047
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
2048
 
2049 7 unneback
cnt_gray_ce_bin
2050 6 unneback
    # (.length(addr_width))
2051
    fifo_rd_adr( .cke(wr), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_rst));
2052
 
2053 7 unneback
vl_dpram_1r1w
2054 6 unneback
    # (.data_width(data_width), .addr_width(addr_width))
2055
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
2056
 
2057
vl_fifo_cmp_async
2058
    # (.addr_width(addr_width))
2059
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
2060
 
2061
endmodule
2062
 
2063 8 unneback
module vl_fifo_2r2w_async (
2064 6 unneback
    // a side
2065
    a_d, a_wr, a_fifo_full,
2066
    a_q, a_rd, a_fifo_empty,
2067
    a_clk, a_rst,
2068
    // b side
2069
    b_d, b_wr, b_fifo_full,
2070
    b_q, b_rd, b_fifo_empty,
2071
    b_clk, b_rst
2072
    );
2073
 
2074
parameter data_width = 18;
2075
parameter addr_width = 4;
2076
 
2077
// a side
2078
input  [data_width-1:0] a_d;
2079
input                   a_wr;
2080
output                  a_fifo_full;
2081
output [data_width-1:0] a_q;
2082
input                   a_rd;
2083
output                  a_fifo_empty;
2084
input                   a_clk;
2085
input                   a_rst;
2086
 
2087
// b side
2088
input  [data_width-1:0] b_d;
2089
input                   b_wr;
2090
output                  b_fifo_full;
2091
output [data_width-1:0] b_q;
2092
input                   b_rd;
2093
output                  b_fifo_empty;
2094
input                   b_clk;
2095
input                   b_rst;
2096
 
2097
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
2098
vl_fifo_1r1w_async_a (
2099
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
2100
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
2101
    );
2102
 
2103
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
2104
vl_fifo_1r1w_async_b (
2105
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
2106
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
2107
    );
2108
 
2109
endmodule
2110
 
2111 8 unneback
module vl_fifo_2r2w_async_simplex (
2112 6 unneback
    // a side
2113
    a_d, a_wr, a_fifo_full,
2114
    a_q, a_rd, a_fifo_empty,
2115
    a_clk, a_rst,
2116
    // b side
2117
    b_d, b_wr, b_fifo_full,
2118
    b_q, b_rd, b_fifo_empty,
2119
    b_clk, b_rst
2120
    );
2121
 
2122
parameter data_width = 18;
2123
parameter addr_width = 4;
2124
 
2125
// a side
2126
input  [data_width-1:0] a_d;
2127
input                   a_wr;
2128
output                  a_fifo_full;
2129
output [data_width-1:0] a_q;
2130
input                   a_rd;
2131
output                  a_fifo_empty;
2132
input                   a_clk;
2133
input                   a_rst;
2134
 
2135
// b side
2136
input  [data_width-1:0] b_d;
2137
input                   b_wr;
2138
output                  b_fifo_full;
2139
output [data_width-1:0] b_q;
2140
input                   b_rd;
2141
output                  b_fifo_empty;
2142
input                   b_clk;
2143
input                   b_rst;
2144
 
2145
// adr_gen
2146
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
2147
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
2148
// dpram
2149
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
2150
 
2151 7 unneback
cnt_gray_ce_bin
2152 6 unneback
    # ( .length(addr_width))
2153
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
2154
 
2155 7 unneback
cnt_gray_ce_bin
2156 6 unneback
    # (.length(addr_width))
2157
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
2158
 
2159 7 unneback
cnt_gray_ce_bin
2160 6 unneback
    # ( .length(addr_width))
2161
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
2162
 
2163 7 unneback
cnt_gray_ce_bin
2164 6 unneback
    # (.length(addr_width))
2165
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
2166
 
2167
// mux read or write adr to DPRAM
2168
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
2169
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
2170
 
2171 11 unneback
vl_dpram_2r2w
2172 6 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
2173
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
2174
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
2175
 
2176 11 unneback
vl_fifo_cmp_async
2177 6 unneback
    # (.addr_width(addr_width))
2178
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
2179
 
2180 11 unneback
vl_fifo_cmp_async
2181 6 unneback
    # (.addr_width(addr_width))
2182
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
2183
 
2184
endmodule
2185 12 unneback
//////////////////////////////////////////////////////////////////////
2186
////                                                              ////
2187
////  Versatile library, wishbone stuff                           ////
2188
////                                                              ////
2189
////  Description                                                 ////
2190
////  Wishbone compliant modules                                  ////
2191
////                                                              ////
2192
////                                                              ////
2193
////  To Do:                                                      ////
2194
////   -                                                          ////
2195
////                                                              ////
2196
////  Author(s):                                                  ////
2197
////      - Michael Unneback, unneback@opencores.org              ////
2198
////        ORSoC AB                                              ////
2199
////                                                              ////
2200
//////////////////////////////////////////////////////////////////////
2201
////                                                              ////
2202
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2203
////                                                              ////
2204
//// This source file may be used and distributed without         ////
2205
//// restriction provided that this copyright statement is not    ////
2206
//// removed from the file and that any derivative work contains  ////
2207
//// the original copyright notice and the associated disclaimer. ////
2208
////                                                              ////
2209
//// This source file is free software; you can redistribute it   ////
2210
//// and/or modify it under the terms of the GNU Lesser General   ////
2211
//// Public License as published by the Free Software Foundation; ////
2212
//// either version 2.1 of the License, or (at your option) any   ////
2213
//// later version.                                               ////
2214
////                                                              ////
2215
//// This source is distributed in the hope that it will be       ////
2216
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2217
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2218
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2219
//// details.                                                     ////
2220
////                                                              ////
2221
//// You should have received a copy of the GNU Lesser General    ////
2222
//// Public License along with this source; if not, download it   ////
2223
//// from http://www.opencores.org/lgpl.shtml                     ////
2224
////                                                              ////
2225
//////////////////////////////////////////////////////////////////////
2226
 
2227
// async wb3 - wb3 bridge
2228
`timescale 1ns/1ns
2229
module wb3wb3_bridge (
2230
        // wishbone slave side
2231
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
2232
        // wishbone master side
2233
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
2234
 
2235
input [31:0] wbs_dat_i;
2236
input [31:2] wbs_adr_i;
2237
input [3:0]  wbs_sel_i;
2238
input [1:0]  wbs_bte_i;
2239
input [2:0]  wbs_cti_i;
2240
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
2241
output [31:0] wbs_dat_o;
2242 14 unneback
output wbs_ack_o;
2243 12 unneback
input wbs_clk, wbs_rst;
2244
 
2245
output [31:0] wbm_dat_o;
2246
output reg [31:2] wbm_adr_o;
2247
output [3:0]  wbm_sel_o;
2248
output reg [1:0]  wbm_bte_o;
2249
output reg [2:0]  wbm_cti_o;
2250 14 unneback
output reg wbm_we_o;
2251
output wbm_cyc_o;
2252 12 unneback
output wbm_stb_o;
2253
input [31:0]  wbm_dat_i;
2254
input wbm_ack_i;
2255
input wbm_clk, wbm_rst;
2256
 
2257
parameter addr_width = 4;
2258
 
2259
// bte
2260
parameter linear       = 2'b00;
2261
parameter wrap4        = 2'b01;
2262
parameter wrap8        = 2'b10;
2263
parameter wrap16       = 2'b11;
2264
// cti
2265
parameter classic      = 3'b000;
2266
parameter incburst     = 3'b010;
2267
parameter endofburst   = 3'b111;
2268
 
2269
parameter wbs_adr  = 1'b0;
2270
parameter wbs_data = 1'b1;
2271
 
2272
parameter wbm_adr0 = 2'b00;
2273
parameter wbm_adr1 = 2'b01;
2274
parameter wbm_data = 2'b10;
2275
 
2276
reg [1:0] wbs_bte_reg;
2277
reg wbs;
2278
wire wbs_eoc_alert, wbm_eoc_alert;
2279
reg wbs_eoc, wbm_eoc;
2280
reg [1:0] wbm;
2281
 
2282 14 unneback
wire [1:16] wbs_count, wbm_count;
2283 12 unneback
 
2284
wire [35:0] a_d, a_q, b_d, b_q;
2285
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
2286
reg a_rd_reg;
2287
wire b_rd_adr, b_rd_data;
2288 14 unneback
wire b_rd_data_reg;
2289
wire [35:0] temp;
2290 12 unneback
 
2291
`define WE 5
2292
`define BTE 4:3
2293
`define CTI 2:0
2294
 
2295
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
2296
always @ (posedge wbs_clk or posedge wbs_rst)
2297
if (wbs_rst)
2298
        wbs_eoc <= 1'b0;
2299
else
2300
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
2301
                wbs_eoc <= wbs_bte_i==linear;
2302
        else if (wbs_eoc_alert & (a_rd | a_wr))
2303
                wbs_eoc <= 1'b1;
2304
 
2305
cnt_shreg_ce_clear # ( .length(16))
2306
    cnt0 (
2307
        .cke(wbs_ack_o),
2308
        .clear(wbs_eoc),
2309
        .q(wbs_count),
2310
        .rst(wbs_rst),
2311
        .clk(wbs_clk));
2312
 
2313
always @ (posedge wbs_clk or posedge wbs_rst)
2314
if (wbs_rst)
2315
        wbs <= wbs_adr;
2316
else
2317
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & !a_fifo_full)
2318
                wbs <= wbs_data;
2319
        else if (wbs_eoc & wbs_ack_o)
2320
                wbs <= wbs_adr;
2321
 
2322
// wbs FIFO
2323
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,wbs_bte_i,wbs_cti_i} : {wbs_dat_i,wbs_sel_i};
2324
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & !a_fifo_full :
2325
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
2326
              1'b0;
2327
assign a_rd = !a_fifo_empty;
2328
always @ (posedge wbs_clk or posedge wbs_rst)
2329
if (wbs_rst)
2330
        a_rd_reg <= 1'b0;
2331
else
2332
        a_rd_reg <= a_rd;
2333
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
2334
 
2335
assign wbs_dat_o = a_q[35:4];
2336
 
2337
always @ (posedge wbs_clk or posedge wbs_rst)
2338
if (wbs_rst)
2339 13 unneback
        wbs_bte_reg <= 2'b00;
2340 12 unneback
else
2341 13 unneback
        wbs_bte_reg <= wbs_bte_i;
2342 12 unneback
 
2343
// wbm FIFO
2344
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
2345
always @ (posedge wbm_clk or posedge wbm_rst)
2346
if (wbm_rst)
2347
        wbm_eoc <= 1'b0;
2348
else
2349
        if (wbm==wbm_adr0 & !b_fifo_empty)
2350
                wbm_eoc <= b_q[`BTE] == linear;
2351
        else if (wbm_eoc_alert & wbm_ack_i)
2352
                wbm_eoc <= 1'b1;
2353
 
2354
always @ (posedge wbm_clk or posedge wbm_rst)
2355
if (wbm_rst)
2356
        wbm <= wbm_adr0;
2357
else
2358
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
2359
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
2360
        (wbm==wbm_adr1 & !wbm_we_o) |
2361
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
2362
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
2363
 
2364
assign b_d = {wbm_dat_i,4'b1111};
2365
assign b_wr = !wbm_we_o & wbm_ack_i;
2366
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
2367
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
2368
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
2369
                   1'b0;
2370
assign b_rd = b_rd_adr | b_rd_data;
2371
 
2372
dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
2373
dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
2374
 
2375
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
2376
 
2377
cnt_shreg_ce_clear # ( .length(16))
2378
    cnt1 (
2379
        .cke(wbm_ack_i),
2380
        .clear(wbm_eoc),
2381
        .q(wbm_count),
2382
        .rst(wbm_rst),
2383
        .clk(wbm_clk));
2384
 
2385
assign wbm_cyc_o = wbm==wbm_data;
2386
assign wbm_stb_o = (wbm==wbm_data & wbm_we_o) ? !b_fifo_empty :
2387
                   (wbm==wbm_data) ? 1'b1 :
2388
                   1'b0;
2389
 
2390
always @ (posedge wbm_clk or posedge wbm_rst)
2391
if (wbm_rst)
2392
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
2393
else begin
2394
        if (wbm==wbm_adr0 & !b_fifo_empty)
2395
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
2396
        else if (wbm_eoc_alert & wbm_ack_i)
2397
                wbm_cti_o <= endofburst;
2398
end
2399
 
2400
//async_fifo_dw_simplex_top
2401
vl_fifo_2r2w_async_simplex
2402
# ( .data_width(36), .addr_width(addr_width))
2403
fifo (
2404
    // a side
2405
    .a_d(a_d),
2406
    .a_wr(a_wr),
2407
    .a_fifo_full(a_fifo_full),
2408
    .a_q(a_q),
2409
    .a_rd(a_rd),
2410
    .a_fifo_empty(a_fifo_empty),
2411
    .a_clk(wbs_clk),
2412
    .a_rst(wbs_rst),
2413
    // b side
2414
    .b_d(b_d),
2415
    .b_wr(b_wr),
2416
    .b_fifo_full(b_fifo_full),
2417
    .b_q(b_q),
2418
    .b_rd(b_rd),
2419
    .b_fifo_empty(b_fifo_empty),
2420
    .b_clk(wbm_clk),
2421
    .b_rst(wbm_rst)
2422
    );
2423
 
2424
endmodule
2425 17 unneback
 
2426
// WB ROM
2427
module wb_boot_rom (
2428
    wb_adr_i, wb_stb_i, wb_cyc_i,
2429
    wb_dat_o, wb_ack_o, wb_clk, wb_rst);
2430
 
2431
`ifndef BOOT_ROM
2432
`define BOOT_ROM "boot_rom.v"
2433
`endif
2434
    parameter addr_width = 5;
2435
 
2436
   input [(addr_width+2)-1:2]       wb_adr_i;
2437
   input                            wb_stb_i;
2438
   input                            wb_cyc_i;
2439
   output reg [31:0]                 wb_dat_o;
2440
   output reg                       wb_ack_o;
2441
   input                            wb_clk;
2442
   input                            wb_rst;
2443
 
2444
always @ (posedge wb_clk or posedge wb_rst)
2445
    if (wb_rst)
2446
        wb_dat_o <= 32'h15000000;
2447
    else
2448
         case (wb_adr_i)
2449
`include `BOOT_ROM
2450
           /*
2451
            // Zero r0 and jump to 0x00000100
2452
 
2453
            1 : wb_dat_o <= 32'hA8200000;
2454
            2 : wb_dat_o <= 32'hA8C00100;
2455
            3 : wb_dat_o <= 32'h44003000;
2456
            4 : wb_dat_o <= 32'h15000000;
2457
            */
2458
           default:
2459
             wb_dat_o <= 32'h00000000;
2460
 
2461
         endcase // case (wb_adr_i)
2462
 
2463
 
2464
always @ (posedge wb_clk or posedge wb_rst)
2465
    if (wb_rst)
2466
        wb_ack_o <= 1'b0;
2467
    else
2468
        wb_ack_o <= wb_stb_i & wb_cyc_i & !wb_ack_o;
2469
 
2470
endmodule

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