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1 6 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  Versatile library, clock and reset                          ////
4
////                                                              ////
5
////  Description                                                 ////
6
////  Logic related to clock and reset                            ////
7
////                                                              ////
8
////                                                              ////
9
////  To Do:                                                      ////
10
////   - add more different registers                             ////
11
////                                                              ////
12
////  Author(s):                                                  ////
13
////      - Michael Unneback, unneback@opencores.org              ////
14
////        ORSoC AB                                              ////
15
////                                                              ////
16
//////////////////////////////////////////////////////////////////////
17
////                                                              ////
18
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
19
////                                                              ////
20
//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
36
////                                                              ////
37
//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
 
43
// Global buffer
44
// usage:
45
// use to enable global buffers for high fan out signals such as clock and reset
46
 
47
`ifdef ACTEL
48
 
49
`timescale 1 ns/100 ps
50
// Version: 8.4 8.4.0.33
51
module gbuf(GL,CLK);
52
output GL;
53
input  CLK;
54
 
55
    wire GND;
56
 
57
    GND GND_1_net(.Y(GND));
58
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
59
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
60
 
61
endmodule
62
`timescale 1 ns/1 ns
63
module vl_gbuf ( i, o);
64
input i;
65
output o;
66
`ifdef SIM_GBUF
67
assign o=i;
68
`else
69
gbuf gbuf_i0 ( .CLK(i), .GL(o));
70
`endif
71
endmodule
72
`else
73
`ifdef ALTERA
74 21 unneback
//altera
75 6 unneback
`else
76
 
77
`timescale 1 ns/100 ps
78
module vl_gbuf ( i, o);
79
input i;
80
output o;
81
assign o = i;
82
endmodule
83
`endif // ALTERA
84
`endif //ACTEL
85
 
86
// sync reset
87 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
88 6 unneback
// output active high global reset sync with two DFFs 
89
`timescale 1 ns/100 ps
90
module vl_sync_rst ( rst_n_i, rst_o, clk);
91
input rst_n_i, clk;
92
output rst_o;
93 18 unneback
reg [1:0] tmp;
94 6 unneback
always @ (posedge clk or negedge rst_n_i)
95
if (!rst_n_i)
96 17 unneback
        tmp <= 2'b11;
97 6 unneback
else
98 17 unneback
        tmp <= {1'b0,tmp[0]};
99
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
100 6 unneback
endmodule
101
 
102
// vl_pll
103
`ifdef ACTEL
104 17 unneback
`timescale 1 ps/1 ps
105 6 unneback
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
106
parameter index = 0;
107
parameter number_of_clk = 1;
108 17 unneback
parameter period_time_0 = 20000;
109
parameter period_time_1 = 20000;
110
parameter period_time_2 = 20000;
111
parameter lock_delay = 2000000;
112 6 unneback
input clk_i, rst_n_i;
113
output lock;
114
output reg [0:number_of_clk-1] clk_o;
115
output [0:number_of_clk-1] rst_o;
116
 
117
`ifdef SIM_PLL
118
 
119
always
120
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
121
 
122
generate if (number_of_clk > 1)
123
always
124
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
125
endgenerate
126
 
127
generate if (number_of_clk > 2)
128
always
129
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
130
endgenerate
131
 
132
genvar i;
133
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
134
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
135
end
136
endgenerate
137
 
138
assign #lock_delay lock = rst_n_i;
139
 
140
endmodule
141
`else
142
generate if (number_of_clk==1 & index==0) begin
143
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
144
end
145
endgenerate // index==0
146
generate if (number_of_clk==1 & index==1) begin
147
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
148
end
149
endgenerate // index==1
150
generate if (number_of_clk==1 & index==2) begin
151
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
152
end
153
endgenerate // index==2
154
generate if (number_of_clk==1 & index==3) begin
155
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
156
end
157
endgenerate // index==0
158
 
159
generate if (number_of_clk==2 & index==0) begin
160
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
161
end
162
endgenerate // index==0
163
generate if (number_of_clk==2 & index==1) begin
164
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
165
end
166
endgenerate // index==1
167
generate if (number_of_clk==2 & index==2) begin
168
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
169
end
170
endgenerate // index==2
171
generate if (number_of_clk==2 & index==3) begin
172
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
173
end
174
endgenerate // index==0
175
 
176
generate if (number_of_clk==3 & index==0) begin
177
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
178
end
179
endgenerate // index==0
180
generate if (number_of_clk==3 & index==1) begin
181
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
182
end
183
endgenerate // index==1
184
generate if (number_of_clk==3 & index==2) begin
185
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
186
end
187
endgenerate // index==2
188
generate if (number_of_clk==3 & index==3) begin
189
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
190
end
191
endgenerate // index==0
192
 
193
genvar i;
194
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
195
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
196
end
197
endgenerate
198
endmodule
199
`endif
200
 
201
`else
202
 
203
`ifdef ALTERA
204
 
205
`else
206
 
207
// generic PLL
208 17 unneback
`timescale 1 ps/1 ps
209 6 unneback
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
210
parameter index = 0;
211
parameter number_of_clk = 1;
212 17 unneback
parameter period_time_0 = 20000;
213
parameter period_time_1 = 20000;
214
parameter period_time_2 = 20000;
215 6 unneback
parameter lock_delay = 2000;
216
input clk_i, rst_n_i;
217
output lock;
218
output reg [0:number_of_clk-1] clk_o;
219
output [0:number_of_clk-1] rst_o;
220
 
221
always
222
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
223
 
224
generate if (number_of_clk > 1)
225
always
226
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
227
endgenerate
228
 
229
generate if (number_of_clk > 2)
230
always
231
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
232
endgenerate
233
 
234
genvar i;
235
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
236
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
237
end
238
endgenerate
239
 
240
assign #lock_delay lock = rst_n_i;
241
 
242
endmodule
243
 
244
`endif //altera
245 17 unneback
`endif //actel
246
//////////////////////////////////////////////////////////////////////
247 6 unneback
////                                                              ////
248
////  Versatile library, registers                                ////
249
////                                                              ////
250
////  Description                                                 ////
251
////  Different type of registers                                 ////
252
////                                                              ////
253
////                                                              ////
254
////  To Do:                                                      ////
255
////   - add more different registers                             ////
256
////                                                              ////
257
////  Author(s):                                                  ////
258
////      - Michael Unneback, unneback@opencores.org              ////
259
////        ORSoC AB                                              ////
260
////                                                              ////
261
//////////////////////////////////////////////////////////////////////
262
////                                                              ////
263
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
264
////                                                              ////
265
//// This source file may be used and distributed without         ////
266
//// restriction provided that this copyright statement is not    ////
267
//// removed from the file and that any derivative work contains  ////
268
//// the original copyright notice and the associated disclaimer. ////
269
////                                                              ////
270
//// This source file is free software; you can redistribute it   ////
271
//// and/or modify it under the terms of the GNU Lesser General   ////
272
//// Public License as published by the Free Software Foundation; ////
273
//// either version 2.1 of the License, or (at your option) any   ////
274
//// later version.                                               ////
275
////                                                              ////
276
//// This source is distributed in the hope that it will be       ////
277
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
278
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
279
//// PURPOSE.  See the GNU Lesser General Public License for more ////
280
//// details.                                                     ////
281
////                                                              ////
282
//// You should have received a copy of the GNU Lesser General    ////
283
//// Public License along with this source; if not, download it   ////
284
//// from http://www.opencores.org/lgpl.shtml                     ////
285
////                                                              ////
286
//////////////////////////////////////////////////////////////////////
287
 
288 18 unneback
module vl_dff ( d, q, clk, rst);
289 6 unneback
 
290
        parameter width = 1;
291
        parameter reset_value = 0;
292
 
293
        input [width-1:0] d;
294
        input clk, rst;
295
        output reg [width-1:0] q;
296
 
297
        always @ (posedge clk or posedge rst)
298
        if (rst)
299
                q <= reset_value;
300
        else
301
                q <= d;
302
 
303
endmodule
304
 
305 18 unneback
module vl_dff_array ( d, q, clk, rst);
306 6 unneback
 
307
        parameter width = 1;
308
        parameter depth = 2;
309
        parameter reset_value = 1'b0;
310
 
311
        input [width-1:0] d;
312
        input clk, rst;
313
        output [width-1:0] q;
314
        reg  [0:depth-1] q_tmp [width-1:0];
315
        integer i;
316
        always @ (posedge clk or posedge rst)
317
        if (rst) begin
318
            for (i=0;i<depth;i=i+1)
319
                q_tmp[i] <= {width{reset_value}};
320
        end else begin
321
            q_tmp[0] <= d;
322
            for (i=1;i<depth;i=i+1)
323
                q_tmp[i] <= q_tmp[i-1];
324
        end
325
 
326
    assign q = q_tmp[depth-1];
327
 
328
endmodule
329
 
330 18 unneback
module vl_dff_ce ( d, ce, q, clk, rst);
331 6 unneback
 
332
        parameter width = 1;
333
        parameter reset_value = 0;
334
 
335
        input [width-1:0] d;
336
        input ce, clk, rst;
337
        output reg [width-1:0] q;
338
 
339
        always @ (posedge clk or posedge rst)
340
        if (rst)
341
                q <= reset_value;
342
        else
343
                if (ce)
344
                        q <= d;
345
 
346
endmodule
347
 
348 18 unneback
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
349 8 unneback
 
350
        parameter width = 1;
351
        parameter reset_value = 0;
352
 
353
        input [width-1:0] d;
354 10 unneback
        input ce, clear, clk, rst;
355 8 unneback
        output reg [width-1:0] q;
356
 
357
        always @ (posedge clk or posedge rst)
358
        if (rst)
359
            q <= reset_value;
360
        else
361
            if (ce)
362
                if (clear)
363
                    q <= {width{1'b0}};
364
                else
365
                    q <= d;
366
 
367
endmodule
368
 
369 24 unneback
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
370
 
371
        parameter width = 1;
372
        parameter reset_value = 0;
373
 
374
        input [width-1:0] d;
375
        input ce, set, clk, rst;
376
        output reg [width-1:0] q;
377
 
378
        always @ (posedge clk or posedge rst)
379
        if (rst)
380
            q <= reset_value;
381
        else
382
            if (ce)
383
                if (set)
384
                    q <= {width{1'b1}};
385
                else
386
                    q <= d;
387
 
388
endmodule
389
 
390 6 unneback
`ifdef ALTERA
391
// megafunction wizard: %LPM_FF%
392
// GENERATION: STANDARD
393
// VERSION: WM1.0
394
// MODULE: lpm_ff 
395
 
396
// ============================================================
397
// File Name: dff_sr.v
398
// Megafunction Name(s):
399
//                      lpm_ff
400
//
401
// Simulation Library Files(s):
402
//                      lpm
403
// ============================================================
404
// ************************************************************
405
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
406
//
407
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
408
// ************************************************************
409
 
410
 
411
//Copyright (C) 1991-2010 Altera Corporation
412
//Your use of Altera Corporation's design tools, logic functions 
413
//and other software and tools, and its AMPP partner logic 
414
//functions, and any output files from any of the foregoing 
415
//(including device programming or simulation files), and any 
416
//associated documentation or information are expressly subject 
417
//to the terms and conditions of the Altera Program License 
418
//Subscription Agreement, Altera MegaCore Function License 
419
//Agreement, or other applicable license agreement, including, 
420
//without limitation, that your use is for the sole purpose of 
421
//programming logic devices manufactured by Altera and sold by 
422
//Altera or its authorized distributors.  Please refer to the 
423
//applicable agreement for further details.
424
 
425
 
426
// synopsys translate_off
427
`timescale 1 ps / 1 ps
428
// synopsys translate_on
429 18 unneback
module vl_dff_sr (
430 6 unneback
        aclr,
431
        aset,
432
        clock,
433
        data,
434
        q);
435
 
436
        input     aclr;
437
        input     aset;
438
        input     clock;
439
        input     data;
440
        output    q;
441
 
442
        wire [0:0] sub_wire0;
443
        wire [0:0] sub_wire1 = sub_wire0[0:0];
444
        wire  q = sub_wire1;
445
        wire  sub_wire2 = data;
446
        wire  sub_wire3 = sub_wire2;
447
 
448
        lpm_ff  lpm_ff_component (
449
                                .aclr (aclr),
450
                                .clock (clock),
451
                                .data (sub_wire3),
452
                                .aset (aset),
453
                                .q (sub_wire0)
454
                                // synopsys translate_off
455
                                ,
456
                                .aload (),
457
                                .enable (),
458
                                .sclr (),
459
                                .sload (),
460
                                .sset ()
461
                                // synopsys translate_on
462
                                );
463
        defparam
464
                lpm_ff_component.lpm_fftype = "DFF",
465
                lpm_ff_component.lpm_type = "LPM_FF",
466
                lpm_ff_component.lpm_width = 1;
467
 
468
 
469
endmodule
470
 
471
// ============================================================
472
// CNX file retrieval info
473
// ============================================================
474
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
475
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
476
// Retrieval info: PRIVATE: ASET NUMERIC "1"
477
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
478
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
479
// Retrieval info: PRIVATE: DFF NUMERIC "1"
480
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
481
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
482
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
483
// Retrieval info: PRIVATE: SSET NUMERIC "0"
484
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
485
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
486
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
487
// Retrieval info: PRIVATE: nBit NUMERIC "1"
488
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
489
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
490
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
491
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
492
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
493
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
494
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
495
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
496
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
497
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
498
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
499
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
500
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
501
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
502
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
503
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
504
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
505
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
506
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
507
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
508
// Retrieval info: LIB_FILE: lpm
509
 
510
 
511
`else
512
 
513
 
514 18 unneback
module vl_dff_sr ( aclr, aset, clock, data, q);
515 6 unneback
 
516
    input         aclr;
517
    input         aset;
518
    input         clock;
519
    input         data;
520
    output reg    q;
521
 
522
   always @ (posedge clock or posedge aclr or posedge aset)
523
     if (aclr)
524
       q <= 1'b0;
525
     else if (aset)
526
       q <= 1'b1;
527
     else
528
       q <= data;
529
 
530
endmodule
531
 
532
`endif
533
 
534
// LATCH
535
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
536
`ifdef ALTERA
537 18 unneback
module vl_latch ( d, le, q, clk);
538 6 unneback
input d, le;
539
output q;
540
input clk;
541
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
542
endmodule
543
`else
544
module latch ( d, le, q, clk);
545
input d, le;
546
output q;
547
input clk;/*
548
   always @ (posedge direction_set or posedge direction_clr)
549
     if (direction_clr)
550
       direction <= going_empty;
551
     else
552
       direction <= going_full;*/
553
endmodule
554 15 unneback
`endif
555
 
556 18 unneback
module vl_shreg ( d, q, clk, rst);
557 17 unneback
parameter depth = 10;
558
input d;
559
output q;
560
input clk, rst;
561
 
562
reg [1:depth] dffs;
563
 
564
always @ (posedge clk or posedge rst)
565
if (rst)
566
    dffs <= {depth{1'b0}};
567
else
568
    dffs <= {d,dffs[1:depth-1]};
569
assign q = dffs[depth];
570
endmodule
571
 
572 18 unneback
module vl_shreg_ce ( d, ce, q, clk, rst);
573 17 unneback
parameter depth = 10;
574
input d, ce;
575
output q;
576
input clk, rst;
577
 
578
reg [1:depth] dffs;
579
 
580
always @ (posedge clk or posedge rst)
581
if (rst)
582
    dffs <= {depth{1'b0}};
583
else
584
    if (ce)
585
        dffs <= {d,dffs[1:depth-1]};
586
assign q = dffs[depth];
587
endmodule
588
 
589 18 unneback
module vl_delay ( d, q, clk, rst);
590 15 unneback
parameter depth = 10;
591
input d;
592
output q;
593
input clk, rst;
594
 
595
reg [1:depth] dffs;
596
 
597
always @ (posedge clk or posedge rst)
598
if (rst)
599
    dffs <= {depth{1'b0}};
600
else
601
    dffs <= {d,dffs[1:depth-1]};
602
assign q = dffs[depth];
603 17 unneback
endmodule
604
 
605 18 unneback
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
606 17 unneback
parameter depth = 10;
607
input d;
608
output q, emptyflag;
609
input clk, rst;
610
 
611
reg [1:depth] dffs;
612
 
613
always @ (posedge clk or posedge rst)
614
if (rst)
615
    dffs <= {depth{1'b0}};
616
else
617
    dffs <= {d,dffs[1:depth-1]};
618
assign q = dffs[depth];
619
assign emptyflag = !(|dffs);
620
endmodule
621
//////////////////////////////////////////////////////////////////////
622 6 unneback
////                                                              ////
623 18 unneback
////  Logic functions                                             ////
624
////                                                              ////
625
////  Description                                                 ////
626
////  Logic functions such as multiplexers                        ////
627
////                                                              ////
628
////                                                              ////
629
////  To Do:                                                      ////
630
////   -                                                          ////
631
////                                                              ////
632
////  Author(s):                                                  ////
633
////      - Michael Unneback, unneback@opencores.org              ////
634
////        ORSoC AB                                              ////
635
////                                                              ////
636
//////////////////////////////////////////////////////////////////////
637
////                                                              ////
638
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
639
////                                                              ////
640
//// This source file may be used and distributed without         ////
641
//// restriction provided that this copyright statement is not    ////
642
//// removed from the file and that any derivative work contains  ////
643
//// the original copyright notice and the associated disclaimer. ////
644
////                                                              ////
645
//// This source file is free software; you can redistribute it   ////
646
//// and/or modify it under the terms of the GNU Lesser General   ////
647
//// Public License as published by the Free Software Foundation; ////
648
//// either version 2.1 of the License, or (at your option) any   ////
649
//// later version.                                               ////
650
////                                                              ////
651
//// This source is distributed in the hope that it will be       ////
652
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
653
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
654
//// PURPOSE.  See the GNU Lesser General Public License for more ////
655
//// details.                                                     ////
656
////                                                              ////
657
//// You should have received a copy of the GNU Lesser General    ////
658
//// Public License along with this source; if not, download it   ////
659
//// from http://www.opencores.org/lgpl.shtml                     ////
660
////                                                              ////
661
//////////////////////////////////////////////////////////////////////
662
 
663
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
664
 
665
parameter width = 32;
666
parameter nr_of_ports = 4;
667
input [width-1:0] a3, a2, a1, a0;
668
input [nr_of_ports-1:0] sel;
669 22 unneback
output [width-1:0] dout;
670 18 unneback
 
671 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
672 18 unneback
integer i;
673
 
674
// and
675
assign tmp[0] = {width{sel[0]}} & a0;
676
assign tmp[1] = {width{sel[1]}} & a1;
677
assign tmp[2] = {width{sel[2]}} & a2;
678
assign tmp[3] = {width{sel[3]}} & a3;
679
 
680
// or
681
assign dout = tmp[3] | tmp[2] | tmp[1] | tmp[0];
682
 
683
endmodule
684
 
685
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
686
 
687
parameter width = 32;
688
parameter nr_of_ports = 5;
689
input [width-1:0] a4, a3, a2, a1, a0;
690
input [nr_of_ports-1:0] sel;
691 22 unneback
output [width-1:0] dout;
692 18 unneback
 
693 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
694 18 unneback
integer i;
695
 
696
// and
697
assign tmp[0] = {width{sel[0]}} & a0;
698
assign tmp[1] = {width{sel[1]}} & a1;
699
assign tmp[2] = {width{sel[2]}} & a2;
700
assign tmp[3] = {width{sel[3]}} & a3;
701
assign tmp[4] = {width{sel[4]}} & a4;
702
 
703
// or
704
assign dout = tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
705
 
706
endmodule
707
 
708
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
709
 
710
parameter width = 32;
711
parameter nr_of_ports = 6;
712
input [width-1:0] a5, a4, a3, a2, a1, a0;
713
input [nr_of_ports-1:0] sel;
714 22 unneback
output [width-1:0] dout;
715 18 unneback
 
716 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
717 18 unneback
integer i;
718
 
719
// and
720
assign tmp[0] = {width{sel[0]}} & a0;
721
assign tmp[1] = {width{sel[1]}} & a1;
722
assign tmp[2] = {width{sel[2]}} & a2;
723
assign tmp[3] = {width{sel[3]}} & a3;
724
assign tmp[4] = {width{sel[4]}} & a4;
725
assign tmp[5] = {width{sel[5]}} & a5;
726
 
727
// or
728
assign dout = tmp[5] | tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
729
 
730
endmodule
731
//////////////////////////////////////////////////////////////////////
732
////                                                              ////
733 6 unneback
////  Versatile counter                                           ////
734
////                                                              ////
735
////  Description                                                 ////
736
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
737
////  counter                                                     ////
738
////                                                              ////
739
////  To Do:                                                      ////
740
////   - add LFSR with more taps                                  ////
741
////                                                              ////
742
////  Author(s):                                                  ////
743
////      - Michael Unneback, unneback@opencores.org              ////
744
////        ORSoC AB                                              ////
745
////                                                              ////
746
//////////////////////////////////////////////////////////////////////
747
////                                                              ////
748
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
749
////                                                              ////
750
//// This source file may be used and distributed without         ////
751
//// restriction provided that this copyright statement is not    ////
752
//// removed from the file and that any derivative work contains  ////
753
//// the original copyright notice and the associated disclaimer. ////
754
////                                                              ////
755
//// This source file is free software; you can redistribute it   ////
756
//// and/or modify it under the terms of the GNU Lesser General   ////
757
//// Public License as published by the Free Software Foundation; ////
758
//// either version 2.1 of the License, or (at your option) any   ////
759
//// later version.                                               ////
760
////                                                              ////
761
//// This source is distributed in the hope that it will be       ////
762
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
763
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
764
//// PURPOSE.  See the GNU Lesser General Public License for more ////
765
//// details.                                                     ////
766
////                                                              ////
767
//// You should have received a copy of the GNU Lesser General    ////
768
//// Public License along with this source; if not, download it   ////
769
//// from http://www.opencores.org/lgpl.shtml                     ////
770
////                                                              ////
771
//////////////////////////////////////////////////////////////////////
772
 
773
// binary counter
774 22 unneback
module vl_cnt_bin ( q, rst, clk);
775
 
776
   parameter length = 4;
777
   output [length:1] q;
778
   input rst;
779
   input clk;
780
 
781
   parameter clear_value = 0;
782
   parameter set_value = 1;
783
   parameter wrap_value = 0;
784
   parameter level1_value = 15;
785
 
786
   reg  [length:1] qi;
787
   wire [length:1] q_next;
788
   assign q_next = qi + {{length-1{1'b0}},1'b1};
789
 
790
   always @ (posedge clk or posedge rst)
791
     if (rst)
792
       qi <= {length{1'b0}};
793
     else
794
       qi <= q_next;
795
 
796
   assign q = qi;
797
 
798
endmodule
799
//////////////////////////////////////////////////////////////////////
800
////                                                              ////
801
////  Versatile counter                                           ////
802
////                                                              ////
803
////  Description                                                 ////
804
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
805
////  counter                                                     ////
806
////                                                              ////
807
////  To Do:                                                      ////
808
////   - add LFSR with more taps                                  ////
809
////                                                              ////
810
////  Author(s):                                                  ////
811
////      - Michael Unneback, unneback@opencores.org              ////
812
////        ORSoC AB                                              ////
813
////                                                              ////
814
//////////////////////////////////////////////////////////////////////
815
////                                                              ////
816
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
817
////                                                              ////
818
//// This source file may be used and distributed without         ////
819
//// restriction provided that this copyright statement is not    ////
820
//// removed from the file and that any derivative work contains  ////
821
//// the original copyright notice and the associated disclaimer. ////
822
////                                                              ////
823
//// This source file is free software; you can redistribute it   ////
824
//// and/or modify it under the terms of the GNU Lesser General   ////
825
//// Public License as published by the Free Software Foundation; ////
826
//// either version 2.1 of the License, or (at your option) any   ////
827
//// later version.                                               ////
828
////                                                              ////
829
//// This source is distributed in the hope that it will be       ////
830
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
831
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
832
//// PURPOSE.  See the GNU Lesser General Public License for more ////
833
//// details.                                                     ////
834
////                                                              ////
835
//// You should have received a copy of the GNU Lesser General    ////
836
//// Public License along with this source; if not, download it   ////
837
//// from http://www.opencores.org/lgpl.shtml                     ////
838
////                                                              ////
839
//////////////////////////////////////////////////////////////////////
840
 
841
// binary counter
842
module vl_cnt_bin_clear ( clear, q, rst, clk);
843
 
844
   parameter length = 4;
845
   input clear;
846
   output [length:1] q;
847
   input rst;
848
   input clk;
849
 
850
   parameter clear_value = 0;
851
   parameter set_value = 1;
852
   parameter wrap_value = 0;
853
   parameter level1_value = 15;
854
 
855
   reg  [length:1] qi;
856
   wire [length:1] q_next;
857
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
858
 
859
   always @ (posedge clk or posedge rst)
860
     if (rst)
861
       qi <= {length{1'b0}};
862
     else
863
       qi <= q_next;
864
 
865
   assign q = qi;
866
 
867
endmodule
868
//////////////////////////////////////////////////////////////////////
869
////                                                              ////
870
////  Versatile counter                                           ////
871
////                                                              ////
872
////  Description                                                 ////
873
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
874
////  counter                                                     ////
875
////                                                              ////
876
////  To Do:                                                      ////
877
////   - add LFSR with more taps                                  ////
878
////                                                              ////
879
////  Author(s):                                                  ////
880
////      - Michael Unneback, unneback@opencores.org              ////
881
////        ORSoC AB                                              ////
882
////                                                              ////
883
//////////////////////////////////////////////////////////////////////
884
////                                                              ////
885
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
886
////                                                              ////
887
//// This source file may be used and distributed without         ////
888
//// restriction provided that this copyright statement is not    ////
889
//// removed from the file and that any derivative work contains  ////
890
//// the original copyright notice and the associated disclaimer. ////
891
////                                                              ////
892
//// This source file is free software; you can redistribute it   ////
893
//// and/or modify it under the terms of the GNU Lesser General   ////
894
//// Public License as published by the Free Software Foundation; ////
895
//// either version 2.1 of the License, or (at your option) any   ////
896
//// later version.                                               ////
897
////                                                              ////
898
//// This source is distributed in the hope that it will be       ////
899
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
900
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
901
//// PURPOSE.  See the GNU Lesser General Public License for more ////
902
//// details.                                                     ////
903
////                                                              ////
904
//// You should have received a copy of the GNU Lesser General    ////
905
//// Public License along with this source; if not, download it   ////
906
//// from http://www.opencores.org/lgpl.shtml                     ////
907
////                                                              ////
908
//////////////////////////////////////////////////////////////////////
909
 
910
// binary counter
911 18 unneback
module vl_cnt_bin_ce ( cke, q, rst, clk);
912 6 unneback
 
913
   parameter length = 4;
914
   input cke;
915
   output [length:1] q;
916
   input rst;
917
   input clk;
918
 
919
   parameter clear_value = 0;
920
   parameter set_value = 1;
921
   parameter wrap_value = 0;
922
   parameter level1_value = 15;
923
 
924
   reg  [length:1] qi;
925
   wire [length:1] q_next;
926
   assign q_next = qi + {{length-1{1'b0}},1'b1};
927
 
928
   always @ (posedge clk or posedge rst)
929
     if (rst)
930
       qi <= {length{1'b0}};
931
     else
932
     if (cke)
933
       qi <= q_next;
934
 
935
   assign q = qi;
936
 
937
endmodule
938
//////////////////////////////////////////////////////////////////////
939
////                                                              ////
940
////  Versatile counter                                           ////
941
////                                                              ////
942
////  Description                                                 ////
943
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
944
////  counter                                                     ////
945
////                                                              ////
946
////  To Do:                                                      ////
947
////   - add LFSR with more taps                                  ////
948
////                                                              ////
949
////  Author(s):                                                  ////
950
////      - Michael Unneback, unneback@opencores.org              ////
951
////        ORSoC AB                                              ////
952
////                                                              ////
953
//////////////////////////////////////////////////////////////////////
954
////                                                              ////
955
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
956
////                                                              ////
957
//// This source file may be used and distributed without         ////
958
//// restriction provided that this copyright statement is not    ////
959
//// removed from the file and that any derivative work contains  ////
960
//// the original copyright notice and the associated disclaimer. ////
961
////                                                              ////
962
//// This source file is free software; you can redistribute it   ////
963
//// and/or modify it under the terms of the GNU Lesser General   ////
964
//// Public License as published by the Free Software Foundation; ////
965
//// either version 2.1 of the License, or (at your option) any   ////
966
//// later version.                                               ////
967
////                                                              ////
968
//// This source is distributed in the hope that it will be       ////
969
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
970
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
971
//// PURPOSE.  See the GNU Lesser General Public License for more ////
972
//// details.                                                     ////
973
////                                                              ////
974
//// You should have received a copy of the GNU Lesser General    ////
975
//// Public License along with this source; if not, download it   ////
976
//// from http://www.opencores.org/lgpl.shtml                     ////
977
////                                                              ////
978
//////////////////////////////////////////////////////////////////////
979
 
980
// binary counter
981 18 unneback
module vl_cnt_bin_ce_clear ( clear, cke, q, rst, clk);
982 6 unneback
 
983
   parameter length = 4;
984
   input clear;
985
   input cke;
986
   output [length:1] q;
987
   input rst;
988
   input clk;
989
 
990
   parameter clear_value = 0;
991
   parameter set_value = 1;
992
   parameter wrap_value = 0;
993
   parameter level1_value = 15;
994
 
995
   reg  [length:1] qi;
996
   wire [length:1] q_next;
997
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
998
 
999
   always @ (posedge clk or posedge rst)
1000
     if (rst)
1001
       qi <= {length{1'b0}};
1002
     else
1003
     if (cke)
1004
       qi <= q_next;
1005
 
1006
   assign q = qi;
1007
 
1008
endmodule
1009
//////////////////////////////////////////////////////////////////////
1010
////                                                              ////
1011
////  Versatile counter                                           ////
1012
////                                                              ////
1013
////  Description                                                 ////
1014
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1015
////  counter                                                     ////
1016
////                                                              ////
1017
////  To Do:                                                      ////
1018
////   - add LFSR with more taps                                  ////
1019
////                                                              ////
1020
////  Author(s):                                                  ////
1021
////      - Michael Unneback, unneback@opencores.org              ////
1022
////        ORSoC AB                                              ////
1023
////                                                              ////
1024
//////////////////////////////////////////////////////////////////////
1025
////                                                              ////
1026
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1027
////                                                              ////
1028
//// This source file may be used and distributed without         ////
1029
//// restriction provided that this copyright statement is not    ////
1030
//// removed from the file and that any derivative work contains  ////
1031
//// the original copyright notice and the associated disclaimer. ////
1032
////                                                              ////
1033
//// This source file is free software; you can redistribute it   ////
1034
//// and/or modify it under the terms of the GNU Lesser General   ////
1035
//// Public License as published by the Free Software Foundation; ////
1036
//// either version 2.1 of the License, or (at your option) any   ////
1037
//// later version.                                               ////
1038
////                                                              ////
1039
//// This source is distributed in the hope that it will be       ////
1040
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1041
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1042
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1043
//// details.                                                     ////
1044
////                                                              ////
1045
//// You should have received a copy of the GNU Lesser General    ////
1046
//// Public License along with this source; if not, download it   ////
1047
//// from http://www.opencores.org/lgpl.shtml                     ////
1048
////                                                              ////
1049
//////////////////////////////////////////////////////////////////////
1050
 
1051
// binary counter
1052 18 unneback
module vl_cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk);
1053 6 unneback
 
1054
   parameter length = 4;
1055
   input clear;
1056
   input set;
1057
   input cke;
1058
   input rew;
1059
   output [length:1] q;
1060
   input rst;
1061
   input clk;
1062
 
1063
   parameter clear_value = 0;
1064
   parameter set_value = 1;
1065
   parameter wrap_value = 0;
1066
   parameter level1_value = 15;
1067
 
1068
   reg  [length:1] qi;
1069
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1070
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
1071
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
1072
   assign q_next = rew ? q_next_rew : q_next_fw;
1073
 
1074
   always @ (posedge clk or posedge rst)
1075
     if (rst)
1076
       qi <= {length{1'b0}};
1077
     else
1078
     if (cke)
1079
       qi <= q_next;
1080
 
1081
   assign q = qi;
1082
 
1083
endmodule
1084
//////////////////////////////////////////////////////////////////////
1085
////                                                              ////
1086
////  Versatile counter                                           ////
1087
////                                                              ////
1088
////  Description                                                 ////
1089
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1090
////  counter                                                     ////
1091
////                                                              ////
1092
////  To Do:                                                      ////
1093
////   - add LFSR with more taps                                  ////
1094
////                                                              ////
1095
////  Author(s):                                                  ////
1096
////      - Michael Unneback, unneback@opencores.org              ////
1097
////        ORSoC AB                                              ////
1098
////                                                              ////
1099
//////////////////////////////////////////////////////////////////////
1100
////                                                              ////
1101
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1102
////                                                              ////
1103
//// This source file may be used and distributed without         ////
1104
//// restriction provided that this copyright statement is not    ////
1105
//// removed from the file and that any derivative work contains  ////
1106
//// the original copyright notice and the associated disclaimer. ////
1107
////                                                              ////
1108
//// This source file is free software; you can redistribute it   ////
1109
//// and/or modify it under the terms of the GNU Lesser General   ////
1110
//// Public License as published by the Free Software Foundation; ////
1111
//// either version 2.1 of the License, or (at your option) any   ////
1112
//// later version.                                               ////
1113
////                                                              ////
1114
//// This source is distributed in the hope that it will be       ////
1115
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1116
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1117
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1118
//// details.                                                     ////
1119
////                                                              ////
1120
//// You should have received a copy of the GNU Lesser General    ////
1121
//// Public License along with this source; if not, download it   ////
1122
//// from http://www.opencores.org/lgpl.shtml                     ////
1123
////                                                              ////
1124
//////////////////////////////////////////////////////////////////////
1125
 
1126
// binary counter
1127 18 unneback
module vl_cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk);
1128 6 unneback
 
1129
   parameter length = 4;
1130
   input cke;
1131
   input rew;
1132
   output reg level1;
1133
   input rst;
1134
   input clk;
1135
 
1136
   parameter clear_value = 0;
1137
   parameter set_value = 1;
1138
   parameter wrap_value = 1;
1139
   parameter level1_value = 15;
1140
 
1141
   reg  [length:1] qi;
1142
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1143
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1144
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1145
   assign q_next = rew ? q_next_rew : q_next_fw;
1146
 
1147
   always @ (posedge clk or posedge rst)
1148
     if (rst)
1149
       qi <= {length{1'b0}};
1150
     else
1151
     if (cke)
1152
       qi <= q_next;
1153
 
1154
 
1155
 
1156
    always @ (posedge clk or posedge rst)
1157
    if (rst)
1158
        level1 <= 1'b0;
1159
    else
1160
    if (cke)
1161
    if (q_next == level1_value)
1162
        level1 <= 1'b1;
1163
    else if (qi == level1_value & rew)
1164
        level1 <= 1'b0;
1165
endmodule
1166
//////////////////////////////////////////////////////////////////////
1167
////                                                              ////
1168
////  Versatile counter                                           ////
1169
////                                                              ////
1170
////  Description                                                 ////
1171
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1172
////  counter                                                     ////
1173
////                                                              ////
1174
////  To Do:                                                      ////
1175
////   - add LFSR with more taps                                  ////
1176
////                                                              ////
1177
////  Author(s):                                                  ////
1178
////      - Michael Unneback, unneback@opencores.org              ////
1179
////        ORSoC AB                                              ////
1180
////                                                              ////
1181
//////////////////////////////////////////////////////////////////////
1182
////                                                              ////
1183
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1184
////                                                              ////
1185
//// This source file may be used and distributed without         ////
1186
//// restriction provided that this copyright statement is not    ////
1187
//// removed from the file and that any derivative work contains  ////
1188
//// the original copyright notice and the associated disclaimer. ////
1189
////                                                              ////
1190
//// This source file is free software; you can redistribute it   ////
1191
//// and/or modify it under the terms of the GNU Lesser General   ////
1192
//// Public License as published by the Free Software Foundation; ////
1193
//// either version 2.1 of the License, or (at your option) any   ////
1194
//// later version.                                               ////
1195
////                                                              ////
1196
//// This source is distributed in the hope that it will be       ////
1197
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1198
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1199
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1200
//// details.                                                     ////
1201
////                                                              ////
1202
//// You should have received a copy of the GNU Lesser General    ////
1203
//// Public License along with this source; if not, download it   ////
1204
//// from http://www.opencores.org/lgpl.shtml                     ////
1205
////                                                              ////
1206
//////////////////////////////////////////////////////////////////////
1207
 
1208
// LFSR counter
1209 18 unneback
module vl_cnt_lfsr_zq ( zq, rst, clk);
1210 6 unneback
 
1211
   parameter length = 4;
1212
   output reg zq;
1213
   input rst;
1214
   input clk;
1215
 
1216
   parameter clear_value = 0;
1217
   parameter set_value = 1;
1218
   parameter wrap_value = 8;
1219
   parameter level1_value = 15;
1220
 
1221
   reg  [length:1] qi;
1222
   reg lfsr_fb;
1223
   wire [length:1] q_next;
1224
   reg [32:1] polynom;
1225
   integer i;
1226
 
1227
   always @ (qi)
1228
   begin
1229
        case (length)
1230
         2: polynom = 32'b11;                               // 0x3
1231
         3: polynom = 32'b110;                              // 0x6
1232
         4: polynom = 32'b1100;                             // 0xC
1233
         5: polynom = 32'b10100;                            // 0x14
1234
         6: polynom = 32'b110000;                           // 0x30
1235
         7: polynom = 32'b1100000;                          // 0x60
1236
         8: polynom = 32'b10111000;                         // 0xb8
1237
         9: polynom = 32'b100010000;                        // 0x110
1238
        10: polynom = 32'b1001000000;                       // 0x240
1239
        11: polynom = 32'b10100000000;                      // 0x500
1240
        12: polynom = 32'b100000101001;                     // 0x829
1241
        13: polynom = 32'b1000000001100;                    // 0x100C
1242
        14: polynom = 32'b10000000010101;                   // 0x2015
1243
        15: polynom = 32'b110000000000000;                  // 0x6000
1244
        16: polynom = 32'b1101000000001000;                 // 0xD008
1245
        17: polynom = 32'b10010000000000000;                // 0x12000
1246
        18: polynom = 32'b100000010000000000;               // 0x20400
1247
        19: polynom = 32'b1000000000000100011;              // 0x40023
1248
        20: polynom = 32'b10000010000000000000;             // 0x82000
1249
        21: polynom = 32'b101000000000000000000;            // 0x140000
1250
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1251
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1252
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1253
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1254
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1255
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1256
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1257
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1258
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1259
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1260
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1261
        default: polynom = 32'b0;
1262
        endcase
1263
        lfsr_fb = qi[length];
1264
        for (i=length-1; i>=1; i=i-1) begin
1265
            if (polynom[i])
1266
                lfsr_fb = lfsr_fb  ~^ qi[i];
1267
        end
1268
    end
1269
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1270
 
1271
   always @ (posedge clk or posedge rst)
1272
     if (rst)
1273
       qi <= {length{1'b0}};
1274
     else
1275
       qi <= q_next;
1276
 
1277
 
1278
 
1279
   always @ (posedge clk or posedge rst)
1280
     if (rst)
1281
       zq <= 1'b1;
1282
     else
1283
       zq <= q_next == {length{1'b0}};
1284
endmodule
1285
//////////////////////////////////////////////////////////////////////
1286
////                                                              ////
1287
////  Versatile counter                                           ////
1288
////                                                              ////
1289
////  Description                                                 ////
1290
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1291
////  counter                                                     ////
1292
////                                                              ////
1293
////  To Do:                                                      ////
1294
////   - add LFSR with more taps                                  ////
1295
////                                                              ////
1296
////  Author(s):                                                  ////
1297
////      - Michael Unneback, unneback@opencores.org              ////
1298
////        ORSoC AB                                              ////
1299
////                                                              ////
1300
//////////////////////////////////////////////////////////////////////
1301
////                                                              ////
1302
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1303
////                                                              ////
1304
//// This source file may be used and distributed without         ////
1305
//// restriction provided that this copyright statement is not    ////
1306
//// removed from the file and that any derivative work contains  ////
1307
//// the original copyright notice and the associated disclaimer. ////
1308
////                                                              ////
1309
//// This source file is free software; you can redistribute it   ////
1310
//// and/or modify it under the terms of the GNU Lesser General   ////
1311
//// Public License as published by the Free Software Foundation; ////
1312
//// either version 2.1 of the License, or (at your option) any   ////
1313
//// later version.                                               ////
1314
////                                                              ////
1315
//// This source is distributed in the hope that it will be       ////
1316
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1317
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1318
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1319
//// details.                                                     ////
1320
////                                                              ////
1321
//// You should have received a copy of the GNU Lesser General    ////
1322
//// Public License along with this source; if not, download it   ////
1323
//// from http://www.opencores.org/lgpl.shtml                     ////
1324
////                                                              ////
1325
//////////////////////////////////////////////////////////////////////
1326
 
1327
// LFSR counter
1328 18 unneback
module vl_cnt_lfsr_ce_zq ( cke, zq, rst, clk);
1329 6 unneback
 
1330
   parameter length = 4;
1331
   input cke;
1332
   output reg zq;
1333
   input rst;
1334
   input clk;
1335
 
1336
   parameter clear_value = 0;
1337
   parameter set_value = 1;
1338
   parameter wrap_value = 8;
1339
   parameter level1_value = 15;
1340
 
1341
   reg  [length:1] qi;
1342
   reg lfsr_fb;
1343
   wire [length:1] q_next;
1344
   reg [32:1] polynom;
1345
   integer i;
1346
 
1347
   always @ (qi)
1348
   begin
1349
        case (length)
1350
         2: polynom = 32'b11;                               // 0x3
1351
         3: polynom = 32'b110;                              // 0x6
1352
         4: polynom = 32'b1100;                             // 0xC
1353
         5: polynom = 32'b10100;                            // 0x14
1354
         6: polynom = 32'b110000;                           // 0x30
1355
         7: polynom = 32'b1100000;                          // 0x60
1356
         8: polynom = 32'b10111000;                         // 0xb8
1357
         9: polynom = 32'b100010000;                        // 0x110
1358
        10: polynom = 32'b1001000000;                       // 0x240
1359
        11: polynom = 32'b10100000000;                      // 0x500
1360
        12: polynom = 32'b100000101001;                     // 0x829
1361
        13: polynom = 32'b1000000001100;                    // 0x100C
1362
        14: polynom = 32'b10000000010101;                   // 0x2015
1363
        15: polynom = 32'b110000000000000;                  // 0x6000
1364
        16: polynom = 32'b1101000000001000;                 // 0xD008
1365
        17: polynom = 32'b10010000000000000;                // 0x12000
1366
        18: polynom = 32'b100000010000000000;               // 0x20400
1367
        19: polynom = 32'b1000000000000100011;              // 0x40023
1368
        20: polynom = 32'b10000010000000000000;             // 0x82000
1369
        21: polynom = 32'b101000000000000000000;            // 0x140000
1370
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1371
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1372
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1373
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1374
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1375
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1376
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1377
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1378
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1379
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1380
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1381
        default: polynom = 32'b0;
1382
        endcase
1383
        lfsr_fb = qi[length];
1384
        for (i=length-1; i>=1; i=i-1) begin
1385
            if (polynom[i])
1386
                lfsr_fb = lfsr_fb  ~^ qi[i];
1387
        end
1388
    end
1389
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1390
 
1391
   always @ (posedge clk or posedge rst)
1392
     if (rst)
1393
       qi <= {length{1'b0}};
1394
     else
1395
     if (cke)
1396
       qi <= q_next;
1397
 
1398
 
1399
 
1400
   always @ (posedge clk or posedge rst)
1401
     if (rst)
1402
       zq <= 1'b1;
1403
     else
1404
     if (cke)
1405
       zq <= q_next == {length{1'b0}};
1406
endmodule
1407
//////////////////////////////////////////////////////////////////////
1408
////                                                              ////
1409
////  Versatile counter                                           ////
1410
////                                                              ////
1411
////  Description                                                 ////
1412
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1413
////  counter                                                     ////
1414
////                                                              ////
1415
////  To Do:                                                      ////
1416
////   - add LFSR with more taps                                  ////
1417
////                                                              ////
1418
////  Author(s):                                                  ////
1419
////      - Michael Unneback, unneback@opencores.org              ////
1420
////        ORSoC AB                                              ////
1421
////                                                              ////
1422
//////////////////////////////////////////////////////////////////////
1423
////                                                              ////
1424
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1425
////                                                              ////
1426
//// This source file may be used and distributed without         ////
1427
//// restriction provided that this copyright statement is not    ////
1428
//// removed from the file and that any derivative work contains  ////
1429
//// the original copyright notice and the associated disclaimer. ////
1430
////                                                              ////
1431
//// This source file is free software; you can redistribute it   ////
1432
//// and/or modify it under the terms of the GNU Lesser General   ////
1433
//// Public License as published by the Free Software Foundation; ////
1434
//// either version 2.1 of the License, or (at your option) any   ////
1435
//// later version.                                               ////
1436
////                                                              ////
1437
//// This source is distributed in the hope that it will be       ////
1438
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1439
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1440
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1441
//// details.                                                     ////
1442
////                                                              ////
1443
//// You should have received a copy of the GNU Lesser General    ////
1444
//// Public License along with this source; if not, download it   ////
1445
//// from http://www.opencores.org/lgpl.shtml                     ////
1446
////                                                              ////
1447
//////////////////////////////////////////////////////////////////////
1448 22 unneback
 
1449
// LFSR counter
1450
module vl_cnt_lfsr_ce_q_zq ( cke, q, zq, rst, clk);
1451
 
1452
   parameter length = 4;
1453
   input cke;
1454
   output [length:1] q;
1455
   output reg zq;
1456
   input rst;
1457
   input clk;
1458
 
1459
   parameter clear_value = 0;
1460
   parameter set_value = 1;
1461
   parameter wrap_value = 8;
1462
   parameter level1_value = 15;
1463
 
1464
   reg  [length:1] qi;
1465
   reg lfsr_fb;
1466
   wire [length:1] q_next;
1467
   reg [32:1] polynom;
1468
   integer i;
1469
 
1470
   always @ (qi)
1471
   begin
1472
        case (length)
1473
         2: polynom = 32'b11;                               // 0x3
1474
         3: polynom = 32'b110;                              // 0x6
1475
         4: polynom = 32'b1100;                             // 0xC
1476
         5: polynom = 32'b10100;                            // 0x14
1477
         6: polynom = 32'b110000;                           // 0x30
1478
         7: polynom = 32'b1100000;                          // 0x60
1479
         8: polynom = 32'b10111000;                         // 0xb8
1480
         9: polynom = 32'b100010000;                        // 0x110
1481
        10: polynom = 32'b1001000000;                       // 0x240
1482
        11: polynom = 32'b10100000000;                      // 0x500
1483
        12: polynom = 32'b100000101001;                     // 0x829
1484
        13: polynom = 32'b1000000001100;                    // 0x100C
1485
        14: polynom = 32'b10000000010101;                   // 0x2015
1486
        15: polynom = 32'b110000000000000;                  // 0x6000
1487
        16: polynom = 32'b1101000000001000;                 // 0xD008
1488
        17: polynom = 32'b10010000000000000;                // 0x12000
1489
        18: polynom = 32'b100000010000000000;               // 0x20400
1490
        19: polynom = 32'b1000000000000100011;              // 0x40023
1491
        20: polynom = 32'b10000010000000000000;             // 0x82000
1492
        21: polynom = 32'b101000000000000000000;            // 0x140000
1493
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1494
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1495
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1496
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1497
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1498
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1499
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1500
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1501
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1502
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1503
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1504
        default: polynom = 32'b0;
1505
        endcase
1506
        lfsr_fb = qi[length];
1507
        for (i=length-1; i>=1; i=i-1) begin
1508
            if (polynom[i])
1509
                lfsr_fb = lfsr_fb  ~^ qi[i];
1510
        end
1511
    end
1512
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1513
 
1514
   always @ (posedge clk or posedge rst)
1515
     if (rst)
1516
       qi <= {length{1'b0}};
1517
     else
1518
     if (cke)
1519
       qi <= q_next;
1520
 
1521
   assign q = qi;
1522
 
1523
 
1524
   always @ (posedge clk or posedge rst)
1525
     if (rst)
1526
       zq <= 1'b1;
1527
     else
1528
     if (cke)
1529
       zq <= q_next == {length{1'b0}};
1530
endmodule
1531
//////////////////////////////////////////////////////////////////////
1532
////                                                              ////
1533
////  Versatile counter                                           ////
1534
////                                                              ////
1535
////  Description                                                 ////
1536
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1537
////  counter                                                     ////
1538
////                                                              ////
1539
////  To Do:                                                      ////
1540
////   - add LFSR with more taps                                  ////
1541
////                                                              ////
1542
////  Author(s):                                                  ////
1543
////      - Michael Unneback, unneback@opencores.org              ////
1544
////        ORSoC AB                                              ////
1545
////                                                              ////
1546
//////////////////////////////////////////////////////////////////////
1547
////                                                              ////
1548
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1549
////                                                              ////
1550
//// This source file may be used and distributed without         ////
1551
//// restriction provided that this copyright statement is not    ////
1552
//// removed from the file and that any derivative work contains  ////
1553
//// the original copyright notice and the associated disclaimer. ////
1554
////                                                              ////
1555
//// This source file is free software; you can redistribute it   ////
1556
//// and/or modify it under the terms of the GNU Lesser General   ////
1557
//// Public License as published by the Free Software Foundation; ////
1558
//// either version 2.1 of the License, or (at your option) any   ////
1559
//// later version.                                               ////
1560
////                                                              ////
1561
//// This source is distributed in the hope that it will be       ////
1562
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1563
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1564
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1565
//// details.                                                     ////
1566
////                                                              ////
1567
//// You should have received a copy of the GNU Lesser General    ////
1568
//// Public License along with this source; if not, download it   ////
1569
//// from http://www.opencores.org/lgpl.shtml                     ////
1570
////                                                              ////
1571
//////////////////////////////////////////////////////////////////////
1572 6 unneback
 
1573
// LFSR counter
1574 18 unneback
module vl_cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk);
1575 6 unneback
 
1576
   parameter length = 4;
1577
   input cke;
1578
   input rew;
1579
   output reg level1;
1580
   input rst;
1581
   input clk;
1582
 
1583
   parameter clear_value = 0;
1584
   parameter set_value = 1;
1585
   parameter wrap_value = 8;
1586
   parameter level1_value = 15;
1587
 
1588
   reg  [length:1] qi;
1589
   reg lfsr_fb, lfsr_fb_rew;
1590
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1591
   reg [32:1] polynom_rew;
1592
   integer j;
1593
   reg [32:1] polynom;
1594
   integer i;
1595
 
1596
   always @ (qi)
1597
   begin
1598
        case (length)
1599
         2: polynom = 32'b11;                               // 0x3
1600
         3: polynom = 32'b110;                              // 0x6
1601
         4: polynom = 32'b1100;                             // 0xC
1602
         5: polynom = 32'b10100;                            // 0x14
1603
         6: polynom = 32'b110000;                           // 0x30
1604
         7: polynom = 32'b1100000;                          // 0x60
1605
         8: polynom = 32'b10111000;                         // 0xb8
1606
         9: polynom = 32'b100010000;                        // 0x110
1607
        10: polynom = 32'b1001000000;                       // 0x240
1608
        11: polynom = 32'b10100000000;                      // 0x500
1609
        12: polynom = 32'b100000101001;                     // 0x829
1610
        13: polynom = 32'b1000000001100;                    // 0x100C
1611
        14: polynom = 32'b10000000010101;                   // 0x2015
1612
        15: polynom = 32'b110000000000000;                  // 0x6000
1613
        16: polynom = 32'b1101000000001000;                 // 0xD008
1614
        17: polynom = 32'b10010000000000000;                // 0x12000
1615
        18: polynom = 32'b100000010000000000;               // 0x20400
1616
        19: polynom = 32'b1000000000000100011;              // 0x40023
1617
        20: polynom = 32'b10000010000000000000;             // 0x82000
1618
        21: polynom = 32'b101000000000000000000;            // 0x140000
1619
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1620
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1621
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1622
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1623
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1624
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1625
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1626
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1627
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1628
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1629
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1630
        default: polynom = 32'b0;
1631
        endcase
1632
        lfsr_fb = qi[length];
1633
        for (i=length-1; i>=1; i=i-1) begin
1634
            if (polynom[i])
1635
                lfsr_fb = lfsr_fb  ~^ qi[i];
1636
        end
1637
    end
1638
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1639
   always @ (qi)
1640
   begin
1641
        case (length)
1642
         2: polynom_rew = 32'b11;
1643
         3: polynom_rew = 32'b110;
1644
         4: polynom_rew = 32'b1100;
1645
         5: polynom_rew = 32'b10100;
1646
         6: polynom_rew = 32'b110000;
1647
         7: polynom_rew = 32'b1100000;
1648
         8: polynom_rew = 32'b10111000;
1649
         9: polynom_rew = 32'b100010000;
1650
        10: polynom_rew = 32'b1001000000;
1651
        11: polynom_rew = 32'b10100000000;
1652
        12: polynom_rew = 32'b100000101001;
1653
        13: polynom_rew = 32'b1000000001100;
1654
        14: polynom_rew = 32'b10000000010101;
1655
        15: polynom_rew = 32'b110000000000000;
1656
        16: polynom_rew = 32'b1101000000001000;
1657
        17: polynom_rew = 32'b10010000000000000;
1658
        18: polynom_rew = 32'b100000010000000000;
1659
        19: polynom_rew = 32'b1000000000000100011;
1660
        20: polynom_rew = 32'b10000010000000000000;
1661
        21: polynom_rew = 32'b101000000000000000000;
1662
        22: polynom_rew = 32'b1100000000000000000000;
1663
        23: polynom_rew = 32'b10000100000000000000000;
1664
        24: polynom_rew = 32'b111000010000000000000000;
1665
        25: polynom_rew = 32'b1001000000000000000000000;
1666
        26: polynom_rew = 32'b10000000000000000000100011;
1667
        27: polynom_rew = 32'b100000000000000000000010011;
1668
        28: polynom_rew = 32'b1100100000000000000000000000;
1669
        29: polynom_rew = 32'b10100000000000000000000000000;
1670
        30: polynom_rew = 32'b100000000000000000000000101001;
1671
        31: polynom_rew = 32'b1001000000000000000000000000000;
1672
        32: polynom_rew = 32'b10000000001000000000000000000011;
1673
        default: polynom_rew = 32'b0;
1674
        endcase
1675
        // rotate left
1676
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
1677
        lfsr_fb_rew = qi[length];
1678
        for (i=length-1; i>=1; i=i-1) begin
1679
            if (polynom_rew[i])
1680
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
1681
        end
1682
    end
1683
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
1684
   assign q_next = rew ? q_next_rew : q_next_fw;
1685
 
1686
   always @ (posedge clk or posedge rst)
1687
     if (rst)
1688
       qi <= {length{1'b0}};
1689
     else
1690
     if (cke)
1691
       qi <= q_next;
1692
 
1693
 
1694
 
1695
    always @ (posedge clk or posedge rst)
1696
    if (rst)
1697
        level1 <= 1'b0;
1698
    else
1699
    if (cke)
1700
    if (q_next == level1_value)
1701
        level1 <= 1'b1;
1702
    else if (qi == level1_value & rew)
1703
        level1 <= 1'b0;
1704
endmodule
1705
//////////////////////////////////////////////////////////////////////
1706
////                                                              ////
1707
////  Versatile counter                                           ////
1708
////                                                              ////
1709
////  Description                                                 ////
1710
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1711
////  counter                                                     ////
1712
////                                                              ////
1713
////  To Do:                                                      ////
1714
////   - add LFSR with more taps                                  ////
1715
////                                                              ////
1716
////  Author(s):                                                  ////
1717
////      - Michael Unneback, unneback@opencores.org              ////
1718
////        ORSoC AB                                              ////
1719
////                                                              ////
1720
//////////////////////////////////////////////////////////////////////
1721
////                                                              ////
1722
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1723
////                                                              ////
1724
//// This source file may be used and distributed without         ////
1725
//// restriction provided that this copyright statement is not    ////
1726
//// removed from the file and that any derivative work contains  ////
1727
//// the original copyright notice and the associated disclaimer. ////
1728
////                                                              ////
1729
//// This source file is free software; you can redistribute it   ////
1730
//// and/or modify it under the terms of the GNU Lesser General   ////
1731
//// Public License as published by the Free Software Foundation; ////
1732
//// either version 2.1 of the License, or (at your option) any   ////
1733
//// later version.                                               ////
1734
////                                                              ////
1735
//// This source is distributed in the hope that it will be       ////
1736
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1737
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1738
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1739
//// details.                                                     ////
1740
////                                                              ////
1741
//// You should have received a copy of the GNU Lesser General    ////
1742
//// Public License along with this source; if not, download it   ////
1743
//// from http://www.opencores.org/lgpl.shtml                     ////
1744
////                                                              ////
1745
//////////////////////////////////////////////////////////////////////
1746
 
1747
// GRAY counter
1748 18 unneback
module vl_cnt_gray ( q, rst, clk);
1749 6 unneback
 
1750
   parameter length = 4;
1751
   output reg [length:1] q;
1752
   input rst;
1753
   input clk;
1754
 
1755
   parameter clear_value = 0;
1756
   parameter set_value = 1;
1757
   parameter wrap_value = 8;
1758
   parameter level1_value = 15;
1759
 
1760
   reg  [length:1] qi;
1761
   wire [length:1] q_next;
1762
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1763
 
1764
   always @ (posedge clk or posedge rst)
1765
     if (rst)
1766
       qi <= {length{1'b0}};
1767
     else
1768
       qi <= q_next;
1769
 
1770
   always @ (posedge clk or posedge rst)
1771
     if (rst)
1772
       q <= {length{1'b0}};
1773
     else
1774
         q <= (q_next>>1) ^ q_next;
1775
 
1776
endmodule
1777
//////////////////////////////////////////////////////////////////////
1778
////                                                              ////
1779
////  Versatile counter                                           ////
1780
////                                                              ////
1781
////  Description                                                 ////
1782
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1783
////  counter                                                     ////
1784
////                                                              ////
1785
////  To Do:                                                      ////
1786
////   - add LFSR with more taps                                  ////
1787
////                                                              ////
1788
////  Author(s):                                                  ////
1789
////      - Michael Unneback, unneback@opencores.org              ////
1790
////        ORSoC AB                                              ////
1791
////                                                              ////
1792
//////////////////////////////////////////////////////////////////////
1793
////                                                              ////
1794
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1795
////                                                              ////
1796
//// This source file may be used and distributed without         ////
1797
//// restriction provided that this copyright statement is not    ////
1798
//// removed from the file and that any derivative work contains  ////
1799
//// the original copyright notice and the associated disclaimer. ////
1800
////                                                              ////
1801
//// This source file is free software; you can redistribute it   ////
1802
//// and/or modify it under the terms of the GNU Lesser General   ////
1803
//// Public License as published by the Free Software Foundation; ////
1804
//// either version 2.1 of the License, or (at your option) any   ////
1805
//// later version.                                               ////
1806
////                                                              ////
1807
//// This source is distributed in the hope that it will be       ////
1808
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1809
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1810
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1811
//// details.                                                     ////
1812
////                                                              ////
1813
//// You should have received a copy of the GNU Lesser General    ////
1814
//// Public License along with this source; if not, download it   ////
1815
//// from http://www.opencores.org/lgpl.shtml                     ////
1816
////                                                              ////
1817
//////////////////////////////////////////////////////////////////////
1818
 
1819
// GRAY counter
1820 18 unneback
module vl_cnt_gray_ce ( cke, q, rst, clk);
1821 6 unneback
 
1822
   parameter length = 4;
1823
   input cke;
1824
   output reg [length:1] q;
1825
   input rst;
1826
   input clk;
1827
 
1828
   parameter clear_value = 0;
1829
   parameter set_value = 1;
1830
   parameter wrap_value = 8;
1831
   parameter level1_value = 15;
1832
 
1833
   reg  [length:1] qi;
1834
   wire [length:1] q_next;
1835
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1836
 
1837
   always @ (posedge clk or posedge rst)
1838
     if (rst)
1839
       qi <= {length{1'b0}};
1840
     else
1841
     if (cke)
1842
       qi <= q_next;
1843
 
1844
   always @ (posedge clk or posedge rst)
1845
     if (rst)
1846
       q <= {length{1'b0}};
1847
     else
1848
       if (cke)
1849
         q <= (q_next>>1) ^ q_next;
1850
 
1851
endmodule
1852
//////////////////////////////////////////////////////////////////////
1853
////                                                              ////
1854
////  Versatile counter                                           ////
1855
////                                                              ////
1856
////  Description                                                 ////
1857
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1858
////  counter                                                     ////
1859
////                                                              ////
1860
////  To Do:                                                      ////
1861
////   - add LFSR with more taps                                  ////
1862
////                                                              ////
1863
////  Author(s):                                                  ////
1864
////      - Michael Unneback, unneback@opencores.org              ////
1865
////        ORSoC AB                                              ////
1866
////                                                              ////
1867
//////////////////////////////////////////////////////////////////////
1868
////                                                              ////
1869
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1870
////                                                              ////
1871
//// This source file may be used and distributed without         ////
1872
//// restriction provided that this copyright statement is not    ////
1873
//// removed from the file and that any derivative work contains  ////
1874
//// the original copyright notice and the associated disclaimer. ////
1875
////                                                              ////
1876
//// This source file is free software; you can redistribute it   ////
1877
//// and/or modify it under the terms of the GNU Lesser General   ////
1878
//// Public License as published by the Free Software Foundation; ////
1879
//// either version 2.1 of the License, or (at your option) any   ////
1880
//// later version.                                               ////
1881
////                                                              ////
1882
//// This source is distributed in the hope that it will be       ////
1883
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1884
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1885
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1886
//// details.                                                     ////
1887
////                                                              ////
1888
//// You should have received a copy of the GNU Lesser General    ////
1889
//// Public License along with this source; if not, download it   ////
1890
//// from http://www.opencores.org/lgpl.shtml                     ////
1891
////                                                              ////
1892
//////////////////////////////////////////////////////////////////////
1893
 
1894
// GRAY counter
1895 18 unneback
module vl_cnt_gray_ce_bin ( cke, q, q_bin, rst, clk);
1896 6 unneback
 
1897
   parameter length = 4;
1898
   input cke;
1899
   output reg [length:1] q;
1900
   output [length:1] q_bin;
1901
   input rst;
1902
   input clk;
1903
 
1904
   parameter clear_value = 0;
1905
   parameter set_value = 1;
1906
   parameter wrap_value = 8;
1907
   parameter level1_value = 15;
1908
 
1909
   reg  [length:1] qi;
1910
   wire [length:1] q_next;
1911
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1912
 
1913
   always @ (posedge clk or posedge rst)
1914
     if (rst)
1915
       qi <= {length{1'b0}};
1916
     else
1917
     if (cke)
1918
       qi <= q_next;
1919
 
1920
   always @ (posedge clk or posedge rst)
1921
     if (rst)
1922
       q <= {length{1'b0}};
1923
     else
1924
       if (cke)
1925
         q <= (q_next>>1) ^ q_next;
1926
 
1927
   assign q_bin = qi;
1928
 
1929
endmodule
1930
//////////////////////////////////////////////////////////////////////
1931
////                                                              ////
1932
////  Versatile library, counters                                 ////
1933
////                                                              ////
1934
////  Description                                                 ////
1935
////  counters                                                    ////
1936
////                                                              ////
1937
////                                                              ////
1938
////  To Do:                                                      ////
1939
////   - add more counters                                        ////
1940
////                                                              ////
1941
////  Author(s):                                                  ////
1942
////      - Michael Unneback, unneback@opencores.org              ////
1943
////        ORSoC AB                                              ////
1944
////                                                              ////
1945
//////////////////////////////////////////////////////////////////////
1946
////                                                              ////
1947
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1948
////                                                              ////
1949
//// This source file may be used and distributed without         ////
1950
//// restriction provided that this copyright statement is not    ////
1951
//// removed from the file and that any derivative work contains  ////
1952
//// the original copyright notice and the associated disclaimer. ////
1953
////                                                              ////
1954
//// This source file is free software; you can redistribute it   ////
1955
//// and/or modify it under the terms of the GNU Lesser General   ////
1956
//// Public License as published by the Free Software Foundation; ////
1957
//// either version 2.1 of the License, or (at your option) any   ////
1958
//// later version.                                               ////
1959
////                                                              ////
1960
//// This source is distributed in the hope that it will be       ////
1961
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1962
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1963
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1964
//// details.                                                     ////
1965
////                                                              ////
1966
//// You should have received a copy of the GNU Lesser General    ////
1967
//// Public License along with this source; if not, download it   ////
1968
//// from http://www.opencores.org/lgpl.shtml                     ////
1969
////                                                              ////
1970
//////////////////////////////////////////////////////////////////////
1971
 
1972 18 unneback
module vl_cnt_shreg_wrap ( q, rst, clk);
1973 6 unneback
 
1974
   parameter length = 4;
1975
   output reg [0:length-1] q;
1976
   input rst;
1977
   input clk;
1978
 
1979
    always @ (posedge clk or posedge rst)
1980
    if (rst)
1981
        q <= {1'b1,{length-1{1'b0}}};
1982
    else
1983
        q <= {q[length-1],q[0:length-2]};
1984
 
1985
endmodule
1986
 
1987 18 unneback
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
1988 6 unneback
 
1989
   parameter length = 4;
1990
   input cke;
1991
   output reg [0:length-1] q;
1992
   input rst;
1993
   input clk;
1994
 
1995
    always @ (posedge clk or posedge rst)
1996
    if (rst)
1997
        q <= {1'b1,{length-1{1'b0}}};
1998
    else
1999
        if (cke)
2000
            q <= {q[length-1],q[0:length-2]};
2001
 
2002
endmodule
2003
 
2004 18 unneback
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
2005 6 unneback
 
2006
   parameter length = 4;
2007
   input cke, clear;
2008
   output reg [0:length-1] q;
2009
   input rst;
2010
   input clk;
2011
 
2012
    always @ (posedge clk or posedge rst)
2013
    if (rst)
2014
        q <= {1'b1,{length-1{1'b0}}};
2015
    else
2016
        if (cke)
2017
            if (clear)
2018
                q <= {1'b1,{length-1{1'b0}}};
2019
            else
2020
                q <= q >> 1;
2021
 
2022
endmodule
2023
 
2024 18 unneback
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
2025 6 unneback
 
2026
   parameter length = 4;
2027
   input cke, clear;
2028
   output reg [0:length-1] q;
2029
   input rst;
2030
   input clk;
2031
 
2032
    always @ (posedge clk or posedge rst)
2033
    if (rst)
2034
        q <= {1'b1,{length-1{1'b0}}};
2035
    else
2036
        if (cke)
2037
            if (clear)
2038
                q <= {1'b1,{length-1{1'b0}}};
2039
            else
2040
            q <= {q[length-1],q[0:length-2]};
2041
 
2042
endmodule
2043
//////////////////////////////////////////////////////////////////////
2044
////                                                              ////
2045
////  Versatile library, memories                                 ////
2046
////                                                              ////
2047
////  Description                                                 ////
2048
////  memories                                                    ////
2049
////                                                              ////
2050
////                                                              ////
2051
////  To Do:                                                      ////
2052
////   - add more memory types                                    ////
2053
////                                                              ////
2054
////  Author(s):                                                  ////
2055
////      - Michael Unneback, unneback@opencores.org              ////
2056
////        ORSoC AB                                              ////
2057
////                                                              ////
2058
//////////////////////////////////////////////////////////////////////
2059
////                                                              ////
2060
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2061
////                                                              ////
2062
//// This source file may be used and distributed without         ////
2063
//// restriction provided that this copyright statement is not    ////
2064
//// removed from the file and that any derivative work contains  ////
2065
//// the original copyright notice and the associated disclaimer. ////
2066
////                                                              ////
2067
//// This source file is free software; you can redistribute it   ////
2068
//// and/or modify it under the terms of the GNU Lesser General   ////
2069
//// Public License as published by the Free Software Foundation; ////
2070
//// either version 2.1 of the License, or (at your option) any   ////
2071
//// later version.                                               ////
2072
////                                                              ////
2073
//// This source is distributed in the hope that it will be       ////
2074
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2075
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2076
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2077
//// details.                                                     ////
2078
////                                                              ////
2079
//// You should have received a copy of the GNU Lesser General    ////
2080
//// Public License along with this source; if not, download it   ////
2081
//// from http://www.opencores.org/lgpl.shtml                     ////
2082
////                                                              ////
2083
//////////////////////////////////////////////////////////////////////
2084
 
2085
/// ROM
2086
 
2087 7 unneback
module vl_rom_init ( adr, q, clk);
2088
   parameter data_width = 32;
2089
   parameter addr_width = 8;
2090
   input [(addr_width-1):0]       adr;
2091
   output reg [(data_width-1):0] q;
2092
   input                         clk;
2093
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
2094
   parameter memory_file = "vl_rom.vmem";
2095
   initial
2096
     begin
2097
        $readmemh(memory_file, rom);
2098
     end
2099
 
2100
   always @ (posedge clk)
2101
     q <= rom[adr];
2102 6 unneback
 
2103 7 unneback
endmodule
2104
 
2105 14 unneback
/*
2106 7 unneback
module vl_rom ( adr, q, clk);
2107
 
2108 6 unneback
parameter data_width = 32;
2109
parameter addr_width = 4;
2110
 
2111
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
2112
    {32'h18000000},
2113
    {32'hA8200000},
2114
    {32'hA8200000},
2115
    {32'hA8200000},
2116
    {32'h44003000},
2117
    {32'h15000000},
2118
    {32'h15000000},
2119
    {32'h15000000},
2120
    {32'h15000000},
2121
    {32'h15000000},
2122
    {32'h15000000},
2123
    {32'h15000000},
2124
    {32'h15000000},
2125
    {32'h15000000},
2126
    {32'h15000000},
2127
    {32'h15000000}};
2128
 
2129 7 unneback
input [addr_width-1:0] adr;
2130 6 unneback
output reg [data_width-1:0] q;
2131
input clk;
2132
 
2133
always @ (posedge clk)
2134 7 unneback
    q <= data[adr];
2135 6 unneback
 
2136
endmodule
2137 14 unneback
*/
2138 6 unneback
// Single port RAM
2139
 
2140
module vl_ram ( d, adr, we, q, clk);
2141
   parameter data_width = 32;
2142
   parameter addr_width = 8;
2143
   input [(data_width-1):0]      d;
2144
   input [(addr_width-1):0]       adr;
2145
   input                         we;
2146 7 unneback
   output reg [(data_width-1):0] q;
2147 6 unneback
   input                         clk;
2148
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
2149 7 unneback
   parameter init = 0;
2150
   parameter memory_file = "vl_ram.vmem";
2151
   generate if (init) begin : init_mem
2152
   initial
2153
     begin
2154
        $readmemh(memory_file, ram);
2155
     end
2156
   end
2157
   endgenerate
2158
 
2159 6 unneback
   always @ (posedge clk)
2160
   begin
2161
   if (we)
2162
     ram[adr] <= d;
2163
   q <= ram[adr];
2164
   end
2165
 
2166
endmodule
2167
 
2168 7 unneback
module vl_ram_be ( d, adr, be, we, q, clk);
2169
   parameter data_width = 32;
2170
   parameter addr_width = 8;
2171
   input [(data_width-1):0]      d;
2172
   input [(addr_width-1):0]       adr;
2173
   input [(addr_width/4)-1:0]    be;
2174
   input                         we;
2175
   output reg [(data_width-1):0] q;
2176
   input                         clk;
2177
 
2178
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
2179
 
2180
   parameter init = 0;
2181
   parameter memory_file = "vl_ram.vmem";
2182
   generate if (init) begin : init_mem
2183
   initial
2184
     begin
2185
        $readmemh(memory_file, ram);
2186
     end
2187
   end
2188
   endgenerate
2189
 
2190
   genvar i;
2191
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
2192
      always @ (posedge clk)
2193
      if (we & be[i])
2194
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
2195
   end
2196
   endgenerate
2197
 
2198
   always @ (posedge clk)
2199
      q <= ram[adr];
2200
 
2201
endmodule
2202
 
2203
 
2204 6 unneback
// Dual port RAM
2205
 
2206
// ACTEL FPGA should not use logic to handle rw collision
2207
`ifdef ACTEL
2208
        `define SYN /*synthesis syn_ramstyle = "no_rw_check"*/
2209
`else
2210
        `define SYN
2211
`endif
2212
 
2213 7 unneback
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
2214 6 unneback
   parameter data_width = 32;
2215
   parameter addr_width = 8;
2216
   input [(data_width-1):0]      d_a;
2217
   input [(addr_width-1):0]       adr_a;
2218
   input [(addr_width-1):0]       adr_b;
2219
   input                         we_a;
2220
   output [(data_width-1):0]      q_b;
2221
   input                         clk_a, clk_b;
2222
   reg [(addr_width-1):0]         adr_b_reg;
2223
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
2224 7 unneback
 
2225
   parameter init = 0;
2226
   parameter memory_file = "vl_ram.vmem";
2227
   generate if (init) begin : init_mem
2228
   initial
2229
     begin
2230
        $readmemh(memory_file, ram);
2231
     end
2232
   end
2233
   endgenerate
2234
 
2235 6 unneback
   always @ (posedge clk_a)
2236
   if (we_a)
2237
     ram[adr_a] <= d_a;
2238
   always @ (posedge clk_b)
2239
   adr_b_reg <= adr_b;
2240
   assign q_b = ram[adr_b_reg];
2241
endmodule
2242
 
2243 7 unneback
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
2244 6 unneback
   parameter data_width = 32;
2245
   parameter addr_width = 8;
2246
   input [(data_width-1):0]      d_a;
2247
   input [(addr_width-1):0]       adr_a;
2248
   input [(addr_width-1):0]       adr_b;
2249
   input                         we_a;
2250
   output [(data_width-1):0]      q_b;
2251
   output reg [(data_width-1):0] q_a;
2252
   input                         clk_a, clk_b;
2253
   reg [(data_width-1):0]         q_b;
2254
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
2255 7 unneback
 
2256
   parameter init = 0;
2257
   parameter memory_file = "vl_ram.vmem";
2258
   generate if (init) begin : init_mem
2259
   initial
2260
     begin
2261
        $readmemh(memory_file, ram);
2262
     end
2263
   end
2264
   endgenerate
2265
 
2266 6 unneback
   always @ (posedge clk_a)
2267
     begin
2268
        q_a <= ram[adr_a];
2269
        if (we_a)
2270
             ram[adr_a] <= d_a;
2271
     end
2272
   always @ (posedge clk_b)
2273
          q_b <= ram[adr_b];
2274
endmodule
2275
 
2276 7 unneback
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
2277 6 unneback
   parameter data_width = 32;
2278
   parameter addr_width = 8;
2279
   input [(data_width-1):0]      d_a;
2280
   input [(addr_width-1):0]       adr_a;
2281
   input [(addr_width-1):0]       adr_b;
2282
   input                         we_a;
2283
   output [(data_width-1):0]      q_b;
2284
   input [(data_width-1):0]       d_b;
2285
   output reg [(data_width-1):0] q_a;
2286
   input                         we_b;
2287
   input                         clk_a, clk_b;
2288
   reg [(data_width-1):0]         q_b;
2289
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
2290 7 unneback
 
2291
   parameter init = 0;
2292
   parameter memory_file = "vl_ram.vmem";
2293
   generate if (init) begin : init_mem
2294
   initial
2295
     begin
2296
        $readmemh(memory_file, ram);
2297
     end
2298
   end
2299
   endgenerate
2300
 
2301 6 unneback
   always @ (posedge clk_a)
2302
     begin
2303
        q_a <= ram[adr_a];
2304
        if (we_a)
2305
             ram[adr_a] <= d_a;
2306
     end
2307
   always @ (posedge clk_b)
2308
     begin
2309
        q_b <= ram[adr_b];
2310
        if (we_b)
2311
          ram[adr_b] <= d_b;
2312
     end
2313
endmodule
2314
 
2315
// Content addresable memory, CAM
2316
 
2317
// FIFO
2318
 
2319
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
2320
 
2321 11 unneback
   parameter addr_width = 4;
2322
   parameter N = addr_width-1;
2323 6 unneback
 
2324
   parameter Q1 = 2'b00;
2325
   parameter Q2 = 2'b01;
2326
   parameter Q3 = 2'b11;
2327
   parameter Q4 = 2'b10;
2328
 
2329
   parameter going_empty = 1'b0;
2330
   parameter going_full  = 1'b1;
2331
 
2332
   input [N:0]  wptr, rptr;
2333 14 unneback
   output       fifo_empty;
2334 6 unneback
   output       fifo_full;
2335
   input        wclk, rclk, rst;
2336
 
2337
`ifndef GENERATE_DIRECTION_AS_LATCH
2338
   wire direction;
2339
`endif
2340
`ifdef GENERATE_DIRECTION_AS_LATCH
2341
   reg direction;
2342
`endif
2343
   reg  direction_set, direction_clr;
2344
 
2345
   wire async_empty, async_full;
2346
   wire fifo_full2;
2347 14 unneback
   wire fifo_empty2;
2348 6 unneback
 
2349
   // direction_set
2350
   always @ (wptr[N:N-1] or rptr[N:N-1])
2351
     case ({wptr[N:N-1],rptr[N:N-1]})
2352
       {Q1,Q2} : direction_set <= 1'b1;
2353
       {Q2,Q3} : direction_set <= 1'b1;
2354
       {Q3,Q4} : direction_set <= 1'b1;
2355
       {Q4,Q1} : direction_set <= 1'b1;
2356
       default : direction_set <= 1'b0;
2357
     endcase
2358
 
2359
   // direction_clear
2360
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
2361
     if (rst)
2362
       direction_clr <= 1'b1;
2363
     else
2364
       case ({wptr[N:N-1],rptr[N:N-1]})
2365
         {Q2,Q1} : direction_clr <= 1'b1;
2366
         {Q3,Q2} : direction_clr <= 1'b1;
2367
         {Q4,Q3} : direction_clr <= 1'b1;
2368
         {Q1,Q4} : direction_clr <= 1'b1;
2369
         default : direction_clr <= 1'b0;
2370
       endcase
2371
 
2372
`ifndef GENERATE_DIRECTION_AS_LATCH
2373 18 unneback
    vl_dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
2374 6 unneback
`endif
2375
 
2376
`ifdef GENERATE_DIRECTION_AS_LATCH
2377
   always @ (posedge direction_set or posedge direction_clr)
2378
     if (direction_clr)
2379
       direction <= going_empty;
2380
     else
2381
       direction <= going_full;
2382
`endif
2383
 
2384
   assign async_empty = (wptr == rptr) && (direction==going_empty);
2385
   assign async_full  = (wptr == rptr) && (direction==going_full);
2386
 
2387 18 unneback
    vl_dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
2388
    vl_dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
2389 6 unneback
 
2390
/*
2391
   always @ (posedge wclk or posedge rst or posedge async_full)
2392
     if (rst)
2393
       {fifo_full, fifo_full2} <= 2'b00;
2394
     else if (async_full)
2395
       {fifo_full, fifo_full2} <= 2'b11;
2396
     else
2397
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
2398
*/
2399 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
2400 6 unneback
     if (async_empty)
2401
       {fifo_empty, fifo_empty2} <= 2'b11;
2402
     else
2403 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
2404 18 unneback
    vl_dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
2405
    vl_dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
2406 6 unneback
 
2407
endmodule // async_comp
2408
 
2409
module vl_fifo_1r1w_async (
2410
    d, wr, fifo_full, wr_clk, wr_rst,
2411
    q, rd, fifo_empty, rd_clk, rd_rst
2412
    );
2413
 
2414
parameter data_width = 18;
2415
parameter addr_width = 4;
2416
 
2417
// write side
2418
input  [data_width-1:0] d;
2419
input                   wr;
2420
output                  fifo_full;
2421
input                   wr_clk;
2422
input                   wr_rst;
2423
// read side
2424
output [data_width-1:0] q;
2425
input                   rd;
2426
output                  fifo_empty;
2427
input                   rd_clk;
2428
input                   rd_rst;
2429
 
2430
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
2431 23 unneback
 
2432 18 unneback
vl_cnt_gray_ce_bin
2433 6 unneback
    # ( .length(addr_width))
2434
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
2435
 
2436 18 unneback
vl_cnt_gray_ce_bin
2437 6 unneback
    # (.length(addr_width))
2438 23 unneback
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
2439 6 unneback
 
2440 7 unneback
vl_dpram_1r1w
2441 6 unneback
    # (.data_width(data_width), .addr_width(addr_width))
2442
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
2443
 
2444
vl_fifo_cmp_async
2445
    # (.addr_width(addr_width))
2446
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
2447
 
2448
endmodule
2449
 
2450 8 unneback
module vl_fifo_2r2w_async (
2451 6 unneback
    // a side
2452
    a_d, a_wr, a_fifo_full,
2453
    a_q, a_rd, a_fifo_empty,
2454
    a_clk, a_rst,
2455
    // b side
2456
    b_d, b_wr, b_fifo_full,
2457
    b_q, b_rd, b_fifo_empty,
2458
    b_clk, b_rst
2459
    );
2460
 
2461
parameter data_width = 18;
2462
parameter addr_width = 4;
2463
 
2464
// a side
2465
input  [data_width-1:0] a_d;
2466
input                   a_wr;
2467
output                  a_fifo_full;
2468
output [data_width-1:0] a_q;
2469
input                   a_rd;
2470
output                  a_fifo_empty;
2471
input                   a_clk;
2472
input                   a_rst;
2473
 
2474
// b side
2475
input  [data_width-1:0] b_d;
2476
input                   b_wr;
2477
output                  b_fifo_full;
2478
output [data_width-1:0] b_q;
2479
input                   b_rd;
2480
output                  b_fifo_empty;
2481
input                   b_clk;
2482
input                   b_rst;
2483
 
2484
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
2485
vl_fifo_1r1w_async_a (
2486
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
2487
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
2488
    );
2489
 
2490
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
2491
vl_fifo_1r1w_async_b (
2492
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
2493
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
2494
    );
2495
 
2496
endmodule
2497
 
2498 8 unneback
module vl_fifo_2r2w_async_simplex (
2499 6 unneback
    // a side
2500
    a_d, a_wr, a_fifo_full,
2501
    a_q, a_rd, a_fifo_empty,
2502
    a_clk, a_rst,
2503
    // b side
2504
    b_d, b_wr, b_fifo_full,
2505
    b_q, b_rd, b_fifo_empty,
2506
    b_clk, b_rst
2507
    );
2508
 
2509
parameter data_width = 18;
2510
parameter addr_width = 4;
2511
 
2512
// a side
2513
input  [data_width-1:0] a_d;
2514
input                   a_wr;
2515
output                  a_fifo_full;
2516
output [data_width-1:0] a_q;
2517
input                   a_rd;
2518
output                  a_fifo_empty;
2519
input                   a_clk;
2520
input                   a_rst;
2521
 
2522
// b side
2523
input  [data_width-1:0] b_d;
2524
input                   b_wr;
2525
output                  b_fifo_full;
2526
output [data_width-1:0] b_q;
2527
input                   b_rd;
2528
output                  b_fifo_empty;
2529
input                   b_clk;
2530
input                   b_rst;
2531
 
2532
// adr_gen
2533
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
2534
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
2535
// dpram
2536
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
2537
 
2538 18 unneback
vl_cnt_gray_ce_bin
2539 6 unneback
    # ( .length(addr_width))
2540
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
2541
 
2542 18 unneback
vl_cnt_gray_ce_bin
2543 6 unneback
    # (.length(addr_width))
2544
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
2545
 
2546 18 unneback
vl_cnt_gray_ce_bin
2547 6 unneback
    # ( .length(addr_width))
2548
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
2549
 
2550 18 unneback
vl_cnt_gray_ce_bin
2551 6 unneback
    # (.length(addr_width))
2552
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
2553
 
2554
// mux read or write adr to DPRAM
2555
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
2556
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
2557
 
2558 11 unneback
vl_dpram_2r2w
2559 6 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
2560
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
2561
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
2562
 
2563 11 unneback
vl_fifo_cmp_async
2564 6 unneback
    # (.addr_width(addr_width))
2565
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
2566
 
2567 11 unneback
vl_fifo_cmp_async
2568 6 unneback
    # (.addr_width(addr_width))
2569
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
2570
 
2571
endmodule
2572 12 unneback
//////////////////////////////////////////////////////////////////////
2573
////                                                              ////
2574
////  Versatile library, wishbone stuff                           ////
2575
////                                                              ////
2576
////  Description                                                 ////
2577
////  Wishbone compliant modules                                  ////
2578
////                                                              ////
2579
////                                                              ////
2580
////  To Do:                                                      ////
2581
////   -                                                          ////
2582
////                                                              ////
2583
////  Author(s):                                                  ////
2584
////      - Michael Unneback, unneback@opencores.org              ////
2585
////        ORSoC AB                                              ////
2586
////                                                              ////
2587
//////////////////////////////////////////////////////////////////////
2588
////                                                              ////
2589
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2590
////                                                              ////
2591
//// This source file may be used and distributed without         ////
2592
//// restriction provided that this copyright statement is not    ////
2593
//// removed from the file and that any derivative work contains  ////
2594
//// the original copyright notice and the associated disclaimer. ////
2595
////                                                              ////
2596
//// This source file is free software; you can redistribute it   ////
2597
//// and/or modify it under the terms of the GNU Lesser General   ////
2598
//// Public License as published by the Free Software Foundation; ////
2599
//// either version 2.1 of the License, or (at your option) any   ////
2600
//// later version.                                               ////
2601
////                                                              ////
2602
//// This source is distributed in the hope that it will be       ////
2603
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2604
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2605
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2606
//// details.                                                     ////
2607
////                                                              ////
2608
//// You should have received a copy of the GNU Lesser General    ////
2609
//// Public License along with this source; if not, download it   ////
2610
//// from http://www.opencores.org/lgpl.shtml                     ////
2611
////                                                              ////
2612
//////////////////////////////////////////////////////////////////////
2613
 
2614
// async wb3 - wb3 bridge
2615
`timescale 1ns/1ns
2616 18 unneback
module vl_wb3wb3_bridge (
2617 12 unneback
        // wishbone slave side
2618
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
2619
        // wishbone master side
2620
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
2621
 
2622
input [31:0] wbs_dat_i;
2623
input [31:2] wbs_adr_i;
2624
input [3:0]  wbs_sel_i;
2625
input [1:0]  wbs_bte_i;
2626
input [2:0]  wbs_cti_i;
2627
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
2628
output [31:0] wbs_dat_o;
2629 14 unneback
output wbs_ack_o;
2630 12 unneback
input wbs_clk, wbs_rst;
2631
 
2632
output [31:0] wbm_dat_o;
2633
output reg [31:2] wbm_adr_o;
2634
output [3:0]  wbm_sel_o;
2635
output reg [1:0]  wbm_bte_o;
2636
output reg [2:0]  wbm_cti_o;
2637 14 unneback
output reg wbm_we_o;
2638
output wbm_cyc_o;
2639 12 unneback
output wbm_stb_o;
2640
input [31:0]  wbm_dat_i;
2641
input wbm_ack_i;
2642
input wbm_clk, wbm_rst;
2643
 
2644
parameter addr_width = 4;
2645
 
2646
// bte
2647
parameter linear       = 2'b00;
2648
parameter wrap4        = 2'b01;
2649
parameter wrap8        = 2'b10;
2650
parameter wrap16       = 2'b11;
2651
// cti
2652
parameter classic      = 3'b000;
2653
parameter incburst     = 3'b010;
2654
parameter endofburst   = 3'b111;
2655
 
2656
parameter wbs_adr  = 1'b0;
2657
parameter wbs_data = 1'b1;
2658
 
2659
parameter wbm_adr0 = 2'b00;
2660
parameter wbm_adr1 = 2'b01;
2661
parameter wbm_data = 2'b10;
2662
 
2663
reg [1:0] wbs_bte_reg;
2664
reg wbs;
2665
wire wbs_eoc_alert, wbm_eoc_alert;
2666
reg wbs_eoc, wbm_eoc;
2667
reg [1:0] wbm;
2668
 
2669 14 unneback
wire [1:16] wbs_count, wbm_count;
2670 12 unneback
 
2671
wire [35:0] a_d, a_q, b_d, b_q;
2672
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
2673
reg a_rd_reg;
2674
wire b_rd_adr, b_rd_data;
2675 14 unneback
wire b_rd_data_reg;
2676
wire [35:0] temp;
2677 12 unneback
 
2678
`define WE 5
2679
`define BTE 4:3
2680
`define CTI 2:0
2681
 
2682
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
2683
always @ (posedge wbs_clk or posedge wbs_rst)
2684
if (wbs_rst)
2685
        wbs_eoc <= 1'b0;
2686
else
2687
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
2688
                wbs_eoc <= wbs_bte_i==linear;
2689
        else if (wbs_eoc_alert & (a_rd | a_wr))
2690
                wbs_eoc <= 1'b1;
2691
 
2692 18 unneback
vl_cnt_shreg_ce_clear # ( .length(16))
2693 12 unneback
    cnt0 (
2694
        .cke(wbs_ack_o),
2695
        .clear(wbs_eoc),
2696
        .q(wbs_count),
2697
        .rst(wbs_rst),
2698
        .clk(wbs_clk));
2699
 
2700
always @ (posedge wbs_clk or posedge wbs_rst)
2701
if (wbs_rst)
2702
        wbs <= wbs_adr;
2703
else
2704
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & !a_fifo_full)
2705
                wbs <= wbs_data;
2706
        else if (wbs_eoc & wbs_ack_o)
2707
                wbs <= wbs_adr;
2708
 
2709
// wbs FIFO
2710
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,wbs_bte_i,wbs_cti_i} : {wbs_dat_i,wbs_sel_i};
2711
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & !a_fifo_full :
2712
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
2713
              1'b0;
2714
assign a_rd = !a_fifo_empty;
2715
always @ (posedge wbs_clk or posedge wbs_rst)
2716
if (wbs_rst)
2717
        a_rd_reg <= 1'b0;
2718
else
2719
        a_rd_reg <= a_rd;
2720
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
2721
 
2722
assign wbs_dat_o = a_q[35:4];
2723
 
2724
always @ (posedge wbs_clk or posedge wbs_rst)
2725
if (wbs_rst)
2726 13 unneback
        wbs_bte_reg <= 2'b00;
2727 12 unneback
else
2728 13 unneback
        wbs_bte_reg <= wbs_bte_i;
2729 12 unneback
 
2730
// wbm FIFO
2731
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
2732
always @ (posedge wbm_clk or posedge wbm_rst)
2733
if (wbm_rst)
2734
        wbm_eoc <= 1'b0;
2735
else
2736
        if (wbm==wbm_adr0 & !b_fifo_empty)
2737
                wbm_eoc <= b_q[`BTE] == linear;
2738
        else if (wbm_eoc_alert & wbm_ack_i)
2739
                wbm_eoc <= 1'b1;
2740
 
2741
always @ (posedge wbm_clk or posedge wbm_rst)
2742
if (wbm_rst)
2743
        wbm <= wbm_adr0;
2744
else
2745
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
2746
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
2747
        (wbm==wbm_adr1 & !wbm_we_o) |
2748
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
2749
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
2750
 
2751
assign b_d = {wbm_dat_i,4'b1111};
2752
assign b_wr = !wbm_we_o & wbm_ack_i;
2753
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
2754
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
2755
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
2756