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1 6 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  Versatile library, clock and reset                          ////
4
////                                                              ////
5
////  Description                                                 ////
6
////  Logic related to clock and reset                            ////
7
////                                                              ////
8
////                                                              ////
9
////  To Do:                                                      ////
10
////   - add more different registers                             ////
11
////                                                              ////
12
////  Author(s):                                                  ////
13
////      - Michael Unneback, unneback@opencores.org              ////
14
////        ORSoC AB                                              ////
15
////                                                              ////
16
//////////////////////////////////////////////////////////////////////
17
////                                                              ////
18
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
19
////                                                              ////
20
//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
36
////                                                              ////
37
//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
 
43
// Global buffer
44
// usage:
45
// use to enable global buffers for high fan out signals such as clock and reset
46
 
47
`ifdef ACTEL
48
 
49
`timescale 1 ns/100 ps
50
// Version: 8.4 8.4.0.33
51
module gbuf(GL,CLK);
52
output GL;
53
input  CLK;
54
 
55
    wire GND;
56
 
57
    GND GND_1_net(.Y(GND));
58
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
59
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
60
 
61
endmodule
62
`timescale 1 ns/1 ns
63
module vl_gbuf ( i, o);
64
input i;
65
output o;
66
`ifdef SIM_GBUF
67
assign o=i;
68
`else
69
gbuf gbuf_i0 ( .CLK(i), .GL(o));
70
`endif
71
endmodule
72
`else
73
`ifdef ALTERA
74 21 unneback
//altera
75 6 unneback
`else
76
 
77
`timescale 1 ns/100 ps
78
module vl_gbuf ( i, o);
79
input i;
80
output o;
81
assign o = i;
82
endmodule
83
`endif // ALTERA
84
`endif //ACTEL
85
 
86
// sync reset
87 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
88 6 unneback
// output active high global reset sync with two DFFs 
89
`timescale 1 ns/100 ps
90
module vl_sync_rst ( rst_n_i, rst_o, clk);
91
input rst_n_i, clk;
92
output rst_o;
93 18 unneback
reg [1:0] tmp;
94 6 unneback
always @ (posedge clk or negedge rst_n_i)
95
if (!rst_n_i)
96 17 unneback
        tmp <= 2'b11;
97 6 unneback
else
98 17 unneback
        tmp <= {1'b0,tmp[0]};
99
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
100 6 unneback
endmodule
101
 
102
// vl_pll
103
`ifdef ACTEL
104 17 unneback
`timescale 1 ps/1 ps
105 6 unneback
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
106
parameter index = 0;
107
parameter number_of_clk = 1;
108 17 unneback
parameter period_time_0 = 20000;
109
parameter period_time_1 = 20000;
110
parameter period_time_2 = 20000;
111
parameter lock_delay = 2000000;
112 6 unneback
input clk_i, rst_n_i;
113
output lock;
114
output reg [0:number_of_clk-1] clk_o;
115
output [0:number_of_clk-1] rst_o;
116
 
117
`ifdef SIM_PLL
118
 
119
always
120
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
121
 
122
generate if (number_of_clk > 1)
123
always
124
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
125
endgenerate
126
 
127
generate if (number_of_clk > 2)
128
always
129
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
130
endgenerate
131
 
132
genvar i;
133
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
134
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
135
end
136
endgenerate
137
 
138
assign #lock_delay lock = rst_n_i;
139
 
140
endmodule
141
`else
142
generate if (number_of_clk==1 & index==0) begin
143
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
144
end
145
endgenerate // index==0
146
generate if (number_of_clk==1 & index==1) begin
147
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
148
end
149
endgenerate // index==1
150
generate if (number_of_clk==1 & index==2) begin
151
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
152
end
153
endgenerate // index==2
154
generate if (number_of_clk==1 & index==3) begin
155
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
156
end
157
endgenerate // index==0
158
 
159
generate if (number_of_clk==2 & index==0) begin
160
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
161
end
162
endgenerate // index==0
163
generate if (number_of_clk==2 & index==1) begin
164
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
165
end
166
endgenerate // index==1
167
generate if (number_of_clk==2 & index==2) begin
168
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
169
end
170
endgenerate // index==2
171
generate if (number_of_clk==2 & index==3) begin
172
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
173
end
174
endgenerate // index==0
175
 
176
generate if (number_of_clk==3 & index==0) begin
177
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
178
end
179
endgenerate // index==0
180
generate if (number_of_clk==3 & index==1) begin
181
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
182
end
183
endgenerate // index==1
184
generate if (number_of_clk==3 & index==2) begin
185
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
186
end
187
endgenerate // index==2
188
generate if (number_of_clk==3 & index==3) begin
189
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
190
end
191
endgenerate // index==0
192
 
193
genvar i;
194
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
195
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
196
end
197
endgenerate
198
endmodule
199
`endif
200
 
201
`else
202
 
203
`ifdef ALTERA
204
 
205
`else
206
 
207
// generic PLL
208 17 unneback
`timescale 1 ps/1 ps
209 6 unneback
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
210
parameter index = 0;
211
parameter number_of_clk = 1;
212 17 unneback
parameter period_time_0 = 20000;
213
parameter period_time_1 = 20000;
214
parameter period_time_2 = 20000;
215 6 unneback
parameter lock_delay = 2000;
216
input clk_i, rst_n_i;
217
output lock;
218
output reg [0:number_of_clk-1] clk_o;
219
output [0:number_of_clk-1] rst_o;
220
 
221
always
222
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
223
 
224
generate if (number_of_clk > 1)
225
always
226
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
227
endgenerate
228
 
229
generate if (number_of_clk > 2)
230
always
231
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
232
endgenerate
233
 
234
genvar i;
235
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
236
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
237
end
238
endgenerate
239
 
240
assign #lock_delay lock = rst_n_i;
241
 
242
endmodule
243
 
244
`endif //altera
245 17 unneback
`endif //actel
246
//////////////////////////////////////////////////////////////////////
247 6 unneback
////                                                              ////
248
////  Versatile library, registers                                ////
249
////                                                              ////
250
////  Description                                                 ////
251
////  Different type of registers                                 ////
252
////                                                              ////
253
////                                                              ////
254
////  To Do:                                                      ////
255
////   - add more different registers                             ////
256
////                                                              ////
257
////  Author(s):                                                  ////
258
////      - Michael Unneback, unneback@opencores.org              ////
259
////        ORSoC AB                                              ////
260
////                                                              ////
261
//////////////////////////////////////////////////////////////////////
262
////                                                              ////
263
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
264
////                                                              ////
265
//// This source file may be used and distributed without         ////
266
//// restriction provided that this copyright statement is not    ////
267
//// removed from the file and that any derivative work contains  ////
268
//// the original copyright notice and the associated disclaimer. ////
269
////                                                              ////
270
//// This source file is free software; you can redistribute it   ////
271
//// and/or modify it under the terms of the GNU Lesser General   ////
272
//// Public License as published by the Free Software Foundation; ////
273
//// either version 2.1 of the License, or (at your option) any   ////
274
//// later version.                                               ////
275
////                                                              ////
276
//// This source is distributed in the hope that it will be       ////
277
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
278
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
279
//// PURPOSE.  See the GNU Lesser General Public License for more ////
280
//// details.                                                     ////
281
////                                                              ////
282
//// You should have received a copy of the GNU Lesser General    ////
283
//// Public License along with this source; if not, download it   ////
284
//// from http://www.opencores.org/lgpl.shtml                     ////
285
////                                                              ////
286
//////////////////////////////////////////////////////////////////////
287
 
288 18 unneback
module vl_dff ( d, q, clk, rst);
289 6 unneback
 
290
        parameter width = 1;
291
        parameter reset_value = 0;
292
 
293
        input [width-1:0] d;
294
        input clk, rst;
295
        output reg [width-1:0] q;
296
 
297
        always @ (posedge clk or posedge rst)
298
        if (rst)
299
                q <= reset_value;
300
        else
301
                q <= d;
302
 
303
endmodule
304
 
305 18 unneback
module vl_dff_array ( d, q, clk, rst);
306 6 unneback
 
307
        parameter width = 1;
308
        parameter depth = 2;
309
        parameter reset_value = 1'b0;
310
 
311
        input [width-1:0] d;
312
        input clk, rst;
313
        output [width-1:0] q;
314
        reg  [0:depth-1] q_tmp [width-1:0];
315
        integer i;
316
        always @ (posedge clk or posedge rst)
317
        if (rst) begin
318
            for (i=0;i<depth;i=i+1)
319
                q_tmp[i] <= {width{reset_value}};
320
        end else begin
321
            q_tmp[0] <= d;
322
            for (i=1;i<depth;i=i+1)
323
                q_tmp[i] <= q_tmp[i-1];
324
        end
325
 
326
    assign q = q_tmp[depth-1];
327
 
328
endmodule
329
 
330 18 unneback
module vl_dff_ce ( d, ce, q, clk, rst);
331 6 unneback
 
332
        parameter width = 1;
333
        parameter reset_value = 0;
334
 
335
        input [width-1:0] d;
336
        input ce, clk, rst;
337
        output reg [width-1:0] q;
338
 
339
        always @ (posedge clk or posedge rst)
340
        if (rst)
341
                q <= reset_value;
342
        else
343
                if (ce)
344
                        q <= d;
345
 
346
endmodule
347
 
348 18 unneback
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
349 8 unneback
 
350
        parameter width = 1;
351
        parameter reset_value = 0;
352
 
353
        input [width-1:0] d;
354 10 unneback
        input ce, clear, clk, rst;
355 8 unneback
        output reg [width-1:0] q;
356
 
357
        always @ (posedge clk or posedge rst)
358
        if (rst)
359
            q <= reset_value;
360
        else
361
            if (ce)
362
                if (clear)
363
                    q <= {width{1'b0}};
364
                else
365
                    q <= d;
366
 
367
endmodule
368
 
369 24 unneback
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
370
 
371
        parameter width = 1;
372
        parameter reset_value = 0;
373
 
374
        input [width-1:0] d;
375
        input ce, set, clk, rst;
376
        output reg [width-1:0] q;
377
 
378
        always @ (posedge clk or posedge rst)
379
        if (rst)
380
            q <= reset_value;
381
        else
382
            if (ce)
383
                if (set)
384
                    q <= {width{1'b1}};
385
                else
386
                    q <= d;
387
 
388
endmodule
389
 
390 6 unneback
`ifdef ALTERA
391
// megafunction wizard: %LPM_FF%
392
// GENERATION: STANDARD
393
// VERSION: WM1.0
394
// MODULE: lpm_ff 
395
 
396
// ============================================================
397
// File Name: dff_sr.v
398
// Megafunction Name(s):
399
//                      lpm_ff
400
//
401
// Simulation Library Files(s):
402
//                      lpm
403
// ============================================================
404
// ************************************************************
405
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
406
//
407
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
408
// ************************************************************
409
 
410
 
411
//Copyright (C) 1991-2010 Altera Corporation
412
//Your use of Altera Corporation's design tools, logic functions 
413
//and other software and tools, and its AMPP partner logic 
414
//functions, and any output files from any of the foregoing 
415
//(including device programming or simulation files), and any 
416
//associated documentation or information are expressly subject 
417
//to the terms and conditions of the Altera Program License 
418
//Subscription Agreement, Altera MegaCore Function License 
419
//Agreement, or other applicable license agreement, including, 
420
//without limitation, that your use is for the sole purpose of 
421
//programming logic devices manufactured by Altera and sold by 
422
//Altera or its authorized distributors.  Please refer to the 
423
//applicable agreement for further details.
424
 
425
 
426
// synopsys translate_off
427
`timescale 1 ps / 1 ps
428
// synopsys translate_on
429 18 unneback
module vl_dff_sr (
430 6 unneback
        aclr,
431
        aset,
432
        clock,
433
        data,
434
        q);
435
 
436
        input     aclr;
437
        input     aset;
438
        input     clock;
439
        input     data;
440
        output    q;
441
 
442
        wire [0:0] sub_wire0;
443
        wire [0:0] sub_wire1 = sub_wire0[0:0];
444
        wire  q = sub_wire1;
445
        wire  sub_wire2 = data;
446
        wire  sub_wire3 = sub_wire2;
447
 
448
        lpm_ff  lpm_ff_component (
449
                                .aclr (aclr),
450
                                .clock (clock),
451
                                .data (sub_wire3),
452
                                .aset (aset),
453
                                .q (sub_wire0)
454
                                // synopsys translate_off
455
                                ,
456
                                .aload (),
457
                                .enable (),
458
                                .sclr (),
459
                                .sload (),
460
                                .sset ()
461
                                // synopsys translate_on
462
                                );
463
        defparam
464
                lpm_ff_component.lpm_fftype = "DFF",
465
                lpm_ff_component.lpm_type = "LPM_FF",
466
                lpm_ff_component.lpm_width = 1;
467
 
468
 
469
endmodule
470
 
471
// ============================================================
472
// CNX file retrieval info
473
// ============================================================
474
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
475
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
476
// Retrieval info: PRIVATE: ASET NUMERIC "1"
477
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
478
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
479
// Retrieval info: PRIVATE: DFF NUMERIC "1"
480
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
481
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
482
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
483
// Retrieval info: PRIVATE: SSET NUMERIC "0"
484
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
485
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
486
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
487
// Retrieval info: PRIVATE: nBit NUMERIC "1"
488
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
489
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
490
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
491
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
492
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
493
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
494
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
495
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
496
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
497
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
498
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
499
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
500
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
501
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
502
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
503
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
504
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
505
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
506
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
507
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
508
// Retrieval info: LIB_FILE: lpm
509
 
510
 
511
`else
512
 
513
 
514 18 unneback
module vl_dff_sr ( aclr, aset, clock, data, q);
515 6 unneback
 
516
    input         aclr;
517
    input         aset;
518
    input         clock;
519
    input         data;
520
    output reg    q;
521
 
522
   always @ (posedge clock or posedge aclr or posedge aset)
523
     if (aclr)
524
       q <= 1'b0;
525
     else if (aset)
526
       q <= 1'b1;
527
     else
528
       q <= data;
529
 
530
endmodule
531
 
532
`endif
533
 
534
// LATCH
535
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
536
`ifdef ALTERA
537 18 unneback
module vl_latch ( d, le, q, clk);
538 6 unneback
input d, le;
539
output q;
540
input clk;
541
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
542
endmodule
543
`else
544
module latch ( d, le, q, clk);
545
input d, le;
546
output q;
547
input clk;/*
548
   always @ (posedge direction_set or posedge direction_clr)
549
     if (direction_clr)
550
       direction <= going_empty;
551
     else
552
       direction <= going_full;*/
553
endmodule
554 15 unneback
`endif
555
 
556 18 unneback
module vl_shreg ( d, q, clk, rst);
557 17 unneback
parameter depth = 10;
558
input d;
559
output q;
560
input clk, rst;
561
 
562
reg [1:depth] dffs;
563
 
564
always @ (posedge clk or posedge rst)
565
if (rst)
566
    dffs <= {depth{1'b0}};
567
else
568
    dffs <= {d,dffs[1:depth-1]};
569
assign q = dffs[depth];
570
endmodule
571
 
572 18 unneback
module vl_shreg_ce ( d, ce, q, clk, rst);
573 17 unneback
parameter depth = 10;
574
input d, ce;
575
output q;
576
input clk, rst;
577
 
578
reg [1:depth] dffs;
579
 
580
always @ (posedge clk or posedge rst)
581
if (rst)
582
    dffs <= {depth{1'b0}};
583
else
584
    if (ce)
585
        dffs <= {d,dffs[1:depth-1]};
586
assign q = dffs[depth];
587
endmodule
588
 
589 18 unneback
module vl_delay ( d, q, clk, rst);
590 15 unneback
parameter depth = 10;
591
input d;
592
output q;
593
input clk, rst;
594
 
595
reg [1:depth] dffs;
596
 
597
always @ (posedge clk or posedge rst)
598
if (rst)
599
    dffs <= {depth{1'b0}};
600
else
601
    dffs <= {d,dffs[1:depth-1]};
602
assign q = dffs[depth];
603 17 unneback
endmodule
604
 
605 18 unneback
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
606 17 unneback
parameter depth = 10;
607
input d;
608
output q, emptyflag;
609
input clk, rst;
610
 
611
reg [1:depth] dffs;
612
 
613
always @ (posedge clk or posedge rst)
614
if (rst)
615
    dffs <= {depth{1'b0}};
616
else
617
    dffs <= {d,dffs[1:depth-1]};
618
assign q = dffs[depth];
619
assign emptyflag = !(|dffs);
620
endmodule
621
//////////////////////////////////////////////////////////////////////
622 6 unneback
////                                                              ////
623 18 unneback
////  Logic functions                                             ////
624
////                                                              ////
625
////  Description                                                 ////
626
////  Logic functions such as multiplexers                        ////
627
////                                                              ////
628
////                                                              ////
629
////  To Do:                                                      ////
630
////   -                                                          ////
631
////                                                              ////
632
////  Author(s):                                                  ////
633
////      - Michael Unneback, unneback@opencores.org              ////
634
////        ORSoC AB                                              ////
635
////                                                              ////
636
//////////////////////////////////////////////////////////////////////
637
////                                                              ////
638
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
639
////                                                              ////
640
//// This source file may be used and distributed without         ////
641
//// restriction provided that this copyright statement is not    ////
642
//// removed from the file and that any derivative work contains  ////
643
//// the original copyright notice and the associated disclaimer. ////
644
////                                                              ////
645
//// This source file is free software; you can redistribute it   ////
646
//// and/or modify it under the terms of the GNU Lesser General   ////
647
//// Public License as published by the Free Software Foundation; ////
648
//// either version 2.1 of the License, or (at your option) any   ////
649
//// later version.                                               ////
650
////                                                              ////
651
//// This source is distributed in the hope that it will be       ////
652
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
653
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
654
//// PURPOSE.  See the GNU Lesser General Public License for more ////
655
//// details.                                                     ////
656
////                                                              ////
657
//// You should have received a copy of the GNU Lesser General    ////
658
//// Public License along with this source; if not, download it   ////
659
//// from http://www.opencores.org/lgpl.shtml                     ////
660
////                                                              ////
661
//////////////////////////////////////////////////////////////////////
662
 
663
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
664
 
665
parameter width = 32;
666
parameter nr_of_ports = 4;
667
input [width-1:0] a3, a2, a1, a0;
668
input [nr_of_ports-1:0] sel;
669 22 unneback
output [width-1:0] dout;
670 18 unneback
 
671 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
672 18 unneback
integer i;
673
 
674
// and
675
assign tmp[0] = {width{sel[0]}} & a0;
676
assign tmp[1] = {width{sel[1]}} & a1;
677
assign tmp[2] = {width{sel[2]}} & a2;
678
assign tmp[3] = {width{sel[3]}} & a3;
679
 
680
// or
681
assign dout = tmp[3] | tmp[2] | tmp[1] | tmp[0];
682
 
683
endmodule
684
 
685
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
686
 
687
parameter width = 32;
688
parameter nr_of_ports = 5;
689
input [width-1:0] a4, a3, a2, a1, a0;
690
input [nr_of_ports-1:0] sel;
691 22 unneback
output [width-1:0] dout;
692 18 unneback
 
693 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
694 18 unneback
integer i;
695
 
696
// and
697
assign tmp[0] = {width{sel[0]}} & a0;
698
assign tmp[1] = {width{sel[1]}} & a1;
699
assign tmp[2] = {width{sel[2]}} & a2;
700
assign tmp[3] = {width{sel[3]}} & a3;
701
assign tmp[4] = {width{sel[4]}} & a4;
702
 
703
// or
704
assign dout = tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
705
 
706
endmodule
707
 
708
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
709
 
710
parameter width = 32;
711
parameter nr_of_ports = 6;
712
input [width-1:0] a5, a4, a3, a2, a1, a0;
713
input [nr_of_ports-1:0] sel;
714 22 unneback
output [width-1:0] dout;
715 18 unneback
 
716 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
717 18 unneback
integer i;
718
 
719
// and
720
assign tmp[0] = {width{sel[0]}} & a0;
721
assign tmp[1] = {width{sel[1]}} & a1;
722
assign tmp[2] = {width{sel[2]}} & a2;
723
assign tmp[3] = {width{sel[3]}} & a3;
724
assign tmp[4] = {width{sel[4]}} & a4;
725
assign tmp[5] = {width{sel[5]}} & a5;
726
 
727
// or
728
assign dout = tmp[5] | tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
729
 
730
endmodule
731
//////////////////////////////////////////////////////////////////////
732
////                                                              ////
733 6 unneback
////  Versatile counter                                           ////
734
////                                                              ////
735
////  Description                                                 ////
736
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
737
////  counter                                                     ////
738
////                                                              ////
739
////  To Do:                                                      ////
740
////   - add LFSR with more taps                                  ////
741
////                                                              ////
742
////  Author(s):                                                  ////
743
////      - Michael Unneback, unneback@opencores.org              ////
744
////        ORSoC AB                                              ////
745
////                                                              ////
746
//////////////////////////////////////////////////////////////////////
747
////                                                              ////
748
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
749
////                                                              ////
750
//// This source file may be used and distributed without         ////
751
//// restriction provided that this copyright statement is not    ////
752
//// removed from the file and that any derivative work contains  ////
753
//// the original copyright notice and the associated disclaimer. ////
754
////                                                              ////
755
//// This source file is free software; you can redistribute it   ////
756
//// and/or modify it under the terms of the GNU Lesser General   ////
757
//// Public License as published by the Free Software Foundation; ////
758
//// either version 2.1 of the License, or (at your option) any   ////
759
//// later version.                                               ////
760
////                                                              ////
761
//// This source is distributed in the hope that it will be       ////
762
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
763
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
764
//// PURPOSE.  See the GNU Lesser General Public License for more ////
765
//// details.                                                     ////
766
////                                                              ////
767
//// You should have received a copy of the GNU Lesser General    ////
768
//// Public License along with this source; if not, download it   ////
769
//// from http://www.opencores.org/lgpl.shtml                     ////
770
////                                                              ////
771
//////////////////////////////////////////////////////////////////////
772
 
773
// binary counter
774 22 unneback
module vl_cnt_bin ( q, rst, clk);
775
 
776
   parameter length = 4;
777
   output [length:1] q;
778
   input rst;
779
   input clk;
780
 
781
   parameter clear_value = 0;
782
   parameter set_value = 1;
783
   parameter wrap_value = 0;
784
   parameter level1_value = 15;
785
 
786
   reg  [length:1] qi;
787
   wire [length:1] q_next;
788
   assign q_next = qi + {{length-1{1'b0}},1'b1};
789
 
790
   always @ (posedge clk or posedge rst)
791
     if (rst)
792
       qi <= {length{1'b0}};
793
     else
794
       qi <= q_next;
795
 
796
   assign q = qi;
797
 
798
endmodule
799
//////////////////////////////////////////////////////////////////////
800
////                                                              ////
801
////  Versatile counter                                           ////
802
////                                                              ////
803
////  Description                                                 ////
804
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
805
////  counter                                                     ////
806
////                                                              ////
807
////  To Do:                                                      ////
808
////   - add LFSR with more taps                                  ////
809
////                                                              ////
810
////  Author(s):                                                  ////
811
////      - Michael Unneback, unneback@opencores.org              ////
812
////        ORSoC AB                                              ////
813
////                                                              ////
814
//////////////////////////////////////////////////////////////////////
815
////                                                              ////
816
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
817
////                                                              ////
818
//// This source file may be used and distributed without         ////
819
//// restriction provided that this copyright statement is not    ////
820
//// removed from the file and that any derivative work contains  ////
821
//// the original copyright notice and the associated disclaimer. ////
822
////                                                              ////
823
//// This source file is free software; you can redistribute it   ////
824
//// and/or modify it under the terms of the GNU Lesser General   ////
825
//// Public License as published by the Free Software Foundation; ////
826
//// either version 2.1 of the License, or (at your option) any   ////
827
//// later version.                                               ////
828
////                                                              ////
829
//// This source is distributed in the hope that it will be       ////
830
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
831
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
832
//// PURPOSE.  See the GNU Lesser General Public License for more ////
833
//// details.                                                     ////
834
////                                                              ////
835
//// You should have received a copy of the GNU Lesser General    ////
836
//// Public License along with this source; if not, download it   ////
837
//// from http://www.opencores.org/lgpl.shtml                     ////
838
////                                                              ////
839
//////////////////////////////////////////////////////////////////////
840
 
841
// binary counter
842
module vl_cnt_bin_clear ( clear, q, rst, clk);
843
 
844
   parameter length = 4;
845
   input clear;
846
   output [length:1] q;
847
   input rst;
848
   input clk;
849
 
850
   parameter clear_value = 0;
851
   parameter set_value = 1;
852
   parameter wrap_value = 0;
853
   parameter level1_value = 15;
854
 
855
   reg  [length:1] qi;
856
   wire [length:1] q_next;
857
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
858
 
859
   always @ (posedge clk or posedge rst)
860
     if (rst)
861
       qi <= {length{1'b0}};
862
     else
863
       qi <= q_next;
864
 
865
   assign q = qi;
866
 
867
endmodule
868
//////////////////////////////////////////////////////////////////////
869
////                                                              ////
870
////  Versatile counter                                           ////
871
////                                                              ////
872
////  Description                                                 ////
873
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
874
////  counter                                                     ////
875
////                                                              ////
876
////  To Do:                                                      ////
877
////   - add LFSR with more taps                                  ////
878
////                                                              ////
879
////  Author(s):                                                  ////
880
////      - Michael Unneback, unneback@opencores.org              ////
881
////        ORSoC AB                                              ////
882
////                                                              ////
883
//////////////////////////////////////////////////////////////////////
884
////                                                              ////
885
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
886
////                                                              ////
887
//// This source file may be used and distributed without         ////
888
//// restriction provided that this copyright statement is not    ////
889
//// removed from the file and that any derivative work contains  ////
890
//// the original copyright notice and the associated disclaimer. ////
891
////                                                              ////
892
//// This source file is free software; you can redistribute it   ////
893
//// and/or modify it under the terms of the GNU Lesser General   ////
894
//// Public License as published by the Free Software Foundation; ////
895
//// either version 2.1 of the License, or (at your option) any   ////
896
//// later version.                                               ////
897
////                                                              ////
898
//// This source is distributed in the hope that it will be       ////
899
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
900
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
901
//// PURPOSE.  See the GNU Lesser General Public License for more ////
902
//// details.                                                     ////
903
////                                                              ////
904
//// You should have received a copy of the GNU Lesser General    ////
905
//// Public License along with this source; if not, download it   ////
906
//// from http://www.opencores.org/lgpl.shtml                     ////
907
////                                                              ////
908
//////////////////////////////////////////////////////////////////////
909
 
910
// binary counter
911 18 unneback
module vl_cnt_bin_ce ( cke, q, rst, clk);
912 6 unneback
 
913
   parameter length = 4;
914
   input cke;
915
   output [length:1] q;
916
   input rst;
917
   input clk;
918
 
919
   parameter clear_value = 0;
920
   parameter set_value = 1;
921
   parameter wrap_value = 0;
922
   parameter level1_value = 15;
923
 
924
   reg  [length:1] qi;
925
   wire [length:1] q_next;
926
   assign q_next = qi + {{length-1{1'b0}},1'b1};
927
 
928
   always @ (posedge clk or posedge rst)
929
     if (rst)
930
       qi <= {length{1'b0}};
931
     else
932
     if (cke)
933
       qi <= q_next;
934
 
935
   assign q = qi;
936
 
937
endmodule
938
//////////////////////////////////////////////////////////////////////
939
////                                                              ////
940
////  Versatile counter                                           ////
941
////                                                              ////
942
////  Description                                                 ////
943
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
944
////  counter                                                     ////
945
////                                                              ////
946
////  To Do:                                                      ////
947
////   - add LFSR with more taps                                  ////
948
////                                                              ////
949
////  Author(s):                                                  ////
950
////      - Michael Unneback, unneback@opencores.org              ////
951
////        ORSoC AB                                              ////
952
////                                                              ////
953
//////////////////////////////////////////////////////////////////////
954
////                                                              ////
955
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
956
////                                                              ////
957
//// This source file may be used and distributed without         ////
958
//// restriction provided that this copyright statement is not    ////
959
//// removed from the file and that any derivative work contains  ////
960
//// the original copyright notice and the associated disclaimer. ////
961
////                                                              ////
962
//// This source file is free software; you can redistribute it   ////
963
//// and/or modify it under the terms of the GNU Lesser General   ////
964
//// Public License as published by the Free Software Foundation; ////
965
//// either version 2.1 of the License, or (at your option) any   ////
966
//// later version.                                               ////
967
////                                                              ////
968
//// This source is distributed in the hope that it will be       ////
969
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
970
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
971
//// PURPOSE.  See the GNU Lesser General Public License for more ////
972
//// details.                                                     ////
973
////                                                              ////
974
//// You should have received a copy of the GNU Lesser General    ////
975
//// Public License along with this source; if not, download it   ////
976
//// from http://www.opencores.org/lgpl.shtml                     ////
977
////                                                              ////
978
//////////////////////////////////////////////////////////////////////
979
 
980
// binary counter
981 18 unneback
module vl_cnt_bin_ce_clear ( clear, cke, q, rst, clk);
982 6 unneback
 
983
   parameter length = 4;
984
   input clear;
985
   input cke;
986
   output [length:1] q;
987
   input rst;
988
   input clk;
989
 
990
   parameter clear_value = 0;
991
   parameter set_value = 1;
992
   parameter wrap_value = 0;
993
   parameter level1_value = 15;
994
 
995
   reg  [length:1] qi;
996
   wire [length:1] q_next;
997
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
998
 
999
   always @ (posedge clk or posedge rst)
1000
     if (rst)
1001
       qi <= {length{1'b0}};
1002
     else
1003
     if (cke)
1004
       qi <= q_next;
1005
 
1006
   assign q = qi;
1007
 
1008
endmodule
1009
//////////////////////////////////////////////////////////////////////
1010
////                                                              ////
1011
////  Versatile counter                                           ////
1012
////                                                              ////
1013
////  Description                                                 ////
1014
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1015
////  counter                                                     ////
1016
////                                                              ////
1017
////  To Do:                                                      ////
1018
////   - add LFSR with more taps                                  ////
1019
////                                                              ////
1020
////  Author(s):                                                  ////
1021
////      - Michael Unneback, unneback@opencores.org              ////
1022
////        ORSoC AB                                              ////
1023
////                                                              ////
1024
//////////////////////////////////////////////////////////////////////
1025
////                                                              ////
1026
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1027
////                                                              ////
1028
//// This source file may be used and distributed without         ////
1029
//// restriction provided that this copyright statement is not    ////
1030
//// removed from the file and that any derivative work contains  ////
1031
//// the original copyright notice and the associated disclaimer. ////
1032
////                                                              ////
1033
//// This source file is free software; you can redistribute it   ////
1034
//// and/or modify it under the terms of the GNU Lesser General   ////
1035
//// Public License as published by the Free Software Foundation; ////
1036
//// either version 2.1 of the License, or (at your option) any   ////
1037
//// later version.                                               ////
1038
////                                                              ////
1039
//// This source is distributed in the hope that it will be       ////
1040
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1041
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1042
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1043
//// details.                                                     ////
1044
////                                                              ////
1045
//// You should have received a copy of the GNU Lesser General    ////
1046
//// Public License along with this source; if not, download it   ////
1047
//// from http://www.opencores.org/lgpl.shtml                     ////
1048
////                                                              ////
1049
//////////////////////////////////////////////////////////////////////
1050
 
1051
// binary counter
1052 18 unneback
module vl_cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk);
1053 6 unneback
 
1054
   parameter length = 4;
1055
   input clear;
1056
   input set;
1057
   input cke;
1058
   input rew;
1059
   output [length:1] q;
1060
   input rst;
1061
   input clk;
1062
 
1063
   parameter clear_value = 0;
1064
   parameter set_value = 1;
1065
   parameter wrap_value = 0;
1066
   parameter level1_value = 15;
1067
 
1068
   reg  [length:1] qi;
1069
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1070
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
1071
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
1072
   assign q_next = rew ? q_next_rew : q_next_fw;
1073
 
1074
   always @ (posedge clk or posedge rst)
1075
     if (rst)
1076
       qi <= {length{1'b0}};
1077
     else
1078
     if (cke)
1079
       qi <= q_next;
1080
 
1081
   assign q = qi;
1082
 
1083
endmodule
1084
//////////////////////////////////////////////////////////////////////
1085
////                                                              ////
1086
////  Versatile counter                                           ////
1087
////                                                              ////
1088
////  Description                                                 ////
1089
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1090
////  counter                                                     ////
1091
////                                                              ////
1092
////  To Do:                                                      ////
1093
////   - add LFSR with more taps                                  ////
1094
////                                                              ////
1095
////  Author(s):                                                  ////
1096
////      - Michael Unneback, unneback@opencores.org              ////
1097
////        ORSoC AB                                              ////
1098
////                                                              ////
1099
//////////////////////////////////////////////////////////////////////
1100
////                                                              ////
1101
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1102
////                                                              ////
1103
//// This source file may be used and distributed without         ////
1104
//// restriction provided that this copyright statement is not    ////
1105
//// removed from the file and that any derivative work contains  ////
1106
//// the original copyright notice and the associated disclaimer. ////
1107
////                                                              ////
1108
//// This source file is free software; you can redistribute it   ////
1109
//// and/or modify it under the terms of the GNU Lesser General   ////
1110
//// Public License as published by the Free Software Foundation; ////
1111
//// either version 2.1 of the License, or (at your option) any   ////
1112
//// later version.                                               ////
1113
////                                                              ////
1114
//// This source is distributed in the hope that it will be       ////
1115
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1116
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1117
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1118
//// details.                                                     ////
1119
////                                                              ////
1120
//// You should have received a copy of the GNU Lesser General    ////
1121
//// Public License along with this source; if not, download it   ////
1122
//// from http://www.opencores.org/lgpl.shtml                     ////
1123
////                                                              ////
1124
//////////////////////////////////////////////////////////////////////
1125
 
1126
// binary counter
1127 18 unneback
module vl_cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk);
1128 6 unneback
 
1129
   parameter length = 4;
1130
   input cke;
1131
   input rew;
1132
   output reg level1;
1133
   input rst;
1134
   input clk;
1135
 
1136
   parameter clear_value = 0;
1137
   parameter set_value = 1;
1138
   parameter wrap_value = 1;
1139
   parameter level1_value = 15;
1140
 
1141
   reg  [length:1] qi;
1142
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1143
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1144
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1145
   assign q_next = rew ? q_next_rew : q_next_fw;
1146
 
1147
   always @ (posedge clk or posedge rst)
1148
     if (rst)
1149
       qi <= {length{1'b0}};
1150
     else
1151
     if (cke)
1152
       qi <= q_next;
1153
 
1154
 
1155
 
1156
    always @ (posedge clk or posedge rst)
1157
    if (rst)
1158
        level1 <= 1'b0;
1159
    else
1160
    if (cke)
1161
    if (q_next == level1_value)
1162
        level1 <= 1'b1;
1163
    else if (qi == level1_value & rew)
1164
        level1 <= 1'b0;
1165
endmodule
1166
//////////////////////////////////////////////////////////////////////
1167
////                                                              ////
1168
////  Versatile counter                                           ////
1169
////                                                              ////
1170
////  Description                                                 ////
1171
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1172
////  counter                                                     ////
1173
////                                                              ////
1174
////  To Do:                                                      ////
1175
////   - add LFSR with more taps                                  ////
1176
////                                                              ////
1177
////  Author(s):                                                  ////
1178
////      - Michael Unneback, unneback@opencores.org              ////
1179
////        ORSoC AB                                              ////
1180
////                                                              ////
1181
//////////////////////////////////////////////////////////////////////
1182
////                                                              ////
1183
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1184
////                                                              ////
1185
//// This source file may be used and distributed without         ////
1186
//// restriction provided that this copyright statement is not    ////
1187
//// removed from the file and that any derivative work contains  ////
1188
//// the original copyright notice and the associated disclaimer. ////
1189
////                                                              ////
1190
//// This source file is free software; you can redistribute it   ////
1191
//// and/or modify it under the terms of the GNU Lesser General   ////
1192
//// Public License as published by the Free Software Foundation; ////
1193
//// either version 2.1 of the License, or (at your option) any   ////
1194
//// later version.                                               ////
1195
////                                                              ////
1196
//// This source is distributed in the hope that it will be       ////
1197
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1198
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1199
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1200
//// details.                                                     ////
1201
////                                                              ////
1202
//// You should have received a copy of the GNU Lesser General    ////
1203
//// Public License along with this source; if not, download it   ////
1204
//// from http://www.opencores.org/lgpl.shtml                     ////
1205
////                                                              ////
1206
//////////////////////////////////////////////////////////////////////
1207
 
1208 25 unneback
// binary counter
1209
module vl_cnt_bin_ce_rew_zq_l1 ( cke, rew, zq, level1, rst, clk);
1210
 
1211
   parameter length = 4;
1212
   input cke;
1213
   input rew;
1214
   output reg zq;
1215
   output reg level1;
1216
   input rst;
1217
   input clk;
1218
 
1219
   parameter clear_value = 0;
1220
   parameter set_value = 1;
1221
   parameter wrap_value = 1;
1222
   parameter level1_value = 15;
1223
 
1224
   reg  [length:1] qi;
1225
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1226
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1227
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1228
   assign q_next = rew ? q_next_rew : q_next_fw;
1229
 
1230
   always @ (posedge clk or posedge rst)
1231
     if (rst)
1232
       qi <= {length{1'b0}};
1233
     else
1234
     if (cke)
1235
       qi <= q_next;
1236
 
1237
 
1238
 
1239
   always @ (posedge clk or posedge rst)
1240
     if (rst)
1241
       zq <= 1'b1;
1242
     else
1243
     if (cke)
1244
       zq <= q_next == {length{1'b0}};
1245
 
1246
    always @ (posedge clk or posedge rst)
1247
    if (rst)
1248
        level1 <= 1'b0;
1249
    else
1250
    if (cke)
1251
    if (q_next == level1_value)
1252
        level1 <= 1'b1;
1253
    else if (qi == level1_value & rew)
1254
        level1 <= 1'b0;
1255
endmodule
1256
//////////////////////////////////////////////////////////////////////
1257
////                                                              ////
1258
////  Versatile counter                                           ////
1259
////                                                              ////
1260
////  Description                                                 ////
1261
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1262
////  counter                                                     ////
1263
////                                                              ////
1264
////  To Do:                                                      ////
1265
////   - add LFSR with more taps                                  ////
1266
////                                                              ////
1267
////  Author(s):                                                  ////
1268
////      - Michael Unneback, unneback@opencores.org              ////
1269
////        ORSoC AB                                              ////
1270
////                                                              ////
1271
//////////////////////////////////////////////////////////////////////
1272
////                                                              ////
1273
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1274
////                                                              ////
1275
//// This source file may be used and distributed without         ////
1276
//// restriction provided that this copyright statement is not    ////
1277
//// removed from the file and that any derivative work contains  ////
1278
//// the original copyright notice and the associated disclaimer. ////
1279
////                                                              ////
1280
//// This source file is free software; you can redistribute it   ////
1281
//// and/or modify it under the terms of the GNU Lesser General   ////
1282
//// Public License as published by the Free Software Foundation; ////
1283
//// either version 2.1 of the License, or (at your option) any   ////
1284
//// later version.                                               ////
1285
////                                                              ////
1286
//// This source is distributed in the hope that it will be       ////
1287
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1288
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1289
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1290
//// details.                                                     ////
1291
////                                                              ////
1292
//// You should have received a copy of the GNU Lesser General    ////
1293
//// Public License along with this source; if not, download it   ////
1294
//// from http://www.opencores.org/lgpl.shtml                     ////
1295
////                                                              ////
1296
//////////////////////////////////////////////////////////////////////
1297
 
1298
// binary counter
1299
module vl_cnt_bin_ce_rew_q_zq_l1 ( cke, rew, q, zq, level1, rst, clk);
1300
 
1301
   parameter length = 4;
1302
   input cke;
1303
   input rew;
1304
   output [length:1] q;
1305
   output reg zq;
1306
   output reg level1;
1307
   input rst;
1308
   input clk;
1309
 
1310
   parameter clear_value = 0;
1311
   parameter set_value = 1;
1312
   parameter wrap_value = 1;
1313
   parameter level1_value = 15;
1314
 
1315
   reg  [length:1] qi;
1316
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1317
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1318
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1319
   assign q_next = rew ? q_next_rew : q_next_fw;
1320
 
1321
   always @ (posedge clk or posedge rst)
1322
     if (rst)
1323
       qi <= {length{1'b0}};
1324
     else
1325
     if (cke)
1326
       qi <= q_next;
1327
 
1328
   assign q = qi;
1329
 
1330
 
1331
   always @ (posedge clk or posedge rst)
1332
     if (rst)
1333
       zq <= 1'b1;
1334
     else
1335
     if (cke)
1336
       zq <= q_next == {length{1'b0}};
1337
 
1338
    always @ (posedge clk or posedge rst)
1339
    if (rst)
1340
        level1 <= 1'b0;
1341
    else
1342
    if (cke)
1343
    if (q_next == level1_value)
1344
        level1 <= 1'b1;
1345
    else if (qi == level1_value & rew)
1346
        level1 <= 1'b0;
1347
endmodule
1348
//////////////////////////////////////////////////////////////////////
1349
////                                                              ////
1350
////  Versatile counter                                           ////
1351
////                                                              ////
1352
////  Description                                                 ////
1353
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1354
////  counter                                                     ////
1355
////                                                              ////
1356
////  To Do:                                                      ////
1357
////   - add LFSR with more taps                                  ////
1358
////                                                              ////
1359
////  Author(s):                                                  ////
1360
////      - Michael Unneback, unneback@opencores.org              ////
1361
////        ORSoC AB                                              ////
1362
////                                                              ////
1363
//////////////////////////////////////////////////////////////////////
1364
////                                                              ////
1365
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1366
////                                                              ////
1367
//// This source file may be used and distributed without         ////
1368
//// restriction provided that this copyright statement is not    ////
1369
//// removed from the file and that any derivative work contains  ////
1370
//// the original copyright notice and the associated disclaimer. ////
1371
////                                                              ////
1372
//// This source file is free software; you can redistribute it   ////
1373
//// and/or modify it under the terms of the GNU Lesser General   ////
1374
//// Public License as published by the Free Software Foundation; ////
1375
//// either version 2.1 of the License, or (at your option) any   ////
1376
//// later version.                                               ////
1377
////                                                              ////
1378
//// This source is distributed in the hope that it will be       ////
1379
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1380
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1381
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1382
//// details.                                                     ////
1383
////                                                              ////
1384
//// You should have received a copy of the GNU Lesser General    ////
1385
//// Public License along with this source; if not, download it   ////
1386
//// from http://www.opencores.org/lgpl.shtml                     ////
1387
////                                                              ////
1388
//////////////////////////////////////////////////////////////////////
1389
 
1390 6 unneback
// LFSR counter
1391 18 unneback
module vl_cnt_lfsr_zq ( zq, rst, clk);
1392 6 unneback
 
1393
   parameter length = 4;
1394
   output reg zq;
1395
   input rst;
1396
   input clk;
1397
 
1398
   parameter clear_value = 0;
1399
   parameter set_value = 1;
1400
   parameter wrap_value = 8;
1401
   parameter level1_value = 15;
1402
 
1403
   reg  [length:1] qi;
1404
   reg lfsr_fb;
1405
   wire [length:1] q_next;
1406
   reg [32:1] polynom;
1407
   integer i;
1408
 
1409
   always @ (qi)
1410
   begin
1411
        case (length)
1412
         2: polynom = 32'b11;                               // 0x3
1413
         3: polynom = 32'b110;                              // 0x6
1414
         4: polynom = 32'b1100;                             // 0xC
1415
         5: polynom = 32'b10100;                            // 0x14
1416
         6: polynom = 32'b110000;                           // 0x30
1417
         7: polynom = 32'b1100000;                          // 0x60
1418
         8: polynom = 32'b10111000;                         // 0xb8
1419
         9: polynom = 32'b100010000;                        // 0x110
1420
        10: polynom = 32'b1001000000;                       // 0x240
1421
        11: polynom = 32'b10100000000;                      // 0x500
1422
        12: polynom = 32'b100000101001;                     // 0x829
1423
        13: polynom = 32'b1000000001100;                    // 0x100C
1424
        14: polynom = 32'b10000000010101;                   // 0x2015
1425
        15: polynom = 32'b110000000000000;                  // 0x6000
1426
        16: polynom = 32'b1101000000001000;                 // 0xD008
1427
        17: polynom = 32'b10010000000000000;                // 0x12000
1428
        18: polynom = 32'b100000010000000000;               // 0x20400
1429
        19: polynom = 32'b1000000000000100011;              // 0x40023
1430
        20: polynom = 32'b10000010000000000000;             // 0x82000
1431
        21: polynom = 32'b101000000000000000000;            // 0x140000
1432
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1433
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1434
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1435
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1436
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1437
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1438
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1439
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1440
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1441
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1442
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1443
        default: polynom = 32'b0;
1444
        endcase
1445
        lfsr_fb = qi[length];
1446
        for (i=length-1; i>=1; i=i-1) begin
1447
            if (polynom[i])
1448
                lfsr_fb = lfsr_fb  ~^ qi[i];
1449
        end
1450
    end
1451
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1452
 
1453
   always @ (posedge clk or posedge rst)
1454
     if (rst)
1455
       qi <= {length{1'b0}};
1456
     else
1457
       qi <= q_next;
1458
 
1459
 
1460
 
1461
   always @ (posedge clk or posedge rst)
1462
     if (rst)
1463
       zq <= 1'b1;
1464
     else
1465
       zq <= q_next == {length{1'b0}};
1466
endmodule
1467
//////////////////////////////////////////////////////////////////////
1468
////                                                              ////
1469
////  Versatile counter                                           ////
1470
////                                                              ////
1471
////  Description                                                 ////
1472
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1473
////  counter                                                     ////
1474
////                                                              ////
1475
////  To Do:                                                      ////
1476
////   - add LFSR with more taps                                  ////
1477
////                                                              ////
1478
////  Author(s):                                                  ////
1479
////      - Michael Unneback, unneback@opencores.org              ////
1480
////        ORSoC AB                                              ////
1481
////                                                              ////
1482
//////////////////////////////////////////////////////////////////////
1483
////                                                              ////
1484
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1485
////                                                              ////
1486
//// This source file may be used and distributed without         ////
1487
//// restriction provided that this copyright statement is not    ////
1488
//// removed from the file and that any derivative work contains  ////
1489
//// the original copyright notice and the associated disclaimer. ////
1490
////                                                              ////
1491
//// This source file is free software; you can redistribute it   ////
1492
//// and/or modify it under the terms of the GNU Lesser General   ////
1493
//// Public License as published by the Free Software Foundation; ////
1494
//// either version 2.1 of the License, or (at your option) any   ////
1495
//// later version.                                               ////
1496
////                                                              ////
1497
//// This source is distributed in the hope that it will be       ////
1498
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1499
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1500
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1501
//// details.                                                     ////
1502
////                                                              ////
1503
//// You should have received a copy of the GNU Lesser General    ////
1504
//// Public License along with this source; if not, download it   ////
1505
//// from http://www.opencores.org/lgpl.shtml                     ////
1506
////                                                              ////
1507
//////////////////////////////////////////////////////////////////////
1508
 
1509
// LFSR counter
1510 18 unneback
module vl_cnt_lfsr_ce_zq ( cke, zq, rst, clk);
1511 6 unneback
 
1512
   parameter length = 4;
1513
   input cke;
1514
   output reg zq;
1515
   input rst;
1516
   input clk;
1517
 
1518
   parameter clear_value = 0;
1519
   parameter set_value = 1;
1520
   parameter wrap_value = 8;
1521
   parameter level1_value = 15;
1522
 
1523
   reg  [length:1] qi;
1524
   reg lfsr_fb;
1525
   wire [length:1] q_next;
1526
   reg [32:1] polynom;
1527
   integer i;
1528
 
1529
   always @ (qi)
1530
   begin
1531
        case (length)
1532
         2: polynom = 32'b11;                               // 0x3
1533
         3: polynom = 32'b110;                              // 0x6
1534
         4: polynom = 32'b1100;                             // 0xC
1535
         5: polynom = 32'b10100;                            // 0x14
1536
         6: polynom = 32'b110000;                           // 0x30
1537
         7: polynom = 32'b1100000;                          // 0x60
1538
         8: polynom = 32'b10111000;                         // 0xb8
1539
         9: polynom = 32'b100010000;                        // 0x110
1540
        10: polynom = 32'b1001000000;                       // 0x240
1541
        11: polynom = 32'b10100000000;                      // 0x500
1542
        12: polynom = 32'b100000101001;                     // 0x829
1543
        13: polynom = 32'b1000000001100;                    // 0x100C
1544
        14: polynom = 32'b10000000010101;                   // 0x2015
1545
        15: polynom = 32'b110000000000000;                  // 0x6000
1546
        16: polynom = 32'b1101000000001000;                 // 0xD008
1547
        17: polynom = 32'b10010000000000000;                // 0x12000
1548
        18: polynom = 32'b100000010000000000;               // 0x20400
1549
        19: polynom = 32'b1000000000000100011;              // 0x40023
1550
        20: polynom = 32'b10000010000000000000;             // 0x82000
1551
        21: polynom = 32'b101000000000000000000;            // 0x140000
1552
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1553
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1554
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1555
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1556
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1557
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1558
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1559
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1560
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1561
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1562
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1563
        default: polynom = 32'b0;
1564
        endcase
1565
        lfsr_fb = qi[length];
1566
        for (i=length-1; i>=1; i=i-1) begin
1567
            if (polynom[i])
1568
                lfsr_fb = lfsr_fb  ~^ qi[i];
1569
        end
1570
    end
1571
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1572
 
1573
   always @ (posedge clk or posedge rst)
1574
     if (rst)
1575
       qi <= {length{1'b0}};
1576
     else
1577
     if (cke)
1578
       qi <= q_next;
1579
 
1580
 
1581
 
1582
   always @ (posedge clk or posedge rst)
1583
     if (rst)
1584
       zq <= 1'b1;
1585
     else
1586
     if (cke)
1587
       zq <= q_next == {length{1'b0}};
1588
endmodule
1589
//////////////////////////////////////////////////////////////////////
1590
////                                                              ////
1591
////  Versatile counter                                           ////
1592
////                                                              ////
1593
////  Description                                                 ////
1594
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1595
////  counter                                                     ////
1596
////                                                              ////
1597
////  To Do:                                                      ////
1598
////   - add LFSR with more taps                                  ////
1599
////                                                              ////
1600
////  Author(s):                                                  ////
1601
////      - Michael Unneback, unneback@opencores.org              ////
1602
////        ORSoC AB                                              ////
1603
////                                                              ////
1604
//////////////////////////////////////////////////////////////////////
1605
////                                                              ////
1606
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1607
////                                                              ////
1608
//// This source file may be used and distributed without         ////
1609
//// restriction provided that this copyright statement is not    ////
1610
//// removed from the file and that any derivative work contains  ////
1611
//// the original copyright notice and the associated disclaimer. ////
1612
////                                                              ////
1613
//// This source file is free software; you can redistribute it   ////
1614
//// and/or modify it under the terms of the GNU Lesser General   ////
1615
//// Public License as published by the Free Software Foundation; ////
1616
//// either version 2.1 of the License, or (at your option) any   ////
1617
//// later version.                                               ////
1618
////                                                              ////
1619
//// This source is distributed in the hope that it will be       ////
1620
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1621
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1622
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1623
//// details.                                                     ////
1624
////                                                              ////
1625
//// You should have received a copy of the GNU Lesser General    ////
1626
//// Public License along with this source; if not, download it   ////
1627
//// from http://www.opencores.org/lgpl.shtml                     ////
1628
////                                                              ////
1629
//////////////////////////////////////////////////////////////////////
1630 22 unneback
 
1631
// LFSR counter
1632
module vl_cnt_lfsr_ce_q_zq ( cke, q, zq, rst, clk);
1633
 
1634
   parameter length = 4;
1635
   input cke;
1636
   output [length:1] q;
1637
   output reg zq;
1638
   input rst;
1639
   input clk;
1640
 
1641
   parameter clear_value = 0;
1642
   parameter set_value = 1;
1643
   parameter wrap_value = 8;
1644
   parameter level1_value = 15;
1645
 
1646
   reg  [length:1] qi;
1647
   reg lfsr_fb;
1648
   wire [length:1] q_next;
1649
   reg [32:1] polynom;
1650
   integer i;
1651
 
1652
   always @ (qi)
1653
   begin
1654
        case (length)
1655
         2: polynom = 32'b11;                               // 0x3
1656
         3: polynom = 32'b110;                              // 0x6
1657
         4: polynom = 32'b1100;                             // 0xC
1658
         5: polynom = 32'b10100;                            // 0x14
1659
         6: polynom = 32'b110000;                           // 0x30
1660
         7: polynom = 32'b1100000;                          // 0x60
1661
         8: polynom = 32'b10111000;                         // 0xb8
1662
         9: polynom = 32'b100010000;                        // 0x110
1663
        10: polynom = 32'b1001000000;                       // 0x240
1664
        11: polynom = 32'b10100000000;                      // 0x500
1665
        12: polynom = 32'b100000101001;                     // 0x829
1666
        13: polynom = 32'b1000000001100;                    // 0x100C
1667
        14: polynom = 32'b10000000010101;                   // 0x2015
1668
        15: polynom = 32'b110000000000000;                  // 0x6000
1669
        16: polynom = 32'b1101000000001000;                 // 0xD008
1670
        17: polynom = 32'b10010000000000000;                // 0x12000
1671
        18: polynom = 32'b100000010000000000;               // 0x20400
1672
        19: polynom = 32'b1000000000000100011;              // 0x40023
1673
        20: polynom = 32'b10000010000000000000;             // 0x82000
1674
        21: polynom = 32'b101000000000000000000;            // 0x140000
1675
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1676
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1677
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1678
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1679
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1680
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1681
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1682
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1683
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1684
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1685
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1686
        default: polynom = 32'b0;
1687
        endcase
1688
        lfsr_fb = qi[length];
1689
        for (i=length-1; i>=1; i=i-1) begin
1690
            if (polynom[i])
1691
                lfsr_fb = lfsr_fb  ~^ qi[i];
1692
        end
1693
    end
1694
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1695
 
1696
   always @ (posedge clk or posedge rst)
1697
     if (rst)
1698
       qi <= {length{1'b0}};
1699
     else
1700
     if (cke)
1701
       qi <= q_next;
1702
 
1703
   assign q = qi;
1704
 
1705
 
1706
   always @ (posedge clk or posedge rst)
1707
     if (rst)
1708
       zq <= 1'b1;
1709
     else
1710
     if (cke)
1711
       zq <= q_next == {length{1'b0}};
1712
endmodule
1713
//////////////////////////////////////////////////////////////////////
1714
////                                                              ////
1715
////  Versatile counter                                           ////
1716
////                                                              ////
1717
////  Description                                                 ////
1718
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1719
////  counter                                                     ////
1720
////                                                              ////
1721
////  To Do:                                                      ////
1722
////   - add LFSR with more taps                                  ////
1723
////                                                              ////
1724
////  Author(s):                                                  ////
1725
////      - Michael Unneback, unneback@opencores.org              ////
1726
////        ORSoC AB                                              ////
1727
////                                                              ////
1728
//////////////////////////////////////////////////////////////////////
1729
////                                                              ////
1730
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1731
////                                                              ////
1732
//// This source file may be used and distributed without         ////
1733
//// restriction provided that this copyright statement is not    ////
1734
//// removed from the file and that any derivative work contains  ////
1735
//// the original copyright notice and the associated disclaimer. ////
1736
////                                                              ////
1737
//// This source file is free software; you can redistribute it   ////
1738
//// and/or modify it under the terms of the GNU Lesser General   ////
1739
//// Public License as published by the Free Software Foundation; ////
1740
//// either version 2.1 of the License, or (at your option) any   ////
1741
//// later version.                                               ////
1742
////                                                              ////
1743
//// This source is distributed in the hope that it will be       ////
1744
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1745
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1746
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1747
//// details.                                                     ////
1748
////                                                              ////
1749
//// You should have received a copy of the GNU Lesser General    ////
1750
//// Public License along with this source; if not, download it   ////
1751
//// from http://www.opencores.org/lgpl.shtml                     ////
1752
////                                                              ////
1753
//////////////////////////////////////////////////////////////////////
1754 6 unneback
 
1755
// LFSR counter
1756 18 unneback
module vl_cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk);
1757 6 unneback
 
1758
   parameter length = 4;
1759
   input cke;
1760
   input rew;
1761
   output reg level1;
1762
   input rst;
1763
   input clk;
1764
 
1765
   parameter clear_value = 0;
1766
   parameter set_value = 1;
1767
   parameter wrap_value = 8;
1768
   parameter level1_value = 15;
1769
 
1770
   reg  [length:1] qi;
1771
   reg lfsr_fb, lfsr_fb_rew;
1772
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1773
   reg [32:1] polynom_rew;
1774
   integer j;
1775
   reg [32:1] polynom;
1776
   integer i;
1777
 
1778
   always @ (qi)
1779
   begin
1780
        case (length)
1781
         2: polynom = 32'b11;                               // 0x3
1782
         3: polynom = 32'b110;                              // 0x6
1783
         4: polynom = 32'b1100;                             // 0xC
1784
         5: polynom = 32'b10100;                            // 0x14
1785
         6: polynom = 32'b110000;                           // 0x30
1786
         7: polynom = 32'b1100000;                          // 0x60
1787
         8: polynom = 32'b10111000;                         // 0xb8
1788
         9: polynom = 32'b100010000;                        // 0x110
1789
        10: polynom = 32'b1001000000;                       // 0x240
1790
        11: polynom = 32'b10100000000;                      // 0x500
1791
        12: polynom = 32'b100000101001;                     // 0x829
1792
        13: polynom = 32'b1000000001100;                    // 0x100C
1793
        14: polynom = 32'b10000000010101;                   // 0x2015
1794
        15: polynom = 32'b110000000000000;                  // 0x6000
1795
        16: polynom = 32'b1101000000001000;                 // 0xD008
1796
        17: polynom = 32'b10010000000000000;                // 0x12000
1797
        18: polynom = 32'b100000010000000000;               // 0x20400
1798
        19: polynom = 32'b1000000000000100011;              // 0x40023
1799
        20: polynom = 32'b10000010000000000000;             // 0x82000
1800
        21: polynom = 32'b101000000000000000000;            // 0x140000
1801
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1802
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1803
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1804
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1805
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1806
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1807
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1808
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1809
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1810
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1811
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1812
        default: polynom = 32'b0;
1813
        endcase
1814
        lfsr_fb = qi[length];
1815
        for (i=length-1; i>=1; i=i-1) begin
1816
            if (polynom[i])
1817
                lfsr_fb = lfsr_fb  ~^ qi[i];
1818
        end
1819
    end
1820
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1821
   always @ (qi)
1822
   begin
1823
        case (length)
1824
         2: polynom_rew = 32'b11;
1825
         3: polynom_rew = 32'b110;
1826
         4: polynom_rew = 32'b1100;
1827
         5: polynom_rew = 32'b10100;
1828
         6: polynom_rew = 32'b110000;
1829
         7: polynom_rew = 32'b1100000;
1830
         8: polynom_rew = 32'b10111000;
1831
         9: polynom_rew = 32'b100010000;
1832
        10: polynom_rew = 32'b1001000000;
1833
        11: polynom_rew = 32'b10100000000;
1834
        12: polynom_rew = 32'b100000101001;
1835
        13: polynom_rew = 32'b1000000001100;
1836
        14: polynom_rew = 32'b10000000010101;
1837
        15: polynom_rew = 32'b110000000000000;
1838
        16: polynom_rew = 32'b1101000000001000;
1839
        17: polynom_rew = 32'b10010000000000000;
1840
        18: polynom_rew = 32'b100000010000000000;
1841
        19: polynom_rew = 32'b1000000000000100011;
1842
        20: polynom_rew = 32'b10000010000000000000;
1843
        21: polynom_rew = 32'b101000000000000000000;
1844
        22: polynom_rew = 32'b1100000000000000000000;
1845
        23: polynom_rew = 32'b10000100000000000000000;
1846
        24: polynom_rew = 32'b111000010000000000000000;
1847
        25: polynom_rew = 32'b1001000000000000000000000;
1848
        26: polynom_rew = 32'b10000000000000000000100011;
1849
        27: polynom_rew = 32'b100000000000000000000010011;
1850
        28: polynom_rew = 32'b1100100000000000000000000000;
1851
        29: polynom_rew = 32'b10100000000000000000000000000;
1852
        30: polynom_rew = 32'b100000000000000000000000101001;
1853
        31: polynom_rew = 32'b1001000000000000000000000000000;
1854
        32: polynom_rew = 32'b10000000001000000000000000000011;
1855
        default: polynom_rew = 32'b0;
1856
        endcase
1857
        // rotate left
1858
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
1859
        lfsr_fb_rew = qi[length];
1860
        for (i=length-1; i>=1; i=i-1) begin
1861
            if (polynom_rew[i])
1862
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
1863
        end
1864
    end
1865
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
1866
   assign q_next = rew ? q_next_rew : q_next_fw;
1867
 
1868
   always @ (posedge clk or posedge rst)
1869
     if (rst)
1870
       qi <= {length{1'b0}};
1871
     else
1872
     if (cke)
1873
       qi <= q_next;
1874
 
1875
 
1876
 
1877
    always @ (posedge clk or posedge rst)
1878
    if (rst)
1879
        level1 <= 1'b0;
1880
    else
1881
    if (cke)
1882
    if (q_next == level1_value)
1883
        level1 <= 1'b1;
1884
    else if (qi == level1_value & rew)
1885
        level1 <= 1'b0;
1886
endmodule
1887
//////////////////////////////////////////////////////////////////////
1888
////                                                              ////
1889
////  Versatile counter                                           ////
1890
////                                                              ////
1891
////  Description                                                 ////
1892
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1893
////  counter                                                     ////
1894
////                                                              ////
1895
////  To Do:                                                      ////
1896
////   - add LFSR with more taps                                  ////
1897
////                                                              ////
1898
////  Author(s):                                                  ////
1899
////      - Michael Unneback, unneback@opencores.org              ////
1900
////        ORSoC AB                                              ////
1901
////                                                              ////
1902
//////////////////////////////////////////////////////////////////////
1903
////                                                              ////
1904
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1905
////                                                              ////
1906
//// This source file may be used and distributed without         ////
1907
//// restriction provided that this copyright statement is not    ////
1908
//// removed from the file and that any derivative work contains  ////
1909
//// the original copyright notice and the associated disclaimer. ////
1910
////                                                              ////
1911
//// This source file is free software; you can redistribute it   ////
1912
//// and/or modify it under the terms of the GNU Lesser General   ////
1913
//// Public License as published by the Free Software Foundation; ////
1914
//// either version 2.1 of the License, or (at your option) any   ////
1915
//// later version.                                               ////
1916
////                                                              ////
1917
//// This source is distributed in the hope that it will be       ////
1918
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1919
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1920
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1921
//// details.                                                     ////
1922
////                                                              ////
1923
//// You should have received a copy of the GNU Lesser General    ////
1924
//// Public License along with this source; if not, download it   ////
1925
//// from http://www.opencores.org/lgpl.shtml                     ////
1926
////                                                              ////
1927
//////////////////////////////////////////////////////////////////////
1928
 
1929
// GRAY counter
1930 18 unneback
module vl_cnt_gray ( q, rst, clk);
1931 6 unneback
 
1932
   parameter length = 4;
1933
   output reg [length:1] q;
1934
   input rst;
1935
   input clk;
1936
 
1937
   parameter clear_value = 0;
1938
   parameter set_value = 1;
1939
   parameter wrap_value = 8;
1940
   parameter level1_value = 15;
1941
 
1942
   reg  [length:1] qi;
1943
   wire [length:1] q_next;
1944
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1945
 
1946
   always @ (posedge clk or posedge rst)
1947
     if (rst)
1948
       qi <= {length{1'b0}};
1949
     else
1950
       qi <= q_next;
1951
 
1952
   always @ (posedge clk or posedge rst)
1953
     if (rst)
1954
       q <= {length{1'b0}};
1955
     else
1956
         q <= (q_next>>1) ^ q_next;
1957
 
1958
endmodule
1959
//////////////////////////////////////////////////////////////////////
1960
////                                                              ////
1961
////  Versatile counter                                           ////
1962
////                                                              ////
1963
////  Description                                                 ////
1964
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1965
////  counter                                                     ////
1966
////                                                              ////
1967
////  To Do:                                                      ////
1968
////   - add LFSR with more taps                                  ////
1969
////                                                              ////
1970
////  Author(s):                                                  ////
1971
////      - Michael Unneback, unneback@opencores.org              ////
1972
////        ORSoC AB                                              ////
1973
////                                                              ////
1974
//////////////////////////////////////////////////////////////////////
1975
////                                                              ////
1976
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1977
////                                                              ////
1978
//// This source file may be used and distributed without         ////
1979
//// restriction provided that this copyright statement is not    ////
1980
//// removed from the file and that any derivative work contains  ////
1981
//// the original copyright notice and the associated disclaimer. ////
1982
////                                                              ////
1983
//// This source file is free software; you can redistribute it   ////
1984
//// and/or modify it under the terms of the GNU Lesser General   ////
1985
//// Public License as published by the Free Software Foundation; ////
1986
//// either version 2.1 of the License, or (at your option) any   ////
1987
//// later version.                                               ////
1988
////                                                              ////
1989
//// This source is distributed in the hope that it will be       ////
1990
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1991
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1992
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1993
//// details.                                                     ////
1994
////                                                              ////
1995
//// You should have received a copy of the GNU Lesser General    ////
1996
//// Public License along with this source; if not, download it   ////
1997
//// from http://www.opencores.org/lgpl.shtml                     ////
1998
////                                                              ////
1999
//////////////////////////////////////////////////////////////////////
2000
 
2001
// GRAY counter
2002 18 unneback
module vl_cnt_gray_ce ( cke, q, rst, clk);
2003 6 unneback
 
2004
   parameter length = 4;
2005
   input cke;
2006
   output reg [length:1] q;
2007
   input rst;
2008
   input clk;
2009
 
2010
   parameter clear_value = 0;
2011
   parameter set_value = 1;
2012
   parameter wrap_value = 8;
2013
   parameter level1_value = 15;
2014
 
2015
   reg  [length:1] qi;
2016
   wire [length:1] q_next;
2017
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2018
 
2019
   always @ (posedge clk or posedge rst)
2020
     if (rst)
2021
       qi <= {length{1'b0}};
2022
     else
2023
     if (cke)
2024
       qi <= q_next;
2025
 
2026
   always @ (posedge clk or posedge rst)
2027
     if (rst)
2028
       q <= {length{1'b0}};
2029
     else
2030
       if (cke)
2031
         q <= (q_next>>1) ^ q_next;
2032
 
2033
endmodule
2034
//////////////////////////////////////////////////////////////////////
2035
////                                                              ////
2036
////  Versatile counter                                           ////
2037
////                                                              ////
2038
////  Description                                                 ////
2039
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2040
////  counter                                                     ////
2041
////                                                              ////
2042
////  To Do:                                                      ////
2043
////   - add LFSR with more taps                                  ////
2044
////                                                              ////
2045
////  Author(s):                                                  ////
2046
////      - Michael Unneback, unneback@opencores.org              ////
2047
////        ORSoC AB                                              ////
2048
////                                                              ////
2049
//////////////////////////////////////////////////////////////////////
2050
////                                                              ////
2051
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2052
////                                                              ////
2053
//// This source file may be used and distributed without         ////
2054
//// restriction provided that this copyright statement is not    ////
2055
//// removed from the file and that any derivative work contains  ////
2056
//// the original copyright notice and the associated disclaimer. ////
2057
////                                                              ////
2058
//// This source file is free software; you can redistribute it   ////
2059
//// and/or modify it under the terms of the GNU Lesser General   ////
2060
//// Public License as published by the Free Software Foundation; ////
2061
//// either version 2.1 of the License, or (at your option) any   ////
2062
//// later version.                                               ////
2063
////                                                              ////
2064
//// This source is distributed in the hope that it will be       ////
2065
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2066
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2067
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2068
//// details.                                                     ////
2069
////                                                              ////
2070
//// You should have received a copy of the GNU Lesser General    ////
2071
//// Public License along with this source; if not, download it   ////
2072
//// from http://www.opencores.org/lgpl.shtml                     ////
2073
////                                                              ////
2074
//////////////////////////////////////////////////////////////////////
2075
 
2076
// GRAY counter
2077 18 unneback
module vl_cnt_gray_ce_bin ( cke, q, q_bin, rst, clk);
2078 6 unneback
 
2079
   parameter length = 4;
2080
   input cke;
2081
   output reg [length:1] q;
2082
   output [length:1] q_bin;
2083
   input rst;
2084
   input clk;
2085
 
2086
   parameter clear_value = 0;
2087
   parameter set_value = 1;
2088
   parameter wrap_value = 8;
2089
   parameter level1_value = 15;
2090
 
2091
   reg  [length:1] qi;
2092
   wire [length:1] q_next;
2093
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2094
 
2095
   always @ (posedge clk or posedge rst)
2096
     if (rst)
2097
       qi <= {length{1'b0}};
2098
     else
2099
     if (cke)
2100
       qi <= q_next;
2101
 
2102
   always @ (posedge clk or posedge rst)
2103
     if (rst)
2104
       q <= {length{1'b0}};
2105
     else
2106
       if (cke)
2107
         q <= (q_next>>1) ^ q_next;
2108
 
2109
   assign q_bin = qi;
2110
 
2111
endmodule
2112
//////////////////////////////////////////////////////////////////////
2113
////                                                              ////
2114
////  Versatile library, counters                                 ////
2115
////                                                              ////
2116
////  Description                                                 ////
2117
////  counters                                                    ////
2118
////                                                              ////
2119
////                                                              ////
2120
////  To Do:                                                      ////
2121
////   - add more counters                                        ////
2122
////                                                              ////
2123
////  Author(s):                                                  ////
2124
////      - Michael Unneback, unneback@opencores.org              ////
2125
////        ORSoC AB                                              ////
2126
////                                                              ////
2127
//////////////////////////////////////////////////////////////////////
2128
////                                                              ////
2129
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2130
////                                                              ////
2131
//// This source file may be used and distributed without         ////
2132
//// restriction provided that this copyright statement is not    ////
2133
//// removed from the file and that any derivative work contains  ////
2134
//// the original copyright notice and the associated disclaimer. ////
2135
////                                                              ////
2136
//// This source file is free software; you can redistribute it   ////
2137
//// and/or modify it under the terms of the GNU Lesser General   ////
2138
//// Public License as published by the Free Software Foundation; ////
2139
//// either version 2.1 of the License, or (at your option) any   ////
2140
//// later version.                                               ////
2141
////                                                              ////
2142
//// This source is distributed in the hope that it will be       ////
2143
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2144
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2145
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2146
//// details.                                                     ////
2147
////                                                              ////
2148
//// You should have received a copy of the GNU Lesser General    ////
2149
//// Public License along with this source; if not, download it   ////
2150
//// from http://www.opencores.org/lgpl.shtml                     ////
2151
////                                                              ////
2152
//////////////////////////////////////////////////////////////////////
2153
 
2154 18 unneback
module vl_cnt_shreg_wrap ( q, rst, clk);
2155 6 unneback
 
2156
   parameter length = 4;
2157
   output reg [0:length-1] q;
2158
   input rst;
2159
   input clk;
2160
 
2161
    always @ (posedge clk or posedge rst)
2162
    if (rst)
2163
        q <= {1'b1,{length-1{1'b0}}};
2164
    else
2165
        q <= {q[length-1],q[0:length-2]};
2166
 
2167
endmodule
2168
 
2169 18 unneback
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
2170 6 unneback
 
2171
   parameter length = 4;
2172
   input cke;
2173
   output reg [0:length-1] q;
2174
   input rst;
2175
   input clk;
2176
 
2177
    always @ (posedge clk or posedge rst)
2178
    if (rst)
2179
        q <= {1'b1,{length-1{1'b0}}};
2180
    else
2181
        if (cke)
2182
            q <= {q[length-1],q[0:length-2]};
2183
 
2184
endmodule
2185
 
2186 18 unneback
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
2187 6 unneback
 
2188
   parameter length = 4;
2189
   input cke, clear;
2190
   output reg [0:length-1] q;
2191
   input rst;
2192
   input clk;
2193
 
2194
    always @ (posedge clk or posedge rst)
2195
    if (rst)
2196
        q <= {1'b1,{length-1{1'b0}}};
2197
    else
2198
        if (cke)
2199
            if (clear)
2200
                q <= {1'b1,{length-1{1'b0}}};
2201
            else
2202
                q <= q >> 1;
2203
 
2204
endmodule
2205
 
2206 18 unneback
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
2207 6 unneback
 
2208
   parameter length = 4;
2209
   input cke, clear;
2210
   output reg [0:length-1] q;
2211
   input rst;
2212
   input clk;
2213
 
2214
    always @ (posedge clk or posedge rst)
2215
    if (rst)
2216
        q <= {1'b1,{length-1{1'b0}}};
2217
    else
2218
        if (cke)
2219
            if (clear)
2220
                q <= {1'b1,{length-1{1'b0}}};
2221
            else
2222
            q <= {q[length-1],q[0:length-2]};
2223
 
2224
endmodule
2225
//////////////////////////////////////////////////////////////////////
2226
////                                                              ////
2227
////  Versatile library, memories                                 ////
2228
////                                                              ////
2229
////  Description                                                 ////
2230
////  memories                                                    ////
2231
////                                                              ////
2232
////                                                              ////
2233
////  To Do:                                                      ////
2234
////   - add more memory types                                    ////
2235
////                                                              ////
2236
////  Author(s):                                                  ////
2237
////      - Michael Unneback, unneback@opencores.org              ////
2238
////        ORSoC AB                                              ////
2239
////                                                              ////
2240
//////////////////////////////////////////////////////////////////////
2241
////                                                              ////
2242
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2243
////                                                              ////
2244
//// This source file may be used and distributed without         ////
2245
//// restriction provided that this copyright statement is not    ////
2246
//// removed from the file and that any derivative work contains  ////
2247
//// the original copyright notice and the associated disclaimer. ////
2248
////                                                              ////
2249
//// This source file is free software; you can redistribute it   ////
2250
//// and/or modify it under the terms of the GNU Lesser General   ////
2251
//// Public License as published by the Free Software Foundation; ////
2252
//// either version 2.1 of the License, or (at your option) any   ////
2253
//// later version.                                               ////
2254
////                                                              ////
2255
//// This source is distributed in the hope that it will be       ////
2256
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2257
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2258
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2259
//// details.                                                     ////
2260
////                                                              ////
2261
//// You should have received a copy of the GNU Lesser General    ////
2262
//// Public License along with this source; if not, download it   ////
2263
//// from http://www.opencores.org/lgpl.shtml                     ////
2264
////                                                              ////
2265
//////////////////////////////////////////////////////////////////////
2266
 
2267
/// ROM
2268
 
2269 7 unneback
module vl_rom_init ( adr, q, clk);
2270
   parameter data_width = 32;
2271
   parameter addr_width = 8;
2272
   input [(addr_width-1):0]       adr;
2273
   output reg [(data_width-1):0] q;
2274
   input                         clk;
2275
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
2276
   parameter memory_file = "vl_rom.vmem";
2277
   initial
2278
     begin
2279
        $readmemh(memory_file, rom);
2280
     end
2281
 
2282
   always @ (posedge clk)
2283
     q <= rom[adr];
2284 6 unneback
 
2285 7 unneback
endmodule
2286
 
2287 14 unneback
/*
2288 7 unneback
module vl_rom ( adr, q, clk);
2289
 
2290 6 unneback
parameter data_width = 32;
2291
parameter addr_width = 4;
2292
 
2293
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
2294
    {32'h18000000},
2295
    {32'hA8200000},
2296
    {32'hA8200000},
2297
    {32'hA8200000},
2298
    {32'h44003000},
2299
    {32'h15000000},
2300
    {32'h15000000},
2301
    {32'h15000000},
2302
    {32'h15000000},
2303
    {32'h15000000},
2304
    {32'h15000000},
2305
    {32'h15000000},
2306
    {32'h15000000},
2307
    {32'h15000000},
2308
    {32'h15000000},
2309
    {32'h15000000}};
2310
 
2311 7 unneback
input [addr_width-1:0] adr;
2312 6 unneback
output reg [data_width-1:0] q;
2313
input clk;
2314
 
2315
always @ (posedge clk)
2316 7 unneback
    q <= data[adr];
2317 6 unneback
 
2318
endmodule
2319 14 unneback
*/
2320 6 unneback
// Single port RAM
2321
 
2322
module vl_ram ( d, adr, we, q, clk);
2323
   parameter data_width = 32;
2324
   parameter addr_width = 8;
2325
   input [(data_width-1):0]      d;
2326
   input [(addr_width-1):0]       adr;
2327
   input                         we;
2328 7 unneback
   output reg [(data_width-1):0] q;
2329 6 unneback
   input                         clk;
2330
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
2331 7 unneback
   parameter init = 0;
2332
   parameter memory_file = "vl_ram.vmem";
2333
   generate if (init) begin : init_mem
2334
   initial
2335
     begin
2336
        $readmemh(memory_file, ram);
2337
     end
2338
   end
2339
   endgenerate
2340
 
2341 6 unneback
   always @ (posedge clk)
2342
   begin
2343
   if (we)
2344
     ram[adr] <= d;
2345
   q <= ram[adr];
2346
   end
2347
 
2348
endmodule
2349
 
2350 7 unneback
module vl_ram_be ( d, adr, be, we, q, clk);
2351
   parameter data_width = 32;
2352
   parameter addr_width = 8;
2353
   input [(data_width-1):0]      d;
2354
   input [(addr_width-1):0]       adr;
2355
   input [(addr_width/4)-1:0]    be;
2356
   input                         we;
2357
   output reg [(data_width-1):0] q;
2358
   input                         clk;
2359
 
2360
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
2361
 
2362
   parameter init = 0;
2363
   parameter memory_file = "vl_ram.vmem";
2364
   generate if (init) begin : init_mem
2365
   initial
2366
     begin
2367
        $readmemh(memory_file, ram);
2368
     end
2369
   end
2370
   endgenerate
2371
 
2372
   genvar i;
2373
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
2374
      always @ (posedge clk)
2375
      if (we & be[i])
2376
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
2377
   end
2378
   endgenerate
2379
 
2380
   always @ (posedge clk)
2381
      q <= ram[adr];
2382
 
2383
endmodule
2384
 
2385
 
2386 6 unneback
// Dual port RAM
2387
 
2388
// ACTEL FPGA should not use logic to handle rw collision
2389
`ifdef ACTEL
2390
        `define SYN /*synthesis syn_ramstyle = "no_rw_check"*/
2391
`else
2392
        `define SYN
2393
`endif
2394
 
2395 7 unneback
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
2396 6 unneback
   parameter data_width = 32;
2397
   parameter addr_width = 8;
2398
   input [(data_width-1):0]      d_a;
2399
   input [(addr_width-1):0]       adr_a;
2400
   input [(addr_width-1):0]       adr_b;
2401
   input                         we_a;
2402
   output [(data_width-1):0]      q_b;
2403
   input                         clk_a, clk_b;
2404
   reg [(addr_width-1):0]         adr_b_reg;
2405
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
2406 7 unneback
 
2407
   parameter init = 0;
2408
   parameter memory_file = "vl_ram.vmem";
2409
   generate if (init) begin : init_mem
2410
   initial
2411
     begin
2412
        $readmemh(memory_file, ram);
2413
     end
2414
   end
2415
   endgenerate
2416
 
2417 6 unneback
   always @ (posedge clk_a)
2418
   if (we_a)
2419
     ram[adr_a] <= d_a;
2420
   always @ (posedge clk_b)
2421
   adr_b_reg <= adr_b;
2422
   assign q_b = ram[adr_b_reg];
2423
endmodule
2424
 
2425 7 unneback
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
2426 6 unneback
   parameter data_width = 32;
2427
   parameter addr_width = 8;
2428
   input [(data_width-1):0]      d_a;
2429
   input [(addr_width-1):0]       adr_a;
2430
   input [(addr_width-1):0]       adr_b;
2431
   input                         we_a;
2432
   output [(data_width-1):0]      q_b;
2433
   output reg [(data_width-1):0] q_a;
2434
   input                         clk_a, clk_b;
2435
   reg [(data_width-1):0]         q_b;
2436
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
2437 7 unneback
 
2438
   parameter init = 0;
2439
   parameter memory_file = "vl_ram.vmem";
2440
   generate if (init) begin : init_mem
2441
   initial
2442
     begin
2443
        $readmemh(memory_file, ram);
2444
     end
2445
   end
2446
   endgenerate
2447
 
2448 6 unneback
   always @ (posedge clk_a)
2449
     begin
2450
        q_a <= ram[adr_a];
2451
        if (we_a)
2452
             ram[adr_a] <= d_a;
2453
     end
2454
   always @ (posedge clk_b)
2455
          q_b <= ram[adr_b];
2456
endmodule
2457
 
2458 7 unneback
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
2459 6 unneback
   parameter data_width = 32;
2460
   parameter addr_width = 8;
2461
   input [(data_width-1):0]      d_a;
2462
   input [(addr_width-1):0]       adr_a;
2463
   input [(addr_width-1):0]       adr_b;
2464
   input                         we_a;
2465
   output [(data_width-1):0]      q_b;
2466
   input [(data_width-1):0]       d_b;
2467
   output reg [(data_width-1):0] q_a;
2468
   input                         we_b;
2469
   input                         clk_a, clk_b;
2470
   reg [(data_width-1):0]         q_b;
2471
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
2472 7 unneback
 
2473
   parameter init = 0;
2474
   parameter memory_file = "vl_ram.vmem";
2475
   generate if (init) begin : init_mem
2476
   initial
2477
     begin
2478
        $readmemh(memory_file, ram);
2479
     end
2480
   end
2481
   endgenerate
2482
 
2483 6 unneback
   always @ (posedge clk_a)
2484
     begin
2485
        q_a <= ram[adr_a];
2486
        if (we_a)
2487
             ram[adr_a] <= d_a;
2488
     end
2489
   always @ (posedge clk_b)
2490
     begin
2491
        q_b <= ram[adr_b];
2492
        if (we_b)
2493
          ram[adr_b] <= d_b;
2494
     end
2495
endmodule
2496
 
2497
// Content addresable memory, CAM
2498
 
2499
// FIFO
2500 25 unneback
module vl_fifo_1r1w_fill_level_sync (
2501
    d, wr, fifo_full,
2502
    q, rd, fifo_empty,
2503
    fill_level,
2504
    clk, rst
2505
    );
2506
 
2507
parameter data_width = 18;
2508
parameter addr_width = 4;
2509 6 unneback
 
2510 25 unneback
// write side
2511
input  [data_width-1:0] d;
2512
input                   wr;
2513
output                  fifo_full;
2514
// read side
2515
output [data_width-1:0] q;
2516
input                   rd;
2517
output                  fifo_empty;
2518
// common
2519
output [addr_width:0]   fill_level;
2520
input rst, clk;
2521
 
2522
wire [addr_width:1] wadr, radr;
2523
 
2524
vl_cnt_bin_ce
2525
    # ( .length(addr_width))
2526
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
2527
 
2528
vl_cnt_bin_ce
2529
    # (.length(addr_width))
2530
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
2531
 
2532
vl_dpram_1r1w
2533
    # (.data_width(data_width), .addr_width(addr_width))
2534
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
2535
 
2536
vl_cnt_bin_ce_rew_zq_l1
2537
    # (.length(addr_width+1), .level1(1<<add_width))
2538
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
2539
 
2540
endmodule
2541
 
2542 6 unneback
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
2543
 
2544 11 unneback
   parameter addr_width = 4;
2545
   parameter N = addr_width-1;
2546 6 unneback
 
2547
   parameter Q1 = 2'b00;
2548
   parameter Q2 = 2'b01;
2549
   parameter Q3 = 2'b11;
2550
   parameter Q4 = 2'b10;
2551
 
2552
   parameter going_empty = 1'b0;
2553
   parameter going_full  = 1'b1;
2554
 
2555
   input [N:0]  wptr, rptr;
2556 14 unneback
   output       fifo_empty;
2557 6 unneback
   output       fifo_full;
2558
   input        wclk, rclk, rst;
2559
 
2560
`ifndef GENERATE_DIRECTION_AS_LATCH
2561
   wire direction;
2562
`endif
2563
`ifdef GENERATE_DIRECTION_AS_LATCH
2564
   reg direction;
2565
`endif
2566
   reg  direction_set, direction_clr;
2567
 
2568
   wire async_empty, async_full;
2569
   wire fifo_full2;
2570 14 unneback
   wire fifo_empty2;
2571 6 unneback
 
2572
   // direction_set
2573
   always @ (wptr[N:N-1] or rptr[N:N-1])
2574
     case ({wptr[N:N-1],rptr[N:N-1]})
2575
       {Q1,Q2} : direction_set <= 1'b1;
2576
       {Q2,Q3} : direction_set <= 1'b1;
2577
       {Q3,Q4} : direction_set <= 1'b1;
2578
       {Q4,Q1} : direction_set <= 1'b1;
2579
       default : direction_set <= 1'b0;
2580
     endcase
2581
 
2582
   // direction_clear
2583
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
2584
     if (rst)
2585
       direction_clr <= 1'b1;
2586
     else
2587
       case ({wptr[N:N-1],rptr[N:N-1]})
2588
         {Q2,Q1} : direction_clr <= 1'b1;
2589
         {Q3,Q2} : direction_clr <= 1'b1;
2590
         {Q4,Q3} : direction_clr <= 1'b1;
2591
         {Q1,Q4} : direction_clr <= 1'b1;
2592
         default : direction_clr <= 1'b0;
2593
       endcase
2594
 
2595
`ifndef GENERATE_DIRECTION_AS_LATCH
2596 18 unneback
    vl_dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
2597 6 unneback
`endif
2598
 
2599
`ifdef GENERATE_DIRECTION_AS_LATCH
2600
   always @ (posedge direction_set or posedge direction_clr)
2601
     if (direction_clr)
2602
       direction <= going_empty;
2603
     else
2604
       direction <= going_full;
2605
`endif
2606
 
2607
   assign async_empty = (wptr == rptr) && (direction==going_empty);
2608
   assign async_full  = (wptr == rptr) && (direction==going_full);
2609
 
2610 18 unneback
    vl_dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
2611
    vl_dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
2612 6 unneback
 
2613
/*
2614
   always @ (posedge wclk or posedge rst or posedge async_full)
2615
     if (rst)
2616
       {fifo_full, fifo_full2} <= 2'b00;
2617
     else if (async_full)
2618
       {fifo_full, fifo_full2} <= 2'b11;
2619
     else
2620
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
2621
*/
2622 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
2623 6 unneback
     if (async_empty)
2624
       {fifo_empty, fifo_empty2} <= 2'b11;
2625
     else
2626 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
2627 18 unneback
    vl_dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
2628
    vl_dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
2629 6 unneback
 
2630
endmodule // async_comp
2631
 
2632
module vl_fifo_1r1w_async (
2633
    d, wr, fifo_full, wr_clk, wr_rst,
2634
    q, rd, fifo_empty, rd_clk, rd_rst
2635
    );
2636
 
2637
parameter data_width = 18;
2638
parameter addr_width = 4;
2639
 
2640
// write side
2641
input  [data_width-1:0] d;
2642
input                   wr;
2643
output                  fifo_full;
2644
input                   wr_clk;
2645
input                   wr_rst;
2646
// read side
2647
output [data_width-1:0] q;
2648
input                   rd;
2649
output                  fifo_empty;
2650
input                   rd_clk;
2651
input                   rd_rst;
2652
 
2653
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
2654 23 unneback
 
2655 18 unneback
vl_cnt_gray_ce_bin
2656 6 unneback
    # ( .length(addr_width))
2657
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
2658
 
2659 18 unneback
vl_cnt_gray_ce_bin
2660 6 unneback
    # (.length(addr_width))
2661 23 unneback
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
2662 6 unneback
 
2663 7 unneback
vl_dpram_1r1w
2664 6 unneback
    # (.data_width(data_width), .addr_width(addr_width))
2665
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
2666
 
2667
vl_fifo_cmp_async
2668
    # (.addr_width(addr_width))
2669
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
2670
 
2671
endmodule
2672
 
2673 8 unneback
module vl_fifo_2r2w_async (
2674 6 unneback
    // a side
2675
    a_d, a_wr, a_fifo_full,
2676
    a_q, a_rd, a_fifo_empty,
2677
    a_clk, a_rst,
2678
    // b side
2679
    b_d, b_wr, b_fifo_full,
2680
    b_q, b_rd, b_fifo_empty,
2681
    b_clk, b_rst
2682
    );
2683
 
2684
parameter data_width = 18;
2685
parameter addr_width = 4;
2686
 
2687
// a side
2688
input  [data_width-1:0] a_d;
2689
input                   a_wr;
2690
output                  a_fifo_full;
2691
output [data_width-1:0] a_q;
2692
input                   a_rd;
2693
output                  a_fifo_empty;
2694
input                   a_clk;
2695
input                   a_rst;
2696
 
2697
// b side
2698
input  [data_width-1:0] b_d;
2699
input                   b_wr;
2700
output                  b_fifo_full;
2701
output [data_width-1:0] b_q;
2702
input                   b_rd;
2703
output                  b_fifo_empty;
2704
input                   b_clk;
2705
input                   b_rst;
2706
 
2707
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
2708
vl_fifo_1r1w_async_a (
2709
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
2710
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
2711
    );
2712
 
2713
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
2714
vl_fifo_1r1w_async_b (
2715
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
2716
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
2717
    );
2718
 
2719
endmodule
2720
 
2721 8 unneback
module vl_fifo_2r2w_async_simplex (
2722 6 unneback
    // a side
2723
    a_d, a_wr, a_fifo_full,
2724
    a_q, a_rd, a_fifo_empty,
2725
    a_clk, a_rst,
2726
    // b side
2727
    b_d, b_wr, b_fifo_full,
2728
    b_q, b_rd, b_fifo_empty,
2729
    b_clk, b_rst
2730
    );
2731
 
2732
parameter data_width = 18;
2733
parameter addr_width = 4;
2734
 
2735
// a side
2736
input  [data_width-1:0] a_d;
2737
input                   a_wr;
2738
output                  a_fifo_full;
2739
output [data_width-1:0] a_q;
2740
input                   a_rd;
2741
output                  a_fifo_empty;
2742
input                   a_clk;
2743
input                   a_rst;
2744
 
2745
// b side
2746
input  [data_width-1:0] b_d;
2747
input                   b_wr;
2748
output                  b_fifo_full;
2749
output [data_width-1:0] b_q;
2750
input                   b_rd;
2751
output                  b_fifo_empty;
2752
input                   b_clk;
2753
input                   b_rst;
2754
 
2755
// adr_gen
2756
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
2757
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
2758
// dpram
2759
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
2760
 
2761 18 unneback
vl_cnt_gray_ce_bin
2762 6 unneback
    # ( .length(addr_width))
2763
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
2764
 
2765 18 unneback
vl_cnt_gray_ce_bin
2766 6 unneback
    # (.length(addr_width))
2767
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
2768
 
2769 18 unneback
vl_cnt_gray_ce_bin
2770 6 unneback
    # ( .length(addr_width))
2771
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
2772
 
2773 18 unneback
vl_cnt_gray_ce_bin
2774 6 unneback
    # (.length(addr_width))
2775
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
2776
 
2777
// mux read or write adr to DPRAM
2778
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
2779
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
2780
 
2781 11 unneback
vl_dpram_2r2w
2782 6 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
2783
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
2784
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
2785
 
2786 11 unneback