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1 6 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  Versatile library, clock and reset                          ////
4
////                                                              ////
5
////  Description                                                 ////
6
////  Logic related to clock and reset                            ////
7
////                                                              ////
8
////                                                              ////
9
////  To Do:                                                      ////
10
////   - add more different registers                             ////
11
////                                                              ////
12
////  Author(s):                                                  ////
13
////      - Michael Unneback, unneback@opencores.org              ////
14
////        ORSoC AB                                              ////
15
////                                                              ////
16
//////////////////////////////////////////////////////////////////////
17
////                                                              ////
18
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
19
////                                                              ////
20
//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
36
////                                                              ////
37
//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
 
43
// Global buffer
44
// usage:
45
// use to enable global buffers for high fan out signals such as clock and reset
46
 
47
`ifdef ACTEL
48
 
49
`timescale 1 ns/100 ps
50
// Version: 8.4 8.4.0.33
51
module gbuf(GL,CLK);
52
output GL;
53
input  CLK;
54
 
55
    wire GND;
56
 
57
    GND GND_1_net(.Y(GND));
58
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
59
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
60
 
61
endmodule
62
`timescale 1 ns/1 ns
63
module vl_gbuf ( i, o);
64
input i;
65
output o;
66
`ifdef SIM_GBUF
67
assign o=i;
68
`else
69
gbuf gbuf_i0 ( .CLK(i), .GL(o));
70
`endif
71
endmodule
72
`else
73
`ifdef ALTERA
74 21 unneback
//altera
75 6 unneback
`else
76
 
77
`timescale 1 ns/100 ps
78
module vl_gbuf ( i, o);
79
input i;
80
output o;
81
assign o = i;
82
endmodule
83
`endif // ALTERA
84
`endif //ACTEL
85
 
86
// sync reset
87 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
88 6 unneback
// output active high global reset sync with two DFFs 
89
`timescale 1 ns/100 ps
90
module vl_sync_rst ( rst_n_i, rst_o, clk);
91
input rst_n_i, clk;
92
output rst_o;
93 18 unneback
reg [1:0] tmp;
94 6 unneback
always @ (posedge clk or negedge rst_n_i)
95
if (!rst_n_i)
96 17 unneback
        tmp <= 2'b11;
97 6 unneback
else
98 17 unneback
        tmp <= {1'b0,tmp[0]};
99
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
100 6 unneback
endmodule
101
 
102
// vl_pll
103
`ifdef ACTEL
104 17 unneback
`timescale 1 ps/1 ps
105 6 unneback
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
106
parameter index = 0;
107
parameter number_of_clk = 1;
108 17 unneback
parameter period_time_0 = 20000;
109
parameter period_time_1 = 20000;
110
parameter period_time_2 = 20000;
111
parameter lock_delay = 2000000;
112 6 unneback
input clk_i, rst_n_i;
113
output lock;
114
output reg [0:number_of_clk-1] clk_o;
115
output [0:number_of_clk-1] rst_o;
116
 
117
`ifdef SIM_PLL
118
 
119
always
120
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
121
 
122
generate if (number_of_clk > 1)
123
always
124
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
125
endgenerate
126
 
127
generate if (number_of_clk > 2)
128
always
129
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
130
endgenerate
131
 
132
genvar i;
133
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
134
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
135
end
136
endgenerate
137
 
138
assign #lock_delay lock = rst_n_i;
139
 
140
endmodule
141
`else
142
generate if (number_of_clk==1 & index==0) begin
143
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
144
end
145
endgenerate // index==0
146
generate if (number_of_clk==1 & index==1) begin
147
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
148
end
149
endgenerate // index==1
150
generate if (number_of_clk==1 & index==2) begin
151
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
152
end
153
endgenerate // index==2
154
generate if (number_of_clk==1 & index==3) begin
155
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
156
end
157
endgenerate // index==0
158
 
159
generate if (number_of_clk==2 & index==0) begin
160
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
161
end
162
endgenerate // index==0
163
generate if (number_of_clk==2 & index==1) begin
164
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
165
end
166
endgenerate // index==1
167
generate if (number_of_clk==2 & index==2) begin
168
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
169
end
170
endgenerate // index==2
171
generate if (number_of_clk==2 & index==3) begin
172
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
173
end
174
endgenerate // index==0
175
 
176
generate if (number_of_clk==3 & index==0) begin
177
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
178
end
179
endgenerate // index==0
180
generate if (number_of_clk==3 & index==1) begin
181
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
182
end
183
endgenerate // index==1
184
generate if (number_of_clk==3 & index==2) begin
185
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
186
end
187
endgenerate // index==2
188
generate if (number_of_clk==3 & index==3) begin
189
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
190
end
191
endgenerate // index==0
192
 
193
genvar i;
194
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
195
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
196
end
197
endgenerate
198
endmodule
199
`endif
200
 
201
`else
202
 
203
`ifdef ALTERA
204
 
205
`else
206
 
207
// generic PLL
208 17 unneback
`timescale 1 ps/1 ps
209 6 unneback
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
210
parameter index = 0;
211
parameter number_of_clk = 1;
212 17 unneback
parameter period_time_0 = 20000;
213
parameter period_time_1 = 20000;
214
parameter period_time_2 = 20000;
215 6 unneback
parameter lock_delay = 2000;
216
input clk_i, rst_n_i;
217
output lock;
218
output reg [0:number_of_clk-1] clk_o;
219
output [0:number_of_clk-1] rst_o;
220
 
221
always
222
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
223
 
224
generate if (number_of_clk > 1)
225
always
226
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
227
endgenerate
228
 
229
generate if (number_of_clk > 2)
230
always
231
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
232
endgenerate
233
 
234
genvar i;
235
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
236
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
237
end
238
endgenerate
239
 
240
assign #lock_delay lock = rst_n_i;
241
 
242
endmodule
243
 
244
`endif //altera
245 17 unneback
`endif //actel
246
//////////////////////////////////////////////////////////////////////
247 6 unneback
////                                                              ////
248
////  Versatile library, registers                                ////
249
////                                                              ////
250
////  Description                                                 ////
251
////  Different type of registers                                 ////
252
////                                                              ////
253
////                                                              ////
254
////  To Do:                                                      ////
255
////   - add more different registers                             ////
256
////                                                              ////
257
////  Author(s):                                                  ////
258
////      - Michael Unneback, unneback@opencores.org              ////
259
////        ORSoC AB                                              ////
260
////                                                              ////
261
//////////////////////////////////////////////////////////////////////
262
////                                                              ////
263
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
264
////                                                              ////
265
//// This source file may be used and distributed without         ////
266
//// restriction provided that this copyright statement is not    ////
267
//// removed from the file and that any derivative work contains  ////
268
//// the original copyright notice and the associated disclaimer. ////
269
////                                                              ////
270
//// This source file is free software; you can redistribute it   ////
271
//// and/or modify it under the terms of the GNU Lesser General   ////
272
//// Public License as published by the Free Software Foundation; ////
273
//// either version 2.1 of the License, or (at your option) any   ////
274
//// later version.                                               ////
275
////                                                              ////
276
//// This source is distributed in the hope that it will be       ////
277
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
278
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
279
//// PURPOSE.  See the GNU Lesser General Public License for more ////
280
//// details.                                                     ////
281
////                                                              ////
282
//// You should have received a copy of the GNU Lesser General    ////
283
//// Public License along with this source; if not, download it   ////
284
//// from http://www.opencores.org/lgpl.shtml                     ////
285
////                                                              ////
286
//////////////////////////////////////////////////////////////////////
287
 
288 18 unneback
module vl_dff ( d, q, clk, rst);
289 6 unneback
 
290
        parameter width = 1;
291
        parameter reset_value = 0;
292
 
293
        input [width-1:0] d;
294
        input clk, rst;
295
        output reg [width-1:0] q;
296
 
297
        always @ (posedge clk or posedge rst)
298
        if (rst)
299
                q <= reset_value;
300
        else
301
                q <= d;
302
 
303
endmodule
304
 
305 18 unneback
module vl_dff_array ( d, q, clk, rst);
306 6 unneback
 
307
        parameter width = 1;
308
        parameter depth = 2;
309
        parameter reset_value = 1'b0;
310
 
311
        input [width-1:0] d;
312
        input clk, rst;
313
        output [width-1:0] q;
314
        reg  [0:depth-1] q_tmp [width-1:0];
315
        integer i;
316
        always @ (posedge clk or posedge rst)
317
        if (rst) begin
318
            for (i=0;i<depth;i=i+1)
319
                q_tmp[i] <= {width{reset_value}};
320
        end else begin
321
            q_tmp[0] <= d;
322
            for (i=1;i<depth;i=i+1)
323
                q_tmp[i] <= q_tmp[i-1];
324
        end
325
 
326
    assign q = q_tmp[depth-1];
327
 
328
endmodule
329
 
330 18 unneback
module vl_dff_ce ( d, ce, q, clk, rst);
331 6 unneback
 
332
        parameter width = 1;
333
        parameter reset_value = 0;
334
 
335
        input [width-1:0] d;
336
        input ce, clk, rst;
337
        output reg [width-1:0] q;
338
 
339
        always @ (posedge clk or posedge rst)
340
        if (rst)
341
                q <= reset_value;
342
        else
343
                if (ce)
344
                        q <= d;
345
 
346
endmodule
347
 
348 18 unneback
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
349 8 unneback
 
350
        parameter width = 1;
351
        parameter reset_value = 0;
352
 
353
        input [width-1:0] d;
354 10 unneback
        input ce, clear, clk, rst;
355 8 unneback
        output reg [width-1:0] q;
356
 
357
        always @ (posedge clk or posedge rst)
358
        if (rst)
359
            q <= reset_value;
360
        else
361
            if (ce)
362
                if (clear)
363
                    q <= {width{1'b0}};
364
                else
365
                    q <= d;
366
 
367
endmodule
368
 
369 24 unneback
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
370
 
371
        parameter width = 1;
372
        parameter reset_value = 0;
373
 
374
        input [width-1:0] d;
375
        input ce, set, clk, rst;
376
        output reg [width-1:0] q;
377
 
378
        always @ (posedge clk or posedge rst)
379
        if (rst)
380
            q <= reset_value;
381
        else
382
            if (ce)
383
                if (set)
384
                    q <= {width{1'b1}};
385
                else
386
                    q <= d;
387
 
388
endmodule
389
 
390 29 unneback
module vl_spr ( sp, r, q, clk, rst);
391
 
392
        parameter width = 1;
393
        parameter reset_value = 0;
394
 
395
        input sp, r;
396
        output reg q;
397
        input clk, rst;
398
 
399
        always @ (posedge clk or posedge rst)
400
        if (rst)
401
            q <= reset_value;
402
        else
403
            if (sp)
404
                q <= 1'b1;
405
            else if (r)
406
                q <= 1'b0;
407
 
408
endmodule
409
 
410
module vl_srp ( s, rp, q, clk, rst);
411
 
412
        parameter width = 1;
413
        parameter reset_value = 0;
414
 
415
        input s, rp;
416
        output reg q;
417
        input clk, rst;
418
 
419
        always @ (posedge clk or posedge rst)
420
        if (rst)
421
            q <= reset_value;
422
        else
423
            if (rp)
424
                q <= 1'b0;
425
            else if (s)
426
                q <= 1'b1;
427
 
428
endmodule
429
 
430
 
431 6 unneback
`ifdef ALTERA
432
// megafunction wizard: %LPM_FF%
433
// GENERATION: STANDARD
434
// VERSION: WM1.0
435
// MODULE: lpm_ff 
436
 
437
// ============================================================
438
// File Name: dff_sr.v
439
// Megafunction Name(s):
440
//                      lpm_ff
441
//
442
// Simulation Library Files(s):
443
//                      lpm
444
// ============================================================
445
// ************************************************************
446
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
447
//
448
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
449
// ************************************************************
450
 
451
 
452
//Copyright (C) 1991-2010 Altera Corporation
453
//Your use of Altera Corporation's design tools, logic functions 
454
//and other software and tools, and its AMPP partner logic 
455
//functions, and any output files from any of the foregoing 
456
//(including device programming or simulation files), and any 
457
//associated documentation or information are expressly subject 
458
//to the terms and conditions of the Altera Program License 
459
//Subscription Agreement, Altera MegaCore Function License 
460
//Agreement, or other applicable license agreement, including, 
461
//without limitation, that your use is for the sole purpose of 
462
//programming logic devices manufactured by Altera and sold by 
463
//Altera or its authorized distributors.  Please refer to the 
464
//applicable agreement for further details.
465
 
466
 
467
// synopsys translate_off
468
`timescale 1 ps / 1 ps
469
// synopsys translate_on
470 18 unneback
module vl_dff_sr (
471 6 unneback
        aclr,
472
        aset,
473
        clock,
474
        data,
475
        q);
476
 
477
        input     aclr;
478
        input     aset;
479
        input     clock;
480
        input     data;
481
        output    q;
482
 
483
        wire [0:0] sub_wire0;
484
        wire [0:0] sub_wire1 = sub_wire0[0:0];
485
        wire  q = sub_wire1;
486
        wire  sub_wire2 = data;
487
        wire  sub_wire3 = sub_wire2;
488
 
489
        lpm_ff  lpm_ff_component (
490
                                .aclr (aclr),
491
                                .clock (clock),
492
                                .data (sub_wire3),
493
                                .aset (aset),
494
                                .q (sub_wire0)
495
                                // synopsys translate_off
496
                                ,
497
                                .aload (),
498
                                .enable (),
499
                                .sclr (),
500
                                .sload (),
501
                                .sset ()
502
                                // synopsys translate_on
503
                                );
504
        defparam
505
                lpm_ff_component.lpm_fftype = "DFF",
506
                lpm_ff_component.lpm_type = "LPM_FF",
507
                lpm_ff_component.lpm_width = 1;
508
 
509
 
510
endmodule
511
 
512
// ============================================================
513
// CNX file retrieval info
514
// ============================================================
515
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
516
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
517
// Retrieval info: PRIVATE: ASET NUMERIC "1"
518
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
519
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
520
// Retrieval info: PRIVATE: DFF NUMERIC "1"
521
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
522
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
523
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
524
// Retrieval info: PRIVATE: SSET NUMERIC "0"
525
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
526
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
527
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
528
// Retrieval info: PRIVATE: nBit NUMERIC "1"
529
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
530
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
531
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
532
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
533
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
534
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
535
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
536
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
537
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
538
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
539
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
540
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
541
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
542
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
543
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
544
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
545
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
546
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
547
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
548
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
549
// Retrieval info: LIB_FILE: lpm
550
 
551
 
552
`else
553
 
554
 
555 18 unneback
module vl_dff_sr ( aclr, aset, clock, data, q);
556 6 unneback
 
557
    input         aclr;
558
    input         aset;
559
    input         clock;
560
    input         data;
561
    output reg    q;
562
 
563
   always @ (posedge clock or posedge aclr or posedge aset)
564
     if (aclr)
565
       q <= 1'b0;
566
     else if (aset)
567
       q <= 1'b1;
568
     else
569
       q <= data;
570
 
571
endmodule
572
 
573
`endif
574
 
575
// LATCH
576
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
577
`ifdef ALTERA
578 18 unneback
module vl_latch ( d, le, q, clk);
579 6 unneback
input d, le;
580
output q;
581
input clk;
582
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
583
endmodule
584
`else
585
module latch ( d, le, q, clk);
586
input d, le;
587
output q;
588
input clk;/*
589
   always @ (posedge direction_set or posedge direction_clr)
590
     if (direction_clr)
591
       direction <= going_empty;
592
     else
593
       direction <= going_full;*/
594
endmodule
595 15 unneback
`endif
596
 
597 18 unneback
module vl_shreg ( d, q, clk, rst);
598 17 unneback
parameter depth = 10;
599
input d;
600
output q;
601
input clk, rst;
602
 
603
reg [1:depth] dffs;
604
 
605
always @ (posedge clk or posedge rst)
606
if (rst)
607
    dffs <= {depth{1'b0}};
608
else
609
    dffs <= {d,dffs[1:depth-1]};
610
assign q = dffs[depth];
611
endmodule
612
 
613 18 unneback
module vl_shreg_ce ( d, ce, q, clk, rst);
614 17 unneback
parameter depth = 10;
615
input d, ce;
616
output q;
617
input clk, rst;
618
 
619
reg [1:depth] dffs;
620
 
621
always @ (posedge clk or posedge rst)
622
if (rst)
623
    dffs <= {depth{1'b0}};
624
else
625
    if (ce)
626
        dffs <= {d,dffs[1:depth-1]};
627
assign q = dffs[depth];
628
endmodule
629
 
630 18 unneback
module vl_delay ( d, q, clk, rst);
631 15 unneback
parameter depth = 10;
632
input d;
633
output q;
634
input clk, rst;
635
 
636
reg [1:depth] dffs;
637
 
638
always @ (posedge clk or posedge rst)
639
if (rst)
640
    dffs <= {depth{1'b0}};
641
else
642
    dffs <= {d,dffs[1:depth-1]};
643
assign q = dffs[depth];
644 17 unneback
endmodule
645
 
646 18 unneback
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
647 17 unneback
parameter depth = 10;
648
input d;
649
output q, emptyflag;
650
input clk, rst;
651
 
652
reg [1:depth] dffs;
653
 
654
always @ (posedge clk or posedge rst)
655
if (rst)
656
    dffs <= {depth{1'b0}};
657
else
658
    dffs <= {d,dffs[1:depth-1]};
659
assign q = dffs[depth];
660
assign emptyflag = !(|dffs);
661
endmodule
662
//////////////////////////////////////////////////////////////////////
663 6 unneback
////                                                              ////
664 18 unneback
////  Logic functions                                             ////
665
////                                                              ////
666
////  Description                                                 ////
667
////  Logic functions such as multiplexers                        ////
668
////                                                              ////
669
////                                                              ////
670
////  To Do:                                                      ////
671
////   -                                                          ////
672
////                                                              ////
673
////  Author(s):                                                  ////
674
////      - Michael Unneback, unneback@opencores.org              ////
675
////        ORSoC AB                                              ////
676
////                                                              ////
677
//////////////////////////////////////////////////////////////////////
678
////                                                              ////
679
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
680
////                                                              ////
681
//// This source file may be used and distributed without         ////
682
//// restriction provided that this copyright statement is not    ////
683
//// removed from the file and that any derivative work contains  ////
684
//// the original copyright notice and the associated disclaimer. ////
685
////                                                              ////
686
//// This source file is free software; you can redistribute it   ////
687
//// and/or modify it under the terms of the GNU Lesser General   ////
688
//// Public License as published by the Free Software Foundation; ////
689
//// either version 2.1 of the License, or (at your option) any   ////
690
//// later version.                                               ////
691
////                                                              ////
692
//// This source is distributed in the hope that it will be       ////
693
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
694
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
695
//// PURPOSE.  See the GNU Lesser General Public License for more ////
696
//// details.                                                     ////
697
////                                                              ////
698
//// You should have received a copy of the GNU Lesser General    ////
699
//// Public License along with this source; if not, download it   ////
700
//// from http://www.opencores.org/lgpl.shtml                     ////
701
////                                                              ////
702
//////////////////////////////////////////////////////////////////////
703
 
704
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
705
 
706
parameter width = 32;
707
parameter nr_of_ports = 4;
708
input [width-1:0] a3, a2, a1, a0;
709
input [nr_of_ports-1:0] sel;
710 22 unneback
output [width-1:0] dout;
711 18 unneback
 
712 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
713 18 unneback
integer i;
714
 
715
// and
716
assign tmp[0] = {width{sel[0]}} & a0;
717
assign tmp[1] = {width{sel[1]}} & a1;
718
assign tmp[2] = {width{sel[2]}} & a2;
719
assign tmp[3] = {width{sel[3]}} & a3;
720
 
721
// or
722
assign dout = tmp[3] | tmp[2] | tmp[1] | tmp[0];
723
 
724
endmodule
725
 
726
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
727
 
728
parameter width = 32;
729
parameter nr_of_ports = 5;
730
input [width-1:0] a4, a3, a2, a1, a0;
731
input [nr_of_ports-1:0] sel;
732 22 unneback
output [width-1:0] dout;
733 18 unneback
 
734 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
735 18 unneback
integer i;
736
 
737
// and
738
assign tmp[0] = {width{sel[0]}} & a0;
739
assign tmp[1] = {width{sel[1]}} & a1;
740
assign tmp[2] = {width{sel[2]}} & a2;
741
assign tmp[3] = {width{sel[3]}} & a3;
742
assign tmp[4] = {width{sel[4]}} & a4;
743
 
744
// or
745
assign dout = tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
746
 
747
endmodule
748
 
749
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
750
 
751
parameter width = 32;
752
parameter nr_of_ports = 6;
753
input [width-1:0] a5, a4, a3, a2, a1, a0;
754
input [nr_of_ports-1:0] sel;
755 22 unneback
output [width-1:0] dout;
756 18 unneback
 
757 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
758 18 unneback
integer i;
759
 
760
// and
761
assign tmp[0] = {width{sel[0]}} & a0;
762
assign tmp[1] = {width{sel[1]}} & a1;
763
assign tmp[2] = {width{sel[2]}} & a2;
764
assign tmp[3] = {width{sel[3]}} & a3;
765
assign tmp[4] = {width{sel[4]}} & a4;
766
assign tmp[5] = {width{sel[5]}} & a5;
767
 
768
// or
769
assign dout = tmp[5] | tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
770
 
771
endmodule
772
//////////////////////////////////////////////////////////////////////
773
////                                                              ////
774 6 unneback
////  Versatile counter                                           ////
775
////                                                              ////
776
////  Description                                                 ////
777
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
778
////  counter                                                     ////
779
////                                                              ////
780
////  To Do:                                                      ////
781
////   - add LFSR with more taps                                  ////
782
////                                                              ////
783
////  Author(s):                                                  ////
784
////      - Michael Unneback, unneback@opencores.org              ////
785
////        ORSoC AB                                              ////
786
////                                                              ////
787
//////////////////////////////////////////////////////////////////////
788
////                                                              ////
789
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
790
////                                                              ////
791
//// This source file may be used and distributed without         ////
792
//// restriction provided that this copyright statement is not    ////
793
//// removed from the file and that any derivative work contains  ////
794
//// the original copyright notice and the associated disclaimer. ////
795
////                                                              ////
796
//// This source file is free software; you can redistribute it   ////
797
//// and/or modify it under the terms of the GNU Lesser General   ////
798
//// Public License as published by the Free Software Foundation; ////
799
//// either version 2.1 of the License, or (at your option) any   ////
800
//// later version.                                               ////
801
////                                                              ////
802
//// This source is distributed in the hope that it will be       ////
803
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
804
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
805
//// PURPOSE.  See the GNU Lesser General Public License for more ////
806
//// details.                                                     ////
807
////                                                              ////
808
//// You should have received a copy of the GNU Lesser General    ////
809
//// Public License along with this source; if not, download it   ////
810
//// from http://www.opencores.org/lgpl.shtml                     ////
811
////                                                              ////
812
//////////////////////////////////////////////////////////////////////
813
 
814
// binary counter
815 22 unneback
module vl_cnt_bin ( q, rst, clk);
816
 
817
   parameter length = 4;
818
   output [length:1] q;
819
   input rst;
820
   input clk;
821
 
822
   parameter clear_value = 0;
823
   parameter set_value = 1;
824
   parameter wrap_value = 0;
825
   parameter level1_value = 15;
826
 
827
   reg  [length:1] qi;
828
   wire [length:1] q_next;
829
   assign q_next = qi + {{length-1{1'b0}},1'b1};
830
 
831
   always @ (posedge clk or posedge rst)
832
     if (rst)
833
       qi <= {length{1'b0}};
834
     else
835
       qi <= q_next;
836
 
837
   assign q = qi;
838
 
839
endmodule
840
//////////////////////////////////////////////////////////////////////
841
////                                                              ////
842
////  Versatile counter                                           ////
843
////                                                              ////
844
////  Description                                                 ////
845
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
846
////  counter                                                     ////
847
////                                                              ////
848
////  To Do:                                                      ////
849
////   - add LFSR with more taps                                  ////
850
////                                                              ////
851
////  Author(s):                                                  ////
852
////      - Michael Unneback, unneback@opencores.org              ////
853
////        ORSoC AB                                              ////
854
////                                                              ////
855
//////////////////////////////////////////////////////////////////////
856
////                                                              ////
857
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
858
////                                                              ////
859
//// This source file may be used and distributed without         ////
860
//// restriction provided that this copyright statement is not    ////
861
//// removed from the file and that any derivative work contains  ////
862
//// the original copyright notice and the associated disclaimer. ////
863
////                                                              ////
864
//// This source file is free software; you can redistribute it   ////
865
//// and/or modify it under the terms of the GNU Lesser General   ////
866
//// Public License as published by the Free Software Foundation; ////
867
//// either version 2.1 of the License, or (at your option) any   ////
868
//// later version.                                               ////
869
////                                                              ////
870
//// This source is distributed in the hope that it will be       ////
871
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
872
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
873
//// PURPOSE.  See the GNU Lesser General Public License for more ////
874
//// details.                                                     ////
875
////                                                              ////
876
//// You should have received a copy of the GNU Lesser General    ////
877
//// Public License along with this source; if not, download it   ////
878
//// from http://www.opencores.org/lgpl.shtml                     ////
879
////                                                              ////
880
//////////////////////////////////////////////////////////////////////
881
 
882
// binary counter
883
module vl_cnt_bin_clear ( clear, q, rst, clk);
884
 
885
   parameter length = 4;
886
   input clear;
887
   output [length:1] q;
888
   input rst;
889
   input clk;
890
 
891
   parameter clear_value = 0;
892
   parameter set_value = 1;
893
   parameter wrap_value = 0;
894
   parameter level1_value = 15;
895
 
896
   reg  [length:1] qi;
897
   wire [length:1] q_next;
898
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
899
 
900
   always @ (posedge clk or posedge rst)
901
     if (rst)
902
       qi <= {length{1'b0}};
903
     else
904
       qi <= q_next;
905
 
906
   assign q = qi;
907
 
908
endmodule
909
//////////////////////////////////////////////////////////////////////
910
////                                                              ////
911
////  Versatile counter                                           ////
912
////                                                              ////
913
////  Description                                                 ////
914
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
915
////  counter                                                     ////
916
////                                                              ////
917
////  To Do:                                                      ////
918
////   - add LFSR with more taps                                  ////
919
////                                                              ////
920
////  Author(s):                                                  ////
921
////      - Michael Unneback, unneback@opencores.org              ////
922
////        ORSoC AB                                              ////
923
////                                                              ////
924
//////////////////////////////////////////////////////////////////////
925
////                                                              ////
926
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
927
////                                                              ////
928
//// This source file may be used and distributed without         ////
929
//// restriction provided that this copyright statement is not    ////
930
//// removed from the file and that any derivative work contains  ////
931
//// the original copyright notice and the associated disclaimer. ////
932
////                                                              ////
933
//// This source file is free software; you can redistribute it   ////
934
//// and/or modify it under the terms of the GNU Lesser General   ////
935
//// Public License as published by the Free Software Foundation; ////
936
//// either version 2.1 of the License, or (at your option) any   ////
937
//// later version.                                               ////
938
////                                                              ////
939
//// This source is distributed in the hope that it will be       ////
940
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
941
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
942
//// PURPOSE.  See the GNU Lesser General Public License for more ////
943
//// details.                                                     ////
944
////                                                              ////
945
//// You should have received a copy of the GNU Lesser General    ////
946
//// Public License along with this source; if not, download it   ////
947
//// from http://www.opencores.org/lgpl.shtml                     ////
948
////                                                              ////
949
//////////////////////////////////////////////////////////////////////
950
 
951
// binary counter
952 18 unneback
module vl_cnt_bin_ce ( cke, q, rst, clk);
953 6 unneback
 
954
   parameter length = 4;
955
   input cke;
956
   output [length:1] q;
957
   input rst;
958
   input clk;
959
 
960
   parameter clear_value = 0;
961
   parameter set_value = 1;
962
   parameter wrap_value = 0;
963
   parameter level1_value = 15;
964
 
965
   reg  [length:1] qi;
966
   wire [length:1] q_next;
967
   assign q_next = qi + {{length-1{1'b0}},1'b1};
968
 
969
   always @ (posedge clk or posedge rst)
970
     if (rst)
971
       qi <= {length{1'b0}};
972
     else
973
     if (cke)
974
       qi <= q_next;
975
 
976
   assign q = qi;
977
 
978
endmodule
979
//////////////////////////////////////////////////////////////////////
980
////                                                              ////
981
////  Versatile counter                                           ////
982
////                                                              ////
983
////  Description                                                 ////
984
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
985
////  counter                                                     ////
986
////                                                              ////
987
////  To Do:                                                      ////
988
////   - add LFSR with more taps                                  ////
989
////                                                              ////
990
////  Author(s):                                                  ////
991
////      - Michael Unneback, unneback@opencores.org              ////
992
////        ORSoC AB                                              ////
993
////                                                              ////
994
//////////////////////////////////////////////////////////////////////
995
////                                                              ////
996
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
997
////                                                              ////
998
//// This source file may be used and distributed without         ////
999
//// restriction provided that this copyright statement is not    ////
1000
//// removed from the file and that any derivative work contains  ////
1001
//// the original copyright notice and the associated disclaimer. ////
1002
////                                                              ////
1003
//// This source file is free software; you can redistribute it   ////
1004
//// and/or modify it under the terms of the GNU Lesser General   ////
1005
//// Public License as published by the Free Software Foundation; ////
1006
//// either version 2.1 of the License, or (at your option) any   ////
1007
//// later version.                                               ////
1008
////                                                              ////
1009
//// This source is distributed in the hope that it will be       ////
1010
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1011
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1012
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1013
//// details.                                                     ////
1014
////                                                              ////
1015
//// You should have received a copy of the GNU Lesser General    ////
1016
//// Public License along with this source; if not, download it   ////
1017
//// from http://www.opencores.org/lgpl.shtml                     ////
1018
////                                                              ////
1019
//////////////////////////////////////////////////////////////////////
1020
 
1021
// binary counter
1022 18 unneback
module vl_cnt_bin_ce_clear ( clear, cke, q, rst, clk);
1023 6 unneback
 
1024
   parameter length = 4;
1025
   input clear;
1026
   input cke;
1027
   output [length:1] q;
1028
   input rst;
1029
   input clk;
1030
 
1031
   parameter clear_value = 0;
1032
   parameter set_value = 1;
1033
   parameter wrap_value = 0;
1034
   parameter level1_value = 15;
1035
 
1036
   reg  [length:1] qi;
1037
   wire [length:1] q_next;
1038
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1039
 
1040
   always @ (posedge clk or posedge rst)
1041
     if (rst)
1042
       qi <= {length{1'b0}};
1043
     else
1044
     if (cke)
1045
       qi <= q_next;
1046
 
1047
   assign q = qi;
1048
 
1049
endmodule
1050
//////////////////////////////////////////////////////////////////////
1051
////                                                              ////
1052
////  Versatile counter                                           ////
1053
////                                                              ////
1054
////  Description                                                 ////
1055
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1056
////  counter                                                     ////
1057
////                                                              ////
1058
////  To Do:                                                      ////
1059
////   - add LFSR with more taps                                  ////
1060
////                                                              ////
1061
////  Author(s):                                                  ////
1062
////      - Michael Unneback, unneback@opencores.org              ////
1063
////        ORSoC AB                                              ////
1064
////                                                              ////
1065
//////////////////////////////////////////////////////////////////////
1066
////                                                              ////
1067
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1068
////                                                              ////
1069
//// This source file may be used and distributed without         ////
1070
//// restriction provided that this copyright statement is not    ////
1071
//// removed from the file and that any derivative work contains  ////
1072
//// the original copyright notice and the associated disclaimer. ////
1073
////                                                              ////
1074
//// This source file is free software; you can redistribute it   ////
1075
//// and/or modify it under the terms of the GNU Lesser General   ////
1076
//// Public License as published by the Free Software Foundation; ////
1077
//// either version 2.1 of the License, or (at your option) any   ////
1078
//// later version.                                               ////
1079
////                                                              ////
1080
//// This source is distributed in the hope that it will be       ////
1081
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1082
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1083
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1084
//// details.                                                     ////
1085
////                                                              ////
1086
//// You should have received a copy of the GNU Lesser General    ////
1087
//// Public License along with this source; if not, download it   ////
1088
//// from http://www.opencores.org/lgpl.shtml                     ////
1089
////                                                              ////
1090
//////////////////////////////////////////////////////////////////////
1091
 
1092
// binary counter
1093 29 unneback
module vl_cnt_bin_ce_clear_l1_l2 ( clear, cke, q, level1, level2, rst, clk);
1094
 
1095
   parameter length = 4;
1096
   input clear;
1097
   input cke;
1098
   output [length:1] q;
1099
   output reg level1;
1100
   output reg level2;
1101
   input rst;
1102
   input clk;
1103
 
1104
   parameter clear_value = 0;
1105
   parameter set_value = 1;
1106 30 unneback
   parameter wrap_value = 15;
1107
   parameter level1_value = 8;
1108
   parameter level2_value = 15;
1109 29 unneback
 
1110
   wire rew;
1111 30 unneback
   assign rew = 1'b0;
1112 29 unneback
   reg  [length:1] qi;
1113
   wire [length:1] q_next;
1114
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1115
 
1116
   always @ (posedge clk or posedge rst)
1117
     if (rst)
1118
       qi <= {length{1'b0}};
1119
     else
1120
     if (cke)
1121
       qi <= q_next;
1122
 
1123
   assign q = qi;
1124
 
1125
 
1126
    always @ (posedge clk or posedge rst)
1127
    if (rst)
1128
        level1 <= 1'b0;
1129
    else
1130
    if (cke)
1131
    if (clear)
1132
        level1 <= 1'b0;
1133
    else if (q_next == level1_value)
1134
        level1 <= 1'b1;
1135
    else if (qi == level1_value & rew)
1136
        level1 <= 1'b0;
1137
 
1138
    always @ (posedge clk or posedge rst)
1139
    if (rst)
1140
        level2 <= 1'b0;
1141
    else
1142
    if (cke)
1143
    if (clear)
1144
        level2 <= 1'b0;
1145
    else if (q_next == level2_value)
1146
        level2 <= 1'b1;
1147
    else if (qi == level2_value & rew)
1148
        level2 <= 1'b0;
1149
endmodule
1150
//////////////////////////////////////////////////////////////////////
1151
////                                                              ////
1152
////  Versatile counter                                           ////
1153
////                                                              ////
1154
////  Description                                                 ////
1155
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1156
////  counter                                                     ////
1157
////                                                              ////
1158
////  To Do:                                                      ////
1159
////   - add LFSR with more taps                                  ////
1160
////                                                              ////
1161
////  Author(s):                                                  ////
1162
////      - Michael Unneback, unneback@opencores.org              ////
1163
////        ORSoC AB                                              ////
1164
////                                                              ////
1165
//////////////////////////////////////////////////////////////////////
1166
////                                                              ////
1167
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1168
////                                                              ////
1169
//// This source file may be used and distributed without         ////
1170
//// restriction provided that this copyright statement is not    ////
1171
//// removed from the file and that any derivative work contains  ////
1172
//// the original copyright notice and the associated disclaimer. ////
1173
////                                                              ////
1174
//// This source file is free software; you can redistribute it   ////
1175
//// and/or modify it under the terms of the GNU Lesser General   ////
1176
//// Public License as published by the Free Software Foundation; ////
1177
//// either version 2.1 of the License, or (at your option) any   ////
1178
//// later version.                                               ////
1179
////                                                              ////
1180
//// This source is distributed in the hope that it will be       ////
1181
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1182
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1183
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1184
//// details.                                                     ////
1185
////                                                              ////
1186
//// You should have received a copy of the GNU Lesser General    ////
1187
//// Public License along with this source; if not, download it   ////
1188
//// from http://www.opencores.org/lgpl.shtml                     ////
1189
////                                                              ////
1190
//////////////////////////////////////////////////////////////////////
1191
 
1192
// binary counter
1193 18 unneback
module vl_cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk);
1194 6 unneback
 
1195
   parameter length = 4;
1196
   input clear;
1197
   input set;
1198
   input cke;
1199
   input rew;
1200
   output [length:1] q;
1201
   input rst;
1202
   input clk;
1203
 
1204
   parameter clear_value = 0;
1205
   parameter set_value = 1;
1206
   parameter wrap_value = 0;
1207
   parameter level1_value = 15;
1208
 
1209
   reg  [length:1] qi;
1210
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1211
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
1212
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
1213
   assign q_next = rew ? q_next_rew : q_next_fw;
1214
 
1215
   always @ (posedge clk or posedge rst)
1216
     if (rst)
1217
       qi <= {length{1'b0}};
1218
     else
1219
     if (cke)
1220
       qi <= q_next;
1221
 
1222
   assign q = qi;
1223
 
1224
endmodule
1225
//////////////////////////////////////////////////////////////////////
1226
////                                                              ////
1227
////  Versatile counter                                           ////
1228
////                                                              ////
1229
////  Description                                                 ////
1230
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1231
////  counter                                                     ////
1232
////                                                              ////
1233
////  To Do:                                                      ////
1234
////   - add LFSR with more taps                                  ////
1235
////                                                              ////
1236
////  Author(s):                                                  ////
1237
////      - Michael Unneback, unneback@opencores.org              ////
1238
////        ORSoC AB                                              ////
1239
////                                                              ////
1240
//////////////////////////////////////////////////////////////////////
1241
////                                                              ////
1242
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1243
////                                                              ////
1244
//// This source file may be used and distributed without         ////
1245
//// restriction provided that this copyright statement is not    ////
1246
//// removed from the file and that any derivative work contains  ////
1247
//// the original copyright notice and the associated disclaimer. ////
1248
////                                                              ////
1249
//// This source file is free software; you can redistribute it   ////
1250
//// and/or modify it under the terms of the GNU Lesser General   ////
1251
//// Public License as published by the Free Software Foundation; ////
1252
//// either version 2.1 of the License, or (at your option) any   ////
1253
//// later version.                                               ////
1254
////                                                              ////
1255
//// This source is distributed in the hope that it will be       ////
1256
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1257
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1258
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1259
//// details.                                                     ////
1260
////                                                              ////
1261
//// You should have received a copy of the GNU Lesser General    ////
1262
//// Public License along with this source; if not, download it   ////
1263
//// from http://www.opencores.org/lgpl.shtml                     ////
1264
////                                                              ////
1265
//////////////////////////////////////////////////////////////////////
1266
 
1267
// binary counter
1268 18 unneback
module vl_cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk);
1269 6 unneback
 
1270
   parameter length = 4;
1271
   input cke;
1272
   input rew;
1273
   output reg level1;
1274
   input rst;
1275
   input clk;
1276
 
1277
   parameter clear_value = 0;
1278
   parameter set_value = 1;
1279
   parameter wrap_value = 1;
1280
   parameter level1_value = 15;
1281
 
1282 29 unneback
   wire clear;
1283 30 unneback
   assign clear = 1'b0;
1284 6 unneback
   reg  [length:1] qi;
1285
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1286
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1287
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1288
   assign q_next = rew ? q_next_rew : q_next_fw;
1289
 
1290
   always @ (posedge clk or posedge rst)
1291
     if (rst)
1292
       qi <= {length{1'b0}};
1293
     else
1294
     if (cke)
1295
       qi <= q_next;
1296
 
1297
 
1298
 
1299
    always @ (posedge clk or posedge rst)
1300
    if (rst)
1301
        level1 <= 1'b0;
1302
    else
1303
    if (cke)
1304 29 unneback
    if (clear)
1305
        level1 <= 1'b0;
1306
    else if (q_next == level1_value)
1307 6 unneback
        level1 <= 1'b1;
1308
    else if (qi == level1_value & rew)
1309
        level1 <= 1'b0;
1310
endmodule
1311
//////////////////////////////////////////////////////////////////////
1312
////                                                              ////
1313
////  Versatile counter                                           ////
1314
////                                                              ////
1315
////  Description                                                 ////
1316
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1317
////  counter                                                     ////
1318
////                                                              ////
1319
////  To Do:                                                      ////
1320
////   - add LFSR with more taps                                  ////
1321
////                                                              ////
1322
////  Author(s):                                                  ////
1323
////      - Michael Unneback, unneback@opencores.org              ////
1324
////        ORSoC AB                                              ////
1325
////                                                              ////
1326
//////////////////////////////////////////////////////////////////////
1327
////                                                              ////
1328
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1329
////                                                              ////
1330
//// This source file may be used and distributed without         ////
1331
//// restriction provided that this copyright statement is not    ////
1332
//// removed from the file and that any derivative work contains  ////
1333
//// the original copyright notice and the associated disclaimer. ////
1334
////                                                              ////
1335
//// This source file is free software; you can redistribute it   ////
1336
//// and/or modify it under the terms of the GNU Lesser General   ////
1337
//// Public License as published by the Free Software Foundation; ////
1338
//// either version 2.1 of the License, or (at your option) any   ////
1339
//// later version.                                               ////
1340
////                                                              ////
1341
//// This source is distributed in the hope that it will be       ////
1342
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1343
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1344
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1345
//// details.                                                     ////
1346
////                                                              ////
1347
//// You should have received a copy of the GNU Lesser General    ////
1348
//// Public License along with this source; if not, download it   ////
1349
//// from http://www.opencores.org/lgpl.shtml                     ////
1350
////                                                              ////
1351
//////////////////////////////////////////////////////////////////////
1352
 
1353 25 unneback
// binary counter
1354
module vl_cnt_bin_ce_rew_zq_l1 ( cke, rew, zq, level1, rst, clk);
1355
 
1356
   parameter length = 4;
1357
   input cke;
1358
   input rew;
1359
   output reg zq;
1360
   output reg level1;
1361
   input rst;
1362
   input clk;
1363
 
1364
   parameter clear_value = 0;
1365
   parameter set_value = 1;
1366
   parameter wrap_value = 1;
1367
   parameter level1_value = 15;
1368
 
1369 29 unneback
   wire clear;
1370 30 unneback
   assign clear = 1'b0;
1371 25 unneback
   reg  [length:1] qi;
1372
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1373
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1374
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1375
   assign q_next = rew ? q_next_rew : q_next_fw;
1376
 
1377
   always @ (posedge clk or posedge rst)
1378
     if (rst)
1379
       qi <= {length{1'b0}};
1380
     else
1381
     if (cke)
1382
       qi <= q_next;
1383
 
1384
 
1385
 
1386
   always @ (posedge clk or posedge rst)
1387
     if (rst)
1388
       zq <= 1'b1;
1389
     else
1390
     if (cke)
1391
       zq <= q_next == {length{1'b0}};
1392
 
1393
    always @ (posedge clk or posedge rst)
1394
    if (rst)
1395
        level1 <= 1'b0;
1396
    else
1397
    if (cke)
1398 29 unneback
    if (clear)
1399
        level1 <= 1'b0;
1400
    else if (q_next == level1_value)
1401 25 unneback
        level1 <= 1'b1;
1402
    else if (qi == level1_value & rew)
1403
        level1 <= 1'b0;
1404
endmodule
1405
//////////////////////////////////////////////////////////////////////
1406
////                                                              ////
1407
////  Versatile counter                                           ////
1408
////                                                              ////
1409
////  Description                                                 ////
1410
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1411
////  counter                                                     ////
1412
////                                                              ////
1413
////  To Do:                                                      ////
1414
////   - add LFSR with more taps                                  ////
1415
////                                                              ////
1416
////  Author(s):                                                  ////
1417
////      - Michael Unneback, unneback@opencores.org              ////
1418
////        ORSoC AB                                              ////
1419
////                                                              ////
1420
//////////////////////////////////////////////////////////////////////
1421
////                                                              ////
1422
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1423
////                                                              ////
1424
//// This source file may be used and distributed without         ////
1425
//// restriction provided that this copyright statement is not    ////
1426
//// removed from the file and that any derivative work contains  ////
1427
//// the original copyright notice and the associated disclaimer. ////
1428
////                                                              ////
1429
//// This source file is free software; you can redistribute it   ////
1430
//// and/or modify it under the terms of the GNU Lesser General   ////
1431
//// Public License as published by the Free Software Foundation; ////
1432
//// either version 2.1 of the License, or (at your option) any   ////
1433
//// later version.                                               ////
1434
////                                                              ////
1435
//// This source is distributed in the hope that it will be       ////
1436
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1437
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1438
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1439
//// details.                                                     ////
1440
////                                                              ////
1441
//// You should have received a copy of the GNU Lesser General    ////
1442
//// Public License along with this source; if not, download it   ////
1443
//// from http://www.opencores.org/lgpl.shtml                     ////
1444
////                                                              ////
1445
//////////////////////////////////////////////////////////////////////
1446
 
1447
// binary counter
1448
module vl_cnt_bin_ce_rew_q_zq_l1 ( cke, rew, q, zq, level1, rst, clk);
1449
 
1450
   parameter length = 4;
1451
   input cke;
1452
   input rew;
1453
   output [length:1] q;
1454
   output reg zq;
1455
   output reg level1;
1456
   input rst;
1457
   input clk;
1458
 
1459
   parameter clear_value = 0;
1460
   parameter set_value = 1;
1461
   parameter wrap_value = 1;
1462
   parameter level1_value = 15;
1463
 
1464 29 unneback
   wire clear;
1465 30 unneback
   assign clear = 1'b0;
1466 25 unneback
   reg  [length:1] qi;
1467
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1468
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1469
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1470
   assign q_next = rew ? q_next_rew : q_next_fw;
1471
 
1472
   always @ (posedge clk or posedge rst)
1473
     if (rst)
1474
       qi <= {length{1'b0}};
1475
     else
1476
     if (cke)
1477
       qi <= q_next;
1478
 
1479
   assign q = qi;
1480
 
1481
 
1482
   always @ (posedge clk or posedge rst)
1483
     if (rst)
1484
       zq <= 1'b1;
1485
     else
1486
     if (cke)
1487
       zq <= q_next == {length{1'b0}};
1488
 
1489
    always @ (posedge clk or posedge rst)
1490
    if (rst)
1491
        level1 <= 1'b0;
1492
    else
1493
    if (cke)
1494 29 unneback
    if (clear)
1495
        level1 <= 1'b0;
1496
    else if (q_next == level1_value)
1497 25 unneback
        level1 <= 1'b1;
1498
    else if (qi == level1_value & rew)
1499
        level1 <= 1'b0;
1500
endmodule
1501
//////////////////////////////////////////////////////////////////////
1502
////                                                              ////
1503
////  Versatile counter                                           ////
1504
////                                                              ////
1505
////  Description                                                 ////
1506
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1507
////  counter                                                     ////
1508
////                                                              ////
1509
////  To Do:                                                      ////
1510
////   - add LFSR with more taps                                  ////
1511
////                                                              ////
1512
////  Author(s):                                                  ////
1513
////      - Michael Unneback, unneback@opencores.org              ////
1514
////        ORSoC AB                                              ////
1515
////                                                              ////
1516
//////////////////////////////////////////////////////////////////////
1517
////                                                              ////
1518
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1519
////                                                              ////
1520
//// This source file may be used and distributed without         ////
1521
//// restriction provided that this copyright statement is not    ////
1522
//// removed from the file and that any derivative work contains  ////
1523
//// the original copyright notice and the associated disclaimer. ////
1524
////                                                              ////
1525
//// This source file is free software; you can redistribute it   ////
1526
//// and/or modify it under the terms of the GNU Lesser General   ////
1527
//// Public License as published by the Free Software Foundation; ////
1528
//// either version 2.1 of the License, or (at your option) any   ////
1529
//// later version.                                               ////
1530
////                                                              ////
1531
//// This source is distributed in the hope that it will be       ////
1532
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1533
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1534
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1535
//// details.                                                     ////
1536
////                                                              ////
1537
//// You should have received a copy of the GNU Lesser General    ////
1538
//// Public License along with this source; if not, download it   ////
1539
//// from http://www.opencores.org/lgpl.shtml                     ////
1540
////                                                              ////
1541
//////////////////////////////////////////////////////////////////////
1542
 
1543 6 unneback
// LFSR counter
1544 18 unneback
module vl_cnt_lfsr_zq ( zq, rst, clk);
1545 6 unneback
 
1546
   parameter length = 4;
1547
   output reg zq;
1548
   input rst;
1549
   input clk;
1550
 
1551
   parameter clear_value = 0;
1552
   parameter set_value = 1;
1553
   parameter wrap_value = 8;
1554
   parameter level1_value = 15;
1555
 
1556
   reg  [length:1] qi;
1557
   reg lfsr_fb;
1558
   wire [length:1] q_next;
1559
   reg [32:1] polynom;
1560
   integer i;
1561
 
1562
   always @ (qi)
1563
   begin
1564
        case (length)
1565
         2: polynom = 32'b11;                               // 0x3
1566
         3: polynom = 32'b110;                              // 0x6
1567
         4: polynom = 32'b1100;                             // 0xC
1568
         5: polynom = 32'b10100;                            // 0x14
1569
         6: polynom = 32'b110000;                           // 0x30
1570
         7: polynom = 32'b1100000;                          // 0x60
1571
         8: polynom = 32'b10111000;                         // 0xb8
1572
         9: polynom = 32'b100010000;                        // 0x110
1573
        10: polynom = 32'b1001000000;                       // 0x240
1574
        11: polynom = 32'b10100000000;                      // 0x500
1575
        12: polynom = 32'b100000101001;                     // 0x829
1576
        13: polynom = 32'b1000000001100;                    // 0x100C
1577
        14: polynom = 32'b10000000010101;                   // 0x2015
1578
        15: polynom = 32'b110000000000000;                  // 0x6000
1579
        16: polynom = 32'b1101000000001000;                 // 0xD008
1580
        17: polynom = 32'b10010000000000000;                // 0x12000
1581
        18: polynom = 32'b100000010000000000;               // 0x20400
1582
        19: polynom = 32'b1000000000000100011;              // 0x40023
1583
        20: polynom = 32'b10000010000000000000;             // 0x82000
1584
        21: polynom = 32'b101000000000000000000;            // 0x140000
1585
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1586
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1587
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1588
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1589
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1590
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1591
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1592
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1593
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1594
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1595
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1596
        default: polynom = 32'b0;
1597
        endcase
1598
        lfsr_fb = qi[length];
1599
        for (i=length-1; i>=1; i=i-1) begin
1600
            if (polynom[i])
1601
                lfsr_fb = lfsr_fb  ~^ qi[i];
1602
        end
1603
    end
1604
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1605
 
1606
   always @ (posedge clk or posedge rst)
1607
     if (rst)
1608
       qi <= {length{1'b0}};
1609
     else
1610
       qi <= q_next;
1611
 
1612
 
1613
 
1614
   always @ (posedge clk or posedge rst)
1615
     if (rst)
1616
       zq <= 1'b1;
1617
     else
1618
       zq <= q_next == {length{1'b0}};
1619
endmodule
1620
//////////////////////////////////////////////////////////////////////
1621
////                                                              ////
1622
////  Versatile counter                                           ////
1623
////                                                              ////
1624
////  Description                                                 ////
1625
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1626
////  counter                                                     ////
1627
////                                                              ////
1628
////  To Do:                                                      ////
1629
////   - add LFSR with more taps                                  ////
1630
////                                                              ////
1631
////  Author(s):                                                  ////
1632
////      - Michael Unneback, unneback@opencores.org              ////
1633
////        ORSoC AB                                              ////
1634
////                                                              ////
1635
//////////////////////////////////////////////////////////////////////
1636
////                                                              ////
1637
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1638
////                                                              ////
1639
//// This source file may be used and distributed without         ////
1640
//// restriction provided that this copyright statement is not    ////
1641
//// removed from the file and that any derivative work contains  ////
1642
//// the original copyright notice and the associated disclaimer. ////
1643
////                                                              ////
1644
//// This source file is free software; you can redistribute it   ////
1645
//// and/or modify it under the terms of the GNU Lesser General   ////
1646
//// Public License as published by the Free Software Foundation; ////
1647
//// either version 2.1 of the License, or (at your option) any   ////
1648
//// later version.                                               ////
1649
////                                                              ////
1650
//// This source is distributed in the hope that it will be       ////
1651
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1652
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1653
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1654
//// details.                                                     ////
1655
////                                                              ////
1656
//// You should have received a copy of the GNU Lesser General    ////
1657
//// Public License along with this source; if not, download it   ////
1658
//// from http://www.opencores.org/lgpl.shtml                     ////
1659
////                                                              ////
1660
//////////////////////////////////////////////////////////////////////
1661
 
1662
// LFSR counter
1663 18 unneback
module vl_cnt_lfsr_ce_zq ( cke, zq, rst, clk);
1664 6 unneback
 
1665
   parameter length = 4;
1666
   input cke;
1667
   output reg zq;
1668
   input rst;
1669
   input clk;
1670
 
1671
   parameter clear_value = 0;
1672
   parameter set_value = 1;
1673
   parameter wrap_value = 8;
1674
   parameter level1_value = 15;
1675
 
1676
   reg  [length:1] qi;
1677
   reg lfsr_fb;
1678
   wire [length:1] q_next;
1679
   reg [32:1] polynom;
1680
   integer i;
1681
 
1682
   always @ (qi)
1683
   begin
1684
        case (length)
1685
         2: polynom = 32'b11;                               // 0x3
1686
         3: polynom = 32'b110;                              // 0x6
1687
         4: polynom = 32'b1100;                             // 0xC
1688
         5: polynom = 32'b10100;                            // 0x14
1689
         6: polynom = 32'b110000;                           // 0x30
1690
         7: polynom = 32'b1100000;                          // 0x60
1691
         8: polynom = 32'b10111000;                         // 0xb8
1692
         9: polynom = 32'b100010000;                        // 0x110
1693
        10: polynom = 32'b1001000000;                       // 0x240
1694
        11: polynom = 32'b10100000000;                      // 0x500
1695
        12: polynom = 32'b100000101001;                     // 0x829
1696
        13: polynom = 32'b1000000001100;                    // 0x100C
1697
        14: polynom = 32'b10000000010101;                   // 0x2015
1698
        15: polynom = 32'b110000000000000;                  // 0x6000
1699
        16: polynom = 32'b1101000000001000;                 // 0xD008
1700
        17: polynom = 32'b10010000000000000;                // 0x12000
1701
        18: polynom = 32'b100000010000000000;               // 0x20400
1702
        19: polynom = 32'b1000000000000100011;              // 0x40023
1703
        20: polynom = 32'b10000010000000000000;             // 0x82000
1704
        21: polynom = 32'b101000000000000000000;            // 0x140000
1705
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1706
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1707
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1708
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1709
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1710
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1711
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1712
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1713
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1714
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1715
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1716
        default: polynom = 32'b0;
1717
        endcase
1718
        lfsr_fb = qi[length];
1719
        for (i=length-1; i>=1; i=i-1) begin
1720
            if (polynom[i])
1721
                lfsr_fb = lfsr_fb  ~^ qi[i];
1722
        end
1723
    end
1724
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1725
 
1726
   always @ (posedge clk or posedge rst)
1727
     if (rst)
1728
       qi <= {length{1'b0}};
1729
     else
1730
     if (cke)
1731
       qi <= q_next;
1732
 
1733
 
1734
 
1735
   always @ (posedge clk or posedge rst)
1736
     if (rst)
1737
       zq <= 1'b1;
1738
     else
1739
     if (cke)
1740
       zq <= q_next == {length{1'b0}};
1741
endmodule
1742
//////////////////////////////////////////////////////////////////////
1743
////                                                              ////
1744
////  Versatile counter                                           ////
1745
////                                                              ////
1746
////  Description                                                 ////
1747
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1748
////  counter                                                     ////
1749
////                                                              ////
1750
////  To Do:                                                      ////
1751
////   - add LFSR with more taps                                  ////
1752
////                                                              ////
1753
////  Author(s):                                                  ////
1754
////      - Michael Unneback, unneback@opencores.org              ////
1755
////        ORSoC AB                                              ////
1756
////                                                              ////
1757
//////////////////////////////////////////////////////////////////////
1758
////                                                              ////
1759
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1760
////                                                              ////
1761
//// This source file may be used and distributed without         ////
1762
//// restriction provided that this copyright statement is not    ////
1763
//// removed from the file and that any derivative work contains  ////
1764
//// the original copyright notice and the associated disclaimer. ////
1765
////                                                              ////
1766
//// This source file is free software; you can redistribute it   ////
1767
//// and/or modify it under the terms of the GNU Lesser General   ////
1768
//// Public License as published by the Free Software Foundation; ////
1769
//// either version 2.1 of the License, or (at your option) any   ////
1770
//// later version.                                               ////
1771
////                                                              ////
1772
//// This source is distributed in the hope that it will be       ////
1773
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1774
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1775
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1776
//// details.                                                     ////
1777
////                                                              ////
1778
//// You should have received a copy of the GNU Lesser General    ////
1779
//// Public License along with this source; if not, download it   ////
1780
//// from http://www.opencores.org/lgpl.shtml                     ////
1781
////                                                              ////
1782
//////////////////////////////////////////////////////////////////////
1783 22 unneback
 
1784
// LFSR counter
1785 27 unneback
module vl_cnt_lfsr_ce_q ( cke, q, rst, clk);
1786
 
1787
   parameter length = 4;
1788
   input cke;
1789
   output [length:1] q;
1790
   input rst;
1791
   input clk;
1792
 
1793
   parameter clear_value = 0;
1794
   parameter set_value = 1;
1795
   parameter wrap_value = 8;
1796
   parameter level1_value = 15;
1797
 
1798
   reg  [length:1] qi;
1799
   reg lfsr_fb;
1800
   wire [length:1] q_next;
1801
   reg [32:1] polynom;
1802
   integer i;
1803
 
1804
   always @ (qi)
1805
   begin
1806
        case (length)
1807
         2: polynom = 32'b11;                               // 0x3
1808
         3: polynom = 32'b110;                              // 0x6
1809
         4: polynom = 32'b1100;                             // 0xC
1810
         5: polynom = 32'b10100;                            // 0x14
1811
         6: polynom = 32'b110000;                           // 0x30
1812
         7: polynom = 32'b1100000;                          // 0x60
1813
         8: polynom = 32'b10111000;                         // 0xb8
1814
         9: polynom = 32'b100010000;                        // 0x110
1815
        10: polynom = 32'b1001000000;                       // 0x240
1816
        11: polynom = 32'b10100000000;                      // 0x500
1817
        12: polynom = 32'b100000101001;                     // 0x829
1818
        13: polynom = 32'b1000000001100;                    // 0x100C
1819
        14: polynom = 32'b10000000010101;                   // 0x2015
1820
        15: polynom = 32'b110000000000000;                  // 0x6000
1821
        16: polynom = 32'b1101000000001000;                 // 0xD008
1822
        17: polynom = 32'b10010000000000000;                // 0x12000
1823
        18: polynom = 32'b100000010000000000;               // 0x20400
1824
        19: polynom = 32'b1000000000000100011;              // 0x40023
1825
        20: polynom = 32'b10000010000000000000;             // 0x82000
1826
        21: polynom = 32'b101000000000000000000;            // 0x140000
1827
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1828
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1829
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1830
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1831
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1832
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1833
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1834
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1835
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1836
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1837
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1838
        default: polynom = 32'b0;
1839
        endcase
1840
        lfsr_fb = qi[length];
1841
        for (i=length-1; i>=1; i=i-1) begin
1842
            if (polynom[i])
1843
                lfsr_fb = lfsr_fb  ~^ qi[i];
1844
        end
1845
    end
1846
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1847
 
1848
   always @ (posedge clk or posedge rst)
1849
     if (rst)
1850
       qi <= {length{1'b0}};
1851
     else
1852
     if (cke)
1853
       qi <= q_next;
1854
 
1855
   assign q = qi;
1856
 
1857
endmodule
1858
//////////////////////////////////////////////////////////////////////
1859
////                                                              ////
1860
////  Versatile counter                                           ////
1861
////                                                              ////
1862
////  Description                                                 ////
1863
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1864
////  counter                                                     ////
1865
////                                                              ////
1866
////  To Do:                                                      ////
1867
////   - add LFSR with more taps                                  ////
1868
////                                                              ////
1869
////  Author(s):                                                  ////
1870
////      - Michael Unneback, unneback@opencores.org              ////
1871
////        ORSoC AB                                              ////
1872
////                                                              ////
1873
//////////////////////////////////////////////////////////////////////
1874
////                                                              ////
1875
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1876
////                                                              ////
1877
//// This source file may be used and distributed without         ////
1878
//// restriction provided that this copyright statement is not    ////
1879
//// removed from the file and that any derivative work contains  ////
1880
//// the original copyright notice and the associated disclaimer. ////
1881
////                                                              ////
1882
//// This source file is free software; you can redistribute it   ////
1883
//// and/or modify it under the terms of the GNU Lesser General   ////
1884
//// Public License as published by the Free Software Foundation; ////
1885
//// either version 2.1 of the License, or (at your option) any   ////
1886
//// later version.                                               ////
1887
////                                                              ////
1888
//// This source is distributed in the hope that it will be       ////
1889
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1890
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1891
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1892
//// details.                                                     ////
1893
////                                                              ////
1894
//// You should have received a copy of the GNU Lesser General    ////
1895
//// Public License along with this source; if not, download it   ////
1896
//// from http://www.opencores.org/lgpl.shtml                     ////
1897
////                                                              ////
1898
//////////////////////////////////////////////////////////////////////
1899
 
1900
// LFSR counter
1901
module vl_cnt_lfsr_ce_clear_q ( clear, cke, q, rst, clk);
1902
 
1903
   parameter length = 4;
1904
   input clear;
1905
   input cke;
1906
   output [length:1] q;
1907
   input rst;
1908
   input clk;
1909
 
1910
   parameter clear_value = 0;
1911
   parameter set_value = 1;
1912
   parameter wrap_value = 8;
1913
   parameter level1_value = 15;
1914
 
1915
   reg  [length:1] qi;
1916
   reg lfsr_fb;
1917
   wire [length:1] q_next;
1918
   reg [32:1] polynom;
1919
   integer i;
1920
 
1921
   always @ (qi)
1922
   begin
1923
        case (length)
1924
         2: polynom = 32'b11;                               // 0x3
1925
         3: polynom = 32'b110;                              // 0x6
1926
         4: polynom = 32'b1100;                             // 0xC
1927
         5: polynom = 32'b10100;                            // 0x14
1928
         6: polynom = 32'b110000;                           // 0x30
1929
         7: polynom = 32'b1100000;                          // 0x60
1930
         8: polynom = 32'b10111000;                         // 0xb8
1931
         9: polynom = 32'b100010000;                        // 0x110
1932
        10: polynom = 32'b1001000000;                       // 0x240
1933
        11: polynom = 32'b10100000000;                      // 0x500
1934
        12: polynom = 32'b100000101001;                     // 0x829
1935
        13: polynom = 32'b1000000001100;                    // 0x100C
1936
        14: polynom = 32'b10000000010101;                   // 0x2015
1937
        15: polynom = 32'b110000000000000;                  // 0x6000
1938
        16: polynom = 32'b1101000000001000;                 // 0xD008
1939
        17: polynom = 32'b10010000000000000;                // 0x12000
1940
        18: polynom = 32'b100000010000000000;               // 0x20400
1941
        19: polynom = 32'b1000000000000100011;              // 0x40023
1942
        20: polynom = 32'b10000010000000000000;             // 0x82000
1943
        21: polynom = 32'b101000000000000000000;            // 0x140000
1944
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1945
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1946
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1947
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1948
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1949
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1950
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1951
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1952
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1953
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1954
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1955
        default: polynom = 32'b0;
1956
        endcase
1957
        lfsr_fb = qi[length];
1958
        for (i=length-1; i>=1; i=i-1) begin
1959
            if (polynom[i])
1960
                lfsr_fb = lfsr_fb  ~^ qi[i];
1961
        end
1962
    end
1963
   assign q_next =  clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1964
 
1965
   always @ (posedge clk or posedge rst)
1966
     if (rst)
1967
       qi <= {length{1'b0}};
1968
     else
1969
     if (cke)
1970
       qi <= q_next;
1971
 
1972
   assign q = qi;
1973
 
1974
endmodule
1975
//////////////////////////////////////////////////////////////////////
1976
////                                                              ////
1977
////  Versatile counter                                           ////
1978
////                                                              ////
1979
////  Description                                                 ////
1980
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1981
////  counter                                                     ////
1982
////                                                              ////
1983
////  To Do:                                                      ////
1984
////   - add LFSR with more taps                                  ////
1985
////                                                              ////
1986
////  Author(s):                                                  ////
1987
////      - Michael Unneback, unneback@opencores.org              ////
1988
////        ORSoC AB                                              ////
1989
////                                                              ////
1990
//////////////////////////////////////////////////////////////////////
1991
////                                                              ////
1992
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1993
////                                                              ////
1994
//// This source file may be used and distributed without         ////
1995
//// restriction provided that this copyright statement is not    ////
1996
//// removed from the file and that any derivative work contains  ////
1997
//// the original copyright notice and the associated disclaimer. ////
1998
////                                                              ////
1999
//// This source file is free software; you can redistribute it   ////
2000
//// and/or modify it under the terms of the GNU Lesser General   ////
2001
//// Public License as published by the Free Software Foundation; ////
2002
//// either version 2.1 of the License, or (at your option) any   ////
2003
//// later version.                                               ////
2004
////                                                              ////
2005
//// This source is distributed in the hope that it will be       ////
2006
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2007
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2008
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2009
//// details.                                                     ////
2010
////                                                              ////
2011
//// You should have received a copy of the GNU Lesser General    ////
2012
//// Public License along with this source; if not, download it   ////
2013
//// from http://www.opencores.org/lgpl.shtml                     ////
2014
////                                                              ////
2015
//////////////////////////////////////////////////////////////////////
2016
 
2017
// LFSR counter
2018 22 unneback
module vl_cnt_lfsr_ce_q_zq ( cke, q, zq, rst, clk);
2019
 
2020
   parameter length = 4;
2021
   input cke;
2022
   output [length:1] q;
2023
   output reg zq;
2024
   input rst;
2025
   input clk;
2026
 
2027
   parameter clear_value = 0;
2028
   parameter set_value = 1;
2029
   parameter wrap_value = 8;
2030
   parameter level1_value = 15;
2031
 
2032
   reg  [length:1] qi;
2033
   reg lfsr_fb;
2034
   wire [length:1] q_next;
2035
   reg [32:1] polynom;
2036
   integer i;
2037
 
2038
   always @ (qi)
2039
   begin
2040
        case (length)
2041
         2: polynom = 32'b11;                               // 0x3
2042
         3: polynom = 32'b110;                              // 0x6
2043
         4: polynom = 32'b1100;                             // 0xC
2044
         5: polynom = 32'b10100;                            // 0x14
2045
         6: polynom = 32'b110000;                           // 0x30
2046
         7: polynom = 32'b1100000;                          // 0x60
2047
         8: polynom = 32'b10111000;                         // 0xb8
2048
         9: polynom = 32'b100010000;                        // 0x110
2049
        10: polynom = 32'b1001000000;                       // 0x240
2050
        11: polynom = 32'b10100000000;                      // 0x500
2051
        12: polynom = 32'b100000101001;                     // 0x829
2052
        13: polynom = 32'b1000000001100;                    // 0x100C
2053
        14: polynom = 32'b10000000010101;                   // 0x2015
2054
        15: polynom = 32'b110000000000000;                  // 0x6000
2055
        16: polynom = 32'b1101000000001000;                 // 0xD008
2056
        17: polynom = 32'b10010000000000000;                // 0x12000
2057
        18: polynom = 32'b100000010000000000;               // 0x20400
2058
        19: polynom = 32'b1000000000000100011;              // 0x40023
2059
        20: polynom = 32'b10000010000000000000;             // 0x82000
2060
        21: polynom = 32'b101000000000000000000;            // 0x140000
2061
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2062
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2063
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2064
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2065
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2066
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2067
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2068
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2069
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2070
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2071
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2072
        default: polynom = 32'b0;
2073
        endcase
2074
        lfsr_fb = qi[length];
2075
        for (i=length-1; i>=1; i=i-1) begin
2076
            if (polynom[i])
2077
                lfsr_fb = lfsr_fb  ~^ qi[i];
2078
        end
2079
    end
2080
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2081
 
2082
   always @ (posedge clk or posedge rst)
2083
     if (rst)
2084
       qi <= {length{1'b0}};
2085
     else
2086
     if (cke)
2087
       qi <= q_next;
2088
 
2089
   assign q = qi;
2090
 
2091
 
2092
   always @ (posedge clk or posedge rst)
2093
     if (rst)
2094
       zq <= 1'b1;
2095
     else
2096
     if (cke)
2097
       zq <= q_next == {length{1'b0}};
2098
endmodule
2099
//////////////////////////////////////////////////////////////////////
2100
////                                                              ////
2101
////  Versatile counter                                           ////
2102
////                                                              ////
2103
////  Description                                                 ////
2104
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2105
////  counter                                                     ////
2106
////                                                              ////
2107
////  To Do:                                                      ////
2108
////   - add LFSR with more taps                                  ////
2109
////                                                              ////
2110
////  Author(s):                                                  ////
2111
////      - Michael Unneback, unneback@opencores.org              ////
2112
////        ORSoC AB                                              ////
2113
////                                                              ////
2114
//////////////////////////////////////////////////////////////////////
2115
////                                                              ////
2116
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2117
////                                                              ////
2118
//// This source file may be used and distributed without         ////
2119
//// restriction provided that this copyright statement is not    ////
2120
//// removed from the file and that any derivative work contains  ////
2121
//// the original copyright notice and the associated disclaimer. ////
2122
////                                                              ////
2123
//// This source file is free software; you can redistribute it   ////
2124
//// and/or modify it under the terms of the GNU Lesser General   ////
2125
//// Public License as published by the Free Software Foundation; ////
2126
//// either version 2.1 of the License, or (at your option) any   ////
2127
//// later version.                                               ////
2128
////                                                              ////
2129
//// This source is distributed in the hope that it will be       ////
2130
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2131
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2132
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2133
//// details.                                                     ////
2134
////                                                              ////
2135
//// You should have received a copy of the GNU Lesser General    ////
2136
//// Public License along with this source; if not, download it   ////
2137
//// from http://www.opencores.org/lgpl.shtml                     ////
2138
////                                                              ////
2139
//////////////////////////////////////////////////////////////////////
2140 6 unneback
 
2141
// LFSR counter
2142 18 unneback
module vl_cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk);
2143 6 unneback
 
2144
   parameter length = 4;
2145
   input cke;
2146
   input rew;
2147
   output reg level1;
2148
   input rst;
2149
   input clk;
2150
 
2151
   parameter clear_value = 0;
2152
   parameter set_value = 1;
2153
   parameter wrap_value = 8;
2154
   parameter level1_value = 15;
2155
 
2156 29 unneback
   wire clear;
2157 30 unneback
   assign clear = 1'b0;
2158 6 unneback
   reg  [length:1] qi;
2159
   reg lfsr_fb, lfsr_fb_rew;
2160
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2161
   reg [32:1] polynom_rew;
2162
   integer j;
2163
   reg [32:1] polynom;
2164
   integer i;
2165
 
2166
   always @ (qi)
2167
   begin
2168
        case (length)
2169
         2: polynom = 32'b11;                               // 0x3
2170
         3: polynom = 32'b110;                              // 0x6
2171
         4: polynom = 32'b1100;                             // 0xC
2172
         5: polynom = 32'b10100;                            // 0x14
2173
         6: polynom = 32'b110000;                           // 0x30
2174
         7: polynom = 32'b1100000;                          // 0x60
2175
         8: polynom = 32'b10111000;                         // 0xb8
2176
         9: polynom = 32'b100010000;                        // 0x110
2177
        10: polynom = 32'b1001000000;                       // 0x240
2178
        11: polynom = 32'b10100000000;                      // 0x500
2179
        12: polynom = 32'b100000101001;                     // 0x829
2180
        13: polynom = 32'b1000000001100;                    // 0x100C
2181
        14: polynom = 32'b10000000010101;                   // 0x2015
2182
        15: polynom = 32'b110000000000000;                  // 0x6000
2183
        16: polynom = 32'b1101000000001000;                 // 0xD008
2184
        17: polynom = 32'b10010000000000000;                // 0x12000
2185
        18: polynom = 32'b100000010000000000;               // 0x20400
2186
        19: polynom = 32'b1000000000000100011;              // 0x40023
2187
        20: polynom = 32'b10000010000000000000;             // 0x82000
2188
        21: polynom = 32'b101000000000000000000;            // 0x140000
2189
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2190
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2191
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2192
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2193
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2194
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2195
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2196
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2197
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2198
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2199
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2200
        default: polynom = 32'b0;
2201
        endcase
2202
        lfsr_fb = qi[length];
2203
        for (i=length-1; i>=1; i=i-1) begin
2204
            if (polynom[i])
2205
                lfsr_fb = lfsr_fb  ~^ qi[i];
2206
        end
2207
    end
2208
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2209
   always @ (qi)
2210
   begin
2211
        case (length)
2212
         2: polynom_rew = 32'b11;
2213
         3: polynom_rew = 32'b110;
2214
         4: polynom_rew = 32'b1100;
2215
         5: polynom_rew = 32'b10100;
2216
         6: polynom_rew = 32'b110000;
2217
         7: polynom_rew = 32'b1100000;
2218
         8: polynom_rew = 32'b10111000;
2219
         9: polynom_rew = 32'b100010000;
2220
        10: polynom_rew = 32'b1001000000;
2221
        11: polynom_rew = 32'b10100000000;
2222
        12: polynom_rew = 32'b100000101001;
2223
        13: polynom_rew = 32'b1000000001100;
2224
        14: polynom_rew = 32'b10000000010101;
2225
        15: polynom_rew = 32'b110000000000000;
2226
        16: polynom_rew = 32'b1101000000001000;
2227
        17: polynom_rew = 32'b10010000000000000;
2228
        18: polynom_rew = 32'b100000010000000000;
2229
        19: polynom_rew = 32'b1000000000000100011;
2230
        20: polynom_rew = 32'b10000010000000000000;
2231
        21: polynom_rew = 32'b101000000000000000000;
2232
        22: polynom_rew = 32'b1100000000000000000000;
2233
        23: polynom_rew = 32'b10000100000000000000000;
2234
        24: polynom_rew = 32'b111000010000000000000000;
2235
        25: polynom_rew = 32'b1001000000000000000000000;
2236
        26: polynom_rew = 32'b10000000000000000000100011;
2237
        27: polynom_rew = 32'b100000000000000000000010011;
2238
        28: polynom_rew = 32'b1100100000000000000000000000;
2239
        29: polynom_rew = 32'b10100000000000000000000000000;
2240
        30: polynom_rew = 32'b100000000000000000000000101001;
2241
        31: polynom_rew = 32'b1001000000000000000000000000000;
2242
        32: polynom_rew = 32'b10000000001000000000000000000011;
2243
        default: polynom_rew = 32'b0;
2244
        endcase
2245
        // rotate left
2246
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
2247
        lfsr_fb_rew = qi[length];
2248
        for (i=length-1; i>=1; i=i-1) begin
2249
            if (polynom_rew[i])
2250
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
2251
        end
2252
    end
2253
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
2254
   assign q_next = rew ? q_next_rew : q_next_fw;
2255
 
2256
   always @ (posedge clk or posedge rst)
2257
     if (rst)
2258
       qi <= {length{1'b0}};
2259
     else
2260
     if (cke)
2261
       qi <= q_next;
2262
 
2263
 
2264
 
2265
    always @ (posedge clk or posedge rst)
2266
    if (rst)
2267
        level1 <= 1'b0;
2268
    else
2269
    if (cke)
2270 29 unneback
    if (clear)
2271
        level1 <= 1'b0;
2272
    else if (q_next == level1_value)
2273 6 unneback
        level1 <= 1'b1;
2274
    else if (qi == level1_value & rew)
2275
        level1 <= 1'b0;
2276
endmodule
2277
//////////////////////////////////////////////////////////////////////
2278
////                                                              ////
2279
////  Versatile counter                                           ////
2280
////                                                              ////
2281
////  Description                                                 ////
2282
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2283
////  counter                                                     ////
2284
////                                                              ////
2285
////  To Do:                                                      ////
2286
////   - add LFSR with more taps                                  ////
2287
////                                                              ////
2288
////  Author(s):                                                  ////
2289
////      - Michael Unneback, unneback@opencores.org              ////
2290
////        ORSoC AB                                              ////
2291
////                                                              ////
2292
//////////////////////////////////////////////////////////////////////
2293
////                                                              ////
2294
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2295
////                                                              ////
2296
//// This source file may be used and distributed without         ////
2297
//// restriction provided that this copyright statement is not    ////
2298
//// removed from the file and that any derivative work contains  ////
2299
//// the original copyright notice and the associated disclaimer. ////
2300
////                                                              ////
2301
//// This source file is free software; you can redistribute it   ////
2302
//// and/or modify it under the terms of the GNU Lesser General   ////
2303
//// Public License as published by the Free Software Foundation; ////
2304
//// either version 2.1 of the License, or (at your option) any   ////
2305
//// later version.                                               ////
2306
////                                                              ////
2307
//// This source is distributed in the hope that it will be       ////
2308
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2309
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2310
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2311
//// details.                                                     ////
2312
////                                                              ////
2313
//// You should have received a copy of the GNU Lesser General    ////
2314
//// Public License along with this source; if not, download it   ////
2315
//// from http://www.opencores.org/lgpl.shtml                     ////
2316
////                                                              ////
2317
//////////////////////////////////////////////////////////////////////
2318
 
2319
// GRAY counter
2320 18 unneback
module vl_cnt_gray ( q, rst, clk);
2321 6 unneback
 
2322
   parameter length = 4;
2323
   output reg [length:1] q;
2324
   input rst;
2325
   input clk;
2326
 
2327
   parameter clear_value = 0;
2328
   parameter set_value = 1;
2329
   parameter wrap_value = 8;
2330
   parameter level1_value = 15;
2331
 
2332
   reg  [length:1] qi;
2333
   wire [length:1] q_next;
2334
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2335
 
2336
   always @ (posedge clk or posedge rst)
2337
     if (rst)
2338
       qi <= {length{1'b0}};
2339
     else
2340
       qi <= q_next;
2341
 
2342
   always @ (posedge clk or posedge rst)
2343
     if (rst)
2344
       q <= {length{1'b0}};
2345
     else
2346
         q <= (q_next>>1) ^ q_next;
2347
 
2348
endmodule
2349
//////////////////////////////////////////////////////////////////////
2350
////                                                              ////
2351
////  Versatile counter                                           ////
2352
////                                                              ////
2353
////  Description                                                 ////
2354
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2355
////  counter                                                     ////
2356
////                                                              ////
2357
////  To Do:                                                      ////
2358
////   - add LFSR with more taps                                  ////
2359
////                                                              ////
2360
////  Author(s):                                                  ////
2361
////      - Michael Unneback, unneback@opencores.org              ////
2362
////        ORSoC AB                                              ////
2363
////                                                              ////
2364
//////////////////////////////////////////////////////////////////////
2365
////                                                              ////
2366
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2367
////                                                              ////
2368
//// This source file may be used and distributed without         ////
2369
//// restriction provided that this copyright statement is not    ////
2370
//// removed from the file and that any derivative work contains  ////
2371
//// the original copyright notice and the associated disclaimer. ////
2372
////                                                              ////
2373
//// This source file is free software; you can redistribute it   ////
2374
//// and/or modify it under the terms of the GNU Lesser General   ////
2375
//// Public License as published by the Free Software Foundation; ////
2376
//// either version 2.1 of the License, or (at your option) any   ////
2377
//// later version.                                               ////
2378
////                                                              ////
2379
//// This source is distributed in the hope that it will be       ////
2380
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2381
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2382
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2383
//// details.                                                     ////
2384
////                                                              ////
2385
//// You should have received a copy of the GNU Lesser General    ////
2386
//// Public License along with this source; if not, download it   ////
2387
//// from http://www.opencores.org/lgpl.shtml                     ////
2388
////                                                              ////
2389
//////////////////////////////////////////////////////////////////////
2390
 
2391
// GRAY counter
2392 18 unneback
module vl_cnt_gray_ce ( cke, q, rst, clk);
2393 6 unneback
 
2394
   parameter length = 4;
2395
   input cke;
2396
   output reg [length:1] q;
2397
   input rst;
2398
   input clk;
2399
 
2400
   parameter clear_value = 0;
2401
   parameter set_value = 1;
2402
   parameter wrap_value = 8;
2403
   parameter level1_value = 15;
2404
 
2405
   reg  [length:1] qi;
2406
   wire [length:1] q_next;
2407
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2408
 
2409
   always @ (posedge clk or posedge rst)
2410
     if (rst)
2411
       qi <= {length{1'b0}};
2412
     else
2413
     if (cke)
2414
       qi <= q_next;
2415
 
2416
   always @ (posedge clk or posedge rst)
2417
     if (rst)
2418
       q <= {length{1'b0}};
2419
     else
2420
       if (cke)
2421
         q <= (q_next>>1) ^ q_next;
2422
 
2423
endmodule
2424
//////////////////////////////////////////////////////////////////////
2425
////                                                              ////
2426
////  Versatile counter                                           ////
2427
////                                                              ////
2428
////  Description                                                 ////
2429
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2430
////  counter                                                     ////
2431
////                                                              ////
2432
////  To Do:                                                      ////
2433
////   - add LFSR with more taps                                  ////
2434
////                                                              ////
2435
////  Author(s):                                                  ////
2436
////      - Michael Unneback, unneback@opencores.org              ////
2437
////        ORSoC AB                                              ////
2438
////                                                              ////
2439
//////////////////////////////////////////////////////////////////////
2440
////                                                              ////
2441
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2442
////                                                              ////
2443
//// This source file may be used and distributed without         ////
2444
//// restriction provided that this copyright statement is not    ////
2445
//// removed from the file and that any derivative work contains  ////
2446
//// the original copyright notice and the associated disclaimer. ////
2447
////                                                              ////
2448
//// This source file is free software; you can redistribute it   ////
2449
//// and/or modify it under the terms of the GNU Lesser General   ////
2450
//// Public License as published by the Free Software Foundation; ////
2451
//// either version 2.1 of the License, or (at your option) any   ////
2452
//// later version.                                               ////
2453
////                                                              ////
2454
//// This source is distributed in the hope that it will be       ////
2455
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2456
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2457
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2458
//// details.                                                     ////
2459
////                                                              ////
2460
//// You should have received a copy of the GNU Lesser General    ////
2461
//// Public License along with this source; if not, download it   ////
2462
//// from http://www.opencores.org/lgpl.shtml                     ////
2463
////                                                              ////
2464
//////////////////////////////////////////////////////////////////////
2465
 
2466
// GRAY counter
2467 18 unneback
module vl_cnt_gray_ce_bin ( cke, q, q_bin, rst, clk);
2468 6 unneback
 
2469
   parameter length = 4;
2470
   input cke;
2471
   output reg [length:1] q;
2472
   output [length:1] q_bin;
2473
   input rst;
2474
   input clk;
2475
 
2476
   parameter clear_value = 0;
2477
   parameter set_value = 1;
2478
   parameter wrap_value = 8;
2479
   parameter level1_value = 15;
2480
 
2481
   reg  [length:1] qi;
2482
   wire [length:1] q_next;
2483
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2484
 
2485
   always @ (posedge clk or posedge rst)
2486
     if (rst)
2487
       qi <= {length{1'b0}};
2488
     else
2489
     if (cke)
2490
       qi <= q_next;
2491
 
2492
   always @ (posedge clk or posedge rst)
2493
     if (rst)
2494
       q <= {length{1'b0}};
2495
     else
2496
       if (cke)
2497
         q <= (q_next>>1) ^ q_next;
2498
 
2499
   assign q_bin = qi;
2500
 
2501
endmodule
2502
//////////////////////////////////////////////////////////////////////
2503
////                                                              ////
2504
////  Versatile library, counters                                 ////
2505
////                                                              ////
2506
////  Description                                                 ////
2507
////  counters                                                    ////
2508
////                                                              ////
2509
////                                                              ////
2510
////  To Do:                                                      ////
2511
////   - add more counters                                        ////
2512
////                                                              ////
2513
////  Author(s):                                                  ////
2514
////      - Michael Unneback, unneback@opencores.org              ////
2515
////        ORSoC AB                                              ////
2516
////                                                              ////
2517
//////////////////////////////////////////////////////////////////////
2518
////                                                              ////
2519
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2520
////                                                              ////
2521
//// This source file may be used and distributed without         ////
2522
//// restriction provided that this copyright statement is not    ////
2523
//// removed from the file and that any derivative work contains  ////
2524
//// the original copyright notice and the associated disclaimer. ////
2525
////                                                              ////
2526
//// This source file is free software; you can redistribute it   ////
2527
//// and/or modify it under the terms of the GNU Lesser General   ////
2528
//// Public License as published by the Free Software Foundation; ////
2529
//// either version 2.1 of the License, or (at your option) any   ////
2530
//// later version.                                               ////
2531
////                                                              ////
2532
//// This source is distributed in the hope that it will be       ////
2533
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2534
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2535
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2536
//// details.                                                     ////
2537
////                                                              ////
2538
//// You should have received a copy of the GNU Lesser General    ////
2539
//// Public License along with this source; if not, download it   ////
2540
//// from http://www.opencores.org/lgpl.shtml                     ////
2541
////                                                              ////
2542
//////////////////////////////////////////////////////////////////////
2543
 
2544 18 unneback
module vl_cnt_shreg_wrap ( q, rst, clk);
2545 6 unneback
 
2546
   parameter length = 4;
2547
   output reg [0:length-1] q;
2548
   input rst;
2549
   input clk;
2550
 
2551
    always @ (posedge clk or posedge rst)
2552
    if (rst)
2553
        q <= {1'b1,{length-1{1'b0}}};
2554
    else
2555
        q <= {q[length-1],q[0:length-2]};
2556
 
2557
endmodule
2558
 
2559 18 unneback
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
2560 6 unneback
 
2561
   parameter length = 4;
2562
   input cke;
2563
   output reg [0:length-1] q;
2564
   input rst;
2565
   input clk;
2566
 
2567
    always @ (posedge clk or posedge rst)
2568
    if (rst)
2569
        q <= {1'b1,{length-1{1'b0}}};
2570
    else
2571
        if (cke)
2572
            q <= {q[length-1],q[0:length-2]};
2573
 
2574
endmodule
2575
 
2576 18 unneback
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
2577 6 unneback
 
2578
   parameter length = 4;
2579
   input cke, clear;
2580
   output reg [0:length-1] q;
2581
   input rst;
2582
   input clk;
2583
 
2584
    always @ (posedge clk or posedge rst)
2585
    if (rst)
2586
        q <= {1'b1,{length-1{1'b0}}};
2587
    else
2588
        if (cke)
2589
            if (clear)
2590
                q <= {1'b1,{length-1{1'b0}}};
2591
            else
2592
                q <= q >> 1;
2593
 
2594
endmodule
2595
 
2596 18 unneback
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
2597 6 unneback
 
2598
   parameter length = 4;
2599
   input cke, clear;
2600
   output reg [0:length-1] q;
2601
   input rst;
2602
   input clk;
2603
 
2604
    always @ (posedge clk or posedge rst)
2605
    if (rst)
2606
        q <= {1'b1,{length-1{1'b0}}};
2607
    else
2608
        if (cke)
2609
            if (clear)
2610
                q <= {1'b1,{length-1{1'b0}}};
2611
            else
2612
            q <= {q[length-1],q[0:length-2]};
2613
 
2614
endmodule
2615
//////////////////////////////////////////////////////////////////////
2616
////                                                              ////
2617
////  Versatile library, memories                                 ////
2618
////                                                              ////
2619
////  Description                                                 ////
2620
////  memories                                                    ////
2621
////                                                              ////
2622
////                                                              ////
2623
////  To Do:                                                      ////
2624
////   - add more memory types                                    ////
2625
////                                                              ////
2626
////  Author(s):                                                  ////
2627
////      - Michael Unneback, unneback@opencores.org              ////
2628
////        ORSoC AB                                              ////
2629
////                                                              ////
2630
//////////////////////////////////////////////////////////////////////
2631
////                                                              ////
2632
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2633
////                                                              ////
2634
//// This source file may be used and distributed without         ////
2635
//// restriction provided that this copyright statement is not    ////
2636
//// removed from the file and that any derivative work contains  ////
2637
//// the original copyright notice and the associated disclaimer. ////
2638
////                                                              ////
2639
//// This source file is free software; you can redistribute it   ////
2640
//// and/or modify it under the terms of the GNU Lesser General   ////
2641
//// Public License as published by the Free Software Foundation; ////
2642
//// either version 2.1 of the License, or (at your option) any   ////
2643
//// later version.                                               ////
2644
////                                                              ////
2645
//// This source is distributed in the hope that it will be       ////
2646
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2647
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2648
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2649
//// details.                                                     ////
2650
////                                                              ////
2651
//// You should have received a copy of the GNU Lesser General    ////
2652
//// Public License along with this source; if not, download it   ////
2653
//// from http://www.opencores.org/lgpl.shtml                     ////
2654
////                                                              ////
2655
//////////////////////////////////////////////////////////////////////
2656
 
2657
/// ROM
2658
 
2659 7 unneback
module vl_rom_init ( adr, q, clk);
2660
   parameter data_width = 32;
2661
   parameter addr_width = 8;
2662
   input [(addr_width-1):0]       adr;
2663
   output reg [(data_width-1):0] q;
2664
   input                         clk;
2665
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
2666
   parameter memory_file = "vl_rom.vmem";
2667
   initial
2668
     begin
2669
        $readmemh(memory_file, rom);
2670
     end
2671
 
2672
   always @ (posedge clk)
2673
     q <= rom[adr];
2674 6 unneback
 
2675 7 unneback
endmodule
2676
 
2677 14 unneback
/*
2678 7 unneback
module vl_rom ( adr, q, clk);
2679
 
2680 6 unneback
parameter data_width = 32;
2681
parameter addr_width = 4;
2682
 
2683
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
2684
    {32'h18000000},
2685
    {32'hA8200000},
2686
    {32'hA8200000},
2687
    {32'hA8200000},
2688
    {32'h44003000},
2689
    {32'h15000000},
2690
    {32'h15000000},
2691
    {32'h15000000},
2692
    {32'h15000000},
2693
    {32'h15000000},
2694
    {32'h15000000},
2695
    {32'h15000000},
2696
    {32'h15000000},
2697
    {32'h15000000},
2698
    {32'h15000000},
2699
    {32'h15000000}};
2700
 
2701 7 unneback
input [addr_width-1:0] adr;
2702 6 unneback
output reg [data_width-1:0] q;
2703
input clk;
2704
 
2705
always @ (posedge clk)
2706 7 unneback
    q <= data[adr];
2707 6 unneback
 
2708
endmodule
2709 14 unneback
*/
2710 6 unneback
// Single port RAM
2711
 
2712
module vl_ram ( d, adr, we, q, clk);
2713
   parameter data_width = 32;
2714
   parameter addr_width = 8;
2715
   input [(data_width-1):0]      d;
2716
   input [(addr_width-1):0]       adr;
2717
   input                         we;
2718 7 unneback
   output reg [(data_width-1):0] q;
2719 6 unneback
   input                         clk;
2720
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
2721 7 unneback
   parameter init = 0;
2722
   parameter memory_file = "vl_ram.vmem";
2723
   generate if (init) begin : init_mem
2724
   initial
2725
     begin
2726
        $readmemh(memory_file, ram);
2727
     end
2728
   end
2729
   endgenerate
2730
 
2731 6 unneback
   always @ (posedge clk)
2732
   begin
2733
   if (we)
2734
     ram[adr] <= d;
2735
   q <= ram[adr];
2736
   end
2737
 
2738
endmodule
2739
 
2740 7 unneback
module vl_ram_be ( d, adr, be, we, q, clk);
2741
   parameter data_width = 32;
2742
   parameter addr_width = 8;
2743
   input [(data_width-1):0]      d;
2744
   input [(addr_width-1):0]       adr;
2745
   input [(addr_width/4)-1:0]    be;
2746
   input                         we;
2747
   output reg [(data_width-1):0] q;
2748
   input                         clk;
2749
 
2750
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
2751
 
2752
   parameter init = 0;
2753
   parameter memory_file = "vl_ram.vmem";
2754
   generate if (init) begin : init_mem
2755
   initial
2756
     begin
2757
        $readmemh(memory_file, ram);
2758
     end
2759
   end
2760
   endgenerate
2761
 
2762
   genvar i;
2763
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
2764
      always @ (posedge clk)
2765
      if (we & be[i])
2766
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
2767
   end
2768
   endgenerate
2769
 
2770
   always @ (posedge clk)
2771
      q <= ram[adr];
2772
 
2773
endmodule
2774
 
2775
 
2776 6 unneback
// Dual port RAM
2777
 
2778
// ACTEL FPGA should not use logic to handle rw collision
2779
`ifdef ACTEL
2780
        `define SYN /*synthesis syn_ramstyle = "no_rw_check"*/
2781
`else
2782
        `define SYN
2783
`endif
2784
 
2785 7 unneback
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
2786 6 unneback
   parameter data_width = 32;
2787
   parameter addr_width = 8;
2788
   input [(data_width-1):0]      d_a;
2789
   input [(addr_width-1):0]       adr_a;
2790
   input [(addr_width-1):0]       adr_b;
2791
   input                         we_a;
2792
   output [(data_width-1):0]      q_b;
2793
   input                         clk_a, clk_b;
2794
   reg [(addr_width-1):0]         adr_b_reg;
2795
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
2796 7 unneback
 
2797
   parameter init = 0;
2798
   parameter memory_file = "vl_ram.vmem";
2799
   generate if (init) begin : init_mem
2800
   initial
2801
     begin
2802
        $readmemh(memory_file, ram);
2803
     end
2804
   end
2805
   endgenerate
2806
 
2807 6 unneback
   always @ (posedge clk_a)