OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Blame information for rev 32

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 6 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  Versatile library, clock and reset                          ////
4
////                                                              ////
5
////  Description                                                 ////
6
////  Logic related to clock and reset                            ////
7
////                                                              ////
8
////                                                              ////
9
////  To Do:                                                      ////
10
////   - add more different registers                             ////
11
////                                                              ////
12
////  Author(s):                                                  ////
13
////      - Michael Unneback, unneback@opencores.org              ////
14
////        ORSoC AB                                              ////
15
////                                                              ////
16
//////////////////////////////////////////////////////////////////////
17
////                                                              ////
18
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
19
////                                                              ////
20
//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
36
////                                                              ////
37
//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
 
43
// Global buffer
44
// usage:
45
// use to enable global buffers for high fan out signals such as clock and reset
46
 
47
`ifdef ACTEL
48
 
49
`timescale 1 ns/100 ps
50
// Version: 8.4 8.4.0.33
51
module gbuf(GL,CLK);
52
output GL;
53
input  CLK;
54
 
55
    wire GND;
56
 
57
    GND GND_1_net(.Y(GND));
58
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
59
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
60
 
61
endmodule
62
`timescale 1 ns/1 ns
63
module vl_gbuf ( i, o);
64
input i;
65
output o;
66
`ifdef SIM_GBUF
67
assign o=i;
68
`else
69
gbuf gbuf_i0 ( .CLK(i), .GL(o));
70
`endif
71
endmodule
72
`else
73
`ifdef ALTERA
74 21 unneback
//altera
75 6 unneback
`else
76
 
77
`timescale 1 ns/100 ps
78
module vl_gbuf ( i, o);
79
input i;
80
output o;
81
assign o = i;
82
endmodule
83
`endif // ALTERA
84
`endif //ACTEL
85
 
86
// sync reset
87 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
88 6 unneback
// output active high global reset sync with two DFFs 
89
`timescale 1 ns/100 ps
90
module vl_sync_rst ( rst_n_i, rst_o, clk);
91
input rst_n_i, clk;
92
output rst_o;
93 18 unneback
reg [1:0] tmp;
94 6 unneback
always @ (posedge clk or negedge rst_n_i)
95
if (!rst_n_i)
96 17 unneback
        tmp <= 2'b11;
97 6 unneback
else
98 17 unneback
        tmp <= {1'b0,tmp[0]};
99
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
100 6 unneback
endmodule
101
 
102
// vl_pll
103
`ifdef ACTEL
104 32 unneback
///////////////////////////////////////////////////////////////////////////////
105 17 unneback
`timescale 1 ps/1 ps
106 6 unneback
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
107
parameter index = 0;
108
parameter number_of_clk = 1;
109 17 unneback
parameter period_time_0 = 20000;
110
parameter period_time_1 = 20000;
111
parameter period_time_2 = 20000;
112
parameter lock_delay = 2000000;
113 6 unneback
input clk_i, rst_n_i;
114
output lock;
115
output reg [0:number_of_clk-1] clk_o;
116
output [0:number_of_clk-1] rst_o;
117
 
118
`ifdef SIM_PLL
119
 
120
always
121
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
122
 
123
generate if (number_of_clk > 1)
124
always
125
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
126
endgenerate
127
 
128
generate if (number_of_clk > 2)
129
always
130
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
131
endgenerate
132
 
133
genvar i;
134
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
135
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
136
end
137
endgenerate
138
 
139
assign #lock_delay lock = rst_n_i;
140
 
141
endmodule
142
`else
143
generate if (number_of_clk==1 & index==0) begin
144
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
145
end
146
endgenerate // index==0
147
generate if (number_of_clk==1 & index==1) begin
148
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
149
end
150
endgenerate // index==1
151
generate if (number_of_clk==1 & index==2) begin
152
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
153
end
154
endgenerate // index==2
155
generate if (number_of_clk==1 & index==3) begin
156
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
157
end
158
endgenerate // index==0
159
 
160
generate if (number_of_clk==2 & index==0) begin
161
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
162
end
163
endgenerate // index==0
164
generate if (number_of_clk==2 & index==1) begin
165
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
166
end
167
endgenerate // index==1
168
generate if (number_of_clk==2 & index==2) begin
169
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
170
end
171
endgenerate // index==2
172
generate if (number_of_clk==2 & index==3) begin
173
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
174
end
175
endgenerate // index==0
176
 
177
generate if (number_of_clk==3 & index==0) begin
178
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
179
end
180
endgenerate // index==0
181
generate if (number_of_clk==3 & index==1) begin
182
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
183
end
184
endgenerate // index==1
185
generate if (number_of_clk==3 & index==2) begin
186
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
187
end
188
endgenerate // index==2
189
generate if (number_of_clk==3 & index==3) begin
190
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
191
end
192
endgenerate // index==0
193
 
194
genvar i;
195
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
196
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
197
end
198
endgenerate
199
endmodule
200
`endif
201 32 unneback
///////////////////////////////////////////////////////////////////////////////
202 6 unneback
 
203
`else
204
 
205 32 unneback
///////////////////////////////////////////////////////////////////////////////
206 6 unneback
`ifdef ALTERA
207
 
208 32 unneback
`timescale 1 ps/1 ps
209
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
210
parameter index = 0;
211
parameter number_of_clk = 1;
212
parameter period_time_0 = 20000;
213
parameter period_time_1 = 20000;
214
parameter period_time_2 = 20000;
215
parameter period_time_3 = 20000;
216
parameter period_time_4 = 20000;
217
parameter lock_delay = 2000000;
218
input clk_i, rst_n_i;
219
output lock;
220
output reg [0:number_of_clk-1] clk_o;
221
output [0:number_of_clk-1] rst_o;
222
 
223
`ifdef SIM_PLL
224
 
225
always
226
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
227
 
228
generate if (number_of_clk > 1)
229
always
230
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
231
endgenerate
232
 
233
generate if (number_of_clk > 2)
234
always
235
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
236
endgenerate
237
 
238
always
239
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
240
endgenerate
241
 
242
always
243
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
244
endgenerate
245
 
246
genvar i;
247
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
248
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
249
end
250
endgenerate
251
 
252
assign #lock_delay lock = rst_n_i;
253
 
254
endmodule
255 6 unneback
`else
256 32 unneback
generate if (number_of_clk==1 & index==0) begin
257
        pll0 pll_i0 (.areset(1'b1), .inclk(clk_i), .locked(lock), .c0(clk_o[0]));
258
end
259
endgenerate // index==0
260
generate if (number_of_clk==1 & index==1) begin
261
        pll1 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
262
end
263
endgenerate // index==1
264
generate if (number_of_clk==1 & index==2) begin
265
        pll2 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
266
end
267
endgenerate // index==2
268
generate if (number_of_clk==1 & index==3) begin
269
        pll3 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
270
end
271
endgenerate // index==3
272 6 unneback
 
273 32 unneback
generate if (number_of_clk==2 & index==0) begin
274
        pll0 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
275
end
276
endgenerate // index==0
277
generate if (number_of_clk==2 & index==1) begin
278
        pll1 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
279
end
280
endgenerate // index==1
281
generate if (number_of_clk==2 & index==2) begin
282
        pll2 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
283
end
284
endgenerate // index==2
285
generate if (number_of_clk==2 & index==3) begin
286
        pll3 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
287
end
288
endgenerate // index==3
289
 
290
generate if (number_of_clk==3 & index==0) begin
291
        pll0 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
292
end
293
endgenerate // index==0
294
generate if (number_of_clk==3 & index==1) begin
295
        pll1 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
296
end
297
endgenerate // index==1
298
generate if (number_of_clk==3 & index==2) begin
299
        pll2 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
300
end
301
endgenerate // index==2
302
generate if (number_of_clk==3 & index==3) begin
303
        pll3 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
304
end
305
endgenerate // index==3
306
 
307
generate if (number_of_clk==4 & index==0) begin
308
        pll0 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
309
end
310
endgenerate // index==0
311
generate if (number_of_clk==4 & index==1) begin
312
        pll1 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2], .c3(clk_o[3]));
313
end
314
endgenerate // index==1
315
generate if (number_of_clk==4 & index==2) begin
316
        pll2 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2], .c3(clk_o[3]));
317
end
318
endgenerate // index==2
319
generate if (number_of_clk==4 & index==3) begin
320
        pll3 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2], .c3(clk_o[3]));
321
end
322
endgenerate // index==3
323
 
324
generate if (number_of_clk==5 & index==0) begin
325
        pll0 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3], .c4(clk_o[4]));
326
end
327
endgenerate // index==0
328
generate if (number_of_clk==5 & index==1) begin
329
        pll1 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2], .c3(clk_o[3], .c4(clk_o[4]));
330
end
331
endgenerate // index==1
332
generate if (number_of_clk==5 & index==2) begin
333
        pll2 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2], .c3(clk_o[3], .c4(clk_o[4]));
334
end
335
endgenerate // index==2
336
generate if (number_of_clk==5 & index==3) begin
337
        pll3 pll_i0 (.areset(1'b1), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2], .c3(clk_o[3], .c4(clk_o[4]));
338
end
339
endgenerate // index==3
340
 
341
genvar i;
342
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
343
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
344
end
345
endgenerate
346
endmodule
347
`endif
348
///////////////////////////////////////////////////////////////////////////////
349
 
350
`else
351
 
352 6 unneback
// generic PLL
353 17 unneback
`timescale 1 ps/1 ps
354 6 unneback
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
355
parameter index = 0;
356
parameter number_of_clk = 1;
357 17 unneback
parameter period_time_0 = 20000;
358
parameter period_time_1 = 20000;
359
parameter period_time_2 = 20000;
360 6 unneback
parameter lock_delay = 2000;
361
input clk_i, rst_n_i;
362
output lock;
363
output reg [0:number_of_clk-1] clk_o;
364
output [0:number_of_clk-1] rst_o;
365
 
366
always
367
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
368
 
369
generate if (number_of_clk > 1)
370
always
371
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
372
endgenerate
373
 
374
generate if (number_of_clk > 2)
375
always
376
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
377
endgenerate
378
 
379
genvar i;
380
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
381
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
382
end
383
endgenerate
384
 
385
assign #lock_delay lock = rst_n_i;
386
 
387
endmodule
388
 
389
`endif //altera
390 17 unneback
`endif //actel
391
//////////////////////////////////////////////////////////////////////
392 6 unneback
////                                                              ////
393
////  Versatile library, registers                                ////
394
////                                                              ////
395
////  Description                                                 ////
396
////  Different type of registers                                 ////
397
////                                                              ////
398
////                                                              ////
399
////  To Do:                                                      ////
400
////   - add more different registers                             ////
401
////                                                              ////
402
////  Author(s):                                                  ////
403
////      - Michael Unneback, unneback@opencores.org              ////
404
////        ORSoC AB                                              ////
405
////                                                              ////
406
//////////////////////////////////////////////////////////////////////
407
////                                                              ////
408
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
409
////                                                              ////
410
//// This source file may be used and distributed without         ////
411
//// restriction provided that this copyright statement is not    ////
412
//// removed from the file and that any derivative work contains  ////
413
//// the original copyright notice and the associated disclaimer. ////
414
////                                                              ////
415
//// This source file is free software; you can redistribute it   ////
416
//// and/or modify it under the terms of the GNU Lesser General   ////
417
//// Public License as published by the Free Software Foundation; ////
418
//// either version 2.1 of the License, or (at your option) any   ////
419
//// later version.                                               ////
420
////                                                              ////
421
//// This source is distributed in the hope that it will be       ////
422
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
423
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
424
//// PURPOSE.  See the GNU Lesser General Public License for more ////
425
//// details.                                                     ////
426
////                                                              ////
427
//// You should have received a copy of the GNU Lesser General    ////
428
//// Public License along with this source; if not, download it   ////
429
//// from http://www.opencores.org/lgpl.shtml                     ////
430
////                                                              ////
431
//////////////////////////////////////////////////////////////////////
432
 
433 18 unneback
module vl_dff ( d, q, clk, rst);
434 6 unneback
 
435
        parameter width = 1;
436
        parameter reset_value = 0;
437
 
438
        input [width-1:0] d;
439
        input clk, rst;
440
        output reg [width-1:0] q;
441
 
442
        always @ (posedge clk or posedge rst)
443
        if (rst)
444
                q <= reset_value;
445
        else
446
                q <= d;
447
 
448
endmodule
449
 
450 18 unneback
module vl_dff_array ( d, q, clk, rst);
451 6 unneback
 
452
        parameter width = 1;
453
        parameter depth = 2;
454
        parameter reset_value = 1'b0;
455
 
456
        input [width-1:0] d;
457
        input clk, rst;
458
        output [width-1:0] q;
459
        reg  [0:depth-1] q_tmp [width-1:0];
460
        integer i;
461
        always @ (posedge clk or posedge rst)
462
        if (rst) begin
463
            for (i=0;i<depth;i=i+1)
464
                q_tmp[i] <= {width{reset_value}};
465
        end else begin
466
            q_tmp[0] <= d;
467
            for (i=1;i<depth;i=i+1)
468
                q_tmp[i] <= q_tmp[i-1];
469
        end
470
 
471
    assign q = q_tmp[depth-1];
472
 
473
endmodule
474
 
475 18 unneback
module vl_dff_ce ( d, ce, q, clk, rst);
476 6 unneback
 
477
        parameter width = 1;
478
        parameter reset_value = 0;
479
 
480
        input [width-1:0] d;
481
        input ce, clk, rst;
482
        output reg [width-1:0] q;
483
 
484
        always @ (posedge clk or posedge rst)
485
        if (rst)
486
                q <= reset_value;
487
        else
488
                if (ce)
489
                        q <= d;
490
 
491
endmodule
492
 
493 18 unneback
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
494 8 unneback
 
495
        parameter width = 1;
496
        parameter reset_value = 0;
497
 
498
        input [width-1:0] d;
499 10 unneback
        input ce, clear, clk, rst;
500 8 unneback
        output reg [width-1:0] q;
501
 
502
        always @ (posedge clk or posedge rst)
503
        if (rst)
504
            q <= reset_value;
505
        else
506
            if (ce)
507
                if (clear)
508
                    q <= {width{1'b0}};
509
                else
510
                    q <= d;
511
 
512
endmodule
513
 
514 24 unneback
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
515
 
516
        parameter width = 1;
517
        parameter reset_value = 0;
518
 
519
        input [width-1:0] d;
520
        input ce, set, clk, rst;
521
        output reg [width-1:0] q;
522
 
523
        always @ (posedge clk or posedge rst)
524
        if (rst)
525
            q <= reset_value;
526
        else
527
            if (ce)
528
                if (set)
529
                    q <= {width{1'b1}};
530
                else
531
                    q <= d;
532
 
533
endmodule
534
 
535 29 unneback
module vl_spr ( sp, r, q, clk, rst);
536
 
537
        parameter width = 1;
538
        parameter reset_value = 0;
539
 
540
        input sp, r;
541
        output reg q;
542
        input clk, rst;
543
 
544
        always @ (posedge clk or posedge rst)
545
        if (rst)
546
            q <= reset_value;
547
        else
548
            if (sp)
549
                q <= 1'b1;
550
            else if (r)
551
                q <= 1'b0;
552
 
553
endmodule
554
 
555
module vl_srp ( s, rp, q, clk, rst);
556
 
557
        parameter width = 1;
558
        parameter reset_value = 0;
559
 
560
        input s, rp;
561
        output reg q;
562
        input clk, rst;
563
 
564
        always @ (posedge clk or posedge rst)
565
        if (rst)
566
            q <= reset_value;
567
        else
568
            if (rp)
569
                q <= 1'b0;
570
            else if (s)
571
                q <= 1'b1;
572
 
573
endmodule
574
 
575
 
576 6 unneback
`ifdef ALTERA
577
// megafunction wizard: %LPM_FF%
578
// GENERATION: STANDARD
579
// VERSION: WM1.0
580
// MODULE: lpm_ff 
581
 
582
// ============================================================
583
// File Name: dff_sr.v
584
// Megafunction Name(s):
585
//                      lpm_ff
586
//
587
// Simulation Library Files(s):
588
//                      lpm
589
// ============================================================
590
// ************************************************************
591
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
592
//
593
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
594
// ************************************************************
595
 
596
 
597
//Copyright (C) 1991-2010 Altera Corporation
598
//Your use of Altera Corporation's design tools, logic functions 
599
//and other software and tools, and its AMPP partner logic 
600
//functions, and any output files from any of the foregoing 
601
//(including device programming or simulation files), and any 
602
//associated documentation or information are expressly subject 
603
//to the terms and conditions of the Altera Program License 
604
//Subscription Agreement, Altera MegaCore Function License 
605
//Agreement, or other applicable license agreement, including, 
606
//without limitation, that your use is for the sole purpose of 
607
//programming logic devices manufactured by Altera and sold by 
608
//Altera or its authorized distributors.  Please refer to the 
609
//applicable agreement for further details.
610
 
611
 
612
// synopsys translate_off
613
`timescale 1 ps / 1 ps
614
// synopsys translate_on
615 18 unneback
module vl_dff_sr (
616 6 unneback
        aclr,
617
        aset,
618
        clock,
619
        data,
620
        q);
621
 
622
        input     aclr;
623
        input     aset;
624
        input     clock;
625
        input     data;
626
        output    q;
627
 
628
        wire [0:0] sub_wire0;
629
        wire [0:0] sub_wire1 = sub_wire0[0:0];
630
        wire  q = sub_wire1;
631
        wire  sub_wire2 = data;
632
        wire  sub_wire3 = sub_wire2;
633
 
634
        lpm_ff  lpm_ff_component (
635
                                .aclr (aclr),
636
                                .clock (clock),
637
                                .data (sub_wire3),
638
                                .aset (aset),
639
                                .q (sub_wire0)
640
                                // synopsys translate_off
641
                                ,
642
                                .aload (),
643
                                .enable (),
644
                                .sclr (),
645
                                .sload (),
646
                                .sset ()
647
                                // synopsys translate_on
648
                                );
649
        defparam
650
                lpm_ff_component.lpm_fftype = "DFF",
651
                lpm_ff_component.lpm_type = "LPM_FF",
652
                lpm_ff_component.lpm_width = 1;
653
 
654
 
655
endmodule
656
 
657
// ============================================================
658
// CNX file retrieval info
659
// ============================================================
660
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
661
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
662
// Retrieval info: PRIVATE: ASET NUMERIC "1"
663
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
664
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
665
// Retrieval info: PRIVATE: DFF NUMERIC "1"
666
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
667
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
668
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
669
// Retrieval info: PRIVATE: SSET NUMERIC "0"
670
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
671
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
672
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
673
// Retrieval info: PRIVATE: nBit NUMERIC "1"
674
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
675
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
676
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
677
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
678
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
679
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
680
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
681
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
682
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
683
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
684
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
685
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
686
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
687
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
688
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
689
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
690
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
691
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
692
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
693
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
694
// Retrieval info: LIB_FILE: lpm
695
 
696
 
697
`else
698
 
699
 
700 18 unneback
module vl_dff_sr ( aclr, aset, clock, data, q);
701 6 unneback
 
702
    input         aclr;
703
    input         aset;
704
    input         clock;
705
    input         data;
706
    output reg    q;
707
 
708
   always @ (posedge clock or posedge aclr or posedge aset)
709
     if (aclr)
710
       q <= 1'b0;
711
     else if (aset)
712
       q <= 1'b1;
713
     else
714
       q <= data;
715
 
716
endmodule
717
 
718
`endif
719
 
720
// LATCH
721
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
722
`ifdef ALTERA
723 18 unneback
module vl_latch ( d, le, q, clk);
724 6 unneback
input d, le;
725
output q;
726
input clk;
727
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
728
endmodule
729
`else
730
module latch ( d, le, q, clk);
731
input d, le;
732
output q;
733
input clk;/*
734
   always @ (posedge direction_set or posedge direction_clr)
735
     if (direction_clr)
736
       direction <= going_empty;
737
     else
738
       direction <= going_full;*/
739
endmodule
740 15 unneback
`endif
741
 
742 18 unneback
module vl_shreg ( d, q, clk, rst);
743 17 unneback
parameter depth = 10;
744
input d;
745
output q;
746
input clk, rst;
747
 
748
reg [1:depth] dffs;
749
 
750
always @ (posedge clk or posedge rst)
751
if (rst)
752
    dffs <= {depth{1'b0}};
753
else
754
    dffs <= {d,dffs[1:depth-1]};
755
assign q = dffs[depth];
756
endmodule
757
 
758 18 unneback
module vl_shreg_ce ( d, ce, q, clk, rst);
759 17 unneback
parameter depth = 10;
760
input d, ce;
761
output q;
762
input clk, rst;
763
 
764
reg [1:depth] dffs;
765
 
766
always @ (posedge clk or posedge rst)
767
if (rst)
768
    dffs <= {depth{1'b0}};
769
else
770
    if (ce)
771
        dffs <= {d,dffs[1:depth-1]};
772
assign q = dffs[depth];
773
endmodule
774
 
775 18 unneback
module vl_delay ( d, q, clk, rst);
776 15 unneback
parameter depth = 10;
777
input d;
778
output q;
779
input clk, rst;
780
 
781
reg [1:depth] dffs;
782
 
783
always @ (posedge clk or posedge rst)
784
if (rst)
785
    dffs <= {depth{1'b0}};
786
else
787
    dffs <= {d,dffs[1:depth-1]};
788
assign q = dffs[depth];
789 17 unneback
endmodule
790
 
791 18 unneback
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
792 17 unneback
parameter depth = 10;
793
input d;
794
output q, emptyflag;
795
input clk, rst;
796
 
797
reg [1:depth] dffs;
798
 
799
always @ (posedge clk or posedge rst)
800
if (rst)
801
    dffs <= {depth{1'b0}};
802
else
803
    dffs <= {d,dffs[1:depth-1]};
804
assign q = dffs[depth];
805
assign emptyflag = !(|dffs);
806
endmodule
807
//////////////////////////////////////////////////////////////////////
808 6 unneback
////                                                              ////
809 18 unneback
////  Logic functions                                             ////
810
////                                                              ////
811
////  Description                                                 ////
812
////  Logic functions such as multiplexers                        ////
813
////                                                              ////
814
////                                                              ////
815
////  To Do:                                                      ////
816
////   -                                                          ////
817
////                                                              ////
818
////  Author(s):                                                  ////
819
////      - Michael Unneback, unneback@opencores.org              ////
820
////        ORSoC AB                                              ////
821
////                                                              ////
822
//////////////////////////////////////////////////////////////////////
823
////                                                              ////
824
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
825
////                                                              ////
826
//// This source file may be used and distributed without         ////
827
//// restriction provided that this copyright statement is not    ////
828
//// removed from the file and that any derivative work contains  ////
829
//// the original copyright notice and the associated disclaimer. ////
830
////                                                              ////
831
//// This source file is free software; you can redistribute it   ////
832
//// and/or modify it under the terms of the GNU Lesser General   ////
833
//// Public License as published by the Free Software Foundation; ////
834
//// either version 2.1 of the License, or (at your option) any   ////
835
//// later version.                                               ////
836
////                                                              ////
837
//// This source is distributed in the hope that it will be       ////
838
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
839
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
840
//// PURPOSE.  See the GNU Lesser General Public License for more ////
841
//// details.                                                     ////
842
////                                                              ////
843
//// You should have received a copy of the GNU Lesser General    ////
844
//// Public License along with this source; if not, download it   ////
845
//// from http://www.opencores.org/lgpl.shtml                     ////
846
////                                                              ////
847
//////////////////////////////////////////////////////////////////////
848
 
849
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
850
 
851
parameter width = 32;
852
parameter nr_of_ports = 4;
853
input [width-1:0] a3, a2, a1, a0;
854
input [nr_of_ports-1:0] sel;
855 22 unneback
output [width-1:0] dout;
856 18 unneback
 
857 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
858 18 unneback
integer i;
859
 
860
// and
861
assign tmp[0] = {width{sel[0]}} & a0;
862
assign tmp[1] = {width{sel[1]}} & a1;
863
assign tmp[2] = {width{sel[2]}} & a2;
864
assign tmp[3] = {width{sel[3]}} & a3;
865
 
866
// or
867
assign dout = tmp[3] | tmp[2] | tmp[1] | tmp[0];
868
 
869
endmodule
870
 
871
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
872
 
873
parameter width = 32;
874
parameter nr_of_ports = 5;
875
input [width-1:0] a4, a3, a2, a1, a0;
876
input [nr_of_ports-1:0] sel;
877 22 unneback
output [width-1:0] dout;
878 18 unneback
 
879 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
880 18 unneback
integer i;
881
 
882
// and
883
assign tmp[0] = {width{sel[0]}} & a0;
884
assign tmp[1] = {width{sel[1]}} & a1;
885
assign tmp[2] = {width{sel[2]}} & a2;
886
assign tmp[3] = {width{sel[3]}} & a3;
887
assign tmp[4] = {width{sel[4]}} & a4;
888
 
889
// or
890
assign dout = tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
891
 
892
endmodule
893
 
894
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
895
 
896
parameter width = 32;
897
parameter nr_of_ports = 6;
898
input [width-1:0] a5, a4, a3, a2, a1, a0;
899
input [nr_of_ports-1:0] sel;
900 22 unneback
output [width-1:0] dout;
901 18 unneback
 
902 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
903 18 unneback
integer i;
904
 
905
// and
906
assign tmp[0] = {width{sel[0]}} & a0;
907
assign tmp[1] = {width{sel[1]}} & a1;
908
assign tmp[2] = {width{sel[2]}} & a2;
909
assign tmp[3] = {width{sel[3]}} & a3;
910
assign tmp[4] = {width{sel[4]}} & a4;
911
assign tmp[5] = {width{sel[5]}} & a5;
912
 
913
// or
914
assign dout = tmp[5] | tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
915
 
916
endmodule
917
//////////////////////////////////////////////////////////////////////
918
////                                                              ////
919 6 unneback
////  Versatile counter                                           ////
920
////                                                              ////
921
////  Description                                                 ////
922
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
923
////  counter                                                     ////
924
////                                                              ////
925
////  To Do:                                                      ////
926
////   - add LFSR with more taps                                  ////
927
////                                                              ////
928
////  Author(s):                                                  ////
929
////      - Michael Unneback, unneback@opencores.org              ////
930
////        ORSoC AB                                              ////
931
////                                                              ////
932
//////////////////////////////////////////////////////////////////////
933
////                                                              ////
934
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
935
////                                                              ////
936
//// This source file may be used and distributed without         ////
937
//// restriction provided that this copyright statement is not    ////
938
//// removed from the file and that any derivative work contains  ////
939
//// the original copyright notice and the associated disclaimer. ////
940
////                                                              ////
941
//// This source file is free software; you can redistribute it   ////
942
//// and/or modify it under the terms of the GNU Lesser General   ////
943
//// Public License as published by the Free Software Foundation; ////
944
//// either version 2.1 of the License, or (at your option) any   ////
945
//// later version.                                               ////
946
////                                                              ////
947
//// This source is distributed in the hope that it will be       ////
948
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
949
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
950
//// PURPOSE.  See the GNU Lesser General Public License for more ////
951
//// details.                                                     ////
952
////                                                              ////
953
//// You should have received a copy of the GNU Lesser General    ////
954
//// Public License along with this source; if not, download it   ////
955
//// from http://www.opencores.org/lgpl.shtml                     ////
956
////                                                              ////
957
//////////////////////////////////////////////////////////////////////
958
 
959
// binary counter
960 22 unneback
module vl_cnt_bin ( q, rst, clk);
961
 
962
   parameter length = 4;
963
   output [length:1] q;
964
   input rst;
965
   input clk;
966
 
967
   parameter clear_value = 0;
968
   parameter set_value = 1;
969
   parameter wrap_value = 0;
970
   parameter level1_value = 15;
971
 
972
   reg  [length:1] qi;
973
   wire [length:1] q_next;
974
   assign q_next = qi + {{length-1{1'b0}},1'b1};
975
 
976
   always @ (posedge clk or posedge rst)
977
     if (rst)
978
       qi <= {length{1'b0}};
979
     else
980
       qi <= q_next;
981
 
982
   assign q = qi;
983
 
984
endmodule
985
//////////////////////////////////////////////////////////////////////
986
////                                                              ////
987
////  Versatile counter                                           ////
988
////                                                              ////
989
////  Description                                                 ////
990
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
991
////  counter                                                     ////
992
////                                                              ////
993
////  To Do:                                                      ////
994
////   - add LFSR with more taps                                  ////
995
////                                                              ////
996
////  Author(s):                                                  ////
997
////      - Michael Unneback, unneback@opencores.org              ////
998
////        ORSoC AB                                              ////
999
////                                                              ////
1000
//////////////////////////////////////////////////////////////////////
1001
////                                                              ////
1002
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1003
////                                                              ////
1004
//// This source file may be used and distributed without         ////
1005
//// restriction provided that this copyright statement is not    ////
1006
//// removed from the file and that any derivative work contains  ////
1007
//// the original copyright notice and the associated disclaimer. ////
1008
////                                                              ////
1009
//// This source file is free software; you can redistribute it   ////
1010
//// and/or modify it under the terms of the GNU Lesser General   ////
1011
//// Public License as published by the Free Software Foundation; ////
1012
//// either version 2.1 of the License, or (at your option) any   ////
1013
//// later version.                                               ////
1014
////                                                              ////
1015
//// This source is distributed in the hope that it will be       ////
1016
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1017
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1018
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1019
//// details.                                                     ////
1020
////                                                              ////
1021
//// You should have received a copy of the GNU Lesser General    ////
1022
//// Public License along with this source; if not, download it   ////
1023
//// from http://www.opencores.org/lgpl.shtml                     ////
1024
////                                                              ////
1025
//////////////////////////////////////////////////////////////////////
1026
 
1027
// binary counter
1028
module vl_cnt_bin_clear ( clear, q, rst, clk);
1029
 
1030
   parameter length = 4;
1031
   input clear;
1032
   output [length:1] q;
1033
   input rst;
1034
   input clk;
1035
 
1036
   parameter clear_value = 0;
1037
   parameter set_value = 1;
1038
   parameter wrap_value = 0;
1039
   parameter level1_value = 15;
1040
 
1041
   reg  [length:1] qi;
1042
   wire [length:1] q_next;
1043
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1044
 
1045
   always @ (posedge clk or posedge rst)
1046
     if (rst)
1047
       qi <= {length{1'b0}};
1048
     else
1049
       qi <= q_next;
1050
 
1051
   assign q = qi;
1052
 
1053
endmodule
1054
//////////////////////////////////////////////////////////////////////
1055
////                                                              ////
1056
////  Versatile counter                                           ////
1057
////                                                              ////
1058
////  Description                                                 ////
1059
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1060
////  counter                                                     ////
1061
////                                                              ////
1062
////  To Do:                                                      ////
1063
////   - add LFSR with more taps                                  ////
1064
////                                                              ////
1065
////  Author(s):                                                  ////
1066
////      - Michael Unneback, unneback@opencores.org              ////
1067
////        ORSoC AB                                              ////
1068
////                                                              ////
1069
//////////////////////////////////////////////////////////////////////
1070
////                                                              ////
1071
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1072
////                                                              ////
1073
//// This source file may be used and distributed without         ////
1074
//// restriction provided that this copyright statement is not    ////
1075
//// removed from the file and that any derivative work contains  ////
1076
//// the original copyright notice and the associated disclaimer. ////
1077
////                                                              ////
1078
//// This source file is free software; you can redistribute it   ////
1079
//// and/or modify it under the terms of the GNU Lesser General   ////
1080
//// Public License as published by the Free Software Foundation; ////
1081
//// either version 2.1 of the License, or (at your option) any   ////
1082
//// later version.                                               ////
1083
////                                                              ////
1084
//// This source is distributed in the hope that it will be       ////
1085
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1086
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1087
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1088
//// details.                                                     ////
1089
////                                                              ////
1090
//// You should have received a copy of the GNU Lesser General    ////
1091
//// Public License along with this source; if not, download it   ////
1092
//// from http://www.opencores.org/lgpl.shtml                     ////
1093
////                                                              ////
1094
//////////////////////////////////////////////////////////////////////
1095
 
1096
// binary counter
1097 18 unneback
module vl_cnt_bin_ce ( cke, q, rst, clk);
1098 6 unneback
 
1099
   parameter length = 4;
1100
   input cke;
1101
   output [length:1] q;
1102
   input rst;
1103
   input clk;
1104
 
1105
   parameter clear_value = 0;
1106
   parameter set_value = 1;
1107
   parameter wrap_value = 0;
1108
   parameter level1_value = 15;
1109
 
1110
   reg  [length:1] qi;
1111
   wire [length:1] q_next;
1112
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1113
 
1114
   always @ (posedge clk or posedge rst)
1115
     if (rst)
1116
       qi <= {length{1'b0}};
1117
     else
1118
     if (cke)
1119
       qi <= q_next;
1120
 
1121
   assign q = qi;
1122
 
1123
endmodule
1124
//////////////////////////////////////////////////////////////////////
1125
////                                                              ////
1126
////  Versatile counter                                           ////
1127
////                                                              ////
1128
////  Description                                                 ////
1129
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1130
////  counter                                                     ////
1131
////                                                              ////
1132
////  To Do:                                                      ////
1133
////   - add LFSR with more taps                                  ////
1134
////                                                              ////
1135
////  Author(s):                                                  ////
1136
////      - Michael Unneback, unneback@opencores.org              ////
1137
////        ORSoC AB                                              ////
1138
////                                                              ////
1139
//////////////////////////////////////////////////////////////////////
1140
////                                                              ////
1141
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1142
////                                                              ////
1143
//// This source file may be used and distributed without         ////
1144
//// restriction provided that this copyright statement is not    ////
1145
//// removed from the file and that any derivative work contains  ////
1146
//// the original copyright notice and the associated disclaimer. ////
1147
////                                                              ////
1148
//// This source file is free software; you can redistribute it   ////
1149
//// and/or modify it under the terms of the GNU Lesser General   ////
1150
//// Public License as published by the Free Software Foundation; ////
1151
//// either version 2.1 of the License, or (at your option) any   ////
1152
//// later version.                                               ////
1153
////                                                              ////
1154
//// This source is distributed in the hope that it will be       ////
1155
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1156
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1157
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1158
//// details.                                                     ////
1159
////                                                              ////
1160
//// You should have received a copy of the GNU Lesser General    ////
1161
//// Public License along with this source; if not, download it   ////
1162
//// from http://www.opencores.org/lgpl.shtml                     ////
1163
////                                                              ////
1164
//////////////////////////////////////////////////////////////////////
1165
 
1166
// binary counter
1167 18 unneback
module vl_cnt_bin_ce_clear ( clear, cke, q, rst, clk);
1168 6 unneback
 
1169
   parameter length = 4;
1170
   input clear;
1171
   input cke;
1172
   output [length:1] q;
1173
   input rst;
1174
   input clk;
1175
 
1176
   parameter clear_value = 0;
1177
   parameter set_value = 1;
1178
   parameter wrap_value = 0;
1179
   parameter level1_value = 15;
1180
 
1181
   reg  [length:1] qi;
1182
   wire [length:1] q_next;
1183
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1184
 
1185
   always @ (posedge clk or posedge rst)
1186
     if (rst)
1187
       qi <= {length{1'b0}};
1188
     else
1189
     if (cke)
1190
       qi <= q_next;
1191
 
1192
   assign q = qi;
1193
 
1194
endmodule
1195
//////////////////////////////////////////////////////////////////////
1196
////                                                              ////
1197
////  Versatile counter                                           ////
1198
////                                                              ////
1199
////  Description                                                 ////
1200
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1201
////  counter                                                     ////
1202
////                                                              ////
1203
////  To Do:                                                      ////
1204
////   - add LFSR with more taps                                  ////
1205
////                                                              ////
1206
////  Author(s):                                                  ////
1207
////      - Michael Unneback, unneback@opencores.org              ////
1208
////        ORSoC AB                                              ////
1209
////                                                              ////
1210
//////////////////////////////////////////////////////////////////////
1211
////                                                              ////
1212
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1213
////                                                              ////
1214
//// This source file may be used and distributed without         ////
1215
//// restriction provided that this copyright statement is not    ////
1216
//// removed from the file and that any derivative work contains  ////
1217
//// the original copyright notice and the associated disclaimer. ////
1218
////                                                              ////
1219
//// This source file is free software; you can redistribute it   ////
1220
//// and/or modify it under the terms of the GNU Lesser General   ////
1221
//// Public License as published by the Free Software Foundation; ////
1222
//// either version 2.1 of the License, or (at your option) any   ////
1223
//// later version.                                               ////
1224
////                                                              ////
1225
//// This source is distributed in the hope that it will be       ////
1226
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1227
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1228
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1229
//// details.                                                     ////
1230
////                                                              ////
1231
//// You should have received a copy of the GNU Lesser General    ////
1232
//// Public License along with this source; if not, download it   ////
1233
//// from http://www.opencores.org/lgpl.shtml                     ////
1234
////                                                              ////
1235
//////////////////////////////////////////////////////////////////////
1236
 
1237
// binary counter
1238 29 unneback
module vl_cnt_bin_ce_clear_l1_l2 ( clear, cke, q, level1, level2, rst, clk);
1239
 
1240
   parameter length = 4;
1241
   input clear;
1242
   input cke;
1243
   output [length:1] q;
1244
   output reg level1;
1245
   output reg level2;
1246
   input rst;
1247
   input clk;
1248
 
1249
   parameter clear_value = 0;
1250
   parameter set_value = 1;
1251 30 unneback
   parameter wrap_value = 15;
1252
   parameter level1_value = 8;
1253
   parameter level2_value = 15;
1254 29 unneback
 
1255
   wire rew;
1256 30 unneback
   assign rew = 1'b0;
1257 29 unneback
   reg  [length:1] qi;
1258
   wire [length:1] q_next;
1259
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1260
 
1261
   always @ (posedge clk or posedge rst)
1262
     if (rst)
1263
       qi <= {length{1'b0}};
1264
     else
1265
     if (cke)
1266
       qi <= q_next;
1267
 
1268
   assign q = qi;
1269
 
1270
 
1271
    always @ (posedge clk or posedge rst)
1272
    if (rst)
1273
        level1 <= 1'b0;
1274
    else
1275
    if (cke)
1276
    if (clear)
1277
        level1 <= 1'b0;
1278
    else if (q_next == level1_value)
1279
        level1 <= 1'b1;
1280
    else if (qi == level1_value & rew)
1281
        level1 <= 1'b0;
1282
 
1283
    always @ (posedge clk or posedge rst)
1284
    if (rst)
1285
        level2 <= 1'b0;
1286
    else
1287
    if (cke)
1288
    if (clear)
1289
        level2 <= 1'b0;
1290
    else if (q_next == level2_value)
1291
        level2 <= 1'b1;
1292
    else if (qi == level2_value & rew)
1293
        level2 <= 1'b0;
1294
endmodule
1295
//////////////////////////////////////////////////////////////////////
1296
////                                                              ////
1297
////  Versatile counter                                           ////
1298
////                                                              ////
1299
////  Description                                                 ////
1300
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1301
////  counter                                                     ////
1302
////                                                              ////
1303
////  To Do:                                                      ////
1304
////   - add LFSR with more taps                                  ////
1305
////                                                              ////
1306
////  Author(s):                                                  ////
1307
////      - Michael Unneback, unneback@opencores.org              ////
1308
////        ORSoC AB                                              ////
1309
////                                                              ////
1310
//////////////////////////////////////////////////////////////////////
1311
////                                                              ////
1312
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1313
////                                                              ////
1314
//// This source file may be used and distributed without         ////
1315
//// restriction provided that this copyright statement is not    ////
1316
//// removed from the file and that any derivative work contains  ////
1317
//// the original copyright notice and the associated disclaimer. ////
1318
////                                                              ////
1319
//// This source file is free software; you can redistribute it   ////
1320
//// and/or modify it under the terms of the GNU Lesser General   ////
1321
//// Public License as published by the Free Software Foundation; ////
1322
//// either version 2.1 of the License, or (at your option) any   ////
1323
//// later version.                                               ////
1324
////                                                              ////
1325
//// This source is distributed in the hope that it will be       ////
1326
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1327
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1328
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1329
//// details.                                                     ////
1330
////                                                              ////
1331
//// You should have received a copy of the GNU Lesser General    ////
1332
//// Public License along with this source; if not, download it   ////
1333
//// from http://www.opencores.org/lgpl.shtml                     ////
1334
////                                                              ////
1335
//////////////////////////////////////////////////////////////////////
1336
 
1337
// binary counter
1338 18 unneback
module vl_cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk);
1339 6 unneback
 
1340
   parameter length = 4;
1341
   input clear;
1342
   input set;
1343
   input cke;
1344
   input rew;
1345
   output [length:1] q;
1346
   input rst;
1347
   input clk;
1348
 
1349
   parameter clear_value = 0;
1350
   parameter set_value = 1;
1351
   parameter wrap_value = 0;
1352
   parameter level1_value = 15;
1353
 
1354
   reg  [length:1] qi;
1355
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1356
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
1357
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
1358
   assign q_next = rew ? q_next_rew : q_next_fw;
1359
 
1360
   always @ (posedge clk or posedge rst)
1361
     if (rst)
1362
       qi <= {length{1'b0}};
1363
     else
1364
     if (cke)
1365
       qi <= q_next;
1366
 
1367
   assign q = qi;
1368
 
1369
endmodule
1370
//////////////////////////////////////////////////////////////////////
1371
////                                                              ////
1372
////  Versatile counter                                           ////
1373
////                                                              ////
1374
////  Description                                                 ////
1375
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1376
////  counter                                                     ////
1377
////                                                              ////
1378
////  To Do:                                                      ////
1379
////   - add LFSR with more taps                                  ////
1380
////                                                              ////
1381
////  Author(s):                                                  ////
1382
////      - Michael Unneback, unneback@opencores.org              ////
1383
////        ORSoC AB                                              ////
1384
////                                                              ////
1385
//////////////////////////////////////////////////////////////////////
1386
////                                                              ////
1387
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1388
////                                                              ////
1389
//// This source file may be used and distributed without         ////
1390
//// restriction provided that this copyright statement is not    ////
1391
//// removed from the file and that any derivative work contains  ////
1392
//// the original copyright notice and the associated disclaimer. ////
1393
////                                                              ////
1394
//// This source file is free software; you can redistribute it   ////
1395
//// and/or modify it under the terms of the GNU Lesser General   ////
1396
//// Public License as published by the Free Software Foundation; ////
1397
//// either version 2.1 of the License, or (at your option) any   ////
1398
//// later version.                                               ////
1399
////                                                              ////
1400
//// This source is distributed in the hope that it will be       ////
1401
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1402
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1403
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1404
//// details.                                                     ////
1405
////                                                              ////
1406
//// You should have received a copy of the GNU Lesser General    ////
1407
//// Public License along with this source; if not, download it   ////
1408
//// from http://www.opencores.org/lgpl.shtml                     ////
1409
////                                                              ////
1410
//////////////////////////////////////////////////////////////////////
1411
 
1412
// binary counter
1413 18 unneback
module vl_cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk);
1414 6 unneback
 
1415
   parameter length = 4;
1416
   input cke;
1417
   input rew;
1418
   output reg level1;
1419
   input rst;
1420
   input clk;
1421
 
1422
   parameter clear_value = 0;
1423
   parameter set_value = 1;
1424
   parameter wrap_value = 1;
1425
   parameter level1_value = 15;
1426
 
1427 29 unneback
   wire clear;
1428 30 unneback
   assign clear = 1'b0;
1429 6 unneback
   reg  [length:1] qi;
1430
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1431
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1432
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1433
   assign q_next = rew ? q_next_rew : q_next_fw;
1434
 
1435
   always @ (posedge clk or posedge rst)
1436
     if (rst)
1437
       qi <= {length{1'b0}};
1438
     else
1439
     if (cke)
1440
       qi <= q_next;
1441
 
1442
 
1443
 
1444
    always @ (posedge clk or posedge rst)
1445
    if (rst)
1446
        level1 <= 1'b0;
1447
    else
1448
    if (cke)
1449 29 unneback
    if (clear)
1450
        level1 <= 1'b0;
1451
    else if (q_next == level1_value)
1452 6 unneback
        level1 <= 1'b1;
1453
    else if (qi == level1_value & rew)
1454
        level1 <= 1'b0;
1455
endmodule
1456
//////////////////////////////////////////////////////////////////////
1457
////                                                              ////
1458
////  Versatile counter                                           ////
1459
////                                                              ////
1460
////  Description                                                 ////
1461
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1462
////  counter                                                     ////
1463
////                                                              ////
1464
////  To Do:                                                      ////
1465
////   - add LFSR with more taps                                  ////
1466
////                                                              ////
1467
////  Author(s):                                                  ////
1468
////      - Michael Unneback, unneback@opencores.org              ////
1469
////        ORSoC AB                                              ////
1470
////                                                              ////
1471
//////////////////////////////////////////////////////////////////////
1472
////                                                              ////
1473
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1474
////                                                              ////
1475
//// This source file may be used and distributed without         ////
1476
//// restriction provided that this copyright statement is not    ////
1477
//// removed from the file and that any derivative work contains  ////
1478
//// the original copyright notice and the associated disclaimer. ////
1479
////                                                              ////
1480
//// This source file is free software; you can redistribute it   ////
1481
//// and/or modify it under the terms of the GNU Lesser General   ////
1482
//// Public License as published by the Free Software Foundation; ////
1483
//// either version 2.1 of the License, or (at your option) any   ////
1484
//// later version.                                               ////
1485
////                                                              ////
1486
//// This source is distributed in the hope that it will be       ////
1487
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1488
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1489
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1490
//// details.                                                     ////
1491
////                                                              ////
1492
//// You should have received a copy of the GNU Lesser General    ////
1493
//// Public License along with this source; if not, download it   ////
1494
//// from http://www.opencores.org/lgpl.shtml                     ////
1495
////                                                              ////
1496
//////////////////////////////////////////////////////////////////////
1497
 
1498 25 unneback
// binary counter
1499
module vl_cnt_bin_ce_rew_zq_l1 ( cke, rew, zq, level1, rst, clk);
1500
 
1501
   parameter length = 4;
1502
   input cke;
1503
   input rew;
1504
   output reg zq;
1505
   output reg level1;
1506
   input rst;
1507
   input clk;
1508
 
1509
   parameter clear_value = 0;
1510
   parameter set_value = 1;
1511
   parameter wrap_value = 1;
1512
   parameter level1_value = 15;
1513
 
1514 29 unneback
   wire clear;
1515 30 unneback
   assign clear = 1'b0;
1516 25 unneback
   reg  [length:1] qi;
1517
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1518
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1519
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1520
   assign q_next = rew ? q_next_rew : q_next_fw;
1521
 
1522
   always @ (posedge clk or posedge rst)
1523
     if (rst)
1524
       qi <= {length{1'b0}};
1525
     else
1526
     if (cke)
1527
       qi <= q_next;
1528
 
1529
 
1530
 
1531
   always @ (posedge clk or posedge rst)
1532
     if (rst)
1533
       zq <= 1'b1;
1534
     else
1535
     if (cke)
1536
       zq <= q_next == {length{1'b0}};
1537
 
1538
    always @ (posedge clk or posedge rst)
1539
    if (rst)
1540
        level1 <= 1'b0;
1541
    else
1542
    if (cke)
1543 29 unneback
    if (clear)
1544
        level1 <= 1'b0;
1545
    else if (q_next == level1_value)
1546 25 unneback
        level1 <= 1'b1;
1547
    else if (qi == level1_value & rew)
1548
        level1 <= 1'b0;
1549
endmodule
1550
//////////////////////////////////////////////////////////////////////
1551
////                                                              ////
1552
////  Versatile counter                                           ////
1553
////                                                              ////
1554
////  Description                                                 ////
1555
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1556
////  counter                                                     ////
1557
////                                                              ////
1558
////  To Do:                                                      ////
1559
////   - add LFSR with more taps                                  ////
1560
////                                                              ////
1561
////  Author(s):                                                  ////
1562
////      - Michael Unneback, unneback@opencores.org              ////
1563
////        ORSoC AB                                              ////
1564
////                                                              ////
1565
//////////////////////////////////////////////////////////////////////
1566
////                                                              ////
1567
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1568
////                                                              ////
1569
//// This source file may be used and distributed without         ////
1570
//// restriction provided that this copyright statement is not    ////
1571
//// removed from the file and that any derivative work contains  ////
1572
//// the original copyright notice and the associated disclaimer. ////
1573
////                                                              ////
1574
//// This source file is free software; you can redistribute it   ////
1575
//// and/or modify it under the terms of the GNU Lesser General   ////
1576
//// Public License as published by the Free Software Foundation; ////
1577
//// either version 2.1 of the License, or (at your option) any   ////
1578
//// later version.                                               ////
1579
////                                                              ////
1580
//// This source is distributed in the hope that it will be       ////
1581
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1582
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1583
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1584
//// details.                                                     ////
1585
////                                                              ////
1586
//// You should have received a copy of the GNU Lesser General    ////
1587
//// Public License along with this source; if not, download it   ////
1588
//// from http://www.opencores.org/lgpl.shtml                     ////
1589
////                                                              ////
1590
//////////////////////////////////////////////////////////////////////
1591
 
1592
// binary counter
1593
module vl_cnt_bin_ce_rew_q_zq_l1 ( cke, rew, q, zq, level1, rst, clk);
1594
 
1595
   parameter length = 4;
1596
   input cke;
1597
   input rew;
1598
   output [length:1] q;
1599
   output reg zq;
1600
   output reg level1;
1601
   input rst;
1602
   input clk;
1603
 
1604
   parameter clear_value = 0;
1605
   parameter set_value = 1;
1606
   parameter wrap_value = 1;
1607
   parameter level1_value = 15;
1608
 
1609 29 unneback
   wire clear;
1610 30 unneback
   assign clear = 1'b0;
1611 25 unneback
   reg  [length:1] qi;
1612
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1613
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1614
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1615
   assign q_next = rew ? q_next_rew : q_next_fw;
1616
 
1617
   always @ (posedge clk or posedge rst)
1618
     if (rst)
1619
       qi <= {length{1'b0}};
1620
     else
1621
     if (cke)
1622
       qi <= q_next;
1623
 
1624
   assign q = qi;
1625
 
1626
 
1627
   always @ (posedge clk or posedge rst)
1628
     if (rst)
1629
       zq <= 1'b1;
1630
     else
1631
     if (cke)
1632
       zq <= q_next == {length{1'b0}};
1633
 
1634
    always @ (posedge clk or posedge rst)
1635
    if (rst)
1636
        level1 <= 1'b0;
1637
    else
1638
    if (cke)
1639 29 unneback
    if (clear)
1640
        level1 <= 1'b0;
1641
    else if (q_next == level1_value)
1642 25 unneback
        level1 <= 1'b1;
1643
    else if (qi == level1_value & rew)
1644
        level1 <= 1'b0;
1645
endmodule
1646
//////////////////////////////////////////////////////////////////////
1647
////                                                              ////
1648
////  Versatile counter                                           ////
1649
////                                                              ////
1650
////  Description                                                 ////
1651
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1652
////  counter                                                     ////
1653
////                                                              ////
1654
////  To Do:                                                      ////
1655
////   - add LFSR with more taps                                  ////
1656
////                                                              ////
1657
////  Author(s):                                                  ////
1658
////      - Michael Unneback, unneback@opencores.org              ////
1659
////        ORSoC AB                                              ////
1660
////                                                              ////
1661
//////////////////////////////////////////////////////////////////////
1662
////                                                              ////
1663
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1664
////                                                              ////
1665
//// This source file may be used and distributed without         ////
1666
//// restriction provided that this copyright statement is not    ////
1667
//// removed from the file and that any derivative work contains  ////
1668
//// the original copyright notice and the associated disclaimer. ////
1669
////                                                              ////
1670
//// This source file is free software; you can redistribute it   ////
1671
//// and/or modify it under the terms of the GNU Lesser General   ////
1672
//// Public License as published by the Free Software Foundation; ////
1673
//// either version 2.1 of the License, or (at your option) any   ////
1674
//// later version.                                               ////
1675
////                                                              ////
1676
//// This source is distributed in the hope that it will be       ////
1677
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1678
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1679
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1680
//// details.                                                     ////
1681
////                                                              ////
1682
//// You should have received a copy of the GNU Lesser General    ////
1683
//// Public License along with this source; if not, download it   ////
1684
//// from http://www.opencores.org/lgpl.shtml                     ////
1685
////                                                              ////
1686
//////////////////////////////////////////////////////////////////////
1687
 
1688 6 unneback
// LFSR counter
1689 18 unneback
module vl_cnt_lfsr_zq ( zq, rst, clk);
1690 6 unneback
 
1691
   parameter length = 4;
1692
   output reg zq;
1693
   input rst;
1694
   input clk;
1695
 
1696
   parameter clear_value = 0;
1697
   parameter set_value = 1;
1698
   parameter wrap_value = 8;
1699
   parameter level1_value = 15;
1700
 
1701
   reg  [length:1] qi;
1702
   reg lfsr_fb;
1703
   wire [length:1] q_next;
1704
   reg [32:1] polynom;
1705
   integer i;
1706
 
1707
   always @ (qi)
1708
   begin
1709
        case (length)
1710
         2: polynom = 32'b11;                               // 0x3
1711
         3: polynom = 32'b110;                              // 0x6
1712
         4: polynom = 32'b1100;                             // 0xC
1713
         5: polynom = 32'b10100;                            // 0x14
1714
         6: polynom = 32'b110000;                           // 0x30
1715
         7: polynom = 32'b1100000;                          // 0x60
1716
         8: polynom = 32'b10111000;                         // 0xb8
1717
         9: polynom = 32'b100010000;                        // 0x110
1718
        10: polynom = 32'b1001000000;                       // 0x240
1719
        11: polynom = 32'b10100000000;                      // 0x500
1720
        12: polynom = 32'b100000101001;                     // 0x829
1721
        13: polynom = 32'b1000000001100;                    // 0x100C
1722
        14: polynom = 32'b10000000010101;                   // 0x2015
1723
        15: polynom = 32'b110000000000000;                  // 0x6000
1724
        16: polynom = 32'b1101000000001000;                 // 0xD008
1725
        17: polynom = 32'b10010000000000000;                // 0x12000
1726
        18: polynom = 32'b100000010000000000;               // 0x20400
1727
        19: polynom = 32'b1000000000000100011;              // 0x40023
1728
        20: polynom = 32'b10000010000000000000;             // 0x82000
1729
        21: polynom = 32'b101000000000000000000;            // 0x140000
1730
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1731
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1732
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1733
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1734
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1735
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1736
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1737
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1738
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1739
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1740
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1741
        default: polynom = 32'b0;
1742
        endcase
1743
        lfsr_fb = qi[length];
1744
        for (i=length-1; i>=1; i=i-1) begin
1745
            if (polynom[i])
1746
                lfsr_fb = lfsr_fb  ~^ qi[i];
1747
        end
1748
    end
1749
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1750
 
1751
   always @ (posedge clk or posedge rst)
1752
     if (rst)
1753
       qi <= {length{1'b0}};
1754
     else
1755
       qi <= q_next;
1756
 
1757
 
1758
 
1759
   always @ (posedge clk or posedge rst)
1760
     if (rst)
1761
       zq <= 1'b1;
1762
     else
1763
       zq <= q_next == {length{1'b0}};
1764
endmodule
1765
//////////////////////////////////////////////////////////////////////
1766
////                                                              ////
1767
////  Versatile counter                                           ////
1768
////                                                              ////
1769
////  Description                                                 ////
1770
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1771
////  counter                                                     ////
1772
////                                                              ////
1773
////  To Do:                                                      ////
1774
////   - add LFSR with more taps                                  ////
1775
////                                                              ////
1776
////  Author(s):                                                  ////
1777
////      - Michael Unneback, unneback@opencores.org              ////
1778
////        ORSoC AB                                              ////
1779
////                                                              ////
1780
//////////////////////////////////////////////////////////////////////
1781
////                                                              ////
1782
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1783
////                                                              ////
1784
//// This source file may be used and distributed without         ////
1785
//// restriction provided that this copyright statement is not    ////
1786
//// removed from the file and that any derivative work contains  ////
1787
//// the original copyright notice and the associated disclaimer. ////
1788
////                                                              ////
1789
//// This source file is free software; you can redistribute it   ////
1790
//// and/or modify it under the terms of the GNU Lesser General   ////
1791
//// Public License as published by the Free Software Foundation; ////
1792
//// either version 2.1 of the License, or (at your option) any   ////
1793
//// later version.                                               ////
1794
////                                                              ////
1795
//// This source is distributed in the hope that it will be       ////
1796
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1797
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1798
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1799
//// details.                                                     ////
1800
////                                                              ////
1801
//// You should have received a copy of the GNU Lesser General    ////
1802
//// Public License along with this source; if not, download it   ////
1803
//// from http://www.opencores.org/lgpl.shtml                     ////
1804
////                                                              ////
1805
//////////////////////////////////////////////////////////////////////
1806
 
1807
// LFSR counter
1808 18 unneback
module vl_cnt_lfsr_ce_zq ( cke, zq, rst, clk);
1809 6 unneback
 
1810
   parameter length = 4;
1811
   input cke;
1812
   output reg zq;
1813
   input rst;
1814
   input clk;
1815
 
1816
   parameter clear_value = 0;
1817
   parameter set_value = 1;
1818
   parameter wrap_value = 8;
1819
   parameter level1_value = 15;
1820
 
1821
   reg  [length:1] qi;
1822
   reg lfsr_fb;
1823
   wire [length:1] q_next;
1824
   reg [32:1] polynom;
1825
   integer i;
1826
 
1827
   always @ (qi)
1828
   begin
1829
        case (length)
1830
         2: polynom = 32'b11;                               // 0x3
1831
         3: polynom = 32'b110;                              // 0x6
1832
         4: polynom = 32'b1100;                             // 0xC
1833
         5: polynom = 32'b10100;                            // 0x14
1834
         6: polynom = 32'b110000;                           // 0x30
1835
         7: polynom = 32'b1100000;                          // 0x60
1836
         8: polynom = 32'b10111000;                         // 0xb8
1837
         9: polynom = 32'b100010000;                        // 0x110
1838
        10: polynom = 32'b1001000000;                       // 0x240
1839
        11: polynom = 32'b10100000000;                      // 0x500
1840
        12: polynom = 32'b100000101001;                     // 0x829
1841
        13: polynom = 32'b1000000001100;                    // 0x100C
1842
        14: polynom = 32'b10000000010101;                   // 0x2015
1843
        15: polynom = 32'b110000000000000;                  // 0x6000
1844
        16: polynom = 32'b1101000000001000;                 // 0xD008
1845
        17: polynom = 32'b10010000000000000;                // 0x12000
1846
        18: polynom = 32'b100000010000000000;               // 0x20400
1847
        19: polynom = 32'b1000000000000100011;              // 0x40023
1848
        20: polynom = 32'b10000010000000000000;             // 0x82000
1849
        21: polynom = 32'b101000000000000000000;            // 0x140000
1850
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1851
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1852
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1853
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1854
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1855
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1856
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1857
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1858
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1859
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1860
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1861
        default: polynom = 32'b0;
1862
        endcase
1863
        lfsr_fb = qi[length];
1864
        for (i=length-1; i>=1; i=i-1) begin
1865
            if (polynom[i])
1866
                lfsr_fb = lfsr_fb  ~^ qi[i];
1867
        end
1868
    end
1869
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1870
 
1871
   always @ (posedge clk or posedge rst)
1872
     if (rst)
1873
       qi <= {length{1'b0}};
1874
     else
1875
     if (cke)
1876
       qi <= q_next;
1877
 
1878
 
1879
 
1880
   always @ (posedge clk or posedge rst)
1881
     if (rst)
1882
       zq <= 1'b1;
1883
     else
1884
     if (cke)
1885
       zq <= q_next == {length{1'b0}};
1886
endmodule
1887
//////////////////////////////////////////////////////////////////////
1888
////                                                              ////
1889
////  Versatile counter                                           ////
1890
////                                                              ////
1891
////  Description                                                 ////
1892
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1893
////  counter                                                     ////
1894
////                                                              ////
1895
////  To Do:                                                      ////
1896
////   - add LFSR with more taps                                  ////
1897
////                                                              ////
1898
////  Author(s):                                                  ////
1899
////      - Michael Unneback, unneback@opencores.org              ////
1900
////        ORSoC AB                                              ////
1901
////                                                              ////
1902
//////////////////////////////////////////////////////////////////////
1903
////                                                              ////
1904
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1905
////                                                              ////
1906
//// This source file may be used and distributed without         ////
1907
//// restriction provided that this copyright statement is not    ////
1908
//// removed from the file and that any derivative work contains  ////
1909
//// the original copyright notice and the associated disclaimer. ////
1910
////                                                              ////
1911
//// This source file is free software; you can redistribute it   ////
1912
//// and/or modify it under the terms of the GNU Lesser General   ////
1913
//// Public License as published by the Free Software Foundation; ////
1914
//// either version 2.1 of the License, or (at your option) any   ////
1915
//// later version.                                               ////
1916
////                                                              ////
1917
//// This source is distributed in the hope that it will be       ////
1918
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1919
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1920
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1921
//// details.                                                     ////
1922
////                                                              ////
1923
//// You should have received a copy of the GNU Lesser General    ////
1924
//// Public License along with this source; if not, download it   ////
1925
//// from http://www.opencores.org/lgpl.shtml                     ////
1926
////                                                              ////
1927
//////////////////////////////////////////////////////////////////////
1928 22 unneback
 
1929
// LFSR counter
1930 27 unneback
module vl_cnt_lfsr_ce_q ( cke, q, rst, clk);
1931
 
1932
   parameter length = 4;
1933
   input cke;
1934
   output [length:1] q;
1935
   input rst;
1936
   input clk;
1937
 
1938
   parameter clear_value = 0;
1939
   parameter set_value = 1;
1940
   parameter wrap_value = 8;
1941
   parameter level1_value = 15;
1942
 
1943
   reg  [length:1] qi;
1944
   reg lfsr_fb;
1945
   wire [length:1] q_next;
1946
   reg [32:1] polynom;
1947
   integer i;
1948
 
1949
   always @ (qi)
1950
   begin
1951
        case (length)
1952
         2: polynom = 32'b11;                               // 0x3
1953
         3: polynom = 32'b110;                              // 0x6
1954
         4: polynom = 32'b1100;                             // 0xC
1955
         5: polynom = 32'b10100;                            // 0x14
1956
         6: polynom = 32'b110000;                           // 0x30
1957
         7: polynom = 32'b1100000;                          // 0x60
1958
         8: polynom = 32'b10111000;                         // 0xb8
1959
         9: polynom = 32'b100010000;                        // 0x110
1960
        10: polynom = 32'b1001000000;                       // 0x240
1961
        11: polynom = 32'b10100000000;                      // 0x500
1962
        12: polynom = 32'b100000101001;                     // 0x829
1963
        13: polynom = 32'b1000000001100;                    // 0x100C
1964
        14: polynom = 32'b10000000010101;                   // 0x2015
1965
        15: polynom = 32'b110000000000000;                  // 0x6000
1966
        16: polynom = 32'b1101000000001000;                 // 0xD008
1967
        17: polynom = 32'b10010000000000000;                // 0x12000
1968
        18: polynom = 32'b100000010000000000;               // 0x20400
1969
        19: polynom = 32'b1000000000000100011;              // 0x40023
1970
        20: polynom = 32'b10000010000000000000;             // 0x82000
1971
        21: polynom = 32'b101000000000000000000;            // 0x140000
1972
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1973
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1974
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1975
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1976
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1977
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1978
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1979
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1980
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1981
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1982
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1983
        default: polynom = 32'b0;
1984
        endcase
1985
        lfsr_fb = qi[length];
1986
        for (i=length-1; i>=1; i=i-1) begin
1987
            if (polynom[i])
1988
                lfsr_fb = lfsr_fb  ~^ qi[i];
1989
        end
1990
    end
1991
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1992
 
1993
   always @ (posedge clk or posedge rst)
1994
     if (rst)
1995
       qi <= {length{1'b0}};
1996
     else
1997
     if (cke)
1998
       qi <= q_next;
1999
 
2000
   assign q = qi;
2001
 
2002
endmodule
2003
//////////////////////////////////////////////////////////////////////
2004
////                                                              ////
2005
////  Versatile counter                                           ////
2006
////                                                              ////
2007
////  Description                                                 ////
2008
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2009
////  counter                                                     ////
2010
////                                                              ////
2011
////  To Do:                                                      ////
2012
////   - add LFSR with more taps                                  ////
2013
////                                                              ////
2014
////  Author(s):                                                  ////
2015
////      - Michael Unneback, unneback@opencores.org              ////
2016
////        ORSoC AB                                              ////
2017
////                                                              ////
2018
//////////////////////////////////////////////////////////////////////
2019
////                                                              ////
2020
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2021
////                                                              ////
2022
//// This source file may be used and distributed without         ////
2023
//// restriction provided that this copyright statement is not    ////
2024
//// removed from the file and that any derivative work contains  ////
2025
//// the original copyright notice and the associated disclaimer. ////
2026
////                                                              ////
2027
//// This source file is free software; you can redistribute it   ////
2028
//// and/or modify it under the terms of the GNU Lesser General   ////
2029
//// Public License as published by the Free Software Foundation; ////
2030
//// either version 2.1 of the License, or (at your option) any   ////
2031
//// later version.                                               ////
2032
////                                                              ////
2033
//// This source is distributed in the hope that it will be       ////
2034
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2035
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2036
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2037
//// details.                                                     ////
2038
////                                                              ////
2039
//// You should have received a copy of the GNU Lesser General    ////
2040
//// Public License along with this source; if not, download it   ////
2041
//// from http://www.opencores.org/lgpl.shtml                     ////
2042
////                                                              ////
2043
//////////////////////////////////////////////////////////////////////
2044
 
2045
// LFSR counter
2046
module vl_cnt_lfsr_ce_clear_q ( clear, cke, q, rst, clk);
2047
 
2048
   parameter length = 4;
2049
   input clear;
2050
   input cke;
2051
   output [length:1] q;
2052
   input rst;
2053
   input clk;
2054
 
2055
   parameter clear_value = 0;
2056
   parameter set_value = 1;
2057
   parameter wrap_value = 8;
2058
   parameter level1_value = 15;
2059
 
2060
   reg  [length:1] qi;
2061
   reg lfsr_fb;
2062
   wire [length:1] q_next;
2063
   reg [32:1] polynom;
2064
   integer i;
2065
 
2066
   always @ (qi)
2067
   begin
2068
        case (length)
2069
         2: polynom = 32'b11;                               // 0x3
2070
         3: polynom = 32'b110;                              // 0x6
2071
         4: polynom = 32'b1100;                             // 0xC
2072
         5: polynom = 32'b10100;                            // 0x14
2073
         6: polynom = 32'b110000;                           // 0x30
2074
         7: polynom = 32'b1100000;                          // 0x60
2075
         8: polynom = 32'b10111000;                         // 0xb8
2076
         9: polynom = 32'b100010000;                        // 0x110
2077
        10: polynom = 32'b1001000000;                       // 0x240
2078
        11: polynom = 32'b10100000000;                      // 0x500
2079
        12: polynom = 32'b100000101001;                     // 0x829
2080
        13: polynom = 32'b1000000001100;                    // 0x100C
2081
        14: polynom = 32'b10000000010101;                   // 0x2015
2082
        15: polynom = 32'b110000000000000;                  // 0x6000
2083
        16: polynom = 32'b1101000000001000;                 // 0xD008
2084
        17: polynom = 32'b10010000000000000;                // 0x12000
2085
        18: polynom = 32'b100000010000000000;               // 0x20400
2086
        19: polynom = 32'b1000000000000100011;              // 0x40023
2087
        20: polynom = 32'b10000010000000000000;             // 0x82000
2088
        21: polynom = 32'b101000000000000000000;            // 0x140000
2089
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2090
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2091
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2092
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2093
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2094
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2095
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2096
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2097
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2098
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2099
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2100
        default: polynom = 32'b0;
2101
        endcase
2102
        lfsr_fb = qi[length];
2103
        for (i=length-1; i>=1; i=i-1) begin
2104
            if (polynom[i])
2105
                lfsr_fb = lfsr_fb  ~^ qi[i];
2106
        end
2107
    end
2108
   assign q_next =  clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2109
 
2110
   always @ (posedge clk or posedge rst)
2111
     if (rst)
2112
       qi <= {length{1'b0}};
2113
     else
2114
     if (cke)
2115
       qi <= q_next;
2116
 
2117
   assign q = qi;
2118
 
2119
endmodule
2120
//////////////////////////////////////////////////////////////////////
2121
////                                                              ////
2122
////  Versatile counter                                           ////
2123
////                                                              ////
2124
////  Description                                                 ////
2125
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2126
////  counter                                                     ////
2127
////                                                              ////
2128
////  To Do:                                                      ////
2129
////   - add LFSR with more taps                                  ////
2130
////                                                              ////
2131
////  Author(s):                                                  ////
2132
////      - Michael Unneback, unneback@opencores.org              ////
2133
////        ORSoC AB                                              ////
2134
////                                                              ////
2135
//////////////////////////////////////////////////////////////////////
2136
////                                                              ////
2137
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2138
////                                                              ////
2139
//// This source file may be used and distributed without         ////
2140
//// restriction provided that this copyright statement is not    ////
2141
//// removed from the file and that any derivative work contains  ////
2142
//// the original copyright notice and the associated disclaimer. ////
2143
////                                                              ////
2144
//// This source file is free software; you can redistribute it   ////
2145
//// and/or modify it under the terms of the GNU Lesser General   ////
2146
//// Public License as published by the Free Software Foundation; ////
2147
//// either version 2.1 of the License, or (at your option) any   ////
2148
//// later version.                                               ////
2149
////                                                              ////
2150
//// This source is distributed in the hope that it will be       ////
2151
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2152
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2153
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2154
//// details.                                                     ////
2155
////                                                              ////
2156
//// You should have received a copy of the GNU Lesser General    ////
2157
//// Public License along with this source; if not, download it   ////
2158
//// from http://www.opencores.org/lgpl.shtml                     ////
2159
////                                                              ////
2160
//////////////////////////////////////////////////////////////////////
2161
 
2162
// LFSR counter
2163 22 unneback
module vl_cnt_lfsr_ce_q_zq ( cke, q, zq, rst, clk);
2164
 
2165
   parameter length = 4;
2166
   input cke;
2167
   output [length:1] q;
2168
   output reg zq;
2169
   input rst;
2170
   input clk;
2171
 
2172
   parameter clear_value = 0;
2173
   parameter set_value = 1;
2174
   parameter wrap_value = 8;
2175
   parameter level1_value = 15;
2176
 
2177
   reg  [length:1] qi;
2178
   reg lfsr_fb;
2179
   wire [length:1] q_next;
2180
   reg [32:1] polynom;
2181
   integer i;
2182
 
2183
   always @ (qi)
2184
   begin
2185
        case (length)
2186
         2: polynom = 32'b11;                               // 0x3
2187
         3: polynom = 32'b110;                              // 0x6
2188
         4: polynom = 32'b1100;                             // 0xC
2189
         5: polynom = 32'b10100;                            // 0x14
2190
         6: polynom = 32'b110000;                           // 0x30
2191
         7: polynom = 32'b1100000;                          // 0x60
2192
         8: polynom = 32'b10111000;                         // 0xb8
2193
         9: polynom = 32'b100010000;                        // 0x110
2194
        10: polynom = 32'b1001000000;                       // 0x240
2195
        11: polynom = 32'b10100000000;                      // 0x500
2196
        12: polynom = 32'b100000101001;                     // 0x829
2197
        13: polynom = 32'b1000000001100;                    // 0x100C
2198
        14: polynom = 32'b10000000010101;                   // 0x2015
2199
        15: polynom = 32'b110000000000000;                  // 0x6000
2200
        16: polynom = 32'b1101000000001000;                 // 0xD008
2201
        17: polynom = 32'b10010000000000000;                // 0x12000
2202
        18: polynom = 32'b100000010000000000;               // 0x20400
2203
        19: polynom = 32'b1000000000000100011;              // 0x40023
2204
        20: polynom = 32'b10000010000000000000;             // 0x82000
2205
        21: polynom = 32'b101000000000000000000;            // 0x140000
2206
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2207
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2208
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2209
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2210
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2211
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2212
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2213
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2214
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2215
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2216
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2217
        default: polynom = 32'b0;
2218
        endcase
2219
        lfsr_fb = qi[length];
2220
        for (i=length-1; i>=1; i=i-1) begin
2221
            if (polynom[i])
2222
                lfsr_fb = lfsr_fb  ~^ qi[i];
2223
        end
2224
    end
2225
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2226
 
2227
   always @ (posedge clk or posedge rst)
2228
     if (rst)
2229
       qi <= {length{1'b0}};
2230
     else
2231
     if (cke)
2232
       qi <= q_next;
2233
 
2234
   assign q = qi;
2235
 
2236
 
2237
   always @ (posedge clk or posedge rst)
2238
     if (rst)
2239
       zq <= 1'b1;
2240
     else
2241
     if (cke)
2242
       zq <= q_next == {length{1'b0}};
2243
endmodule
2244
//////////////////////////////////////////////////////////////////////
2245
////                                                              ////
2246
////  Versatile counter                                           ////
2247
////                                                              ////
2248
////  Description                                                 ////
2249
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2250
////  counter                                                     ////
2251
////                                                              ////
2252
////  To Do:                                                      ////
2253
////   - add LFSR with more taps                                  ////
2254
////                                                              ////
2255
////  Author(s):                                                  ////
2256
////      - Michael Unneback, unneback@opencores.org              ////
2257
////        ORSoC AB                                              ////
2258
////                                                              ////
2259
//////////////////////////////////////////////////////////////////////
2260
////                                                              ////
2261
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2262
////                                                              ////
2263
//// This source file may be used and distributed without         ////
2264
//// restriction provided that this copyright statement is not    ////
2265
//// removed from the file and that any derivative work contains  ////
2266
//// the original copyright notice and the associated disclaimer. ////
2267
////                                                              ////
2268
//// This source file is free software; you can redistribute it   ////
2269
//// and/or modify it under the terms of the GNU Lesser General   ////
2270
//// Public License as published by the Free Software Foundation; ////
2271
//// either version 2.1 of the License, or (at your option) any   ////
2272
//// later version.                                               ////
2273
////                                                              ////
2274
//// This source is distributed in the hope that it will be       ////
2275
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2276
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2277
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2278
//// details.                                                     ////
2279
////                                                              ////
2280
//// You should have received a copy of the GNU Lesser General    ////
2281
//// Public License along with this source; if not, download it   ////
2282
//// from http://www.opencores.org/lgpl.shtml                     ////
2283
////                                                              ////
2284
//////////////////////////////////////////////////////////////////////
2285 6 unneback
 
2286
// LFSR counter
2287 18 unneback
module vl_cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk);
2288 6 unneback
 
2289
   parameter length = 4;
2290
   input cke;
2291
   input rew;
2292
   output reg level1;
2293
   input rst;
2294
   input clk;
2295
 
2296
   parameter clear_value = 0;
2297
   parameter set_value = 1;
2298
   parameter wrap_value = 8;
2299
   parameter level1_value = 15;
2300
 
2301 29 unneback
   wire clear;
2302 30 unneback
   assign clear = 1'b0;
2303 6 unneback
   reg  [length:1] qi;
2304
   reg lfsr_fb, lfsr_fb_rew;
2305
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2306
   reg [32:1] polynom_rew;
2307
   integer j;
2308
   reg [32:1] polynom;
2309
   integer i;
2310
 
2311
   always @ (qi)
2312
   begin
2313
        case (length)
2314
         2: polynom = 32'b11;                               // 0x3
2315
         3: polynom = 32'b110;                              // 0x6
2316
         4: polynom = 32'b1100;                             // 0xC
2317
         5: polynom = 32'b10100;                            // 0x14
2318
         6: polynom = 32'b110000;                           // 0x30
2319
         7: polynom = 32'b1100000;                          // 0x60
2320
         8: polynom = 32'b10111000;                         // 0xb8
2321
         9: polynom = 32'b100010000;                        // 0x110
2322
        10: polynom = 32'b1001000000;                       // 0x240
2323
        11: polynom = 32'b10100000000;                      // 0x500
2324
        12: polynom = 32'b100000101001;                     // 0x829
2325
        13: polynom = 32'b1000000001100;                    // 0x100C
2326
        14: polynom = 32'b10000000010101;                   // 0x2015
2327
        15: polynom = 32'b110000000000000;                  // 0x6000
2328
        16: polynom = 32'b1101000000001000;                 // 0xD008
2329
        17: polynom = 32'b10010000000000000;                // 0x12000
2330
        18: polynom = 32'b100000010000000000;               // 0x20400
2331
        19: polynom = 32'b1000000000000100011;              // 0x40023
2332
        20: polynom = 32'b10000010000000000000;             // 0x82000
2333
        21: polynom = 32'b101000000000000000000;            // 0x140000
2334
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2335
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2336
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2337
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2338
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2339
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2340
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2341
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2342
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2343
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2344
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2345
        default: polynom = 32'b0;
2346
        endcase
2347
        lfsr_fb = qi[length];
2348
        for (i=length-1; i>=1; i=i-1) begin
2349
            if (polynom[i])
2350
                lfsr_fb = lfsr_fb  ~^ qi[i];
2351
        end
2352
    end
2353
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2354
   always @ (qi)
2355
   begin
2356
        case (length)
2357
         2: polynom_rew = 32'b11;
2358
         3: polynom_rew = 32'b110;
2359
         4: polynom_rew = 32'b1100;
2360
         5: polynom_rew = 32'b10100;
2361
         6: polynom_rew = 32'b110000;
2362
         7: polynom_rew = 32'b1100000;
2363
         8: polynom_rew = 32'b10111000;
2364
         9: polynom_rew = 32'b100010000;
2365
        10: polynom_rew = 32'b1001000000;
2366
        11: polynom_rew = 32'b10100000000;
2367
        12: polynom_rew = 32'b100000101001;
2368
        13: polynom_rew = 32'b1000000001100;
2369
        14: polynom_rew = 32'b10000000010101;
2370
        15: polynom_rew = 32'b110000000000000;
2371
        16: polynom_rew = 32'b1101000000001000;
2372
        17: polynom_rew = 32'b10010000000000000;
2373
        18: polynom_rew = 32'b100000010000000000;
2374
        19: polynom_rew = 32'b1000000000000100011;
2375
        20: polynom_rew = 32'b10000010000000000000;
2376
        21: polynom_rew = 32'b101000000000000000000;
2377
        22: polynom_rew = 32'b1100000000000000000000;
2378
        23: polynom_rew = 32'b10000100000000000000000;
2379
        24: polynom_rew = 32'b111000010000000000000000;
2380
        25: polynom_rew = 32'b1001000000000000000000000;
2381
        26: polynom_rew = 32'b10000000000000000000100011;
2382
        27: polynom_rew = 32'b100000000000000000000010011;
2383
        28: polynom_rew = 32'b1100100000000000000000000000;
2384
        29: polynom_rew = 32'b10100000000000000000000000000;
2385
        30: polynom_rew = 32'b100000000000000000000000101001;
2386
        31: polynom_rew = 32'b1001000000000000000000000000000;
2387
        32: polynom_rew = 32'b10000000001000000000000000000011;
2388
        default: polynom_rew = 32'b0;
2389
        endcase
2390
        // rotate left
2391
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
2392
        lfsr_fb_rew = qi[length];
2393
        for (i=length-1; i>=1; i=i-1) begin
2394
            if (polynom_rew[i])
2395
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
2396
        end
2397
    end
2398
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
2399
   assign q_next = rew ? q_next_rew : q_next_fw;
2400
 
2401
   always @ (posedge clk or posedge rst)
2402
     if (rst)
2403
       qi <= {length{1'b0}};
2404
     else
2405
     if (cke)
2406
       qi <= q_next;
2407
 
2408
 
2409
 
2410
    always @ (posedge clk or posedge rst)
2411
    if (rst)
2412
        level1 <= 1'b0;
2413
    else
2414
    if (cke)
2415 29 unneback
    if (clear)
2416
        level1 <= 1'b0;
2417
    else if (q_next == level1_value)
2418 6 unneback
        level1 <= 1'b1;
2419
    else if (qi == level1_value & rew)
2420
        level1 <= 1'b0;
2421
endmodule
2422
//////////////////////////////////////////////////////////////////////
2423
////                                                              ////
2424
////  Versatile counter                                           ////
2425
////                                                              ////
2426
////  Description                                                 ////
2427
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2428
////  counter                                                     ////
2429
////                                                              ////
2430
////  To Do:                                                      ////
2431
////   - add LFSR with more taps                                  ////
2432
////                                                              ////
2433
////  Author(s):                                                  ////
2434
////      - Michael Unneback, unneback@opencores.org              ////
2435
////        ORSoC AB                                              ////
2436
////                                                              ////
2437
//////////////////////////////////////////////////////////////////////
2438
////                                                              ////
2439
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2440
////                                                              ////
2441
//// This source file may be used and distributed without         ////
2442
//// restriction provided that this copyright statement is not    ////
2443
//// removed from the file and that any derivative work contains  ////
2444
//// the original copyright notice and the associated disclaimer. ////
2445
////                                                              ////
2446
//// This source file is free software; you can redistribute it   ////
2447
//// and/or modify it under the terms of the GNU Lesser General   ////
2448
//// Public License as published by the Free Software Foundation; ////
2449
//// either version 2.1 of the License, or (at your option) any   ////
2450
//// later version.                                               ////
2451
////                                                              ////
2452
//// This source is distributed in the hope that it will be       ////
2453
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2454
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2455
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2456
//// details.                                                     ////
2457
////                                                              ////
2458
//// You should have received a copy of the GNU Lesser General    ////
2459
//// Public License along with this source; if not, download it   ////
2460
//// from http://www.opencores.org/lgpl.shtml                     ////
2461
////                                                              ////
2462
//////////////////////////////////////////////////////////////////////
2463
 
2464
// GRAY counter
2465 18 unneback
module vl_cnt_gray ( q, rst, clk);
2466 6 unneback
 
2467
   parameter length = 4;
2468
   output reg [length:1] q;
2469
   input rst;
2470
   input clk;
2471
 
2472
   parameter clear_value = 0;
2473
   parameter set_value = 1;
2474
   parameter wrap_value = 8;
2475
   parameter level1_value = 15;
2476
 
2477
   reg  [length:1] qi;
2478
   wire [length:1] q_next;
2479
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2480
 
2481
   always @ (posedge clk or posedge rst)
2482
     if (rst)
2483
       qi <= {length{1'b0}};
2484
     else
2485
       qi <= q_next;
2486
 
2487
   always @ (posedge clk or posedge rst)
2488
     if (rst)
2489
       q <= {length{1'b0}};
2490
     else
2491
         q <= (q_next>>1) ^ q_next;
2492
 
2493
endmodule
2494
//////////////////////////////////////////////////////////////////////
2495
////                                                              ////
2496
////  Versatile counter                                           ////
2497
////                                                              ////
2498
////  Description                                                 ////
2499
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2500
////  counter                                                     ////
2501
////                                                              ////
2502
////  To Do:                                                      ////
2503
////   - add LFSR with more taps                                  ////
2504
////                                                              ////
2505
////  Author(s):                                                  ////
2506
////      - Michael Unneback, unneback@opencores.org              ////
2507
////        ORSoC AB                                              ////
2508
////                                                              ////
2509
//////////////////////////////////////////////////////////////////////
2510
////                                                              ////
2511
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2512
////                                                              ////
2513
//// This source file may be used and distributed without         ////
2514
//// restriction provided that this copyright statement is not    ////
2515
//// removed from the file and that any derivative work contains  ////
2516
//// the original copyright notice and the associated disclaimer. ////
2517
////                                                              ////
2518
//// This source file is free software; you can redistribute it   ////
2519
//// and/or modify it under the terms of the GNU Lesser General   ////
2520
//// Public License as published by the Free Software Foundation; ////
2521
//// either version 2.1 of the License, or (at your option) any   ////
2522
//// later version.                                               ////
2523
////                                                              ////
2524
//// This source is distributed in the hope that it will be       ////
2525
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2526
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2527
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2528
//// details.                                                     ////
2529
////                                                              ////
2530
//// You should have received a copy of the GNU Lesser General    ////
2531
//// Public License along with this source; if not, download it   ////
2532
//// from http://www.opencores.org/lgpl.shtml                     ////
2533
////                                                              ////
2534
//////////////////////////////////////////////////////////////////////
2535
 
2536
// GRAY counter
2537 18 unneback
module vl_cnt_gray_ce ( cke, q, rst, clk);
2538 6 unneback
 
2539
   parameter length = 4;
2540
   input cke;
2541
   output reg [length:1] q;
2542
   input rst;
2543
   input clk;
2544
 
2545
   parameter clear_value = 0;
2546
   parameter set_value = 1;
2547
   parameter wrap_value = 8;
2548
   parameter level1_value = 15;
2549
 
2550
   reg  [length:1] qi;
2551
   wire [length:1] q_next;
2552
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2553
 
2554
   always @ (posedge clk or posedge rst)
2555
     if (rst)
2556
       qi <= {length{1'b0}};
2557
     else
2558
     if (cke)
2559
       qi <= q_next;
2560
 
2561
   always @ (posedge clk or posedge rst)
2562
     if (rst)
2563
       q <= {length{1'b0}};
2564
     else
2565
       if (cke)
2566
         q <= (q_next>>1) ^ q_next;
2567
 
2568
endmodule
2569
//////////////////////////////////////////////////////////////////////
2570
////                                                              ////
2571
////  Versatile counter                                           ////
2572
////                                                              ////
2573
////  Description                                                 ////
2574
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2575
////  counter                                                     ////
2576
////                                                              ////
2577
////  To Do:                                                      ////
2578
////   - add LFSR with more taps                                  ////
2579
////                                                              ////
2580
////  Author(s):                                                  ////
2581
////      - Michael Unneback, unneback@opencores.org              ////
2582
////        ORSoC AB                                              ////
2583
////                                                              ////
2584
//////////////////////////////////////////////////////////////////////
2585
////                                                              ////
2586
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2587
////                                                              ////
2588
//// This source file may be used and distributed without         ////
2589
//// restriction provided that this copyright statement is not    ////
2590
//// removed from the file and that any derivative work contains  ////
2591
//// the original copyright notice and the associated disclaimer. ////
2592
////                                                              ////
2593
//// This source file is free software; you can redistribute it   ////
2594
//// and/or modify it under the terms of the GNU Lesser General   ////
2595
//// Public License as published by the Free Software Foundation; ////
2596
//// either version 2.1 of the License, or (at your option) any   ////
2597
//// later version.                                               ////
2598
////                                                              ////
2599
//// This source is distributed in the hope that it will be       ////
2600
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2601
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2602
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2603
//// details.                                                     ////
2604
////                                                              ////
2605
//// You should have received a copy of the GNU Lesser General    ////
2606
//// Public License along with this source; if not, download it   ////
2607
//// from http://www.opencores.org/lgpl.shtml                     ////
2608
////                                                              ////
2609
//////////////////////////////////////////////////////////////////////
2610
 
2611
// GRAY counter
2612 18 unneback
module vl_cnt_gray_ce_bin ( cke, q, q_bin, rst, clk);
2613 6 unneback
 
2614
   parameter length = 4;
2615
   input cke;
2616
   output reg [length:1] q;
2617
   output [length:1] q_bin;
2618
   input rst;
2619
   input clk;
2620
 
2621
   parameter clear_value = 0;
2622
   parameter set_value = 1;
2623
   parameter wrap_value = 8;
2624
   parameter level1_value = 15;
2625
 
2626
   reg  [length:1] qi;
2627
   wire [length:1] q_next;
2628
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2629
 
2630
   always @ (posedge clk or posedge rst)
2631
     if (rst)
2632
       qi <= {length{1'b0}};
2633
     else
2634
     if (cke)
2635
       qi <= q_next;
2636
 
2637
   always @ (posedge clk or posedge rst)
2638
     if (rst)
2639
       q <= {length{1'b0}};
2640
     else
2641
       if (cke)
2642
         q <= (q_next>>1) ^ q_next;
2643
 
2644
   assign q_bin = qi;
2645
 
2646
endmodule
2647
//////////////////////////////////////////////////////////////////////
2648
////                                                              ////
2649
////  Versatile library, counters                                 ////
2650
////                                                              ////
2651
////  Description                                                 ////
2652
////  counters                                                    ////
2653
////                                                              ////
2654
////                                                              ////
2655
////  To Do:                                                      ////
2656
////   - add more counters                                        ////
2657
////                                                              ////
2658
////  Author(s):                                                  ////
2659
////      - Michael Unneback, unneback@opencores.org              ////
2660
////        ORSoC AB                                              ////
2661
////                                                              ////
2662
//////////////////////////////////////////////////////////////////////
2663
////                                                              ////
2664
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2665
////                                                              ////
2666
//// This source file may be used and distributed without         ////
2667
//// restriction provided that this copyright statement is not    ////
2668
//// removed from the file and that any derivative work contains  ////
2669
//// the original copyright notice and the associated disclaimer. ////
2670
////                                                              ////
2671
//// This source file is free software; you can redistribute it   ////
2672
//// and/or modify it under the terms of the GNU Lesser General   ////
2673
//// Public License as published by the Free Software Foundation; ////
2674
//// either version 2.1 of the License, or (at your option) any   ////
2675
//// later version.                                               ////
2676
////                                                              ////
2677
//// This source is distributed in the hope that it will be       ////
2678
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2679
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2680
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2681
//// details.                                                     ////
2682
////                                                              ////
2683
//// You should have received a copy of the GNU Lesser General    ////
2684
//// Public License along with this source; if not, download it   ////
2685
//// from http://www.opencores.org/lgpl.shtml                     ////
2686
////                                                              ////
2687
//////////////////////////////////////////////////////////////////////
2688
 
2689 18 unneback
module vl_cnt_shreg_wrap ( q, rst, clk);
2690 6 unneback
 
2691
   parameter length = 4;
2692
   output reg [0:length-1] q;
2693
   input rst;
2694
   input clk;
2695
 
2696
    always @ (posedge clk or posedge rst)
2697
    if (rst)
2698
        q <= {1'b1,{length-1{1'b0}}};
2699
    else
2700
        q <= {q[length-1],q[0:length-2]};
2701
 
2702
endmodule
2703
 
2704 18 unneback
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
2705 6 unneback
 
2706
   parameter length = 4;
2707
   input cke;
2708
   output reg [0:length-1] q;
2709
   input rst;
2710
   input clk;
2711
 
2712
    always @ (posedge clk or posedge rst)
2713
    if (rst)
2714
        q <= {1'b1,{length-1{1'b0}}};
2715
    else
2716
        if (cke)
2717
            q <= {q[length-1],q[0:length-2]};
2718
 
2719
endmodule
2720
 
2721 18 unneback
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
2722 6 unneback
 
2723
   parameter length = 4;
2724
   input cke, clear;
2725
   output reg [0:length-1] q;
2726
   input rst;
2727
   input clk;
2728
 
2729
    always @ (posedge clk or posedge rst)
2730