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1 6 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  Versatile library, clock and reset                          ////
4
////                                                              ////
5
////  Description                                                 ////
6
////  Logic related to clock and reset                            ////
7
////                                                              ////
8
////                                                              ////
9
////  To Do:                                                      ////
10
////   - add more different registers                             ////
11
////                                                              ////
12
////  Author(s):                                                  ////
13
////      - Michael Unneback, unneback@opencores.org              ////
14
////        ORSoC AB                                              ////
15
////                                                              ////
16
//////////////////////////////////////////////////////////////////////
17
////                                                              ////
18
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
19
////                                                              ////
20
//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
36
////                                                              ////
37
//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
 
43
// Global buffer
44
// usage:
45
// use to enable global buffers for high fan out signals such as clock and reset
46
 
47
`ifdef ACTEL
48
 
49
`timescale 1 ns/100 ps
50
// Version: 8.4 8.4.0.33
51
module gbuf(GL,CLK);
52
output GL;
53
input  CLK;
54
 
55
    wire GND;
56
 
57
    GND GND_1_net(.Y(GND));
58
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
59
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
60
 
61
endmodule
62
`timescale 1 ns/1 ns
63
module vl_gbuf ( i, o);
64
input i;
65
output o;
66
`ifdef SIM_GBUF
67
assign o=i;
68
`else
69
gbuf gbuf_i0 ( .CLK(i), .GL(o));
70
`endif
71
endmodule
72 33 unneback
 
73 6 unneback
`else
74 33 unneback
 
75 6 unneback
`ifdef ALTERA
76 21 unneback
//altera
77 33 unneback
module vl_gbuf ( i, o);
78
input i;
79
output o;
80
assign o = i;
81
endmodule
82
 
83 6 unneback
`else
84
 
85
`timescale 1 ns/100 ps
86
module vl_gbuf ( i, o);
87
input i;
88
output o;
89
assign o = i;
90
endmodule
91
`endif // ALTERA
92
`endif //ACTEL
93
 
94
// sync reset
95 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
96 6 unneback
// output active high global reset sync with two DFFs 
97
`timescale 1 ns/100 ps
98
module vl_sync_rst ( rst_n_i, rst_o, clk);
99
input rst_n_i, clk;
100
output rst_o;
101 18 unneback
reg [1:0] tmp;
102 6 unneback
always @ (posedge clk or negedge rst_n_i)
103
if (!rst_n_i)
104 17 unneback
        tmp <= 2'b11;
105 6 unneback
else
106 33 unneback
        tmp <= {1'b0,tmp[1]};
107 17 unneback
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
108 6 unneback
endmodule
109
 
110
// vl_pll
111
`ifdef ACTEL
112 32 unneback
///////////////////////////////////////////////////////////////////////////////
113 17 unneback
`timescale 1 ps/1 ps
114 6 unneback
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
115
parameter index = 0;
116
parameter number_of_clk = 1;
117 17 unneback
parameter period_time_0 = 20000;
118
parameter period_time_1 = 20000;
119
parameter period_time_2 = 20000;
120
parameter lock_delay = 2000000;
121 6 unneback
input clk_i, rst_n_i;
122
output lock;
123
output reg [0:number_of_clk-1] clk_o;
124
output [0:number_of_clk-1] rst_o;
125
 
126
`ifdef SIM_PLL
127
 
128
always
129
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
130
 
131
generate if (number_of_clk > 1)
132
always
133
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
134
endgenerate
135
 
136
generate if (number_of_clk > 2)
137
always
138
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
139
endgenerate
140
 
141
genvar i;
142
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
143
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
144
end
145
endgenerate
146
 
147
assign #lock_delay lock = rst_n_i;
148
 
149
endmodule
150
`else
151
generate if (number_of_clk==1 & index==0) begin
152
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
153
end
154
endgenerate // index==0
155
generate if (number_of_clk==1 & index==1) begin
156
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
157
end
158
endgenerate // index==1
159
generate if (number_of_clk==1 & index==2) begin
160
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
161
end
162
endgenerate // index==2
163
generate if (number_of_clk==1 & index==3) begin
164
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
165
end
166
endgenerate // index==0
167
 
168
generate if (number_of_clk==2 & index==0) begin
169
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
170
end
171
endgenerate // index==0
172
generate if (number_of_clk==2 & index==1) begin
173
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
174
end
175
endgenerate // index==1
176
generate if (number_of_clk==2 & index==2) begin
177
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
178
end
179
endgenerate // index==2
180
generate if (number_of_clk==2 & index==3) begin
181
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
182
end
183
endgenerate // index==0
184
 
185
generate if (number_of_clk==3 & index==0) begin
186
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
187
end
188
endgenerate // index==0
189
generate if (number_of_clk==3 & index==1) begin
190
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
191
end
192
endgenerate // index==1
193
generate if (number_of_clk==3 & index==2) begin
194
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
195
end
196
endgenerate // index==2
197
generate if (number_of_clk==3 & index==3) begin
198
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
199
end
200
endgenerate // index==0
201
 
202
genvar i;
203
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
204
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
205
end
206
endgenerate
207
endmodule
208
`endif
209 32 unneback
///////////////////////////////////////////////////////////////////////////////
210 6 unneback
 
211
`else
212
 
213 32 unneback
///////////////////////////////////////////////////////////////////////////////
214 6 unneback
`ifdef ALTERA
215
 
216 32 unneback
`timescale 1 ps/1 ps
217
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
218
parameter index = 0;
219
parameter number_of_clk = 1;
220
parameter period_time_0 = 20000;
221
parameter period_time_1 = 20000;
222
parameter period_time_2 = 20000;
223
parameter period_time_3 = 20000;
224
parameter period_time_4 = 20000;
225
parameter lock_delay = 2000000;
226
input clk_i, rst_n_i;
227
output lock;
228
output reg [0:number_of_clk-1] clk_o;
229
output [0:number_of_clk-1] rst_o;
230
 
231
`ifdef SIM_PLL
232
 
233
always
234
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
235
 
236
generate if (number_of_clk > 1)
237
always
238
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
239
endgenerate
240
 
241
generate if (number_of_clk > 2)
242
always
243
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
244
endgenerate
245
 
246 33 unneback
generate if (number_of_clk > 3)
247 32 unneback
always
248
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
249
endgenerate
250
 
251 33 unneback
generate if (number_of_clk > 4)
252 32 unneback
always
253
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
254
endgenerate
255
 
256
genvar i;
257
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
258
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
259
end
260
endgenerate
261
 
262 33 unneback
//assign #lock_delay lock = rst_n_i;
263
assign lock = rst_n_i;
264 32 unneback
 
265
endmodule
266 6 unneback
`else
267
 
268 33 unneback
`ifdef VL_PLL0
269
`ifdef VL_PLL0_CLK1
270
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
271
`endif
272
`ifdef VL_PLL0_CLK2
273
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
274
`endif
275
`ifdef VL_PLL0_CLK3
276
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
277
`endif
278
`ifdef VL_PLL0_CLK4
279
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
280
`endif
281
`ifdef VL_PLL0_CLK5
282
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
283
`endif
284
`endif
285 32 unneback
 
286 33 unneback
`ifdef VL_PLL1
287
`ifdef VL_PLL1_CLK1
288
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
289
`endif
290
`ifdef VL_PLL1_CLK2
291
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
292
`endif
293
`ifdef VL_PLL1_CLK3
294
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
295
`endif
296
`ifdef VL_PLL1_CLK4
297
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
298
`endif
299
`ifdef VL_PLL1_CLK5
300
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
301
`endif
302
`endif
303 32 unneback
 
304 33 unneback
`ifdef VL_PLL2
305
`ifdef VL_PLL2_CLK1
306
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
307
`endif
308
`ifdef VL_PLL2_CLK2
309
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
310
`endif
311
`ifdef VL_PLL2_CLK3
312
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
313
`endif
314
`ifdef VL_PLL2_CLK4
315
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
316
`endif
317
`ifdef VL_PLL2_CLK5
318
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
319
`endif
320
`endif
321 32 unneback
 
322 33 unneback
`ifdef VL_PLL3
323
`ifdef VL_PLL3_CLK1
324
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
325
`endif
326
`ifdef VL_PLL3_CLK2
327
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
328
`endif
329
`ifdef VL_PLL3_CLK3
330
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
331
`endif
332
`ifdef VL_PLL3_CLK4
333
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
334
`endif
335
`ifdef VL_PLL3_CLK5
336
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
337
`endif
338
`endif
339 32 unneback
 
340
genvar i;
341
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
342 33 unneback
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
343 32 unneback
end
344
endgenerate
345
endmodule
346
`endif
347
///////////////////////////////////////////////////////////////////////////////
348
 
349
`else
350
 
351 6 unneback
// generic PLL
352 17 unneback
`timescale 1 ps/1 ps
353 6 unneback
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
354
parameter index = 0;
355
parameter number_of_clk = 1;
356 17 unneback
parameter period_time_0 = 20000;
357
parameter period_time_1 = 20000;
358
parameter period_time_2 = 20000;
359 6 unneback
parameter lock_delay = 2000;
360
input clk_i, rst_n_i;
361
output lock;
362
output reg [0:number_of_clk-1] clk_o;
363
output [0:number_of_clk-1] rst_o;
364
 
365
always
366
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
367
 
368
generate if (number_of_clk > 1)
369
always
370
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
371
endgenerate
372
 
373
generate if (number_of_clk > 2)
374
always
375
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
376
endgenerate
377
 
378
genvar i;
379
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
380
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
381
end
382
endgenerate
383
 
384
assign #lock_delay lock = rst_n_i;
385
 
386
endmodule
387
 
388
`endif //altera
389 17 unneback
`endif //actel
390
//////////////////////////////////////////////////////////////////////
391 6 unneback
////                                                              ////
392
////  Versatile library, registers                                ////
393
////                                                              ////
394
////  Description                                                 ////
395
////  Different type of registers                                 ////
396
////                                                              ////
397
////                                                              ////
398
////  To Do:                                                      ////
399
////   - add more different registers                             ////
400
////                                                              ////
401
////  Author(s):                                                  ////
402
////      - Michael Unneback, unneback@opencores.org              ////
403
////        ORSoC AB                                              ////
404
////                                                              ////
405
//////////////////////////////////////////////////////////////////////
406
////                                                              ////
407
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
408
////                                                              ////
409
//// This source file may be used and distributed without         ////
410
//// restriction provided that this copyright statement is not    ////
411
//// removed from the file and that any derivative work contains  ////
412
//// the original copyright notice and the associated disclaimer. ////
413
////                                                              ////
414
//// This source file is free software; you can redistribute it   ////
415
//// and/or modify it under the terms of the GNU Lesser General   ////
416
//// Public License as published by the Free Software Foundation; ////
417
//// either version 2.1 of the License, or (at your option) any   ////
418
//// later version.                                               ////
419
////                                                              ////
420
//// This source is distributed in the hope that it will be       ////
421
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
422
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
423
//// PURPOSE.  See the GNU Lesser General Public License for more ////
424
//// details.                                                     ////
425
////                                                              ////
426
//// You should have received a copy of the GNU Lesser General    ////
427
//// Public License along with this source; if not, download it   ////
428
//// from http://www.opencores.org/lgpl.shtml                     ////
429
////                                                              ////
430
//////////////////////////////////////////////////////////////////////
431
 
432 18 unneback
module vl_dff ( d, q, clk, rst);
433 6 unneback
 
434
        parameter width = 1;
435
        parameter reset_value = 0;
436
 
437
        input [width-1:0] d;
438
        input clk, rst;
439
        output reg [width-1:0] q;
440
 
441
        always @ (posedge clk or posedge rst)
442
        if (rst)
443
                q <= reset_value;
444
        else
445
                q <= d;
446
 
447
endmodule
448
 
449 18 unneback
module vl_dff_array ( d, q, clk, rst);
450 6 unneback
 
451
        parameter width = 1;
452
        parameter depth = 2;
453
        parameter reset_value = 1'b0;
454
 
455
        input [width-1:0] d;
456
        input clk, rst;
457
        output [width-1:0] q;
458
        reg  [0:depth-1] q_tmp [width-1:0];
459
        integer i;
460
        always @ (posedge clk or posedge rst)
461
        if (rst) begin
462
            for (i=0;i<depth;i=i+1)
463
                q_tmp[i] <= {width{reset_value}};
464
        end else begin
465
            q_tmp[0] <= d;
466
            for (i=1;i<depth;i=i+1)
467
                q_tmp[i] <= q_tmp[i-1];
468
        end
469
 
470
    assign q = q_tmp[depth-1];
471
 
472
endmodule
473
 
474 18 unneback
module vl_dff_ce ( d, ce, q, clk, rst);
475 6 unneback
 
476
        parameter width = 1;
477
        parameter reset_value = 0;
478
 
479
        input [width-1:0] d;
480
        input ce, clk, rst;
481
        output reg [width-1:0] q;
482
 
483
        always @ (posedge clk or posedge rst)
484
        if (rst)
485
                q <= reset_value;
486
        else
487
                if (ce)
488
                        q <= d;
489
 
490
endmodule
491
 
492 18 unneback
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
493 8 unneback
 
494
        parameter width = 1;
495
        parameter reset_value = 0;
496
 
497
        input [width-1:0] d;
498 10 unneback
        input ce, clear, clk, rst;
499 8 unneback
        output reg [width-1:0] q;
500
 
501
        always @ (posedge clk or posedge rst)
502
        if (rst)
503
            q <= reset_value;
504
        else
505
            if (ce)
506
                if (clear)
507
                    q <= {width{1'b0}};
508
                else
509
                    q <= d;
510
 
511
endmodule
512
 
513 24 unneback
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
514
 
515
        parameter width = 1;
516
        parameter reset_value = 0;
517
 
518
        input [width-1:0] d;
519
        input ce, set, clk, rst;
520
        output reg [width-1:0] q;
521
 
522
        always @ (posedge clk or posedge rst)
523
        if (rst)
524
            q <= reset_value;
525
        else
526
            if (ce)
527
                if (set)
528
                    q <= {width{1'b1}};
529
                else
530
                    q <= d;
531
 
532
endmodule
533
 
534 29 unneback
module vl_spr ( sp, r, q, clk, rst);
535
 
536
        parameter width = 1;
537
        parameter reset_value = 0;
538
 
539
        input sp, r;
540
        output reg q;
541
        input clk, rst;
542
 
543
        always @ (posedge clk or posedge rst)
544
        if (rst)
545
            q <= reset_value;
546
        else
547
            if (sp)
548
                q <= 1'b1;
549
            else if (r)
550
                q <= 1'b0;
551
 
552
endmodule
553
 
554
module vl_srp ( s, rp, q, clk, rst);
555
 
556
        parameter width = 1;
557
        parameter reset_value = 0;
558
 
559
        input s, rp;
560
        output reg q;
561
        input clk, rst;
562
 
563
        always @ (posedge clk or posedge rst)
564
        if (rst)
565
            q <= reset_value;
566
        else
567
            if (rp)
568
                q <= 1'b0;
569
            else if (s)
570
                q <= 1'b1;
571
 
572
endmodule
573
 
574
 
575 6 unneback
`ifdef ALTERA
576
// megafunction wizard: %LPM_FF%
577
// GENERATION: STANDARD
578
// VERSION: WM1.0
579
// MODULE: lpm_ff 
580
 
581
// ============================================================
582
// File Name: dff_sr.v
583
// Megafunction Name(s):
584
//                      lpm_ff
585
//
586
// Simulation Library Files(s):
587
//                      lpm
588
// ============================================================
589
// ************************************************************
590
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
591
//
592
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
593
// ************************************************************
594
 
595
 
596
//Copyright (C) 1991-2010 Altera Corporation
597
//Your use of Altera Corporation's design tools, logic functions 
598
//and other software and tools, and its AMPP partner logic 
599
//functions, and any output files from any of the foregoing 
600
//(including device programming or simulation files), and any 
601
//associated documentation or information are expressly subject 
602
//to the terms and conditions of the Altera Program License 
603
//Subscription Agreement, Altera MegaCore Function License 
604
//Agreement, or other applicable license agreement, including, 
605
//without limitation, that your use is for the sole purpose of 
606
//programming logic devices manufactured by Altera and sold by 
607
//Altera or its authorized distributors.  Please refer to the 
608
//applicable agreement for further details.
609
 
610
 
611
// synopsys translate_off
612
`timescale 1 ps / 1 ps
613
// synopsys translate_on
614 18 unneback
module vl_dff_sr (
615 6 unneback
        aclr,
616
        aset,
617
        clock,
618
        data,
619
        q);
620
 
621
        input     aclr;
622
        input     aset;
623
        input     clock;
624
        input     data;
625
        output    q;
626
 
627
        wire [0:0] sub_wire0;
628
        wire [0:0] sub_wire1 = sub_wire0[0:0];
629
        wire  q = sub_wire1;
630
        wire  sub_wire2 = data;
631
        wire  sub_wire3 = sub_wire2;
632
 
633
        lpm_ff  lpm_ff_component (
634
                                .aclr (aclr),
635
                                .clock (clock),
636
                                .data (sub_wire3),
637
                                .aset (aset),
638
                                .q (sub_wire0)
639
                                // synopsys translate_off
640
                                ,
641
                                .aload (),
642
                                .enable (),
643
                                .sclr (),
644
                                .sload (),
645
                                .sset ()
646
                                // synopsys translate_on
647
                                );
648
        defparam
649
                lpm_ff_component.lpm_fftype = "DFF",
650
                lpm_ff_component.lpm_type = "LPM_FF",
651
                lpm_ff_component.lpm_width = 1;
652
 
653
 
654
endmodule
655
 
656
// ============================================================
657
// CNX file retrieval info
658
// ============================================================
659
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
660
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
661
// Retrieval info: PRIVATE: ASET NUMERIC "1"
662
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
663
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
664
// Retrieval info: PRIVATE: DFF NUMERIC "1"
665
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
666
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
667
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
668
// Retrieval info: PRIVATE: SSET NUMERIC "0"
669
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
670
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
671
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
672
// Retrieval info: PRIVATE: nBit NUMERIC "1"
673
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
674
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
675
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
676
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
677
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
678
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
679
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
680
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
681
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
682
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
683
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
684
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
685
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
686
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
687
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
688
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
689
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
690
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
691
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
692
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
693
// Retrieval info: LIB_FILE: lpm
694
 
695
 
696
`else
697
 
698
 
699 18 unneback
module vl_dff_sr ( aclr, aset, clock, data, q);
700 6 unneback
 
701
    input         aclr;
702
    input         aset;
703
    input         clock;
704
    input         data;
705
    output reg    q;
706
 
707
   always @ (posedge clock or posedge aclr or posedge aset)
708
     if (aclr)
709
       q <= 1'b0;
710
     else if (aset)
711
       q <= 1'b1;
712
     else
713
       q <= data;
714
 
715
endmodule
716
 
717
`endif
718
 
719
// LATCH
720
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
721
`ifdef ALTERA
722 18 unneback
module vl_latch ( d, le, q, clk);
723 6 unneback
input d, le;
724
output q;
725
input clk;
726
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
727
endmodule
728
`else
729
module latch ( d, le, q, clk);
730
input d, le;
731
output q;
732
input clk;/*
733
   always @ (posedge direction_set or posedge direction_clr)
734
     if (direction_clr)
735
       direction <= going_empty;
736
     else
737
       direction <= going_full;*/
738
endmodule
739 15 unneback
`endif
740
 
741 18 unneback
module vl_shreg ( d, q, clk, rst);
742 17 unneback
parameter depth = 10;
743
input d;
744
output q;
745
input clk, rst;
746
 
747
reg [1:depth] dffs;
748
 
749
always @ (posedge clk or posedge rst)
750
if (rst)
751
    dffs <= {depth{1'b0}};
752
else
753
    dffs <= {d,dffs[1:depth-1]};
754
assign q = dffs[depth];
755
endmodule
756
 
757 18 unneback
module vl_shreg_ce ( d, ce, q, clk, rst);
758 17 unneback
parameter depth = 10;
759
input d, ce;
760
output q;
761
input clk, rst;
762
 
763
reg [1:depth] dffs;
764
 
765
always @ (posedge clk or posedge rst)
766
if (rst)
767
    dffs <= {depth{1'b0}};
768
else
769
    if (ce)
770
        dffs <= {d,dffs[1:depth-1]};
771
assign q = dffs[depth];
772
endmodule
773
 
774 18 unneback
module vl_delay ( d, q, clk, rst);
775 15 unneback
parameter depth = 10;
776
input d;
777
output q;
778
input clk, rst;
779
 
780
reg [1:depth] dffs;
781
 
782
always @ (posedge clk or posedge rst)
783
if (rst)
784
    dffs <= {depth{1'b0}};
785
else
786
    dffs <= {d,dffs[1:depth-1]};
787
assign q = dffs[depth];
788 17 unneback
endmodule
789
 
790 18 unneback
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
791 17 unneback
parameter depth = 10;
792
input d;
793
output q, emptyflag;
794
input clk, rst;
795
 
796
reg [1:depth] dffs;
797
 
798
always @ (posedge clk or posedge rst)
799
if (rst)
800
    dffs <= {depth{1'b0}};
801
else
802
    dffs <= {d,dffs[1:depth-1]};
803
assign q = dffs[depth];
804
assign emptyflag = !(|dffs);
805
endmodule
806
//////////////////////////////////////////////////////////////////////
807 6 unneback
////                                                              ////
808 18 unneback
////  Logic functions                                             ////
809
////                                                              ////
810
////  Description                                                 ////
811
////  Logic functions such as multiplexers                        ////
812
////                                                              ////
813
////                                                              ////
814
////  To Do:                                                      ////
815
////   -                                                          ////
816
////                                                              ////
817
////  Author(s):                                                  ////
818
////      - Michael Unneback, unneback@opencores.org              ////
819
////        ORSoC AB                                              ////
820
////                                                              ////
821
//////////////////////////////////////////////////////////////////////
822
////                                                              ////
823
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
824
////                                                              ////
825
//// This source file may be used and distributed without         ////
826
//// restriction provided that this copyright statement is not    ////
827
//// removed from the file and that any derivative work contains  ////
828
//// the original copyright notice and the associated disclaimer. ////
829
////                                                              ////
830
//// This source file is free software; you can redistribute it   ////
831
//// and/or modify it under the terms of the GNU Lesser General   ////
832
//// Public License as published by the Free Software Foundation; ////
833
//// either version 2.1 of the License, or (at your option) any   ////
834
//// later version.                                               ////
835
////                                                              ////
836
//// This source is distributed in the hope that it will be       ////
837
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
838
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
839
//// PURPOSE.  See the GNU Lesser General Public License for more ////
840
//// details.                                                     ////
841
////                                                              ////
842
//// You should have received a copy of the GNU Lesser General    ////
843
//// Public License along with this source; if not, download it   ////
844
//// from http://www.opencores.org/lgpl.shtml                     ////
845
////                                                              ////
846
//////////////////////////////////////////////////////////////////////
847
 
848
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
849
 
850
parameter width = 32;
851
parameter nr_of_ports = 4;
852
input [width-1:0] a3, a2, a1, a0;
853
input [nr_of_ports-1:0] sel;
854 22 unneback
output [width-1:0] dout;
855 18 unneback
 
856 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
857 18 unneback
integer i;
858
 
859
// and
860
assign tmp[0] = {width{sel[0]}} & a0;
861
assign tmp[1] = {width{sel[1]}} & a1;
862
assign tmp[2] = {width{sel[2]}} & a2;
863
assign tmp[3] = {width{sel[3]}} & a3;
864
 
865
// or
866
assign dout = tmp[3] | tmp[2] | tmp[1] | tmp[0];
867
 
868
endmodule
869
 
870
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
871
 
872
parameter width = 32;
873
parameter nr_of_ports = 5;
874
input [width-1:0] a4, a3, a2, a1, a0;
875
input [nr_of_ports-1:0] sel;
876 22 unneback
output [width-1:0] dout;
877 18 unneback
 
878 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
879 18 unneback
integer i;
880
 
881
// and
882
assign tmp[0] = {width{sel[0]}} & a0;
883
assign tmp[1] = {width{sel[1]}} & a1;
884
assign tmp[2] = {width{sel[2]}} & a2;
885
assign tmp[3] = {width{sel[3]}} & a3;
886
assign tmp[4] = {width{sel[4]}} & a4;
887
 
888
// or
889
assign dout = tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
890
 
891
endmodule
892
 
893
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
894
 
895
parameter width = 32;
896
parameter nr_of_ports = 6;
897
input [width-1:0] a5, a4, a3, a2, a1, a0;
898
input [nr_of_ports-1:0] sel;
899 22 unneback
output [width-1:0] dout;
900 18 unneback
 
901 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
902 18 unneback
integer i;
903
 
904
// and
905
assign tmp[0] = {width{sel[0]}} & a0;
906
assign tmp[1] = {width{sel[1]}} & a1;
907
assign tmp[2] = {width{sel[2]}} & a2;
908
assign tmp[3] = {width{sel[3]}} & a3;
909
assign tmp[4] = {width{sel[4]}} & a4;
910
assign tmp[5] = {width{sel[5]}} & a5;
911
 
912
// or
913
assign dout = tmp[5] | tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
914
 
915
endmodule
916
//////////////////////////////////////////////////////////////////////
917
////                                                              ////
918 6 unneback
////  Versatile counter                                           ////
919
////                                                              ////
920
////  Description                                                 ////
921
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
922
////  counter                                                     ////
923
////                                                              ////
924
////  To Do:                                                      ////
925
////   - add LFSR with more taps                                  ////
926
////                                                              ////
927
////  Author(s):                                                  ////
928
////      - Michael Unneback, unneback@opencores.org              ////
929
////        ORSoC AB                                              ////
930
////                                                              ////
931
//////////////////////////////////////////////////////////////////////
932
////                                                              ////
933
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
934
////                                                              ////
935
//// This source file may be used and distributed without         ////
936
//// restriction provided that this copyright statement is not    ////
937
//// removed from the file and that any derivative work contains  ////
938
//// the original copyright notice and the associated disclaimer. ////
939
////                                                              ////
940
//// This source file is free software; you can redistribute it   ////
941
//// and/or modify it under the terms of the GNU Lesser General   ////
942
//// Public License as published by the Free Software Foundation; ////
943
//// either version 2.1 of the License, or (at your option) any   ////
944
//// later version.                                               ////
945
////                                                              ////
946
//// This source is distributed in the hope that it will be       ////
947
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
948
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
949
//// PURPOSE.  See the GNU Lesser General Public License for more ////
950
//// details.                                                     ////
951
////                                                              ////
952
//// You should have received a copy of the GNU Lesser General    ////
953
//// Public License along with this source; if not, download it   ////
954
//// from http://www.opencores.org/lgpl.shtml                     ////
955
////                                                              ////
956
//////////////////////////////////////////////////////////////////////
957
 
958
// binary counter
959 22 unneback
module vl_cnt_bin ( q, rst, clk);
960
 
961
   parameter length = 4;
962
   output [length:1] q;
963
   input rst;
964
   input clk;
965
 
966
   parameter clear_value = 0;
967
   parameter set_value = 1;
968
   parameter wrap_value = 0;
969
   parameter level1_value = 15;
970
 
971
   reg  [length:1] qi;
972
   wire [length:1] q_next;
973
   assign q_next = qi + {{length-1{1'b0}},1'b1};
974
 
975
   always @ (posedge clk or posedge rst)
976
     if (rst)
977
       qi <= {length{1'b0}};
978
     else
979
       qi <= q_next;
980
 
981
   assign q = qi;
982
 
983
endmodule
984
//////////////////////////////////////////////////////////////////////
985
////                                                              ////
986
////  Versatile counter                                           ////
987
////                                                              ////
988
////  Description                                                 ////
989
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
990
////  counter                                                     ////
991
////                                                              ////
992
////  To Do:                                                      ////
993
////   - add LFSR with more taps                                  ////
994
////                                                              ////
995
////  Author(s):                                                  ////
996
////      - Michael Unneback, unneback@opencores.org              ////
997
////        ORSoC AB                                              ////
998
////                                                              ////
999
//////////////////////////////////////////////////////////////////////
1000
////                                                              ////
1001
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1002
////                                                              ////
1003
//// This source file may be used and distributed without         ////
1004
//// restriction provided that this copyright statement is not    ////
1005
//// removed from the file and that any derivative work contains  ////
1006
//// the original copyright notice and the associated disclaimer. ////
1007
////                                                              ////
1008
//// This source file is free software; you can redistribute it   ////
1009
//// and/or modify it under the terms of the GNU Lesser General   ////
1010
//// Public License as published by the Free Software Foundation; ////
1011
//// either version 2.1 of the License, or (at your option) any   ////
1012
//// later version.                                               ////
1013
////                                                              ////
1014
//// This source is distributed in the hope that it will be       ////
1015
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1016
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1017
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1018
//// details.                                                     ////
1019
////                                                              ////
1020
//// You should have received a copy of the GNU Lesser General    ////
1021
//// Public License along with this source; if not, download it   ////
1022
//// from http://www.opencores.org/lgpl.shtml                     ////
1023
////                                                              ////
1024
//////////////////////////////////////////////////////////////////////
1025
 
1026
// binary counter
1027
module vl_cnt_bin_clear ( clear, q, rst, clk);
1028
 
1029
   parameter length = 4;
1030
   input clear;
1031
   output [length:1] q;
1032
   input rst;
1033
   input clk;
1034
 
1035
   parameter clear_value = 0;
1036
   parameter set_value = 1;
1037
   parameter wrap_value = 0;
1038
   parameter level1_value = 15;
1039
 
1040
   reg  [length:1] qi;
1041
   wire [length:1] q_next;
1042
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1043
 
1044
   always @ (posedge clk or posedge rst)
1045
     if (rst)
1046
       qi <= {length{1'b0}};
1047
     else
1048
       qi <= q_next;
1049
 
1050
   assign q = qi;
1051
 
1052
endmodule
1053
//////////////////////////////////////////////////////////////////////
1054
////                                                              ////
1055
////  Versatile counter                                           ////
1056
////                                                              ////
1057
////  Description                                                 ////
1058
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1059
////  counter                                                     ////
1060
////                                                              ////
1061
////  To Do:                                                      ////
1062
////   - add LFSR with more taps                                  ////
1063
////                                                              ////
1064
////  Author(s):                                                  ////
1065
////      - Michael Unneback, unneback@opencores.org              ////
1066
////        ORSoC AB                                              ////
1067
////                                                              ////
1068
//////////////////////////////////////////////////////////////////////
1069
////                                                              ////
1070
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1071
////                                                              ////
1072
//// This source file may be used and distributed without         ////
1073
//// restriction provided that this copyright statement is not    ////
1074
//// removed from the file and that any derivative work contains  ////
1075
//// the original copyright notice and the associated disclaimer. ////
1076
////                                                              ////
1077
//// This source file is free software; you can redistribute it   ////
1078
//// and/or modify it under the terms of the GNU Lesser General   ////
1079
//// Public License as published by the Free Software Foundation; ////
1080
//// either version 2.1 of the License, or (at your option) any   ////
1081
//// later version.                                               ////
1082
////                                                              ////
1083
//// This source is distributed in the hope that it will be       ////
1084
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1085
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1086
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1087
//// details.                                                     ////
1088
////                                                              ////
1089
//// You should have received a copy of the GNU Lesser General    ////
1090
//// Public License along with this source; if not, download it   ////
1091
//// from http://www.opencores.org/lgpl.shtml                     ////
1092
////                                                              ////
1093
//////////////////////////////////////////////////////////////////////
1094
 
1095
// binary counter
1096 18 unneback
module vl_cnt_bin_ce ( cke, q, rst, clk);
1097 6 unneback
 
1098
   parameter length = 4;
1099
   input cke;
1100
   output [length:1] q;
1101
   input rst;
1102
   input clk;
1103
 
1104
   parameter clear_value = 0;
1105
   parameter set_value = 1;
1106
   parameter wrap_value = 0;
1107
   parameter level1_value = 15;
1108
 
1109
   reg  [length:1] qi;
1110
   wire [length:1] q_next;
1111
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1112
 
1113
   always @ (posedge clk or posedge rst)
1114
     if (rst)
1115
       qi <= {length{1'b0}};
1116
     else
1117
     if (cke)
1118
       qi <= q_next;
1119
 
1120
   assign q = qi;
1121
 
1122
endmodule
1123
//////////////////////////////////////////////////////////////////////
1124
////                                                              ////
1125
////  Versatile counter                                           ////
1126
////                                                              ////
1127
////  Description                                                 ////
1128
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1129
////  counter                                                     ////
1130
////                                                              ////
1131
////  To Do:                                                      ////
1132
////   - add LFSR with more taps                                  ////
1133
////                                                              ////
1134
////  Author(s):                                                  ////
1135
////      - Michael Unneback, unneback@opencores.org              ////
1136
////        ORSoC AB                                              ////
1137
////                                                              ////
1138
//////////////////////////////////////////////////////////////////////
1139
////                                                              ////
1140
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1141
////                                                              ////
1142
//// This source file may be used and distributed without         ////
1143
//// restriction provided that this copyright statement is not    ////
1144
//// removed from the file and that any derivative work contains  ////
1145
//// the original copyright notice and the associated disclaimer. ////
1146
////                                                              ////
1147
//// This source file is free software; you can redistribute it   ////
1148
//// and/or modify it under the terms of the GNU Lesser General   ////
1149
//// Public License as published by the Free Software Foundation; ////
1150
//// either version 2.1 of the License, or (at your option) any   ////
1151
//// later version.                                               ////
1152
////                                                              ////
1153
//// This source is distributed in the hope that it will be       ////
1154
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1155
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1156
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1157
//// details.                                                     ////
1158
////                                                              ////
1159
//// You should have received a copy of the GNU Lesser General    ////
1160
//// Public License along with this source; if not, download it   ////
1161
//// from http://www.opencores.org/lgpl.shtml                     ////
1162
////                                                              ////
1163
//////////////////////////////////////////////////////////////////////
1164
 
1165
// binary counter
1166 18 unneback
module vl_cnt_bin_ce_clear ( clear, cke, q, rst, clk);
1167 6 unneback
 
1168
   parameter length = 4;
1169
   input clear;
1170
   input cke;
1171
   output [length:1] q;
1172
   input rst;
1173
   input clk;
1174
 
1175
   parameter clear_value = 0;
1176
   parameter set_value = 1;
1177
   parameter wrap_value = 0;
1178
   parameter level1_value = 15;
1179
 
1180
   reg  [length:1] qi;
1181
   wire [length:1] q_next;
1182
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1183
 
1184
   always @ (posedge clk or posedge rst)
1185
     if (rst)
1186
       qi <= {length{1'b0}};
1187
     else
1188
     if (cke)
1189
       qi <= q_next;
1190
 
1191
   assign q = qi;
1192
 
1193
endmodule
1194
//////////////////////////////////////////////////////////////////////
1195
////                                                              ////
1196
////  Versatile counter                                           ////
1197
////                                                              ////
1198
////  Description                                                 ////
1199
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1200
////  counter                                                     ////
1201
////                                                              ////
1202
////  To Do:                                                      ////
1203
////   - add LFSR with more taps                                  ////
1204
////                                                              ////
1205
////  Author(s):                                                  ////
1206
////      - Michael Unneback, unneback@opencores.org              ////
1207
////        ORSoC AB                                              ////
1208
////                                                              ////
1209
//////////////////////////////////////////////////////////////////////
1210
////                                                              ////
1211
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1212
////                                                              ////
1213
//// This source file may be used and distributed without         ////
1214
//// restriction provided that this copyright statement is not    ////
1215
//// removed from the file and that any derivative work contains  ////
1216
//// the original copyright notice and the associated disclaimer. ////
1217
////                                                              ////
1218
//// This source file is free software; you can redistribute it   ////
1219
//// and/or modify it under the terms of the GNU Lesser General   ////
1220
//// Public License as published by the Free Software Foundation; ////
1221
//// either version 2.1 of the License, or (at your option) any   ////
1222
//// later version.                                               ////
1223
////                                                              ////
1224
//// This source is distributed in the hope that it will be       ////
1225
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1226
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1227
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1228
//// details.                                                     ////
1229
////                                                              ////
1230
//// You should have received a copy of the GNU Lesser General    ////
1231
//// Public License along with this source; if not, download it   ////
1232
//// from http://www.opencores.org/lgpl.shtml                     ////
1233
////                                                              ////
1234
//////////////////////////////////////////////////////////////////////
1235
 
1236
// binary counter
1237 29 unneback
module vl_cnt_bin_ce_clear_l1_l2 ( clear, cke, q, level1, level2, rst, clk);
1238
 
1239
   parameter length = 4;
1240
   input clear;
1241
   input cke;
1242
   output [length:1] q;
1243
   output reg level1;
1244
   output reg level2;
1245
   input rst;
1246
   input clk;
1247
 
1248
   parameter clear_value = 0;
1249
   parameter set_value = 1;
1250 30 unneback
   parameter wrap_value = 15;
1251
   parameter level1_value = 8;
1252
   parameter level2_value = 15;
1253 29 unneback
 
1254
   wire rew;
1255 30 unneback
   assign rew = 1'b0;
1256 29 unneback
   reg  [length:1] qi;
1257
   wire [length:1] q_next;
1258
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1259
 
1260
   always @ (posedge clk or posedge rst)
1261
     if (rst)
1262
       qi <= {length{1'b0}};
1263
     else
1264
     if (cke)
1265
       qi <= q_next;
1266
 
1267
   assign q = qi;
1268
 
1269
 
1270
    always @ (posedge clk or posedge rst)
1271
    if (rst)
1272
        level1 <= 1'b0;
1273
    else
1274
    if (cke)
1275
    if (clear)
1276
        level1 <= 1'b0;
1277
    else if (q_next == level1_value)
1278
        level1 <= 1'b1;
1279
    else if (qi == level1_value & rew)
1280
        level1 <= 1'b0;
1281
 
1282
    always @ (posedge clk or posedge rst)
1283
    if (rst)
1284
        level2 <= 1'b0;
1285
    else
1286
    if (cke)
1287
    if (clear)
1288
        level2 <= 1'b0;
1289
    else if (q_next == level2_value)
1290
        level2 <= 1'b1;
1291
    else if (qi == level2_value & rew)
1292
        level2 <= 1'b0;
1293
endmodule
1294
//////////////////////////////////////////////////////////////////////
1295
////                                                              ////
1296
////  Versatile counter                                           ////
1297
////                                                              ////
1298
////  Description                                                 ////
1299
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1300
////  counter                                                     ////
1301
////                                                              ////
1302
////  To Do:                                                      ////
1303
////   - add LFSR with more taps                                  ////
1304
////                                                              ////
1305
////  Author(s):                                                  ////
1306
////      - Michael Unneback, unneback@opencores.org              ////
1307
////        ORSoC AB                                              ////
1308
////                                                              ////
1309
//////////////////////////////////////////////////////////////////////
1310
////                                                              ////
1311
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1312
////                                                              ////
1313
//// This source file may be used and distributed without         ////
1314
//// restriction provided that this copyright statement is not    ////
1315
//// removed from the file and that any derivative work contains  ////
1316
//// the original copyright notice and the associated disclaimer. ////
1317
////                                                              ////
1318
//// This source file is free software; you can redistribute it   ////
1319
//// and/or modify it under the terms of the GNU Lesser General   ////
1320
//// Public License as published by the Free Software Foundation; ////
1321
//// either version 2.1 of the License, or (at your option) any   ////
1322
//// later version.                                               ////
1323
////                                                              ////
1324
//// This source is distributed in the hope that it will be       ////
1325
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1326
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1327
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1328
//// details.                                                     ////
1329
////                                                              ////
1330
//// You should have received a copy of the GNU Lesser General    ////
1331
//// Public License along with this source; if not, download it   ////
1332
//// from http://www.opencores.org/lgpl.shtml                     ////
1333
////                                                              ////
1334
//////////////////////////////////////////////////////////////////////
1335
 
1336
// binary counter
1337 18 unneback
module vl_cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk);
1338 6 unneback
 
1339
   parameter length = 4;
1340
   input clear;
1341
   input set;
1342
   input cke;
1343
   input rew;
1344
   output [length:1] q;
1345
   input rst;
1346
   input clk;
1347
 
1348
   parameter clear_value = 0;
1349
   parameter set_value = 1;
1350
   parameter wrap_value = 0;
1351
   parameter level1_value = 15;
1352
 
1353
   reg  [length:1] qi;
1354
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1355
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
1356
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
1357
   assign q_next = rew ? q_next_rew : q_next_fw;
1358
 
1359
   always @ (posedge clk or posedge rst)
1360
     if (rst)
1361
       qi <= {length{1'b0}};
1362
     else
1363
     if (cke)
1364
       qi <= q_next;
1365
 
1366
   assign q = qi;
1367
 
1368
endmodule
1369
//////////////////////////////////////////////////////////////////////
1370
////                                                              ////
1371
////  Versatile counter                                           ////
1372
////                                                              ////
1373
////  Description                                                 ////
1374
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1375
////  counter                                                     ////
1376
////                                                              ////
1377
////  To Do:                                                      ////
1378
////   - add LFSR with more taps                                  ////
1379
////                                                              ////
1380
////  Author(s):                                                  ////
1381
////      - Michael Unneback, unneback@opencores.org              ////
1382
////        ORSoC AB                                              ////
1383
////                                                              ////
1384
//////////////////////////////////////////////////////////////////////
1385
////                                                              ////
1386
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1387
////                                                              ////
1388
//// This source file may be used and distributed without         ////
1389
//// restriction provided that this copyright statement is not    ////
1390
//// removed from the file and that any derivative work contains  ////
1391
//// the original copyright notice and the associated disclaimer. ////
1392
////                                                              ////
1393
//// This source file is free software; you can redistribute it   ////
1394
//// and/or modify it under the terms of the GNU Lesser General   ////
1395
//// Public License as published by the Free Software Foundation; ////
1396
//// either version 2.1 of the License, or (at your option) any   ////
1397
//// later version.                                               ////
1398
////                                                              ////
1399
//// This source is distributed in the hope that it will be       ////
1400
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1401
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1402
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1403
//// details.                                                     ////
1404
////                                                              ////
1405
//// You should have received a copy of the GNU Lesser General    ////
1406
//// Public License along with this source; if not, download it   ////
1407
//// from http://www.opencores.org/lgpl.shtml                     ////
1408
////                                                              ////
1409
//////////////////////////////////////////////////////////////////////
1410
 
1411
// binary counter
1412 18 unneback
module vl_cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk);
1413 6 unneback
 
1414
   parameter length = 4;
1415
   input cke;
1416
   input rew;
1417
   output reg level1;
1418
   input rst;
1419
   input clk;
1420
 
1421
   parameter clear_value = 0;
1422
   parameter set_value = 1;
1423
   parameter wrap_value = 1;
1424
   parameter level1_value = 15;
1425
 
1426 29 unneback
   wire clear;
1427 30 unneback
   assign clear = 1'b0;
1428 6 unneback
   reg  [length:1] qi;
1429
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1430
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1431
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1432
   assign q_next = rew ? q_next_rew : q_next_fw;
1433
 
1434
   always @ (posedge clk or posedge rst)
1435
     if (rst)
1436
       qi <= {length{1'b0}};
1437
     else
1438
     if (cke)
1439
       qi <= q_next;
1440
 
1441
 
1442
 
1443
    always @ (posedge clk or posedge rst)
1444
    if (rst)
1445
        level1 <= 1'b0;
1446
    else
1447
    if (cke)
1448 29 unneback
    if (clear)
1449
        level1 <= 1'b0;
1450
    else if (q_next == level1_value)
1451 6 unneback
        level1 <= 1'b1;
1452
    else if (qi == level1_value & rew)
1453
        level1 <= 1'b0;
1454
endmodule
1455
//////////////////////////////////////////////////////////////////////
1456
////                                                              ////
1457
////  Versatile counter                                           ////
1458
////                                                              ////
1459
////  Description                                                 ////
1460
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1461
////  counter                                                     ////
1462
////                                                              ////
1463
////  To Do:                                                      ////
1464
////   - add LFSR with more taps                                  ////
1465
////                                                              ////
1466
////  Author(s):                                                  ////
1467
////      - Michael Unneback, unneback@opencores.org              ////
1468
////        ORSoC AB                                              ////
1469
////                                                              ////
1470
//////////////////////////////////////////////////////////////////////
1471
////                                                              ////
1472
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1473
////                                                              ////
1474
//// This source file may be used and distributed without         ////
1475
//// restriction provided that this copyright statement is not    ////
1476
//// removed from the file and that any derivative work contains  ////
1477
//// the original copyright notice and the associated disclaimer. ////
1478
////                                                              ////
1479
//// This source file is free software; you can redistribute it   ////
1480
//// and/or modify it under the terms of the GNU Lesser General   ////
1481
//// Public License as published by the Free Software Foundation; ////
1482
//// either version 2.1 of the License, or (at your option) any   ////
1483
//// later version.                                               ////
1484
////                                                              ////
1485
//// This source is distributed in the hope that it will be       ////
1486
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1487
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1488
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1489
//// details.                                                     ////
1490
////                                                              ////
1491
//// You should have received a copy of the GNU Lesser General    ////
1492
//// Public License along with this source; if not, download it   ////
1493
//// from http://www.opencores.org/lgpl.shtml                     ////
1494
////                                                              ////
1495
//////////////////////////////////////////////////////////////////////
1496
 
1497 25 unneback
// binary counter
1498
module vl_cnt_bin_ce_rew_zq_l1 ( cke, rew, zq, level1, rst, clk);
1499
 
1500
   parameter length = 4;
1501
   input cke;
1502
   input rew;
1503
   output reg zq;
1504
   output reg level1;
1505
   input rst;
1506
   input clk;
1507
 
1508
   parameter clear_value = 0;
1509
   parameter set_value = 1;
1510
   parameter wrap_value = 1;
1511
   parameter level1_value = 15;
1512
 
1513 29 unneback
   wire clear;
1514 30 unneback
   assign clear = 1'b0;
1515 25 unneback
   reg  [length:1] qi;
1516
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1517
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1518
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1519
   assign q_next = rew ? q_next_rew : q_next_fw;
1520
 
1521
   always @ (posedge clk or posedge rst)
1522
     if (rst)
1523
       qi <= {length{1'b0}};
1524
     else
1525
     if (cke)
1526
       qi <= q_next;
1527
 
1528
 
1529
 
1530
   always @ (posedge clk or posedge rst)
1531
     if (rst)
1532
       zq <= 1'b1;
1533
     else
1534
     if (cke)
1535
       zq <= q_next == {length{1'b0}};
1536
 
1537
    always @ (posedge clk or posedge rst)
1538
    if (rst)
1539
        level1 <= 1'b0;
1540
    else
1541
    if (cke)
1542 29 unneback
    if (clear)
1543
        level1 <= 1'b0;
1544
    else if (q_next == level1_value)
1545 25 unneback
        level1 <= 1'b1;
1546
    else if (qi == level1_value & rew)
1547
        level1 <= 1'b0;
1548
endmodule
1549
//////////////////////////////////////////////////////////////////////
1550
////                                                              ////
1551
////  Versatile counter                                           ////
1552
////                                                              ////
1553
////  Description                                                 ////
1554
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1555
////  counter                                                     ////
1556
////                                                              ////
1557
////  To Do:                                                      ////
1558
////   - add LFSR with more taps                                  ////
1559
////                                                              ////
1560
////  Author(s):                                                  ////
1561
////      - Michael Unneback, unneback@opencores.org              ////
1562
////        ORSoC AB                                              ////
1563
////                                                              ////
1564
//////////////////////////////////////////////////////////////////////
1565
////                                                              ////
1566
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1567
////                                                              ////
1568
//// This source file may be used and distributed without         ////
1569
//// restriction provided that this copyright statement is not    ////
1570
//// removed from the file and that any derivative work contains  ////
1571
//// the original copyright notice and the associated disclaimer. ////
1572
////                                                              ////
1573
//// This source file is free software; you can redistribute it   ////
1574
//// and/or modify it under the terms of the GNU Lesser General   ////
1575
//// Public License as published by the Free Software Foundation; ////
1576
//// either version 2.1 of the License, or (at your option) any   ////
1577
//// later version.                                               ////
1578
////                                                              ////
1579
//// This source is distributed in the hope that it will be       ////
1580
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1581
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1582
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1583
//// details.                                                     ////
1584
////                                                              ////
1585
//// You should have received a copy of the GNU Lesser General    ////
1586
//// Public License along with this source; if not, download it   ////
1587
//// from http://www.opencores.org/lgpl.shtml                     ////
1588
////                                                              ////
1589
//////////////////////////////////////////////////////////////////////
1590
 
1591
// binary counter
1592
module vl_cnt_bin_ce_rew_q_zq_l1 ( cke, rew, q, zq, level1, rst, clk);
1593
 
1594
   parameter length = 4;
1595
   input cke;
1596
   input rew;
1597
   output [length:1] q;
1598
   output reg zq;
1599
   output reg level1;
1600
   input rst;
1601
   input clk;
1602
 
1603
   parameter clear_value = 0;
1604
   parameter set_value = 1;
1605
   parameter wrap_value = 1;
1606
   parameter level1_value = 15;
1607
 
1608 29 unneback
   wire clear;
1609 30 unneback
   assign clear = 1'b0;
1610 25 unneback
   reg  [length:1] qi;
1611
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1612
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1613
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1614
   assign q_next = rew ? q_next_rew : q_next_fw;
1615
 
1616
   always @ (posedge clk or posedge rst)
1617
     if (rst)
1618
       qi <= {length{1'b0}};
1619
     else
1620
     if (cke)
1621
       qi <= q_next;
1622
 
1623
   assign q = qi;
1624
 
1625
 
1626
   always @ (posedge clk or posedge rst)
1627
     if (rst)
1628
       zq <= 1'b1;
1629
     else
1630
     if (cke)
1631
       zq <= q_next == {length{1'b0}};
1632
 
1633
    always @ (posedge clk or posedge rst)
1634
    if (rst)
1635
        level1 <= 1'b0;
1636
    else
1637
    if (cke)
1638 29 unneback
    if (clear)
1639
        level1 <= 1'b0;
1640
    else if (q_next == level1_value)
1641 25 unneback
        level1 <= 1'b1;
1642
    else if (qi == level1_value & rew)
1643
        level1 <= 1'b0;
1644
endmodule
1645
//////////////////////////////////////////////////////////////////////
1646
////                                                              ////
1647
////  Versatile counter                                           ////
1648
////                                                              ////
1649
////  Description                                                 ////
1650
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1651
////  counter                                                     ////
1652
////                                                              ////
1653
////  To Do:                                                      ////
1654
////   - add LFSR with more taps                                  ////
1655
////                                                              ////
1656
////  Author(s):                                                  ////
1657
////      - Michael Unneback, unneback@opencores.org              ////
1658
////        ORSoC AB                                              ////
1659
////                                                              ////
1660
//////////////////////////////////////////////////////////////////////
1661
////                                                              ////
1662
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1663
////                                                              ////
1664
//// This source file may be used and distributed without         ////
1665
//// restriction provided that this copyright statement is not    ////
1666
//// removed from the file and that any derivative work contains  ////
1667
//// the original copyright notice and the associated disclaimer. ////
1668
////                                                              ////
1669
//// This source file is free software; you can redistribute it   ////
1670
//// and/or modify it under the terms of the GNU Lesser General   ////
1671
//// Public License as published by the Free Software Foundation; ////
1672
//// either version 2.1 of the License, or (at your option) any   ////
1673
//// later version.                                               ////
1674
////                                                              ////
1675
//// This source is distributed in the hope that it will be       ////
1676
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1677
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1678
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1679
//// details.                                                     ////
1680
////                                                              ////
1681
//// You should have received a copy of the GNU Lesser General    ////
1682
//// Public License along with this source; if not, download it   ////
1683
//// from http://www.opencores.org/lgpl.shtml                     ////
1684
////                                                              ////
1685
//////////////////////////////////////////////////////////////////////
1686
 
1687 6 unneback
// LFSR counter
1688 18 unneback
module vl_cnt_lfsr_zq ( zq, rst, clk);
1689 6 unneback
 
1690
   parameter length = 4;
1691
   output reg zq;
1692
   input rst;
1693
   input clk;
1694
 
1695
   parameter clear_value = 0;
1696
   parameter set_value = 1;
1697
   parameter wrap_value = 8;
1698
   parameter level1_value = 15;
1699
 
1700
   reg  [length:1] qi;
1701
   reg lfsr_fb;
1702
   wire [length:1] q_next;
1703
   reg [32:1] polynom;
1704
   integer i;
1705
 
1706
   always @ (qi)
1707
   begin
1708
        case (length)
1709
         2: polynom = 32'b11;                               // 0x3
1710
         3: polynom = 32'b110;                              // 0x6
1711
         4: polynom = 32'b1100;                             // 0xC
1712
         5: polynom = 32'b10100;                            // 0x14
1713
         6: polynom = 32'b110000;                           // 0x30
1714
         7: polynom = 32'b1100000;                          // 0x60
1715
         8: polynom = 32'b10111000;                         // 0xb8
1716
         9: polynom = 32'b100010000;                        // 0x110
1717
        10: polynom = 32'b1001000000;                       // 0x240
1718
        11: polynom = 32'b10100000000;                      // 0x500
1719
        12: polynom = 32'b100000101001;                     // 0x829
1720
        13: polynom = 32'b1000000001100;                    // 0x100C
1721
        14: polynom = 32'b10000000010101;                   // 0x2015
1722
        15: polynom = 32'b110000000000000;                  // 0x6000
1723
        16: polynom = 32'b1101000000001000;                 // 0xD008
1724
        17: polynom = 32'b10010000000000000;                // 0x12000
1725
        18: polynom = 32'b100000010000000000;               // 0x20400
1726
        19: polynom = 32'b1000000000000100011;              // 0x40023
1727
        20: polynom = 32'b10000010000000000000;             // 0x82000
1728
        21: polynom = 32'b101000000000000000000;            // 0x140000
1729
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1730
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1731
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1732
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1733
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1734
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1735
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1736
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1737
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1738
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1739
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1740
        default: polynom = 32'b0;
1741
        endcase
1742
        lfsr_fb = qi[length];
1743
        for (i=length-1; i>=1; i=i-1) begin
1744
            if (polynom[i])
1745
                lfsr_fb = lfsr_fb  ~^ qi[i];
1746
        end
1747
    end
1748
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1749
 
1750
   always @ (posedge clk or posedge rst)
1751
     if (rst)
1752
       qi <= {length{1'b0}};
1753
     else
1754
       qi <= q_next;
1755
 
1756
 
1757
 
1758
   always @ (posedge clk or posedge rst)
1759
     if (rst)
1760
       zq <= 1'b1;
1761
     else
1762
       zq <= q_next == {length{1'b0}};
1763
endmodule
1764
//////////////////////////////////////////////////////////////////////
1765
////                                                              ////
1766
////  Versatile counter                                           ////
1767
////                                                              ////
1768
////  Description                                                 ////
1769
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1770
////  counter                                                     ////
1771
////                                                              ////
1772
////  To Do:                                                      ////
1773
////   - add LFSR with more taps                                  ////
1774
////                                                              ////
1775
////  Author(s):                                                  ////
1776
////      - Michael Unneback, unneback@opencores.org              ////
1777
////        ORSoC AB                                              ////
1778
////                                                              ////
1779
//////////////////////////////////////////////////////////////////////
1780
////                                                              ////
1781
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1782
////                                                              ////
1783
//// This source file may be used and distributed without         ////
1784
//// restriction provided that this copyright statement is not    ////
1785
//// removed from the file and that any derivative work contains  ////
1786
//// the original copyright notice and the associated disclaimer. ////
1787
////                                                              ////
1788
//// This source file is free software; you can redistribute it   ////
1789
//// and/or modify it under the terms of the GNU Lesser General   ////
1790
//// Public License as published by the Free Software Foundation; ////
1791
//// either version 2.1 of the License, or (at your option) any   ////
1792
//// later version.                                               ////
1793
////                                                              ////
1794
//// This source is distributed in the hope that it will be       ////
1795
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1796
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1797
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1798
//// details.                                                     ////
1799
////                                                              ////
1800
//// You should have received a copy of the GNU Lesser General    ////
1801
//// Public License along with this source; if not, download it   ////
1802
//// from http://www.opencores.org/lgpl.shtml                     ////
1803
////                                                              ////
1804
//////////////////////////////////////////////////////////////////////
1805
 
1806
// LFSR counter
1807 18 unneback
module vl_cnt_lfsr_ce_zq ( cke, zq, rst, clk);
1808 6 unneback
 
1809
   parameter length = 4;
1810
   input cke;
1811
   output reg zq;
1812
   input rst;
1813
   input clk;
1814
 
1815
   parameter clear_value = 0;
1816
   parameter set_value = 1;
1817
   parameter wrap_value = 8;
1818
   parameter level1_value = 15;
1819
 
1820
   reg  [length:1] qi;
1821
   reg lfsr_fb;
1822
   wire [length:1] q_next;
1823
   reg [32:1] polynom;
1824
   integer i;
1825
 
1826
   always @ (qi)
1827
   begin
1828
        case (length)
1829
         2: polynom = 32'b11;                               // 0x3
1830
         3: polynom = 32'b110;                              // 0x6
1831
         4: polynom = 32'b1100;                             // 0xC
1832
         5: polynom = 32'b10100;                            // 0x14
1833
         6: polynom = 32'b110000;                           // 0x30
1834
         7: polynom = 32'b1100000;                          // 0x60
1835
         8: polynom = 32'b10111000;                         // 0xb8
1836
         9: polynom = 32'b100010000;                        // 0x110
1837
        10: polynom = 32'b1001000000;                       // 0x240
1838
        11: polynom = 32'b10100000000;                      // 0x500
1839
        12: polynom = 32'b100000101001;                     // 0x829
1840
        13: polynom = 32'b1000000001100;                    // 0x100C
1841
        14: polynom = 32'b10000000010101;                   // 0x2015
1842
        15: polynom = 32'b110000000000000;                  // 0x6000
1843
        16: polynom = 32'b1101000000001000;                 // 0xD008
1844
        17: polynom = 32'b10010000000000000;                // 0x12000
1845
        18: polynom = 32'b100000010000000000;               // 0x20400
1846
        19: polynom = 32'b1000000000000100011;              // 0x40023
1847
        20: polynom = 32'b10000010000000000000;             // 0x82000
1848
        21: polynom = 32'b101000000000000000000;            // 0x140000
1849
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1850
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1851
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1852
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1853
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1854
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1855
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1856
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1857
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1858
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1859
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1860
        default: polynom = 32'b0;
1861
        endcase
1862
        lfsr_fb = qi[length];
1863
        for (i=length-1; i>=1; i=i-1) begin
1864
            if (polynom[i])
1865
                lfsr_fb = lfsr_fb  ~^ qi[i];
1866
        end
1867
    end
1868
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1869
 
1870
   always @ (posedge clk or posedge rst)
1871
     if (rst)
1872
       qi <= {length{1'b0}};
1873
     else
1874
     if (cke)
1875
       qi <= q_next;
1876
 
1877
 
1878
 
1879
   always @ (posedge clk or posedge rst)
1880
     if (rst)
1881
       zq <= 1'b1;
1882
     else
1883
     if (cke)
1884
       zq <= q_next == {length{1'b0}};
1885
endmodule
1886
//////////////////////////////////////////////////////////////////////
1887
////                                                              ////
1888
////  Versatile counter                                           ////
1889
////                                                              ////
1890
////  Description                                                 ////
1891
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1892
////  counter                                                     ////
1893
////                                                              ////
1894
////  To Do:                                                      ////
1895
////   - add LFSR with more taps                                  ////
1896
////                                                              ////
1897
////  Author(s):                                                  ////
1898
////      - Michael Unneback, unneback@opencores.org              ////
1899
////        ORSoC AB                                              ////
1900
////                                                              ////
1901
//////////////////////////////////////////////////////////////////////
1902
////                                                              ////
1903
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1904
////                                                              ////
1905
//// This source file may be used and distributed without         ////
1906
//// restriction provided that this copyright statement is not    ////
1907
//// removed from the file and that any derivative work contains  ////
1908
//// the original copyright notice and the associated disclaimer. ////
1909
////                                                              ////
1910
//// This source file is free software; you can redistribute it   ////
1911
//// and/or modify it under the terms of the GNU Lesser General   ////
1912
//// Public License as published by the Free Software Foundation; ////
1913
//// either version 2.1 of the License, or (at your option) any   ////
1914
//// later version.                                               ////
1915
////                                                              ////
1916
//// This source is distributed in the hope that it will be       ////
1917
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1918
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1919
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1920
//// details.                                                     ////
1921
////                                                              ////
1922
//// You should have received a copy of the GNU Lesser General    ////
1923
//// Public License along with this source; if not, download it   ////
1924
//// from http://www.opencores.org/lgpl.shtml                     ////
1925
////                                                              ////
1926
//////////////////////////////////////////////////////////////////////
1927 22 unneback
 
1928
// LFSR counter
1929 27 unneback
module vl_cnt_lfsr_ce_q ( cke, q, rst, clk);
1930
 
1931
   parameter length = 4;
1932
   input cke;
1933
   output [length:1] q;
1934
   input rst;
1935
   input clk;
1936
 
1937
   parameter clear_value = 0;
1938
   parameter set_value = 1;
1939
   parameter wrap_value = 8;
1940
   parameter level1_value = 15;
1941
 
1942
   reg  [length:1] qi;
1943
   reg lfsr_fb;
1944
   wire [length:1] q_next;
1945
   reg [32:1] polynom;
1946
   integer i;
1947
 
1948
   always @ (qi)
1949
   begin
1950
        case (length)
1951
         2: polynom = 32'b11;                               // 0x3
1952
         3: polynom = 32'b110;                              // 0x6
1953
         4: polynom = 32'b1100;                             // 0xC
1954
         5: polynom = 32'b10100;                            // 0x14
1955
         6: polynom = 32'b110000;                           // 0x30
1956
         7: polynom = 32'b1100000;                          // 0x60
1957
         8: polynom = 32'b10111000;                         // 0xb8
1958
         9: polynom = 32'b100010000;                        // 0x110
1959
        10: polynom = 32'b1001000000;                       // 0x240
1960
        11: polynom = 32'b10100000000;                      // 0x500
1961
        12: polynom = 32'b100000101001;                     // 0x829
1962
        13: polynom = 32'b1000000001100;                    // 0x100C
1963
        14: polynom = 32'b10000000010101;                   // 0x2015
1964
        15: polynom = 32'b110000000000000;                  // 0x6000
1965
        16: polynom = 32'b1101000000001000;                 // 0xD008
1966
        17: polynom = 32'b10010000000000000;                // 0x12000
1967
        18: polynom = 32'b100000010000000000;               // 0x20400
1968
        19: polynom = 32'b1000000000000100011;              // 0x40023
1969
        20: polynom = 32'b10000010000000000000;             // 0x82000
1970
        21: polynom = 32'b101000000000000000000;            // 0x140000
1971
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1972
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1973
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1974
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1975
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1976
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1977
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1978
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1979
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1980
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1981
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1982
        default: polynom = 32'b0;
1983
        endcase
1984
        lfsr_fb = qi[length];
1985
        for (i=length-1; i>=1; i=i-1) begin
1986
            if (polynom[i])
1987
                lfsr_fb = lfsr_fb  ~^ qi[i];
1988
        end
1989
    end
1990
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1991
 
1992
   always @ (posedge clk or posedge rst)
1993
     if (rst)
1994
       qi <= {length{1'b0}};
1995
     else
1996
     if (cke)
1997
       qi <= q_next;
1998
 
1999
   assign q = qi;
2000
 
2001
endmodule
2002
//////////////////////////////////////////////////////////////////////
2003
////                                                              ////
2004
////  Versatile counter                                           ////
2005
////                                                              ////
2006
////  Description                                                 ////
2007
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2008
////  counter                                                     ////
2009
////                                                              ////
2010
////  To Do:                                                      ////
2011
////   - add LFSR with more taps                                  ////
2012
////                                                              ////
2013
////  Author(s):                                                  ////
2014
////      - Michael Unneback, unneback@opencores.org              ////
2015
////        ORSoC AB                                              ////
2016
////                                                              ////
2017
//////////////////////////////////////////////////////////////////////
2018
////                                                              ////
2019
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2020
////                                                              ////
2021
//// This source file may be used and distributed without         ////
2022
//// restriction provided that this copyright statement is not    ////
2023
//// removed from the file and that any derivative work contains  ////
2024
//// the original copyright notice and the associated disclaimer. ////
2025
////                                                              ////
2026
//// This source file is free software; you can redistribute it   ////
2027
//// and/or modify it under the terms of the GNU Lesser General   ////
2028
//// Public License as published by the Free Software Foundation; ////
2029
//// either version 2.1 of the License, or (at your option) any   ////
2030
//// later version.                                               ////
2031
////                                                              ////
2032
//// This source is distributed in the hope that it will be       ////
2033
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2034
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2035
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2036
//// details.                                                     ////
2037
////                                                              ////
2038
//// You should have received a copy of the GNU Lesser General    ////
2039
//// Public License along with this source; if not, download it   ////
2040
//// from http://www.opencores.org/lgpl.shtml                     ////
2041
////                                                              ////
2042
//////////////////////////////////////////////////////////////////////
2043
 
2044
// LFSR counter
2045
module vl_cnt_lfsr_ce_clear_q ( clear, cke, q, rst, clk);
2046
 
2047
   parameter length = 4;
2048
   input clear;
2049
   input cke;
2050
   output [length:1] q;
2051
   input rst;
2052
   input clk;
2053
 
2054
   parameter clear_value = 0;
2055
   parameter set_value = 1;
2056
   parameter wrap_value = 8;
2057
   parameter level1_value = 15;
2058
 
2059
   reg  [length:1] qi;
2060
   reg lfsr_fb;
2061
   wire [length:1] q_next;
2062
   reg [32:1] polynom;
2063
   integer i;
2064
 
2065
   always @ (qi)
2066
   begin
2067
        case (length)
2068
         2: polynom = 32'b11;                               // 0x3
2069
         3: polynom = 32'b110;                              // 0x6
2070
         4: polynom = 32'b1100;                             // 0xC
2071
         5: polynom = 32'b10100;                            // 0x14
2072
         6: polynom = 32'b110000;                           // 0x30
2073
         7: polynom = 32'b1100000;                          // 0x60
2074
         8: polynom = 32'b10111000;                         // 0xb8
2075
         9: polynom = 32'b100010000;                        // 0x110
2076
        10: polynom = 32'b1001000000;                       // 0x240
2077
        11: polynom = 32'b10100000000;                      // 0x500
2078
        12: polynom = 32'b100000101001;                     // 0x829
2079
        13: polynom = 32'b1000000001100;                    // 0x100C
2080
        14: polynom = 32'b10000000010101;                   // 0x2015
2081
        15: polynom = 32'b110000000000000;                  // 0x6000
2082
        16: polynom = 32'b1101000000001000;                 // 0xD008
2083
        17: polynom = 32'b10010000000000000;                // 0x12000
2084
        18: polynom = 32'b100000010000000000;               // 0x20400
2085
        19: polynom = 32'b1000000000000100011;              // 0x40023
2086
        20: polynom = 32'b10000010000000000000;             // 0x82000
2087
        21: polynom = 32'b101000000000000000000;            // 0x140000
2088
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2089
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2090
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2091
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2092
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2093
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2094
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2095
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2096
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2097
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2098
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2099
        default: polynom = 32'b0;
2100
        endcase
2101
        lfsr_fb = qi[length];
2102
        for (i=length-1; i>=1; i=i-1) begin
2103
            if (polynom[i])
2104
                lfsr_fb = lfsr_fb  ~^ qi[i];
2105
        end
2106
    end
2107
   assign q_next =  clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2108
 
2109
   always @ (posedge clk or posedge rst)
2110
     if (rst)
2111
       qi <= {length{1'b0}};
2112
     else
2113
     if (cke)
2114
       qi <= q_next;
2115
 
2116
   assign q = qi;
2117
 
2118
endmodule
2119
//////////////////////////////////////////////////////////////////////
2120
////                                                              ////
2121
////  Versatile counter                                           ////
2122
////                                                              ////
2123
////  Description                                                 ////
2124
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2125
////  counter                                                     ////
2126
////                                                              ////
2127
////  To Do:                                                      ////
2128
////   - add LFSR with more taps                                  ////
2129
////                                                              ////
2130
////  Author(s):                                                  ////
2131
////      - Michael Unneback, unneback@opencores.org              ////
2132
////        ORSoC AB                                              ////
2133
////                                                              ////
2134
//////////////////////////////////////////////////////////////////////
2135
////                                                              ////
2136
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2137
////                                                              ////
2138
//// This source file may be used and distributed without         ////
2139
//// restriction provided that this copyright statement is not    ////
2140
//// removed from the file and that any derivative work contains  ////
2141
//// the original copyright notice and the associated disclaimer. ////
2142
////                                                              ////
2143
//// This source file is free software; you can redistribute it   ////
2144
//// and/or modify it under the terms of the GNU Lesser General   ////
2145
//// Public License as published by the Free Software Foundation; ////
2146
//// either version 2.1 of the License, or (at your option) any   ////
2147
//// later version.                                               ////
2148
////                                                              ////
2149
//// This source is distributed in the hope that it will be       ////
2150
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2151
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2152
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2153
//// details.                                                     ////
2154
////                                                              ////
2155
//// You should have received a copy of the GNU Lesser General    ////
2156
//// Public License along with this source; if not, download it   ////
2157
//// from http://www.opencores.org/lgpl.shtml                     ////
2158
////                                                              ////
2159
//////////////////////////////////////////////////////////////////////
2160
 
2161
// LFSR counter
2162 22 unneback
module vl_cnt_lfsr_ce_q_zq ( cke, q, zq, rst, clk);
2163
 
2164
   parameter length = 4;
2165
   input cke;
2166
   output [length:1] q;
2167
   output reg zq;
2168
   input rst;
2169
   input clk;
2170
 
2171
   parameter clear_value = 0;
2172
   parameter set_value = 1;
2173
   parameter wrap_value = 8;
2174
   parameter level1_value = 15;
2175
 
2176
   reg  [length:1] qi;
2177
   reg lfsr_fb;
2178
   wire [length:1] q_next;
2179
   reg [32:1] polynom;
2180
   integer i;
2181
 
2182
   always @ (qi)
2183
   begin
2184
        case (length)
2185
         2: polynom = 32'b11;                               // 0x3
2186
         3: polynom = 32'b110;                              // 0x6
2187
         4: polynom = 32'b1100;                             // 0xC
2188
         5: polynom = 32'b10100;                            // 0x14
2189
         6: polynom = 32'b110000;                           // 0x30
2190
         7: polynom = 32'b1100000;                          // 0x60
2191
         8: polynom = 32'b10111000;                         // 0xb8
2192
         9: polynom = 32'b100010000;                        // 0x110
2193
        10: polynom = 32'b1001000000;                       // 0x240
2194
        11: polynom = 32'b10100000000;                      // 0x500
2195
        12: polynom = 32'b100000101001;                     // 0x829
2196
        13: polynom = 32'b1000000001100;                    // 0x100C
2197
        14: polynom = 32'b10000000010101;                   // 0x2015
2198
        15: polynom = 32'b110000000000000;                  // 0x6000
2199
        16: polynom = 32'b1101000000001000;                 // 0xD008
2200
        17: polynom = 32'b10010000000000000;                // 0x12000
2201
        18: polynom = 32'b100000010000000000;               // 0x20400
2202
        19: polynom = 32'b1000000000000100011;              // 0x40023
2203
        20: polynom = 32'b10000010000000000000;             // 0x82000
2204
        21: polynom = 32'b101000000000000000000;            // 0x140000
2205
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2206
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2207
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2208
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2209
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2210
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2211
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2212
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2213
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2214
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2215
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2216
        default: polynom = 32'b0;
2217
        endcase
2218
        lfsr_fb = qi[length];
2219
        for (i=length-1; i>=1; i=i-1) begin
2220
            if (polynom[i])
2221
                lfsr_fb = lfsr_fb  ~^ qi[i];
2222
        end
2223
    end
2224
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2225
 
2226
   always @ (posedge clk or posedge rst)
2227
     if (rst)
2228
       qi <= {length{1'b0}};
2229
     else
2230
     if (cke)
2231
       qi <= q_next;
2232
 
2233
   assign q = qi;
2234
 
2235
 
2236
   always @ (posedge clk or posedge rst)
2237
     if (rst)
2238
       zq <= 1'b1;
2239
     else
2240
     if (cke)
2241
       zq <= q_next == {length{1'b0}};
2242
endmodule
2243
//////////////////////////////////////////////////////////////////////
2244
////                                                              ////
2245
////  Versatile counter                                           ////
2246
////                                                              ////
2247
////  Description                                                 ////
2248
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2249
////  counter                                                     ////
2250
////                                                              ////
2251
////  To Do:                                                      ////
2252
////   - add LFSR with more taps                                  ////
2253
////                                                              ////
2254
////  Author(s):                                                  ////
2255
////      - Michael Unneback, unneback@opencores.org              ////
2256
////        ORSoC AB                                              ////
2257
////                                                              ////
2258
//////////////////////////////////////////////////////////////////////
2259
////                                                              ////
2260
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2261
////                                                              ////
2262
//// This source file may be used and distributed without         ////
2263
//// restriction provided that this copyright statement is not    ////
2264
//// removed from the file and that any derivative work contains  ////
2265
//// the original copyright notice and the associated disclaimer. ////
2266
////                                                              ////
2267
//// This source file is free software; you can redistribute it   ////
2268
//// and/or modify it under the terms of the GNU Lesser General   ////
2269
//// Public License as published by the Free Software Foundation; ////
2270
//// either version 2.1 of the License, or (at your option) any   ////
2271
//// later version.                                               ////
2272
////                                                              ////
2273
//// This source is distributed in the hope that it will be       ////
2274
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2275
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2276
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2277
//// details.                                                     ////
2278
////                                                              ////
2279
//// You should have received a copy of the GNU Lesser General    ////
2280
//// Public License along with this source; if not, download it   ////
2281
//// from http://www.opencores.org/lgpl.shtml                     ////
2282
////                                                              ////
2283
//////////////////////////////////////////////////////////////////////
2284 6 unneback
 
2285
// LFSR counter
2286 18 unneback
module vl_cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk);
2287 6 unneback
 
2288
   parameter length = 4;
2289
   input cke;
2290
   input rew;
2291
   output reg level1;
2292
   input rst;
2293
   input clk;
2294
 
2295
   parameter clear_value = 0;
2296
   parameter set_value = 1;
2297
   parameter wrap_value = 8;
2298
   parameter level1_value = 15;
2299
 
2300 29 unneback
   wire clear;
2301 30 unneback
   assign clear = 1'b0;
2302 6 unneback
   reg  [length:1] qi;
2303
   reg lfsr_fb, lfsr_fb_rew;
2304
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2305
   reg [32:1] polynom_rew;
2306
   integer j;
2307
   reg [32:1] polynom;
2308
   integer i;
2309
 
2310
   always @ (qi)
2311
   begin
2312
        case (length)
2313
         2: polynom = 32'b11;                               // 0x3
2314
         3: polynom = 32'b110;                              // 0x6
2315
         4: polynom = 32'b1100;                             // 0xC
2316
         5: polynom = 32'b10100;                            // 0x14
2317
         6: polynom = 32'b110000;                           // 0x30
2318
         7: polynom = 32'b1100000;                          // 0x60
2319
         8: polynom = 32'b10111000;                         // 0xb8
2320
         9: polynom = 32'b100010000;                        // 0x110
2321
        10: polynom = 32'b1001000000;                       // 0x240
2322
        11: polynom = 32'b10100000000;                      // 0x500
2323
        12: polynom = 32'b100000101001;                     // 0x829
2324
        13: polynom = 32'b1000000001100;                    // 0x100C
2325
        14: polynom = 32'b10000000010101;                   // 0x2015
2326
        15: polynom = 32'b110000000000000;                  // 0x6000
2327
        16: polynom = 32'b1101000000001000;                 // 0xD008
2328
        17: polynom = 32'b10010000000000000;                // 0x12000
2329
        18: polynom = 32'b100000010000000000;               // 0x20400
2330
        19: polynom = 32'b1000000000000100011;              // 0x40023
2331
        20: polynom = 32'b10000010000000000000;             // 0x82000
2332
        21: polynom = 32'b101000000000000000000;            // 0x140000
2333
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2334
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2335
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2336
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2337
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2338
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2339
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2340
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2341
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2342
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2343
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2344
        default: polynom = 32'b0;
2345
        endcase
2346
        lfsr_fb = qi[length];
2347
        for (i=length-1; i>=1; i=i-1) begin
2348
            if (polynom[i])
2349
                lfsr_fb = lfsr_fb  ~^ qi[i];
2350
        end
2351
    end
2352
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2353
   always @ (qi)
2354
   begin
2355
        case (length)
2356
         2: polynom_rew = 32'b11;
2357
         3: polynom_rew = 32'b110;
2358
         4: polynom_rew = 32'b1100;
2359
         5: polynom_rew = 32'b10100;
2360
         6: polynom_rew = 32'b110000;
2361
         7: polynom_rew = 32'b1100000;
2362
         8: polynom_rew = 32'b10111000;
2363
         9: polynom_rew = 32'b100010000;
2364
        10: polynom_rew = 32'b1001000000;
2365
        11: polynom_rew = 32'b10100000000;
2366
        12: polynom_rew = 32'b100000101001;
2367
        13: polynom_rew = 32'b1000000001100;
2368
        14: polynom_rew = 32'b10000000010101;
2369
        15: polynom_rew = 32'b110000000000000;
2370
        16: polynom_rew = 32'b1101000000001000;
2371
        17: polynom_rew = 32'b10010000000000000;
2372
        18: polynom_rew = 32'b100000010000000000;
2373
        19: polynom_rew = 32'b1000000000000100011;
2374
        20: polynom_rew = 32'b10000010000000000000;
2375
        21: polynom_rew = 32'b101000000000000000000;
2376
        22: polynom_rew = 32'b1100000000000000000000;
2377
        23: polynom_rew = 32'b10000100000000000000000;
2378
        24: polynom_rew = 32'b111000010000000000000000;
2379
        25: polynom_rew = 32'b1001000000000000000000000;
2380
        26: polynom_rew = 32'b10000000000000000000100011;
2381
        27: polynom_rew = 32'b100000000000000000000010011;
2382
        28: polynom_rew = 32'b1100100000000000000000000000;
2383
        29: polynom_rew = 32'b10100000000000000000000000000;
2384
        30: polynom_rew = 32'b100000000000000000000000101001;
2385
        31: polynom_rew = 32'b1001000000000000000000000000000;
2386
        32: polynom_rew = 32'b10000000001000000000000000000011;
2387
        default: polynom_rew = 32'b0;
2388
        endcase
2389
        // rotate left
2390
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
2391
        lfsr_fb_rew = qi[length];
2392
        for (i=length-1; i>=1; i=i-1) begin
2393
            if (polynom_rew[i])
2394
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
2395
        end
2396
    end
2397
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
2398
   assign q_next = rew ? q_next_rew : q_next_fw;
2399
 
2400
   always @ (posedge clk or posedge rst)
2401
     if (rst)
2402
       qi <= {length{1'b0}};
2403
     else
2404
     if (cke)
2405
       qi <= q_next;
2406
 
2407
 
2408
 
2409
    always @ (posedge clk or posedge rst)
2410
    if (rst)
2411
        level1 <= 1'b0;
2412
    else
2413
    if (cke)
2414 29 unneback
    if (clear)
2415
        level1 <= 1'b0;
2416
    else if (q_next == level1_value)
2417 6 unneback
        level1 <= 1'b1;
2418
    else if (qi == level1_value & rew)
2419
        level1 <= 1'b0;
2420
endmodule
2421
//////////////////////////////////////////////////////////////////////
2422
////                                                              ////
2423
////  Versatile counter                                           ////
2424
////                                                              ////
2425
////  Description                                                 ////
2426
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2427
////  counter                                                     ////
2428
////                                                              ////
2429
////  To Do:                                                      ////
2430
////   - add LFSR with more taps                                  ////
2431
////                                                              ////
2432
////  Author(s):                                                  ////
2433
////      - Michael Unneback, unneback@opencores.org              ////
2434
////        ORSoC AB                                              ////
2435
////                                                              ////
2436
//////////////////////////////////////////////////////////////////////
2437
////                                                              ////
2438
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2439
////                                                              ////
2440
//// This source file may be used and distributed without         ////
2441
//// restriction provided that this copyright statement is not    ////
2442
//// removed from the file and that any derivative work contains  ////
2443
//// the original copyright notice and the associated disclaimer. ////
2444
////                                                              ////
2445
//// This source file is free software; you can redistribute it   ////
2446
//// and/or modify it under the terms of the GNU Lesser General   ////
2447
//// Public License as published by the Free Software Foundation; ////
2448
//// either version 2.1 of the License, or (at your option) any   ////
2449
//// later version.                                               ////
2450
////                                                              ////
2451
//// This source is distributed in the hope that it will be       ////
2452
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2453
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2454
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2455
//// details.                                                     ////
2456
////                                                              ////
2457
//// You should have received a copy of the GNU Lesser General    ////
2458
//// Public License along with this source; if not, download it   ////
2459
//// from http://www.opencores.org/lgpl.shtml                     ////
2460
////                                                              ////
2461
//////////////////////////////////////////////////////////////////////
2462
 
2463
// GRAY counter
2464 18 unneback
module vl_cnt_gray ( q, rst, clk);
2465 6 unneback
 
2466
   parameter length = 4;
2467
   output reg [length:1] q;
2468
   input rst;
2469
   input clk;
2470
 
2471
   parameter clear_value = 0;
2472
   parameter set_value = 1;
2473
   parameter wrap_value = 8;
2474
   parameter level1_value = 15;
2475
 
2476
   reg  [length:1] qi;
2477
   wire [length:1] q_next;
2478
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2479
 
2480
   always @ (posedge clk or posedge rst)
2481
     if (rst)
2482
       qi <= {length{1'b0}};
2483
     else
2484
       qi <= q_next;
2485
 
2486
   always @ (posedge clk or posedge rst)
2487
     if (rst)
2488
       q <= {length{1'b0}};
2489
     else
2490
         q <= (q_next>>1) ^ q_next;
2491
 
2492
endmodule
2493
//////////////////////////////////////////////////////////////////////
2494
////                                                              ////
2495
////  Versatile counter                                           ////
2496
////                                                              ////
2497
////  Description                                                 ////
2498
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2499
////  counter                                                     ////
2500
////                                                              ////
2501
////  To Do:                                                      ////
2502
////   - add LFSR with more taps                                  ////
2503
////                                                              ////
2504
////  Author(s):                                                  ////
2505
////      - Michael Unneback, unneback@opencores.org              ////
2506
////        ORSoC AB                                              ////
2507
////                                                              ////
2508
//////////////////////////////////////////////////////////////////////
2509
////                                                              ////
2510
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2511
////                                                              ////
2512
//// This source file may be used and distributed without         ////
2513
//// restriction provided that this copyright statement is not    ////
2514
//// removed from the file and that any derivative work contains  ////
2515
//// the original copyright notice and the associated disclaimer. ////
2516
////                                                              ////
2517
//// This source file is free software; you can redistribute it   ////
2518
//// and/or modify it under the terms of the GNU Lesser General   ////
2519
//// Public License as published by the Free Software Foundation; ////
2520
//// either version 2.1 of the License, or (at your option) any   ////
2521
//// later version.                                               ////
2522
////                                                              ////
2523
//// This source is distributed in the hope that it will be       ////
2524
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2525
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2526
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2527
//// details.                                                     ////
2528
////                                                              ////
2529
//// You should have received a copy of the GNU Lesser General    ////
2530
//// Public License along with this source; if not, download it   ////
2531
//// from http://www.opencores.org/lgpl.shtml                     ////
2532
////                                                              ////
2533
//////////////////////////////////////////////////////////////////////
2534
 
2535
// GRAY counter
2536 18 unneback
module vl_cnt_gray_ce ( cke, q, rst, clk);
2537 6 unneback
 
2538
   parameter length = 4;
2539
   input cke;
2540
   output reg [length:1] q;
2541
   input rst;
2542
   input clk;
2543
 
2544
   parameter clear_value = 0;
2545
   parameter set_value = 1;
2546
   parameter wrap_value = 8;
2547
   parameter level1_value = 15;
2548
 
2549
   reg  [length:1] qi;
2550
   wire [length:1] q_next;
2551
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2552
 
2553
   always @ (posedge clk or posedge rst)
2554
     if (rst)
2555
       qi <= {length{1'b0}};
2556
     else
2557
     if (cke)
2558
       qi <= q_next;
2559
 
2560
   always @ (posedge clk or posedge rst)
2561
     if (rst)
2562
       q <= {length{1'b0}};
2563
     else
2564
       if (cke)
2565
         q <= (q_next>>1) ^ q_next;
2566
 
2567
endmodule
2568
//////////////////////////////////////////////////////////////////////
2569
////                                                              ////
2570
////  Versatile counter                                           ////
2571
////                                                              ////
2572
////  Description                                                 ////
2573
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2574
////  counter                                                     ////
2575
////                                                              ////
2576
////  To Do:                                                      ////
2577
////   - add LFSR with more taps                                  ////
2578
////                                                              ////
2579
////  Author(s):                                                  ////
2580
////      - Michael Unneback, unneback@opencores.org              ////
2581
////        ORSoC AB                                              ////
2582
////                                                              ////
2583
//////////////////////////////////////////////////////////////////////
2584
////                                                              ////
2585
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2586
////                                                              ////
2587
//// This source file may be used and distributed without         ////
2588
//// restriction provided that this copyright statement is not    ////
2589
//// removed from the file and that any derivative work contains  ////
2590
//// the original copyright notice and the associated disclaimer. ////
2591
////                                                              ////
2592
//// This source file is free software; you can redistribute it   ////
2593
//// and/or modify it under the terms of the GNU Lesser General   ////
2594
//// Public License as published by the Free Software Foundation; ////
2595
//// either version 2.1 of the License, or (at your option) any   ////
2596
//// later version.                                               ////
2597
////                                                              ////
2598
//// This source is distributed in the hope that it will be       ////
2599
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2600
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2601
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2602
//// details.                                                     ////
2603
////                                                              ////
2604
//// You should have received a copy of the GNU Lesser General    ////
2605
//// Public License along with this source; if not, download it   ////
2606
//// from http://www.opencores.org/lgpl.shtml                     ////
2607
////                                                              ////
2608
//////////////////////////////////////////////////////////////////////
2609
 
2610
// GRAY counter
2611 18 unneback
module vl_cnt_gray_ce_bin ( cke, q, q_bin, rst, clk);
2612 6 unneback
 
2613
   parameter length = 4;
2614
   input cke;
2615
   output reg [length:1] q;
2616
   output [length:1] q_bin;
2617
   input rst;
2618
   input clk;
2619
 
2620
   parameter clear_value = 0;
2621
   parameter set_value = 1;
2622
   parameter wrap_value = 8;
2623
   parameter level1_value = 15;
2624
 
2625
   reg  [length:1] qi;
2626
   wire [length:1] q_next;
2627
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2628
 
2629
   always @ (posedge clk or posedge rst)
2630
     if (rst)
2631
       qi <= {length{1'b0}};
2632
     else
2633
     if (cke)
2634
       qi <= q_next;
2635
 
2636
   always @ (posedge clk or posedge rst)
2637
     if (rst)
2638
       q <= {length{1'b0}};
2639
     else
2640
       if (cke)
2641
         q <= (q_next>>1) ^ q_next;
2642
 
2643
   assign q_bin = qi;
2644
 
2645
endmodule
2646
//////////////////////////////////////////////////////////////////////
2647
////                                                              ////
2648
////  Versatile library, counters                                 ////
2649
////                                                              ////
2650
////  Description                                                 ////
2651
////  counters                                                    ////
2652
////                                                              ////
2653
////                                                              ////
2654
////  To Do:                                                      ////
2655
////   - add more counters                                        ////
2656
////                                                              ////
2657
////  Author(s):                                                  ////
2658
////      - Michael Unneback, unneback@opencores.org              ////
2659
////        ORSoC AB                                              ////
2660
////                                                              ////
2661
//////////////////////////////////////////////////////////////////////
2662
////                                                              ////
2663
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2664
////                                                              ////
2665
//// This source file may be used and distributed without         ////
2666
//// restriction provided that this copyright statement is not    ////
2667
//// removed from the file and that any derivative work contains  ////
2668
//// the original copyright notice and the associated disclaimer. ////
2669
////                                                              ////
2670
//// This source file is free software; you can redistribute it   ////
2671
//// and/or modify it under the terms of the GNU Lesser General   ////
2672
//// Public License as published by the Free Software Foundation; ////
2673
//// either version 2.1 of the License, or (at your option) any   ////
2674
//// later version.                                               ////
2675
////                                                              ////
2676
//// This source is distributed in the hope that it will be       ////
2677
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2678
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2679
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2680
//// details.                                                     ////
2681
////                                                              ////
2682
//// You should have received a copy of the GNU Lesser General    ////
2683
//// Public License along with this source; if not, download it   ////
2684
//// from http://www.opencores.org/lgpl.shtml                     ////
2685
////                                                              ////
2686
//////////////////////////////////////////////////////////////////////
2687
 
2688 18 unneback
module vl_cnt_shreg_wrap ( q, rst, clk);
2689 6 unneback
 
2690
   parameter length = 4;
2691
   output reg [0:length-1] q;
2692
   input rst;
2693
   input clk;
2694
 
2695
    always @ (posedge clk or posedge rst)
2696
    if (rst)
2697
        q <= {1'b1,{length-1{1'b0}}};
2698
    else
2699
        q <= {q[length-1],q[0:length-2]};
2700
 
2701
endmodule
2702
 
2703 18 unneback
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
2704 6 unneback
 
2705
   parameter length = 4;
2706
   input cke;
2707
   output reg [0:length-1] q;
2708
   input rst;
2709
   input clk;
2710
 
2711
    always @ (posedge clk or posedge rst)
2712
    if (rst)
2713
        q <= {1'b1,{length-1{1'b0}}};
2714
    else
2715
        if (cke)
2716
            q <= {q[length-1],q[0:length-2]};
2717
 
2718
endmodule
2719
 
2720 18 unneback
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
2721 6 unneback
 
2722
   parameter length = 4;
2723
   input cke, clear;
2724
   output reg [0:length-1] q;
2725
   input rst;
2726
   input clk;
2727
 
2728
    always @ (posedge clk or posedge rst)
2729
    if (rst)
2730
        q <= {1'b1,{length-1{1'b0}}};
2731
    else
2732
        if (cke)
2733
            if (clear)
2734
                q <= {1'b1,{length-1{1'b0}}};
2735
            else
2736
                q <= q >> 1;
2737
 
2738
endmodule
2739
 
2740 18 unneback
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
2741 6 unneback
 
2742
   parameter length = 4;
2743
   input cke, clear;
2744
   output reg [0:length-1] q;
2745