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1 6 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  Versatile library, clock and reset                          ////
4
////                                                              ////
5
////  Description                                                 ////
6
////  Logic related to clock and reset                            ////
7
////                                                              ////
8
////                                                              ////
9
////  To Do:                                                      ////
10
////   - add more different registers                             ////
11
////                                                              ////
12
////  Author(s):                                                  ////
13
////      - Michael Unneback, unneback@opencores.org              ////
14
////        ORSoC AB                                              ////
15
////                                                              ////
16
//////////////////////////////////////////////////////////////////////
17
////                                                              ////
18
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
19
////                                                              ////
20
//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
36
////                                                              ////
37
//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
 
43
// Global buffer
44
// usage:
45
// use to enable global buffers for high fan out signals such as clock and reset
46
 
47
`ifdef ACTEL
48
 
49
`timescale 1 ns/100 ps
50
// Version: 8.4 8.4.0.33
51
module gbuf(GL,CLK);
52
output GL;
53
input  CLK;
54
 
55
    wire GND;
56
 
57
    GND GND_1_net(.Y(GND));
58
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
59
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
60
 
61
endmodule
62
`timescale 1 ns/1 ns
63
module vl_gbuf ( i, o);
64
input i;
65
output o;
66
`ifdef SIM_GBUF
67
assign o=i;
68
`else
69
gbuf gbuf_i0 ( .CLK(i), .GL(o));
70
`endif
71
endmodule
72 33 unneback
 
73 6 unneback
`else
74 33 unneback
 
75 6 unneback
`ifdef ALTERA
76 21 unneback
//altera
77 33 unneback
module vl_gbuf ( i, o);
78
input i;
79
output o;
80
assign o = i;
81
endmodule
82
 
83 6 unneback
`else
84
 
85
`timescale 1 ns/100 ps
86
module vl_gbuf ( i, o);
87
input i;
88
output o;
89
assign o = i;
90
endmodule
91
`endif // ALTERA
92
`endif //ACTEL
93
 
94
// sync reset
95 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
96 6 unneback
// output active high global reset sync with two DFFs 
97
`timescale 1 ns/100 ps
98
module vl_sync_rst ( rst_n_i, rst_o, clk);
99
input rst_n_i, clk;
100
output rst_o;
101 18 unneback
reg [1:0] tmp;
102 6 unneback
always @ (posedge clk or negedge rst_n_i)
103
if (!rst_n_i)
104 17 unneback
        tmp <= 2'b11;
105 6 unneback
else
106 33 unneback
        tmp <= {1'b0,tmp[1]};
107 17 unneback
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
108 6 unneback
endmodule
109
 
110
// vl_pll
111
`ifdef ACTEL
112 32 unneback
///////////////////////////////////////////////////////////////////////////////
113 17 unneback
`timescale 1 ps/1 ps
114 6 unneback
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
115
parameter index = 0;
116
parameter number_of_clk = 1;
117 17 unneback
parameter period_time_0 = 20000;
118
parameter period_time_1 = 20000;
119
parameter period_time_2 = 20000;
120
parameter lock_delay = 2000000;
121 6 unneback
input clk_i, rst_n_i;
122
output lock;
123
output reg [0:number_of_clk-1] clk_o;
124
output [0:number_of_clk-1] rst_o;
125
 
126
`ifdef SIM_PLL
127
 
128
always
129
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
130
 
131
generate if (number_of_clk > 1)
132
always
133
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
134
endgenerate
135
 
136
generate if (number_of_clk > 2)
137
always
138
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
139
endgenerate
140
 
141
genvar i;
142
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
143
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
144
end
145
endgenerate
146
 
147
assign #lock_delay lock = rst_n_i;
148
 
149
endmodule
150
`else
151
generate if (number_of_clk==1 & index==0) begin
152
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
153
end
154
endgenerate // index==0
155
generate if (number_of_clk==1 & index==1) begin
156
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
157
end
158
endgenerate // index==1
159
generate if (number_of_clk==1 & index==2) begin
160
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
161
end
162
endgenerate // index==2
163
generate if (number_of_clk==1 & index==3) begin
164
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
165
end
166
endgenerate // index==0
167
 
168
generate if (number_of_clk==2 & index==0) begin
169
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
170
end
171
endgenerate // index==0
172
generate if (number_of_clk==2 & index==1) begin
173
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
174
end
175
endgenerate // index==1
176
generate if (number_of_clk==2 & index==2) begin
177
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
178
end
179
endgenerate // index==2
180
generate if (number_of_clk==2 & index==3) begin
181
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
182
end
183
endgenerate // index==0
184
 
185
generate if (number_of_clk==3 & index==0) begin
186
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
187
end
188
endgenerate // index==0
189
generate if (number_of_clk==3 & index==1) begin
190
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
191
end
192
endgenerate // index==1
193
generate if (number_of_clk==3 & index==2) begin
194
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
195
end
196
endgenerate // index==2
197
generate if (number_of_clk==3 & index==3) begin
198
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
199
end
200
endgenerate // index==0
201
 
202
genvar i;
203
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
204
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
205
end
206
endgenerate
207
endmodule
208
`endif
209 32 unneback
///////////////////////////////////////////////////////////////////////////////
210 6 unneback
 
211
`else
212
 
213 32 unneback
///////////////////////////////////////////////////////////////////////////////
214 6 unneback
`ifdef ALTERA
215
 
216 32 unneback
`timescale 1 ps/1 ps
217
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
218
parameter index = 0;
219
parameter number_of_clk = 1;
220
parameter period_time_0 = 20000;
221
parameter period_time_1 = 20000;
222
parameter period_time_2 = 20000;
223
parameter period_time_3 = 20000;
224
parameter period_time_4 = 20000;
225
parameter lock_delay = 2000000;
226
input clk_i, rst_n_i;
227
output lock;
228
output reg [0:number_of_clk-1] clk_o;
229
output [0:number_of_clk-1] rst_o;
230
 
231
`ifdef SIM_PLL
232
 
233
always
234
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
235
 
236
generate if (number_of_clk > 1)
237
always
238
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
239
endgenerate
240
 
241
generate if (number_of_clk > 2)
242
always
243
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
244
endgenerate
245
 
246 33 unneback
generate if (number_of_clk > 3)
247 32 unneback
always
248
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
249
endgenerate
250
 
251 33 unneback
generate if (number_of_clk > 4)
252 32 unneback
always
253
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
254
endgenerate
255
 
256
genvar i;
257
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
258
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
259
end
260
endgenerate
261
 
262 33 unneback
//assign #lock_delay lock = rst_n_i;
263
assign lock = rst_n_i;
264 32 unneback
 
265
endmodule
266 6 unneback
`else
267
 
268 33 unneback
`ifdef VL_PLL0
269
`ifdef VL_PLL0_CLK1
270
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
271
`endif
272
`ifdef VL_PLL0_CLK2
273
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
274
`endif
275
`ifdef VL_PLL0_CLK3
276
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
277
`endif
278
`ifdef VL_PLL0_CLK4
279
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
280
`endif
281
`ifdef VL_PLL0_CLK5
282
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
283
`endif
284
`endif
285 32 unneback
 
286 33 unneback
`ifdef VL_PLL1
287
`ifdef VL_PLL1_CLK1
288
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
289
`endif
290
`ifdef VL_PLL1_CLK2
291
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
292
`endif
293
`ifdef VL_PLL1_CLK3
294
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
295
`endif
296
`ifdef VL_PLL1_CLK4
297
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
298
`endif
299
`ifdef VL_PLL1_CLK5
300
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
301
`endif
302
`endif
303 32 unneback
 
304 33 unneback
`ifdef VL_PLL2
305
`ifdef VL_PLL2_CLK1
306
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
307
`endif
308
`ifdef VL_PLL2_CLK2
309
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
310
`endif
311
`ifdef VL_PLL2_CLK3
312
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
313
`endif
314
`ifdef VL_PLL2_CLK4
315
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
316
`endif
317
`ifdef VL_PLL2_CLK5
318
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
319
`endif
320
`endif
321 32 unneback
 
322 33 unneback
`ifdef VL_PLL3
323
`ifdef VL_PLL3_CLK1
324
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
325
`endif
326
`ifdef VL_PLL3_CLK2
327
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
328
`endif
329
`ifdef VL_PLL3_CLK3
330
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
331
`endif
332
`ifdef VL_PLL3_CLK4
333
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
334
`endif
335
`ifdef VL_PLL3_CLK5
336
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
337
`endif
338
`endif
339 32 unneback
 
340
genvar i;
341
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
342 33 unneback
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
343 32 unneback
end
344
endgenerate
345
endmodule
346
`endif
347
///////////////////////////////////////////////////////////////////////////////
348
 
349
`else
350
 
351 6 unneback
// generic PLL
352 17 unneback
`timescale 1 ps/1 ps
353 6 unneback
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
354
parameter index = 0;
355
parameter number_of_clk = 1;
356 17 unneback
parameter period_time_0 = 20000;
357
parameter period_time_1 = 20000;
358
parameter period_time_2 = 20000;
359 6 unneback
parameter lock_delay = 2000;
360
input clk_i, rst_n_i;
361
output lock;
362
output reg [0:number_of_clk-1] clk_o;
363
output [0:number_of_clk-1] rst_o;
364
 
365
always
366
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
367
 
368
generate if (number_of_clk > 1)
369
always
370
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
371
endgenerate
372
 
373
generate if (number_of_clk > 2)
374
always
375
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
376
endgenerate
377
 
378
genvar i;
379
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
380
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
381
end
382
endgenerate
383
 
384
assign #lock_delay lock = rst_n_i;
385
 
386
endmodule
387
 
388
`endif //altera
389 17 unneback
`endif //actel
390
//////////////////////////////////////////////////////////////////////
391 6 unneback
////                                                              ////
392
////  Versatile library, registers                                ////
393
////                                                              ////
394
////  Description                                                 ////
395
////  Different type of registers                                 ////
396
////                                                              ////
397
////                                                              ////
398
////  To Do:                                                      ////
399
////   - add more different registers                             ////
400
////                                                              ////
401
////  Author(s):                                                  ////
402
////      - Michael Unneback, unneback@opencores.org              ////
403
////        ORSoC AB                                              ////
404
////                                                              ////
405
//////////////////////////////////////////////////////////////////////
406
////                                                              ////
407
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
408
////                                                              ////
409
//// This source file may be used and distributed without         ////
410
//// restriction provided that this copyright statement is not    ////
411
//// removed from the file and that any derivative work contains  ////
412
//// the original copyright notice and the associated disclaimer. ////
413
////                                                              ////
414
//// This source file is free software; you can redistribute it   ////
415
//// and/or modify it under the terms of the GNU Lesser General   ////
416
//// Public License as published by the Free Software Foundation; ////
417
//// either version 2.1 of the License, or (at your option) any   ////
418
//// later version.                                               ////
419
////                                                              ////
420
//// This source is distributed in the hope that it will be       ////
421
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
422
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
423
//// PURPOSE.  See the GNU Lesser General Public License for more ////
424
//// details.                                                     ////
425
////                                                              ////
426
//// You should have received a copy of the GNU Lesser General    ////
427
//// Public License along with this source; if not, download it   ////
428
//// from http://www.opencores.org/lgpl.shtml                     ////
429
////                                                              ////
430
//////////////////////////////////////////////////////////////////////
431
 
432 18 unneback
module vl_dff ( d, q, clk, rst);
433 6 unneback
 
434
        parameter width = 1;
435
        parameter reset_value = 0;
436
 
437
        input [width-1:0] d;
438
        input clk, rst;
439
        output reg [width-1:0] q;
440
 
441
        always @ (posedge clk or posedge rst)
442
        if (rst)
443
                q <= reset_value;
444
        else
445
                q <= d;
446
 
447
endmodule
448
 
449 18 unneback
module vl_dff_array ( d, q, clk, rst);
450 6 unneback
 
451
        parameter width = 1;
452
        parameter depth = 2;
453
        parameter reset_value = 1'b0;
454
 
455
        input [width-1:0] d;
456
        input clk, rst;
457
        output [width-1:0] q;
458
        reg  [0:depth-1] q_tmp [width-1:0];
459
        integer i;
460
        always @ (posedge clk or posedge rst)
461
        if (rst) begin
462
            for (i=0;i<depth;i=i+1)
463
                q_tmp[i] <= {width{reset_value}};
464
        end else begin
465
            q_tmp[0] <= d;
466
            for (i=1;i<depth;i=i+1)
467
                q_tmp[i] <= q_tmp[i-1];
468
        end
469
 
470
    assign q = q_tmp[depth-1];
471
 
472
endmodule
473
 
474 18 unneback
module vl_dff_ce ( d, ce, q, clk, rst);
475 6 unneback
 
476
        parameter width = 1;
477
        parameter reset_value = 0;
478
 
479
        input [width-1:0] d;
480
        input ce, clk, rst;
481
        output reg [width-1:0] q;
482
 
483
        always @ (posedge clk or posedge rst)
484
        if (rst)
485
                q <= reset_value;
486
        else
487
                if (ce)
488
                        q <= d;
489
 
490
endmodule
491
 
492 18 unneback
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
493 8 unneback
 
494
        parameter width = 1;
495
        parameter reset_value = 0;
496
 
497
        input [width-1:0] d;
498 10 unneback
        input ce, clear, clk, rst;
499 8 unneback
        output reg [width-1:0] q;
500
 
501
        always @ (posedge clk or posedge rst)
502
        if (rst)
503
            q <= reset_value;
504
        else
505
            if (ce)
506
                if (clear)
507
                    q <= {width{1'b0}};
508
                else
509
                    q <= d;
510
 
511
endmodule
512
 
513 24 unneback
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
514
 
515
        parameter width = 1;
516
        parameter reset_value = 0;
517
 
518
        input [width-1:0] d;
519
        input ce, set, clk, rst;
520
        output reg [width-1:0] q;
521
 
522
        always @ (posedge clk or posedge rst)
523
        if (rst)
524
            q <= reset_value;
525
        else
526
            if (ce)
527
                if (set)
528
                    q <= {width{1'b1}};
529
                else
530
                    q <= d;
531
 
532
endmodule
533
 
534 29 unneback
module vl_spr ( sp, r, q, clk, rst);
535
 
536
        parameter width = 1;
537
        parameter reset_value = 0;
538
 
539
        input sp, r;
540
        output reg q;
541
        input clk, rst;
542
 
543
        always @ (posedge clk or posedge rst)
544
        if (rst)
545
            q <= reset_value;
546
        else
547
            if (sp)
548
                q <= 1'b1;
549
            else if (r)
550
                q <= 1'b0;
551
 
552
endmodule
553
 
554
module vl_srp ( s, rp, q, clk, rst);
555
 
556
        parameter width = 1;
557
        parameter reset_value = 0;
558
 
559
        input s, rp;
560
        output reg q;
561
        input clk, rst;
562
 
563
        always @ (posedge clk or posedge rst)
564
        if (rst)
565
            q <= reset_value;
566
        else
567
            if (rp)
568
                q <= 1'b0;
569
            else if (s)
570
                q <= 1'b1;
571
 
572
endmodule
573
 
574
 
575 6 unneback
`ifdef ALTERA
576
// megafunction wizard: %LPM_FF%
577
// GENERATION: STANDARD
578
// VERSION: WM1.0
579
// MODULE: lpm_ff 
580
 
581
// ============================================================
582
// File Name: dff_sr.v
583
// Megafunction Name(s):
584
//                      lpm_ff
585
//
586
// Simulation Library Files(s):
587
//                      lpm
588
// ============================================================
589
// ************************************************************
590
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
591
//
592
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
593
// ************************************************************
594
 
595
 
596
//Copyright (C) 1991-2010 Altera Corporation
597
//Your use of Altera Corporation's design tools, logic functions 
598
//and other software and tools, and its AMPP partner logic 
599
//functions, and any output files from any of the foregoing 
600
//(including device programming or simulation files), and any 
601
//associated documentation or information are expressly subject 
602
//to the terms and conditions of the Altera Program License 
603
//Subscription Agreement, Altera MegaCore Function License 
604
//Agreement, or other applicable license agreement, including, 
605
//without limitation, that your use is for the sole purpose of 
606
//programming logic devices manufactured by Altera and sold by 
607
//Altera or its authorized distributors.  Please refer to the 
608
//applicable agreement for further details.
609
 
610
 
611
// synopsys translate_off
612
`timescale 1 ps / 1 ps
613
// synopsys translate_on
614 18 unneback
module vl_dff_sr (
615 6 unneback
        aclr,
616
        aset,
617
        clock,
618
        data,
619
        q);
620
 
621
        input     aclr;
622
        input     aset;
623
        input     clock;
624
        input     data;
625
        output    q;
626
 
627
        wire [0:0] sub_wire0;
628
        wire [0:0] sub_wire1 = sub_wire0[0:0];
629
        wire  q = sub_wire1;
630
        wire  sub_wire2 = data;
631
        wire  sub_wire3 = sub_wire2;
632
 
633
        lpm_ff  lpm_ff_component (
634
                                .aclr (aclr),
635
                                .clock (clock),
636
                                .data (sub_wire3),
637
                                .aset (aset),
638
                                .q (sub_wire0)
639
                                // synopsys translate_off
640
                                ,
641
                                .aload (),
642
                                .enable (),
643
                                .sclr (),
644
                                .sload (),
645
                                .sset ()
646
                                // synopsys translate_on
647
                                );
648
        defparam
649
                lpm_ff_component.lpm_fftype = "DFF",
650
                lpm_ff_component.lpm_type = "LPM_FF",
651
                lpm_ff_component.lpm_width = 1;
652
 
653
 
654
endmodule
655
 
656
// ============================================================
657
// CNX file retrieval info
658
// ============================================================
659
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
660
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
661
// Retrieval info: PRIVATE: ASET NUMERIC "1"
662
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
663
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
664
// Retrieval info: PRIVATE: DFF NUMERIC "1"
665
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
666
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
667
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
668
// Retrieval info: PRIVATE: SSET NUMERIC "0"
669
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
670
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
671
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
672
// Retrieval info: PRIVATE: nBit NUMERIC "1"
673
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
674
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
675
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
676
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
677
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
678
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
679
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
680
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
681
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
682
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
683
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
684
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
685
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
686
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
687
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
688
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
689
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
690
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
691
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
692
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
693
// Retrieval info: LIB_FILE: lpm
694
 
695
 
696
`else
697
 
698
 
699 18 unneback
module vl_dff_sr ( aclr, aset, clock, data, q);
700 6 unneback
 
701
    input         aclr;
702
    input         aset;
703
    input         clock;
704
    input         data;
705
    output reg    q;
706
 
707
   always @ (posedge clock or posedge aclr or posedge aset)
708
     if (aclr)
709
       q <= 1'b0;
710
     else if (aset)
711
       q <= 1'b1;
712
     else
713
       q <= data;
714
 
715
endmodule
716
 
717
`endif
718
 
719
// LATCH
720
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
721
`ifdef ALTERA
722 18 unneback
module vl_latch ( d, le, q, clk);
723 6 unneback
input d, le;
724
output q;
725
input clk;
726
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
727
endmodule
728
`else
729
module latch ( d, le, q, clk);
730
input d, le;
731
output q;
732
input clk;/*
733
   always @ (posedge direction_set or posedge direction_clr)
734
     if (direction_clr)
735
       direction <= going_empty;
736
     else
737
       direction <= going_full;*/
738
endmodule
739 15 unneback
`endif
740
 
741 18 unneback
module vl_shreg ( d, q, clk, rst);
742 17 unneback
parameter depth = 10;
743
input d;
744
output q;
745
input clk, rst;
746
 
747
reg [1:depth] dffs;
748
 
749
always @ (posedge clk or posedge rst)
750
if (rst)
751
    dffs <= {depth{1'b0}};
752
else
753
    dffs <= {d,dffs[1:depth-1]};
754
assign q = dffs[depth];
755
endmodule
756
 
757 18 unneback
module vl_shreg_ce ( d, ce, q, clk, rst);
758 17 unneback
parameter depth = 10;
759
input d, ce;
760
output q;
761
input clk, rst;
762
 
763
reg [1:depth] dffs;
764
 
765
always @ (posedge clk or posedge rst)
766
if (rst)
767
    dffs <= {depth{1'b0}};
768
else
769
    if (ce)
770
        dffs <= {d,dffs[1:depth-1]};
771
assign q = dffs[depth];
772
endmodule
773
 
774 18 unneback
module vl_delay ( d, q, clk, rst);
775 15 unneback
parameter depth = 10;
776
input d;
777
output q;
778
input clk, rst;
779
 
780
reg [1:depth] dffs;
781
 
782
always @ (posedge clk or posedge rst)
783
if (rst)
784
    dffs <= {depth{1'b0}};
785
else
786
    dffs <= {d,dffs[1:depth-1]};
787
assign q = dffs[depth];
788 17 unneback
endmodule
789
 
790 18 unneback
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
791 17 unneback
parameter depth = 10;
792
input d;
793
output q, emptyflag;
794
input clk, rst;
795
 
796
reg [1:depth] dffs;
797
 
798
always @ (posedge clk or posedge rst)
799
if (rst)
800
    dffs <= {depth{1'b0}};
801
else
802
    dffs <= {d,dffs[1:depth-1]};
803
assign q = dffs[depth];
804
assign emptyflag = !(|dffs);
805
endmodule
806
//////////////////////////////////////////////////////////////////////
807 6 unneback
////                                                              ////
808 18 unneback
////  Logic functions                                             ////
809
////                                                              ////
810
////  Description                                                 ////
811
////  Logic functions such as multiplexers                        ////
812
////                                                              ////
813
////                                                              ////
814
////  To Do:                                                      ////
815
////   -                                                          ////
816
////                                                              ////
817
////  Author(s):                                                  ////
818
////      - Michael Unneback, unneback@opencores.org              ////
819
////        ORSoC AB                                              ////
820
////                                                              ////
821
//////////////////////////////////////////////////////////////////////
822
////                                                              ////
823
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
824
////                                                              ////
825
//// This source file may be used and distributed without         ////
826
//// restriction provided that this copyright statement is not    ////
827
//// removed from the file and that any derivative work contains  ////
828
//// the original copyright notice and the associated disclaimer. ////
829
////                                                              ////
830
//// This source file is free software; you can redistribute it   ////
831
//// and/or modify it under the terms of the GNU Lesser General   ////
832
//// Public License as published by the Free Software Foundation; ////
833
//// either version 2.1 of the License, or (at your option) any   ////
834
//// later version.                                               ////
835
////                                                              ////
836
//// This source is distributed in the hope that it will be       ////
837
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
838
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
839
//// PURPOSE.  See the GNU Lesser General Public License for more ////
840
//// details.                                                     ////
841
////                                                              ////
842
//// You should have received a copy of the GNU Lesser General    ////
843
//// Public License along with this source; if not, download it   ////
844
//// from http://www.opencores.org/lgpl.shtml                     ////
845
////                                                              ////
846
//////////////////////////////////////////////////////////////////////
847 34 unneback
module vl_mux2_andor ( a1, a0, sel, dout);
848 18 unneback
 
849 34 unneback
parameter width = 32;
850
parameter nr_of_ports = 2;
851
input [width-1:0] a1, a0;
852
input [nr_of_ports-1:0] sel;
853
output [width-1:0] dout;
854
 
855
wire [width-1:0] tmp [nr_of_ports-1:0];
856
integer i;
857
 
858
// and
859
assign tmp[0] = {width{sel[0]}} & a0;
860
assign tmp[1] = {width{sel[1]}} & a1;
861
 
862
// or
863
assign dout = tmp[1] | tmp[0];
864
 
865
endmodule
866
 
867
module vl_mux3_andor ( a2, a1, a0, sel, dout);
868
 
869
parameter width = 32;
870
parameter nr_of_ports = 3;
871
input [width-1:0] a2, a1, a0;
872
input [nr_of_ports-1:0] sel;
873
output [width-1:0] dout;
874
 
875
wire [width-1:0] tmp [nr_of_ports-1:0];
876
integer i;
877
 
878
// and
879
assign tmp[0] = {width{sel[0]}} & a0;
880
assign tmp[1] = {width{sel[1]}} & a1;
881
assign tmp[2] = {width{sel[2]}} & a2;
882
 
883
// or
884
assign dout = tmp[2] | tmp[1] | tmp[0];
885
 
886
endmodule
887
 
888 18 unneback
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
889
 
890
parameter width = 32;
891
parameter nr_of_ports = 4;
892
input [width-1:0] a3, a2, a1, a0;
893
input [nr_of_ports-1:0] sel;
894 22 unneback
output [width-1:0] dout;
895 18 unneback
 
896 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
897 18 unneback
integer i;
898
 
899
// and
900
assign tmp[0] = {width{sel[0]}} & a0;
901
assign tmp[1] = {width{sel[1]}} & a1;
902
assign tmp[2] = {width{sel[2]}} & a2;
903
assign tmp[3] = {width{sel[3]}} & a3;
904
 
905
// or
906
assign dout = tmp[3] | tmp[2] | tmp[1] | tmp[0];
907
 
908
endmodule
909
 
910
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
911
 
912
parameter width = 32;
913
parameter nr_of_ports = 5;
914
input [width-1:0] a4, a3, a2, a1, a0;
915
input [nr_of_ports-1:0] sel;
916 22 unneback
output [width-1:0] dout;
917 18 unneback
 
918 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
919 18 unneback
integer i;
920
 
921
// and
922
assign tmp[0] = {width{sel[0]}} & a0;
923
assign tmp[1] = {width{sel[1]}} & a1;
924
assign tmp[2] = {width{sel[2]}} & a2;
925
assign tmp[3] = {width{sel[3]}} & a3;
926
assign tmp[4] = {width{sel[4]}} & a4;
927
 
928
// or
929
assign dout = tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
930
 
931
endmodule
932
 
933
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
934
 
935
parameter width = 32;
936
parameter nr_of_ports = 6;
937
input [width-1:0] a5, a4, a3, a2, a1, a0;
938
input [nr_of_ports-1:0] sel;
939 22 unneback
output [width-1:0] dout;
940 18 unneback
 
941 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
942 18 unneback
integer i;
943
 
944
// and
945
assign tmp[0] = {width{sel[0]}} & a0;
946
assign tmp[1] = {width{sel[1]}} & a1;
947
assign tmp[2] = {width{sel[2]}} & a2;
948
assign tmp[3] = {width{sel[3]}} & a3;
949
assign tmp[4] = {width{sel[4]}} & a4;
950
assign tmp[5] = {width{sel[5]}} & a5;
951
 
952
// or
953
assign dout = tmp[5] | tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
954
 
955
endmodule
956
//////////////////////////////////////////////////////////////////////
957
////                                                              ////
958 6 unneback
////  Versatile counter                                           ////
959
////                                                              ////
960
////  Description                                                 ////
961
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
962
////  counter                                                     ////
963
////                                                              ////
964
////  To Do:                                                      ////
965
////   - add LFSR with more taps                                  ////
966
////                                                              ////
967
////  Author(s):                                                  ////
968
////      - Michael Unneback, unneback@opencores.org              ////
969
////        ORSoC AB                                              ////
970
////                                                              ////
971
//////////////////////////////////////////////////////////////////////
972
////                                                              ////
973
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
974
////                                                              ////
975
//// This source file may be used and distributed without         ////
976
//// restriction provided that this copyright statement is not    ////
977
//// removed from the file and that any derivative work contains  ////
978
//// the original copyright notice and the associated disclaimer. ////
979
////                                                              ////
980
//// This source file is free software; you can redistribute it   ////
981
//// and/or modify it under the terms of the GNU Lesser General   ////
982
//// Public License as published by the Free Software Foundation; ////
983
//// either version 2.1 of the License, or (at your option) any   ////
984
//// later version.                                               ////
985
////                                                              ////
986
//// This source is distributed in the hope that it will be       ////
987
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
988
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
989
//// PURPOSE.  See the GNU Lesser General Public License for more ////
990
//// details.                                                     ////
991
////                                                              ////
992
//// You should have received a copy of the GNU Lesser General    ////
993
//// Public License along with this source; if not, download it   ////
994
//// from http://www.opencores.org/lgpl.shtml                     ////
995
////                                                              ////
996
//////////////////////////////////////////////////////////////////////
997
 
998
// binary counter
999 22 unneback
module vl_cnt_bin ( q, rst, clk);
1000
 
1001
   parameter length = 4;
1002
   output [length:1] q;
1003
   input rst;
1004
   input clk;
1005
 
1006
   parameter clear_value = 0;
1007
   parameter set_value = 1;
1008
   parameter wrap_value = 0;
1009
   parameter level1_value = 15;
1010
 
1011
   reg  [length:1] qi;
1012
   wire [length:1] q_next;
1013
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1014
 
1015
   always @ (posedge clk or posedge rst)
1016
     if (rst)
1017
       qi <= {length{1'b0}};
1018
     else
1019
       qi <= q_next;
1020
 
1021
   assign q = qi;
1022
 
1023
endmodule
1024
//////////////////////////////////////////////////////////////////////
1025
////                                                              ////
1026
////  Versatile counter                                           ////
1027
////                                                              ////
1028
////  Description                                                 ////
1029
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1030
////  counter                                                     ////
1031
////                                                              ////
1032
////  To Do:                                                      ////
1033
////   - add LFSR with more taps                                  ////
1034
////                                                              ////
1035
////  Author(s):                                                  ////
1036
////      - Michael Unneback, unneback@opencores.org              ////
1037
////        ORSoC AB                                              ////
1038
////                                                              ////
1039
//////////////////////////////////////////////////////////////////////
1040
////                                                              ////
1041
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1042
////                                                              ////
1043
//// This source file may be used and distributed without         ////
1044
//// restriction provided that this copyright statement is not    ////
1045
//// removed from the file and that any derivative work contains  ////
1046
//// the original copyright notice and the associated disclaimer. ////
1047
////                                                              ////
1048
//// This source file is free software; you can redistribute it   ////
1049
//// and/or modify it under the terms of the GNU Lesser General   ////
1050
//// Public License as published by the Free Software Foundation; ////
1051
//// either version 2.1 of the License, or (at your option) any   ////
1052
//// later version.                                               ////
1053
////                                                              ////
1054
//// This source is distributed in the hope that it will be       ////
1055
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1056
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1057
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1058
//// details.                                                     ////
1059
////                                                              ////
1060
//// You should have received a copy of the GNU Lesser General    ////
1061
//// Public License along with this source; if not, download it   ////
1062
//// from http://www.opencores.org/lgpl.shtml                     ////
1063
////                                                              ////
1064
//////////////////////////////////////////////////////////////////////
1065
 
1066
// binary counter
1067
module vl_cnt_bin_clear ( clear, q, rst, clk);
1068
 
1069
   parameter length = 4;
1070
   input clear;
1071
   output [length:1] q;
1072
   input rst;
1073
   input clk;
1074
 
1075
   parameter clear_value = 0;
1076
   parameter set_value = 1;
1077
   parameter wrap_value = 0;
1078
   parameter level1_value = 15;
1079
 
1080
   reg  [length:1] qi;
1081
   wire [length:1] q_next;
1082
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1083
 
1084
   always @ (posedge clk or posedge rst)
1085
     if (rst)
1086
       qi <= {length{1'b0}};
1087
     else
1088
       qi <= q_next;
1089
 
1090
   assign q = qi;
1091
 
1092
endmodule
1093
//////////////////////////////////////////////////////////////////////
1094
////                                                              ////
1095
////  Versatile counter                                           ////
1096
////                                                              ////
1097
////  Description                                                 ////
1098
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1099
////  counter                                                     ////
1100
////                                                              ////
1101
////  To Do:                                                      ////
1102
////   - add LFSR with more taps                                  ////
1103
////                                                              ////
1104
////  Author(s):                                                  ////
1105
////      - Michael Unneback, unneback@opencores.org              ////
1106
////        ORSoC AB                                              ////
1107
////                                                              ////
1108
//////////////////////////////////////////////////////////////////////
1109
////                                                              ////
1110
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1111
////                                                              ////
1112
//// This source file may be used and distributed without         ////
1113
//// restriction provided that this copyright statement is not    ////
1114
//// removed from the file and that any derivative work contains  ////
1115
//// the original copyright notice and the associated disclaimer. ////
1116
////                                                              ////
1117
//// This source file is free software; you can redistribute it   ////
1118
//// and/or modify it under the terms of the GNU Lesser General   ////
1119
//// Public License as published by the Free Software Foundation; ////
1120
//// either version 2.1 of the License, or (at your option) any   ////
1121
//// later version.                                               ////
1122
////                                                              ////
1123
//// This source is distributed in the hope that it will be       ////
1124
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1125
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1126
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1127
//// details.                                                     ////
1128
////                                                              ////
1129
//// You should have received a copy of the GNU Lesser General    ////
1130
//// Public License along with this source; if not, download it   ////
1131
//// from http://www.opencores.org/lgpl.shtml                     ////
1132
////                                                              ////
1133
//////////////////////////////////////////////////////////////////////
1134
 
1135
// binary counter
1136 18 unneback
module vl_cnt_bin_ce ( cke, q, rst, clk);
1137 6 unneback
 
1138
   parameter length = 4;
1139
   input cke;
1140
   output [length:1] q;
1141
   input rst;
1142
   input clk;
1143
 
1144
   parameter clear_value = 0;
1145
   parameter set_value = 1;
1146
   parameter wrap_value = 0;
1147
   parameter level1_value = 15;
1148
 
1149
   reg  [length:1] qi;
1150
   wire [length:1] q_next;
1151
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1152
 
1153
   always @ (posedge clk or posedge rst)
1154
     if (rst)
1155
       qi <= {length{1'b0}};
1156
     else
1157
     if (cke)
1158
       qi <= q_next;
1159
 
1160
   assign q = qi;
1161
 
1162
endmodule
1163
//////////////////////////////////////////////////////////////////////
1164
////                                                              ////
1165
////  Versatile counter                                           ////
1166
////                                                              ////
1167
////  Description                                                 ////
1168
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1169
////  counter                                                     ////
1170
////                                                              ////
1171
////  To Do:                                                      ////
1172
////   - add LFSR with more taps                                  ////
1173
////                                                              ////
1174
////  Author(s):                                                  ////
1175
////      - Michael Unneback, unneback@opencores.org              ////
1176
////        ORSoC AB                                              ////
1177
////                                                              ////
1178
//////////////////////////////////////////////////////////////////////
1179
////                                                              ////
1180
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1181
////                                                              ////
1182
//// This source file may be used and distributed without         ////
1183
//// restriction provided that this copyright statement is not    ////
1184
//// removed from the file and that any derivative work contains  ////
1185
//// the original copyright notice and the associated disclaimer. ////
1186
////                                                              ////
1187
//// This source file is free software; you can redistribute it   ////
1188
//// and/or modify it under the terms of the GNU Lesser General   ////
1189
//// Public License as published by the Free Software Foundation; ////
1190
//// either version 2.1 of the License, or (at your option) any   ////
1191
//// later version.                                               ////
1192
////                                                              ////
1193
//// This source is distributed in the hope that it will be       ////
1194
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1195
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1196
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1197
//// details.                                                     ////
1198
////                                                              ////
1199
//// You should have received a copy of the GNU Lesser General    ////
1200
//// Public License along with this source; if not, download it   ////
1201
//// from http://www.opencores.org/lgpl.shtml                     ////
1202
////                                                              ////
1203
//////////////////////////////////////////////////////////////////////
1204
 
1205
// binary counter
1206 18 unneback
module vl_cnt_bin_ce_clear ( clear, cke, q, rst, clk);
1207 6 unneback
 
1208
   parameter length = 4;
1209
   input clear;
1210
   input cke;
1211
   output [length:1] q;
1212
   input rst;
1213
   input clk;
1214
 
1215
   parameter clear_value = 0;
1216
   parameter set_value = 1;
1217
   parameter wrap_value = 0;
1218
   parameter level1_value = 15;
1219
 
1220
   reg  [length:1] qi;
1221
   wire [length:1] q_next;
1222
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1223
 
1224
   always @ (posedge clk or posedge rst)
1225
     if (rst)
1226
       qi <= {length{1'b0}};
1227
     else
1228
     if (cke)
1229
       qi <= q_next;
1230
 
1231
   assign q = qi;
1232
 
1233
endmodule
1234
//////////////////////////////////////////////////////////////////////
1235
////                                                              ////
1236
////  Versatile counter                                           ////
1237
////                                                              ////
1238
////  Description                                                 ////
1239
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1240
////  counter                                                     ////
1241
////                                                              ////
1242
////  To Do:                                                      ////
1243
////   - add LFSR with more taps                                  ////
1244
////                                                              ////
1245
////  Author(s):                                                  ////
1246
////      - Michael Unneback, unneback@opencores.org              ////
1247
////        ORSoC AB                                              ////
1248
////                                                              ////
1249
//////////////////////////////////////////////////////////////////////
1250
////                                                              ////
1251
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1252
////                                                              ////
1253
//// This source file may be used and distributed without         ////
1254
//// restriction provided that this copyright statement is not    ////
1255
//// removed from the file and that any derivative work contains  ////
1256
//// the original copyright notice and the associated disclaimer. ////
1257
////                                                              ////
1258
//// This source file is free software; you can redistribute it   ////
1259
//// and/or modify it under the terms of the GNU Lesser General   ////
1260
//// Public License as published by the Free Software Foundation; ////
1261
//// either version 2.1 of the License, or (at your option) any   ////
1262
//// later version.                                               ////
1263
////                                                              ////
1264
//// This source is distributed in the hope that it will be       ////
1265
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1266
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1267
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1268
//// details.                                                     ////
1269
////                                                              ////
1270
//// You should have received a copy of the GNU Lesser General    ////
1271
//// Public License along with this source; if not, download it   ////
1272
//// from http://www.opencores.org/lgpl.shtml                     ////
1273
////                                                              ////
1274
//////////////////////////////////////////////////////////////////////
1275
 
1276
// binary counter
1277 29 unneback
module vl_cnt_bin_ce_clear_l1_l2 ( clear, cke, q, level1, level2, rst, clk);
1278
 
1279
   parameter length = 4;
1280
   input clear;
1281
   input cke;
1282
   output [length:1] q;
1283
   output reg level1;
1284
   output reg level2;
1285
   input rst;
1286
   input clk;
1287
 
1288
   parameter clear_value = 0;
1289
   parameter set_value = 1;
1290 30 unneback
   parameter wrap_value = 15;
1291
   parameter level1_value = 8;
1292
   parameter level2_value = 15;
1293 29 unneback
 
1294
   wire rew;
1295 30 unneback
   assign rew = 1'b0;
1296 29 unneback
   reg  [length:1] qi;
1297
   wire [length:1] q_next;
1298
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1299
 
1300
   always @ (posedge clk or posedge rst)
1301
     if (rst)
1302
       qi <= {length{1'b0}};
1303
     else
1304
     if (cke)
1305
       qi <= q_next;
1306
 
1307
   assign q = qi;
1308
 
1309
 
1310
    always @ (posedge clk or posedge rst)
1311
    if (rst)
1312
        level1 <= 1'b0;
1313
    else
1314
    if (cke)
1315
    if (clear)
1316
        level1 <= 1'b0;
1317
    else if (q_next == level1_value)
1318
        level1 <= 1'b1;
1319
    else if (qi == level1_value & rew)
1320
        level1 <= 1'b0;
1321
 
1322
    always @ (posedge clk or posedge rst)
1323
    if (rst)
1324
        level2 <= 1'b0;
1325
    else
1326
    if (cke)
1327
    if (clear)
1328
        level2 <= 1'b0;
1329
    else if (q_next == level2_value)
1330
        level2 <= 1'b1;
1331
    else if (qi == level2_value & rew)
1332
        level2 <= 1'b0;
1333
endmodule
1334
//////////////////////////////////////////////////////////////////////
1335
////                                                              ////
1336
////  Versatile counter                                           ////
1337
////                                                              ////
1338
////  Description                                                 ////
1339
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1340
////  counter                                                     ////
1341
////                                                              ////
1342
////  To Do:                                                      ////
1343
////   - add LFSR with more taps                                  ////
1344
////                                                              ////
1345
////  Author(s):                                                  ////
1346
////      - Michael Unneback, unneback@opencores.org              ////
1347
////        ORSoC AB                                              ////
1348
////                                                              ////
1349
//////////////////////////////////////////////////////////////////////
1350
////                                                              ////
1351
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1352
////                                                              ////
1353
//// This source file may be used and distributed without         ////
1354
//// restriction provided that this copyright statement is not    ////
1355
//// removed from the file and that any derivative work contains  ////
1356
//// the original copyright notice and the associated disclaimer. ////
1357
////                                                              ////
1358
//// This source file is free software; you can redistribute it   ////
1359
//// and/or modify it under the terms of the GNU Lesser General   ////
1360
//// Public License as published by the Free Software Foundation; ////
1361
//// either version 2.1 of the License, or (at your option) any   ////
1362
//// later version.                                               ////
1363
////                                                              ////
1364
//// This source is distributed in the hope that it will be       ////
1365
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1366
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1367
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1368
//// details.                                                     ////
1369
////                                                              ////
1370
//// You should have received a copy of the GNU Lesser General    ////
1371
//// Public License along with this source; if not, download it   ////
1372
//// from http://www.opencores.org/lgpl.shtml                     ////
1373
////                                                              ////
1374
//////////////////////////////////////////////////////////////////////
1375
 
1376
// binary counter
1377 18 unneback
module vl_cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk);
1378 6 unneback
 
1379
   parameter length = 4;
1380
   input clear;
1381
   input set;
1382
   input cke;
1383
   input rew;
1384
   output [length:1] q;
1385
   input rst;
1386
   input clk;
1387
 
1388
   parameter clear_value = 0;
1389
   parameter set_value = 1;
1390
   parameter wrap_value = 0;
1391
   parameter level1_value = 15;
1392
 
1393
   reg  [length:1] qi;
1394
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1395
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
1396
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
1397
   assign q_next = rew ? q_next_rew : q_next_fw;
1398
 
1399
   always @ (posedge clk or posedge rst)
1400
     if (rst)
1401
       qi <= {length{1'b0}};
1402
     else
1403
     if (cke)
1404
       qi <= q_next;
1405
 
1406
   assign q = qi;
1407
 
1408
endmodule
1409
//////////////////////////////////////////////////////////////////////
1410
////                                                              ////
1411
////  Versatile counter                                           ////
1412
////                                                              ////
1413
////  Description                                                 ////
1414
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1415
////  counter                                                     ////
1416
////                                                              ////
1417
////  To Do:                                                      ////
1418
////   - add LFSR with more taps                                  ////
1419
////                                                              ////
1420
////  Author(s):                                                  ////
1421
////      - Michael Unneback, unneback@opencores.org              ////
1422
////        ORSoC AB                                              ////
1423
////                                                              ////
1424
//////////////////////////////////////////////////////////////////////
1425
////                                                              ////
1426
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1427
////                                                              ////
1428
//// This source file may be used and distributed without         ////
1429
//// restriction provided that this copyright statement is not    ////
1430
//// removed from the file and that any derivative work contains  ////
1431
//// the original copyright notice and the associated disclaimer. ////
1432
////                                                              ////
1433
//// This source file is free software; you can redistribute it   ////
1434
//// and/or modify it under the terms of the GNU Lesser General   ////
1435
//// Public License as published by the Free Software Foundation; ////
1436
//// either version 2.1 of the License, or (at your option) any   ////
1437
//// later version.                                               ////
1438
////                                                              ////
1439
//// This source is distributed in the hope that it will be       ////
1440
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1441
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1442
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1443
//// details.                                                     ////
1444
////                                                              ////
1445
//// You should have received a copy of the GNU Lesser General    ////
1446
//// Public License along with this source; if not, download it   ////
1447
//// from http://www.opencores.org/lgpl.shtml                     ////
1448
////                                                              ////
1449
//////////////////////////////////////////////////////////////////////
1450
 
1451
// binary counter
1452 18 unneback
module vl_cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk);
1453 6 unneback
 
1454
   parameter length = 4;
1455
   input cke;
1456
   input rew;
1457
   output reg level1;
1458
   input rst;
1459
   input clk;
1460
 
1461
   parameter clear_value = 0;
1462
   parameter set_value = 1;
1463
   parameter wrap_value = 1;
1464
   parameter level1_value = 15;
1465
 
1466 29 unneback
   wire clear;
1467 30 unneback
   assign clear = 1'b0;
1468 6 unneback
   reg  [length:1] qi;
1469
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1470
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1471
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1472
   assign q_next = rew ? q_next_rew : q_next_fw;
1473
 
1474
   always @ (posedge clk or posedge rst)
1475
     if (rst)
1476
       qi <= {length{1'b0}};
1477
     else
1478
     if (cke)
1479
       qi <= q_next;
1480
 
1481
 
1482
 
1483
    always @ (posedge clk or posedge rst)
1484
    if (rst)
1485
        level1 <= 1'b0;
1486
    else
1487
    if (cke)
1488 29 unneback
    if (clear)
1489
        level1 <= 1'b0;
1490
    else if (q_next == level1_value)
1491 6 unneback
        level1 <= 1'b1;
1492
    else if (qi == level1_value & rew)
1493
        level1 <= 1'b0;
1494
endmodule
1495
//////////////////////////////////////////////////////////////////////
1496
////                                                              ////
1497
////  Versatile counter                                           ////
1498
////                                                              ////
1499
////  Description                                                 ////
1500
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1501
////  counter                                                     ////
1502
////                                                              ////
1503
////  To Do:                                                      ////
1504
////   - add LFSR with more taps                                  ////
1505
////                                                              ////
1506
////  Author(s):                                                  ////
1507
////      - Michael Unneback, unneback@opencores.org              ////
1508
////        ORSoC AB                                              ////
1509
////                                                              ////
1510
//////////////////////////////////////////////////////////////////////
1511
////                                                              ////
1512
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1513
////                                                              ////
1514
//// This source file may be used and distributed without         ////
1515
//// restriction provided that this copyright statement is not    ////
1516
//// removed from the file and that any derivative work contains  ////
1517
//// the original copyright notice and the associated disclaimer. ////
1518
////                                                              ////
1519
//// This source file is free software; you can redistribute it   ////
1520
//// and/or modify it under the terms of the GNU Lesser General   ////
1521
//// Public License as published by the Free Software Foundation; ////
1522
//// either version 2.1 of the License, or (at your option) any   ////
1523
//// later version.                                               ////
1524
////                                                              ////
1525
//// This source is distributed in the hope that it will be       ////
1526
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1527
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1528
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1529
//// details.                                                     ////
1530
////                                                              ////
1531
//// You should have received a copy of the GNU Lesser General    ////
1532
//// Public License along with this source; if not, download it   ////
1533
//// from http://www.opencores.org/lgpl.shtml                     ////
1534
////                                                              ////
1535
//////////////////////////////////////////////////////////////////////
1536
 
1537 25 unneback
// binary counter
1538
module vl_cnt_bin_ce_rew_zq_l1 ( cke, rew, zq, level1, rst, clk);
1539
 
1540
   parameter length = 4;
1541
   input cke;
1542
   input rew;
1543
   output reg zq;
1544
   output reg level1;
1545
   input rst;
1546
   input clk;
1547
 
1548
   parameter clear_value = 0;
1549
   parameter set_value = 1;
1550
   parameter wrap_value = 1;
1551
   parameter level1_value = 15;
1552
 
1553 29 unneback
   wire clear;
1554 30 unneback
   assign clear = 1'b0;
1555 25 unneback
   reg  [length:1] qi;
1556
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1557
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1558
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1559
   assign q_next = rew ? q_next_rew : q_next_fw;
1560
 
1561
   always @ (posedge clk or posedge rst)
1562
     if (rst)
1563
       qi <= {length{1'b0}};
1564
     else
1565
     if (cke)
1566
       qi <= q_next;
1567
 
1568
 
1569
 
1570
   always @ (posedge clk or posedge rst)
1571
     if (rst)
1572
       zq <= 1'b1;
1573
     else
1574
     if (cke)
1575
       zq <= q_next == {length{1'b0}};
1576
 
1577
    always @ (posedge clk or posedge rst)
1578
    if (rst)
1579
        level1 <= 1'b0;
1580
    else
1581
    if (cke)
1582 29 unneback
    if (clear)
1583
        level1 <= 1'b0;
1584
    else if (q_next == level1_value)
1585 25 unneback
        level1 <= 1'b1;
1586
    else if (qi == level1_value & rew)
1587
        level1 <= 1'b0;
1588
endmodule
1589
//////////////////////////////////////////////////////////////////////
1590
////                                                              ////
1591
////  Versatile counter                                           ////
1592
////                                                              ////
1593
////  Description                                                 ////
1594
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1595
////  counter                                                     ////
1596
////                                                              ////
1597
////  To Do:                                                      ////
1598
////   - add LFSR with more taps                                  ////
1599
////                                                              ////
1600
////  Author(s):                                                  ////
1601
////      - Michael Unneback, unneback@opencores.org              ////
1602
////        ORSoC AB                                              ////
1603
////                                                              ////
1604
//////////////////////////////////////////////////////////////////////
1605
////                                                              ////
1606
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1607
////                                                              ////
1608
//// This source file may be used and distributed without         ////
1609
//// restriction provided that this copyright statement is not    ////
1610
//// removed from the file and that any derivative work contains  ////
1611
//// the original copyright notice and the associated disclaimer. ////
1612
////                                                              ////
1613
//// This source file is free software; you can redistribute it   ////
1614
//// and/or modify it under the terms of the GNU Lesser General   ////
1615
//// Public License as published by the Free Software Foundation; ////
1616
//// either version 2.1 of the License, or (at your option) any   ////
1617
//// later version.                                               ////
1618
////                                                              ////
1619
//// This source is distributed in the hope that it will be       ////
1620
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1621
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1622
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1623
//// details.                                                     ////
1624
////                                                              ////
1625
//// You should have received a copy of the GNU Lesser General    ////
1626
//// Public License along with this source; if not, download it   ////
1627
//// from http://www.opencores.org/lgpl.shtml                     ////
1628
////                                                              ////
1629
//////////////////////////////////////////////////////////////////////
1630
 
1631
// binary counter
1632
module vl_cnt_bin_ce_rew_q_zq_l1 ( cke, rew, q, zq, level1, rst, clk);
1633
 
1634
   parameter length = 4;
1635
   input cke;
1636
   input rew;
1637
   output [length:1] q;
1638
   output reg zq;
1639
   output reg level1;
1640
   input rst;
1641
   input clk;
1642
 
1643
   parameter clear_value = 0;
1644
   parameter set_value = 1;
1645
   parameter wrap_value = 1;
1646
   parameter level1_value = 15;
1647
 
1648 29 unneback
   wire clear;
1649 30 unneback
   assign clear = 1'b0;
1650 25 unneback
   reg  [length:1] qi;
1651
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1652
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1653
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1654
   assign q_next = rew ? q_next_rew : q_next_fw;
1655
 
1656
   always @ (posedge clk or posedge rst)
1657
     if (rst)
1658
       qi <= {length{1'b0}};
1659
     else
1660
     if (cke)
1661
       qi <= q_next;
1662
 
1663
   assign q = qi;
1664
 
1665
 
1666
   always @ (posedge clk or posedge rst)
1667
     if (rst)
1668
       zq <= 1'b1;
1669
     else
1670
     if (cke)
1671
       zq <= q_next == {length{1'b0}};
1672
 
1673
    always @ (posedge clk or posedge rst)
1674
    if (rst)
1675
        level1 <= 1'b0;
1676
    else
1677
    if (cke)
1678 29 unneback
    if (clear)
1679
        level1 <= 1'b0;
1680
    else if (q_next == level1_value)
1681 25 unneback
        level1 <= 1'b1;
1682
    else if (qi == level1_value & rew)
1683
        level1 <= 1'b0;
1684
endmodule
1685
//////////////////////////////////////////////////////////////////////
1686
////                                                              ////
1687
////  Versatile counter                                           ////
1688
////                                                              ////
1689
////  Description                                                 ////
1690
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1691
////  counter                                                     ////
1692
////                                                              ////
1693
////  To Do:                                                      ////
1694
////   - add LFSR with more taps                                  ////
1695
////                                                              ////
1696
////  Author(s):                                                  ////
1697
////      - Michael Unneback, unneback@opencores.org              ////
1698
////        ORSoC AB                                              ////
1699
////                                                              ////
1700
//////////////////////////////////////////////////////////////////////
1701
////                                                              ////
1702
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1703
////                                                              ////
1704
//// This source file may be used and distributed without         ////
1705
//// restriction provided that this copyright statement is not    ////
1706
//// removed from the file and that any derivative work contains  ////
1707
//// the original copyright notice and the associated disclaimer. ////
1708
////                                                              ////
1709
//// This source file is free software; you can redistribute it   ////
1710
//// and/or modify it under the terms of the GNU Lesser General   ////
1711
//// Public License as published by the Free Software Foundation; ////
1712
//// either version 2.1 of the License, or (at your option) any   ////
1713
//// later version.                                               ////
1714
////                                                              ////
1715
//// This source is distributed in the hope that it will be       ////
1716
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1717
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1718
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1719
//// details.                                                     ////
1720
////                                                              ////
1721
//// You should have received a copy of the GNU Lesser General    ////
1722
//// Public License along with this source; if not, download it   ////
1723
//// from http://www.opencores.org/lgpl.shtml                     ////
1724
////                                                              ////
1725
//////////////////////////////////////////////////////////////////////
1726
 
1727 6 unneback
// LFSR counter
1728 18 unneback
module vl_cnt_lfsr_zq ( zq, rst, clk);
1729 6 unneback
 
1730
   parameter length = 4;
1731
   output reg zq;
1732
   input rst;
1733
   input clk;
1734
 
1735
   parameter clear_value = 0;
1736
   parameter set_value = 1;
1737
   parameter wrap_value = 8;
1738
   parameter level1_value = 15;
1739
 
1740
   reg  [length:1] qi;
1741
   reg lfsr_fb;
1742
   wire [length:1] q_next;
1743
   reg [32:1] polynom;
1744
   integer i;
1745
 
1746
   always @ (qi)
1747
   begin
1748
        case (length)
1749
         2: polynom = 32'b11;                               // 0x3
1750
         3: polynom = 32'b110;                              // 0x6
1751
         4: polynom = 32'b1100;                             // 0xC
1752
         5: polynom = 32'b10100;                            // 0x14
1753
         6: polynom = 32'b110000;                           // 0x30
1754
         7: polynom = 32'b1100000;                          // 0x60
1755
         8: polynom = 32'b10111000;                         // 0xb8
1756
         9: polynom = 32'b100010000;                        // 0x110
1757
        10: polynom = 32'b1001000000;                       // 0x240
1758
        11: polynom = 32'b10100000000;                      // 0x500
1759
        12: polynom = 32'b100000101001;                     // 0x829
1760
        13: polynom = 32'b1000000001100;                    // 0x100C
1761
        14: polynom = 32'b10000000010101;                   // 0x2015
1762
        15: polynom = 32'b110000000000000;                  // 0x6000
1763
        16: polynom = 32'b1101000000001000;                 // 0xD008
1764
        17: polynom = 32'b10010000000000000;                // 0x12000
1765
        18: polynom = 32'b100000010000000000;               // 0x20400
1766
        19: polynom = 32'b1000000000000100011;              // 0x40023
1767
        20: polynom = 32'b10000010000000000000;             // 0x82000
1768
        21: polynom = 32'b101000000000000000000;            // 0x140000
1769
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1770
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1771
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1772
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1773
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1774
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1775
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1776
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1777
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1778
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1779
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1780
        default: polynom = 32'b0;
1781
        endcase
1782
        lfsr_fb = qi[length];
1783
        for (i=length-1; i>=1; i=i-1) begin
1784
            if (polynom[i])
1785
                lfsr_fb = lfsr_fb  ~^ qi[i];
1786
        end
1787
    end
1788
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1789
 
1790
   always @ (posedge clk or posedge rst)
1791
     if (rst)
1792
       qi <= {length{1'b0}};
1793
     else
1794
       qi <= q_next;
1795
 
1796
 
1797
 
1798
   always @ (posedge clk or posedge rst)
1799
     if (rst)
1800
       zq <= 1'b1;
1801
     else
1802
       zq <= q_next == {length{1'b0}};
1803
endmodule
1804
//////////////////////////////////////////////////////////////////////
1805
////                                                              ////
1806
////  Versatile counter                                           ////
1807
////                                                              ////
1808
////  Description                                                 ////
1809
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1810
////  counter                                                     ////
1811
////                                                              ////
1812
////  To Do:                                                      ////
1813
////   - add LFSR with more taps                                  ////
1814
////                                                              ////
1815
////  Author(s):                                                  ////
1816
////      - Michael Unneback, unneback@opencores.org              ////
1817
////        ORSoC AB                                              ////
1818
////                                                              ////
1819
//////////////////////////////////////////////////////////////////////
1820
////                                                              ////
1821
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1822
////                                                              ////
1823
//// This source file may be used and distributed without         ////
1824
//// restriction provided that this copyright statement is not    ////
1825
//// removed from the file and that any derivative work contains  ////
1826
//// the original copyright notice and the associated disclaimer. ////
1827
////                                                              ////
1828
//// This source file is free software; you can redistribute it   ////
1829
//// and/or modify it under the terms of the GNU Lesser General   ////
1830
//// Public License as published by the Free Software Foundation; ////
1831
//// either version 2.1 of the License, or (at your option) any   ////
1832
//// later version.                                               ////
1833
////                                                              ////
1834
//// This source is distributed in the hope that it will be       ////
1835
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1836
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1837
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1838
//// details.                                                     ////
1839
////                                                              ////
1840
//// You should have received a copy of the GNU Lesser General    ////
1841
//// Public License along with this source; if not, download it   ////
1842
//// from http://www.opencores.org/lgpl.shtml                     ////
1843
////                                                              ////
1844
//////////////////////////////////////////////////////////////////////
1845
 
1846
// LFSR counter
1847 18 unneback
module vl_cnt_lfsr_ce_zq ( cke, zq, rst, clk);
1848 6 unneback
 
1849
   parameter length = 4;
1850
   input cke;
1851
   output reg zq;
1852
   input rst;
1853
   input clk;
1854
 
1855
   parameter clear_value = 0;
1856
   parameter set_value = 1;
1857
   parameter wrap_value = 8;
1858
   parameter level1_value = 15;
1859
 
1860
   reg  [length:1] qi;
1861
   reg lfsr_fb;
1862
   wire [length:1] q_next;
1863
   reg [32:1] polynom;
1864
   integer i;
1865
 
1866
   always @ (qi)
1867
   begin
1868
        case (length)
1869
         2: polynom = 32'b11;                               // 0x3
1870
         3: polynom = 32'b110;                              // 0x6
1871
         4: polynom = 32'b1100;                             // 0xC
1872
         5: polynom = 32'b10100;                            // 0x14
1873
         6: polynom = 32'b110000;                           // 0x30
1874
         7: polynom = 32'b1100000;                          // 0x60
1875
         8: polynom = 32'b10111000;                         // 0xb8
1876
         9: polynom = 32'b100010000;                        // 0x110
1877
        10: polynom = 32'b1001000000;                       // 0x240
1878
        11: polynom = 32'b10100000000;                      // 0x500
1879
        12: polynom = 32'b100000101001;                     // 0x829
1880
        13: polynom = 32'b1000000001100;                    // 0x100C
1881
        14: polynom = 32'b10000000010101;                   // 0x2015
1882
        15: polynom = 32'b110000000000000;                  // 0x6000
1883
        16: polynom = 32'b1101000000001000;                 // 0xD008
1884
        17: polynom = 32'b10010000000000000;                // 0x12000
1885
        18: polynom = 32'b100000010000000000;               // 0x20400
1886
        19: polynom = 32'b1000000000000100011;              // 0x40023
1887
        20: polynom = 32'b10000010000000000000;             // 0x82000
1888
        21: polynom = 32'b101000000000000000000;            // 0x140000
1889
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1890
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1891
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1892
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1893
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1894
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1895
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1896
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1897
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1898
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1899
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1900
        default: polynom = 32'b0;
1901
        endcase
1902
        lfsr_fb = qi[length];
1903
        for (i=length-1; i>=1; i=i-1) begin
1904
            if (polynom[i])
1905
                lfsr_fb = lfsr_fb  ~^ qi[i];
1906
        end
1907
    end
1908
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1909
 
1910
   always @ (posedge clk or posedge rst)
1911
     if (rst)
1912
       qi <= {length{1'b0}};
1913
     else
1914
     if (cke)
1915
       qi <= q_next;
1916
 
1917
 
1918
 
1919
   always @ (posedge clk or posedge rst)
1920
     if (rst)
1921
       zq <= 1'b1;
1922
     else
1923
     if (cke)
1924
       zq <= q_next == {length{1'b0}};
1925
endmodule
1926
//////////////////////////////////////////////////////////////////////
1927
////                                                              ////
1928
////  Versatile counter                                           ////
1929
////                                                              ////
1930
////  Description                                                 ////
1931
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1932
////  counter                                                     ////
1933
////                                                              ////
1934
////  To Do:                                                      ////
1935
////   - add LFSR with more taps                                  ////
1936
////                                                              ////
1937
////  Author(s):                                                  ////
1938
////      - Michael Unneback, unneback@opencores.org              ////
1939
////        ORSoC AB                                              ////
1940
////                                                              ////
1941
//////////////////////////////////////////////////////////////////////
1942
////                                                              ////
1943
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1944
////                                                              ////
1945
//// This source file may be used and distributed without         ////
1946
//// restriction provided that this copyright statement is not    ////
1947
//// removed from the file and that any derivative work contains  ////
1948
//// the original copyright notice and the associated disclaimer. ////
1949
////                                                              ////
1950
//// This source file is free software; you can redistribute it   ////
1951
//// and/or modify it under the terms of the GNU Lesser General   ////
1952
//// Public License as published by the Free Software Foundation; ////
1953
//// either version 2.1 of the License, or (at your option) any   ////
1954
//// later version.                                               ////
1955
////                                                              ////
1956
//// This source is distributed in the hope that it will be       ////
1957
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1958
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1959
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1960
//// details.                                                     ////
1961
////                                                              ////
1962
//// You should have received a copy of the GNU Lesser General    ////
1963
//// Public License along with this source; if not, download it   ////
1964
//// from http://www.opencores.org/lgpl.shtml                     ////
1965
////                                                              ////
1966
//////////////////////////////////////////////////////////////////////
1967 22 unneback
 
1968
// LFSR counter
1969 27 unneback
module vl_cnt_lfsr_ce_q ( cke, q, rst, clk);
1970
 
1971
   parameter length = 4;
1972
   input cke;
1973
   output [length:1] q;
1974
   input rst;
1975
   input clk;
1976
 
1977
   parameter clear_value = 0;
1978
   parameter set_value = 1;
1979
   parameter wrap_value = 8;
1980
   parameter level1_value = 15;
1981
 
1982
   reg  [length:1] qi;
1983
   reg lfsr_fb;
1984
   wire [length:1] q_next;
1985
   reg [32:1] polynom;
1986
   integer i;
1987
 
1988
   always @ (qi)
1989
   begin
1990
        case (length)
1991
         2: polynom = 32'b11;                               // 0x3
1992
         3: polynom = 32'b110;                              // 0x6
1993
         4: polynom = 32'b1100;                             // 0xC
1994
         5: polynom = 32'b10100;                            // 0x14
1995
         6: polynom = 32'b110000;                           // 0x30
1996
         7: polynom = 32'b1100000;                          // 0x60
1997
         8: polynom = 32'b10111000;                         // 0xb8
1998
         9: polynom = 32'b100010000;                        // 0x110
1999
        10: polynom = 32'b1001000000;                       // 0x240
2000
        11: polynom = 32'b10100000000;                      // 0x500
2001
        12: polynom = 32'b100000101001;                     // 0x829
2002
        13: polynom = 32'b1000000001100;                    // 0x100C
2003
        14: polynom = 32'b10000000010101;                   // 0x2015
2004
        15: polynom = 32'b110000000000000;                  // 0x6000
2005
        16: polynom = 32'b1101000000001000;                 // 0xD008
2006
        17: polynom = 32'b10010000000000000;                // 0x12000
2007
        18: polynom = 32'b100000010000000000;               // 0x20400
2008
        19: polynom = 32'b1000000000000100011;              // 0x40023
2009
        20: polynom = 32'b10000010000000000000;             // 0x82000
2010
        21: polynom = 32'b101000000000000000000;            // 0x140000
2011
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2012
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2013
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2014
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2015
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2016
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2017
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2018
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2019
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2020
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2021
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2022
        default: polynom = 32'b0;
2023
        endcase
2024
        lfsr_fb = qi[length];
2025
        for (i=length-1; i>=1; i=i-1) begin
2026
            if (polynom[i])
2027
                lfsr_fb = lfsr_fb  ~^ qi[i];
2028
        end
2029
    end
2030
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2031
 
2032
   always @ (posedge clk or posedge rst)
2033
     if (rst)
2034
       qi <= {length{1'b0}};
2035
     else
2036
     if (cke)
2037
       qi <= q_next;
2038
 
2039
   assign q = qi;
2040
 
2041
endmodule
2042
//////////////////////////////////////////////////////////////////////
2043
////                                                              ////
2044
////  Versatile counter                                           ////
2045
////                                                              ////
2046
////  Description                                                 ////
2047
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2048
////  counter                                                     ////
2049
////                                                              ////
2050
////  To Do:                                                      ////
2051
////   - add LFSR with more taps                                  ////
2052
////                                                              ////
2053
////  Author(s):                                                  ////
2054
////      - Michael Unneback, unneback@opencores.org              ////
2055
////        ORSoC AB                                              ////
2056
////                                                              ////
2057
//////////////////////////////////////////////////////////////////////
2058
////                                                              ////
2059
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2060
////                                                              ////
2061
//// This source file may be used and distributed without         ////
2062
//// restriction provided that this copyright statement is not    ////
2063
//// removed from the file and that any derivative work contains  ////
2064
//// the original copyright notice and the associated disclaimer. ////
2065
////                                                              ////
2066
//// This source file is free software; you can redistribute it   ////
2067
//// and/or modify it under the terms of the GNU Lesser General   ////
2068
//// Public License as published by the Free Software Foundation; ////
2069
//// either version 2.1 of the License, or (at your option) any   ////
2070
//// later version.                                               ////
2071
////                                                              ////
2072
//// This source is distributed in the hope that it will be       ////
2073
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2074
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2075
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2076
//// details.                                                     ////
2077
////                                                              ////
2078
//// You should have received a copy of the GNU Lesser General    ////
2079
//// Public License along with this source; if not, download it   ////
2080
//// from http://www.opencores.org/lgpl.shtml                     ////
2081
////                                                              ////
2082
//////////////////////////////////////////////////////////////////////
2083
 
2084
// LFSR counter
2085
module vl_cnt_lfsr_ce_clear_q ( clear, cke, q, rst, clk);
2086
 
2087
   parameter length = 4;
2088
   input clear;
2089
   input cke;
2090
   output [length:1] q;
2091
   input rst;
2092
   input clk;
2093
 
2094
   parameter clear_value = 0;
2095
   parameter set_value = 1;
2096
   parameter wrap_value = 8;
2097
   parameter level1_value = 15;
2098
 
2099
   reg  [length:1] qi;
2100
   reg lfsr_fb;
2101
   wire [length:1] q_next;
2102
   reg [32:1] polynom;
2103
   integer i;
2104
 
2105
   always @ (qi)
2106
   begin
2107
        case (length)
2108
         2: polynom = 32'b11;                               // 0x3
2109
         3: polynom = 32'b110;                              // 0x6
2110
         4: polynom = 32'b1100;                             // 0xC
2111
         5: polynom = 32'b10100;                            // 0x14
2112
         6: polynom = 32'b110000;                           // 0x30
2113
         7: polynom = 32'b1100000;                          // 0x60
2114
         8: polynom = 32'b10111000;                         // 0xb8
2115
         9: polynom = 32'b100010000;                        // 0x110
2116
        10: polynom = 32'b1001000000;                       // 0x240
2117
        11: polynom = 32'b10100000000;                      // 0x500
2118
        12: polynom = 32'b100000101001;                     // 0x829
2119
        13: polynom = 32'b1000000001100;                    // 0x100C
2120
        14: polynom = 32'b10000000010101;                   // 0x2015
2121
        15: polynom = 32'b110000000000000;                  // 0x6000
2122
        16: polynom = 32'b1101000000001000;                 // 0xD008
2123
        17: polynom = 32'b10010000000000000;                // 0x12000
2124
        18: polynom = 32'b100000010000000000;               // 0x20400
2125
        19: polynom = 32'b1000000000000100011;              // 0x40023
2126
        20: polynom = 32'b10000010000000000000;             // 0x82000
2127
        21: polynom = 32'b101000000000000000000;            // 0x140000
2128
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2129
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2130
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2131
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2132
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2133
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2134
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2135
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2136
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2137
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2138
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2139
        default: polynom = 32'b0;
2140
        endcase
2141
        lfsr_fb = qi[length];
2142
        for (i=length-1; i>=1; i=i-1) begin
2143
            if (polynom[i])
2144
                lfsr_fb = lfsr_fb  ~^ qi[i];
2145
        end
2146
    end
2147
   assign q_next =  clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2148
 
2149
   always @ (posedge clk or posedge rst)
2150
     if (rst)
2151
       qi <= {length{1'b0}};
2152
     else
2153
     if (cke)
2154
       qi <= q_next;
2155
 
2156
   assign q = qi;
2157
 
2158
endmodule
2159
//////////////////////////////////////////////////////////////////////
2160
////                                                              ////
2161
////  Versatile counter                                           ////
2162
////                                                              ////
2163
////  Description                                                 ////
2164
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2165
////  counter                                                     ////
2166
////                                                              ////
2167
////  To Do:                                                      ////
2168
////   - add LFSR with more taps                                  ////
2169
////                                                              ////
2170
////  Author(s):                                                  ////
2171
////      - Michael Unneback, unneback@opencores.org              ////
2172
////        ORSoC AB                                              ////
2173
////                                                              ////
2174
//////////////////////////////////////////////////////////////////////
2175
////                                                              ////
2176
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2177
////                                                              ////
2178
//// This source file may be used and distributed without         ////
2179
//// restriction provided that this copyright statement is not    ////
2180
//// removed from the file and that any derivative work contains  ////
2181
//// the original copyright notice and the associated disclaimer. ////
2182
////                                                              ////
2183
//// This source file is free software; you can redistribute it   ////
2184
//// and/or modify it under the terms of the GNU Lesser General   ////
2185
//// Public License as published by the Free Software Foundation; ////
2186
//// either version 2.1 of the License, or (at your option) any   ////
2187
//// later version.                                               ////
2188
////                                                              ////
2189
//// This source is distributed in the hope that it will be       ////
2190
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2191
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2192
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2193
//// details.                                                     ////
2194
////                                                              ////
2195
//// You should have received a copy of the GNU Lesser General    ////
2196
//// Public License along with this source; if not, download it   ////
2197
//// from http://www.opencores.org/lgpl.shtml                     ////
2198
////                                                              ////
2199
//////////////////////////////////////////////////////////////////////
2200
 
2201
// LFSR counter
2202 22 unneback
module vl_cnt_lfsr_ce_q_zq ( cke, q, zq, rst, clk);
2203
 
2204
   parameter length = 4;
2205
   input cke;
2206
   output [length:1] q;
2207
   output reg zq;
2208
   input rst;
2209
   input clk;
2210
 
2211
   parameter clear_value = 0;
2212
   parameter set_value = 1;
2213
   parameter wrap_value = 8;
2214
   parameter level1_value = 15;
2215
 
2216
   reg  [length:1] qi;
2217
   reg lfsr_fb;
2218
   wire [length:1] q_next;
2219
   reg [32:1] polynom;
2220
   integer i;
2221
 
2222
   always @ (qi)
2223
   begin
2224
        case (length)
2225
         2: polynom = 32'b11;                               // 0x3
2226
         3: polynom = 32'b110;                              // 0x6
2227
         4: polynom = 32'b1100;                             // 0xC
2228
         5: polynom = 32'b10100;                            // 0x14
2229
         6: polynom = 32'b110000;                           // 0x30
2230
         7: polynom = 32'b1100000;                          // 0x60
2231
         8: polynom = 32'b10111000;                         // 0xb8
2232
         9: polynom = 32'b100010000;                        // 0x110
2233
        10: polynom = 32'b1001000000;                       // 0x240
2234
        11: polynom = 32'b10100000000;                      // 0x500
2235
        12: polynom = 32'b100000101001;                     // 0x829
2236
        13: polynom = 32'b1000000001100;                    // 0x100C
2237
        14: polynom = 32'b10000000010101;                   // 0x2015
2238
        15: polynom = 32'b110000000000000;                  // 0x6000
2239
        16: polynom = 32'b1101000000001000;                 // 0xD008
2240
        17: polynom = 32'b10010000000000000;                // 0x12000
2241
        18: polynom = 32'b100000010000000000;               // 0x20400
2242
        19: polynom = 32'b1000000000000100011;              // 0x40023
2243
        20: polynom = 32'b10000010000000000000;             // 0x82000
2244
        21: polynom = 32'b101000000000000000000;            // 0x140000
2245
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2246
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2247
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2248
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2249
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2250
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2251
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2252
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2253
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2254
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2255
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2256
        default: polynom = 32'b0;
2257
        endcase
2258
        lfsr_fb = qi[length];
2259
        for (i=length-1; i>=1; i=i-1) begin
2260
            if (polynom[i])
2261
                lfsr_fb = lfsr_fb  ~^ qi[i];
2262
        end
2263
    end
2264
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2265
 
2266
   always @ (posedge clk or posedge rst)
2267
     if (rst)
2268
       qi <= {length{1'b0}};
2269
     else
2270
     if (cke)
2271
       qi <= q_next;
2272
 
2273
   assign q = qi;
2274
 
2275
 
2276
   always @ (posedge clk or posedge rst)
2277
     if (rst)
2278
       zq <= 1'b1;
2279
     else
2280
     if (cke)
2281
       zq <= q_next == {length{1'b0}};
2282
endmodule
2283
//////////////////////////////////////////////////////////////////////
2284
////                                                              ////
2285
////  Versatile counter                                           ////
2286
////                                                              ////
2287
////  Description                                                 ////
2288
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2289
////  counter                                                     ////
2290
////                                                              ////
2291
////  To Do:                                                      ////
2292
////   - add LFSR with more taps                                  ////
2293
////                                                              ////
2294
////  Author(s):                                                  ////
2295
////      - Michael Unneback, unneback@opencores.org              ////
2296
////        ORSoC AB                                              ////
2297
////                                                              ////
2298
//////////////////////////////////////////////////////////////////////
2299
////                                                              ////
2300
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2301
////                                                              ////
2302
//// This source file may be used and distributed without         ////
2303
//// restriction provided that this copyright statement is not    ////
2304
//// removed from the file and that any derivative work contains  ////
2305
//// the original copyright notice and the associated disclaimer. ////
2306
////                                                              ////
2307
//// This source file is free software; you can redistribute it   ////
2308
//// and/or modify it under the terms of the GNU Lesser General   ////
2309
//// Public License as published by the Free Software Foundation; ////
2310
//// either version 2.1 of the License, or (at your option) any   ////
2311
//// later version.                                               ////
2312
////                                                              ////
2313
//// This source is distributed in the hope that it will be       ////
2314
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2315
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2316
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2317
//// details.                                                     ////
2318
////                                                              ////
2319
//// You should have received a copy of the GNU Lesser General    ////
2320
//// Public License along with this source; if not, download it   ////
2321
//// from http://www.opencores.org/lgpl.shtml                     ////
2322
////                                                              ////
2323
//////////////////////////////////////////////////////////////////////
2324 6 unneback
 
2325
// LFSR counter
2326 18 unneback
module vl_cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk);
2327 6 unneback
 
2328
   parameter length = 4;
2329
   input cke;
2330
   input rew;
2331
   output reg level1;
2332
   input rst;
2333
   input clk;
2334
 
2335
   parameter clear_value = 0;
2336
   parameter set_value = 1;
2337
   parameter wrap_value = 8;
2338
   parameter level1_value = 15;
2339
 
2340 29 unneback
   wire clear;
2341 30 unneback
   assign clear = 1'b0;
2342 6 unneback
   reg  [length:1] qi;
2343
   reg lfsr_fb, lfsr_fb_rew;
2344
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2345
   reg [32:1] polynom_rew;
2346
   integer j;
2347
   reg [32:1] polynom;
2348
   integer i;
2349
 
2350
   always @ (qi)
2351
   begin
2352
        case (length)
2353
         2: polynom = 32'b11;                               // 0x3
2354
         3: polynom = 32'b110;                              // 0x6
2355
         4: polynom = 32'b1100;                             // 0xC
2356
         5: polynom = 32'b10100;                            // 0x14
2357
         6: polynom = 32'b110000;                           // 0x30
2358
         7: polynom = 32'b1100000;                          // 0x60
2359
         8: polynom = 32'b10111000;                         // 0xb8
2360
         9: polynom = 32'b100010000;                        // 0x110
2361
        10: polynom = 32'b1001000000;                       // 0x240
2362
        11: polynom = 32'b10100000000;                      // 0x500
2363
        12: polynom = 32'b100000101001;                     // 0x829
2364
        13: polynom = 32'b1000000001100;                    // 0x100C
2365
        14: polynom = 32'b10000000010101;                   // 0x2015
2366
        15: polynom = 32'b110000000000000;                  // 0x6000
2367
        16: polynom = 32'b1101000000001000;                 // 0xD008
2368
        17: polynom = 32'b10010000000000000;                // 0x12000
2369
        18: polynom = 32'b100000010000000000;               // 0x20400
2370
        19: polynom = 32'b1000000000000100011;              // 0x40023
2371
        20: polynom = 32'b10000010000000000000;             // 0x82000
2372
        21: polynom = 32'b101000000000000000000;            // 0x140000
2373
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2374
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2375
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2376
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2377
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2378
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2379
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2380
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2381
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2382
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2383
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2384
        default: polynom = 32'b0;
2385
        endcase
2386
        lfsr_fb = qi[length];
2387
        for (i=length-1; i>=1; i=i-1) begin
2388
            if (polynom[i])
2389
                lfsr_fb = lfsr_fb  ~^ qi[i];
2390
        end
2391
    end
2392
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2393
   always @ (qi)
2394
   begin
2395
        case (length)
2396
         2: polynom_rew = 32'b11;
2397
         3: polynom_rew = 32'b110;
2398
         4: polynom_rew = 32'b1100;
2399
         5: polynom_rew = 32'b10100;
2400
         6: polynom_rew = 32'b110000;
2401
         7: polynom_rew = 32'b1100000;
2402
         8: polynom_rew = 32'b10111000;
2403
         9: polynom_rew = 32'b100010000;
2404
        10: polynom_rew = 32'b1001000000;
2405
        11: polynom_rew = 32'b10100000000;
2406
        12: polynom_rew = 32'b100000101001;
2407
        13: polynom_rew = 32'b1000000001100;
2408
        14: polynom_rew = 32'b10000000010101;
2409
        15: polynom_rew = 32'b110000000000000;
2410
        16: polynom_rew = 32'b1101000000001000;
2411
        17: polynom_rew = 32'b10010000000000000;
2412
        18: polynom_rew = 32'b100000010000000000;
2413
        19: polynom_rew = 32'b1000000000000100011;
2414
        20: polynom_rew = 32'b10000010000000000000;
2415
        21: polynom_rew = 32'b101000000000000000000;
2416
        22: polynom_rew = 32'b1100000000000000000000;
2417
        23: polynom_rew = 32'b10000100000000000000000;
2418
        24: polynom_rew = 32'b111000010000000000000000;
2419
        25: polynom_rew = 32'b1001000000000000000000000;
2420
        26: polynom_rew = 32'b10000000000000000000100011;
2421
        27: polynom_rew = 32'b100000000000000000000010011;
2422
        28: polynom_rew = 32'b1100100000000000000000000000;
2423
        29: polynom_rew = 32'b10100000000000000000000000000;
2424
        30: polynom_rew = 32'b100000000000000000000000101001;
2425
        31: polynom_rew = 32'b1001000000000000000000000000000;
2426
        32: polynom_rew = 32'b10000000001000000000000000000011;
2427
        default: polynom_rew = 32'b0;
2428
        endcase
2429
        // rotate left
2430
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
2431
        lfsr_fb_rew = qi[length];
2432
        for (i=length-1; i>=1; i=i-1) begin
2433
            if (polynom_rew[i])
2434
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
2435
        end
2436
    end
2437
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
2438
   assign q_next = rew ? q_next_rew : q_next_fw;
2439
 
2440
   always @ (posedge clk or posedge rst)
2441
     if (rst)
2442
       qi <= {length{1'b0}};
2443
     else
2444
     if (cke)
2445
       qi <= q_next;
2446
 
2447
 
2448
 
2449
    always @ (posedge clk or posedge rst)
2450
    if (rst)
2451
        level1 <= 1'b0;
2452
    else
2453
    if (cke)
2454 29 unneback
    if (clear)
2455
        level1 <= 1'b0;
2456
    else if (q_next == level1_value)
2457 6 unneback
        level1 <= 1'b1;
2458
    else if (qi == level1_value & rew)
2459
        level1 <= 1'b0;
2460
endmodule
2461
//////////////////////////////////////////////////////////////////////
2462
////                                                              ////
2463
////  Versatile counter                                           ////
2464
////                                                              ////
2465
////  Description                                                 ////
2466
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2467
////  counter                                                     ////
2468
////                                                              ////
2469
////  To Do:                                                      ////
2470
////   - add LFSR with more taps                                  ////
2471
////                                                              ////
2472
////  Author(s):                                                  ////
2473
////      - Michael Unneback, unneback@opencores.org              ////
2474
////        ORSoC AB                                              ////
2475
////                                                              ////
2476
//////////////////////////////////////////////////////////////////////
2477
////                                                              ////
2478
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2479
////                                                              ////
2480
//// This source file may be used and distributed without         ////
2481
//// restriction provided that this copyright statement is not    ////
2482
//// removed from the file and that any derivative work contains  ////
2483
//// the original copyright notice and the associated disclaimer. ////
2484
////                                                              ////
2485
//// This source file is free software; you can redistribute it   ////
2486
//// and/or modify it under the terms of the GNU Lesser General   ////
2487
//// Public License as published by the Free Software Foundation; ////
2488
//// either version 2.1 of the License, or (at your option) any   ////
2489
//// later version.                                               ////
2490
////                                                              ////
2491
//// This source is distributed in the hope that it will be       ////
2492
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2493
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2494
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2495
//// details.                                                     ////
2496
////                                                              ////
2497
//// You should have received a copy of the GNU Lesser General    ////
2498
//// Public License along with this source; if not, download it   ////
2499
//// from http://www.opencores.org/lgpl.shtml                     ////
2500
////                                                              ////
2501
//////////////////////////////////////////////////////////////////////
2502
 
2503
// GRAY counter
2504 18 unneback
module vl_cnt_gray ( q, rst, clk);
2505 6 unneback
 
2506
   parameter length = 4;
2507
   output reg [length:1] q;
2508
   input rst;
2509
   input clk;
2510
 
2511
   parameter clear_value = 0;
2512
   parameter set_value = 1;
2513
   parameter wrap_value = 8;
2514
   parameter level1_value = 15;
2515
 
2516
   reg  [length:1] qi;
2517
   wire [length:1] q_next;
2518
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2519
 
2520
   always @ (posedge clk or posedge rst)
2521
     if (rst)
2522
       qi <= {length{1'b0}};
2523
     else
2524
       qi <= q_next;
2525
 
2526
   always @ (posedge clk or posedge rst)
2527
     if (rst)
2528
       q <= {length{1'b0}};
2529
     else
2530
         q <= (q_next>>1) ^ q_next;
2531
 
2532
endmodule
2533
//////////////////////////////////////////////////////////////////////
2534
////                                                              ////
2535
////  Versatile counter                                           ////
2536
////                                                              ////
2537
////  Description                                                 ////
2538
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2539
////  counter                                                     ////
2540
////                                                              ////
2541
////  To Do:                                                      ////
2542
////   - add LFSR with more taps                                  ////
2543
////                                                              ////
2544
////  Author(s):                                                  ////
2545
////      - Michael Unneback, unneback@opencores.org              ////
2546
////        ORSoC AB                                              ////
2547
////                                                              ////
2548
//////////////////////////////////////////////////////////////////////
2549
////                                                              ////
2550
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2551
////                                                              ////
2552
//// This source file may be used and distributed without         ////
2553
//// restriction provided that this copyright statement is not    ////
2554
//// removed from the file and that any derivative work contains  ////
2555
//// the original copyright notice and the associated disclaimer. ////
2556
////                                                              ////
2557
//// This source file is free software; you can redistribute it   ////
2558
//// and/or modify it under the terms of the GNU Lesser General   ////
2559
//// Public License as published by the Free Software Foundation; ////
2560
//// either version 2.1 of the License, or (at your option) any   ////
2561
//// later version.                                               ////
2562
////                                                              ////
2563
//// This source is distributed in the hope that it will be       ////
2564
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2565
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2566
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2567
//// details.                                                     ////
2568
////                                                              ////
2569
//// You should have received a copy of the GNU Lesser General    ////
2570
//// Public License along with this source; if not, download it   ////
2571
//// from http://www.opencores.org/lgpl.shtml                     ////
2572
////                                                              ////
2573
//////////////////////////////////////////////////////////////////////
2574
 
2575
// GRAY counter
2576 18 unneback
module vl_cnt_gray_ce ( cke, q, rst, clk);
2577 6 unneback
 
2578
   parameter length = 4;
2579
   input cke;
2580
   output reg [length:1] q;
2581
   input rst;
2582
   input clk;
2583
 
2584
   parameter clear_value = 0;
2585
   parameter set_value = 1;
2586
   parameter wrap_value = 8;
2587
   parameter level1_value = 15;
2588
 
2589
   reg  [length:1] qi;
2590
   wire [length:1] q_next;
2591
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2592
 
2593
   always @ (posedge clk or posedge rst)
2594
     if (rst)
2595
       qi <= {length{1'b0}};
2596
     else
2597
     if (cke)
2598
       qi <= q_next;
2599
 
2600
   always @ (posedge clk or posedge rst)
2601
     if (rst)
2602
       q <= {length{1'b0}};
2603
     else
2604
       if (cke)
2605
         q <= (q_next>>1) ^ q_next;
2606
 
2607
endmodule
2608
//////////////////////////////////////////////////////////////////////
2609
////                                                              ////
2610
////  Versatile counter                                           ////
2611
////                                                              ////
2612
////  Description                                                 ////
2613
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2614
////  counter                                                     ////
2615
////                                                              ////
2616
////  To Do:                                                      ////
2617
////   - add LFSR with more taps                                  ////
2618
////                                                              ////
2619
////  Author(s):                                                  ////
2620
////      - Michael Unneback, unneback@opencores.org              ////
2621
////        ORSoC AB                                              ////
2622
////                                                              ////
2623
//////////////////////////////////////////////////////////////////////
2624
////                                                              ////
2625
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2626
////                                                              ////
2627
//// This source file may be used and distributed without         ////
2628
//// restriction provided that this copyright statement is not    ////
2629
//// removed from the file and that any derivative work contains  ////
2630
//// the original copyright notice and the associated disclaimer. ////
2631
////                                                              ////
2632
//// This source file is free software; you can redistribute it   ////
2633
//// and/or modify it under the terms of the GNU Lesser General   ////
2634
//// Public License as published by the Free Software Foundation; ////
2635
//// either version 2.1 of the License, or (at your option) any   ////
2636
//// later version.                                               ////
2637
////                                                              ////
2638
//// This source is distributed in the hope that it will be       ////
2639
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2640
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2641
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2642
//// details.                                                     ////
2643
////                                                              ////
2644
//// You should have received a copy of the GNU Lesser General    ////
2645
//// Public License along with this source; if not, download it   ////
2646
//// from http://www.opencores.org/lgpl.shtml                     ////
2647
////                                                              ////
2648
//////////////////////////////////////////////////////////////////////
2649
 
2650
// GRAY counter
2651 18 unneback
module vl_cnt_gray_ce_bin ( cke, q, q_bin, rst, clk);
2652 6 unneback
 
2653
   parameter length = 4;
2654
   input cke;
2655
   output reg [length:1] q;
2656
   output [length:1] q_bin;
2657
   input rst;
2658
   input clk;
2659
 
2660
   parameter clear_value = 0;
2661
   parameter set_value = 1;
2662
   parameter wrap_value = 8;
2663
   parameter level1_value = 15;
2664
 
2665
   reg  [length:1] qi;
2666
   wire [length:1] q_next;
2667
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2668
 
2669
   always @ (posedge clk or posedge rst)
2670
     if (rst)
2671
       qi <= {length{1'b0}};
2672
     else
2673
     if (cke)
2674
       qi <= q_next;
2675
 
2676
   always @ (posedge clk or posedge rst)
2677
     if (rst)
2678
       q <= {length{1'b0}};
2679
     else
2680
       if (cke)
2681
         q <= (q_next>>1) ^ q_next;
2682
 
2683
   assign q_bin = qi;
2684
 
2685
endmodule
2686
//////////////////////////////////////////////////////////////////////
2687
////                                                              ////
2688
////  Versatile library, counters                                 ////
2689
////                                                              ////
2690
////  Description                                                 ////
2691
////  counters                                                    ////
2692
////                                                              ////
2693
////                                                              ////
2694
////  To Do:                                                      ////
2695
////   - add more counters                                        ////
2696
////                                                              ////
2697
////  Author(s):                                                  ////
2698
////      - Michael Unneback, unneback@opencores.org              ////
2699
////        ORSoC AB                                              ////
2700
////                                                              ////
2701
//////////////////////////////////////////////////////////////////////
2702
////                                                              ////
2703
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2704
////                                                              ////
2705
//// This source file may be used and distributed without         ////
2706
//// restriction provided that this copyright statement is not    ////
2707
//// removed from the file and that any derivative work contains  ////
2708
//// the original copyright notice and the associated disclaimer. ////
2709
////                                                              ////
2710
//// This source file is free software; you can redistribute it   ////
2711
//// and/or modify it under the terms of the GNU Lesser General   ////
2712
//// Public License as published by the Free Software Foundation; ////
2713
//// either version 2.1 of the License, or (at your option) any   ////
2714
//// later version.                                               ////
2715
////                                                              ////
2716
//// This source is distributed in the hope that it will be       ////
2717
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2718
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2719
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2720
//// details.                                                     ////
2721
////                                                              ////
2722
//// You should have received a copy of the GNU Lesser General    ////
2723
//// Public License along with this source; if not, download it   ////
2724
//// from http://www.opencores.org/lgpl.shtml                     ////
2725
////                                                              ////
2726
//////////////////////////////////////////////////////////////////////
2727
 
2728 18 unneback
module vl_cnt_shreg_wrap ( q, rst, clk);
2729 6 unneback
 
2730
   parameter length = 4;
2731
   output reg [0:length-1] q;
2732
   input rst;
2733
   input clk;
2734
 
2735
    always @ (posedge clk or posedge rst)
2736
    if (rst)
2737
        q <= {1'b1,{length-1{1'b0}}};
2738
    else
2739
        q <= {q[length-1],q[0:length-2]};
2740
 
2741
endmodule
2742
 
2743 18 unneback
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk