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1 6 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  Versatile library, clock and reset                          ////
4
////                                                              ////
5
////  Description                                                 ////
6
////  Logic related to clock and reset                            ////
7
////                                                              ////
8
////                                                              ////
9
////  To Do:                                                      ////
10
////   - add more different registers                             ////
11
////                                                              ////
12
////  Author(s):                                                  ////
13
////      - Michael Unneback, unneback@opencores.org              ////
14
////        ORSoC AB                                              ////
15
////                                                              ////
16
//////////////////////////////////////////////////////////////////////
17
////                                                              ////
18
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
19
////                                                              ////
20
//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
36
////                                                              ////
37
//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
 
43
// Global buffer
44
// usage:
45
// use to enable global buffers for high fan out signals such as clock and reset
46
 
47
`ifdef ACTEL
48
 
49
`timescale 1 ns/100 ps
50
// Version: 8.4 8.4.0.33
51
module gbuf(GL,CLK);
52
output GL;
53
input  CLK;
54
 
55
    wire GND;
56
 
57
    GND GND_1_net(.Y(GND));
58
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
59
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
60
 
61
endmodule
62
`timescale 1 ns/1 ns
63
module vl_gbuf ( i, o);
64
input i;
65
output o;
66
`ifdef SIM_GBUF
67
assign o=i;
68
`else
69
gbuf gbuf_i0 ( .CLK(i), .GL(o));
70
`endif
71
endmodule
72 33 unneback
 
73 6 unneback
`else
74 33 unneback
 
75 6 unneback
`ifdef ALTERA
76 21 unneback
//altera
77 33 unneback
module vl_gbuf ( i, o);
78
input i;
79
output o;
80
assign o = i;
81
endmodule
82
 
83 6 unneback
`else
84
 
85
`timescale 1 ns/100 ps
86
module vl_gbuf ( i, o);
87
input i;
88
output o;
89
assign o = i;
90
endmodule
91
`endif // ALTERA
92
`endif //ACTEL
93
 
94
// sync reset
95 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
96 6 unneback
// output active high global reset sync with two DFFs 
97
`timescale 1 ns/100 ps
98
module vl_sync_rst ( rst_n_i, rst_o, clk);
99
input rst_n_i, clk;
100
output rst_o;
101 18 unneback
reg [1:0] tmp;
102 6 unneback
always @ (posedge clk or negedge rst_n_i)
103
if (!rst_n_i)
104 17 unneback
        tmp <= 2'b11;
105 6 unneback
else
106 33 unneback
        tmp <= {1'b0,tmp[1]};
107 17 unneback
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
108 6 unneback
endmodule
109
 
110
// vl_pll
111
`ifdef ACTEL
112 32 unneback
///////////////////////////////////////////////////////////////////////////////
113 17 unneback
`timescale 1 ps/1 ps
114 6 unneback
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
115
parameter index = 0;
116
parameter number_of_clk = 1;
117 17 unneback
parameter period_time_0 = 20000;
118
parameter period_time_1 = 20000;
119
parameter period_time_2 = 20000;
120
parameter lock_delay = 2000000;
121 6 unneback
input clk_i, rst_n_i;
122
output lock;
123
output reg [0:number_of_clk-1] clk_o;
124
output [0:number_of_clk-1] rst_o;
125
 
126
`ifdef SIM_PLL
127
 
128
always
129
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
130
 
131
generate if (number_of_clk > 1)
132
always
133
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
134
endgenerate
135
 
136
generate if (number_of_clk > 2)
137
always
138
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
139
endgenerate
140
 
141
genvar i;
142
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
143
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
144
end
145
endgenerate
146
 
147
assign #lock_delay lock = rst_n_i;
148
 
149
endmodule
150
`else
151
generate if (number_of_clk==1 & index==0) begin
152
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
153
end
154
endgenerate // index==0
155
generate if (number_of_clk==1 & index==1) begin
156
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
157
end
158
endgenerate // index==1
159
generate if (number_of_clk==1 & index==2) begin
160
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
161
end
162
endgenerate // index==2
163
generate if (number_of_clk==1 & index==3) begin
164
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
165
end
166
endgenerate // index==0
167
 
168
generate if (number_of_clk==2 & index==0) begin
169
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
170
end
171
endgenerate // index==0
172
generate if (number_of_clk==2 & index==1) begin
173
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
174
end
175
endgenerate // index==1
176
generate if (number_of_clk==2 & index==2) begin
177
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
178
end
179
endgenerate // index==2
180
generate if (number_of_clk==2 & index==3) begin
181
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
182
end
183
endgenerate // index==0
184
 
185
generate if (number_of_clk==3 & index==0) begin
186
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
187
end
188
endgenerate // index==0
189
generate if (number_of_clk==3 & index==1) begin
190
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
191
end
192
endgenerate // index==1
193
generate if (number_of_clk==3 & index==2) begin
194
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
195
end
196
endgenerate // index==2
197
generate if (number_of_clk==3 & index==3) begin
198
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
199
end
200
endgenerate // index==0
201
 
202
genvar i;
203
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
204
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
205
end
206
endgenerate
207
endmodule
208
`endif
209 32 unneback
///////////////////////////////////////////////////////////////////////////////
210 6 unneback
 
211
`else
212
 
213 32 unneback
///////////////////////////////////////////////////////////////////////////////
214 6 unneback
`ifdef ALTERA
215
 
216 32 unneback
`timescale 1 ps/1 ps
217
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
218
parameter index = 0;
219
parameter number_of_clk = 1;
220
parameter period_time_0 = 20000;
221
parameter period_time_1 = 20000;
222
parameter period_time_2 = 20000;
223
parameter period_time_3 = 20000;
224
parameter period_time_4 = 20000;
225
parameter lock_delay = 2000000;
226
input clk_i, rst_n_i;
227
output lock;
228
output reg [0:number_of_clk-1] clk_o;
229
output [0:number_of_clk-1] rst_o;
230
 
231
`ifdef SIM_PLL
232
 
233
always
234
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
235
 
236
generate if (number_of_clk > 1)
237
always
238
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
239
endgenerate
240
 
241
generate if (number_of_clk > 2)
242
always
243
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
244
endgenerate
245
 
246 33 unneback
generate if (number_of_clk > 3)
247 32 unneback
always
248
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
249
endgenerate
250
 
251 33 unneback
generate if (number_of_clk > 4)
252 32 unneback
always
253
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
254
endgenerate
255
 
256
genvar i;
257
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
258
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
259
end
260
endgenerate
261
 
262 33 unneback
//assign #lock_delay lock = rst_n_i;
263
assign lock = rst_n_i;
264 32 unneback
 
265
endmodule
266 6 unneback
`else
267
 
268 33 unneback
`ifdef VL_PLL0
269
`ifdef VL_PLL0_CLK1
270
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
271
`endif
272
`ifdef VL_PLL0_CLK2
273
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
274
`endif
275
`ifdef VL_PLL0_CLK3
276
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
277
`endif
278
`ifdef VL_PLL0_CLK4
279
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
280
`endif
281
`ifdef VL_PLL0_CLK5
282
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
283
`endif
284
`endif
285 32 unneback
 
286 33 unneback
`ifdef VL_PLL1
287
`ifdef VL_PLL1_CLK1
288
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
289
`endif
290
`ifdef VL_PLL1_CLK2
291
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
292
`endif
293
`ifdef VL_PLL1_CLK3
294
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
295
`endif
296
`ifdef VL_PLL1_CLK4
297
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
298
`endif
299
`ifdef VL_PLL1_CLK5
300
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
301
`endif
302
`endif
303 32 unneback
 
304 33 unneback
`ifdef VL_PLL2
305
`ifdef VL_PLL2_CLK1
306
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
307
`endif
308
`ifdef VL_PLL2_CLK2
309
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
310
`endif
311
`ifdef VL_PLL2_CLK3
312
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
313
`endif
314
`ifdef VL_PLL2_CLK4
315
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
316
`endif
317
`ifdef VL_PLL2_CLK5
318
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
319
`endif
320
`endif
321 32 unneback
 
322 33 unneback
`ifdef VL_PLL3
323
`ifdef VL_PLL3_CLK1
324
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
325
`endif
326
`ifdef VL_PLL3_CLK2
327
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
328
`endif
329
`ifdef VL_PLL3_CLK3
330
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
331
`endif
332
`ifdef VL_PLL3_CLK4
333
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
334
`endif
335
`ifdef VL_PLL3_CLK5
336
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
337
`endif
338
`endif
339 32 unneback
 
340
genvar i;
341
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
342 33 unneback
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
343 32 unneback
end
344
endgenerate
345
endmodule
346
`endif
347
///////////////////////////////////////////////////////////////////////////////
348
 
349
`else
350
 
351 6 unneback
// generic PLL
352 17 unneback
`timescale 1 ps/1 ps
353 6 unneback
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
354
parameter index = 0;
355
parameter number_of_clk = 1;
356 17 unneback
parameter period_time_0 = 20000;
357
parameter period_time_1 = 20000;
358
parameter period_time_2 = 20000;
359 6 unneback
parameter lock_delay = 2000;
360
input clk_i, rst_n_i;
361
output lock;
362
output reg [0:number_of_clk-1] clk_o;
363
output [0:number_of_clk-1] rst_o;
364
 
365
always
366
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
367
 
368
generate if (number_of_clk > 1)
369
always
370
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
371
endgenerate
372
 
373
generate if (number_of_clk > 2)
374
always
375
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
376
endgenerate
377
 
378
genvar i;
379
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
380
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
381
end
382
endgenerate
383
 
384
assign #lock_delay lock = rst_n_i;
385
 
386
endmodule
387
 
388
`endif //altera
389 17 unneback
`endif //actel
390
//////////////////////////////////////////////////////////////////////
391 6 unneback
////                                                              ////
392
////  Versatile library, registers                                ////
393
////                                                              ////
394
////  Description                                                 ////
395
////  Different type of registers                                 ////
396
////                                                              ////
397
////                                                              ////
398
////  To Do:                                                      ////
399
////   - add more different registers                             ////
400
////                                                              ////
401
////  Author(s):                                                  ////
402
////      - Michael Unneback, unneback@opencores.org              ////
403
////        ORSoC AB                                              ////
404
////                                                              ////
405
//////////////////////////////////////////////////////////////////////
406
////                                                              ////
407
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
408
////                                                              ////
409
//// This source file may be used and distributed without         ////
410
//// restriction provided that this copyright statement is not    ////
411
//// removed from the file and that any derivative work contains  ////
412
//// the original copyright notice and the associated disclaimer. ////
413
////                                                              ////
414
//// This source file is free software; you can redistribute it   ////
415
//// and/or modify it under the terms of the GNU Lesser General   ////
416
//// Public License as published by the Free Software Foundation; ////
417
//// either version 2.1 of the License, or (at your option) any   ////
418
//// later version.                                               ////
419
////                                                              ////
420
//// This source is distributed in the hope that it will be       ////
421
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
422
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
423
//// PURPOSE.  See the GNU Lesser General Public License for more ////
424
//// details.                                                     ////
425
////                                                              ////
426
//// You should have received a copy of the GNU Lesser General    ////
427
//// Public License along with this source; if not, download it   ////
428
//// from http://www.opencores.org/lgpl.shtml                     ////
429
////                                                              ////
430
//////////////////////////////////////////////////////////////////////
431
 
432 18 unneback
module vl_dff ( d, q, clk, rst);
433 6 unneback
 
434
        parameter width = 1;
435
        parameter reset_value = 0;
436
 
437
        input [width-1:0] d;
438
        input clk, rst;
439
        output reg [width-1:0] q;
440
 
441
        always @ (posedge clk or posedge rst)
442
        if (rst)
443
                q <= reset_value;
444
        else
445
                q <= d;
446
 
447
endmodule
448
 
449 18 unneback
module vl_dff_array ( d, q, clk, rst);
450 6 unneback
 
451
        parameter width = 1;
452
        parameter depth = 2;
453
        parameter reset_value = 1'b0;
454
 
455
        input [width-1:0] d;
456
        input clk, rst;
457
        output [width-1:0] q;
458
        reg  [0:depth-1] q_tmp [width-1:0];
459
        integer i;
460
        always @ (posedge clk or posedge rst)
461
        if (rst) begin
462
            for (i=0;i<depth;i=i+1)
463
                q_tmp[i] <= {width{reset_value}};
464
        end else begin
465
            q_tmp[0] <= d;
466
            for (i=1;i<depth;i=i+1)
467
                q_tmp[i] <= q_tmp[i-1];
468
        end
469
 
470
    assign q = q_tmp[depth-1];
471
 
472
endmodule
473
 
474 18 unneback
module vl_dff_ce ( d, ce, q, clk, rst);
475 6 unneback
 
476
        parameter width = 1;
477
        parameter reset_value = 0;
478
 
479
        input [width-1:0] d;
480
        input ce, clk, rst;
481
        output reg [width-1:0] q;
482
 
483
        always @ (posedge clk or posedge rst)
484
        if (rst)
485
                q <= reset_value;
486
        else
487
                if (ce)
488
                        q <= d;
489
 
490
endmodule
491
 
492 18 unneback
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
493 8 unneback
 
494
        parameter width = 1;
495
        parameter reset_value = 0;
496
 
497
        input [width-1:0] d;
498 10 unneback
        input ce, clear, clk, rst;
499 8 unneback
        output reg [width-1:0] q;
500
 
501
        always @ (posedge clk or posedge rst)
502
        if (rst)
503
            q <= reset_value;
504
        else
505
            if (ce)
506
                if (clear)
507
                    q <= {width{1'b0}};
508
                else
509
                    q <= d;
510
 
511
endmodule
512
 
513 24 unneback
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
514
 
515
        parameter width = 1;
516
        parameter reset_value = 0;
517
 
518
        input [width-1:0] d;
519
        input ce, set, clk, rst;
520
        output reg [width-1:0] q;
521
 
522
        always @ (posedge clk or posedge rst)
523
        if (rst)
524
            q <= reset_value;
525
        else
526
            if (ce)
527
                if (set)
528
                    q <= {width{1'b1}};
529
                else
530
                    q <= d;
531
 
532
endmodule
533
 
534 29 unneback
module vl_spr ( sp, r, q, clk, rst);
535
 
536
        parameter width = 1;
537
        parameter reset_value = 0;
538
 
539
        input sp, r;
540
        output reg q;
541
        input clk, rst;
542
 
543
        always @ (posedge clk or posedge rst)
544
        if (rst)
545
            q <= reset_value;
546
        else
547
            if (sp)
548
                q <= 1'b1;
549
            else if (r)
550
                q <= 1'b0;
551
 
552
endmodule
553
 
554
module vl_srp ( s, rp, q, clk, rst);
555
 
556
        parameter width = 1;
557
        parameter reset_value = 0;
558
 
559
        input s, rp;
560
        output reg q;
561
        input clk, rst;
562
 
563
        always @ (posedge clk or posedge rst)
564
        if (rst)
565
            q <= reset_value;
566
        else
567
            if (rp)
568
                q <= 1'b0;
569
            else if (s)
570
                q <= 1'b1;
571
 
572
endmodule
573
 
574
 
575 6 unneback
`ifdef ALTERA
576
// megafunction wizard: %LPM_FF%
577
// GENERATION: STANDARD
578
// VERSION: WM1.0
579
// MODULE: lpm_ff 
580
 
581
// ============================================================
582
// File Name: dff_sr.v
583
// Megafunction Name(s):
584
//                      lpm_ff
585
//
586
// Simulation Library Files(s):
587
//                      lpm
588
// ============================================================
589
// ************************************************************
590
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
591
//
592
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
593
// ************************************************************
594
 
595
 
596
//Copyright (C) 1991-2010 Altera Corporation
597
//Your use of Altera Corporation's design tools, logic functions 
598
//and other software and tools, and its AMPP partner logic 
599
//functions, and any output files from any of the foregoing 
600
//(including device programming or simulation files), and any 
601
//associated documentation or information are expressly subject 
602
//to the terms and conditions of the Altera Program License 
603
//Subscription Agreement, Altera MegaCore Function License 
604
//Agreement, or other applicable license agreement, including, 
605
//without limitation, that your use is for the sole purpose of 
606
//programming logic devices manufactured by Altera and sold by 
607
//Altera or its authorized distributors.  Please refer to the 
608
//applicable agreement for further details.
609
 
610
 
611
// synopsys translate_off
612
`timescale 1 ps / 1 ps
613
// synopsys translate_on
614 18 unneback
module vl_dff_sr (
615 6 unneback
        aclr,
616
        aset,
617
        clock,
618
        data,
619
        q);
620
 
621
        input     aclr;
622
        input     aset;
623
        input     clock;
624
        input     data;
625
        output    q;
626
 
627
        wire [0:0] sub_wire0;
628
        wire [0:0] sub_wire1 = sub_wire0[0:0];
629
        wire  q = sub_wire1;
630
        wire  sub_wire2 = data;
631
        wire  sub_wire3 = sub_wire2;
632
 
633
        lpm_ff  lpm_ff_component (
634
                                .aclr (aclr),
635
                                .clock (clock),
636
                                .data (sub_wire3),
637
                                .aset (aset),
638
                                .q (sub_wire0)
639
                                // synopsys translate_off
640
                                ,
641
                                .aload (),
642
                                .enable (),
643
                                .sclr (),
644
                                .sload (),
645
                                .sset ()
646
                                // synopsys translate_on
647
                                );
648
        defparam
649
                lpm_ff_component.lpm_fftype = "DFF",
650
                lpm_ff_component.lpm_type = "LPM_FF",
651
                lpm_ff_component.lpm_width = 1;
652
 
653
 
654
endmodule
655
 
656
// ============================================================
657
// CNX file retrieval info
658
// ============================================================
659
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
660
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
661
// Retrieval info: PRIVATE: ASET NUMERIC "1"
662
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
663
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
664
// Retrieval info: PRIVATE: DFF NUMERIC "1"
665
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
666
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
667
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
668
// Retrieval info: PRIVATE: SSET NUMERIC "0"
669
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
670
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
671
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
672
// Retrieval info: PRIVATE: nBit NUMERIC "1"
673
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
674
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
675
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
676
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
677
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
678
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
679
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
680
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
681
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
682
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
683
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
684
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
685
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
686
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
687
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
688
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
689
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
690
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
691
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
692
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
693
// Retrieval info: LIB_FILE: lpm
694
 
695
 
696
`else
697
 
698
 
699 18 unneback
module vl_dff_sr ( aclr, aset, clock, data, q);
700 6 unneback
 
701
    input         aclr;
702
    input         aset;
703
    input         clock;
704
    input         data;
705
    output reg    q;
706
 
707
   always @ (posedge clock or posedge aclr or posedge aset)
708
     if (aclr)
709
       q <= 1'b0;
710
     else if (aset)
711
       q <= 1'b1;
712
     else
713
       q <= data;
714
 
715
endmodule
716
 
717
`endif
718
 
719
// LATCH
720
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
721
`ifdef ALTERA
722 18 unneback
module vl_latch ( d, le, q, clk);
723 6 unneback
input d, le;
724
output q;
725
input clk;
726
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
727
endmodule
728
`else
729
module latch ( d, le, q, clk);
730
input d, le;
731
output q;
732
input clk;/*
733
   always @ (posedge direction_set or posedge direction_clr)
734
     if (direction_clr)
735
       direction <= going_empty;
736
     else
737
       direction <= going_full;*/
738
endmodule
739 15 unneback
`endif
740
 
741 18 unneback
module vl_shreg ( d, q, clk, rst);
742 17 unneback
parameter depth = 10;
743
input d;
744
output q;
745
input clk, rst;
746
 
747
reg [1:depth] dffs;
748
 
749
always @ (posedge clk or posedge rst)
750
if (rst)
751
    dffs <= {depth{1'b0}};
752
else
753
    dffs <= {d,dffs[1:depth-1]};
754
assign q = dffs[depth];
755
endmodule
756
 
757 18 unneback
module vl_shreg_ce ( d, ce, q, clk, rst);
758 17 unneback
parameter depth = 10;
759
input d, ce;
760
output q;
761
input clk, rst;
762
 
763
reg [1:depth] dffs;
764
 
765
always @ (posedge clk or posedge rst)
766
if (rst)
767
    dffs <= {depth{1'b0}};
768
else
769
    if (ce)
770
        dffs <= {d,dffs[1:depth-1]};
771
assign q = dffs[depth];
772
endmodule
773
 
774 18 unneback
module vl_delay ( d, q, clk, rst);
775 15 unneback
parameter depth = 10;
776
input d;
777
output q;
778
input clk, rst;
779
 
780
reg [1:depth] dffs;
781
 
782
always @ (posedge clk or posedge rst)
783
if (rst)
784
    dffs <= {depth{1'b0}};
785
else
786
    dffs <= {d,dffs[1:depth-1]};
787
assign q = dffs[depth];
788 17 unneback
endmodule
789
 
790 18 unneback
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
791 17 unneback
parameter depth = 10;
792
input d;
793
output q, emptyflag;
794
input clk, rst;
795
 
796
reg [1:depth] dffs;
797
 
798
always @ (posedge clk or posedge rst)
799
if (rst)
800
    dffs <= {depth{1'b0}};
801
else
802
    dffs <= {d,dffs[1:depth-1]};
803
assign q = dffs[depth];
804
assign emptyflag = !(|dffs);
805
endmodule
806
//////////////////////////////////////////////////////////////////////
807 6 unneback
////                                                              ////
808 18 unneback
////  Logic functions                                             ////
809
////                                                              ////
810
////  Description                                                 ////
811
////  Logic functions such as multiplexers                        ////
812
////                                                              ////
813
////                                                              ////
814
////  To Do:                                                      ////
815
////   -                                                          ////
816
////                                                              ////
817
////  Author(s):                                                  ////
818
////      - Michael Unneback, unneback@opencores.org              ////
819
////        ORSoC AB                                              ////
820
////                                                              ////
821
//////////////////////////////////////////////////////////////////////
822
////                                                              ////
823
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
824
////                                                              ////
825
//// This source file may be used and distributed without         ////
826
//// restriction provided that this copyright statement is not    ////
827
//// removed from the file and that any derivative work contains  ////
828
//// the original copyright notice and the associated disclaimer. ////
829
////                                                              ////
830
//// This source file is free software; you can redistribute it   ////
831
//// and/or modify it under the terms of the GNU Lesser General   ////
832
//// Public License as published by the Free Software Foundation; ////
833
//// either version 2.1 of the License, or (at your option) any   ////
834
//// later version.                                               ////
835
////                                                              ////
836
//// This source is distributed in the hope that it will be       ////
837
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
838
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
839
//// PURPOSE.  See the GNU Lesser General Public License for more ////
840
//// details.                                                     ////
841
////                                                              ////
842
//// You should have received a copy of the GNU Lesser General    ////
843
//// Public License along with this source; if not, download it   ////
844
//// from http://www.opencores.org/lgpl.shtml                     ////
845
////                                                              ////
846
//////////////////////////////////////////////////////////////////////
847 36 unneback
module vl_mux_andor ( a, sel, dout);
848
 
849
parameter width = 32;
850
parameter nr_of_ports = 4;
851
 
852
input [nr_of_ports*width-1:0] a;
853
input [nr_of_ports-1:0] sel;
854
output reg [width-1:0] dout;
855
 
856
always @ (a, sel)
857
begin
858
    dout = a[width-1:0] & {width{sel[0]}};
859
    for (i=nr_of_ports-2;i<nr_of_ports;i=i+1)
860
        dout = (a[i*width-1:(i-1)*width] & {width{sel[i]}}) | dout;
861
end
862
 
863
endmodule
864
 
865 34 unneback
module vl_mux2_andor ( a1, a0, sel, dout);
866 18 unneback
 
867 34 unneback
parameter width = 32;
868 35 unneback
localparam nr_of_ports = 2;
869 34 unneback
input [width-1:0] a1, a0;
870
input [nr_of_ports-1:0] sel;
871
output [width-1:0] dout;
872
 
873 36 unneback
vl_mux_andor
874
    # ( .width(width), .nr_of_ports(nr_of_ports)
875
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
876
/*
877 34 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
878
integer i;
879
 
880
// and
881
assign tmp[0] = {width{sel[0]}} & a0;
882
assign tmp[1] = {width{sel[1]}} & a1;
883
 
884
// or
885
assign dout = tmp[1] | tmp[0];
886 36 unneback
*/
887 34 unneback
endmodule
888
 
889
module vl_mux3_andor ( a2, a1, a0, sel, dout);
890
 
891
parameter width = 32;
892 35 unneback
localparam nr_of_ports = 3;
893 34 unneback
input [width-1:0] a2, a1, a0;
894
input [nr_of_ports-1:0] sel;
895
output [width-1:0] dout;
896
 
897 36 unneback
vl_mux_andor
898
    # ( .width(width), .nr_of_ports(nr_of_ports)
899
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
900
/*
901
 
902 34 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
903
integer i;
904
 
905
// and
906
assign tmp[0] = {width{sel[0]}} & a0;
907
assign tmp[1] = {width{sel[1]}} & a1;
908
assign tmp[2] = {width{sel[2]}} & a2;
909
 
910
// or
911
assign dout = tmp[2] | tmp[1] | tmp[0];
912 36 unneback
*/
913 34 unneback
endmodule
914
 
915 18 unneback
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
916
 
917
parameter width = 32;
918 35 unneback
localparam nr_of_ports = 4;
919 18 unneback
input [width-1:0] a3, a2, a1, a0;
920
input [nr_of_ports-1:0] sel;
921 22 unneback
output [width-1:0] dout;
922 18 unneback
 
923 36 unneback
vl_mux_andor
924
    # ( .width(width), .nr_of_ports(nr_of_ports)
925
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
926
/*
927 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
928 18 unneback
integer i;
929
 
930
// and
931
assign tmp[0] = {width{sel[0]}} & a0;
932
assign tmp[1] = {width{sel[1]}} & a1;
933
assign tmp[2] = {width{sel[2]}} & a2;
934
assign tmp[3] = {width{sel[3]}} & a3;
935
 
936
// or
937
assign dout = tmp[3] | tmp[2] | tmp[1] | tmp[0];
938 36 unneback
*/
939 18 unneback
endmodule
940
 
941
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
942
 
943
parameter width = 32;
944 35 unneback
localparam nr_of_ports = 5;
945 18 unneback
input [width-1:0] a4, a3, a2, a1, a0;
946
input [nr_of_ports-1:0] sel;
947 22 unneback
output [width-1:0] dout;
948 18 unneback
 
949 36 unneback
vl_mux_andor
950
    # ( .width(width), .nr_of_ports(nr_of_ports)
951
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
952
/*
953 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
954 18 unneback
integer i;
955
 
956
// and
957
assign tmp[0] = {width{sel[0]}} & a0;
958
assign tmp[1] = {width{sel[1]}} & a1;
959
assign tmp[2] = {width{sel[2]}} & a2;
960
assign tmp[3] = {width{sel[3]}} & a3;
961
assign tmp[4] = {width{sel[4]}} & a4;
962
 
963
// or
964
assign dout = tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
965 36 unneback
*/
966 18 unneback
endmodule
967
 
968
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
969
 
970
parameter width = 32;
971 35 unneback
localparam nr_of_ports = 6;
972 18 unneback
input [width-1:0] a5, a4, a3, a2, a1, a0;
973
input [nr_of_ports-1:0] sel;
974 22 unneback
output [width-1:0] dout;
975 18 unneback
 
976 36 unneback
vl_mux_andor
977
    # ( .width(width), .nr_of_ports(nr_of_ports)
978
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
979
/*
980 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
981 18 unneback
integer i;
982
 
983
// and
984
assign tmp[0] = {width{sel[0]}} & a0;
985
assign tmp[1] = {width{sel[1]}} & a1;
986
assign tmp[2] = {width{sel[2]}} & a2;
987
assign tmp[3] = {width{sel[3]}} & a3;
988
assign tmp[4] = {width{sel[4]}} & a4;
989
assign tmp[5] = {width{sel[5]}} & a5;
990
 
991
// or
992
assign dout = tmp[5] | tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
993 36 unneback
*/
994 18 unneback
endmodule
995
//////////////////////////////////////////////////////////////////////
996
////                                                              ////
997 6 unneback
////  Versatile counter                                           ////
998
////                                                              ////
999
////  Description                                                 ////
1000
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1001
////  counter                                                     ////
1002
////                                                              ////
1003
////  To Do:                                                      ////
1004
////   - add LFSR with more taps                                  ////
1005
////                                                              ////
1006
////  Author(s):                                                  ////
1007
////      - Michael Unneback, unneback@opencores.org              ////
1008
////        ORSoC AB                                              ////
1009
////                                                              ////
1010
//////////////////////////////////////////////////////////////////////
1011
////                                                              ////
1012
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1013
////                                                              ////
1014
//// This source file may be used and distributed without         ////
1015
//// restriction provided that this copyright statement is not    ////
1016
//// removed from the file and that any derivative work contains  ////
1017
//// the original copyright notice and the associated disclaimer. ////
1018
////                                                              ////
1019
//// This source file is free software; you can redistribute it   ////
1020
//// and/or modify it under the terms of the GNU Lesser General   ////
1021
//// Public License as published by the Free Software Foundation; ////
1022
//// either version 2.1 of the License, or (at your option) any   ////
1023
//// later version.                                               ////
1024
////                                                              ////
1025
//// This source is distributed in the hope that it will be       ////
1026
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1027
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1028
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1029
//// details.                                                     ////
1030
////                                                              ////
1031
//// You should have received a copy of the GNU Lesser General    ////
1032
//// Public License along with this source; if not, download it   ////
1033
//// from http://www.opencores.org/lgpl.shtml                     ////
1034
////                                                              ////
1035
//////////////////////////////////////////////////////////////////////
1036
 
1037
// binary counter
1038 22 unneback
module vl_cnt_bin ( q, rst, clk);
1039
 
1040
   parameter length = 4;
1041
   output [length:1] q;
1042
   input rst;
1043
   input clk;
1044
 
1045
   parameter clear_value = 0;
1046
   parameter set_value = 1;
1047
   parameter wrap_value = 0;
1048
   parameter level1_value = 15;
1049
 
1050
   reg  [length:1] qi;
1051
   wire [length:1] q_next;
1052
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1053
 
1054
   always @ (posedge clk or posedge rst)
1055
     if (rst)
1056
       qi <= {length{1'b0}};
1057
     else
1058
       qi <= q_next;
1059
 
1060
   assign q = qi;
1061
 
1062
endmodule
1063
//////////////////////////////////////////////////////////////////////
1064
////                                                              ////
1065
////  Versatile counter                                           ////
1066
////                                                              ////
1067
////  Description                                                 ////
1068
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1069
////  counter                                                     ////
1070
////                                                              ////
1071
////  To Do:                                                      ////
1072
////   - add LFSR with more taps                                  ////
1073
////                                                              ////
1074
////  Author(s):                                                  ////
1075
////      - Michael Unneback, unneback@opencores.org              ////
1076
////        ORSoC AB                                              ////
1077
////                                                              ////
1078
//////////////////////////////////////////////////////////////////////
1079
////                                                              ////
1080
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1081
////                                                              ////
1082
//// This source file may be used and distributed without         ////
1083
//// restriction provided that this copyright statement is not    ////
1084
//// removed from the file and that any derivative work contains  ////
1085
//// the original copyright notice and the associated disclaimer. ////
1086
////                                                              ////
1087
//// This source file is free software; you can redistribute it   ////
1088
//// and/or modify it under the terms of the GNU Lesser General   ////
1089
//// Public License as published by the Free Software Foundation; ////
1090
//// either version 2.1 of the License, or (at your option) any   ////
1091
//// later version.                                               ////
1092
////                                                              ////
1093
//// This source is distributed in the hope that it will be       ////
1094
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1095
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1096
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1097
//// details.                                                     ////
1098
////                                                              ////
1099
//// You should have received a copy of the GNU Lesser General    ////
1100
//// Public License along with this source; if not, download it   ////
1101
//// from http://www.opencores.org/lgpl.shtml                     ////
1102
////                                                              ////
1103
//////////////////////////////////////////////////////////////////////
1104
 
1105
// binary counter
1106
module vl_cnt_bin_clear ( clear, q, rst, clk);
1107
 
1108
   parameter length = 4;
1109
   input clear;
1110
   output [length:1] q;
1111
   input rst;
1112
   input clk;
1113
 
1114
   parameter clear_value = 0;
1115
   parameter set_value = 1;
1116
   parameter wrap_value = 0;
1117
   parameter level1_value = 15;
1118
 
1119
   reg  [length:1] qi;
1120
   wire [length:1] q_next;
1121
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1122
 
1123
   always @ (posedge clk or posedge rst)
1124
     if (rst)
1125
       qi <= {length{1'b0}};
1126
     else
1127
       qi <= q_next;
1128
 
1129
   assign q = qi;
1130
 
1131
endmodule
1132
//////////////////////////////////////////////////////////////////////
1133
////                                                              ////
1134
////  Versatile counter                                           ////
1135
////                                                              ////
1136
////  Description                                                 ////
1137
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1138
////  counter                                                     ////
1139
////                                                              ////
1140
////  To Do:                                                      ////
1141
////   - add LFSR with more taps                                  ////
1142
////                                                              ////
1143
////  Author(s):                                                  ////
1144
////      - Michael Unneback, unneback@opencores.org              ////
1145
////        ORSoC AB                                              ////
1146
////                                                              ////
1147
//////////////////////////////////////////////////////////////////////
1148
////                                                              ////
1149
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1150
////                                                              ////
1151
//// This source file may be used and distributed without         ////
1152
//// restriction provided that this copyright statement is not    ////
1153
//// removed from the file and that any derivative work contains  ////
1154
//// the original copyright notice and the associated disclaimer. ////
1155
////                                                              ////
1156
//// This source file is free software; you can redistribute it   ////
1157
//// and/or modify it under the terms of the GNU Lesser General   ////
1158
//// Public License as published by the Free Software Foundation; ////
1159
//// either version 2.1 of the License, or (at your option) any   ////
1160
//// later version.                                               ////
1161
////                                                              ////
1162
//// This source is distributed in the hope that it will be       ////
1163
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1164
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1165
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1166
//// details.                                                     ////
1167
////                                                              ////
1168
//// You should have received a copy of the GNU Lesser General    ////
1169
//// Public License along with this source; if not, download it   ////
1170
//// from http://www.opencores.org/lgpl.shtml                     ////
1171
////                                                              ////
1172
//////////////////////////////////////////////////////////////////////
1173
 
1174
// binary counter
1175 18 unneback
module vl_cnt_bin_ce ( cke, q, rst, clk);
1176 6 unneback
 
1177
   parameter length = 4;
1178
   input cke;
1179
   output [length:1] q;
1180
   input rst;
1181
   input clk;
1182
 
1183
   parameter clear_value = 0;
1184
   parameter set_value = 1;
1185
   parameter wrap_value = 0;
1186
   parameter level1_value = 15;
1187
 
1188
   reg  [length:1] qi;
1189
   wire [length:1] q_next;
1190
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1191
 
1192
   always @ (posedge clk or posedge rst)
1193
     if (rst)
1194
       qi <= {length{1'b0}};
1195
     else
1196
     if (cke)
1197
       qi <= q_next;
1198
 
1199
   assign q = qi;
1200
 
1201
endmodule
1202
//////////////////////////////////////////////////////////////////////
1203
////                                                              ////
1204
////  Versatile counter                                           ////
1205
////                                                              ////
1206
////  Description                                                 ////
1207
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1208
////  counter                                                     ////
1209
////                                                              ////
1210
////  To Do:                                                      ////
1211
////   - add LFSR with more taps                                  ////
1212
////                                                              ////
1213
////  Author(s):                                                  ////
1214
////      - Michael Unneback, unneback@opencores.org              ////
1215
////        ORSoC AB                                              ////
1216
////                                                              ////
1217
//////////////////////////////////////////////////////////////////////
1218
////                                                              ////
1219
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1220
////                                                              ////
1221
//// This source file may be used and distributed without         ////
1222
//// restriction provided that this copyright statement is not    ////
1223
//// removed from the file and that any derivative work contains  ////
1224
//// the original copyright notice and the associated disclaimer. ////
1225
////                                                              ////
1226
//// This source file is free software; you can redistribute it   ////
1227
//// and/or modify it under the terms of the GNU Lesser General   ////
1228
//// Public License as published by the Free Software Foundation; ////
1229
//// either version 2.1 of the License, or (at your option) any   ////
1230
//// later version.                                               ////
1231
////                                                              ////
1232
//// This source is distributed in the hope that it will be       ////
1233
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1234
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1235
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1236
//// details.                                                     ////
1237
////                                                              ////
1238
//// You should have received a copy of the GNU Lesser General    ////
1239
//// Public License along with this source; if not, download it   ////
1240
//// from http://www.opencores.org/lgpl.shtml                     ////
1241
////                                                              ////
1242
//////////////////////////////////////////////////////////////////////
1243
 
1244
// binary counter
1245 18 unneback
module vl_cnt_bin_ce_clear ( clear, cke, q, rst, clk);
1246 6 unneback
 
1247
   parameter length = 4;
1248
   input clear;
1249
   input cke;
1250
   output [length:1] q;
1251
   input rst;
1252
   input clk;
1253
 
1254
   parameter clear_value = 0;
1255
   parameter set_value = 1;
1256
   parameter wrap_value = 0;
1257
   parameter level1_value = 15;
1258
 
1259
   reg  [length:1] qi;
1260
   wire [length:1] q_next;
1261
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1262
 
1263
   always @ (posedge clk or posedge rst)
1264
     if (rst)
1265
       qi <= {length{1'b0}};
1266
     else
1267
     if (cke)
1268
       qi <= q_next;
1269
 
1270
   assign q = qi;
1271
 
1272
endmodule
1273
//////////////////////////////////////////////////////////////////////
1274
////                                                              ////
1275
////  Versatile counter                                           ////
1276
////                                                              ////
1277
////  Description                                                 ////
1278
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1279
////  counter                                                     ////
1280
////                                                              ////
1281
////  To Do:                                                      ////
1282
////   - add LFSR with more taps                                  ////
1283
////                                                              ////
1284
////  Author(s):                                                  ////
1285
////      - Michael Unneback, unneback@opencores.org              ////
1286
////        ORSoC AB                                              ////
1287
////                                                              ////
1288
//////////////////////////////////////////////////////////////////////
1289
////                                                              ////
1290
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1291
////                                                              ////
1292
//// This source file may be used and distributed without         ////
1293
//// restriction provided that this copyright statement is not    ////
1294
//// removed from the file and that any derivative work contains  ////
1295
//// the original copyright notice and the associated disclaimer. ////
1296
////                                                              ////
1297
//// This source file is free software; you can redistribute it   ////
1298
//// and/or modify it under the terms of the GNU Lesser General   ////
1299
//// Public License as published by the Free Software Foundation; ////
1300
//// either version 2.1 of the License, or (at your option) any   ////
1301
//// later version.                                               ////
1302
////                                                              ////
1303
//// This source is distributed in the hope that it will be       ////
1304
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1305
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1306
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1307
//// details.                                                     ////
1308
////                                                              ////
1309
//// You should have received a copy of the GNU Lesser General    ////
1310
//// Public License along with this source; if not, download it   ////
1311
//// from http://www.opencores.org/lgpl.shtml                     ////
1312
////                                                              ////
1313
//////////////////////////////////////////////////////////////////////
1314
 
1315
// binary counter
1316 29 unneback
module vl_cnt_bin_ce_clear_l1_l2 ( clear, cke, q, level1, level2, rst, clk);
1317
 
1318
   parameter length = 4;
1319
   input clear;
1320
   input cke;
1321
   output [length:1] q;
1322
   output reg level1;
1323
   output reg level2;
1324
   input rst;
1325
   input clk;
1326
 
1327
   parameter clear_value = 0;
1328
   parameter set_value = 1;
1329 30 unneback
   parameter wrap_value = 15;
1330
   parameter level1_value = 8;
1331
   parameter level2_value = 15;
1332 29 unneback
 
1333
   wire rew;
1334 30 unneback
   assign rew = 1'b0;
1335 29 unneback
   reg  [length:1] qi;
1336
   wire [length:1] q_next;
1337
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1338
 
1339
   always @ (posedge clk or posedge rst)
1340
     if (rst)
1341
       qi <= {length{1'b0}};
1342
     else
1343
     if (cke)
1344
       qi <= q_next;
1345
 
1346
   assign q = qi;
1347
 
1348
 
1349
    always @ (posedge clk or posedge rst)
1350
    if (rst)
1351
        level1 <= 1'b0;
1352
    else
1353
    if (cke)
1354
    if (clear)
1355
        level1 <= 1'b0;
1356
    else if (q_next == level1_value)
1357
        level1 <= 1'b1;
1358
    else if (qi == level1_value & rew)
1359
        level1 <= 1'b0;
1360
 
1361
    always @ (posedge clk or posedge rst)
1362
    if (rst)
1363
        level2 <= 1'b0;
1364
    else
1365
    if (cke)
1366
    if (clear)
1367
        level2 <= 1'b0;
1368
    else if (q_next == level2_value)
1369
        level2 <= 1'b1;
1370
    else if (qi == level2_value & rew)
1371
        level2 <= 1'b0;
1372
endmodule
1373
//////////////////////////////////////////////////////////////////////
1374
////                                                              ////
1375
////  Versatile counter                                           ////
1376
////                                                              ////
1377
////  Description                                                 ////
1378
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1379
////  counter                                                     ////
1380
////                                                              ////
1381
////  To Do:                                                      ////
1382
////   - add LFSR with more taps                                  ////
1383
////                                                              ////
1384
////  Author(s):                                                  ////
1385
////      - Michael Unneback, unneback@opencores.org              ////
1386
////        ORSoC AB                                              ////
1387
////                                                              ////
1388
//////////////////////////////////////////////////////////////////////
1389
////                                                              ////
1390
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1391
////                                                              ////
1392
//// This source file may be used and distributed without         ////
1393
//// restriction provided that this copyright statement is not    ////
1394
//// removed from the file and that any derivative work contains  ////
1395
//// the original copyright notice and the associated disclaimer. ////
1396
////                                                              ////
1397
//// This source file is free software; you can redistribute it   ////
1398
//// and/or modify it under the terms of the GNU Lesser General   ////
1399
//// Public License as published by the Free Software Foundation; ////
1400
//// either version 2.1 of the License, or (at your option) any   ////
1401
//// later version.                                               ////
1402
////                                                              ////
1403
//// This source is distributed in the hope that it will be       ////
1404
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1405
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1406
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1407
//// details.                                                     ////
1408
////                                                              ////
1409
//// You should have received a copy of the GNU Lesser General    ////
1410
//// Public License along with this source; if not, download it   ////
1411
//// from http://www.opencores.org/lgpl.shtml                     ////
1412
////                                                              ////
1413
//////////////////////////////////////////////////////////////////////
1414
 
1415
// binary counter
1416 18 unneback
module vl_cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk);
1417 6 unneback
 
1418
   parameter length = 4;
1419
   input clear;
1420
   input set;
1421
   input cke;
1422
   input rew;
1423
   output [length:1] q;
1424
   input rst;
1425
   input clk;
1426
 
1427
   parameter clear_value = 0;
1428
   parameter set_value = 1;
1429
   parameter wrap_value = 0;
1430
   parameter level1_value = 15;
1431
 
1432
   reg  [length:1] qi;
1433
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1434
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
1435
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
1436
   assign q_next = rew ? q_next_rew : q_next_fw;
1437
 
1438
   always @ (posedge clk or posedge rst)
1439
     if (rst)
1440
       qi <= {length{1'b0}};
1441
     else
1442
     if (cke)
1443
       qi <= q_next;
1444
 
1445
   assign q = qi;
1446
 
1447
endmodule
1448
//////////////////////////////////////////////////////////////////////
1449
////                                                              ////
1450
////  Versatile counter                                           ////
1451
////                                                              ////
1452
////  Description                                                 ////
1453
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1454
////  counter                                                     ////
1455
////                                                              ////
1456
////  To Do:                                                      ////
1457
////   - add LFSR with more taps                                  ////
1458
////                                                              ////
1459
////  Author(s):                                                  ////
1460
////      - Michael Unneback, unneback@opencores.org              ////
1461
////        ORSoC AB                                              ////
1462
////                                                              ////
1463
//////////////////////////////////////////////////////////////////////
1464
////                                                              ////
1465
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1466
////                                                              ////
1467
//// This source file may be used and distributed without         ////
1468
//// restriction provided that this copyright statement is not    ////
1469
//// removed from the file and that any derivative work contains  ////
1470
//// the original copyright notice and the associated disclaimer. ////
1471
////                                                              ////
1472
//// This source file is free software; you can redistribute it   ////
1473
//// and/or modify it under the terms of the GNU Lesser General   ////
1474
//// Public License as published by the Free Software Foundation; ////
1475
//// either version 2.1 of the License, or (at your option) any   ////
1476
//// later version.                                               ////
1477
////                                                              ////
1478
//// This source is distributed in the hope that it will be       ////
1479
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1480
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1481
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1482
//// details.                                                     ////
1483
////                                                              ////
1484
//// You should have received a copy of the GNU Lesser General    ////
1485
//// Public License along with this source; if not, download it   ////
1486
//// from http://www.opencores.org/lgpl.shtml                     ////
1487
////                                                              ////
1488
//////////////////////////////////////////////////////////////////////
1489
 
1490
// binary counter
1491 18 unneback
module vl_cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk);
1492 6 unneback
 
1493
   parameter length = 4;
1494
   input cke;
1495
   input rew;
1496
   output reg level1;
1497
   input rst;
1498
   input clk;
1499
 
1500
   parameter clear_value = 0;
1501
   parameter set_value = 1;
1502
   parameter wrap_value = 1;
1503
   parameter level1_value = 15;
1504
 
1505 29 unneback
   wire clear;
1506 30 unneback
   assign clear = 1'b0;
1507 6 unneback
   reg  [length:1] qi;
1508
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1509
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1510
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1511
   assign q_next = rew ? q_next_rew : q_next_fw;
1512
 
1513
   always @ (posedge clk or posedge rst)
1514
     if (rst)
1515
       qi <= {length{1'b0}};
1516
     else
1517
     if (cke)
1518
       qi <= q_next;
1519
 
1520
 
1521
 
1522
    always @ (posedge clk or posedge rst)
1523
    if (rst)
1524
        level1 <= 1'b0;
1525
    else
1526
    if (cke)
1527 29 unneback
    if (clear)
1528
        level1 <= 1'b0;
1529
    else if (q_next == level1_value)
1530 6 unneback
        level1 <= 1'b1;
1531
    else if (qi == level1_value & rew)
1532
        level1 <= 1'b0;
1533
endmodule
1534
//////////////////////////////////////////////////////////////////////
1535
////                                                              ////
1536
////  Versatile counter                                           ////
1537
////                                                              ////
1538
////  Description                                                 ////
1539
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1540
////  counter                                                     ////
1541
////                                                              ////
1542
////  To Do:                                                      ////
1543
////   - add LFSR with more taps                                  ////
1544
////                                                              ////
1545
////  Author(s):                                                  ////
1546
////      - Michael Unneback, unneback@opencores.org              ////
1547
////        ORSoC AB                                              ////
1548
////                                                              ////
1549
//////////////////////////////////////////////////////////////////////
1550
////                                                              ////
1551
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1552
////                                                              ////
1553
//// This source file may be used and distributed without         ////
1554
//// restriction provided that this copyright statement is not    ////
1555
//// removed from the file and that any derivative work contains  ////
1556
//// the original copyright notice and the associated disclaimer. ////
1557
////                                                              ////
1558
//// This source file is free software; you can redistribute it   ////
1559
//// and/or modify it under the terms of the GNU Lesser General   ////
1560
//// Public License as published by the Free Software Foundation; ////
1561
//// either version 2.1 of the License, or (at your option) any   ////
1562
//// later version.                                               ////
1563
////                                                              ////
1564
//// This source is distributed in the hope that it will be       ////
1565
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1566
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1567
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1568
//// details.                                                     ////
1569
////                                                              ////
1570
//// You should have received a copy of the GNU Lesser General    ////
1571
//// Public License along with this source; if not, download it   ////
1572
//// from http://www.opencores.org/lgpl.shtml                     ////
1573
////                                                              ////
1574
//////////////////////////////////////////////////////////////////////
1575
 
1576 25 unneback
// binary counter
1577
module vl_cnt_bin_ce_rew_zq_l1 ( cke, rew, zq, level1, rst, clk);
1578
 
1579
   parameter length = 4;
1580
   input cke;
1581
   input rew;
1582
   output reg zq;
1583
   output reg level1;
1584
   input rst;
1585
   input clk;
1586
 
1587
   parameter clear_value = 0;
1588
   parameter set_value = 1;
1589
   parameter wrap_value = 1;
1590
   parameter level1_value = 15;
1591
 
1592 29 unneback
   wire clear;
1593 30 unneback
   assign clear = 1'b0;
1594 25 unneback
   reg  [length:1] qi;
1595
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1596
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1597
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1598
   assign q_next = rew ? q_next_rew : q_next_fw;
1599
 
1600
   always @ (posedge clk or posedge rst)
1601
     if (rst)
1602
       qi <= {length{1'b0}};
1603
     else
1604
     if (cke)
1605
       qi <= q_next;
1606
 
1607
 
1608
 
1609
   always @ (posedge clk or posedge rst)
1610
     if (rst)
1611
       zq <= 1'b1;
1612
     else
1613
     if (cke)
1614
       zq <= q_next == {length{1'b0}};
1615
 
1616
    always @ (posedge clk or posedge rst)
1617
    if (rst)
1618
        level1 <= 1'b0;
1619
    else
1620
    if (cke)
1621 29 unneback
    if (clear)
1622
        level1 <= 1'b0;
1623
    else if (q_next == level1_value)
1624 25 unneback
        level1 <= 1'b1;
1625
    else if (qi == level1_value & rew)
1626
        level1 <= 1'b0;
1627
endmodule
1628
//////////////////////////////////////////////////////////////////////
1629
////                                                              ////
1630
////  Versatile counter                                           ////
1631
////                                                              ////
1632
////  Description                                                 ////
1633
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1634
////  counter                                                     ////
1635
////                                                              ////
1636
////  To Do:                                                      ////
1637
////   - add LFSR with more taps                                  ////
1638
////                                                              ////
1639
////  Author(s):                                                  ////
1640
////      - Michael Unneback, unneback@opencores.org              ////
1641
////        ORSoC AB                                              ////
1642
////                                                              ////
1643
//////////////////////////////////////////////////////////////////////
1644
////                                                              ////
1645
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1646
////                                                              ////
1647
//// This source file may be used and distributed without         ////
1648
//// restriction provided that this copyright statement is not    ////
1649
//// removed from the file and that any derivative work contains  ////
1650
//// the original copyright notice and the associated disclaimer. ////
1651
////                                                              ////
1652
//// This source file is free software; you can redistribute it   ////
1653
//// and/or modify it under the terms of the GNU Lesser General   ////
1654
//// Public License as published by the Free Software Foundation; ////
1655
//// either version 2.1 of the License, or (at your option) any   ////
1656
//// later version.                                               ////
1657
////                                                              ////
1658
//// This source is distributed in the hope that it will be       ////
1659
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1660
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1661
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1662
//// details.                                                     ////
1663
////                                                              ////
1664
//// You should have received a copy of the GNU Lesser General    ////
1665
//// Public License along with this source; if not, download it   ////
1666
//// from http://www.opencores.org/lgpl.shtml                     ////
1667
////                                                              ////
1668
//////////////////////////////////////////////////////////////////////
1669
 
1670
// binary counter
1671
module vl_cnt_bin_ce_rew_q_zq_l1 ( cke, rew, q, zq, level1, rst, clk);
1672
 
1673
   parameter length = 4;
1674
   input cke;
1675
   input rew;
1676
   output [length:1] q;
1677
   output reg zq;
1678
   output reg level1;
1679
   input rst;
1680
   input clk;
1681
 
1682
   parameter clear_value = 0;
1683
   parameter set_value = 1;
1684
   parameter wrap_value = 1;
1685
   parameter level1_value = 15;
1686
 
1687 29 unneback
   wire clear;
1688 30 unneback
   assign clear = 1'b0;
1689 25 unneback
   reg  [length:1] qi;
1690
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1691
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1692
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1693
   assign q_next = rew ? q_next_rew : q_next_fw;
1694
 
1695
   always @ (posedge clk or posedge rst)
1696
     if (rst)
1697
       qi <= {length{1'b0}};
1698
     else
1699
     if (cke)
1700
       qi <= q_next;
1701
 
1702
   assign q = qi;
1703
 
1704
 
1705
   always @ (posedge clk or posedge rst)
1706
     if (rst)
1707
       zq <= 1'b1;
1708
     else
1709
     if (cke)
1710
       zq <= q_next == {length{1'b0}};
1711
 
1712
    always @ (posedge clk or posedge rst)
1713
    if (rst)
1714
        level1 <= 1'b0;
1715
    else
1716
    if (cke)
1717 29 unneback
    if (clear)
1718
        level1 <= 1'b0;
1719
    else if (q_next == level1_value)
1720 25 unneback
        level1 <= 1'b1;
1721
    else if (qi == level1_value & rew)
1722
        level1 <= 1'b0;
1723
endmodule
1724
//////////////////////////////////////////////////////////////////////
1725
////                                                              ////
1726
////  Versatile counter                                           ////
1727
////                                                              ////
1728
////  Description                                                 ////
1729
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1730
////  counter                                                     ////
1731
////                                                              ////
1732
////  To Do:                                                      ////
1733
////   - add LFSR with more taps                                  ////
1734
////                                                              ////
1735
////  Author(s):                                                  ////
1736
////      - Michael Unneback, unneback@opencores.org              ////
1737
////        ORSoC AB                                              ////
1738
////                                                              ////
1739
//////////////////////////////////////////////////////////////////////
1740
////                                                              ////
1741
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1742
////                                                              ////
1743
//// This source file may be used and distributed without         ////
1744
//// restriction provided that this copyright statement is not    ////
1745
//// removed from the file and that any derivative work contains  ////
1746
//// the original copyright notice and the associated disclaimer. ////
1747
////                                                              ////
1748
//// This source file is free software; you can redistribute it   ////
1749
//// and/or modify it under the terms of the GNU Lesser General   ////
1750
//// Public License as published by the Free Software Foundation; ////
1751
//// either version 2.1 of the License, or (at your option) any   ////
1752
//// later version.                                               ////
1753
////                                                              ////
1754
//// This source is distributed in the hope that it will be       ////
1755
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1756
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1757
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1758
//// details.                                                     ////
1759
////                                                              ////
1760
//// You should have received a copy of the GNU Lesser General    ////
1761
//// Public License along with this source; if not, download it   ////
1762
//// from http://www.opencores.org/lgpl.shtml                     ////
1763
////                                                              ////
1764
//////////////////////////////////////////////////////////////////////
1765
 
1766 6 unneback
// LFSR counter
1767 18 unneback
module vl_cnt_lfsr_zq ( zq, rst, clk);
1768 6 unneback
 
1769
   parameter length = 4;
1770
   output reg zq;
1771
   input rst;
1772
   input clk;
1773
 
1774
   parameter clear_value = 0;
1775
   parameter set_value = 1;
1776
   parameter wrap_value = 8;
1777
   parameter level1_value = 15;
1778
 
1779
   reg  [length:1] qi;
1780
   reg lfsr_fb;
1781
   wire [length:1] q_next;
1782
   reg [32:1] polynom;
1783
   integer i;
1784
 
1785
   always @ (qi)
1786
   begin
1787
        case (length)
1788
         2: polynom = 32'b11;                               // 0x3
1789
         3: polynom = 32'b110;                              // 0x6
1790
         4: polynom = 32'b1100;                             // 0xC
1791
         5: polynom = 32'b10100;                            // 0x14
1792
         6: polynom = 32'b110000;                           // 0x30
1793
         7: polynom = 32'b1100000;                          // 0x60
1794
         8: polynom = 32'b10111000;                         // 0xb8
1795
         9: polynom = 32'b100010000;                        // 0x110
1796
        10: polynom = 32'b1001000000;                       // 0x240
1797
        11: polynom = 32'b10100000000;                      // 0x500
1798
        12: polynom = 32'b100000101001;                     // 0x829
1799
        13: polynom = 32'b1000000001100;                    // 0x100C
1800
        14: polynom = 32'b10000000010101;                   // 0x2015
1801
        15: polynom = 32'b110000000000000;                  // 0x6000
1802
        16: polynom = 32'b1101000000001000;                 // 0xD008
1803
        17: polynom = 32'b10010000000000000;                // 0x12000
1804
        18: polynom = 32'b100000010000000000;               // 0x20400
1805
        19: polynom = 32'b1000000000000100011;              // 0x40023
1806
        20: polynom = 32'b10000010000000000000;             // 0x82000
1807
        21: polynom = 32'b101000000000000000000;            // 0x140000
1808
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1809
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1810
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1811
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1812
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1813
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1814
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1815
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1816
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1817
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1818
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1819
        default: polynom = 32'b0;
1820
        endcase
1821
        lfsr_fb = qi[length];
1822
        for (i=length-1; i>=1; i=i-1) begin
1823
            if (polynom[i])
1824
                lfsr_fb = lfsr_fb  ~^ qi[i];
1825
        end
1826
    end
1827
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1828
 
1829
   always @ (posedge clk or posedge rst)
1830
     if (rst)
1831
       qi <= {length{1'b0}};
1832
     else
1833
       qi <= q_next;
1834
 
1835
 
1836
 
1837
   always @ (posedge clk or posedge rst)
1838
     if (rst)
1839
       zq <= 1'b1;
1840
     else
1841
       zq <= q_next == {length{1'b0}};
1842
endmodule
1843
//////////////////////////////////////////////////////////////////////
1844
////                                                              ////
1845
////  Versatile counter                                           ////
1846
////                                                              ////
1847
////  Description                                                 ////
1848
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1849
////  counter                                                     ////
1850
////                                                              ////
1851
////  To Do:                                                      ////
1852
////   - add LFSR with more taps                                  ////
1853
////                                                              ////
1854
////  Author(s):                                                  ////
1855
////      - Michael Unneback, unneback@opencores.org              ////
1856
////        ORSoC AB                                              ////
1857
////                                                              ////
1858
//////////////////////////////////////////////////////////////////////
1859
////                                                              ////
1860
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1861
////                                                              ////
1862
//// This source file may be used and distributed without         ////
1863
//// restriction provided that this copyright statement is not    ////
1864
//// removed from the file and that any derivative work contains  ////
1865
//// the original copyright notice and the associated disclaimer. ////
1866
////                                                              ////
1867
//// This source file is free software; you can redistribute it   ////
1868
//// and/or modify it under the terms of the GNU Lesser General   ////
1869
//// Public License as published by the Free Software Foundation; ////
1870
//// either version 2.1 of the License, or (at your option) any   ////
1871
//// later version.                                               ////
1872
////                                                              ////
1873
//// This source is distributed in the hope that it will be       ////
1874
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1875
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1876
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1877
//// details.                                                     ////
1878
////                                                              ////
1879
//// You should have received a copy of the GNU Lesser General    ////
1880
//// Public License along with this source; if not, download it   ////
1881
//// from http://www.opencores.org/lgpl.shtml                     ////
1882
////                                                              ////
1883
//////////////////////////////////////////////////////////////////////
1884
 
1885
// LFSR counter
1886 18 unneback
module vl_cnt_lfsr_ce_zq ( cke, zq, rst, clk);
1887 6 unneback
 
1888
   parameter length = 4;
1889
   input cke;
1890
   output reg zq;
1891
   input rst;
1892
   input clk;
1893
 
1894
   parameter clear_value = 0;
1895
   parameter set_value = 1;
1896
   parameter wrap_value = 8;
1897
   parameter level1_value = 15;
1898
 
1899
   reg  [length:1] qi;
1900
   reg lfsr_fb;
1901
   wire [length:1] q_next;
1902
   reg [32:1] polynom;
1903
   integer i;
1904
 
1905
   always @ (qi)
1906
   begin
1907
        case (length)
1908
         2: polynom = 32'b11;                               // 0x3
1909
         3: polynom = 32'b110;                              // 0x6
1910
         4: polynom = 32'b1100;                             // 0xC
1911
         5: polynom = 32'b10100;                            // 0x14
1912
         6: polynom = 32'b110000;                           // 0x30
1913
         7: polynom = 32'b1100000;                          // 0x60
1914
         8: polynom = 32'b10111000;                         // 0xb8
1915
         9: polynom = 32'b100010000;                        // 0x110
1916
        10: polynom = 32'b1001000000;                       // 0x240
1917
        11: polynom = 32'b10100000000;                      // 0x500
1918
        12: polynom = 32'b100000101001;                     // 0x829
1919
        13: polynom = 32'b1000000001100;                    // 0x100C
1920
        14: polynom = 32'b10000000010101;                   // 0x2015
1921
        15: polynom = 32'b110000000000000;                  // 0x6000
1922
        16: polynom = 32'b1101000000001000;                 // 0xD008
1923
        17: polynom = 32'b10010000000000000;                // 0x12000
1924
        18: polynom = 32'b100000010000000000;               // 0x20400
1925
        19: polynom = 32'b1000000000000100011;              // 0x40023
1926
        20: polynom = 32'b10000010000000000000;             // 0x82000
1927
        21: polynom = 32'b101000000000000000000;            // 0x140000
1928
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1929
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1930
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1931
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1932
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1933
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1934
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1935
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1936
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1937
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1938
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1939
        default: polynom = 32'b0;
1940
        endcase
1941
        lfsr_fb = qi[length];
1942
        for (i=length-1; i>=1; i=i-1) begin
1943
            if (polynom[i])
1944
                lfsr_fb = lfsr_fb  ~^ qi[i];
1945
        end
1946
    end
1947
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1948
 
1949
   always @ (posedge clk or posedge rst)
1950
     if (rst)
1951
       qi <= {length{1'b0}};
1952
     else
1953
     if (cke)
1954
       qi <= q_next;
1955
 
1956
 
1957
 
1958
   always @ (posedge clk or posedge rst)
1959
     if (rst)
1960
       zq <= 1'b1;
1961
     else
1962
     if (cke)
1963
       zq <= q_next == {length{1'b0}};
1964
endmodule
1965
//////////////////////////////////////////////////////////////////////
1966
////                                                              ////
1967
////  Versatile counter                                           ////
1968
////                                                              ////
1969
////  Description                                                 ////
1970
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1971
////  counter                                                     ////
1972
////                                                              ////
1973
////  To Do:                                                      ////
1974
////   - add LFSR with more taps                                  ////
1975
////                                                              ////
1976
////  Author(s):                                                  ////
1977
////      - Michael Unneback, unneback@opencores.org              ////
1978
////        ORSoC AB                                              ////
1979
////                                                              ////
1980
//////////////////////////////////////////////////////////////////////
1981
////                                                              ////
1982
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1983
////                                                              ////
1984
//// This source file may be used and distributed without         ////
1985
//// restriction provided that this copyright statement is not    ////
1986
//// removed from the file and that any derivative work contains  ////
1987
//// the original copyright notice and the associated disclaimer. ////
1988
////                                                              ////
1989
//// This source file is free software; you can redistribute it   ////
1990
//// and/or modify it under the terms of the GNU Lesser General   ////
1991
//// Public License as published by the Free Software Foundation; ////
1992
//// either version 2.1 of the License, or (at your option) any   ////
1993
//// later version.                                               ////
1994
////                                                              ////
1995
//// This source is distributed in the hope that it will be       ////
1996
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1997
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1998
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1999
//// details.                                                     ////
2000
////                                                              ////
2001
//// You should have received a copy of the GNU Lesser General    ////
2002
//// Public License along with this source; if not, download it   ////
2003
//// from http://www.opencores.org/lgpl.shtml                     ////
2004
////                                                              ////
2005
//////////////////////////////////////////////////////////////////////
2006 22 unneback
 
2007
// LFSR counter
2008 27 unneback
module vl_cnt_lfsr_ce_q ( cke, q, rst, clk);
2009
 
2010
   parameter length = 4;
2011
   input cke;
2012
   output [length:1] q;
2013
   input rst;
2014
   input clk;
2015
 
2016
   parameter clear_value = 0;
2017
   parameter set_value = 1;
2018
   parameter wrap_value = 8;
2019
   parameter level1_value = 15;
2020
 
2021
   reg  [length:1] qi;
2022
   reg lfsr_fb;
2023
   wire [length:1] q_next;
2024
   reg [32:1] polynom;
2025
   integer i;
2026
 
2027
   always @ (qi)
2028
   begin
2029
        case (length)
2030
         2: polynom = 32'b11;                               // 0x3
2031
         3: polynom = 32'b110;                              // 0x6
2032
         4: polynom = 32'b1100;                             // 0xC
2033
         5: polynom = 32'b10100;                            // 0x14
2034
         6: polynom = 32'b110000;                           // 0x30
2035
         7: polynom = 32'b1100000;                          // 0x60
2036
         8: polynom = 32'b10111000;                         // 0xb8
2037
         9: polynom = 32'b100010000;                        // 0x110
2038
        10: polynom = 32'b1001000000;                       // 0x240
2039
        11: polynom = 32'b10100000000;                      // 0x500
2040
        12: polynom = 32'b100000101001;                     // 0x829
2041
        13: polynom = 32'b1000000001100;                    // 0x100C
2042
        14: polynom = 32'b10000000010101;                   // 0x2015
2043
        15: polynom = 32'b110000000000000;                  // 0x6000
2044
        16: polynom = 32'b1101000000001000;                 // 0xD008
2045
        17: polynom = 32'b10010000000000000;                // 0x12000
2046
        18: polynom = 32'b100000010000000000;               // 0x20400
2047
        19: polynom = 32'b1000000000000100011;              // 0x40023
2048
        20: polynom = 32'b10000010000000000000;             // 0x82000
2049
        21: polynom = 32'b101000000000000000000;            // 0x140000
2050
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2051
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2052
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2053
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2054
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2055
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2056
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2057
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2058
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2059
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2060
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2061
        default: polynom = 32'b0;
2062
        endcase
2063
        lfsr_fb = qi[length];
2064
        for (i=length-1; i>=1; i=i-1) begin
2065
            if (polynom[i])
2066
                lfsr_fb = lfsr_fb  ~^ qi[i];
2067
        end
2068
    end
2069
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2070
 
2071
   always @ (posedge clk or posedge rst)
2072
     if (rst)
2073
       qi <= {length{1'b0}};
2074
     else
2075
     if (cke)
2076
       qi <= q_next;
2077
 
2078
   assign q = qi;
2079
 
2080
endmodule
2081
//////////////////////////////////////////////////////////////////////
2082
////                                                              ////
2083
////  Versatile counter                                           ////
2084
////                                                              ////
2085
////  Description                                                 ////
2086
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2087
////  counter                                                     ////
2088
////                                                              ////
2089
////  To Do:                                                      ////
2090
////   - add LFSR with more taps                                  ////
2091
////                                                              ////
2092
////  Author(s):                                                  ////
2093
////      - Michael Unneback, unneback@opencores.org              ////
2094
////        ORSoC AB                                              ////
2095
////                                                              ////
2096
//////////////////////////////////////////////////////////////////////
2097
////                                                              ////
2098
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2099
////                                                              ////
2100
//// This source file may be used and distributed without         ////
2101
//// restriction provided that this copyright statement is not    ////
2102
//// removed from the file and that any derivative work contains  ////
2103
//// the original copyright notice and the associated disclaimer. ////
2104
////                                                              ////
2105
//// This source file is free software; you can redistribute it   ////
2106
//// and/or modify it under the terms of the GNU Lesser General   ////
2107
//// Public License as published by the Free Software Foundation; ////
2108
//// either version 2.1 of the License, or (at your option) any   ////
2109
//// later version.                                               ////
2110
////                                                              ////
2111
//// This source is distributed in the hope that it will be       ////
2112
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2113
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2114
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2115
//// details.                                                     ////
2116
////                                                              ////
2117
//// You should have received a copy of the GNU Lesser General    ////
2118
//// Public License along with this source; if not, download it   ////
2119
//// from http://www.opencores.org/lgpl.shtml                     ////
2120
////                                                              ////
2121
//////////////////////////////////////////////////////////////////////
2122
 
2123
// LFSR counter
2124
module vl_cnt_lfsr_ce_clear_q ( clear, cke, q, rst, clk);
2125
 
2126
   parameter length = 4;
2127
   input clear;
2128
   input cke;
2129
   output [length:1] q;
2130
   input rst;
2131
   input clk;
2132
 
2133
   parameter clear_value = 0;
2134
   parameter set_value = 1;
2135
   parameter wrap_value = 8;
2136
   parameter level1_value = 15;
2137
 
2138
   reg  [length:1] qi;
2139
   reg lfsr_fb;
2140
   wire [length:1] q_next;
2141
   reg [32:1] polynom;
2142
   integer i;
2143
 
2144
   always @ (qi)
2145
   begin
2146
        case (length)
2147
         2: polynom = 32'b11;                               // 0x3
2148
         3: polynom = 32'b110;                              // 0x6
2149
         4: polynom = 32'b1100;                             // 0xC
2150
         5: polynom = 32'b10100;                            // 0x14
2151
         6: polynom = 32'b110000;                           // 0x30
2152
         7: polynom = 32'b1100000;                          // 0x60
2153
         8: polynom = 32'b10111000;                         // 0xb8
2154
         9: polynom = 32'b100010000;                        // 0x110
2155
        10: polynom = 32'b1001000000;                       // 0x240
2156
        11: polynom = 32'b10100000000;                      // 0x500
2157
        12: polynom = 32'b100000101001;                     // 0x829
2158
        13: polynom = 32'b1000000001100;                    // 0x100C
2159
        14: polynom = 32'b10000000010101;                   // 0x2015
2160
        15: polynom = 32'b110000000000000;                  // 0x6000
2161
        16: polynom = 32'b1101000000001000;                 // 0xD008
2162
        17: polynom = 32'b10010000000000000;                // 0x12000
2163
        18: polynom = 32'b100000010000000000;               // 0x20400
2164
        19: polynom = 32'b1000000000000100011;              // 0x40023
2165
        20: polynom = 32'b10000010000000000000;             // 0x82000
2166
        21: polynom = 32'b101000000000000000000;            // 0x140000
2167
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2168
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2169
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2170
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2171
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2172
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2173
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2174
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2175
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2176
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2177
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2178
        default: polynom = 32'b0;
2179
        endcase
2180
        lfsr_fb = qi[length];
2181
        for (i=length-1; i>=1; i=i-1) begin
2182
            if (polynom[i])
2183
                lfsr_fb = lfsr_fb  ~^ qi[i];
2184
        end
2185
    end
2186
   assign q_next =  clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2187
 
2188
   always @ (posedge clk or posedge rst)
2189
     if (rst)
2190
       qi <= {length{1'b0}};
2191
     else
2192
     if (cke)
2193
       qi <= q_next;
2194
 
2195
   assign q = qi;
2196
 
2197
endmodule
2198
//////////////////////////////////////////////////////////////////////
2199
////                                                              ////
2200
////  Versatile counter                                           ////
2201
////                                                              ////
2202
////  Description                                                 ////
2203
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2204
////  counter                                                     ////
2205
////                                                              ////
2206
////  To Do:                                                      ////
2207
////   - add LFSR with more taps                                  ////
2208
////                                                              ////
2209
////  Author(s):                                                  ////
2210
////      - Michael Unneback, unneback@opencores.org              ////
2211
////        ORSoC AB                                              ////
2212
////                                                              ////
2213
//////////////////////////////////////////////////////////////////////
2214
////                                                              ////
2215
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2216
////                                                              ////
2217
//// This source file may be used and distributed without         ////
2218
//// restriction provided that this copyright statement is not    ////
2219
//// removed from the file and that any derivative work contains  ////
2220
//// the original copyright notice and the associated disclaimer. ////
2221
////                                                              ////
2222
//// This source file is free software; you can redistribute it   ////
2223
//// and/or modify it under the terms of the GNU Lesser General   ////
2224
//// Public License as published by the Free Software Foundation; ////
2225
//// either version 2.1 of the License, or (at your option) any   ////
2226
//// later version.                                               ////
2227
////                                                              ////
2228
//// This source is distributed in the hope that it will be       ////
2229
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2230
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2231
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2232
//// details.                                                     ////
2233
////                                                              ////
2234
//// You should have received a copy of the GNU Lesser General    ////
2235
//// Public License along with this source; if not, download it   ////
2236
//// from http://www.opencores.org/lgpl.shtml                     ////
2237
////                                                              ////
2238
//////////////////////////////////////////////////////////////////////
2239
 
2240
// LFSR counter
2241 22 unneback
module vl_cnt_lfsr_ce_q_zq ( cke, q, zq, rst, clk);
2242
 
2243
   parameter length = 4;
2244
   input cke;
2245
   output [length:1] q;
2246
   output reg zq;
2247
   input rst;
2248
   input clk;
2249
 
2250
   parameter clear_value = 0;
2251
   parameter set_value = 1;
2252
   parameter wrap_value = 8;
2253
   parameter level1_value = 15;
2254
 
2255
   reg  [length:1] qi;
2256
   reg lfsr_fb;
2257
   wire [length:1] q_next;
2258
   reg [32:1] polynom;
2259
   integer i;
2260
 
2261
   always @ (qi)
2262
   begin
2263
        case (length)
2264
         2: polynom = 32'b11;                               // 0x3
2265
         3: polynom = 32'b110;                              // 0x6
2266
         4: polynom = 32'b1100;                             // 0xC
2267
         5: polynom = 32'b10100;                            // 0x14
2268
         6: polynom = 32'b110000;                           // 0x30
2269
         7: polynom = 32'b1100000;                          // 0x60
2270
         8: polynom = 32'b10111000;                         // 0xb8
2271
         9: polynom = 32'b100010000;                        // 0x110
2272
        10: polynom = 32'b1001000000;                       // 0x240
2273
        11: polynom = 32'b10100000000;                      // 0x500
2274
        12: polynom = 32'b100000101001;                     // 0x829
2275
        13: polynom = 32'b1000000001100;                    // 0x100C
2276
        14: polynom = 32'b10000000010101;                   // 0x2015
2277
        15: polynom = 32'b110000000000000;                  // 0x6000
2278
        16: polynom = 32'b1101000000001000;                 // 0xD008
2279
        17: polynom = 32'b10010000000000000;                // 0x12000
2280
        18: polynom = 32'b100000010000000000;               // 0x20400
2281
        19: polynom = 32'b1000000000000100011;              // 0x40023
2282
        20: polynom = 32'b10000010000000000000;             // 0x82000
2283
        21: polynom = 32'b101000000000000000000;            // 0x140000
2284
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2285
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2286
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2287
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2288
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2289
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2290
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2291
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2292
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2293
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2294
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2295
        default: polynom = 32'b0;
2296
        endcase
2297
        lfsr_fb = qi[length];
2298
        for (i=length-1; i>=1; i=i-1) begin
2299
            if (polynom[i])
2300
                lfsr_fb = lfsr_fb  ~^ qi[i];
2301
        end
2302
    end
2303
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2304
 
2305
   always @ (posedge clk or posedge rst)
2306
     if (rst)
2307
       qi <= {length{1'b0}};
2308
     else
2309
     if (cke)
2310
       qi <= q_next;
2311
 
2312
   assign q = qi;
2313
 
2314
 
2315
   always @ (posedge clk or posedge rst)
2316
     if (rst)
2317
       zq <= 1'b1;
2318
     else
2319
     if (cke)
2320
       zq <= q_next == {length{1'b0}};
2321
endmodule
2322
//////////////////////////////////////////////////////////////////////
2323
////                                                              ////
2324
////  Versatile counter                                           ////
2325
////                                                              ////
2326
////  Description                                                 ////
2327
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2328
////  counter                                                     ////
2329
////                                                              ////
2330
////  To Do:                                                      ////
2331
////   - add LFSR with more taps                                  ////
2332
////                                                              ////
2333
////  Author(s):                                                  ////
2334
////      - Michael Unneback, unneback@opencores.org              ////
2335
////        ORSoC AB                                              ////
2336
////                                                              ////
2337
//////////////////////////////////////////////////////////////////////
2338
////                                                              ////
2339
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2340
////                                                              ////
2341
//// This source file may be used and distributed without         ////
2342
//// restriction provided that this copyright statement is not    ////
2343
//// removed from the file and that any derivative work contains  ////
2344
//// the original copyright notice and the associated disclaimer. ////
2345
////                                                              ////
2346
//// This source file is free software; you can redistribute it   ////
2347
//// and/or modify it under the terms of the GNU Lesser General   ////
2348
//// Public License as published by the Free Software Foundation; ////
2349
//// either version 2.1 of the License, or (at your option) any   ////
2350
//// later version.                                               ////
2351
////                                                              ////
2352
//// This source is distributed in the hope that it will be       ////
2353
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2354
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2355
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2356
//// details.                                                     ////
2357
////                                                              ////
2358
//// You should have received a copy of the GNU Lesser General    ////
2359
//// Public License along with this source; if not, download it   ////
2360
//// from http://www.opencores.org/lgpl.shtml                     ////
2361
////                                                              ////
2362
//////////////////////////////////////////////////////////////////////
2363 6 unneback
 
2364
// LFSR counter
2365 18 unneback
module vl_cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk);
2366 6 unneback
 
2367
   parameter length = 4;
2368
   input cke;
2369
   input rew;
2370
   output reg level1;
2371
   input rst;
2372
   input clk;
2373
 
2374
   parameter clear_value = 0;
2375
   parameter set_value = 1;
2376
   parameter wrap_value = 8;
2377
   parameter level1_value = 15;
2378
 
2379 29 unneback
   wire clear;
2380 30 unneback
   assign clear = 1'b0;
2381 6 unneback
   reg  [length:1] qi;
2382
   reg lfsr_fb, lfsr_fb_rew;
2383
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2384
   reg [32:1] polynom_rew;
2385
   integer j;
2386
   reg [32:1] polynom;
2387
   integer i;
2388
 
2389
   always @ (qi)
2390
   begin
2391
        case (length)
2392
         2: polynom = 32'b11;                               // 0x3
2393
         3: polynom = 32'b110;                              // 0x6
2394
         4: polynom = 32'b1100;                             // 0xC
2395
         5: polynom = 32'b10100;                            // 0x14
2396
         6: polynom = 32'b110000;                           // 0x30
2397
         7: polynom = 32'b1100000;                          // 0x60
2398
         8: polynom = 32'b10111000;                         // 0xb8
2399
         9: polynom = 32'b100010000;                        // 0x110
2400
        10: polynom = 32'b1001000000;                       // 0x240
2401
        11: polynom = 32'b10100000000;                      // 0x500
2402
        12: polynom = 32'b100000101001;                     // 0x829
2403
        13: polynom = 32'b1000000001100;                    // 0x100C
2404
        14: polynom = 32'b10000000010101;                   // 0x2015
2405
        15: polynom = 32'b110000000000000;                  // 0x6000
2406
        16: polynom = 32'b1101000000001000;                 // 0xD008
2407
        17: polynom = 32'b10010000000000000;                // 0x12000
2408
        18: polynom = 32'b100000010000000000;               // 0x20400
2409
        19: polynom = 32'b1000000000000100011;              // 0x40023
2410
        20: polynom = 32'b10000010000000000000;             // 0x82000
2411
        21: polynom = 32'b101000000000000000000;            // 0x140000
2412
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2413
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2414
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2415
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2416
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2417
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2418
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2419
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2420
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2421
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2422
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2423
        default: polynom = 32'b0;
2424
        endcase
2425
        lfsr_fb = qi[length];
2426
        for (i=length-1; i>=1; i=i-1) begin
2427
            if (polynom[i])
2428
                lfsr_fb = lfsr_fb  ~^ qi[i];
2429
        end
2430
    end
2431
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2432
   always @ (qi)
2433
   begin
2434
        case (length)
2435
         2: polynom_rew = 32'b11;
2436
         3: polynom_rew = 32'b110;
2437
         4: polynom_rew = 32'b1100;
2438
         5: polynom_rew = 32'b10100;
2439
         6: polynom_rew = 32'b110000;
2440
         7: polynom_rew = 32'b1100000;
2441
         8: polynom_rew = 32'b10111000;
2442
         9: polynom_rew = 32'b100010000;
2443
        10: polynom_rew = 32'b1001000000;
2444
        11: polynom_rew = 32'b10100000000;
2445
        12: polynom_rew = 32'b100000101001;
2446
        13: polynom_rew = 32'b1000000001100;
2447
        14: polynom_rew = 32'b10000000010101;
2448
        15: polynom_rew = 32'b110000000000000;
2449
        16: polynom_rew = 32'b1101000000001000;
2450
        17: polynom_rew = 32'b10010000000000000;
2451
        18: polynom_rew = 32'b100000010000000000;
2452
        19: polynom_rew = 32'b1000000000000100011;
2453
        20: polynom_rew = 32'b10000010000000000000;
2454
        21: polynom_rew = 32'b101000000000000000000;
2455
        22: polynom_rew = 32'b1100000000000000000000;
2456
        23: polynom_rew = 32'b10000100000000000000000;
2457
        24: polynom_rew = 32'b111000010000000000000000;
2458
        25: polynom_rew = 32'b1001000000000000000000000;
2459
        26: polynom_rew = 32'b10000000000000000000100011;
2460
        27: polynom_rew = 32'b100000000000000000000010011;
2461
        28: polynom_rew = 32'b1100100000000000000000000000;
2462
        29: polynom_rew = 32'b10100000000000000000000000000;
2463
        30: polynom_rew = 32'b100000000000000000000000101001;
2464
        31: polynom_rew = 32'b1001000000000000000000000000000;
2465
        32: polynom_rew = 32'b10000000001000000000000000000011;
2466
        default: polynom_rew = 32'b0;
2467
        endcase
2468
        // rotate left
2469
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
2470
        lfsr_fb_rew = qi[length];
2471
        for (i=length-1; i>=1; i=i-1) begin
2472
            if (polynom_rew[i])
2473
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
2474
        end
2475
    end
2476
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
2477
   assign q_next = rew ? q_next_rew : q_next_fw;
2478
 
2479
   always @ (posedge clk or posedge rst)
2480
     if (rst)
2481
       qi <= {length{1'b0}};
2482
     else
2483
     if (cke)
2484
       qi <= q_next;
2485
 
2486
 
2487
 
2488
    always @ (posedge clk or posedge rst)
2489
    if (rst)
2490
        level1 <= 1'b0;
2491
    else
2492
    if (cke)
2493 29 unneback
    if (clear)
2494
        level1 <= 1'b0;
2495
    else if (q_next == level1_value)
2496 6 unneback
        level1 <= 1'b1;
2497
    else if (qi == level1_value & rew)
2498
        level1 <= 1'b0;
2499
endmodule
2500
//////////////////////////////////////////////////////////////////////
2501
////                                                              ////
2502
////  Versatile counter                                           ////
2503
////                                                              ////
2504
////  Description                                                 ////
2505
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2506
////  counter                                                     ////
2507
////                                                              ////
2508
////  To Do:                                                      ////
2509
////   - add LFSR with more taps                                  ////
2510
////                                                              ////
2511
////  Author(s):                                                  ////
2512
////      - Michael Unneback, unneback@opencores.org              ////
2513
////        ORSoC AB                                              ////
2514
////                                                              ////
2515
//////////////////////////////////////////////////////////////////////
2516
////                                                              ////
2517
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2518
////                                                              ////
2519
//// This source file may be used and distributed without         ////
2520
//// restriction provided that this copyright statement is not    ////
2521
//// removed from the file and that any derivative work contains  ////
2522
//// the original copyright notice and the associated disclaimer. ////
2523
////                                                              ////
2524
//// This source file is free software; you can redistribute it   ////
2525
//// and/or modify it under the terms of the GNU Lesser General   ////
2526
//// Public License as published by the Free Software Foundation; ////
2527
//// either version 2.1 of the License, or (at your option) any   ////
2528
//// later version.                                               ////
2529
////                                                              ////
2530
//// This source is distributed in the hope that it will be       ////
2531
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2532
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2533
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2534
//// details.                                                     ////
2535
////                                                              ////
2536
//// You should have received a copy of the GNU Lesser General    ////
2537
//// Public License along with this source; if not, download it   ////
2538
//// from http://www.opencores.org/lgpl.shtml                     ////
2539
////                                                              ////
2540
//////////////////////////////////////////////////////////////////////
2541
 
2542
// GRAY counter
2543 18 unneback
module vl_cnt_gray ( q, rst, clk);
2544 6 unneback
 
2545
   parameter length = 4;
2546
   output reg [length:1] q;
2547
   input rst;
2548
   input clk;
2549
 
2550
   parameter clear_value = 0;
2551
   parameter set_value = 1;
2552
   parameter wrap_value = 8;
2553
   parameter level1_value = 15;
2554
 
2555
   reg  [length:1] qi;
2556
   wire [length:1] q_next;
2557
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2558
 
2559
   always @ (posedge clk or posedge rst)
2560
     if (rst)
2561
       qi <= {length{1'b0}};
2562
     else
2563
       qi <= q_next;
2564
 
2565
   always @ (posedge clk or posedge rst)
2566
     if (rst)
2567
       q <= {length{1'b0}};
2568
     else
2569
         q <= (q_next>>1) ^ q_next;
2570
 
2571
endmodule
2572
//////////////////////////////////////////////////////////////////////
2573
////                                                              ////
2574
////  Versatile counter                                           ////
2575
////                                                              ////
2576
////  Description                                                 ////
2577
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2578
////  counter                                                     ////
2579
////                                                              ////
2580
////  To Do:                                                      ////
2581
////   - add LFSR with more taps                                  ////
2582
////                                                              ////
2583
////  Author(s):                                                  ////
2584
////      - Michael Unneback, unneback@opencores.org              ////
2585
////        ORSoC AB                                              ////
2586
////                                                              ////
2587
//////////////////////////////////////////////////////////////////////
2588
////                                                              ////
2589
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2590
////                                                              ////
2591
//// This source file may be used and distributed without         ////
2592
//// restriction provided that this copyright statement is not    ////
2593
//// removed from the file and that any derivative work contains  ////
2594
//// the original copyright notice and the associated disclaimer. ////
2595
////                                                              ////
2596
//// This source file is free software; you can redistribute it   ////
2597
//// and/or modify it under the terms of the GNU Lesser General   ////
2598
//// Public License as published by the Free Software Foundation; ////
2599
//// either version 2.1 of the License, or (at your option) any   ////
2600
//// later version.                                               ////
2601
////                                                              ////
2602
//// This source is distributed in the hope that it will be       ////
2603
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2604
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2605
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2606
//// details.                                                     ////
2607
////                                                              ////
2608
//// You should have received a copy of the GNU Lesser General    ////
2609
//// Public License along with this source; if not, download it   ////
2610
//// from http://www.opencores.org/lgpl.shtml                     ////
2611
////                                                              ////
2612
//////////////////////////////////////////////////////////////////////
2613
 
2614
// GRAY counter
2615 18 unneback
module vl_cnt_gray_ce ( cke, q, rst, clk);
2616 6 unneback
 
2617
   parameter length = 4;
2618
   input cke;
2619
   output reg [length:1] q;
2620
   input rst;
2621
   input clk;
2622
 
2623
   parameter clear_value = 0;
2624
   parameter set_value = 1;
2625
   parameter wrap_value = 8;
2626
   parameter level1_value = 15;
2627
 
2628
   reg  [length:1] qi;
2629
   wire [length:1] q_next;
2630
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2631
 
2632
   always @ (posedge clk or posedge rst)
2633
     if (rst)
2634
       qi <= {length{1'b0}};
2635
     else
2636
     if (cke)
2637
       qi <= q_next;
2638
 
2639
   always @ (posedge clk or posedge rst)
2640
     if (rst)
2641
       q <= {length{1'b0}};
2642
     else
2643
       if (cke)
2644
         q <= (q_next>>1) ^ q_next;
2645
 
2646
endmodule
2647
//////////////////////////////////////////////////////////////////////
2648
////                                                              ////
2649
////  Versatile counter                                           ////
2650
////                                                              ////
2651
////  Description                                                 ////
2652
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2653
////  counter                                                     ////
2654
////                                                              ////
2655
////  To Do:                                                      ////
2656
////   - add LFSR with more taps                                  ////
2657
////                                                              ////
2658
////  Author(s):                                                  ////
2659
////      - Michael Unneback, unneback@opencores.org              ////
2660
////        ORSoC AB                                              ////
2661
////                                                              ////
2662
//////////////////////////////////////////////////////////////////////
2663
////                                                              ////
2664
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2665
////                                                              ////
2666
//// This source file may be used and distributed without         ////
2667
//// restriction provided that this copyright statement is not    ////
2668
//// removed from the file and that any derivative work contains  ////
2669
//// the original copyright notice and the associated disclaimer. ////
2670
////                                                              ////
2671
//// This source file is free software; you can redistribute it   ////
2672
//// and/or modify it under the terms of the GNU Lesser General   ////
2673
//// Public License as published by the Free Software Foundation; ////
2674
//// either version 2.1 of the License, or (at your option) any   ////
2675
//// later version.                                               ////
2676
////                                                              ////
2677
//// This source is distributed in the hope that it will be       ////
2678
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2679
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2680
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2681
//// details.                                                     ////
2682
////                                                              ////
2683
//// You should have received a copy of the GNU Lesser General    ////
2684
//// Public License along with this source; if not, download it   ////
2685
//// from http://www.opencores.org/lgpl.shtml                     ////
2686
////                                                              ////
2687
//////////////////////////////////////////////////////////////////////
2688
 
2689
// GRAY counter
2690 18 unneback
module vl_cnt_gray_ce_bin ( cke, q, q_bin, rst, clk);
2691 6 unneback
 
2692
   parameter length = 4;
2693
   input cke;
2694
   output reg [length:1] q;
2695
   output [length:1] q_bin;
2696
   input rst;
2697
   input clk;
2698
 
2699
   parameter clear_value = 0;
2700
   parameter set_value = 1;
2701
   parameter wrap_value = 8;
2702
   parameter level1_value = 15;
2703
 
2704
   reg  [length:1] qi;
2705
   wire [length:1] q_next;
2706
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2707
 
2708
   always @ (posedge clk or posedge rst)
2709
     if (rst)
2710
       qi <= {length{1'b0}};
2711
     else
2712
     if (cke)
2713
       qi <= q_next;
2714
 
2715
   always @ (posedge clk or posedge rst)
2716
     if (rst)
2717
       q <= {length{1'b0}};
2718
     else
2719
       if (cke)
2720
         q <= (q_next>>1) ^ q_next;
2721
 
2722
   assign q_bin = qi;
2723
 
2724
endmodule
2725
//////////////////////////////////////////////////////////////////////
2726
////                                                              ////
2727
////  Versatile library, counters                                 ////
2728
////                                                              ////
2729
////  Description                                                 ////
2730
////  counters                                                    ////
2731
////                                                              ////
2732
////                                                              ////
2733
////  To Do:                                                      ////
2734
////   - add more counters                                        ////
2735
////                                                              ////
2736
////  Author(s):                                                  ////
2737
////      - Michael Unneback, unneback@opencores.org              ////
2738
////        ORSoC AB                                              ////
2739
////                                                              ////
2740
//////////////////////////////////////////////////////////////////////
2741
////                                                              ////
2742
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2743
////                                                              ////
2744
//// This source file may be used and distributed without         ////
2745
//// restriction provided that this copyright statement is not    ////
2746
//// removed from the file and that any derivative work contains  ////
2747
//// the original copyright notice and the associated disclaimer. ////
2748
////                                                              ////
2749
//// This source file is free software; you can redistribute it   ////
2750
//// and/or modify it under the terms of the GNU Lesser General   ////
2751
//// Public License as published by the Free Software Foundation; ////
2752
//// either version 2.1 of the License, or (at your option) any   ////
2753
//// later version.                                               ////
2754
////                                                              ////
2755
//// This source is distributed in the hope that it will be       ////
2756
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2757
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2758
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2759
//// details.                                                     ////
2760
////                                                              ////
2761
//// You should have received a copy of the GNU Lesser General    ////
2762
//// Public License along with this source; if not, download it   ////
2763
//// from http://www.opencores.org/lgpl.shtml                     ////
2764
////                                                              ////
2765
//////////////////////////////////////////////////////////////////////
2766
 
2767 18 unneback
module vl_cnt_shreg_wrap ( q, rst, clk);
2768 6 unneback
 
2769
   parameter length = 4;
2770
   output reg [0:length-1] q;
2771
   input rst;
2772
   input clk;