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1 6 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  Versatile library, clock and reset                          ////
4
////                                                              ////
5
////  Description                                                 ////
6
////  Logic related to clock and reset                            ////
7
////                                                              ////
8
////                                                              ////
9
////  To Do:                                                      ////
10
////   - add more different registers                             ////
11
////                                                              ////
12
////  Author(s):                                                  ////
13
////      - Michael Unneback, unneback@opencores.org              ////
14
////        ORSoC AB                                              ////
15
////                                                              ////
16
//////////////////////////////////////////////////////////////////////
17
////                                                              ////
18
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
19
////                                                              ////
20
//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
36
////                                                              ////
37
//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
 
43
// Global buffer
44
// usage:
45
// use to enable global buffers for high fan out signals such as clock and reset
46
 
47
`ifdef ACTEL
48
 
49
`timescale 1 ns/100 ps
50
// Version: 8.4 8.4.0.33
51
module gbuf(GL,CLK);
52
output GL;
53
input  CLK;
54
 
55
    wire GND;
56
 
57
    GND GND_1_net(.Y(GND));
58
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
59
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
60
 
61
endmodule
62
`timescale 1 ns/1 ns
63
module vl_gbuf ( i, o);
64
input i;
65
output o;
66
`ifdef SIM_GBUF
67
assign o=i;
68
`else
69
gbuf gbuf_i0 ( .CLK(i), .GL(o));
70
`endif
71
endmodule
72 33 unneback
 
73 6 unneback
`else
74 33 unneback
 
75 6 unneback
`ifdef ALTERA
76 21 unneback
//altera
77 33 unneback
module vl_gbuf ( i, o);
78
input i;
79
output o;
80
assign o = i;
81
endmodule
82
 
83 6 unneback
`else
84
 
85
`timescale 1 ns/100 ps
86
module vl_gbuf ( i, o);
87
input i;
88
output o;
89
assign o = i;
90
endmodule
91
`endif // ALTERA
92
`endif //ACTEL
93
 
94
// sync reset
95 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
96 6 unneback
// output active high global reset sync with two DFFs 
97
`timescale 1 ns/100 ps
98
module vl_sync_rst ( rst_n_i, rst_o, clk);
99
input rst_n_i, clk;
100
output rst_o;
101 18 unneback
reg [1:0] tmp;
102 6 unneback
always @ (posedge clk or negedge rst_n_i)
103
if (!rst_n_i)
104 17 unneback
        tmp <= 2'b11;
105 6 unneback
else
106 33 unneback
        tmp <= {1'b0,tmp[1]};
107 17 unneback
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
108 6 unneback
endmodule
109
 
110
// vl_pll
111
`ifdef ACTEL
112 32 unneback
///////////////////////////////////////////////////////////////////////////////
113 17 unneback
`timescale 1 ps/1 ps
114 6 unneback
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
115
parameter index = 0;
116
parameter number_of_clk = 1;
117 17 unneback
parameter period_time_0 = 20000;
118
parameter period_time_1 = 20000;
119
parameter period_time_2 = 20000;
120
parameter lock_delay = 2000000;
121 6 unneback
input clk_i, rst_n_i;
122
output lock;
123
output reg [0:number_of_clk-1] clk_o;
124
output [0:number_of_clk-1] rst_o;
125
 
126
`ifdef SIM_PLL
127
 
128
always
129
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
130
 
131
generate if (number_of_clk > 1)
132
always
133
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
134
endgenerate
135
 
136
generate if (number_of_clk > 2)
137
always
138
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
139
endgenerate
140
 
141
genvar i;
142
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
143
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
144
end
145
endgenerate
146
 
147
assign #lock_delay lock = rst_n_i;
148
 
149
endmodule
150
`else
151
generate if (number_of_clk==1 & index==0) begin
152
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
153
end
154
endgenerate // index==0
155
generate if (number_of_clk==1 & index==1) begin
156
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
157
end
158
endgenerate // index==1
159
generate if (number_of_clk==1 & index==2) begin
160
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
161
end
162
endgenerate // index==2
163
generate if (number_of_clk==1 & index==3) begin
164
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
165
end
166
endgenerate // index==0
167
 
168
generate if (number_of_clk==2 & index==0) begin
169
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
170
end
171
endgenerate // index==0
172
generate if (number_of_clk==2 & index==1) begin
173
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
174
end
175
endgenerate // index==1
176
generate if (number_of_clk==2 & index==2) begin
177
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
178
end
179
endgenerate // index==2
180
generate if (number_of_clk==2 & index==3) begin
181
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
182
end
183
endgenerate // index==0
184
 
185
generate if (number_of_clk==3 & index==0) begin
186
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
187
end
188
endgenerate // index==0
189
generate if (number_of_clk==3 & index==1) begin
190
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
191
end
192
endgenerate // index==1
193
generate if (number_of_clk==3 & index==2) begin
194
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
195
end
196
endgenerate // index==2
197
generate if (number_of_clk==3 & index==3) begin
198
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
199
end
200
endgenerate // index==0
201
 
202
genvar i;
203
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
204
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
205
end
206
endgenerate
207
endmodule
208
`endif
209 32 unneback
///////////////////////////////////////////////////////////////////////////////
210 6 unneback
 
211
`else
212
 
213 32 unneback
///////////////////////////////////////////////////////////////////////////////
214 6 unneback
`ifdef ALTERA
215
 
216 32 unneback
`timescale 1 ps/1 ps
217
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
218
parameter index = 0;
219
parameter number_of_clk = 1;
220
parameter period_time_0 = 20000;
221
parameter period_time_1 = 20000;
222
parameter period_time_2 = 20000;
223
parameter period_time_3 = 20000;
224
parameter period_time_4 = 20000;
225
parameter lock_delay = 2000000;
226
input clk_i, rst_n_i;
227
output lock;
228
output reg [0:number_of_clk-1] clk_o;
229
output [0:number_of_clk-1] rst_o;
230
 
231
`ifdef SIM_PLL
232
 
233
always
234
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
235
 
236
generate if (number_of_clk > 1)
237
always
238
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
239
endgenerate
240
 
241
generate if (number_of_clk > 2)
242
always
243
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
244
endgenerate
245
 
246 33 unneback
generate if (number_of_clk > 3)
247 32 unneback
always
248
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
249
endgenerate
250
 
251 33 unneback
generate if (number_of_clk > 4)
252 32 unneback
always
253
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
254
endgenerate
255
 
256
genvar i;
257
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
258
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
259
end
260
endgenerate
261
 
262 33 unneback
//assign #lock_delay lock = rst_n_i;
263
assign lock = rst_n_i;
264 32 unneback
 
265
endmodule
266 6 unneback
`else
267
 
268 33 unneback
`ifdef VL_PLL0
269
`ifdef VL_PLL0_CLK1
270
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
271
`endif
272
`ifdef VL_PLL0_CLK2
273
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
274
`endif
275
`ifdef VL_PLL0_CLK3
276
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
277
`endif
278
`ifdef VL_PLL0_CLK4
279
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
280
`endif
281
`ifdef VL_PLL0_CLK5
282
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
283
`endif
284
`endif
285 32 unneback
 
286 33 unneback
`ifdef VL_PLL1
287
`ifdef VL_PLL1_CLK1
288
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
289
`endif
290
`ifdef VL_PLL1_CLK2
291
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
292
`endif
293
`ifdef VL_PLL1_CLK3
294
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
295
`endif
296
`ifdef VL_PLL1_CLK4
297
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
298
`endif
299
`ifdef VL_PLL1_CLK5
300
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
301
`endif
302
`endif
303 32 unneback
 
304 33 unneback
`ifdef VL_PLL2
305
`ifdef VL_PLL2_CLK1
306
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
307
`endif
308
`ifdef VL_PLL2_CLK2
309
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
310
`endif
311
`ifdef VL_PLL2_CLK3
312
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
313
`endif
314
`ifdef VL_PLL2_CLK4
315
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
316
`endif
317
`ifdef VL_PLL2_CLK5
318
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
319
`endif
320
`endif
321 32 unneback
 
322 33 unneback
`ifdef VL_PLL3
323
`ifdef VL_PLL3_CLK1
324
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
325
`endif
326
`ifdef VL_PLL3_CLK2
327
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
328
`endif
329
`ifdef VL_PLL3_CLK3
330
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
331
`endif
332
`ifdef VL_PLL3_CLK4
333
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
334
`endif
335
`ifdef VL_PLL3_CLK5
336
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
337
`endif
338
`endif
339 32 unneback
 
340
genvar i;
341
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
342 33 unneback
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
343 32 unneback
end
344
endgenerate
345
endmodule
346
`endif
347
///////////////////////////////////////////////////////////////////////////////
348
 
349
`else
350
 
351 6 unneback
// generic PLL
352 17 unneback
`timescale 1 ps/1 ps
353 6 unneback
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
354
parameter index = 0;
355
parameter number_of_clk = 1;
356 17 unneback
parameter period_time_0 = 20000;
357
parameter period_time_1 = 20000;
358
parameter period_time_2 = 20000;
359 6 unneback
parameter lock_delay = 2000;
360
input clk_i, rst_n_i;
361
output lock;
362
output reg [0:number_of_clk-1] clk_o;
363
output [0:number_of_clk-1] rst_o;
364
 
365
always
366
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
367
 
368
generate if (number_of_clk > 1)
369
always
370
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
371
endgenerate
372
 
373
generate if (number_of_clk > 2)
374
always
375
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
376
endgenerate
377
 
378
genvar i;
379
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
380
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
381
end
382
endgenerate
383
 
384
assign #lock_delay lock = rst_n_i;
385
 
386
endmodule
387
 
388
`endif //altera
389 17 unneback
`endif //actel
390
//////////////////////////////////////////////////////////////////////
391 6 unneback
////                                                              ////
392
////  Versatile library, registers                                ////
393
////                                                              ////
394
////  Description                                                 ////
395
////  Different type of registers                                 ////
396
////                                                              ////
397
////                                                              ////
398
////  To Do:                                                      ////
399
////   - add more different registers                             ////
400
////                                                              ////
401
////  Author(s):                                                  ////
402
////      - Michael Unneback, unneback@opencores.org              ////
403
////        ORSoC AB                                              ////
404
////                                                              ////
405
//////////////////////////////////////////////////////////////////////
406
////                                                              ////
407
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
408
////                                                              ////
409
//// This source file may be used and distributed without         ////
410
//// restriction provided that this copyright statement is not    ////
411
//// removed from the file and that any derivative work contains  ////
412
//// the original copyright notice and the associated disclaimer. ////
413
////                                                              ////
414
//// This source file is free software; you can redistribute it   ////
415
//// and/or modify it under the terms of the GNU Lesser General   ////
416
//// Public License as published by the Free Software Foundation; ////
417
//// either version 2.1 of the License, or (at your option) any   ////
418
//// later version.                                               ////
419
////                                                              ////
420
//// This source is distributed in the hope that it will be       ////
421
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
422
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
423
//// PURPOSE.  See the GNU Lesser General Public License for more ////
424
//// details.                                                     ////
425
////                                                              ////
426
//// You should have received a copy of the GNU Lesser General    ////
427
//// Public License along with this source; if not, download it   ////
428
//// from http://www.opencores.org/lgpl.shtml                     ////
429
////                                                              ////
430
//////////////////////////////////////////////////////////////////////
431
 
432 18 unneback
module vl_dff ( d, q, clk, rst);
433 6 unneback
 
434
        parameter width = 1;
435
        parameter reset_value = 0;
436
 
437
        input [width-1:0] d;
438
        input clk, rst;
439
        output reg [width-1:0] q;
440
 
441
        always @ (posedge clk or posedge rst)
442
        if (rst)
443
                q <= reset_value;
444
        else
445
                q <= d;
446
 
447
endmodule
448
 
449 18 unneback
module vl_dff_array ( d, q, clk, rst);
450 6 unneback
 
451
        parameter width = 1;
452
        parameter depth = 2;
453
        parameter reset_value = 1'b0;
454
 
455
        input [width-1:0] d;
456
        input clk, rst;
457
        output [width-1:0] q;
458
        reg  [0:depth-1] q_tmp [width-1:0];
459
        integer i;
460
        always @ (posedge clk or posedge rst)
461
        if (rst) begin
462
            for (i=0;i<depth;i=i+1)
463
                q_tmp[i] <= {width{reset_value}};
464
        end else begin
465
            q_tmp[0] <= d;
466
            for (i=1;i<depth;i=i+1)
467
                q_tmp[i] <= q_tmp[i-1];
468
        end
469
 
470
    assign q = q_tmp[depth-1];
471
 
472
endmodule
473
 
474 18 unneback
module vl_dff_ce ( d, ce, q, clk, rst);
475 6 unneback
 
476
        parameter width = 1;
477
        parameter reset_value = 0;
478
 
479
        input [width-1:0] d;
480
        input ce, clk, rst;
481
        output reg [width-1:0] q;
482
 
483
        always @ (posedge clk or posedge rst)
484
        if (rst)
485
                q <= reset_value;
486
        else
487
                if (ce)
488
                        q <= d;
489
 
490
endmodule
491
 
492 18 unneback
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
493 8 unneback
 
494
        parameter width = 1;
495
        parameter reset_value = 0;
496
 
497
        input [width-1:0] d;
498 10 unneback
        input ce, clear, clk, rst;
499 8 unneback
        output reg [width-1:0] q;
500
 
501
        always @ (posedge clk or posedge rst)
502
        if (rst)
503
            q <= reset_value;
504
        else
505
            if (ce)
506
                if (clear)
507
                    q <= {width{1'b0}};
508
                else
509
                    q <= d;
510
 
511
endmodule
512
 
513 24 unneback
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
514
 
515
        parameter width = 1;
516
        parameter reset_value = 0;
517
 
518
        input [width-1:0] d;
519
        input ce, set, clk, rst;
520
        output reg [width-1:0] q;
521
 
522
        always @ (posedge clk or posedge rst)
523
        if (rst)
524
            q <= reset_value;
525
        else
526
            if (ce)
527
                if (set)
528
                    q <= {width{1'b1}};
529
                else
530
                    q <= d;
531
 
532
endmodule
533
 
534 29 unneback
module vl_spr ( sp, r, q, clk, rst);
535
 
536
        parameter width = 1;
537
        parameter reset_value = 0;
538
 
539
        input sp, r;
540
        output reg q;
541
        input clk, rst;
542
 
543
        always @ (posedge clk or posedge rst)
544
        if (rst)
545
            q <= reset_value;
546
        else
547
            if (sp)
548
                q <= 1'b1;
549
            else if (r)
550
                q <= 1'b0;
551
 
552
endmodule
553
 
554
module vl_srp ( s, rp, q, clk, rst);
555
 
556
        parameter width = 1;
557
        parameter reset_value = 0;
558
 
559
        input s, rp;
560
        output reg q;
561
        input clk, rst;
562
 
563
        always @ (posedge clk or posedge rst)
564
        if (rst)
565
            q <= reset_value;
566
        else
567
            if (rp)
568
                q <= 1'b0;
569
            else if (s)
570
                q <= 1'b1;
571
 
572
endmodule
573
 
574
 
575 6 unneback
`ifdef ALTERA
576
// megafunction wizard: %LPM_FF%
577
// GENERATION: STANDARD
578
// VERSION: WM1.0
579
// MODULE: lpm_ff 
580
 
581
// ============================================================
582
// File Name: dff_sr.v
583
// Megafunction Name(s):
584
//                      lpm_ff
585
//
586
// Simulation Library Files(s):
587
//                      lpm
588
// ============================================================
589
// ************************************************************
590
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
591
//
592
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
593
// ************************************************************
594
 
595
 
596
//Copyright (C) 1991-2010 Altera Corporation
597
//Your use of Altera Corporation's design tools, logic functions 
598
//and other software and tools, and its AMPP partner logic 
599
//functions, and any output files from any of the foregoing 
600
//(including device programming or simulation files), and any 
601
//associated documentation or information are expressly subject 
602
//to the terms and conditions of the Altera Program License 
603
//Subscription Agreement, Altera MegaCore Function License 
604
//Agreement, or other applicable license agreement, including, 
605
//without limitation, that your use is for the sole purpose of 
606
//programming logic devices manufactured by Altera and sold by 
607
//Altera or its authorized distributors.  Please refer to the 
608
//applicable agreement for further details.
609
 
610
 
611
// synopsys translate_off
612
`timescale 1 ps / 1 ps
613
// synopsys translate_on
614 18 unneback
module vl_dff_sr (
615 6 unneback
        aclr,
616
        aset,
617
        clock,
618
        data,
619
        q);
620
 
621
        input     aclr;
622
        input     aset;
623
        input     clock;
624
        input     data;
625
        output    q;
626
 
627
        wire [0:0] sub_wire0;
628
        wire [0:0] sub_wire1 = sub_wire0[0:0];
629
        wire  q = sub_wire1;
630
        wire  sub_wire2 = data;
631
        wire  sub_wire3 = sub_wire2;
632
 
633
        lpm_ff  lpm_ff_component (
634
                                .aclr (aclr),
635
                                .clock (clock),
636
                                .data (sub_wire3),
637
                                .aset (aset),
638
                                .q (sub_wire0)
639
                                // synopsys translate_off
640
                                ,
641
                                .aload (),
642
                                .enable (),
643
                                .sclr (),
644
                                .sload (),
645
                                .sset ()
646
                                // synopsys translate_on
647
                                );
648
        defparam
649
                lpm_ff_component.lpm_fftype = "DFF",
650
                lpm_ff_component.lpm_type = "LPM_FF",
651
                lpm_ff_component.lpm_width = 1;
652
 
653
 
654
endmodule
655
 
656
// ============================================================
657
// CNX file retrieval info
658
// ============================================================
659
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
660
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
661
// Retrieval info: PRIVATE: ASET NUMERIC "1"
662
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
663
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
664
// Retrieval info: PRIVATE: DFF NUMERIC "1"
665
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
666
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
667
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
668
// Retrieval info: PRIVATE: SSET NUMERIC "0"
669
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
670
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
671
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
672
// Retrieval info: PRIVATE: nBit NUMERIC "1"
673
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
674
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
675
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
676
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
677
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
678
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
679
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
680
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
681
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
682
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
683
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
684
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
685
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
686
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
687
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
688
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
689
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
690
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
691
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
692
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
693
// Retrieval info: LIB_FILE: lpm
694
 
695
 
696
`else
697
 
698
 
699 18 unneback
module vl_dff_sr ( aclr, aset, clock, data, q);
700 6 unneback
 
701
    input         aclr;
702
    input         aset;
703
    input         clock;
704
    input         data;
705
    output reg    q;
706
 
707
   always @ (posedge clock or posedge aclr or posedge aset)
708
     if (aclr)
709
       q <= 1'b0;
710
     else if (aset)
711
       q <= 1'b1;
712
     else
713
       q <= data;
714
 
715
endmodule
716
 
717
`endif
718
 
719
// LATCH
720
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
721
`ifdef ALTERA
722 18 unneback
module vl_latch ( d, le, q, clk);
723 6 unneback
input d, le;
724
output q;
725
input clk;
726
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
727
endmodule
728
`else
729
module latch ( d, le, q, clk);
730
input d, le;
731
output q;
732
input clk;/*
733
   always @ (posedge direction_set or posedge direction_clr)
734
     if (direction_clr)
735
       direction <= going_empty;
736
     else
737
       direction <= going_full;*/
738
endmodule
739 15 unneback
`endif
740
 
741 18 unneback
module vl_shreg ( d, q, clk, rst);
742 17 unneback
parameter depth = 10;
743
input d;
744
output q;
745
input clk, rst;
746
 
747
reg [1:depth] dffs;
748
 
749
always @ (posedge clk or posedge rst)
750
if (rst)
751
    dffs <= {depth{1'b0}};
752
else
753
    dffs <= {d,dffs[1:depth-1]};
754
assign q = dffs[depth];
755
endmodule
756
 
757 18 unneback
module vl_shreg_ce ( d, ce, q, clk, rst);
758 17 unneback
parameter depth = 10;
759
input d, ce;
760
output q;
761
input clk, rst;
762
 
763
reg [1:depth] dffs;
764
 
765
always @ (posedge clk or posedge rst)
766
if (rst)
767
    dffs <= {depth{1'b0}};
768
else
769
    if (ce)
770
        dffs <= {d,dffs[1:depth-1]};
771
assign q = dffs[depth];
772
endmodule
773
 
774 18 unneback
module vl_delay ( d, q, clk, rst);
775 15 unneback
parameter depth = 10;
776
input d;
777
output q;
778
input clk, rst;
779
 
780
reg [1:depth] dffs;
781
 
782
always @ (posedge clk or posedge rst)
783
if (rst)
784
    dffs <= {depth{1'b0}};
785
else
786
    dffs <= {d,dffs[1:depth-1]};
787
assign q = dffs[depth];
788 17 unneback
endmodule
789
 
790 18 unneback
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
791 17 unneback
parameter depth = 10;
792
input d;
793
output q, emptyflag;
794
input clk, rst;
795
 
796
reg [1:depth] dffs;
797
 
798
always @ (posedge clk or posedge rst)
799
if (rst)
800
    dffs <= {depth{1'b0}};
801
else
802
    dffs <= {d,dffs[1:depth-1]};
803
assign q = dffs[depth];
804
assign emptyflag = !(|dffs);
805
endmodule
806
//////////////////////////////////////////////////////////////////////
807 6 unneback
////                                                              ////
808 18 unneback
////  Logic functions                                             ////
809
////                                                              ////
810
////  Description                                                 ////
811
////  Logic functions such as multiplexers                        ////
812
////                                                              ////
813
////                                                              ////
814
////  To Do:                                                      ////
815
////   -                                                          ////
816
////                                                              ////
817
////  Author(s):                                                  ////
818
////      - Michael Unneback, unneback@opencores.org              ////
819
////        ORSoC AB                                              ////
820
////                                                              ////
821
//////////////////////////////////////////////////////////////////////
822
////                                                              ////
823
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
824
////                                                              ////
825
//// This source file may be used and distributed without         ////
826
//// restriction provided that this copyright statement is not    ////
827
//// removed from the file and that any derivative work contains  ////
828
//// the original copyright notice and the associated disclaimer. ////
829
////                                                              ////
830
//// This source file is free software; you can redistribute it   ////
831
//// and/or modify it under the terms of the GNU Lesser General   ////
832
//// Public License as published by the Free Software Foundation; ////
833
//// either version 2.1 of the License, or (at your option) any   ////
834
//// later version.                                               ////
835
////                                                              ////
836
//// This source is distributed in the hope that it will be       ////
837
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
838
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
839
//// PURPOSE.  See the GNU Lesser General Public License for more ////
840
//// details.                                                     ////
841
////                                                              ////
842
//// You should have received a copy of the GNU Lesser General    ////
843
//// Public License along with this source; if not, download it   ////
844
//// from http://www.opencores.org/lgpl.shtml                     ////
845
////                                                              ////
846
//////////////////////////////////////////////////////////////////////
847 36 unneback
module vl_mux_andor ( a, sel, dout);
848
 
849
parameter width = 32;
850
parameter nr_of_ports = 4;
851
 
852
input [nr_of_ports*width-1:0] a;
853
input [nr_of_ports-1:0] sel;
854
output reg [width-1:0] dout;
855
 
856 38 unneback
integer i,j;
857
 
858 36 unneback
always @ (a, sel)
859
begin
860
    dout = a[width-1:0] & {width{sel[0]}};
861
    for (i=nr_of_ports-2;i<nr_of_ports;i=i+1)
862 38 unneback
        for (j=0;j<32;j=j+1)
863
            dout[j] = (a[(i-1)*width + j] & sel[i]) | dout[j];
864 36 unneback
end
865
 
866
endmodule
867
 
868 34 unneback
module vl_mux2_andor ( a1, a0, sel, dout);
869 18 unneback
 
870 34 unneback
parameter width = 32;
871 35 unneback
localparam nr_of_ports = 2;
872 34 unneback
input [width-1:0] a1, a0;
873
input [nr_of_ports-1:0] sel;
874
output [width-1:0] dout;
875
 
876 36 unneback
vl_mux_andor
877 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
878 36 unneback
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
879 38 unneback
 
880 34 unneback
endmodule
881
 
882
module vl_mux3_andor ( a2, a1, a0, sel, dout);
883
 
884
parameter width = 32;
885 35 unneback
localparam nr_of_ports = 3;
886 34 unneback
input [width-1:0] a2, a1, a0;
887
input [nr_of_ports-1:0] sel;
888
output [width-1:0] dout;
889
 
890 36 unneback
vl_mux_andor
891 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
892 36 unneback
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
893 38 unneback
 
894 34 unneback
endmodule
895
 
896 18 unneback
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
897
 
898
parameter width = 32;
899 35 unneback
localparam nr_of_ports = 4;
900 18 unneback
input [width-1:0] a3, a2, a1, a0;
901
input [nr_of_ports-1:0] sel;
902 22 unneback
output [width-1:0] dout;
903 18 unneback
 
904 36 unneback
vl_mux_andor
905 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
906 36 unneback
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
907 18 unneback
 
908
endmodule
909
 
910
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
911
 
912
parameter width = 32;
913 35 unneback
localparam nr_of_ports = 5;
914 18 unneback
input [width-1:0] a4, a3, a2, a1, a0;
915
input [nr_of_ports-1:0] sel;
916 22 unneback
output [width-1:0] dout;
917 18 unneback
 
918 36 unneback
vl_mux_andor
919 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
920 36 unneback
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
921 18 unneback
 
922
endmodule
923
 
924
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
925
 
926
parameter width = 32;
927 35 unneback
localparam nr_of_ports = 6;
928 18 unneback
input [width-1:0] a5, a4, a3, a2, a1, a0;
929
input [nr_of_ports-1:0] sel;
930 22 unneback
output [width-1:0] dout;
931 18 unneback
 
932 36 unneback
vl_mux_andor
933 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
934 36 unneback
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
935 18 unneback
 
936
endmodule
937
//////////////////////////////////////////////////////////////////////
938
////                                                              ////
939 6 unneback
////  Versatile counter                                           ////
940
////                                                              ////
941
////  Description                                                 ////
942
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
943
////  counter                                                     ////
944
////                                                              ////
945
////  To Do:                                                      ////
946
////   - add LFSR with more taps                                  ////
947
////                                                              ////
948
////  Author(s):                                                  ////
949
////      - Michael Unneback, unneback@opencores.org              ////
950
////        ORSoC AB                                              ////
951
////                                                              ////
952
//////////////////////////////////////////////////////////////////////
953
////                                                              ////
954
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
955
////                                                              ////
956
//// This source file may be used and distributed without         ////
957
//// restriction provided that this copyright statement is not    ////
958
//// removed from the file and that any derivative work contains  ////
959
//// the original copyright notice and the associated disclaimer. ////
960
////                                                              ////
961
//// This source file is free software; you can redistribute it   ////
962
//// and/or modify it under the terms of the GNU Lesser General   ////
963
//// Public License as published by the Free Software Foundation; ////
964
//// either version 2.1 of the License, or (at your option) any   ////
965
//// later version.                                               ////
966
////                                                              ////
967
//// This source is distributed in the hope that it will be       ////
968
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
969
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
970
//// PURPOSE.  See the GNU Lesser General Public License for more ////
971
//// details.                                                     ////
972
////                                                              ////
973
//// You should have received a copy of the GNU Lesser General    ////
974
//// Public License along with this source; if not, download it   ////
975
//// from http://www.opencores.org/lgpl.shtml                     ////
976
////                                                              ////
977
//////////////////////////////////////////////////////////////////////
978
 
979
// binary counter
980 22 unneback
module vl_cnt_bin ( q, rst, clk);
981
 
982
   parameter length = 4;
983
   output [length:1] q;
984
   input rst;
985
   input clk;
986
 
987
   parameter clear_value = 0;
988
   parameter set_value = 1;
989
   parameter wrap_value = 0;
990
   parameter level1_value = 15;
991
 
992
   reg  [length:1] qi;
993
   wire [length:1] q_next;
994
   assign q_next = qi + {{length-1{1'b0}},1'b1};
995
 
996
   always @ (posedge clk or posedge rst)
997
     if (rst)
998
       qi <= {length{1'b0}};
999
     else
1000
       qi <= q_next;
1001
 
1002
   assign q = qi;
1003
 
1004
endmodule
1005
//////////////////////////////////////////////////////////////////////
1006
////                                                              ////
1007
////  Versatile counter                                           ////
1008
////                                                              ////
1009
////  Description                                                 ////
1010
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1011
////  counter                                                     ////
1012
////                                                              ////
1013
////  To Do:                                                      ////
1014
////   - add LFSR with more taps                                  ////
1015
////                                                              ////
1016
////  Author(s):                                                  ////
1017
////      - Michael Unneback, unneback@opencores.org              ////
1018
////        ORSoC AB                                              ////
1019
////                                                              ////
1020
//////////////////////////////////////////////////////////////////////
1021
////                                                              ////
1022
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1023
////                                                              ////
1024
//// This source file may be used and distributed without         ////
1025
//// restriction provided that this copyright statement is not    ////
1026
//// removed from the file and that any derivative work contains  ////
1027
//// the original copyright notice and the associated disclaimer. ////
1028
////                                                              ////
1029
//// This source file is free software; you can redistribute it   ////
1030
//// and/or modify it under the terms of the GNU Lesser General   ////
1031
//// Public License as published by the Free Software Foundation; ////
1032
//// either version 2.1 of the License, or (at your option) any   ////
1033
//// later version.                                               ////
1034
////                                                              ////
1035
//// This source is distributed in the hope that it will be       ////
1036
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1037
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1038
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1039
//// details.                                                     ////
1040
////                                                              ////
1041
//// You should have received a copy of the GNU Lesser General    ////
1042
//// Public License along with this source; if not, download it   ////
1043
//// from http://www.opencores.org/lgpl.shtml                     ////
1044
////                                                              ////
1045
//////////////////////////////////////////////////////////////////////
1046
 
1047
// binary counter
1048
module vl_cnt_bin_clear ( clear, q, rst, clk);
1049
 
1050
   parameter length = 4;
1051
   input clear;
1052
   output [length:1] q;
1053
   input rst;
1054
   input clk;
1055
 
1056
   parameter clear_value = 0;
1057
   parameter set_value = 1;
1058
   parameter wrap_value = 0;
1059
   parameter level1_value = 15;
1060
 
1061
   reg  [length:1] qi;
1062
   wire [length:1] q_next;
1063
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1064
 
1065
   always @ (posedge clk or posedge rst)
1066
     if (rst)
1067
       qi <= {length{1'b0}};
1068
     else
1069
       qi <= q_next;
1070
 
1071
   assign q = qi;
1072
 
1073
endmodule
1074
//////////////////////////////////////////////////////////////////////
1075
////                                                              ////
1076
////  Versatile counter                                           ////
1077
////                                                              ////
1078
////  Description                                                 ////
1079
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1080
////  counter                                                     ////
1081
////                                                              ////
1082
////  To Do:                                                      ////
1083
////   - add LFSR with more taps                                  ////
1084
////                                                              ////
1085
////  Author(s):                                                  ////
1086
////      - Michael Unneback, unneback@opencores.org              ////
1087
////        ORSoC AB                                              ////
1088
////                                                              ////
1089
//////////////////////////////////////////////////////////////////////
1090
////                                                              ////
1091
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1092
////                                                              ////
1093
//// This source file may be used and distributed without         ////
1094
//// restriction provided that this copyright statement is not    ////
1095
//// removed from the file and that any derivative work contains  ////
1096
//// the original copyright notice and the associated disclaimer. ////
1097
////                                                              ////
1098
//// This source file is free software; you can redistribute it   ////
1099
//// and/or modify it under the terms of the GNU Lesser General   ////
1100
//// Public License as published by the Free Software Foundation; ////
1101
//// either version 2.1 of the License, or (at your option) any   ////
1102
//// later version.                                               ////
1103
////                                                              ////
1104
//// This source is distributed in the hope that it will be       ////
1105
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1106
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1107
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1108
//// details.                                                     ////
1109
////                                                              ////
1110
//// You should have received a copy of the GNU Lesser General    ////
1111
//// Public License along with this source; if not, download it   ////
1112
//// from http://www.opencores.org/lgpl.shtml                     ////
1113
////                                                              ////
1114
//////////////////////////////////////////////////////////////////////
1115
 
1116
// binary counter
1117 18 unneback
module vl_cnt_bin_ce ( cke, q, rst, clk);
1118 6 unneback
 
1119
   parameter length = 4;
1120
   input cke;
1121
   output [length:1] q;
1122
   input rst;
1123
   input clk;
1124
 
1125
   parameter clear_value = 0;
1126
   parameter set_value = 1;
1127
   parameter wrap_value = 0;
1128
   parameter level1_value = 15;
1129
 
1130
   reg  [length:1] qi;
1131
   wire [length:1] q_next;
1132
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1133
 
1134
   always @ (posedge clk or posedge rst)
1135
     if (rst)
1136
       qi <= {length{1'b0}};
1137
     else
1138
     if (cke)
1139
       qi <= q_next;
1140
 
1141
   assign q = qi;
1142
 
1143
endmodule
1144
//////////////////////////////////////////////////////////////////////
1145
////                                                              ////
1146
////  Versatile counter                                           ////
1147
////                                                              ////
1148
////  Description                                                 ////
1149
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1150
////  counter                                                     ////
1151
////                                                              ////
1152
////  To Do:                                                      ////
1153
////   - add LFSR with more taps                                  ////
1154
////                                                              ////
1155
////  Author(s):                                                  ////
1156
////      - Michael Unneback, unneback@opencores.org              ////
1157
////        ORSoC AB                                              ////
1158
////                                                              ////
1159
//////////////////////////////////////////////////////////////////////
1160
////                                                              ////
1161
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1162
////                                                              ////
1163
//// This source file may be used and distributed without         ////
1164
//// restriction provided that this copyright statement is not    ////
1165
//// removed from the file and that any derivative work contains  ////
1166
//// the original copyright notice and the associated disclaimer. ////
1167
////                                                              ////
1168
//// This source file is free software; you can redistribute it   ////
1169
//// and/or modify it under the terms of the GNU Lesser General   ////
1170
//// Public License as published by the Free Software Foundation; ////
1171
//// either version 2.1 of the License, or (at your option) any   ////
1172
//// later version.                                               ////
1173
////                                                              ////
1174
//// This source is distributed in the hope that it will be       ////
1175
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1176
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1177
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1178
//// details.                                                     ////
1179
////                                                              ////
1180
//// You should have received a copy of the GNU Lesser General    ////
1181
//// Public License along with this source; if not, download it   ////
1182
//// from http://www.opencores.org/lgpl.shtml                     ////
1183
////                                                              ////
1184
//////////////////////////////////////////////////////////////////////
1185
 
1186
// binary counter
1187 18 unneback
module vl_cnt_bin_ce_clear ( clear, cke, q, rst, clk);
1188 6 unneback
 
1189
   parameter length = 4;
1190
   input clear;
1191
   input cke;
1192
   output [length:1] q;
1193
   input rst;
1194
   input clk;
1195
 
1196
   parameter clear_value = 0;
1197
   parameter set_value = 1;
1198
   parameter wrap_value = 0;
1199
   parameter level1_value = 15;
1200
 
1201
   reg  [length:1] qi;
1202
   wire [length:1] q_next;
1203
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1204
 
1205
   always @ (posedge clk or posedge rst)
1206
     if (rst)
1207
       qi <= {length{1'b0}};
1208
     else
1209
     if (cke)
1210
       qi <= q_next;
1211
 
1212
   assign q = qi;
1213
 
1214
endmodule
1215
//////////////////////////////////////////////////////////////////////
1216
////                                                              ////
1217
////  Versatile counter                                           ////
1218
////                                                              ////
1219
////  Description                                                 ////
1220
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1221
////  counter                                                     ////
1222
////                                                              ////
1223
////  To Do:                                                      ////
1224
////   - add LFSR with more taps                                  ////
1225
////                                                              ////
1226
////  Author(s):                                                  ////
1227
////      - Michael Unneback, unneback@opencores.org              ////
1228
////        ORSoC AB                                              ////
1229
////                                                              ////
1230
//////////////////////////////////////////////////////////////////////
1231
////                                                              ////
1232
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1233
////                                                              ////
1234
//// This source file may be used and distributed without         ////
1235
//// restriction provided that this copyright statement is not    ////
1236
//// removed from the file and that any derivative work contains  ////
1237
//// the original copyright notice and the associated disclaimer. ////
1238
////                                                              ////
1239
//// This source file is free software; you can redistribute it   ////
1240
//// and/or modify it under the terms of the GNU Lesser General   ////
1241
//// Public License as published by the Free Software Foundation; ////
1242
//// either version 2.1 of the License, or (at your option) any   ////
1243
//// later version.                                               ////
1244
////                                                              ////
1245
//// This source is distributed in the hope that it will be       ////
1246
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1247
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1248
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1249
//// details.                                                     ////
1250
////                                                              ////
1251
//// You should have received a copy of the GNU Lesser General    ////
1252
//// Public License along with this source; if not, download it   ////
1253
//// from http://www.opencores.org/lgpl.shtml                     ////
1254
////                                                              ////
1255
//////////////////////////////////////////////////////////////////////
1256
 
1257
// binary counter
1258 29 unneback
module vl_cnt_bin_ce_clear_l1_l2 ( clear, cke, q, level1, level2, rst, clk);
1259
 
1260
   parameter length = 4;
1261
   input clear;
1262
   input cke;
1263
   output [length:1] q;
1264
   output reg level1;
1265
   output reg level2;
1266
   input rst;
1267
   input clk;
1268
 
1269
   parameter clear_value = 0;
1270
   parameter set_value = 1;
1271 30 unneback
   parameter wrap_value = 15;
1272
   parameter level1_value = 8;
1273
   parameter level2_value = 15;
1274 29 unneback
 
1275
   wire rew;
1276 30 unneback
   assign rew = 1'b0;
1277 29 unneback
   reg  [length:1] qi;
1278
   wire [length:1] q_next;
1279
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1280
 
1281
   always @ (posedge clk or posedge rst)
1282
     if (rst)
1283
       qi <= {length{1'b0}};
1284
     else
1285
     if (cke)
1286
       qi <= q_next;
1287
 
1288
   assign q = qi;
1289
 
1290
 
1291
    always @ (posedge clk or posedge rst)
1292
    if (rst)
1293
        level1 <= 1'b0;
1294
    else
1295
    if (cke)
1296
    if (clear)
1297
        level1 <= 1'b0;
1298
    else if (q_next == level1_value)
1299
        level1 <= 1'b1;
1300
    else if (qi == level1_value & rew)
1301
        level1 <= 1'b0;
1302
 
1303
    always @ (posedge clk or posedge rst)
1304
    if (rst)
1305
        level2 <= 1'b0;
1306
    else
1307
    if (cke)
1308
    if (clear)
1309
        level2 <= 1'b0;
1310
    else if (q_next == level2_value)
1311
        level2 <= 1'b1;
1312
    else if (qi == level2_value & rew)
1313
        level2 <= 1'b0;
1314
endmodule
1315
//////////////////////////////////////////////////////////////////////
1316
////                                                              ////
1317
////  Versatile counter                                           ////
1318
////                                                              ////
1319
////  Description                                                 ////
1320
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1321
////  counter                                                     ////
1322
////                                                              ////
1323
////  To Do:                                                      ////
1324
////   - add LFSR with more taps                                  ////
1325
////                                                              ////
1326
////  Author(s):                                                  ////
1327
////      - Michael Unneback, unneback@opencores.org              ////
1328
////        ORSoC AB                                              ////
1329
////                                                              ////
1330
//////////////////////////////////////////////////////////////////////
1331
////                                                              ////
1332
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1333
////                                                              ////
1334
//// This source file may be used and distributed without         ////
1335
//// restriction provided that this copyright statement is not    ////
1336
//// removed from the file and that any derivative work contains  ////
1337
//// the original copyright notice and the associated disclaimer. ////
1338
////                                                              ////
1339
//// This source file is free software; you can redistribute it   ////
1340
//// and/or modify it under the terms of the GNU Lesser General   ////
1341
//// Public License as published by the Free Software Foundation; ////
1342
//// either version 2.1 of the License, or (at your option) any   ////
1343
//// later version.                                               ////
1344
////                                                              ////
1345
//// This source is distributed in the hope that it will be       ////
1346
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1347
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1348
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1349
//// details.                                                     ////
1350
////                                                              ////
1351
//// You should have received a copy of the GNU Lesser General    ////
1352
//// Public License along with this source; if not, download it   ////
1353
//// from http://www.opencores.org/lgpl.shtml                     ////
1354
////                                                              ////
1355
//////////////////////////////////////////////////////////////////////
1356
 
1357
// binary counter
1358 18 unneback
module vl_cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk);
1359 6 unneback
 
1360
   parameter length = 4;
1361
   input clear;
1362
   input set;
1363
   input cke;
1364
   input rew;
1365
   output [length:1] q;
1366
   input rst;
1367
   input clk;
1368
 
1369
   parameter clear_value = 0;
1370
   parameter set_value = 1;
1371
   parameter wrap_value = 0;
1372
   parameter level1_value = 15;
1373
 
1374
   reg  [length:1] qi;
1375
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1376
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
1377
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
1378
   assign q_next = rew ? q_next_rew : q_next_fw;
1379
 
1380
   always @ (posedge clk or posedge rst)
1381
     if (rst)
1382
       qi <= {length{1'b0}};
1383
     else
1384
     if (cke)
1385
       qi <= q_next;
1386
 
1387
   assign q = qi;
1388
 
1389
endmodule
1390
//////////////////////////////////////////////////////////////////////
1391
////                                                              ////
1392
////  Versatile counter                                           ////
1393
////                                                              ////
1394
////  Description                                                 ////
1395
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1396
////  counter                                                     ////
1397
////                                                              ////
1398
////  To Do:                                                      ////
1399
////   - add LFSR with more taps                                  ////
1400
////                                                              ////
1401
////  Author(s):                                                  ////
1402
////      - Michael Unneback, unneback@opencores.org              ////
1403
////        ORSoC AB                                              ////
1404
////                                                              ////
1405
//////////////////////////////////////////////////////////////////////
1406
////                                                              ////
1407
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1408
////                                                              ////
1409
//// This source file may be used and distributed without         ////
1410
//// restriction provided that this copyright statement is not    ////
1411
//// removed from the file and that any derivative work contains  ////
1412
//// the original copyright notice and the associated disclaimer. ////
1413
////                                                              ////
1414
//// This source file is free software; you can redistribute it   ////
1415
//// and/or modify it under the terms of the GNU Lesser General   ////
1416
//// Public License as published by the Free Software Foundation; ////
1417
//// either version 2.1 of the License, or (at your option) any   ////
1418
//// later version.                                               ////
1419
////                                                              ////
1420
//// This source is distributed in the hope that it will be       ////
1421
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1422
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1423
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1424
//// details.                                                     ////
1425
////                                                              ////
1426
//// You should have received a copy of the GNU Lesser General    ////
1427
//// Public License along with this source; if not, download it   ////
1428
//// from http://www.opencores.org/lgpl.shtml                     ////
1429
////                                                              ////
1430
//////////////////////////////////////////////////////////////////////
1431
 
1432
// binary counter
1433 18 unneback
module vl_cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk);
1434 6 unneback
 
1435
   parameter length = 4;
1436
   input cke;
1437
   input rew;
1438
   output reg level1;
1439
   input rst;
1440
   input clk;
1441
 
1442
   parameter clear_value = 0;
1443
   parameter set_value = 1;
1444
   parameter wrap_value = 1;
1445
   parameter level1_value = 15;
1446
 
1447 29 unneback
   wire clear;
1448 30 unneback
   assign clear = 1'b0;
1449 6 unneback
   reg  [length:1] qi;
1450
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1451
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1452
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1453
   assign q_next = rew ? q_next_rew : q_next_fw;
1454
 
1455
   always @ (posedge clk or posedge rst)
1456
     if (rst)
1457
       qi <= {length{1'b0}};
1458
     else
1459
     if (cke)
1460
       qi <= q_next;
1461
 
1462
 
1463
 
1464
    always @ (posedge clk or posedge rst)
1465
    if (rst)
1466
        level1 <= 1'b0;
1467
    else
1468
    if (cke)
1469 29 unneback
    if (clear)
1470
        level1 <= 1'b0;
1471
    else if (q_next == level1_value)
1472 6 unneback
        level1 <= 1'b1;
1473
    else if (qi == level1_value & rew)
1474
        level1 <= 1'b0;
1475
endmodule
1476
//////////////////////////////////////////////////////////////////////
1477
////                                                              ////
1478
////  Versatile counter                                           ////
1479
////                                                              ////
1480
////  Description                                                 ////
1481
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1482
////  counter                                                     ////
1483
////                                                              ////
1484
////  To Do:                                                      ////
1485
////   - add LFSR with more taps                                  ////
1486
////                                                              ////
1487
////  Author(s):                                                  ////
1488
////      - Michael Unneback, unneback@opencores.org              ////
1489
////        ORSoC AB                                              ////
1490
////                                                              ////
1491
//////////////////////////////////////////////////////////////////////
1492
////                                                              ////
1493
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1494
////                                                              ////
1495
//// This source file may be used and distributed without         ////
1496
//// restriction provided that this copyright statement is not    ////
1497
//// removed from the file and that any derivative work contains  ////
1498
//// the original copyright notice and the associated disclaimer. ////
1499
////                                                              ////
1500
//// This source file is free software; you can redistribute it   ////
1501
//// and/or modify it under the terms of the GNU Lesser General   ////
1502
//// Public License as published by the Free Software Foundation; ////
1503
//// either version 2.1 of the License, or (at your option) any   ////
1504
//// later version.                                               ////
1505
////                                                              ////
1506
//// This source is distributed in the hope that it will be       ////
1507
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1508
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1509
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1510
//// details.                                                     ////
1511
////                                                              ////
1512
//// You should have received a copy of the GNU Lesser General    ////
1513
//// Public License along with this source; if not, download it   ////
1514
//// from http://www.opencores.org/lgpl.shtml                     ////
1515
////                                                              ////
1516
//////////////////////////////////////////////////////////////////////
1517
 
1518 25 unneback
// binary counter
1519
module vl_cnt_bin_ce_rew_zq_l1 ( cke, rew, zq, level1, rst, clk);
1520
 
1521
   parameter length = 4;
1522
   input cke;
1523
   input rew;
1524
   output reg zq;
1525
   output reg level1;
1526
   input rst;
1527
   input clk;
1528
 
1529
   parameter clear_value = 0;
1530
   parameter set_value = 1;
1531
   parameter wrap_value = 1;
1532
   parameter level1_value = 15;
1533
 
1534 29 unneback
   wire clear;
1535 30 unneback
   assign clear = 1'b0;
1536 25 unneback
   reg  [length:1] qi;
1537
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1538
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1539
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1540
   assign q_next = rew ? q_next_rew : q_next_fw;
1541
 
1542
   always @ (posedge clk or posedge rst)
1543
     if (rst)
1544
       qi <= {length{1'b0}};
1545
     else
1546
     if (cke)
1547
       qi <= q_next;
1548
 
1549
 
1550
 
1551
   always @ (posedge clk or posedge rst)
1552
     if (rst)
1553
       zq <= 1'b1;
1554
     else
1555
     if (cke)
1556
       zq <= q_next == {length{1'b0}};
1557
 
1558
    always @ (posedge clk or posedge rst)
1559
    if (rst)
1560
        level1 <= 1'b0;
1561
    else
1562
    if (cke)
1563 29 unneback
    if (clear)
1564
        level1 <= 1'b0;
1565
    else if (q_next == level1_value)
1566 25 unneback
        level1 <= 1'b1;
1567
    else if (qi == level1_value & rew)
1568
        level1 <= 1'b0;
1569
endmodule
1570
//////////////////////////////////////////////////////////////////////
1571
////                                                              ////
1572
////  Versatile counter                                           ////
1573
////                                                              ////
1574
////  Description                                                 ////
1575
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1576
////  counter                                                     ////
1577
////                                                              ////
1578
////  To Do:                                                      ////
1579
////   - add LFSR with more taps                                  ////
1580
////                                                              ////
1581
////  Author(s):                                                  ////
1582
////      - Michael Unneback, unneback@opencores.org              ////
1583
////        ORSoC AB                                              ////
1584
////                                                              ////
1585
//////////////////////////////////////////////////////////////////////
1586
////                                                              ////
1587
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1588
////                                                              ////
1589
//// This source file may be used and distributed without         ////
1590
//// restriction provided that this copyright statement is not    ////
1591
//// removed from the file and that any derivative work contains  ////
1592
//// the original copyright notice and the associated disclaimer. ////
1593
////                                                              ////
1594
//// This source file is free software; you can redistribute it   ////
1595
//// and/or modify it under the terms of the GNU Lesser General   ////
1596
//// Public License as published by the Free Software Foundation; ////
1597
//// either version 2.1 of the License, or (at your option) any   ////
1598
//// later version.                                               ////
1599
////                                                              ////
1600
//// This source is distributed in the hope that it will be       ////
1601
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1602
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1603
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1604
//// details.                                                     ////
1605
////                                                              ////
1606
//// You should have received a copy of the GNU Lesser General    ////
1607
//// Public License along with this source; if not, download it   ////
1608
//// from http://www.opencores.org/lgpl.shtml                     ////
1609
////                                                              ////
1610
//////////////////////////////////////////////////////////////////////
1611
 
1612
// binary counter
1613
module vl_cnt_bin_ce_rew_q_zq_l1 ( cke, rew, q, zq, level1, rst, clk);
1614
 
1615
   parameter length = 4;
1616
   input cke;
1617
   input rew;
1618
   output [length:1] q;
1619
   output reg zq;
1620
   output reg level1;
1621
   input rst;
1622
   input clk;
1623
 
1624
   parameter clear_value = 0;
1625
   parameter set_value = 1;
1626
   parameter wrap_value = 1;
1627
   parameter level1_value = 15;
1628
 
1629 29 unneback
   wire clear;
1630 30 unneback
   assign clear = 1'b0;
1631 25 unneback
   reg  [length:1] qi;
1632
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1633
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1634
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1635
   assign q_next = rew ? q_next_rew : q_next_fw;
1636
 
1637
   always @ (posedge clk or posedge rst)
1638
     if (rst)
1639
       qi <= {length{1'b0}};
1640
     else
1641
     if (cke)
1642
       qi <= q_next;
1643
 
1644
   assign q = qi;
1645
 
1646
 
1647
   always @ (posedge clk or posedge rst)
1648
     if (rst)
1649
       zq <= 1'b1;
1650
     else
1651
     if (cke)
1652
       zq <= q_next == {length{1'b0}};
1653
 
1654
    always @ (posedge clk or posedge rst)
1655
    if (rst)
1656
        level1 <= 1'b0;
1657
    else
1658
    if (cke)
1659 29 unneback
    if (clear)
1660
        level1 <= 1'b0;
1661
    else if (q_next == level1_value)
1662 25 unneback
        level1 <= 1'b1;
1663
    else if (qi == level1_value & rew)
1664
        level1 <= 1'b0;
1665
endmodule
1666
//////////////////////////////////////////////////////////////////////
1667
////                                                              ////
1668
////  Versatile counter                                           ////
1669
////                                                              ////
1670
////  Description                                                 ////
1671
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1672
////  counter                                                     ////
1673
////                                                              ////
1674
////  To Do:                                                      ////
1675
////   - add LFSR with more taps                                  ////
1676
////                                                              ////
1677
////  Author(s):                                                  ////
1678
////      - Michael Unneback, unneback@opencores.org              ////
1679
////        ORSoC AB                                              ////
1680
////                                                              ////
1681
//////////////////////////////////////////////////////////////////////
1682
////                                                              ////
1683
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1684
////                                                              ////
1685
//// This source file may be used and distributed without         ////
1686
//// restriction provided that this copyright statement is not    ////
1687
//// removed from the file and that any derivative work contains  ////
1688
//// the original copyright notice and the associated disclaimer. ////
1689
////                                                              ////
1690
//// This source file is free software; you can redistribute it   ////
1691
//// and/or modify it under the terms of the GNU Lesser General   ////
1692
//// Public License as published by the Free Software Foundation; ////
1693
//// either version 2.1 of the License, or (at your option) any   ////
1694
//// later version.                                               ////
1695
////                                                              ////
1696
//// This source is distributed in the hope that it will be       ////
1697
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1698
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1699
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1700
//// details.                                                     ////
1701
////                                                              ////
1702
//// You should have received a copy of the GNU Lesser General    ////
1703
//// Public License along with this source; if not, download it   ////
1704
//// from http://www.opencores.org/lgpl.shtml                     ////
1705
////                                                              ////
1706
//////////////////////////////////////////////////////////////////////
1707
 
1708 6 unneback
// LFSR counter
1709 18 unneback
module vl_cnt_lfsr_zq ( zq, rst, clk);
1710 6 unneback
 
1711
   parameter length = 4;
1712
   output reg zq;
1713
   input rst;
1714
   input clk;
1715
 
1716
   parameter clear_value = 0;
1717
   parameter set_value = 1;
1718
   parameter wrap_value = 8;
1719
   parameter level1_value = 15;
1720
 
1721
   reg  [length:1] qi;
1722
   reg lfsr_fb;
1723
   wire [length:1] q_next;
1724
   reg [32:1] polynom;
1725
   integer i;
1726
 
1727
   always @ (qi)
1728
   begin
1729
        case (length)
1730
         2: polynom = 32'b11;                               // 0x3
1731
         3: polynom = 32'b110;                              // 0x6
1732
         4: polynom = 32'b1100;                             // 0xC
1733
         5: polynom = 32'b10100;                            // 0x14
1734
         6: polynom = 32'b110000;                           // 0x30
1735
         7: polynom = 32'b1100000;                          // 0x60
1736
         8: polynom = 32'b10111000;                         // 0xb8
1737
         9: polynom = 32'b100010000;                        // 0x110
1738
        10: polynom = 32'b1001000000;                       // 0x240
1739
        11: polynom = 32'b10100000000;                      // 0x500
1740
        12: polynom = 32'b100000101001;                     // 0x829
1741
        13: polynom = 32'b1000000001100;                    // 0x100C
1742
        14: polynom = 32'b10000000010101;                   // 0x2015
1743
        15: polynom = 32'b110000000000000;                  // 0x6000
1744
        16: polynom = 32'b1101000000001000;                 // 0xD008
1745
        17: polynom = 32'b10010000000000000;                // 0x12000
1746
        18: polynom = 32'b100000010000000000;               // 0x20400
1747
        19: polynom = 32'b1000000000000100011;              // 0x40023
1748 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
1749 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
1750
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1751
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1752
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1753
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1754
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1755
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1756
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1757
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1758
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1759
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1760
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1761
        default: polynom = 32'b0;
1762
        endcase
1763
        lfsr_fb = qi[length];
1764
        for (i=length-1; i>=1; i=i-1) begin
1765
            if (polynom[i])
1766
                lfsr_fb = lfsr_fb  ~^ qi[i];
1767
        end
1768
    end
1769
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1770
 
1771
   always @ (posedge clk or posedge rst)
1772
     if (rst)
1773
       qi <= {length{1'b0}};
1774
     else
1775
       qi <= q_next;
1776
 
1777
 
1778
 
1779
   always @ (posedge clk or posedge rst)
1780
     if (rst)
1781
       zq <= 1'b1;
1782
     else
1783
       zq <= q_next == {length{1'b0}};
1784
endmodule
1785
//////////////////////////////////////////////////////////////////////
1786
////                                                              ////
1787
////  Versatile counter                                           ////
1788
////                                                              ////
1789
////  Description                                                 ////
1790
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1791
////  counter                                                     ////
1792
////                                                              ////
1793
////  To Do:                                                      ////
1794
////   - add LFSR with more taps                                  ////
1795
////                                                              ////
1796
////  Author(s):                                                  ////
1797
////      - Michael Unneback, unneback@opencores.org              ////
1798
////        ORSoC AB                                              ////
1799
////                                                              ////
1800
//////////////////////////////////////////////////////////////////////
1801
////                                                              ////
1802
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1803
////                                                              ////
1804
//// This source file may be used and distributed without         ////
1805
//// restriction provided that this copyright statement is not    ////
1806
//// removed from the file and that any derivative work contains  ////
1807
//// the original copyright notice and the associated disclaimer. ////
1808
////                                                              ////
1809
//// This source file is free software; you can redistribute it   ////
1810
//// and/or modify it under the terms of the GNU Lesser General   ////
1811
//// Public License as published by the Free Software Foundation; ////
1812
//// either version 2.1 of the License, or (at your option) any   ////
1813
//// later version.                                               ////
1814
////                                                              ////
1815
//// This source is distributed in the hope that it will be       ////
1816
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1817
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1818
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1819
//// details.                                                     ////
1820
////                                                              ////
1821
//// You should have received a copy of the GNU Lesser General    ////
1822
//// Public License along with this source; if not, download it   ////
1823
//// from http://www.opencores.org/lgpl.shtml                     ////
1824
////                                                              ////
1825
//////////////////////////////////////////////////////////////////////
1826
 
1827
// LFSR counter
1828 18 unneback
module vl_cnt_lfsr_ce_zq ( cke, zq, rst, clk);
1829 6 unneback
 
1830
   parameter length = 4;
1831
   input cke;
1832
   output reg zq;
1833
   input rst;
1834
   input clk;
1835
 
1836
   parameter clear_value = 0;
1837
   parameter set_value = 1;
1838
   parameter wrap_value = 8;
1839
   parameter level1_value = 15;
1840
 
1841
   reg  [length:1] qi;
1842
   reg lfsr_fb;
1843
   wire [length:1] q_next;
1844
   reg [32:1] polynom;
1845
   integer i;
1846
 
1847
   always @ (qi)
1848
   begin
1849
        case (length)
1850
         2: polynom = 32'b11;                               // 0x3
1851
         3: polynom = 32'b110;                              // 0x6
1852
         4: polynom = 32'b1100;                             // 0xC
1853
         5: polynom = 32'b10100;                            // 0x14
1854
         6: polynom = 32'b110000;                           // 0x30
1855
         7: polynom = 32'b1100000;                          // 0x60
1856
         8: polynom = 32'b10111000;                         // 0xb8
1857
         9: polynom = 32'b100010000;                        // 0x110
1858
        10: polynom = 32'b1001000000;                       // 0x240
1859
        11: polynom = 32'b10100000000;                      // 0x500
1860
        12: polynom = 32'b100000101001;                     // 0x829
1861
        13: polynom = 32'b1000000001100;                    // 0x100C
1862
        14: polynom = 32'b10000000010101;                   // 0x2015
1863
        15: polynom = 32'b110000000000000;                  // 0x6000
1864
        16: polynom = 32'b1101000000001000;                 // 0xD008
1865
        17: polynom = 32'b10010000000000000;                // 0x12000
1866
        18: polynom = 32'b100000010000000000;               // 0x20400
1867
        19: polynom = 32'b1000000000000100011;              // 0x40023
1868 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
1869 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
1870
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1871
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1872
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1873
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1874
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1875
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1876
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1877
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1878
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1879
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1880
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1881
        default: polynom = 32'b0;
1882
        endcase
1883
        lfsr_fb = qi[length];
1884
        for (i=length-1; i>=1; i=i-1) begin
1885
            if (polynom[i])
1886
                lfsr_fb = lfsr_fb  ~^ qi[i];
1887
        end
1888
    end
1889
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1890
 
1891
   always @ (posedge clk or posedge rst)
1892
     if (rst)
1893
       qi <= {length{1'b0}};
1894
     else
1895
     if (cke)
1896
       qi <= q_next;
1897
 
1898
 
1899
 
1900
   always @ (posedge clk or posedge rst)
1901
     if (rst)
1902
       zq <= 1'b1;
1903
     else
1904
     if (cke)
1905
       zq <= q_next == {length{1'b0}};
1906
endmodule
1907
//////////////////////////////////////////////////////////////////////
1908
////                                                              ////
1909
////  Versatile counter                                           ////
1910
////                                                              ////
1911
////  Description                                                 ////
1912
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1913
////  counter                                                     ////
1914
////                                                              ////
1915
////  To Do:                                                      ////
1916
////   - add LFSR with more taps                                  ////
1917
////                                                              ////
1918
////  Author(s):                                                  ////
1919
////      - Michael Unneback, unneback@opencores.org              ////
1920
////        ORSoC AB                                              ////
1921
////                                                              ////
1922
//////////////////////////////////////////////////////////////////////
1923
////                                                              ////
1924
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1925
////                                                              ////
1926
//// This source file may be used and distributed without         ////
1927
//// restriction provided that this copyright statement is not    ////
1928
//// removed from the file and that any derivative work contains  ////
1929
//// the original copyright notice and the associated disclaimer. ////
1930
////                                                              ////
1931
//// This source file is free software; you can redistribute it   ////
1932
//// and/or modify it under the terms of the GNU Lesser General   ////
1933
//// Public License as published by the Free Software Foundation; ////
1934
//// either version 2.1 of the License, or (at your option) any   ////
1935
//// later version.                                               ////
1936
////                                                              ////
1937
//// This source is distributed in the hope that it will be       ////
1938
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1939
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1940
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1941
//// details.                                                     ////
1942
////                                                              ////
1943
//// You should have received a copy of the GNU Lesser General    ////
1944
//// Public License along with this source; if not, download it   ////
1945
//// from http://www.opencores.org/lgpl.shtml                     ////
1946
////                                                              ////
1947
//////////////////////////////////////////////////////////////////////
1948 22 unneback
 
1949
// LFSR counter
1950 27 unneback
module vl_cnt_lfsr_ce_q ( cke, q, rst, clk);
1951
 
1952
   parameter length = 4;
1953
   input cke;
1954
   output [length:1] q;
1955
   input rst;
1956
   input clk;
1957
 
1958
   parameter clear_value = 0;
1959
   parameter set_value = 1;
1960
   parameter wrap_value = 8;
1961
   parameter level1_value = 15;
1962
 
1963
   reg  [length:1] qi;
1964
   reg lfsr_fb;
1965
   wire [length:1] q_next;
1966
   reg [32:1] polynom;
1967
   integer i;
1968
 
1969
   always @ (qi)
1970
   begin
1971
        case (length)
1972
         2: polynom = 32'b11;                               // 0x3
1973
         3: polynom = 32'b110;                              // 0x6
1974
         4: polynom = 32'b1100;                             // 0xC
1975
         5: polynom = 32'b10100;                            // 0x14
1976
         6: polynom = 32'b110000;                           // 0x30
1977
         7: polynom = 32'b1100000;                          // 0x60
1978
         8: polynom = 32'b10111000;                         // 0xb8
1979
         9: polynom = 32'b100010000;                        // 0x110
1980
        10: polynom = 32'b1001000000;                       // 0x240
1981
        11: polynom = 32'b10100000000;                      // 0x500
1982
        12: polynom = 32'b100000101001;                     // 0x829
1983
        13: polynom = 32'b1000000001100;                    // 0x100C
1984
        14: polynom = 32'b10000000010101;                   // 0x2015
1985
        15: polynom = 32'b110000000000000;                  // 0x6000
1986
        16: polynom = 32'b1101000000001000;                 // 0xD008
1987
        17: polynom = 32'b10010000000000000;                // 0x12000
1988
        18: polynom = 32'b100000010000000000;               // 0x20400
1989
        19: polynom = 32'b1000000000000100011;              // 0x40023
1990 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
1991 27 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
1992
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1993
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1994
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1995
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1996
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1997
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1998
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1999
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2000
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2001
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2002
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2003
        default: polynom = 32'b0;
2004
        endcase
2005
        lfsr_fb = qi[length];
2006
        for (i=length-1; i>=1; i=i-1) begin
2007
            if (polynom[i])
2008
                lfsr_fb = lfsr_fb  ~^ qi[i];
2009
        end
2010
    end
2011
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2012
 
2013
   always @ (posedge clk or posedge rst)
2014
     if (rst)
2015
       qi <= {length{1'b0}};
2016
     else
2017
     if (cke)
2018
       qi <= q_next;
2019
 
2020
   assign q = qi;
2021
 
2022
endmodule
2023
//////////////////////////////////////////////////////////////////////
2024
////                                                              ////
2025
////  Versatile counter                                           ////
2026
////                                                              ////
2027
////  Description                                                 ////
2028
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2029
////  counter                                                     ////
2030
////                                                              ////
2031
////  To Do:                                                      ////
2032
////   - add LFSR with more taps                                  ////
2033
////                                                              ////
2034
////  Author(s):                                                  ////
2035
////      - Michael Unneback, unneback@opencores.org              ////
2036
////        ORSoC AB                                              ////
2037
////                                                              ////
2038
//////////////////////////////////////////////////////////////////////
2039
////                                                              ////
2040
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2041
////                                                              ////
2042
//// This source file may be used and distributed without         ////
2043
//// restriction provided that this copyright statement is not    ////
2044
//// removed from the file and that any derivative work contains  ////
2045
//// the original copyright notice and the associated disclaimer. ////
2046
////                                                              ////
2047
//// This source file is free software; you can redistribute it   ////
2048
//// and/or modify it under the terms of the GNU Lesser General   ////
2049
//// Public License as published by the Free Software Foundation; ////
2050
//// either version 2.1 of the License, or (at your option) any   ////
2051
//// later version.                                               ////
2052
////                                                              ////
2053
//// This source is distributed in the hope that it will be       ////
2054
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2055
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2056
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2057
//// details.                                                     ////
2058
////                                                              ////
2059
//// You should have received a copy of the GNU Lesser General    ////
2060
//// Public License along with this source; if not, download it   ////
2061
//// from http://www.opencores.org/lgpl.shtml                     ////
2062
////                                                              ////
2063
//////////////////////////////////////////////////////////////////////
2064
 
2065
// LFSR counter
2066
module vl_cnt_lfsr_ce_clear_q ( clear, cke, q, rst, clk);
2067
 
2068
   parameter length = 4;
2069
   input clear;
2070
   input cke;
2071
   output [length:1] q;
2072
   input rst;
2073
   input clk;
2074
 
2075
   parameter clear_value = 0;
2076
   parameter set_value = 1;
2077
   parameter wrap_value = 8;
2078
   parameter level1_value = 15;
2079
 
2080
   reg  [length:1] qi;
2081
   reg lfsr_fb;
2082
   wire [length:1] q_next;
2083
   reg [32:1] polynom;
2084
   integer i;
2085
 
2086
   always @ (qi)
2087
   begin
2088
        case (length)
2089
         2: polynom = 32'b11;                               // 0x3
2090
         3: polynom = 32'b110;                              // 0x6
2091
         4: polynom = 32'b1100;                             // 0xC
2092
         5: polynom = 32'b10100;                            // 0x14
2093
         6: polynom = 32'b110000;                           // 0x30
2094
         7: polynom = 32'b1100000;                          // 0x60
2095
         8: polynom = 32'b10111000;                         // 0xb8
2096
         9: polynom = 32'b100010000;                        // 0x110
2097
        10: polynom = 32'b1001000000;                       // 0x240
2098
        11: polynom = 32'b10100000000;                      // 0x500
2099
        12: polynom = 32'b100000101001;                     // 0x829
2100
        13: polynom = 32'b1000000001100;                    // 0x100C
2101
        14: polynom = 32'b10000000010101;                   // 0x2015
2102
        15: polynom = 32'b110000000000000;                  // 0x6000
2103
        16: polynom = 32'b1101000000001000;                 // 0xD008
2104
        17: polynom = 32'b10010000000000000;                // 0x12000
2105
        18: polynom = 32'b100000010000000000;               // 0x20400
2106
        19: polynom = 32'b1000000000000100011;              // 0x40023
2107 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2108 27 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2109
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2110
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2111
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2112
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2113
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2114
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2115
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2116
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2117
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2118
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2119
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2120
        default: polynom = 32'b0;
2121
        endcase
2122
        lfsr_fb = qi[length];
2123
        for (i=length-1; i>=1; i=i-1) begin
2124
            if (polynom[i])
2125
                lfsr_fb = lfsr_fb  ~^ qi[i];
2126
        end
2127
    end
2128
   assign q_next =  clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2129
 
2130
   always @ (posedge clk or posedge rst)
2131
     if (rst)
2132
       qi <= {length{1'b0}};
2133
     else
2134
     if (cke)
2135
       qi <= q_next;
2136
 
2137
   assign q = qi;
2138
 
2139
endmodule
2140
//////////////////////////////////////////////////////////////////////
2141
////                                                              ////
2142
////  Versatile counter                                           ////
2143
////                                                              ////
2144
////  Description                                                 ////
2145
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2146
////  counter                                                     ////
2147
////                                                              ////
2148
////  To Do:                                                      ////
2149
////   - add LFSR with more taps                                  ////
2150
////                                                              ////
2151
////  Author(s):                                                  ////
2152
////      - Michael Unneback, unneback@opencores.org              ////
2153
////        ORSoC AB                                              ////
2154
////                                                              ////
2155
//////////////////////////////////////////////////////////////////////
2156
////                                                              ////
2157
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2158
////                                                              ////
2159
//// This source file may be used and distributed without         ////
2160
//// restriction provided that this copyright statement is not    ////
2161
//// removed from the file and that any derivative work contains  ////
2162
//// the original copyright notice and the associated disclaimer. ////
2163
////                                                              ////
2164
//// This source file is free software; you can redistribute it   ////
2165
//// and/or modify it under the terms of the GNU Lesser General   ////
2166
//// Public License as published by the Free Software Foundation; ////
2167
//// either version 2.1 of the License, or (at your option) any   ////
2168
//// later version.                                               ////
2169
////                                                              ////
2170
//// This source is distributed in the hope that it will be       ////
2171
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2172
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2173
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2174
//// details.                                                     ////
2175
////                                                              ////
2176
//// You should have received a copy of the GNU Lesser General    ////
2177
//// Public License along with this source; if not, download it   ////
2178
//// from http://www.opencores.org/lgpl.shtml                     ////
2179
////                                                              ////
2180
//////////////////////////////////////////////////////////////////////
2181
 
2182
// LFSR counter
2183 22 unneback
module vl_cnt_lfsr_ce_q_zq ( cke, q, zq, rst, clk);
2184
 
2185
   parameter length = 4;
2186
   input cke;
2187
   output [length:1] q;
2188
   output reg zq;
2189
   input rst;
2190
   input clk;
2191
 
2192
   parameter clear_value = 0;
2193
   parameter set_value = 1;
2194
   parameter wrap_value = 8;
2195
   parameter level1_value = 15;
2196
 
2197
   reg  [length:1] qi;
2198
   reg lfsr_fb;
2199
   wire [length:1] q_next;
2200
   reg [32:1] polynom;
2201
   integer i;
2202
 
2203
   always @ (qi)
2204
   begin
2205
        case (length)
2206
         2: polynom = 32'b11;                               // 0x3
2207
         3: polynom = 32'b110;                              // 0x6
2208
         4: polynom = 32'b1100;                             // 0xC
2209
         5: polynom = 32'b10100;                            // 0x14
2210
         6: polynom = 32'b110000;                           // 0x30
2211
         7: polynom = 32'b1100000;                          // 0x60
2212
         8: polynom = 32'b10111000;                         // 0xb8
2213
         9: polynom = 32'b100010000;                        // 0x110
2214
        10: polynom = 32'b1001000000;                       // 0x240
2215
        11: polynom = 32'b10100000000;                      // 0x500
2216
        12: polynom = 32'b100000101001;                     // 0x829
2217
        13: polynom = 32'b1000000001100;                    // 0x100C
2218
        14: polynom = 32'b10000000010101;                   // 0x2015
2219
        15: polynom = 32'b110000000000000;                  // 0x6000
2220
        16: polynom = 32'b1101000000001000;                 // 0xD008
2221
        17: polynom = 32'b10010000000000000;                // 0x12000
2222
        18: polynom = 32'b100000010000000000;               // 0x20400
2223
        19: polynom = 32'b1000000000000100011;              // 0x40023
2224 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2225 22 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2226
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2227
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2228
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2229
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2230
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2231
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2232
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2233
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2234
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2235
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2236
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2237
        default: polynom = 32'b0;
2238
        endcase
2239
        lfsr_fb = qi[length];
2240
        for (i=length-1; i>=1; i=i-1) begin
2241
            if (polynom[i])
2242
                lfsr_fb = lfsr_fb  ~^ qi[i];
2243
        end
2244
    end
2245
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2246
 
2247
   always @ (posedge clk or posedge rst)
2248
     if (rst)
2249
       qi <= {length{1'b0}};
2250
     else
2251
     if (cke)
2252
       qi <= q_next;
2253
 
2254
   assign q = qi;
2255
 
2256
 
2257
   always @ (posedge clk or posedge rst)
2258
     if (rst)
2259
       zq <= 1'b1;
2260
     else
2261
     if (cke)
2262
       zq <= q_next == {length{1'b0}};
2263
endmodule
2264
//////////////////////////////////////////////////////////////////////
2265
////                                                              ////
2266
////  Versatile counter                                           ////
2267
////                                                              ////
2268
////  Description                                                 ////
2269
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2270
////  counter                                                     ////
2271
////                                                              ////
2272
////  To Do:                                                      ////
2273
////   - add LFSR with more taps                                  ////
2274
////                                                              ////
2275
////  Author(s):                                                  ////
2276
////      - Michael Unneback, unneback@opencores.org              ////
2277
////        ORSoC AB                                              ////
2278
////                                                              ////
2279
//////////////////////////////////////////////////////////////////////
2280
////                                                              ////
2281
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2282
////                                                              ////
2283
//// This source file may be used and distributed without         ////
2284
//// restriction provided that this copyright statement is not    ////
2285
//// removed from the file and that any derivative work contains  ////
2286
//// the original copyright notice and the associated disclaimer. ////
2287
////                                                              ////
2288
//// This source file is free software; you can redistribute it   ////
2289
//// and/or modify it under the terms of the GNU Lesser General   ////
2290
//// Public License as published by the Free Software Foundation; ////
2291
//// either version 2.1 of the License, or (at your option) any   ////
2292
//// later version.                                               ////
2293
////                                                              ////
2294
//// This source is distributed in the hope that it will be       ////
2295
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2296
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2297
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2298
//// details.                                                     ////
2299
////                                                              ////
2300
//// You should have received a copy of the GNU Lesser General    ////
2301
//// Public License along with this source; if not, download it   ////
2302
//// from http://www.opencores.org/lgpl.shtml                     ////
2303
////                                                              ////
2304
//////////////////////////////////////////////////////////////////////
2305 6 unneback
 
2306
// LFSR counter
2307 18 unneback
module vl_cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk);
2308 6 unneback
 
2309
   parameter length = 4;
2310
   input cke;
2311
   input rew;
2312
   output reg level1;
2313
   input rst;
2314
   input clk;
2315
 
2316
   parameter clear_value = 0;
2317
   parameter set_value = 1;
2318
   parameter wrap_value = 8;
2319
   parameter level1_value = 15;
2320
 
2321 29 unneback
   wire clear;
2322 30 unneback
   assign clear = 1'b0;
2323 6 unneback
   reg  [length:1] qi;
2324
   reg lfsr_fb, lfsr_fb_rew;
2325
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2326
   reg [32:1] polynom_rew;
2327
   integer j;
2328
   reg [32:1] polynom;
2329
   integer i;
2330
 
2331
   always @ (qi)
2332
   begin
2333
        case (length)
2334
         2: polynom = 32'b11;                               // 0x3
2335
         3: polynom = 32'b110;                              // 0x6
2336
         4: polynom = 32'b1100;                             // 0xC
2337
         5: polynom = 32'b10100;                            // 0x14
2338
         6: polynom = 32'b110000;                           // 0x30
2339
         7: polynom = 32'b1100000;                          // 0x60
2340
         8: polynom = 32'b10111000;                         // 0xb8
2341
         9: polynom = 32'b100010000;                        // 0x110
2342
        10: polynom = 32'b1001000000;                       // 0x240
2343
        11: polynom = 32'b10100000000;                      // 0x500
2344
        12: polynom = 32'b100000101001;                     // 0x829
2345
        13: polynom = 32'b1000000001100;                    // 0x100C
2346
        14: polynom = 32'b10000000010101;                   // 0x2015
2347
        15: polynom = 32'b110000000000000;                  // 0x6000
2348
        16: polynom = 32'b1101000000001000;                 // 0xD008
2349
        17: polynom = 32'b10010000000000000;                // 0x12000
2350
        18: polynom = 32'b100000010000000000;               // 0x20400
2351
        19: polynom = 32'b1000000000000100011;              // 0x40023
2352 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2353 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2354
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2355
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2356
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2357
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2358
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2359
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2360
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2361
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2362
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2363
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2364
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2365
        default: polynom = 32'b0;
2366
        endcase
2367
        lfsr_fb = qi[length];
2368
        for (i=length-1; i>=1; i=i-1) begin
2369
            if (polynom[i])
2370
                lfsr_fb = lfsr_fb  ~^ qi[i];
2371
        end
2372
    end
2373
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2374
   always @ (qi)
2375
   begin
2376
        case (length)
2377
         2: polynom_rew = 32'b11;
2378
         3: polynom_rew = 32'b110;
2379
         4: polynom_rew = 32'b1100;
2380
         5: polynom_rew = 32'b10100;
2381
         6: polynom_rew = 32'b110000;
2382
         7: polynom_rew = 32'b1100000;
2383
         8: polynom_rew = 32'b10111000;
2384
         9: polynom_rew = 32'b100010000;
2385
        10: polynom_rew = 32'b1001000000;
2386
        11: polynom_rew = 32'b10100000000;
2387
        12: polynom_rew = 32'b100000101001;
2388
        13: polynom_rew = 32'b1000000001100;
2389
        14: polynom_rew = 32'b10000000010101;
2390
        15: polynom_rew = 32'b110000000000000;
2391
        16: polynom_rew = 32'b1101000000001000;
2392
        17: polynom_rew = 32'b10010000000000000;
2393
        18: polynom_rew = 32'b100000010000000000;
2394
        19: polynom_rew = 32'b1000000000000100011;
2395
        20: polynom_rew = 32'b10000010000000000000;
2396
        21: polynom_rew = 32'b101000000000000000000;
2397
        22: polynom_rew = 32'b1100000000000000000000;
2398
        23: polynom_rew = 32'b10000100000000000000000;
2399
        24: polynom_rew = 32'b111000010000000000000000;
2400
        25: polynom_rew = 32'b1001000000000000000000000;
2401
        26: polynom_rew = 32'b10000000000000000000100011;
2402
        27: polynom_rew = 32'b100000000000000000000010011;
2403
        28: polynom_rew = 32'b1100100000000000000000000000;
2404
        29: polynom_rew = 32'b10100000000000000000000000000;
2405
        30: polynom_rew = 32'b100000000000000000000000101001;
2406
        31: polynom_rew = 32'b1001000000000000000000000000000;
2407
        32: polynom_rew = 32'b10000000001000000000000000000011;
2408
        default: polynom_rew = 32'b0;
2409
        endcase
2410
        // rotate left
2411
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
2412
        lfsr_fb_rew = qi[length];
2413
        for (i=length-1; i>=1; i=i-1) begin
2414
            if (polynom_rew[i])
2415
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
2416
        end
2417
    end
2418
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
2419
   assign q_next = rew ? q_next_rew : q_next_fw;
2420
 
2421
   always @ (posedge clk or posedge rst)
2422
     if (rst)
2423
       qi <= {length{1'b0}};
2424
     else
2425
     if (cke)
2426
       qi <= q_next;
2427
 
2428
 
2429
 
2430
    always @ (posedge clk or posedge rst)
2431
    if (rst)
2432
        level1 <= 1'b0;
2433
    else
2434
    if (cke)
2435 29 unneback
    if (clear)
2436
        level1 <= 1'b0;
2437
    else if (q_next == level1_value)
2438 6 unneback
        level1 <= 1'b1;
2439
    else if (qi == level1_value & rew)
2440
        level1 <= 1'b0;
2441
endmodule
2442
//////////////////////////////////////////////////////////////////////
2443
////                                                              ////
2444
////  Versatile counter                                           ////
2445
////                                                              ////
2446
////  Description                                                 ////
2447
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2448
////  counter                                                     ////
2449
////                                                              ////
2450
////  To Do:                                                      ////
2451
////   - add LFSR with more taps                                  ////
2452
////                                                              ////
2453
////  Author(s):                                                  ////
2454
////      - Michael Unneback, unneback@opencores.org              ////
2455
////        ORSoC AB                                              ////
2456
////                                                              ////
2457
//////////////////////////////////////////////////////////////////////
2458
////                                                              ////
2459
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2460
////                                                              ////
2461
//// This source file may be used and distributed without         ////
2462
//// restriction provided that this copyright statement is not    ////
2463
//// removed from the file and that any derivative work contains  ////
2464
//// the original copyright notice and the associated disclaimer. ////
2465
////                                                              ////
2466
//// This source file is free software; you can redistribute it   ////
2467
//// and/or modify it under the terms of the GNU Lesser General   ////
2468
//// Public License as published by the Free Software Foundation; ////
2469
//// either version 2.1 of the License, or (at your option) any   ////
2470
//// later version.                                               ////
2471
////                                                              ////
2472
//// This source is distributed in the hope that it will be       ////
2473
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2474
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2475
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2476
//// details.                                                     ////
2477
////                                                              ////
2478
//// You should have received a copy of the GNU Lesser General    ////
2479
//// Public License along with this source; if not, download it   ////
2480
//// from http://www.opencores.org/lgpl.shtml                     ////
2481
////                                                              ////
2482
//////////////////////////////////////////////////////////////////////
2483
 
2484
// GRAY counter
2485 18 unneback
module vl_cnt_gray ( q, rst, clk);
2486 6 unneback
 
2487
   parameter length = 4;
2488
   output reg [length:1] q;
2489
   input rst;
2490
   input clk;
2491
 
2492
   parameter clear_value = 0;
2493
   parameter set_value = 1;
2494
   parameter wrap_value = 8;
2495
   parameter level1_value = 15;
2496
 
2497
   reg  [length:1] qi;
2498
   wire [length:1] q_next;
2499
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2500
 
2501
   always @ (posedge clk or posedge rst)
2502
     if (rst)
2503
       qi <= {length{1'b0}};
2504
     else
2505
       qi <= q_next;
2506
 
2507
   always @ (posedge clk or posedge rst)
2508
     if (rst)
2509
       q <= {length{1'b0}};
2510
     else
2511
         q <= (q_next>>1) ^ q_next;
2512
 
2513
endmodule
2514
//////////////////////////////////////////////////////////////////////
2515
////                                                              ////
2516
////  Versatile counter                                           ////
2517
////                                                              ////
2518
////  Description                                                 ////
2519
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2520
////  counter                                                     ////
2521
////                                                              ////
2522
////  To Do:                                                      ////
2523
////   - add LFSR with more taps                                  ////
2524
////                                                              ////
2525
////  Author(s):                                                  ////
2526
////      - Michael Unneback, unneback@opencores.org              ////
2527
////        ORSoC AB                                              ////
2528
////                                                              ////
2529
//////////////////////////////////////////////////////////////////////
2530
////                                                              ////
2531
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2532
////                                                              ////
2533
//// This source file may be used and distributed without         ////
2534
//// restriction provided that this copyright statement is not    ////
2535
//// removed from the file and that any derivative work contains  ////
2536
//// the original copyright notice and the associated disclaimer. ////
2537
////                                                              ////
2538
//// This source file is free software; you can redistribute it   ////
2539
//// and/or modify it under the terms of the GNU Lesser General   ////
2540
//// Public License as published by the Free Software Foundation; ////
2541
//// either version 2.1 of the License, or (at your option) any   ////
2542
//// later version.                                               ////
2543
////                                                              ////
2544
//// This source is distributed in the hope that it will be       ////
2545
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2546
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2547
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2548
//// details.                                                     ////
2549
////                                                              ////
2550
//// You should have received a copy of the GNU Lesser General    ////
2551
//// Public License along with this source; if not, download it   ////
2552
//// from http://www.opencores.org/lgpl.shtml                     ////
2553
////                                                              ////
2554
//////////////////////////////////////////////////////////////////////
2555
 
2556
// GRAY counter
2557 18 unneback
module vl_cnt_gray_ce ( cke, q, rst, clk);
2558 6 unneback
 
2559
   parameter length = 4;
2560
   input cke;
2561
   output reg [length:1] q;
2562
   input rst;
2563
   input clk;
2564
 
2565
   parameter clear_value = 0;
2566
   parameter set_value = 1;
2567
   parameter wrap_value = 8;
2568
   parameter level1_value = 15;
2569
 
2570
   reg  [length:1] qi;
2571
   wire [length:1] q_next;
2572
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2573
 
2574
   always @ (posedge clk or posedge rst)
2575
     if (rst)
2576
       qi <= {length{1'b0}};
2577
     else
2578
     if (cke)
2579
       qi <= q_next;
2580
 
2581
   always @ (posedge clk or posedge rst)
2582
     if (rst)
2583
       q <= {length{1'b0}};
2584
     else
2585
       if (cke)
2586
         q <= (q_next>>1) ^ q_next;
2587
 
2588
endmodule
2589
//////////////////////////////////////////////////////////////////////
2590
////                                                              ////
2591
////  Versatile counter                                           ////
2592
////                                                              ////
2593
////  Description                                                 ////
2594
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2595
////  counter                                                     ////
2596
////                                                              ////
2597
////  To Do:                                                      ////
2598
////   - add LFSR with more taps                                  ////
2599
////                                                              ////
2600
////  Author(s):                                                  ////
2601
////      - Michael Unneback, unneback@opencores.org              ////
2602
////        ORSoC AB                                              ////
2603
////                                                              ////
2604
//////////////////////////////////////////////////////////////////////
2605
////                                                              ////
2606
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2607
////                                                              ////
2608
//// This source file may be used and distributed without         ////
2609
//// restriction provided that this copyright statement is not    ////
2610
//// removed from the file and that any derivative work contains  ////
2611
//// the original copyright notice and the associated disclaimer. ////
2612
////                                                              ////
2613
//// This source file is free software; you can redistribute it   ////
2614
//// and/or modify it under the terms of the GNU Lesser General   ////
2615
//// Public License as published by the Free Software Foundation; ////
2616
//// either version 2.1 of the License, or (at your option) any   ////
2617
//// later version.                                               ////
2618
////                                                              ////
2619
//// This source is distributed in the hope that it will be       ////
2620
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2621
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2622
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2623
//// details.                                                     ////
2624
////                                                              ////
2625
//// You should have received a copy of the GNU Lesser General    ////
2626
//// Public License along with this source; if not, download it   ////
2627
//// from http://www.opencores.org/lgpl.shtml                     ////
2628
////                                                              ////
2629
//////////////////////////////////////////////////////////////////////
2630
 
2631
// GRAY counter
2632 18 unneback
module vl_cnt_gray_ce_bin ( cke, q, q_bin, rst, clk);
2633 6 unneback
 
2634
   parameter length = 4;
2635
   input cke;
2636
   output reg [length:1] q;
2637
   output [length:1] q_bin;
2638
   input rst;
2639
   input clk;
2640
 
2641
   parameter clear_value = 0;
2642
   parameter set_value = 1;
2643
   parameter wrap_value = 8;
2644
   parameter level1_value = 15;
2645
 
2646
   reg  [length:1] qi;
2647
   wire [length:1] q_next;
2648
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2649
 
2650
   always @ (posedge clk or posedge rst)
2651
     if (rst)
2652
       qi <= {length{1'b0}};
2653
     else
2654
     if (cke)
2655
       qi <= q_next;
2656
 
2657
   always @ (posedge clk or posedge rst)
2658
     if (rst)
2659
       q <= {length{1'b0}};
2660
     else
2661
       if (cke)
2662
         q <= (q_next>>1) ^ q_next;
2663
 
2664
   assign q_bin = qi;
2665
 
2666
endmodule
2667
//////////////////////////////////////////////////////////////////////
2668
////                                                              ////
2669
////  Versatile library, counters                                 ////
2670
////                                                              ////
2671
////  Description                                                 ////
2672
////  counters                                                    ////
2673
////                                                              ////
2674
////                                                              ////
2675
////  To Do:                                                      ////
2676
////   - add more counters                                        ////
2677
////                                                              ////
2678
////  Author(s):                                                  ////
2679
////      - Michael Unneback, unneback@opencores.org              ////
2680
////        ORSoC AB                                              ////
2681
////                                                              ////
2682
//////////////////////////////////////////////////////////////////////
2683
////                                                              ////
2684
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2685
////                                                              ////
2686
//// This source file may be used and distributed without         ////
2687
//// restriction provided that this copyright statement is not    ////
2688
//// removed from the file and that any derivative work contains  ////
2689
//// the original copyright notice and the associated disclaimer. ////
2690
////                                                              ////
2691
//// This source file is free software; you can redistribute it   ////
2692
//// and/or modify it under the terms of the GNU Lesser General   ////
2693
//// Public License as published by the Free Software Foundation; ////
2694
//// either version 2.1 of the License, or (at your option) any   ////
2695
//// later version.                                               ////
2696
////                                                              ////
2697
//// This source is distributed in the hope that it will be       ////
2698
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2699
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2700
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2701
//// details.                                                     ////
2702
////                                                              ////
2703
//// You should have received a copy of the GNU Lesser General    ////
2704
//// Public License along with this source; if not, download it   ////
2705
//// from http://www.opencores.org/lgpl.shtml                     ////
2706
////                                                              ////
2707
//////////////////////////////////////////////////////////////////////
2708
 
2709 18 unneback
module vl_cnt_shreg_wrap ( q, rst, clk);
2710 6 unneback
 
2711
   parameter length = 4;
2712
   output reg [0:length-1] q;
2713
   input rst;
2714
   input clk;
2715
 
2716
    always @ (posedge clk or posedge rst)
2717
    if (rst)
2718
        q <= {1'b1,{length-1{1'b0}}};
2719
    else
2720
        q <= {q[length-1],q[0:length-2]};
2721
 
2722
endmodule
2723
 
2724 18 unneback
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
2725 6 unneback
 
2726
   parameter length = 4;
2727
   input cke;
2728
   output reg [0:length-1] q;
2729
   input rst;
2730
   input clk;
2731
 
2732
    always @ (posedge clk or posedge rst)
2733
    if (rst)
2734
        q