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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Blame information for rev 41

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1 40 unneback
`ifndef BASE
2
`define BASE vl_
3
`endif
4
 
5
`ifdef ALL
6
 
7
`define GBUF
8
`define SYNC_RST
9
`define PLL
10
 
11
`define MULTS
12
`define MULTS18X18
13
`define MULT
14
`define SHIFT_UNIT_32
15
`define LOGIC_UNIT
16
 
17
`define CNT_SHREG_WRAP
18
`define CNT_SHREG_CE_WRAP
19
`define CNT_SHREG_CE_CLEAR
20
`define CNT_SHREG_CE_CLEAR_WRAP
21
 
22
`define MUX_ANDOR
23
`define MUX2_ANDOR
24
`define MUX3_ANDOR
25
`define MUX4_ANDOR
26
`define MUX5_ANDOR
27
`define MUX6_ANDOR
28
 
29
`define ROM_INIT
30
`define RAM
31
`define RAM_BE
32
`define DPRAM_1R1W
33
`define DPRAM_2R1W
34
`define DPRAM_2R2W
35
`define FIFO_1R1W_FILL_LEVEL_SYNC
36
`define FIFO_2R2W_SYNC_SIMPLEX
37
`define FIFO_CMP_ASYNC
38
`define FIFO_1R1W_ASYNC
39
`define FIFO_2R2W_ASYNC
40
`define FIFO_2R2W_ASYNC_SIMPLEX
41
 
42
`define DFF
43
`define DFF_ARRAY
44
`define DFF_CE
45
`define DFF_CE_CLEAR
46
`define DF_CE_SET
47
`define SPR
48
`define SRP
49
`define DFF_SR
50
`define LATCH
51
`define SHREG
52
`define SHREG_CE
53
`define DELAY
54
`define DELAY_EMPTYFLAG
55
 
56
`define WB3WB3_BRIDGE
57
`define WB3_ARBITER_TYPE1
58
`define WB_BOOT_ROM
59
`define WB_DPRAM
60
 
61
`endif
62
 
63
`ifdef PLL
64
`ifndef SYNC_RST
65
`define SYNC_RST
66
`endif
67
`endif
68
 
69
`ifdef SYNC_RST
70
`ifndef GBUF
71
`define GBUF
72
`endif
73
`endif
74
 
75
`ifdef WB_DPRAM
76
`ifndef DPRAM_2R2W
77
`define DPRAM_2R2W
78
`endif
79
`ifndef SPR
80
`define SPR
81
`endif
82
`endif
83
 
84
`ifdef WB3_ARBITER_TYPE1
85
`ifndef MUX_ANDOR
86
`define MUX_ANDOR
87
`endif
88
`endif
89
 
90
`ifdef WB3WB3_BRIDGE
91
`ifndef CNT_SHREG_CE_CLEAR
92
`define CNT_SHREG_CE_CLEAR
93
`endif
94
`ifndef DFF
95
`define DFF
96
`endif
97
`ifndef DFF_CE
98
`define DFF_CE
99
`endif
100
`ifndef CNT_SHREG_CE_CLEAR
101
`define CNT_SHREG_CE_CLEAR
102
`endif
103
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
104
`define FIFO_2R2W_ASYNC_SIMPLEX
105
`endif
106
`endif
107
 
108
`ifdef MULTS18X18
109
`ifndef MULTS
110
`define MULTS
111
`endif
112
`endif
113
 
114
`ifdef SHIFT_UNIT_32
115
`ifndef MULTS
116
`define MULTS
117
`endif
118
`endif
119
 
120
`ifdef MUX2_ANDOR
121
`ifndef MUX_ANDOR
122
`define MUX_ANDOR
123
`endif
124
`endif
125
 
126
`ifdef MUX3_ANDOR
127
`ifndef MUX_ANDOR
128
`define MUX_ANDOR
129
`endif
130
`endif
131
 
132
`ifdef MUX4_ANDOR
133
`ifndef MUX_ANDOR
134
`define MUX_ANDOR
135
`endif
136
`endif
137
 
138
`ifdef MUX5_ANDOR
139
`ifndef MUX_ANDOR
140
`define MUX_ANDOR
141
`endif
142
`endif
143
 
144
`ifdef MUX6_ANDOR
145
`ifndef MUX_ANDOR
146
`define MUX_ANDOR
147
`endif
148
`endif
149
 
150
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
151
`ifndef CNT_BIN_CE
152
`define CNT_BIN_CE
153
`endif
154
`ifndef DPRAM_1R1W
155
`define DPRAM_1R1W
156
`endif
157
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
158
`define CNT_BIN_CE_REW_Q_ZQ_L1
159
`endif
160
`endif
161
 
162
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
163
`ifndef CNT_LFSR_CE
164
`define CNT_LFSR_CE
165
`endif
166
`ifndef DPRAM_2R2W
167
`define DPRAM_2R2W
168
`endif
169
`ifndef CNT_BIN_CE_REW_ZQ_L1
170
`define CNT_BIN_CE_REW_ZQ_L1
171
`endif
172
`endif
173
 
174
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
175
`ifndef CNT_GRAY_CE_BIN
176
`define CNT_GRAY_CE_BIN
177
`endif
178
`ifndef DPRAM_2R2W
179
`define DPRAM_2R2W
180
`endif
181
`ifndef FIFO_CMP_ASYNC
182
`define FIFO_CMP_ASYNC
183
`endif
184
`endif
185
 
186
`ifdef FIFO_2R2W_ASYNC
187
`ifndef FIFO_1R1W_ASYNC
188
`define FIFO_1R1W_ASYNC
189
`endif
190
`endif
191
 
192
`ifdef FIFO_1R1W_ASYNC
193
`ifndef CNT_GRAY_CE_BIN
194
`define CNT_GRAY_CE_BIN
195
`endif
196
`ifndef DPRAM_1R1W
197
`define DPRAM_1R1W
198
`endif
199
`ifndef FIFO_CMP_ASYNC
200
`define FIFO_CMP_ASYNC
201
`endif
202
`endif
203
 
204
`ifdef FIFO_CMP_ASYNC
205
`ifndef DFF_SR
206
`define DFF_SR
207
`endif
208
`ifndef DFF
209
`define DFF
210
`endif
211
`endif
212 6 unneback
//////////////////////////////////////////////////////////////////////
213
////                                                              ////
214
////  Versatile library, clock and reset                          ////
215
////                                                              ////
216
////  Description                                                 ////
217
////  Logic related to clock and reset                            ////
218
////                                                              ////
219
////                                                              ////
220
////  To Do:                                                      ////
221
////   - add more different registers                             ////
222
////                                                              ////
223
////  Author(s):                                                  ////
224
////      - Michael Unneback, unneback@opencores.org              ////
225
////        ORSoC AB                                              ////
226
////                                                              ////
227
//////////////////////////////////////////////////////////////////////
228
////                                                              ////
229
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
230
////                                                              ////
231
//// This source file may be used and distributed without         ////
232
//// restriction provided that this copyright statement is not    ////
233
//// removed from the file and that any derivative work contains  ////
234
//// the original copyright notice and the associated disclaimer. ////
235
////                                                              ////
236
//// This source file is free software; you can redistribute it   ////
237
//// and/or modify it under the terms of the GNU Lesser General   ////
238
//// Public License as published by the Free Software Foundation; ////
239
//// either version 2.1 of the License, or (at your option) any   ////
240
//// later version.                                               ////
241
////                                                              ////
242
//// This source is distributed in the hope that it will be       ////
243
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
244
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
245
//// PURPOSE.  See the GNU Lesser General Public License for more ////
246
//// details.                                                     ////
247
////                                                              ////
248
//// You should have received a copy of the GNU Lesser General    ////
249
//// Public License along with this source; if not, download it   ////
250
//// from http://www.opencores.org/lgpl.shtml                     ////
251
////                                                              ////
252
//////////////////////////////////////////////////////////////////////
253
 
254
// Global buffer
255
// usage:
256
// use to enable global buffers for high fan out signals such as clock and reset
257
 
258
`ifdef ACTEL
259 40 unneback
`ifdef GBUF
260 6 unneback
`timescale 1 ns/100 ps
261
// Version: 8.4 8.4.0.33
262
module gbuf(GL,CLK);
263
output GL;
264
input  CLK;
265
 
266
    wire GND;
267
 
268
    GND GND_1_net(.Y(GND));
269
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
270
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
271
 
272
endmodule
273
`timescale 1 ns/1 ns
274 40 unneback
`define MODULE gbuf
275
module `BASE`MODULE ( i, o);
276
`undef MODULE
277 6 unneback
input i;
278
output o;
279
`ifdef SIM_GBUF
280
assign o=i;
281
`else
282
gbuf gbuf_i0 ( .CLK(i), .GL(o));
283
`endif
284
endmodule
285 40 unneback
`endif
286 33 unneback
 
287 6 unneback
`else
288 33 unneback
 
289 40 unneback
`ifdef ALTERA
290
`ifdef GBUF
291 21 unneback
//altera
292 40 unneback
`define MODULE gbuf
293
module `BASE`MODULE ( i, o);
294
`undef MODULE
295 33 unneback
input i;
296
output o;
297
assign o = i;
298
endmodule
299 40 unneback
`endif
300 33 unneback
 
301 6 unneback
`else
302
 
303 40 unneback
`ifdef GBUF
304 6 unneback
`timescale 1 ns/100 ps
305 40 unneback
`define MODULE
306
module `BASE`MODULE ( i, o);
307
`undef MODULE
308 6 unneback
input i;
309
output o;
310
assign o = i;
311
endmodule
312 40 unneback
`endif
313 6 unneback
`endif // ALTERA
314
`endif //ACTEL
315
 
316 40 unneback
`ifdef SYNC_RST
317 6 unneback
// sync reset
318 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
319 6 unneback
// output active high global reset sync with two DFFs 
320
`timescale 1 ns/100 ps
321 40 unneback
`define MODULE sync_rst
322
module `BASE`MODULE ( rst_n_i, rst_o, clk);
323
`undef MODULE
324 6 unneback
input rst_n_i, clk;
325
output rst_o;
326 18 unneback
reg [1:0] tmp;
327 6 unneback
always @ (posedge clk or negedge rst_n_i)
328
if (!rst_n_i)
329 17 unneback
        tmp <= 2'b11;
330 6 unneback
else
331 33 unneback
        tmp <= {1'b0,tmp[1]};
332 40 unneback
`define MODULE gbuf
333
`BASE`MODULE buf_i0( .i(tmp[0]), .o(rst_o));
334
`undef MODULE
335 6 unneback
endmodule
336 40 unneback
`endif
337 6 unneback
 
338 40 unneback
`ifdef PLL
339 6 unneback
// vl_pll
340
`ifdef ACTEL
341 32 unneback
///////////////////////////////////////////////////////////////////////////////
342 17 unneback
`timescale 1 ps/1 ps
343 40 unneback
`define MODULE pll
344
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
345
`undef MODULE
346 6 unneback
parameter index = 0;
347
parameter number_of_clk = 1;
348 17 unneback
parameter period_time_0 = 20000;
349
parameter period_time_1 = 20000;
350
parameter period_time_2 = 20000;
351
parameter lock_delay = 2000000;
352 6 unneback
input clk_i, rst_n_i;
353
output lock;
354
output reg [0:number_of_clk-1] clk_o;
355
output [0:number_of_clk-1] rst_o;
356
 
357
`ifdef SIM_PLL
358
 
359
always
360
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
361
 
362
generate if (number_of_clk > 1)
363
always
364
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
365
endgenerate
366
 
367
generate if (number_of_clk > 2)
368
always
369
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
370
endgenerate
371
 
372
genvar i;
373
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
374
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
375
end
376
endgenerate
377
 
378
assign #lock_delay lock = rst_n_i;
379
 
380
endmodule
381
`else
382
generate if (number_of_clk==1 & index==0) begin
383
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
384
end
385
endgenerate // index==0
386
generate if (number_of_clk==1 & index==1) begin
387
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
388
end
389
endgenerate // index==1
390
generate if (number_of_clk==1 & index==2) begin
391
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
392
end
393
endgenerate // index==2
394
generate if (number_of_clk==1 & index==3) begin
395
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
396
end
397
endgenerate // index==0
398
 
399
generate if (number_of_clk==2 & index==0) begin
400
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
401
end
402
endgenerate // index==0
403
generate if (number_of_clk==2 & index==1) begin
404
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
405
end
406
endgenerate // index==1
407
generate if (number_of_clk==2 & index==2) begin
408
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
409
end
410
endgenerate // index==2
411
generate if (number_of_clk==2 & index==3) begin
412
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
413
end
414
endgenerate // index==0
415
 
416
generate if (number_of_clk==3 & index==0) begin
417
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
418
end
419
endgenerate // index==0
420
generate if (number_of_clk==3 & index==1) begin
421
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
422
end
423
endgenerate // index==1
424
generate if (number_of_clk==3 & index==2) begin
425
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
426
end
427
endgenerate // index==2
428
generate if (number_of_clk==3 & index==3) begin
429
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
430
end
431
endgenerate // index==0
432
 
433
genvar i;
434
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
435 40 unneback
`define MODULE sync_rst
436
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
437
`undef MODULE
438 6 unneback
end
439
endgenerate
440
endmodule
441
`endif
442 32 unneback
///////////////////////////////////////////////////////////////////////////////
443 6 unneback
 
444
`else
445
 
446 32 unneback
///////////////////////////////////////////////////////////////////////////////
447 6 unneback
`ifdef ALTERA
448
 
449 32 unneback
`timescale 1 ps/1 ps
450 40 unneback
`define MODULE pll
451
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
452
`undef MODULE
453 32 unneback
parameter index = 0;
454
parameter number_of_clk = 1;
455
parameter period_time_0 = 20000;
456
parameter period_time_1 = 20000;
457
parameter period_time_2 = 20000;
458
parameter period_time_3 = 20000;
459
parameter period_time_4 = 20000;
460
parameter lock_delay = 2000000;
461
input clk_i, rst_n_i;
462
output lock;
463
output reg [0:number_of_clk-1] clk_o;
464
output [0:number_of_clk-1] rst_o;
465
 
466
`ifdef SIM_PLL
467
 
468
always
469
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
470
 
471
generate if (number_of_clk > 1)
472
always
473
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
474
endgenerate
475
 
476
generate if (number_of_clk > 2)
477
always
478
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
479
endgenerate
480
 
481 33 unneback
generate if (number_of_clk > 3)
482 32 unneback
always
483
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
484
endgenerate
485
 
486 33 unneback
generate if (number_of_clk > 4)
487 32 unneback
always
488
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
489
endgenerate
490
 
491
genvar i;
492
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
493
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
494
end
495
endgenerate
496
 
497 33 unneback
//assign #lock_delay lock = rst_n_i;
498
assign lock = rst_n_i;
499 32 unneback
 
500
endmodule
501 6 unneback
`else
502
 
503 33 unneback
`ifdef VL_PLL0
504
`ifdef VL_PLL0_CLK1
505
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
506
`endif
507
`ifdef VL_PLL0_CLK2
508
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
509
`endif
510
`ifdef VL_PLL0_CLK3
511
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
512
`endif
513
`ifdef VL_PLL0_CLK4
514
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
515
`endif
516
`ifdef VL_PLL0_CLK5
517
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
518
`endif
519
`endif
520 32 unneback
 
521 33 unneback
`ifdef VL_PLL1
522
`ifdef VL_PLL1_CLK1
523
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
524
`endif
525
`ifdef VL_PLL1_CLK2
526
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
527
`endif
528
`ifdef VL_PLL1_CLK3
529
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
530
`endif
531
`ifdef VL_PLL1_CLK4
532
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
533
`endif
534
`ifdef VL_PLL1_CLK5
535
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
536
`endif
537
`endif
538 32 unneback
 
539 33 unneback
`ifdef VL_PLL2
540
`ifdef VL_PLL2_CLK1
541
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
542
`endif
543
`ifdef VL_PLL2_CLK2
544
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
545
`endif
546
`ifdef VL_PLL2_CLK3
547
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
548
`endif
549
`ifdef VL_PLL2_CLK4
550
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
551
`endif
552
`ifdef VL_PLL2_CLK5
553
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
554
`endif
555
`endif
556 32 unneback
 
557 33 unneback
`ifdef VL_PLL3
558
`ifdef VL_PLL3_CLK1
559
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
560
`endif
561
`ifdef VL_PLL3_CLK2
562
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
563
`endif
564
`ifdef VL_PLL3_CLK3
565
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
566
`endif
567
`ifdef VL_PLL3_CLK4
568
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
569
`endif
570
`ifdef VL_PLL3_CLK5
571
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
572
`endif
573
`endif
574 32 unneback
 
575
genvar i;
576
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
577 40 unneback
`define MODULE sync_rst
578
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
579
`undef MODULE
580 32 unneback
end
581
endgenerate
582
endmodule
583
`endif
584
///////////////////////////////////////////////////////////////////////////////
585
 
586
`else
587
 
588 6 unneback
// generic PLL
589 17 unneback
`timescale 1 ps/1 ps
590 40 unneback
`define MODULE pll
591
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
592
`undef MODULE
593 6 unneback
parameter index = 0;
594
parameter number_of_clk = 1;
595 17 unneback
parameter period_time_0 = 20000;
596
parameter period_time_1 = 20000;
597
parameter period_time_2 = 20000;
598 6 unneback
parameter lock_delay = 2000;
599
input clk_i, rst_n_i;
600
output lock;
601
output reg [0:number_of_clk-1] clk_o;
602
output [0:number_of_clk-1] rst_o;
603
 
604
always
605
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
606
 
607
generate if (number_of_clk > 1)
608
always
609
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
610
endgenerate
611
 
612
generate if (number_of_clk > 2)
613
always
614
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
615
endgenerate
616
 
617
genvar i;
618
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
619 40 unneback
`define MODULE sync_rst
620
     `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
621
`undef MODULE
622 6 unneback
end
623
endgenerate
624
 
625
assign #lock_delay lock = rst_n_i;
626
 
627
endmodule
628
 
629
`endif //altera
630 17 unneback
`endif //actel
631 40 unneback
`undef MODULE
632
`endif//////////////////////////////////////////////////////////////////////
633 6 unneback
////                                                              ////
634
////  Versatile library, registers                                ////
635
////                                                              ////
636
////  Description                                                 ////
637
////  Different type of registers                                 ////
638
////                                                              ////
639
////                                                              ////
640
////  To Do:                                                      ////
641
////   - add more different registers                             ////
642
////                                                              ////
643
////  Author(s):                                                  ////
644
////      - Michael Unneback, unneback@opencores.org              ////
645
////        ORSoC AB                                              ////
646
////                                                              ////
647
//////////////////////////////////////////////////////////////////////
648
////                                                              ////
649
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
650
////                                                              ////
651
//// This source file may be used and distributed without         ////
652
//// restriction provided that this copyright statement is not    ////
653
//// removed from the file and that any derivative work contains  ////
654
//// the original copyright notice and the associated disclaimer. ////
655
////                                                              ////
656
//// This source file is free software; you can redistribute it   ////
657
//// and/or modify it under the terms of the GNU Lesser General   ////
658
//// Public License as published by the Free Software Foundation; ////
659
//// either version 2.1 of the License, or (at your option) any   ////
660
//// later version.                                               ////
661
////                                                              ////
662
//// This source is distributed in the hope that it will be       ////
663
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
664
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
665
//// PURPOSE.  See the GNU Lesser General Public License for more ////
666
//// details.                                                     ////
667
////                                                              ////
668
//// You should have received a copy of the GNU Lesser General    ////
669
//// Public License along with this source; if not, download it   ////
670
//// from http://www.opencores.org/lgpl.shtml                     ////
671
////                                                              ////
672
//////////////////////////////////////////////////////////////////////
673
 
674 40 unneback
`ifdef DFF
675
`define MODULE dff
676
module `BASE`MODULE ( d, q, clk, rst);
677
`undef MODULE
678 6 unneback
        parameter width = 1;
679
        parameter reset_value = 0;
680
 
681
        input [width-1:0] d;
682
        input clk, rst;
683
        output reg [width-1:0] q;
684
 
685
        always @ (posedge clk or posedge rst)
686
        if (rst)
687
                q <= reset_value;
688
        else
689
                q <= d;
690
 
691
endmodule
692 40 unneback
`endif
693 6 unneback
 
694 40 unneback
`ifdef DFF_ARRAY
695
`define MODULE dff_array
696
module `BASE`MODULE ( d, q, clk, rst);
697
`undef MODULE
698 6 unneback
 
699
        parameter width = 1;
700
        parameter depth = 2;
701
        parameter reset_value = 1'b0;
702
 
703
        input [width-1:0] d;
704
        input clk, rst;
705
        output [width-1:0] q;
706
        reg  [0:depth-1] q_tmp [width-1:0];
707
        integer i;
708
        always @ (posedge clk or posedge rst)
709
        if (rst) begin
710
            for (i=0;i<depth;i=i+1)
711
                q_tmp[i] <= {width{reset_value}};
712
        end else begin
713
            q_tmp[0] <= d;
714
            for (i=1;i<depth;i=i+1)
715
                q_tmp[i] <= q_tmp[i-1];
716
        end
717
 
718
    assign q = q_tmp[depth-1];
719
 
720
endmodule
721 40 unneback
`endif
722 6 unneback
 
723 40 unneback
`ifdef DFF_CE
724
`define MODULE dff_ce
725
module `BASE`MODULE ( d, ce, q, clk, rst);
726
`undef MODULE
727 6 unneback
 
728
        parameter width = 1;
729
        parameter reset_value = 0;
730
 
731
        input [width-1:0] d;
732
        input ce, clk, rst;
733
        output reg [width-1:0] q;
734
 
735
        always @ (posedge clk or posedge rst)
736
        if (rst)
737
                q <= reset_value;
738
        else
739
                if (ce)
740
                        q <= d;
741
 
742
endmodule
743 40 unneback
`endif
744 6 unneback
 
745 40 unneback
`ifdef DFF_CE_CLEAR
746
`define MODULE dff_ce_clear
747
module `BASE`MODULE ( d, ce, clear, q, clk, rst);
748
`undef MODULE
749 8 unneback
 
750
        parameter width = 1;
751
        parameter reset_value = 0;
752
 
753
        input [width-1:0] d;
754 10 unneback
        input ce, clear, clk, rst;
755 8 unneback
        output reg [width-1:0] q;
756
 
757
        always @ (posedge clk or posedge rst)
758
        if (rst)
759
            q <= reset_value;
760
        else
761
            if (ce)
762
                if (clear)
763
                    q <= {width{1'b0}};
764
                else
765
                    q <= d;
766
 
767
endmodule
768 40 unneback
`endif
769 8 unneback
 
770 40 unneback
`ifdef DF_CE_SET
771
`define MODULE dff_ce_set
772
module `BASE`MODULE ( d, ce, set, q, clk, rst);
773
`undef MODULE
774 24 unneback
 
775
        parameter width = 1;
776
        parameter reset_value = 0;
777
 
778
        input [width-1:0] d;
779
        input ce, set, clk, rst;
780
        output reg [width-1:0] q;
781
 
782
        always @ (posedge clk or posedge rst)
783
        if (rst)
784
            q <= reset_value;
785
        else
786
            if (ce)
787
                if (set)
788
                    q <= {width{1'b1}};
789
                else
790
                    q <= d;
791
 
792
endmodule
793 40 unneback
`endif
794 24 unneback
 
795 40 unneback
`ifdef SPR
796
`define MODULE spr
797
module `BASE`MODULE ( sp, r, q, clk, rst);
798
`undef MODULE
799
 
800 29 unneback
        parameter width = 1;
801
        parameter reset_value = 0;
802
 
803
        input sp, r;
804
        output reg q;
805
        input clk, rst;
806
 
807
        always @ (posedge clk or posedge rst)
808
        if (rst)
809
            q <= reset_value;
810
        else
811
            if (sp)
812
                q <= 1'b1;
813
            else if (r)
814
                q <= 1'b0;
815
 
816
endmodule
817 40 unneback
`endif
818 29 unneback
 
819 40 unneback
`ifdef SRP
820
`define MODULE srp
821
module `BASE`MODULE ( s, rp, q, clk, rst);
822
`undef MODULE
823
 
824 29 unneback
        parameter width = 1;
825
        parameter reset_value = 0;
826
 
827
        input s, rp;
828
        output reg q;
829
        input clk, rst;
830
 
831
        always @ (posedge clk or posedge rst)
832
        if (rst)
833
            q <= reset_value;
834
        else
835
            if (rp)
836
                q <= 1'b0;
837
            else if (s)
838
                q <= 1'b1;
839
 
840
endmodule
841 40 unneback
`endif
842 29 unneback
 
843 40 unneback
`ifdef ALTERA
844 29 unneback
 
845 40 unneback
`ifdef DFF_SR
846 6 unneback
// megafunction wizard: %LPM_FF%
847
// GENERATION: STANDARD
848
// VERSION: WM1.0
849
// MODULE: lpm_ff 
850
 
851
// ============================================================
852
// File Name: dff_sr.v
853
// Megafunction Name(s):
854
//                      lpm_ff
855
//
856
// Simulation Library Files(s):
857
//                      lpm
858
// ============================================================
859
// ************************************************************
860
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
861
//
862
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
863
// ************************************************************
864
 
865
 
866
//Copyright (C) 1991-2010 Altera Corporation
867
//Your use of Altera Corporation's design tools, logic functions 
868
//and other software and tools, and its AMPP partner logic 
869
//functions, and any output files from any of the foregoing 
870
//(including device programming or simulation files), and any 
871
//associated documentation or information are expressly subject 
872
//to the terms and conditions of the Altera Program License 
873
//Subscription Agreement, Altera MegaCore Function License 
874
//Agreement, or other applicable license agreement, including, 
875
//without limitation, that your use is for the sole purpose of 
876
//programming logic devices manufactured by Altera and sold by 
877
//Altera or its authorized distributors.  Please refer to the 
878
//applicable agreement for further details.
879
 
880
 
881
// synopsys translate_off
882
`timescale 1 ps / 1 ps
883
// synopsys translate_on
884 40 unneback
`define MODULE dff_sr
885
module `BASE`MODULE (
886
`undef MODULE
887
 
888 6 unneback
        aclr,
889
        aset,
890
        clock,
891
        data,
892
        q);
893
 
894
        input     aclr;
895
        input     aset;
896
        input     clock;
897
        input     data;
898
        output    q;
899
 
900
        wire [0:0] sub_wire0;
901
        wire [0:0] sub_wire1 = sub_wire0[0:0];
902
        wire  q = sub_wire1;
903
        wire  sub_wire2 = data;
904
        wire  sub_wire3 = sub_wire2;
905
 
906
        lpm_ff  lpm_ff_component (
907
                                .aclr (aclr),
908
                                .clock (clock),
909
                                .data (sub_wire3),
910
                                .aset (aset),
911
                                .q (sub_wire0)
912
                                // synopsys translate_off
913
                                ,
914
                                .aload (),
915
                                .enable (),
916
                                .sclr (),
917
                                .sload (),
918
                                .sset ()
919
                                // synopsys translate_on
920
                                );
921
        defparam
922
                lpm_ff_component.lpm_fftype = "DFF",
923
                lpm_ff_component.lpm_type = "LPM_FF",
924
                lpm_ff_component.lpm_width = 1;
925
 
926
 
927
endmodule
928
 
929
// ============================================================
930
// CNX file retrieval info
931
// ============================================================
932
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
933
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
934
// Retrieval info: PRIVATE: ASET NUMERIC "1"
935
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
936
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
937
// Retrieval info: PRIVATE: DFF NUMERIC "1"
938
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
939
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
940
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
941
// Retrieval info: PRIVATE: SSET NUMERIC "0"
942
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
943
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
944
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
945
// Retrieval info: PRIVATE: nBit NUMERIC "1"
946
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
947
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
948
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
949
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
950
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
951
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
952
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
953
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
954
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
955
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
956
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
957
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
958
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
959
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
960
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
961
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
962
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
963
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
964
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
965
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
966
// Retrieval info: LIB_FILE: lpm
967 40 unneback
`endif
968 6 unneback
 
969
`else
970
 
971 40 unneback
`ifdef DFF_SR
972
`define MODULE dff_sr
973
module `BASE`MODULE ( aclr, aset, clock, data, q);
974
`undef MODULE
975 6 unneback
 
976
    input         aclr;
977
    input         aset;
978
    input         clock;
979
    input         data;
980
    output reg    q;
981
 
982
   always @ (posedge clock or posedge aclr or posedge aset)
983
     if (aclr)
984
       q <= 1'b0;
985
     else if (aset)
986
       q <= 1'b1;
987
     else
988
       q <= data;
989
 
990
endmodule
991 40 unneback
`endif
992 6 unneback
 
993
`endif
994
 
995
// LATCH
996
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
997
`ifdef ALTERA
998 40 unneback
 
999
`ifdef LATCH
1000
`define MODULE latch
1001
module `BASE`MODULE ( d, le, q, clk);
1002
`undef MODULE
1003 6 unneback
input d, le;
1004
output q;
1005
input clk;
1006
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
1007
endmodule
1008 40 unneback
`endif
1009
 
1010 6 unneback
`else
1011 40 unneback
 
1012
`ifdef LATCH
1013
`define MODULE latch
1014
module `BASE`MODULE ( d, le, q, clk);
1015
`undef MODULE
1016 6 unneback
input d, le;
1017
output q;
1018
input clk;/*
1019
   always @ (posedge direction_set or posedge direction_clr)
1020
     if (direction_clr)
1021
       direction <= going_empty;
1022
     else
1023
       direction <= going_full;*/
1024
endmodule
1025 15 unneback
`endif
1026
 
1027 40 unneback
`endif
1028
 
1029
`ifdef SHREG
1030
`define MODULE shreg
1031
module `BASE`MODULE ( d, q, clk, rst);
1032
`undef MODULE
1033
 
1034 17 unneback
parameter depth = 10;
1035
input d;
1036
output q;
1037
input clk, rst;
1038
 
1039
reg [1:depth] dffs;
1040
 
1041
always @ (posedge clk or posedge rst)
1042
if (rst)
1043
    dffs <= {depth{1'b0}};
1044
else
1045
    dffs <= {d,dffs[1:depth-1]};
1046
assign q = dffs[depth];
1047
endmodule
1048 40 unneback
`endif
1049 17 unneback
 
1050 40 unneback
`ifdef SHREG_CE
1051
`define MODULE shreg_ce
1052
module `BASE`MODULE ( d, ce, q, clk, rst);
1053
`undef MODULE
1054 17 unneback
parameter depth = 10;
1055
input d, ce;
1056
output q;
1057
input clk, rst;
1058
 
1059
reg [1:depth] dffs;
1060
 
1061
always @ (posedge clk or posedge rst)
1062
if (rst)
1063
    dffs <= {depth{1'b0}};
1064
else
1065
    if (ce)
1066
        dffs <= {d,dffs[1:depth-1]};
1067
assign q = dffs[depth];
1068
endmodule
1069 40 unneback
`endif
1070 17 unneback
 
1071 40 unneback
`ifdef DELAY
1072
`define MODULE delay
1073
module `BASE`MODULE ( d, q, clk, rst);
1074
`undef MODULE
1075 15 unneback
parameter depth = 10;
1076
input d;
1077
output q;
1078
input clk, rst;
1079
 
1080
reg [1:depth] dffs;
1081
 
1082
always @ (posedge clk or posedge rst)
1083
if (rst)
1084
    dffs <= {depth{1'b0}};
1085
else
1086
    dffs <= {d,dffs[1:depth-1]};
1087
assign q = dffs[depth];
1088 17 unneback
endmodule
1089 40 unneback
`endif
1090 17 unneback
 
1091 40 unneback
`ifdef DELAY_EMPTYFLAG
1092
`define MODULE delay_emptyflag
1093 41 unneback
module `BASE`MODULE ( d, q, emptyflag, clk, rst);
1094 40 unneback
`undef MODULE
1095 17 unneback
parameter depth = 10;
1096
input d;
1097
output q, emptyflag;
1098
input clk, rst;
1099
 
1100
reg [1:depth] dffs;
1101
 
1102
always @ (posedge clk or posedge rst)
1103
if (rst)
1104
    dffs <= {depth{1'b0}};
1105
else
1106
    dffs <= {d,dffs[1:depth-1]};
1107
assign q = dffs[depth];
1108
assign emptyflag = !(|dffs);
1109
endmodule
1110 40 unneback
`endif
1111 17 unneback
//////////////////////////////////////////////////////////////////////
1112 6 unneback
////                                                              ////
1113 18 unneback
////  Logic functions                                             ////
1114
////                                                              ////
1115
////  Description                                                 ////
1116
////  Logic functions such as multiplexers                        ////
1117
////                                                              ////
1118
////                                                              ////
1119
////  To Do:                                                      ////
1120
////   -                                                          ////
1121
////                                                              ////
1122
////  Author(s):                                                  ////
1123
////      - Michael Unneback, unneback@opencores.org              ////
1124
////        ORSoC AB                                              ////
1125
////                                                              ////
1126
//////////////////////////////////////////////////////////////////////
1127
////                                                              ////
1128
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1129
////                                                              ////
1130
//// This source file may be used and distributed without         ////
1131
//// restriction provided that this copyright statement is not    ////
1132
//// removed from the file and that any derivative work contains  ////
1133
//// the original copyright notice and the associated disclaimer. ////
1134
////                                                              ////
1135
//// This source file is free software; you can redistribute it   ////
1136
//// and/or modify it under the terms of the GNU Lesser General   ////
1137
//// Public License as published by the Free Software Foundation; ////
1138
//// either version 2.1 of the License, or (at your option) any   ////
1139
//// later version.                                               ////
1140
////                                                              ////
1141
//// This source is distributed in the hope that it will be       ////
1142
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1143
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1144
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1145
//// details.                                                     ////
1146
////                                                              ////
1147
//// You should have received a copy of the GNU Lesser General    ////
1148
//// Public License along with this source; if not, download it   ////
1149
//// from http://www.opencores.org/lgpl.shtml                     ////
1150
////                                                              ////
1151
//////////////////////////////////////////////////////////////////////
1152 40 unneback
`ifdef MUX_ANDOR
1153
`define MODULE mux_andor
1154
module `BASE`MODULE ( a, sel, dout);
1155
`undef MODULE
1156 36 unneback
 
1157
parameter width = 32;
1158
parameter nr_of_ports = 4;
1159
 
1160
input [nr_of_ports*width-1:0] a;
1161
input [nr_of_ports-1:0] sel;
1162
output reg [width-1:0] dout;
1163
 
1164 38 unneback
integer i,j;
1165
 
1166 36 unneback
always @ (a, sel)
1167
begin
1168
    dout = a[width-1:0] & {width{sel[0]}};
1169
    for (i=nr_of_ports-2;i<nr_of_ports;i=i+1)
1170 38 unneback
        for (j=0;j<32;j=j+1)
1171
            dout[j] = (a[(i-1)*width + j] & sel[i]) | dout[j];
1172 36 unneback
end
1173
 
1174
endmodule
1175 40 unneback
`endif
1176 36 unneback
 
1177 40 unneback
`ifdef MUX2_ANDOR
1178
`define MODULE mux2_andor
1179
module `BASE`MODULE ( a1, a0, sel, dout);
1180
`undef MODULE
1181 18 unneback
 
1182 34 unneback
parameter width = 32;
1183 35 unneback
localparam nr_of_ports = 2;
1184 34 unneback
input [width-1:0] a1, a0;
1185
input [nr_of_ports-1:0] sel;
1186
output [width-1:0] dout;
1187
 
1188 40 unneback
`define MODULE mux_andor
1189
`BASE`MODULE
1190 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1191 36 unneback
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
1192 40 unneback
`undef MODULE
1193
 
1194 34 unneback
endmodule
1195 40 unneback
`endif
1196 34 unneback
 
1197 40 unneback
`ifdef MUX3_ANDOR
1198
`define MODULE mux3_andor
1199
module `BASE`MODULE ( a2, a1, a0, sel, dout);
1200
`undef MODULE
1201 34 unneback
 
1202
parameter width = 32;
1203 35 unneback
localparam nr_of_ports = 3;
1204 34 unneback
input [width-1:0] a2, a1, a0;
1205
input [nr_of_ports-1:0] sel;
1206
output [width-1:0] dout;
1207
 
1208 40 unneback
`define MODULE mux_andor
1209
`BASE`MODULE
1210 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1211 36 unneback
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
1212 40 unneback
`undef MODULE
1213 34 unneback
endmodule
1214 40 unneback
`endif
1215 34 unneback
 
1216 40 unneback
`ifdef MUX4_ANDOR
1217
`define MODULE mux4_andor
1218
module `BASE`MODULE ( a3, a2, a1, a0, sel, dout);
1219
`undef MODULE
1220 18 unneback
 
1221
parameter width = 32;
1222 35 unneback
localparam nr_of_ports = 4;
1223 18 unneback
input [width-1:0] a3, a2, a1, a0;
1224
input [nr_of_ports-1:0] sel;
1225 22 unneback
output [width-1:0] dout;
1226 18 unneback
 
1227 40 unneback
`define MODULE mux_andor
1228
`BASE`MODULE
1229 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1230 36 unneback
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
1231 40 unneback
`undef MODULE
1232 18 unneback
 
1233
endmodule
1234 40 unneback
`endif
1235 18 unneback
 
1236 40 unneback
`ifdef MUX5_ANDOR
1237
`define MODULE mux5_andor
1238
module `BASE`MODULE ( a4, a3, a2, a1, a0, sel, dout);
1239
`undef MODULE
1240 18 unneback
 
1241
parameter width = 32;
1242 35 unneback
localparam nr_of_ports = 5;
1243 18 unneback
input [width-1:0] a4, a3, a2, a1, a0;
1244
input [nr_of_ports-1:0] sel;
1245 22 unneback
output [width-1:0] dout;
1246 18 unneback
 
1247 40 unneback
`define MODULE mux_andor
1248
`BASE`MODULE
1249 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1250 36 unneback
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1251 40 unneback
`undef MODULE
1252 18 unneback
 
1253
endmodule
1254 40 unneback
`endif
1255 18 unneback
 
1256 40 unneback
`ifdef MUX6_ANDOR
1257
`define MODULE mux6_andor
1258
module `BASE`MODULE ( a5, a4, a3, a2, a1, a0, sel, dout);
1259
`undef MODULE
1260 18 unneback
 
1261
parameter width = 32;
1262 35 unneback
localparam nr_of_ports = 6;
1263 18 unneback
input [width-1:0] a5, a4, a3, a2, a1, a0;
1264
input [nr_of_ports-1:0] sel;
1265 22 unneback
output [width-1:0] dout;
1266 18 unneback
 
1267 40 unneback
`define MODULE mux_andor
1268
`BASE`MODULE
1269 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1270 36 unneback
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1271 40 unneback
`undef MODULE
1272 18 unneback
 
1273
endmodule
1274 40 unneback
`endif
1275
`ifdef CNT_BIN
1276 18 unneback
//////////////////////////////////////////////////////////////////////
1277
////                                                              ////
1278 6 unneback
////  Versatile counter                                           ////
1279
////                                                              ////
1280
////  Description                                                 ////
1281
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1282
////  counter                                                     ////
1283
////                                                              ////
1284
////  To Do:                                                      ////
1285
////   - add LFSR with more taps                                  ////
1286
////                                                              ////
1287
////  Author(s):                                                  ////
1288
////      - Michael Unneback, unneback@opencores.org              ////
1289
////        ORSoC AB                                              ////
1290
////                                                              ////
1291
//////////////////////////////////////////////////////////////////////
1292
////                                                              ////
1293
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1294
////                                                              ////
1295
//// This source file may be used and distributed without         ////
1296
//// restriction provided that this copyright statement is not    ////
1297
//// removed from the file and that any derivative work contains  ////
1298
//// the original copyright notice and the associated disclaimer. ////
1299
////                                                              ////
1300
//// This source file is free software; you can redistribute it   ////
1301
//// and/or modify it under the terms of the GNU Lesser General   ////
1302
//// Public License as published by the Free Software Foundation; ////
1303
//// either version 2.1 of the License, or (at your option) any   ////
1304
//// later version.                                               ////
1305
////                                                              ////
1306
//// This source is distributed in the hope that it will be       ////
1307
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1308
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1309
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1310
//// details.                                                     ////
1311
////                                                              ////
1312
//// You should have received a copy of the GNU Lesser General    ////
1313
//// Public License along with this source; if not, download it   ////
1314
//// from http://www.opencores.org/lgpl.shtml                     ////
1315
////                                                              ////
1316
//////////////////////////////////////////////////////////////////////
1317
 
1318
// binary counter
1319 22 unneback
 
1320 40 unneback
`define MODULE cnt_bin
1321
module `BASE`MODULE (
1322
`undef MODULE
1323
 q, rst, clk);
1324
 
1325 22 unneback
   parameter length = 4;
1326
   output [length:1] q;
1327
   input rst;
1328
   input clk;
1329
 
1330
   parameter clear_value = 0;
1331
   parameter set_value = 1;
1332
   parameter wrap_value = 0;
1333
   parameter level1_value = 15;
1334
 
1335
   reg  [length:1] qi;
1336
   wire [length:1] q_next;
1337
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1338
 
1339
   always @ (posedge clk or posedge rst)
1340
     if (rst)
1341
       qi <= {length{1'b0}};
1342
     else
1343
       qi <= q_next;
1344
 
1345
   assign q = qi;
1346
 
1347
endmodule
1348 40 unneback
`endif
1349
`ifdef CNT_BIN_CLEAR
1350 22 unneback
//////////////////////////////////////////////////////////////////////
1351
////                                                              ////
1352
////  Versatile counter                                           ////
1353
////                                                              ////
1354
////  Description                                                 ////
1355
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1356
////  counter                                                     ////
1357
////                                                              ////
1358
////  To Do:                                                      ////
1359
////   - add LFSR with more taps                                  ////
1360
////                                                              ////
1361
////  Author(s):                                                  ////
1362
////      - Michael Unneback, unneback@opencores.org              ////
1363
////        ORSoC AB                                              ////
1364
////                                                              ////
1365
//////////////////////////////////////////////////////////////////////
1366
////                                                              ////
1367
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1368
////                                                              ////
1369
//// This source file may be used and distributed without         ////
1370
//// restriction provided that this copyright statement is not    ////
1371
//// removed from the file and that any derivative work contains  ////
1372
//// the original copyright notice and the associated disclaimer. ////
1373
////                                                              ////
1374
//// This source file is free software; you can redistribute it   ////
1375
//// and/or modify it under the terms of the GNU Lesser General   ////
1376
//// Public License as published by the Free Software Foundation; ////
1377
//// either version 2.1 of the License, or (at your option) any   ////
1378
//// later version.                                               ////
1379
////                                                              ////
1380
//// This source is distributed in the hope that it will be       ////
1381
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1382
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1383
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1384
//// details.                                                     ////
1385
////                                                              ////
1386
//// You should have received a copy of the GNU Lesser General    ////
1387
//// Public License along with this source; if not, download it   ////
1388
//// from http://www.opencores.org/lgpl.shtml                     ////
1389
////                                                              ////
1390
//////////////////////////////////////////////////////////////////////
1391
 
1392
// binary counter
1393
 
1394 40 unneback
`define MODULE cnt_bin_clear
1395
module `BASE`MODULE (
1396
`undef MODULE
1397
 clear, q, rst, clk);
1398
 
1399 22 unneback
   parameter length = 4;
1400
   input clear;
1401
   output [length:1] q;
1402
   input rst;
1403
   input clk;
1404
 
1405
   parameter clear_value = 0;
1406
   parameter set_value = 1;
1407
   parameter wrap_value = 0;
1408
   parameter level1_value = 15;
1409
 
1410
   reg  [length:1] qi;
1411
   wire [length:1] q_next;
1412
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1413
 
1414
   always @ (posedge clk or posedge rst)
1415
     if (rst)
1416
       qi <= {length{1'b0}};
1417
     else
1418
       qi <= q_next;
1419
 
1420
   assign q = qi;
1421
 
1422
endmodule
1423 40 unneback
`endif
1424
`ifdef CNT_BIN_CE
1425 22 unneback
//////////////////////////////////////////////////////////////////////
1426
////                                                              ////
1427
////  Versatile counter                                           ////
1428
////                                                              ////
1429
////  Description                                                 ////
1430
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1431
////  counter                                                     ////
1432
////                                                              ////
1433
////  To Do:                                                      ////
1434
////   - add LFSR with more taps                                  ////
1435
////                                                              ////
1436
////  Author(s):                                                  ////
1437
////      - Michael Unneback, unneback@opencores.org              ////
1438
////        ORSoC AB                                              ////
1439
////                                                              ////
1440
//////////////////////////////////////////////////////////////////////
1441
////                                                              ////
1442
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1443
////                                                              ////
1444
//// This source file may be used and distributed without         ////
1445
//// restriction provided that this copyright statement is not    ////
1446
//// removed from the file and that any derivative work contains  ////
1447
//// the original copyright notice and the associated disclaimer. ////
1448
////                                                              ////
1449
//// This source file is free software; you can redistribute it   ////
1450
//// and/or modify it under the terms of the GNU Lesser General   ////
1451
//// Public License as published by the Free Software Foundation; ////
1452
//// either version 2.1 of the License, or (at your option) any   ////
1453
//// later version.                                               ////
1454
////                                                              ////
1455
//// This source is distributed in the hope that it will be       ////
1456
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1457
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1458
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1459
//// details.                                                     ////
1460
////                                                              ////
1461
//// You should have received a copy of the GNU Lesser General    ////
1462
//// Public License along with this source; if not, download it   ////
1463
//// from http://www.opencores.org/lgpl.shtml                     ////
1464
////                                                              ////
1465
//////////////////////////////////////////////////////////////////////
1466
 
1467
// binary counter
1468 6 unneback
 
1469 40 unneback
`define MODULE cnt_bin_ce
1470
module `BASE`MODULE (
1471
`undef MODULE
1472
 cke, q, rst, clk);
1473
 
1474 6 unneback
   parameter length = 4;
1475
   input cke;
1476
   output [length:1] q;
1477
   input rst;
1478
   input clk;
1479
 
1480
   parameter clear_value = 0;
1481
   parameter set_value = 1;
1482
   parameter wrap_value = 0;
1483
   parameter level1_value = 15;
1484
 
1485
   reg  [length:1] qi;
1486
   wire [length:1] q_next;
1487
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1488
 
1489
   always @ (posedge clk or posedge rst)
1490
     if (rst)
1491
       qi <= {length{1'b0}};
1492
     else
1493
     if (cke)
1494
       qi <= q_next;
1495
 
1496
   assign q = qi;
1497
 
1498
endmodule
1499 40 unneback
`endif
1500
`ifdef CNT_BIN_CE_CLEAR
1501 6 unneback
//////////////////////////////////////////////////////////////////////
1502
////                                                              ////
1503
////  Versatile counter                                           ////
1504
////                                                              ////
1505
////  Description                                                 ////
1506
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1507
////  counter                                                     ////
1508
////                                                              ////
1509
////  To Do:                                                      ////
1510
////   - add LFSR with more taps                                  ////
1511
////                                                              ////
1512
////  Author(s):                                                  ////
1513
////      - Michael Unneback, unneback@opencores.org              ////
1514
////        ORSoC AB                                              ////
1515
////                                                              ////
1516
//////////////////////////////////////////////////////////////////////
1517
////                                                              ////
1518
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1519
////                                                              ////
1520
//// This source file may be used and distributed without         ////
1521
//// restriction provided that this copyright statement is not    ////
1522
//// removed from the file and that any derivative work contains  ////
1523
//// the original copyright notice and the associated disclaimer. ////
1524
////                                                              ////
1525
//// This source file is free software; you can redistribute it   ////
1526
//// and/or modify it under the terms of the GNU Lesser General   ////
1527
//// Public License as published by the Free Software Foundation; ////
1528
//// either version 2.1 of the License, or (at your option) any   ////
1529
//// later version.                                               ////
1530
////                                                              ////
1531
//// This source is distributed in the hope that it will be       ////
1532
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1533
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1534
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1535
//// details.                                                     ////
1536
////                                                              ////
1537
//// You should have received a copy of the GNU Lesser General    ////
1538
//// Public License along with this source; if not, download it   ////
1539
//// from http://www.opencores.org/lgpl.shtml                     ////
1540
////                                                              ////
1541
//////////////////////////////////////////////////////////////////////
1542
 
1543
// binary counter
1544
 
1545 40 unneback
`define MODULE cnt_bin_ce_clear
1546
module `BASE`MODULE (
1547
`undef MODULE
1548
 clear, cke, q, rst, clk);
1549
 
1550 6 unneback
   parameter length = 4;
1551
   input clear;
1552
   input cke;
1553
   output [length:1] q;
1554
   input rst;
1555
   input clk;
1556
 
1557
   parameter clear_value = 0;
1558
   parameter set_value = 1;
1559
   parameter wrap_value = 0;
1560
   parameter level1_value = 15;
1561
 
1562
   reg  [length:1] qi;
1563
   wire [length:1] q_next;
1564
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1565
 
1566
   always @ (posedge clk or posedge rst)
1567
     if (rst)
1568
       qi <= {length{1'b0}};
1569
     else
1570
     if (cke)
1571
       qi <= q_next;
1572
 
1573
   assign q = qi;
1574
 
1575
endmodule
1576 40 unneback
`endif
1577
`ifdef CNT_BIN_CE_CLEAR_L1_L2
1578 6 unneback
//////////////////////////////////////////////////////////////////////
1579
////                                                              ////
1580
////  Versatile counter                                           ////
1581
////                                                              ////
1582
////  Description                                                 ////
1583
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1584
////  counter                                                     ////
1585
////                                                              ////
1586
////  To Do:                                                      ////
1587
////   - add LFSR with more taps                                  ////
1588
////                                                              ////
1589
////  Author(s):                                                  ////
1590
////      - Michael Unneback, unneback@opencores.org              ////
1591
////        ORSoC AB                                              ////
1592
////                                                              ////
1593
//////////////////////////////////////////////////////////////////////
1594
////                                                              ////
1595
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1596
////                                                              ////
1597
//// This source file may be used and distributed without         ////
1598
//// restriction provided that this copyright statement is not    ////
1599
//// removed from the file and that any derivative work contains  ////
1600
//// the original copyright notice and the associated disclaimer. ////
1601
////                                                              ////
1602
//// This source file is free software; you can redistribute it   ////
1603
//// and/or modify it under the terms of the GNU Lesser General   ////
1604
//// Public License as published by the Free Software Foundation; ////
1605
//// either version 2.1 of the License, or (at your option) any   ////
1606
//// later version.                                               ////
1607
////                                                              ////
1608
//// This source is distributed in the hope that it will be       ////
1609
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1610
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1611
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1612
//// details.                                                     ////
1613
////                                                              ////
1614
//// You should have received a copy of the GNU Lesser General    ////
1615
//// Public License along with this source; if not, download it   ////
1616
//// from http://www.opencores.org/lgpl.shtml                     ////
1617
////                                                              ////
1618
//////////////////////////////////////////////////////////////////////
1619
 
1620
// binary counter
1621 29 unneback
 
1622 40 unneback
`define MODULE cnt_bin_ce_clear_l1_l2
1623
module `BASE`MODULE (
1624
`undef MODULE
1625
 clear, cke, q, level1, level2, rst, clk);
1626
 
1627 29 unneback
   parameter length = 4;
1628
   input clear;
1629
   input cke;
1630
   output [length:1] q;
1631
   output reg level1;
1632
   output reg level2;
1633
   input rst;
1634
   input clk;
1635
 
1636
   parameter clear_value = 0;
1637
   parameter set_value = 1;
1638 30 unneback
   parameter wrap_value = 15;
1639
   parameter level1_value = 8;
1640
   parameter level2_value = 15;
1641 29 unneback
 
1642
   wire rew;
1643 30 unneback
   assign rew = 1'b0;
1644 29 unneback
   reg  [length:1] qi;
1645
   wire [length:1] q_next;
1646
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1647
 
1648
   always @ (posedge clk or posedge rst)
1649
     if (rst)
1650
       qi <= {length{1'b0}};
1651
     else
1652
     if (cke)
1653
       qi <= q_next;
1654
 
1655
   assign q = qi;
1656
 
1657
 
1658
    always @ (posedge clk or posedge rst)
1659
    if (rst)
1660
        level1 <= 1'b0;
1661
    else
1662
    if (cke)
1663
    if (clear)
1664
        level1 <= 1'b0;
1665
    else if (q_next == level1_value)
1666
        level1 <= 1'b1;
1667
    else if (qi == level1_value & rew)
1668
        level1 <= 1'b0;
1669
 
1670
    always @ (posedge clk or posedge rst)
1671
    if (rst)
1672
        level2 <= 1'b0;
1673
    else
1674
    if (cke)
1675
    if (clear)
1676
        level2 <= 1'b0;
1677
    else if (q_next == level2_value)
1678
        level2 <= 1'b1;
1679
    else if (qi == level2_value & rew)
1680
        level2 <= 1'b0;
1681
endmodule
1682 40 unneback
`endif
1683
`ifdef CNT_BIN_CE_CLEAR_SET_REW
1684 29 unneback
//////////////////////////////////////////////////////////////////////
1685
////                                                              ////
1686
////  Versatile counter                                           ////
1687
////                                                              ////
1688
////  Description                                                 ////
1689
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1690
////  counter                                                     ////
1691
////                                                              ////
1692
////  To Do:                                                      ////
1693
////   - add LFSR with more taps                                  ////
1694
////                                                              ////
1695
////  Author(s):                                                  ////
1696
////      - Michael Unneback, unneback@opencores.org              ////
1697
////        ORSoC AB                                              ////
1698
////                                                              ////
1699
//////////////////////////////////////////////////////////////////////
1700
////                                                              ////
1701
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1702
////                                                              ////
1703
//// This source file may be used and distributed without         ////
1704
//// restriction provided that this copyright statement is not    ////
1705
//// removed from the file and that any derivative work contains  ////
1706
//// the original copyright notice and the associated disclaimer. ////
1707
////                                                              ////
1708
//// This source file is free software; you can redistribute it   ////
1709
//// and/or modify it under the terms of the GNU Lesser General   ////
1710
//// Public License as published by the Free Software Foundation; ////
1711
//// either version 2.1 of the License, or (at your option) any   ////
1712
//// later version.                                               ////
1713
////                                                              ////
1714
//// This source is distributed in the hope that it will be       ////
1715
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1716
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1717
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1718
//// details.                                                     ////
1719
////                                                              ////
1720
//// You should have received a copy of the GNU Lesser General    ////
1721
//// Public License along with this source; if not, download it   ////
1722
//// from http://www.opencores.org/lgpl.shtml                     ////
1723
////                                                              ////
1724
//////////////////////////////////////////////////////////////////////
1725
 
1726
// binary counter
1727 6 unneback
 
1728 40 unneback
`define MODULE cnt_bin_ce_clear_set_rew
1729
module `BASE`MODULE (
1730
`undef MODULE
1731
 clear, set, cke, rew, q, rst, clk);
1732
 
1733 6 unneback
   parameter length = 4;
1734
   input clear;
1735
   input set;
1736
   input cke;
1737
   input rew;
1738
   output [length:1] q;
1739
   input rst;
1740
   input clk;
1741
 
1742
   parameter clear_value = 0;
1743
   parameter set_value = 1;
1744
   parameter wrap_value = 0;
1745
   parameter level1_value = 15;
1746
 
1747
   reg  [length:1] qi;
1748
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1749
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
1750
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
1751
   assign q_next = rew ? q_next_rew : q_next_fw;
1752
 
1753
   always @ (posedge clk or posedge rst)
1754
     if (rst)
1755
       qi <= {length{1'b0}};
1756
     else
1757
     if (cke)
1758
       qi <= q_next;
1759
 
1760
   assign q = qi;
1761
 
1762
endmodule
1763 40 unneback
`endif
1764
`ifdef CNT_BIN_CE_REW_L1
1765 6 unneback
//////////////////////////////////////////////////////////////////////
1766
////                                                              ////
1767
////  Versatile counter                                           ////
1768
////                                                              ////
1769
////  Description                                                 ////
1770
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1771
////  counter                                                     ////
1772
////                                                              ////
1773
////  To Do:                                                      ////
1774
////   - add LFSR with more taps                                  ////
1775
////                                                              ////
1776
////  Author(s):                                                  ////
1777
////      - Michael Unneback, unneback@opencores.org              ////
1778
////        ORSoC AB                                              ////
1779
////                                                              ////
1780
//////////////////////////////////////////////////////////////////////
1781
////                                                              ////
1782
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1783
////                                                              ////
1784
//// This source file may be used and distributed without         ////
1785
//// restriction provided that this copyright statement is not    ////
1786
//// removed from the file and that any derivative work contains  ////
1787
//// the original copyright notice and the associated disclaimer. ////
1788
////                                                              ////
1789
//// This source file is free software; you can redistribute it   ////
1790
//// and/or modify it under the terms of the GNU Lesser General   ////
1791
//// Public License as published by the Free Software Foundation; ////
1792
//// either version 2.1 of the License, or (at your option) any   ////
1793
//// later version.                                               ////
1794
////                                                              ////
1795
//// This source is distributed in the hope that it will be       ////
1796
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1797
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1798
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1799
//// details.                                                     ////
1800
////                                                              ////
1801
//// You should have received a copy of the GNU Lesser General    ////
1802
//// Public License along with this source; if not, download it   ////
1803
//// from http://www.opencores.org/lgpl.shtml                     ////
1804
////                                                              ////
1805
//////////////////////////////////////////////////////////////////////
1806
 
1807
// binary counter
1808
 
1809 40 unneback
`define MODULE cnt_bin_ce_rew_l1
1810
module `BASE`MODULE (
1811
`undef MODULE
1812
 cke, rew, level1, rst, clk);
1813
 
1814 6 unneback
   parameter length = 4;
1815
   input cke;
1816
   input rew;
1817
   output reg level1;
1818
   input rst;
1819
   input clk;
1820
 
1821
   parameter clear_value = 0;
1822
   parameter set_value = 1;
1823
   parameter wrap_value = 1;
1824
   parameter level1_value = 15;
1825
 
1826 29 unneback
   wire clear;
1827 30 unneback
   assign clear = 1'b0;
1828 6 unneback
   reg  [length:1] qi;
1829
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1830
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1831
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1832
   assign q_next = rew ? q_next_rew : q_next_fw;
1833
 
1834
   always @ (posedge clk or posedge rst)
1835
     if (rst)
1836
       qi <= {length{1'b0}};
1837
     else
1838
     if (cke)
1839
       qi <= q_next;
1840
 
1841
 
1842
 
1843
    always @ (posedge clk or posedge rst)
1844
    if (rst)
1845
        level1 <= 1'b0;
1846
    else
1847
    if (cke)
1848 29 unneback
    if (clear)
1849
        level1 <= 1'b0;
1850
    else if (q_next == level1_value)
1851 6 unneback
        level1 <= 1'b1;
1852
    else if (qi == level1_value & rew)
1853
        level1 <= 1'b0;
1854
endmodule
1855 40 unneback
`endif
1856
`ifdef CNT_BIN_CE_REW_ZQ_L1
1857 6 unneback
//////////////////////////////////////////////////////////////////////
1858
////                                                              ////
1859
////  Versatile counter                                           ////
1860
////                                                              ////
1861
////  Description                                                 ////
1862
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1863
////  counter                                                     ////
1864
////                                                              ////
1865
////  To Do:                                                      ////
1866
////   - add LFSR with more taps                                  ////
1867
////                                                              ////
1868
////  Author(s):                                                  ////
1869
////      - Michael Unneback, unneback@opencores.org              ////
1870
////        ORSoC AB                                              ////
1871
////                                                              ////
1872
//////////////////////////////////////////////////////////////////////
1873
////                                                              ////
1874
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1875
////                                                              ////
1876
//// This source file may be used and distributed without         ////
1877
//// restriction provided that this copyright statement is not    ////
1878
//// removed from the file and that any derivative work contains  ////
1879
//// the original copyright notice and the associated disclaimer. ////
1880
////                                                              ////
1881
//// This source file is free software; you can redistribute it   ////
1882
//// and/or modify it under the terms of the GNU Lesser General   ////
1883
//// Public License as published by the Free Software Foundation; ////
1884
//// either version 2.1 of the License, or (at your option) any   ////
1885
//// later version.                                               ////
1886
////                                                              ////
1887
//// This source is distributed in the hope that it will be       ////
1888
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1889
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1890
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1891
//// details.                                                     ////
1892
////                                                              ////
1893
//// You should have received a copy of the GNU Lesser General    ////
1894
//// Public License along with this source; if not, download it   ////
1895
//// from http://www.opencores.org/lgpl.shtml                     ////
1896
////                                                              ////
1897
//////////////////////////////////////////////////////////////////////
1898
 
1899 25 unneback
// binary counter
1900
 
1901 40 unneback
`define MODULE cnt_bin_ce_rew_zq_l1
1902
module `BASE`MODULE (
1903
`undef MODULE
1904
 cke, rew, zq, level1, rst, clk);
1905
 
1906 25 unneback
   parameter length = 4;
1907
   input cke;
1908
   input rew;
1909
   output reg zq;
1910
   output reg level1;
1911
   input rst;
1912
   input clk;
1913
 
1914
   parameter clear_value = 0;
1915
   parameter set_value = 1;
1916
   parameter wrap_value = 1;
1917
   parameter level1_value = 15;
1918
 
1919 29 unneback
   wire clear;
1920 30 unneback
   assign clear = 1'b0;
1921 25 unneback
   reg  [length:1] qi;
1922
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1923
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1924
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1925
   assign q_next = rew ? q_next_rew : q_next_fw;
1926
 
1927
   always @ (posedge clk or posedge rst)
1928
     if (rst)
1929
       qi <= {length{1'b0}};
1930
     else
1931
     if (cke)
1932
       qi <= q_next;
1933
 
1934
 
1935
 
1936
   always @ (posedge clk or posedge rst)
1937
     if (rst)
1938
       zq <= 1'b1;
1939
     else
1940
     if (cke)
1941
       zq <= q_next == {length{1'b0}};
1942
 
1943
    always @ (posedge clk or posedge rst)
1944
    if (rst)
1945
        level1 <= 1'b0;
1946
    else
1947
    if (cke)
1948 29 unneback
    if (clear)
1949
        level1 <= 1'b0;
1950
    else if (q_next == level1_value)
1951 25 unneback
        level1 <= 1'b1;
1952
    else if (qi == level1_value & rew)
1953
        level1 <= 1'b0;
1954
endmodule
1955 40 unneback
`endif
1956
`ifdef CNT_BIN_CE_REW_Q_ZQ_L1
1957 25 unneback
//////////////////////////////////////////////////////////////////////
1958
////                                                              ////
1959
////  Versatile counter                                           ////
1960
////                                                              ////
1961
////  Description                                                 ////
1962
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1963
////  counter                                                     ////
1964
////                                                              ////
1965
////  To Do:                                                      ////
1966
////   - add LFSR with more taps                                  ////
1967
////                                                              ////
1968
////  Author(s):                                                  ////
1969
////      - Michael Unneback, unneback@opencores.org              ////
1970
////        ORSoC AB                                              ////
1971
////                                                              ////
1972
//////////////////////////////////////////////////////////////////////
1973
////                                                              ////
1974
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1975
////                                                              ////
1976
//// This source file may be used and distributed without         ////
1977
//// restriction provided that this copyright statement is not    ////
1978
//// removed from the file and that any derivative work contains  ////
1979
//// the original copyright notice and the associated disclaimer. ////
1980
////                                                              ////
1981
//// This source file is free software; you can redistribute it   ////
1982
//// and/or modify it under the terms of the GNU Lesser General   ////
1983
//// Public License as published by the Free Software Foundation; ////
1984
//// either version 2.1 of the License, or (at your option) any   ////
1985
//// later version.                                               ////
1986
////                                                              ////
1987
//// This source is distributed in the hope that it will be       ////
1988
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1989
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1990
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1991
//// details.                                                     ////
1992
////                                                              ////
1993
//// You should have received a copy of the GNU Lesser General    ////
1994
//// Public License along with this source; if not, download it   ////
1995
//// from http://www.opencores.org/lgpl.shtml                     ////
1996
////                                                              ////
1997
//////////////////////////////////////////////////////////////////////
1998
 
1999
// binary counter
2000
 
2001 40 unneback
`define MODULE cnt_bin_ce_rew_q_zq_l1
2002
module `BASE`MODULE (
2003
`undef MODULE
2004
 cke, rew, q, zq, level1, rst, clk);
2005
 
2006 25 unneback
   parameter length = 4;
2007
   input cke;
2008
   input rew;
2009
   output [length:1] q;
2010
   output reg zq;
2011
   output reg level1;
2012
   input rst;
2013
   input clk;
2014
 
2015
   parameter clear_value = 0;
2016
   parameter set_value = 1;
2017
   parameter wrap_value = 1;
2018
   parameter level1_value = 15;
2019
 
2020 29 unneback
   wire clear;
2021 30 unneback
   assign clear = 1'b0;
2022 25 unneback
   reg  [length:1] qi;
2023
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2024
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2025
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2026
   assign q_next = rew ? q_next_rew : q_next_fw;
2027
 
2028
   always @ (posedge clk or posedge rst)
2029
     if (rst)
2030
       qi <= {length{1'b0}};
2031
     else
2032
     if (cke)
2033
       qi <= q_next;
2034
 
2035
   assign q = qi;
2036
 
2037
 
2038
   always @ (posedge clk or posedge rst)
2039
     if (rst)
2040
       zq <= 1'b1;
2041
     else
2042
     if (cke)
2043
       zq <= q_next == {length{1'b0}};
2044
 
2045
    always @ (posedge clk or posedge rst)
2046
    if (rst)
2047
        level1 <= 1'b0;
2048
    else
2049
    if (cke)
2050 29 unneback
    if (clear)
2051
        level1 <= 1'b0;
2052
    else if (q_next == level1_value)
2053 25 unneback
        level1 <= 1'b1;
2054
    else if (qi == level1_value & rew)
2055
        level1 <= 1'b0;
2056
endmodule
2057 40 unneback
`endif
2058
`ifdef CNT_LFSR_ZQ
2059 25 unneback
//////////////////////////////////////////////////////////////////////
2060
////                                                              ////
2061
////  Versatile counter                                           ////
2062
////                                                              ////
2063
////  Description                                                 ////
2064
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2065
////  counter                                                     ////
2066
////                                                              ////
2067
////  To Do:                                                      ////
2068
////   - add LFSR with more taps                                  ////
2069
////                                                              ////
2070
////  Author(s):                                                  ////
2071
////      - Michael Unneback, unneback@opencores.org              ////
2072
////        ORSoC AB                                              ////
2073
////                                                              ////
2074
//////////////////////////////////////////////////////////////////////
2075
////                                                              ////
2076
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2077
////                                                              ////
2078
//// This source file may be used and distributed without         ////
2079
//// restriction provided that this copyright statement is not    ////
2080
//// removed from the file and that any derivative work contains  ////
2081
//// the original copyright notice and the associated disclaimer. ////
2082
////                                                              ////
2083
//// This source file is free software; you can redistribute it   ////
2084
//// and/or modify it under the terms of the GNU Lesser General   ////
2085
//// Public License as published by the Free Software Foundation; ////
2086
//// either version 2.1 of the License, or (at your option) any   ////
2087
//// later version.                                               ////
2088
////                                                              ////
2089
//// This source is distributed in the hope that it will be       ////
2090
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2091
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2092
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2093
//// details.                                                     ////
2094
////                                                              ////
2095
//// You should have received a copy of the GNU Lesser General    ////
2096
//// Public License along with this source; if not, download it   ////
2097
//// from http://www.opencores.org/lgpl.shtml                     ////
2098
////                                                              ////
2099
//////////////////////////////////////////////////////////////////////
2100
 
2101 6 unneback
// LFSR counter
2102
 
2103 40 unneback
`define MODULE cnt_lfsr_zq
2104
module `BASE`MODULE (
2105
`undef MODULE
2106
 zq, rst, clk);
2107
 
2108 6 unneback
   parameter length = 4;
2109
   output reg zq;
2110
   input rst;
2111
   input clk;
2112
 
2113
   parameter clear_value = 0;
2114
   parameter set_value = 1;
2115
   parameter wrap_value = 8;
2116
   parameter level1_value = 15;
2117
 
2118
   reg  [length:1] qi;
2119
   reg lfsr_fb;
2120
   wire [length:1] q_next;
2121
   reg [32:1] polynom;
2122
   integer i;
2123
 
2124
   always @ (qi)
2125
   begin
2126
        case (length)
2127
         2: polynom = 32'b11;                               // 0x3
2128
         3: polynom = 32'b110;                              // 0x6
2129
         4: polynom = 32'b1100;                             // 0xC
2130
         5: polynom = 32'b10100;                            // 0x14
2131
         6: polynom = 32'b110000;                           // 0x30
2132
         7: polynom = 32'b1100000;                          // 0x60
2133
         8: polynom = 32'b10111000;                         // 0xb8
2134
         9: polynom = 32'b100010000;                        // 0x110
2135
        10: polynom = 32'b1001000000;                       // 0x240
2136
        11: polynom = 32'b10100000000;                      // 0x500
2137
        12: polynom = 32'b100000101001;                     // 0x829
2138
        13: polynom = 32'b1000000001100;                    // 0x100C
2139
        14: polynom = 32'b10000000010101;                   // 0x2015
2140
        15: polynom = 32'b110000000000000;                  // 0x6000
2141
        16: polynom = 32'b1101000000001000;                 // 0xD008
2142
        17: polynom = 32'b10010000000000000;                // 0x12000
2143
        18: polynom = 32'b100000010000000000;               // 0x20400
2144
        19: polynom = 32'b1000000000000100011;              // 0x40023
2145 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2146 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2147
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2148
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2149
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2150
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2151
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2152
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2153
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2154
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2155
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2156
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2157
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2158
        default: polynom = 32'b0;
2159
        endcase
2160
        lfsr_fb = qi[length];
2161
        for (i=length-1; i>=1; i=i-1) begin
2162
            if (polynom[i])
2163
                lfsr_fb = lfsr_fb  ~^ qi[i];
2164
        end
2165
    end
2166
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2167
 
2168
   always @ (posedge clk or posedge rst)
2169
     if (rst)
2170
       qi <= {length{1'b0}};
2171
     else
2172
       qi <= q_next;
2173
 
2174
 
2175
 
2176
   always @ (posedge clk or posedge rst)
2177
     if (rst)
2178
       zq <= 1'b1;
2179
     else
2180
       zq <= q_next == {length{1'b0}};
2181
endmodule
2182 40 unneback
`endif
2183
`ifdef CNT_LFSR_CE_ZQ
2184 6 unneback
//////////////////////////////////////////////////////////////////////
2185
////                                                              ////
2186
////  Versatile counter                                           ////
2187
////                                                              ////
2188
////  Description                                                 ////
2189
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2190
////  counter                                                     ////
2191
////                                                              ////
2192
////  To Do:                                                      ////
2193
////   - add LFSR with more taps                                  ////
2194
////                                                              ////
2195
////  Author(s):                                                  ////
2196
////      - Michael Unneback, unneback@opencores.org              ////
2197
////        ORSoC AB                                              ////
2198
////                                                              ////
2199
//////////////////////////////////////////////////////////////////////
2200
////                                                              ////
2201
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2202
////                                                              ////
2203
//// This source file may be used and distributed without         ////
2204
//// restriction provided that this copyright statement is not    ////
2205
//// removed from the file and that any derivative work contains  ////
2206
//// the original copyright notice and the associated disclaimer. ////
2207
////                                                              ////
2208
//// This source file is free software; you can redistribute it   ////
2209
//// and/or modify it under the terms of the GNU Lesser General   ////
2210
//// Public License as published by the Free Software Foundation; ////
2211
//// either version 2.1 of the License, or (at your option) any   ////
2212
//// later version.                                               ////
2213
////                                                              ////
2214
//// This source is distributed in the hope that it will be       ////
2215
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2216
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2217
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2218
//// details.                                                     ////
2219
////                                                              ////
2220
//// You should have received a copy of the GNU Lesser General    ////
2221
//// Public License along with this source; if not, download it   ////
2222
//// from http://www.opencores.org/lgpl.shtml                     ////
2223
////                                                              ////
2224
//////////////////////////////////////////////////////////////////////
2225
 
2226
// LFSR counter
2227
 
2228 40 unneback
`define MODULE cnt_lfsr_ce_zq
2229
module `BASE`MODULE (
2230
`undef MODULE
2231
 cke, zq, rst, clk);
2232
 
2233 6 unneback
   parameter length = 4;
2234
   input cke;
2235
   output reg zq;
2236
   input rst;
2237
   input clk;
2238
 
2239
   parameter clear_value = 0;
2240
   parameter set_value = 1;
2241
   parameter wrap_value = 8;
2242
   parameter level1_value = 15;
2243
 
2244
   reg  [length:1] qi;
2245
   reg lfsr_fb;
2246
   wire [length:1] q_next;
2247
   reg [32:1] polynom;
2248
   integer i;
2249
 
2250
   always @ (qi)
2251
   begin
2252
        case (length)
2253
         2: polynom = 32'b11;                               // 0x3
2254
         3: polynom = 32'b110;                              // 0x6
2255
         4: polynom = 32'b1100;                             // 0xC
2256
         5: polynom = 32'b10100;                            // 0x14
2257
         6: polynom = 32'b110000;                           // 0x30
2258
         7: polynom = 32'b1100000;                          // 0x60
2259
         8: polynom = 32'b10111000;                         // 0xb8
2260
         9: polynom = 32'b100010000;                        // 0x110
2261
        10: polynom = 32'b1001000000;                       // 0x240
2262
        11: polynom = 32'b10100000000;                      // 0x500
2263
        12: polynom = 32'b100000101001;                     // 0x829
2264
        13: polynom = 32'b1000000001100;                    // 0x100C
2265
        14: polynom = 32'b10000000010101;                   // 0x2015
2266
        15: polynom = 32'b110000000000000;                  // 0x6000
2267
        16: polynom = 32'b1101000000001000;                 // 0xD008
2268
        17: polynom = 32'b10010000000000000;                // 0x12000
2269
        18: polynom = 32'b100000010000000000;               // 0x20400
2270
        19: polynom = 32'b1000000000000100011;              // 0x40023
2271 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2272 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2273
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2274
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2275
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2276
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2277
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2278
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2279
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2280
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2281
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2282
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2283
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2284
        default: polynom = 32'b0;
2285
        endcase
2286
        lfsr_fb = qi[length];
2287
        for (i=length-1; i>=1; i=i-1) begin
2288
            if (polynom[i])
2289
                lfsr_fb = lfsr_fb  ~^ qi[i];
2290
        end
2291
    end
2292
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2293
 
2294
   always @ (posedge clk or posedge rst)
2295
     if (rst)
2296
       qi <= {length{1'b0}};
2297
     else
2298
     if (cke)
2299
       qi <= q_next;
2300
 
2301
 
2302
 
2303
   always @ (posedge clk or posedge rst)
2304
     if (rst)
2305
       zq <= 1'b1;
2306
     else
2307
     if (cke)
2308
       zq <= q_next == {length{1'b0}};
2309
endmodule
2310 40 unneback
`endif
2311
`ifdef CNT_LFSR_CE_Q
2312 6 unneback
//////////////////////////////////////////////////////////////////////
2313
////                                                              ////
2314
////  Versatile counter                                           ////
2315
////                                                              ////
2316
////  Description                                                 ////
2317
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2318
////  counter                                                     ////
2319
////                                                              ////
2320
////  To Do:                                                      ////
2321
////   - add LFSR with more taps                                  ////
2322
////                                                              ////
2323
////  Author(s):                                                  ////
2324
////      - Michael Unneback, unneback@opencores.org              ////
2325
////        ORSoC AB                                              ////
2326
////                                                              ////
2327
//////////////////////////////////////////////////////////////////////
2328
////                                                              ////
2329
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2330
////                                                              ////
2331
//// This source file may be used and distributed without         ////
2332
//// restriction provided that this copyright statement is not    ////
2333
//// removed from the file and that any derivative work contains  ////
2334
//// the original copyright notice and the associated disclaimer. ////
2335
////                                                              ////
2336
//// This source file is free software; you can redistribute it   ////
2337
//// and/or modify it under the terms of the GNU Lesser General   ////
2338
//// Public License as published by the Free Software Foundation; ////
2339
//// either version 2.1 of the License, or (at your option) any   ////
2340
//// later version.                                               ////
2341
////                                                              ////
2342
//// This source is distributed in the hope that it will be       ////
2343
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2344
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2345
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2346
//// details.                                                     ////
2347
////                                                              ////
2348
//// You should have received a copy of the GNU Lesser General    ////
2349
//// Public License along with this source; if not, download it   ////
2350
//// from http://www.opencores.org/lgpl.shtml                     ////
2351
////                                                              ////
2352
//////////////////////////////////////////////////////////////////////
2353 22 unneback
 
2354
// LFSR counter
2355 27 unneback
 
2356 40 unneback
`define MODULE cnt_lfsr_ce_q
2357
module `BASE`MODULE (
2358
`undef MODULE
2359
 cke, q, rst, clk);
2360
 
2361 27 unneback
   parameter length = 4;
2362
   input cke;
2363
   output [length:1] q;
2364
   input rst;
2365
   input clk;
2366
 
2367
   parameter clear_value = 0;
2368
   parameter set_value = 1;
2369
   parameter wrap_value = 8;
2370
   parameter level1_value = 15;
2371
 
2372
   reg  [length:1] qi;
2373
   reg lfsr_fb;
2374
   wire [length:1] q_next;
2375
   reg [32:1] polynom;
2376
   integer i;
2377
 
2378
   always @ (qi)
2379
   begin
2380
        case (length)
2381
         2: polynom = 32'b11;                               // 0x3
2382
         3: polynom = 32'b110;                              // 0x6
2383
         4: polynom = 32'b1100;                             // 0xC
2384
         5: polynom = 32'b10100;                            // 0x14
2385
         6: polynom = 32'b110000;                           // 0x30
2386
         7: polynom = 32'b1100000;                          // 0x60
2387
         8: polynom = 32'b10111000;                         // 0xb8
2388
         9: polynom = 32'b100010000;                        // 0x110
2389
        10: polynom = 32'b1001000000;                       // 0x240
2390
        11: polynom = 32'b10100000000;                      // 0x500
2391
        12: polynom = 32'b100000101001;                     // 0x829
2392
        13: polynom = 32'b1000000001100;                    // 0x100C
2393
        14: polynom = 32'b10000000010101;                   // 0x2015
2394
        15: polynom = 32'b110000000000000;                  // 0x6000
2395
        16: polynom = 32'b1101000000001000;                 // 0xD008
2396
        17: polynom = 32'b10010000000000000;                // 0x12000
2397
        18: polynom = 32'b100000010000000000;               // 0x20400
2398
        19: polynom = 32'b1000000000000100011;              // 0x40023
2399 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2400 27 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2401
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2402
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2403
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2404
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2405
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2406
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2407
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2408
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2409
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2410
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2411
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2412
        default: polynom = 32'b0;
2413
        endcase
2414
        lfsr_fb = qi[length];
2415
        for (i=length-1; i>=1; i=i-1) begin
2416
            if (polynom[i])
2417
                lfsr_fb = lfsr_fb  ~^ qi[i];
2418
        end
2419
    end
2420
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2421
 
2422
   always @ (posedge clk or posedge rst)
2423
     if (rst)
2424
       qi <= {length{1'b0}};
2425
     else
2426
     if (cke)
2427
       qi <= q_next;
2428
 
2429
   assign q = qi;
2430
 
2431
endmodule
2432 40 unneback
`endif
2433
`ifdef CNT_LFSR_CE_CLEAR_Q
2434 27 unneback
//////////////////////////////////////////////////////////////////////
2435
////                                                              ////
2436
////  Versatile counter                                           ////
2437
////                                                              ////
2438
////  Description                                                 ////
2439
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2440
////  counter                                                     ////
2441
////                                                              ////
2442
////  To Do:                                                      ////
2443
////   - add LFSR with more taps                                  ////
2444
////                                                              ////
2445
////  Author(s):                                                  ////
2446
////      - Michael Unneback, unneback@opencores.org              ////
2447
////        ORSoC AB                                              ////
2448
////                                                              ////
2449
//////////////////////////////////////////////////////////////////////
2450
////                                                              ////
2451
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2452
////                                                              ////
2453
//// This source file may be used and distributed without         ////
2454
//// restriction provided that this copyright statement is not    ////
2455
//// removed from the file and that any derivative work contains  ////
2456
//// the original copyright notice and the associated disclaimer. ////
2457
////                                                              ////
2458
//// This source file is free software; you can redistribute it   ////
2459
//// and/or modify it under the terms of the GNU Lesser General   ////
2460
//// Public License as published by the Free Software Foundation; ////
2461
//// either version 2.1 of the License, or (at your option) any   ////
2462
//// later version.                                               ////
2463
////                                                              ////
2464
//// This source is distributed in the hope that it will be       ////
2465
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2466
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2467
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2468
//// details.                                                     ////
2469
////                                                              ////
2470
//// You should have received a copy of the GNU Lesser General    ////
2471
//// Public License along with this source; if not, download it   ////
2472
//// from http://www.opencores.org/lgpl.shtml                     ////
2473
////                                                              ////
2474
//////////////////////////////////////////////////////////////////////
2475
 
2476
// LFSR counter
2477
 
2478 40 unneback
`define MODULE cnt_lfsr_ce_clear_q
2479
module `BASE`MODULE (
2480
`undef MODULE
2481
 clear, cke, q, rst, clk);
2482
 
2483 27 unneback
   parameter length = 4;
2484
   input clear;
2485
   input cke;
2486
   output [length:1] q;
2487
   input rst;
2488
   input clk;
2489
 
2490
   parameter clear_value = 0;
2491
   parameter set_value = 1;
2492
   parameter wrap_value = 8;
2493
   parameter level1_value = 15;
2494
 
2495
   reg  [length:1] qi;
2496
   reg lfsr_fb;
2497
   wire [length:1] q_next;
2498
   reg [32:1] polynom;
2499
   integer i;
2500
 
2501
   always @ (qi)
2502
   begin
2503
        case (length)
2504
         2: polynom = 32'b11;                               // 0x3
2505
         3: polynom = 32'b110;                              // 0x6
2506
         4: polynom = 32'b1100;                             // 0xC
2507
         5: polynom = 32'b10100;                            // 0x14
2508
         6: polynom = 32'b110000;                           // 0x30
2509
         7: polynom = 32'b1100000;                          // 0x60
2510
         8: polynom = 32'b10111000;                         // 0xb8
2511
         9: polynom = 32'b100010000;                        // 0x110
2512
        10: polynom = 32'b1001000000;                       // 0x240
2513
        11: polynom = 32'b10100000000;                      // 0x500
2514
        12: polynom = 32'b100000101001;                     // 0x829
2515
        13: polynom = 32'b1000000001100;                    // 0x100C
2516
        14: polynom = 32'b10000000010101;                   // 0x2015
2517
        15: polynom = 32'b110000000000000;                  // 0x6000
2518
        16: polynom = 32'b1101000000001000;                 // 0xD008
2519
        17: polynom = 32'b10010000000000000;                // 0x12000
2520
        18: polynom = 32'b100000010000000000;               // 0x20400
2521
        19: polynom = 32'b1000000000000100011;              // 0x40023
2522 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2523 27 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2524
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2525
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2526
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2527
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2528
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2529
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2530
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2531
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2532
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2533
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2534
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2535
        default: polynom = 32'b0;
2536
        endcase
2537
        lfsr_fb = qi[length];
2538
        for (i=length-1; i>=1; i=i-1) begin
2539
            if (polynom[i])
2540
                lfsr_fb = lfsr_fb  ~^ qi[i];
2541
        end
2542
    end
2543
   assign q_next =  clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2544
 
2545
   always @ (posedge clk or posedge rst)
2546
     if (rst)
2547
       qi <= {length{1'b0}};
2548
     else
2549
     if (cke)
2550
       qi <= q_next;
2551
 
2552
   assign q = qi;
2553
 
2554
endmodule
2555 40 unneback
`endif
2556
`ifdef CNT_LFSR_CE_Q_ZQ
2557 27 unneback
//////////////////////////////////////////////////////////////////////
2558
////                                                              ////
2559
////  Versatile counter                                           ////
2560
////                                                              ////
2561
////  Description                                                 ////
2562
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2563
////  counter                                                     ////
2564
////                                                              ////
2565
////  To Do:                                                      ////
2566
////   - add LFSR with more taps                                  ////
2567
////                                                              ////
2568
////  Author(s):                                                  ////
2569
////      - Michael Unneback, unneback@opencores.org              ////
2570
////        ORSoC AB                                              ////
2571
////                                                              ////
2572
//////////////////////////////////////////////////////////////////////
2573
////                                                              ////
2574
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2575
////                                                              ////
2576
//// This source file may be used and distributed without         ////
2577
//// restriction provided that this copyright statement is not    ////
2578
//// removed from the file and that any derivative work contains  ////
2579
//// the original copyright notice and the associated disclaimer. ////
2580
////                                                              ////
2581
//// This source file is free software; you can redistribute it   ////
2582
//// and/or modify it under the terms of the GNU Lesser General   ////
2583
//// Public License as published by the Free Software Foundation; ////
2584
//// either version 2.1 of the License, or (at your option) any   ////
2585
//// later version.                                               ////
2586
////                                                              ////
2587
//// This source is distributed in the hope that it will be       ////
2588
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2589
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2590
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2591
//// details.                                                     ////
2592
////                                                              ////
2593
//// You should have received a copy of the GNU Lesser General    ////
2594
//// Public License along with this source; if not, download it   ////
2595
//// from http://www.opencores.org/lgpl.shtml                     ////
2596
////                                                              ////
2597
//////////////////////////////////////////////////////////////////////
2598
 
2599
// LFSR counter
2600 22 unneback
 
2601 40 unneback
`define MODULE cnt_lfsr_ce_q_zq
2602
module `BASE`MODULE (
2603
`undef MODULE
2604
 cke, q, zq, rst, clk);
2605
 
2606 22 unneback
   parameter length = 4;
2607
   input cke;
2608
   output [length:1] q;
2609
   output reg zq;
2610
   input rst;
2611
   input clk;
2612
 
2613
   parameter clear_value = 0;
2614
   parameter set_value = 1;
2615
   parameter wrap_value = 8;
2616
   parameter level1_value = 15;
2617
 
2618
   reg  [length:1] qi;
2619
   reg lfsr_fb;
2620
   wire [length:1] q_next;
2621
   reg [32:1] polynom;
2622
   integer i;
2623
 
2624
   always @ (qi)
2625
   begin
2626
        case (length)
2627
         2: polynom = 32'b11;                               // 0x3
2628
         3: polynom = 32'b110;                              // 0x6
2629
         4: polynom = 32'b1100;                             // 0xC
2630
         5: polynom = 32'b10100;                            // 0x14
2631
         6: polynom = 32'b110000;                           // 0x30
2632
         7: polynom = 32'b1100000;                          // 0x60
2633
         8: polynom = 32'b10111000;                         // 0xb8
2634
         9: polynom = 32'b100010000;                        // 0x110
2635
        10: polynom = 32'b1001000000;                       // 0x240
2636
        11: polynom = 32'b10100000000;                      // 0x500
2637
        12: polynom = 32'b100000101001;                     // 0x829
2638
        13: polynom = 32'b1000000001100;                    // 0x100C
2639
        14: polynom = 32'b10000000010101;                   // 0x2015
2640
        15: polynom = 32'b110000000000000;                  // 0x6000
2641
        16: polynom = 32'b1101000000001000;                 // 0xD008
2642
        17: polynom = 32'b10010000000000000;                // 0x12000
2643
        18: polynom = 32'b100000010000000000;               // 0x20400
2644
        19: polynom = 32'b1000000000000100011;              // 0x40023
2645 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2646 22 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2647
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2648
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2649
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2650
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2651
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2652
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2653
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2654
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2655
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2656
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2657
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2658
        default: polynom = 32'b0;
2659
        endcase
2660
        lfsr_fb = qi[length];
2661
        for (i=length-1; i>=1; i=i-1) begin
2662
            if (polynom[i])
2663
                lfsr_fb = lfsr_fb  ~^ qi[i];
2664
        end
2665
    end
2666
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2667
 
2668
   always @ (posedge clk or posedge rst)
2669
     if (rst)
2670
       qi <= {length{1'b0}};
2671
     else
2672
     if (cke)
2673
       qi <= q_next;
2674
 
2675
   assign q = qi;
2676
 
2677
 
2678
   always @ (posedge clk or posedge rst)
2679
     if (rst)
2680
       zq <= 1'b1;
2681
     else
2682
     if (cke)
2683
       zq <= q_next == {length{1'b0}};
2684
endmodule
2685 40 unneback
`endif
2686
`ifdef CNT_LFSR_CE_REW_L1
2687 22 unneback
//////////////////////////////////////////////////////////////////////
2688
////                                                              ////
2689
////  Versatile counter                                           ////
2690
////                                                              ////
2691
////  Description                                                 ////
2692
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2693
////  counter                                                     ////
2694
////                                                              ////
2695
////  To Do:                                                      ////
2696
////   - add LFSR with more taps                                  ////
2697
////                                                              ////
2698
////  Author(s):                                                  ////
2699
////      - Michael Unneback, unneback@opencores.org              ////
2700
////        ORSoC AB                                              ////
2701
////                                                              ////
2702
//////////////////////////////////////////////////////////////////////
2703
////                                                              ////
2704
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2705
////                                                              ////
2706
//// This source file may be used and distributed without         ////
2707
//// restriction provided that this copyright statement is not    ////
2708
//// removed from the file and that any derivative work contains  ////
2709
//// the original copyright notice and the associated disclaimer. ////
2710
////                                                              ////
2711
//// This source file is free software; you can redistribute it   ////
2712
//// and/or modify it under the terms of the GNU Lesser General   ////
2713
//// Public License as published by the Free Software Foundation; ////
2714
//// either version 2.1 of the License, or (at your option) any   ////
2715
//// later version.                                               ////
2716
////                                                              ////
2717
//// This source is distributed in the hope that it will be       ////
2718
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2719
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2720
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2721
//// details.                                                     ////
2722
////                                                              ////
2723
//// You should have received a copy of the GNU Lesser General    ////
2724
//// Public License along with this source; if not, download it   ////
2725
//// from http://www.opencores.org/lgpl.shtml                     ////
2726
////                                                              ////
2727
//////////////////////////////////////////////////////////////////////
2728 6 unneback
 
2729
// LFSR counter
2730
 
2731 40 unneback
`define MODULE cnt_lfsr_ce_rew_l1
2732
module `BASE`MODULE (
2733
`undef MODULE
2734
 cke, rew, level1, rst, clk);
2735
 
2736 6 unneback
   parameter length = 4;
2737
   input cke;
2738
   input rew;
2739
   output reg level1;
2740
   input rst;
2741
   input clk;
2742
 
2743
   parameter clear_value = 0;
2744
   parameter set_value = 1;
2745
   parameter wrap_value = 8;
2746
   parameter level1_value = 15;
2747
 
2748 29 unneback
   wire clear;
2749 30 unneback
   assign clear = 1'b0;
2750 6 unneback
   reg  [length:1] qi;
2751
   reg lfsr_fb, lfsr_fb_rew;
2752
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2753
   reg [32:1] polynom_rew;
2754
   integer j;
2755
   reg [32:1] polynom;
2756
   integer i;
2757
 
2758
   always @ (qi)
2759
   begin
2760
        case (length)
2761
         2: polynom = 32'b11;                               // 0x3
2762
         3: polynom = 32'b110;                              // 0x6
2763
         4: polynom = 32'b1100;                             // 0xC
2764
         5: polynom = 32'b10100;                            // 0x14
2765
         6: polynom = 32'b110000;                           // 0x30
2766
         7: polynom = 32'b1100000;                          // 0x60
2767
         8: polynom = 32'b10111000;                         // 0xb8
2768
         9: polynom = 32'b100010000;                        // 0x110
2769
        10: polynom = 32'b1001000000;                       // 0x240
2770
        11: polynom = 32'b10100000000;                      // 0x500
2771
        12: polynom = 32'b100000101001;                     // 0x829
2772
        13: polynom = 32'b1000000001100;                    // 0x100C
2773
        14: polynom = 32'b10000000010101;                   // 0x2015
2774
        15: polynom = 32'b110000000000000;                  // 0x6000
2775
        16: polynom = 32'b1101000000001000;                 // 0xD008
2776
        17: polynom = 32'b10010000000000000;                // 0x12000
2777
        18: polynom = 32'b100000010000000000;               // 0x20400
2778
        19: polynom = 32'b1000000000000100011;              // 0x40023
2779 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2780 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2781
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2782
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2783
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2784
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2785
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2786
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2787
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2788
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2789
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2790
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2791
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2792
        default: polynom = 32'b0;
2793
        endcase
2794
        lfsr_fb = qi[length];
2795
        for (i=length-1; i>=1; i=i-1) begin
2796
            if (polynom[i])
2797
                lfsr_fb = lfsr_fb  ~^ qi[i];
2798
        end
2799
    end
2800
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2801
   always @ (qi)
2802
   begin
2803
        case (length)
2804
         2: polynom_rew = 32'b11;
2805
         3: polynom_rew = 32'b110;
2806
         4: polynom_rew = 32'b1100;
2807
         5: polynom_rew = 32'b10100;
2808
         6: polynom_rew = 32'b110000;
2809
         7: polynom_rew = 32'b1100000;
2810
         8: polynom_rew = 32'b10111000;
2811
         9: polynom_rew = 32'b100010000;
2812
        10: polynom_rew = 32'b1001000000;
2813
        11: polynom_rew = 32'b10100000000;
2814
        12: polynom_rew = 32'b100000101001;
2815
        13: polynom_rew = 32'b1000000001100;
2816
        14: polynom_rew = 32'b10000000010101;
2817
        15: polynom_rew = 32'b110000000000000;
2818
        16: polynom_rew = 32'b1101000000001000;
2819
        17: polynom_rew = 32'b10010000000000000;
2820
        18: polynom_rew = 32'b100000010000000000;
2821
        19: polynom_rew = 32'b1000000000000100011;
2822
        20: polynom_rew = 32'b10000010000000000000;
2823
        21: polynom_rew = 32'b101000000000000000000;
2824
        22: polynom_rew = 32'b1100000000000000000000;
2825
        23: polynom_rew = 32'b10000100000000000000000;
2826
        24: polynom_rew = 32'b111000010000000000000000;
2827
        25: polynom_rew = 32'b1001000000000000000000000;
2828
        26: polynom_rew = 32'b10000000000000000000100011;
2829
        27: polynom_rew = 32'b100000000000000000000010011;
2830
        28: polynom_rew = 32'b1100100000000000000000000000;
2831
        29: polynom_rew = 32'b10100000000000000000000000000;
2832
        30: polynom_rew = 32'b100000000000000000000000101001;
2833
        31: polynom_rew = 32'b1001000000000000000000000000000;
2834
        32: polynom_rew = 32'b10000000001000000000000000000011;
2835
        default: polynom_rew = 32'b0;
2836
        endcase
2837
        // rotate left
2838
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
2839
        lfsr_fb_rew = qi[length];
2840
        for (i=length-1; i>=1; i=i-1) begin
2841
            if (polynom_rew[i])
2842
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
2843
        end
2844
    end
2845
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
2846
   assign q_next = rew ? q_next_rew : q_next_fw;
2847
 
2848
   always @ (posedge clk or posedge rst)
2849
     if (rst)
2850
       qi <= {length{1'b0}};
2851
     else
2852
     if (cke)
2853
       qi <= q_next;
2854
 
2855
 
2856
 
2857
    always @ (posedge clk or posedge rst)
2858
    if (rst)
2859
        level1 <= 1'b0;
2860
    else
2861
    if (cke)
2862 29 unneback
    if (clear)
2863
        level1 <= 1'b0;
2864
    else if (q_next == level1_value)
2865 6 unneback
        level1 <= 1'b1;
2866
    else if (qi == level1_value & rew)
2867
        level1 <= 1'b0;
2868
endmodule
2869 40 unneback
`endif
2870
`ifdef CNT_GRAY
2871 6 unneback
//////////////////////////////////////////////////////////////////////
2872
////                                                              ////
2873
////  Versatile counter                                           ////
2874
////                                                              ////
2875
////  Description                                                 ////
2876
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2877
////  counter                                                     ////
2878
////                                                              ////
2879
////  To Do:                                                      ////
2880
////   - add LFSR with more taps                                  ////
2881
////                                                              ////
2882
////  Author(s):                                                  ////
2883
////      - Michael Unneback, unneback@opencores.org              ////
2884
////        ORSoC AB                                              ////
2885
////                                                              ////
2886
//////////////////////////////////////////////////////////////////////
2887
////                                                              ////
2888
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2889
////                                                              ////
2890
//// This source file may be used and distributed without         ////
2891
//// restriction provided that this copyright statement is not    ////
2892
//// removed from the file and that any derivative work contains  ////
2893
//// the original copyright notice and the associated disclaimer. ////
2894
////                                                              ////
2895
//// This source file is free software; you can redistribute it   ////
2896
//// and/or modify it under the terms of the GNU Lesser General   ////
2897
//// Public License as published by the Free Software Foundation; ////
2898
//// either version 2.1 of the License, or (at your option) any   ////
2899
//// later version.                                               ////
2900
////                                                              ////
2901
//// This source is distributed in the hope that it will be       ////
2902
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2903
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2904
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2905
//// details.                                                     ////
2906
////                                                              ////
2907
//// You should have received a copy of the GNU Lesser General    ////
2908
//// Public License along with this source; if not, download it   ////
2909
//// from http://www.opencores.org/lgpl.shtml                     ////
2910
////                                                              ////
2911
//////////////////////////////////////////////////////////////////////
2912
 
2913
// GRAY counter
2914
 
2915 40 unneback
`define MODULE cnt_gray
2916
module `BASE`MODULE (
2917
`undef MODULE
2918
 q, rst, clk);
2919
 
2920 6 unneback
   parameter length = 4;
2921
   output reg [length:1] q;
2922
   input rst;
2923
   input clk;
2924
 
2925
   parameter clear_value = 0;
2926
   parameter set_value = 1;
2927
   parameter wrap_value = 8;
2928
   parameter level1_value = 15;
2929
 
2930
   reg  [length:1] qi;
2931
   wire [length:1] q_next;
2932
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2933
 
2934
   always @ (posedge clk or posedge rst)
2935
     if (rst)
2936
       qi <= {length{1'b0}};
2937
     else
2938
       qi <= q_next;
2939
 
2940
   always @ (posedge clk or posedge rst)
2941
     if (rst)
2942
       q <= {length{1'b0}};
2943
     else
2944
         q <= (q_next>>1) ^ q_next;
2945
 
2946
endmodule
2947 40 unneback
`endif
2948
`ifdef CNT_GRAY_CE
2949 6 unneback
//////////////////////////////////////////////////////////////////////
2950
////                                                              ////
2951
////  Versatile counter                                           ////
2952
////                                                              ////
2953
////  Description                                                 ////
2954
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2955
////  counter                                                     ////
2956
////                                                              ////
2957
////  To Do:                                                      ////
2958
////   - add LFSR with more taps                                  ////
2959
////                                                              ////
2960
////  Author(s):                                                  ////
2961
////      - Michael Unneback, unneback@opencores.org              ////
2962
////        ORSoC AB                                              ////
2963
////                                                              ////
2964
//////////////////////////////////////////////////////////////////////
2965
////                                                              ////
2966
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2967
////                                                              ////
2968
//// This source file may be used and distributed without         ////
2969
//// restriction provided that this copyright statement is not    ////
2970
//// removed from the file and that any derivative work contains  ////
2971
//// the original copyright notice and the associated disclaimer. ////
2972
////                                                              ////
2973
//// This source file is free software; you can redistribute it   ////
2974
//// and/or modify it under the terms of the GNU Lesser General   ////
2975
//// Public License as published by the Free Software Foundation; ////
2976
//// either version 2.1 of the License, or (at your option) any   ////
2977
//// later version.                                               ////
2978
////                                                              ////
2979
//// This source is distributed in the hope that it will be       ////
2980
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2981
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2982
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2983
//// details.                                                     ////
2984
////                                                              ////
2985
//// You should have received a copy of the GNU Lesser General    ////
2986
//// Public License along with this source; if not, download it   ////
2987
//// from http://www.opencores.org/lgpl.shtml                     ////
2988
////                                                              ////
2989
//////////////////////////////////////////////////////////////////////
2990
 
2991
// GRAY counter
2992
 
2993 40 unneback
`define MODULE cnt_gray_ce
2994
module `BASE`MODULE (
2995
`undef MODULE
2996
 cke, q, rst, clk);
2997
 
2998 6 unneback
   parameter length = 4;
2999
   input cke;
3000
   output reg [length:1] q;
3001
   input rst;
3002
   input clk;
3003
 
3004
   parameter clear_value = 0;
3005
   parameter set_value = 1;
3006
   parameter wrap_value = 8;
3007
   parameter level1_value = 15;
3008
 
3009
   reg  [length:1] qi;
3010
   wire [length:1] q_next;
3011
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3012
 
3013
   always @ (posedge clk or posedge rst)
3014
     if (rst)
3015
       qi <= {length{1'b0}};
3016
     else
3017
     if (cke)
3018
       qi <= q_next;
3019
 
3020
   always @ (posedge clk or posedge rst)
3021
     if (rst)
3022
       q <= {length{1'b0}};
3023
     else
3024
       if (cke)
3025
         q <= (q_next>>1) ^ q_next;
3026
 
3027
endmodule
3028 40 unneback
`endif
3029
`ifdef CNT_GRAY_CE_BIN
3030 6 unneback
//////////////////////////////////////////////////////////////////////
3031
////                                                              ////
3032
////  Versatile counter                                           ////
3033
////                                                              ////
3034
////  Description                                                 ////
3035
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3036
////  counter                                                     ////
3037
////                                                              ////
3038
////  To Do:                                                      ////
3039
////   - add LFSR with more taps                                  ////
3040
////                                                              ////
3041
////  Author(s):                                                  ////
3042
////      - Michael Unneback, unneback@opencores.org              ////
3043
////        ORSoC AB                                              ////
3044
////                                                              ////
3045
//////////////////////////////////////////////////////////////////////
3046
////                                                              ////
3047
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3048
////                                                              ////
3049
//// This source file may be used and distributed without         ////
3050
//// restriction provided that this copyright statement is not    ////
3051
//// removed from the file and that any derivative work contains  ////
3052
//// the original copyright notice and the associated disclaimer. ////
3053
////                                                              ////
3054
//// This source file is free software; you can redistribute it   ////
3055
//// and/or modify it under the terms of the GNU Lesser General   ////
3056
//// Public License as published by the Free Software Foundation; ////
3057
//// either version 2.1 of the License, or (at your option) any   ////
3058
//// later version.                                               ////
3059
////                                                              ////
3060
//// This source is distributed in the hope that it will be       ////
3061
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3062
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3063
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3064
//// details.                                                     ////
3065
////                                                              ////
3066
//// You should have received a copy of the GNU Lesser General    ////
3067
//// Public License along with this source; if not, download it   ////
3068
//// from http://www.opencores.org/lgpl.shtml                     ////
3069
////                                                              ////
3070
//////////////////////////////////////////////////////////////////////
3071
 
3072
// GRAY counter
3073
 
3074 40 unneback
`define MODULE cnt_gray_ce_bin
3075
module `BASE`MODULE (
3076
`undef MODULE
3077
 cke, q, q_bin, rst, clk);
3078
 
3079 6 unneback
   parameter length = 4;
3080
   input cke;
3081
   output reg [length:1] q;
3082
   output [length:1] q_bin;
3083
   input rst;
3084
   input clk;
3085
 
3086
   parameter clear_value = 0;
3087
   parameter set_value = 1;
3088
   parameter wrap_value = 8;
3089
   parameter level1_value = 15;
3090
 
3091
   reg  [length:1] qi;
3092
   wire [length:1] q_next;
3093
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3094
 
3095
   always @ (posedge clk or posedge rst)
3096
     if (rst)
3097
       qi <= {length{1'b0}};
3098
     else
3099
     if (cke)
3100
       qi <= q_next;
3101
 
3102
   always @ (posedge clk or posedge rst)
3103
     if (rst)
3104
       q <= {length{1'b0}};
3105
     else
3106
       if (cke)
3107
         q <= (q_next>>1) ^ q_next;
3108
 
3109
   assign q_bin = qi;
3110
 
3111
endmodule
3112 40 unneback
`endif
3113 6 unneback
//////////////////////////////////////////////////////////////////////
3114
////                                                              ////
3115
////  Versatile library, counters                                 ////
3116
////                                                              ////
3117
////  Description                                                 ////
3118
////  counters                                                    ////
3119
////                                                              ////
3120
////                                                              ////
3121
////  To Do:                                                      ////
3122
////   - add more counters                                        ////
3123
////                                                              ////
3124
////  Author(s):                                                  ////
3125
////      - Michael Unneback, unneback@opencores.org              ////
3126
////        ORSoC AB                                              ////
3127
////                                                              ////
3128
//////////////////////////////////////////////////////////////////////
3129
////                                                              ////
3130
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
3131
////                                                              ////
3132
//// This source file may be used and distributed without         ////
3133
//// restriction provided that this copyright statement is not    ////
3134
//// removed from the file and that any derivative work contains  ////
3135
//// the original copyright notice and the associated disclaimer. ////
3136
////                                                              ////
3137
//// This source file is free software; you can redistribute it   ////
3138
//// and/or modify it under the terms of the GNU Lesser General   ////
3139
//// Public License as published by the Free Software Foundation; ////
3140
//// either version 2.1 of the License, or (at your option) any   ////
3141
//// later version.                                               ////
3142
////                                                              ////
3143
//// This source is distributed in the hope that it will be       ////
3144
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3145
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3146
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3147
//// details.                                                     ////
3148
////                                                              ////
3149
//// You should have received a copy of the GNU Lesser General    ////
3150
//// Public License along with this source; if not, download it   ////
3151
//// from http://www.opencores.org/lgpl.shtml                     ////
3152
////                                                              ////
3153
//////////////////////////////////////////////////////////////////////
3154
 
3155 40 unneback
`ifdef CNT_SHREG_WRAP
3156
`define MODULE cnt_shreg_wrap
3157
module `BASE`MODULE ( q, rst, clk);
3158
`undef MODULE
3159 6 unneback
 
3160
   parameter length = 4;
3161
   output reg [0:length-1] q;
3162
   input rst;
3163
   input clk;
3164
 
3165
    always @ (posedge clk or posedge rst)
3166
    if (rst)
3167
        q <= {1'b1,{length-1{1'b0}}};
3168
    else
3169
        q <= {q[length-1],q[0:length-2]};
3170
 
3171
endmodule
3172 40 unneback
`endif
3173 6 unneback
 
3174 40 unneback
`ifdef CNT_SHREG_CE_WRAP
3175
`define MODULE cnt_shreg_ce_wrap
3176
module `BASE`MODULE ( cke, q, rst, clk);
3177
`undef MODULE
3178 6 unneback
 
3179
   parameter length = 4;
3180
   input cke;
3181
   output reg [0:length-1] q;
3182
   input rst;
3183
   input clk;
3184
 
3185
    always @ (posedge clk or posedge rst)
3186
    if (rst)
3187
        q <= {1'b1,{length-1{1'b0}}};
3188
    else
3189
        if (cke)
3190
            q <= {q[length-1],q[0:length-2]};
3191
 
3192
endmodule
3193 40 unneback
`endif
3194 6 unneback
 
3195 40 unneback
`ifdef CNT_SHREG_CE_CLEAR
3196
`define MODULE cnt_shreg_ce_clear
3197
module `BASE`MODULE ( cke, clear, q, rst, clk);
3198
`undef MODULE
3199 6 unneback
 
3200
   parameter length = 4;
3201
   input cke, clear;
3202
   output reg [0:length-1] q;
3203
   input rst;
3204
   input clk;
3205
 
3206
    always @ (posedge clk or posedge rst)
3207
    if (rst)
3208
        q <= {1'b1,{length-1{1'b0}}};
3209
    else
3210
        if (cke)
3211
            if (clear)
3212
                q <= {1'b1,{length-1{1'b0}}};
3213
            else
3214
                q <= q >> 1;
3215
 
3216
endmodule
3217 40 unneback
`endif
3218 6 unneback
 
3219 40 unneback
`ifdef CNT_SHREG_CE_CLEAR_WRAP
3220
`define MODULE cnt_shreg_ce_clear_wrap
3221
module `BASE`MODULE ( cke, clear, q, rst, clk);
3222
`undef MODULE
3223 6 unneback
 
3224
   parameter length = 4;
3225
   input cke, clear;
3226
   output reg [0:length-1] q;
3227
   input rst;
3228
   input clk;
3229
 
3230
    always @ (posedge clk or posedge rst)
3231
    if (rst)
3232
        q <= {1'b1,{length-1{1'b0}}};
3233
    else
3234
        if (cke)
3235
            if (clear)
3236
                q <= {1'b1,{length-1{1'b0}}};
3237
            else
3238
            q <= {q[length-1],q[0:length-2]};
3239
 
3240
endmodule
3241 40 unneback
`endif
3242 6 unneback
//////////////////////////////////////////////////////////////////////
3243
////                                                              ////
3244
////  Versatile library, memories                                 ////
3245
////                                                              ////
3246
////  Description                                                 ////
3247
////  memories                                                    ////
3248
////                                                              ////
3249
////                                                              ////
3250
////  To Do:                                                      ////
3251
////   - add more memory types                                    ////
3252
////                                                              ////
3253
////  Author(s):                                                  ////
3254
////      - Michael Unneback, unneback@opencores.org              ////
3255
////        ORSoC AB                                              ////
3256
////                                                              ////
3257
//////////////////////////////////////////////////////////////////////
3258
////                                                              ////
3259
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
3260
////                                                              ////
3261
//// This source file may be used and distributed without         ////
3262
//// restriction provided that this copyright statement is not    ////
3263
//// removed from the file and that any derivative work contains  ////
3264
//// the original copyright notice and the associated disclaimer. ////
3265
////                                                              ////
3266
//// This source file is free software; you can redistribute it   ////
3267
//// and/or modify it under the terms of the GNU Lesser General   ////
3268
//// Public License as published by the Free Software Foundation; ////
3269
//// either version 2.1 of the License, or (at your option) any   ////
3270
//// later version.                                               ////
3271
////                                                              ////
3272
//// This source is distributed in the hope that it will be       ////
3273
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3274
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3275
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3276
//// details.                                                     ////
3277
////                                                              ////
3278
//// You should have received a copy of the GNU Lesser General    ////
3279
//// Public License along with this source; if not, download it   ////
3280
//// from http://www.opencores.org/lgpl.shtml                     ////
3281
////                                                              ////
3282
//////////////////////////////////////////////////////////////////////
3283
 
3284 40 unneback
`ifdef ROM_INIT
3285 6 unneback
/// ROM
3286 40 unneback
`define MODULE rom_init
3287
module `BASE`MODULE ( adr, q, clk);
3288
`undef MODULE
3289 6 unneback
 
3290 7 unneback
   parameter data_width = 32;
3291
   parameter addr_width = 8;
3292
   input [(addr_width-1):0]       adr;
3293
   output reg [(data_width-1):0] q;
3294
   input                         clk;
3295
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
3296
   parameter memory_file = "vl_rom.vmem";
3297
   initial
3298
     begin
3299
        $readmemh(memory_file, rom);
3300
     end
3301
 
3302
   always @ (posedge clk)
3303
     q <= rom[adr];
3304 6 unneback
 
3305 7 unneback
endmodule
3306 40 unneback
`endif
3307 7 unneback
 
3308 14 unneback
/*
3309 7 unneback
module vl_rom ( adr, q, clk);
3310
 
3311 6 unneback
parameter data_width = 32;
3312
parameter addr_width = 4;
3313
 
3314
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
3315
    {32'h18000000},
3316
    {32'hA8200000},
3317
    {32'hA8200000},
3318
    {32'hA8200000},
3319
    {32'h44003000},
3320
    {32'h15000000},
3321
    {32'h15000000},
3322
    {32'h15000000},
3323
    {32'h15000000},
3324
    {32'h15000000},
3325
    {32'h15000000},
3326
    {32'h15000000},
3327
    {32'h15000000},
3328
    {32'h15000000},
3329
    {32'h15000000},
3330
    {32'h15000000}};
3331
 
3332 7 unneback
input [addr_width-1:0] adr;
3333 6 unneback
output reg [data_width-1:0] q;
3334
input clk;
3335
 
3336
always @ (posedge clk)
3337 7 unneback
    q <= data[adr];
3338 6 unneback
 
3339
endmodule
3340 14 unneback
*/
3341 40 unneback
 
3342
`ifdef RAM
3343
`define MODULE ram
3344 6 unneback
// Single port RAM
3345 40 unneback
module `BASE`MODULE ( d, adr, we, q, clk);
3346
`undef MODULE
3347 6 unneback
 
3348
   parameter data_width = 32;
3349
   parameter addr_width = 8;
3350
   input [(data_width-1):0]      d;
3351
   input [(addr_width-1):0]       adr;
3352
   input                         we;
3353 7 unneback
   output reg [(data_width-1):0] q;
3354 6 unneback
   input                         clk;
3355
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
3356 7 unneback
   parameter init = 0;
3357
   parameter memory_file = "vl_ram.vmem";
3358
   generate if (init) begin : init_mem
3359
   initial
3360
     begin
3361
        $readmemh(memory_file, ram);
3362
     end
3363
   end
3364
   endgenerate
3365
 
3366 6 unneback
   always @ (posedge clk)
3367
   begin
3368
   if (we)
3369
     ram[adr] <= d;
3370
   q <= ram[adr];
3371
   end
3372
 
3373
endmodule
3374 40 unneback
`endif
3375 6 unneback
 
3376 40 unneback
`ifdef RAM_BE
3377
`define MODULE ram_be
3378
module `BASE`MODULE ( d, adr, be, we, q, clk);
3379
`undef MODULE
3380
 
3381 7 unneback
   parameter data_width = 32;
3382
   parameter addr_width = 8;
3383
   input [(data_width-1):0]      d;
3384
   input [(addr_width-1):0]       adr;
3385
   input [(addr_width/4)-1:0]    be;
3386
   input                         we;
3387
   output reg [(data_width-1):0] q;
3388
   input                         clk;
3389
 
3390
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
3391
 
3392
   parameter init = 0;
3393
   parameter memory_file = "vl_ram.vmem";
3394
   generate if (init) begin : init_mem
3395
   initial
3396
     begin
3397
        $readmemh(memory_file, ram);
3398
     end
3399
   end
3400
   endgenerate
3401
 
3402
   genvar i;
3403
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
3404
      always @ (posedge clk)
3405
      if (we & be[i])
3406
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
3407
   end
3408
   endgenerate
3409
 
3410
   always @ (posedge clk)
3411
      q <= ram[adr];
3412
 
3413
endmodule
3414 40 unneback
`endif
3415 7 unneback
 
3416 6 unneback
// Dual port RAM
3417
 
3418
// ACTEL FPGA should not use logic to handle rw collision
3419
`ifdef ACTEL
3420
        `define SYN /*synthesis syn_ramstyle = "no_rw_check"*/
3421
`else
3422
        `define SYN
3423
`endif
3424
 
3425 40 unneback
`ifdef DPRAM_1R1W
3426
`define MODULE dpram_1r1w
3427
module `BASE`MODULE ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
3428
`undef MODULE
3429 6 unneback
   parameter data_width = 32;
3430
   parameter addr_width = 8;
3431
   input [(data_width-1):0]      d_a;
3432
   input [(addr_width-1):0]       adr_a;
3433
   input [(addr_width-1):0]       adr_b;
3434
   input                         we_a;
3435
   output [(data_width-1):0]      q_b;
3436
   input                         clk_a, clk_b;
3437
   reg [(addr_width-1):0]         adr_b_reg;
3438
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
3439 7 unneback
 
3440
   parameter init = 0;
3441
   parameter memory_file = "vl_ram.vmem";
3442
   generate if (init) begin : init_mem
3443
   initial
3444
     begin
3445
        $readmemh(memory_file, ram);
3446
     end
3447
   end
3448
   endgenerate
3449
 
3450 6 unneback
   always @ (posedge clk_a)
3451
   if (we_a)
3452
     ram[adr_a] <= d_a;
3453
   always @ (posedge clk_b)
3454
   adr_b_reg <= adr_b;
3455
   assign q_b = ram[adr_b_reg];
3456 40 unneback
 
3457 6 unneback
endmodule
3458 40 unneback
`endif
3459 6 unneback
 
3460 40 unneback
`ifdef DPRAM_2R1W
3461
`define MODULE dpram_2r1w
3462
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
3463
`undef MODULE
3464
 
3465 6 unneback
   parameter data_width = 32;
3466
   parameter addr_width = 8;
3467
   input [(data_width-1):0]      d_a;
3468
   input [(addr_width-1):0]       adr_a;
3469
   input [(addr_width-1):0]       adr_b;
3470
   input                         we_a;
3471
   output [(data_width-1):0]      q_b;
3472
   output reg [(data_width-1):0] q_a;
3473
   input                         clk_a, clk_b;
3474
   reg [(data_width-1):0]         q_b;
3475
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
3476 7 unneback
 
3477
   parameter init = 0;
3478
   parameter memory_file = "vl_ram.vmem";
3479
   generate if (init) begin : init_mem
3480
   initial
3481
     begin
3482
        $readmemh(memory_file, ram);
3483
     end
3484
   end
3485
   endgenerate
3486
 
3487 6 unneback
   always @ (posedge clk_a)
3488
     begin
3489
        q_a <= ram[adr_a];
3490
        if (we_a)
3491
             ram[adr_a] <= d_a;
3492
     end
3493
   always @ (posedge clk_b)
3494
          q_b <= ram[adr_b];
3495
endmodule
3496 40 unneback
`endif
3497 6 unneback
 
3498 40 unneback
`ifdef DPRAM_2R2W
3499
`define MODULE dpram_2r2w
3500
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
3501
`undef MODULE
3502
 
3503 6 unneback
   parameter data_width = 32;
3504
   parameter addr_width = 8;
3505
   input [(data_width-1):0]      d_a;
3506
   input [(addr_width-1):0]       adr_a;
3507
   input [(addr_width-1):0]       adr_b;
3508
   input                         we_a;
3509
   output [(data_width-1):0]      q_b;
3510
   input [(data_width-1):0]       d_b;
3511
   output reg [(data_width-1):0] q_a;
3512
   input                         we_b;
3513
   input                         clk_a, clk_b;
3514
   reg [(data_width-1):0]         q_b;
3515
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
3516 7 unneback
 
3517
   parameter init = 0;
3518
   parameter memory_file = "vl_ram.vmem";
3519
   generate if (init) begin : init_mem
3520
   initial
3521
     begin
3522
        $readmemh(memory_file, ram);
3523
     end
3524
   end
3525
   endgenerate
3526
 
3527 6 unneback
   always @ (posedge clk_a)
3528
     begin
3529
        q_a <= ram[adr_a];
3530
        if (we_a)
3531
             ram[adr_a] <= d_a;
3532
     end
3533
   always @ (posedge clk_b)
3534
     begin
3535
        q_b <= ram[adr_b];
3536
        if (we_b)
3537
          ram[adr_b] <= d_b;
3538
     end
3539
endmodule
3540 40 unneback
`endif
3541 6 unneback
 
3542
// Content addresable memory, CAM
3543
 
3544 40 unneback
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
3545 6 unneback
// FIFO
3546 40 unneback
`define MODULE fifo_1r1w_fill_level_sync
3547
module `BASE`MODULE (
3548
`undef MODULE
3549 25 unneback
    d, wr, fifo_full,
3550
    q, rd, fifo_empty,
3551
    fill_level,
3552
    clk, rst
3553
    );
3554
 
3555
parameter data_width = 18;
3556
parameter addr_width = 4;
3557 6 unneback
 
3558 25 unneback
// write side
3559
input  [data_width-1:0] d;
3560
input                   wr;
3561
output                  fifo_full;
3562
// read side
3563
output [data_width-1:0] q;
3564
input                   rd;
3565
output                  fifo_empty;
3566
// common
3567
output [addr_width:0]   fill_level;
3568
input rst, clk;
3569
 
3570
wire [addr_width:1] wadr, radr;
3571
 
3572 40 unneback
`define MODULE cnt_bin_ce
3573
`BASE`MODULE
3574 25 unneback
    # ( .length(addr_width))
3575
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
3576 40 unneback
`BASE`MODULE
3577 25 unneback
    # (.length(addr_width))
3578
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
3579 40 unneback
`undef MODULE
3580 25 unneback
 
3581 40 unneback
`define MODULE dpram_1r1w
3582
`BASE`MODULE
3583 25 unneback
    # (.data_width(data_width), .addr_width(addr_width))
3584
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
3585 40 unneback
`undef MODULE
3586 25 unneback
 
3587 40 unneback
`define MODULE cnt_bin_ce_rew_q_zq_l1
3588
`BASE`MODULE
3589 27 unneback
    # (.length(addr_width+1), .level1_value(1<<addr_width))
3590 25 unneback
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
3591 40 unneback
`undef MODULE
3592 25 unneback
endmodule
3593 40 unneback
`endif
3594 25 unneback
 
3595 40 unneback
`ifdef FIFO_2R2W_SYNC_SIMPLEX
3596 27 unneback
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
3597
// RAM is supposed to be larger than the two FIFOs
3598
// LFSR counters used adr pointers
3599 40 unneback
`define MODULE fifo_2r2w_sync_simplex
3600
module `BASE`MODULE (
3601
`undef MODULE
3602 27 unneback
    // a side
3603
    a_d, a_wr, a_fifo_full,
3604
    a_q, a_rd, a_fifo_empty,
3605
    a_fill_level,
3606
    // b side
3607
    b_d, b_wr, b_fifo_full,
3608
    b_q, b_rd, b_fifo_empty,
3609
    b_fill_level,
3610
    // common
3611
    clk, rst
3612
    );
3613
parameter data_width = 8;
3614
parameter addr_width = 5;
3615
parameter fifo_full_level = (1<<addr_width)-1;
3616
 
3617
// a side
3618
input  [data_width-1:0] a_d;
3619
input                   a_wr;
3620
output                  a_fifo_full;
3621
output [data_width-1:0] a_q;
3622
input                   a_rd;
3623
output                  a_fifo_empty;
3624
output [addr_width-1:0] a_fill_level;
3625
 
3626
// b side
3627
input  [data_width-1:0] b_d;
3628
input                   b_wr;
3629
output                  b_fifo_full;
3630
output [data_width-1:0] b_q;
3631
input                   b_rd;
3632
output                  b_fifo_empty;
3633
output [addr_width-1:0] b_fill_level;
3634
 
3635
input                   clk;
3636
input                   rst;
3637
 
3638
// adr_gen
3639
wire [addr_width:1] a_wadr, a_radr;
3640
wire [addr_width:1] b_wadr, b_radr;
3641
// dpram
3642
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
3643
 
3644 40 unneback
`define MODULE cnt_lfsr_ce
3645
`BASE`MODULE
3646 27 unneback
    # ( .length(addr_width))
3647
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
3648
 
3649 40 unneback
`BASE`MODULE
3650 27 unneback
    # (.length(addr_width))
3651
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
3652
 
3653 40 unneback
`BASE`MODULE
3654 27 unneback
    # ( .length(addr_width))
3655
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
3656
 
3657 40 unneback
`BASE`MODULE
3658 27 unneback
    # (.length(addr_width))
3659
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
3660 40 unneback
`undef MODULE
3661 27 unneback
 
3662
// mux read or write adr to DPRAM
3663
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
3664
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
3665
 
3666 40 unneback
`define MODULE dpram_2r2w
3667
`BASE`MODULE
3668 27 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
3669
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
3670
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
3671 40 unneback
`undef MODULE
3672
 
3673
`define MODULE cnt_bin_ce_rew_zq_l1
3674
`BASE`MODULE
3675 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
3676 27 unneback
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
3677
 
3678 40 unneback
`BASE`MODULE
3679 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
3680 27 unneback
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
3681 40 unneback
`undef MODULE
3682 27 unneback
 
3683
endmodule
3684 40 unneback
`endif
3685 27 unneback
 
3686 40 unneback
`ifdef FIFO_CMP_ASYNC
3687
`define MODULE fifo_cmp_async
3688
module `BASE`MODULE ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
3689
`undef MODULE
3690 6 unneback
 
3691 11 unneback
   parameter addr_width = 4;
3692
   parameter N = addr_width-1;
3693 6 unneback
 
3694
   parameter Q1 = 2'b00;
3695
   parameter Q2 = 2'b01;
3696
   parameter Q3 = 2'b11;
3697
   parameter Q4 = 2'b10;
3698
 
3699
   parameter going_empty = 1'b0;
3700
   parameter going_full  = 1'b1;
3701
 
3702
   input [N:0]  wptr, rptr;
3703 14 unneback
   output       fifo_empty;
3704 6 unneback
   output       fifo_full;
3705
   input        wclk, rclk, rst;
3706
 
3707
`ifndef GENERATE_DIRECTION_AS_LATCH
3708
   wire direction;
3709
`endif
3710
`ifdef GENERATE_DIRECTION_AS_LATCH
3711
   reg direction;
3712
`endif
3713
   reg  direction_set, direction_clr;
3714
 
3715
   wire async_empty, async_full;
3716
   wire fifo_full2;
3717 14 unneback
   wire fifo_empty2;
3718 6 unneback
 
3719
   // direction_set
3720
   always @ (wptr[N:N-1] or rptr[N:N-1])
3721
     case ({wptr[N:N-1],rptr[N:N-1]})
3722
       {Q1,Q2} : direction_set <= 1'b1;
3723
       {Q2,Q3} : direction_set <= 1'b1;
3724
       {Q3,Q4} : direction_set <= 1'b1;
3725
       {Q4,Q1} : direction_set <= 1'b1;
3726
       default : direction_set <= 1'b0;
3727
     endcase
3728
 
3729
   // direction_clear
3730
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
3731
     if (rst)
3732
       direction_clr <= 1'b1;
3733
     else
3734
       case ({wptr[N:N-1],rptr[N:N-1]})
3735
         {Q2,Q1} : direction_clr <= 1'b1;
3736
         {Q3,Q2} : direction_clr <= 1'b1;
3737
         {Q4,Q3} : direction_clr <= 1'b1;
3738
         {Q1,Q4} : direction_clr <= 1'b1;
3739
         default : direction_clr <= 1'b0;
3740
       endcase
3741
 
3742 40 unneback
`define MODULE dff_sr
3743 6 unneback
`ifndef GENERATE_DIRECTION_AS_LATCH
3744 40 unneback
    `BASE`MODULE dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
3745 6 unneback
`endif
3746
 
3747
`ifdef GENERATE_DIRECTION_AS_LATCH
3748
   always @ (posedge direction_set or posedge direction_clr)
3749
     if (direction_clr)
3750
       direction <= going_empty;
3751
     else
3752
       direction <= going_full;
3753
`endif
3754
 
3755
   assign async_empty = (wptr == rptr) && (direction==going_empty);
3756
   assign async_full  = (wptr == rptr) && (direction==going_full);
3757
 
3758 40 unneback
    `BASE`MODULE dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
3759
    `BASE`MODULE dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
3760
`undef MODULE
3761 6 unneback
 
3762
/*
3763
   always @ (posedge wclk or posedge rst or posedge async_full)
3764
     if (rst)
3765
       {fifo_full, fifo_full2} <= 2'b00;
3766
     else if (async_full)
3767
       {fifo_full, fifo_full2} <= 2'b11;
3768
     else
3769
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
3770
*/
3771 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
3772 6 unneback
     if (async_empty)
3773
       {fifo_empty, fifo_empty2} <= 2'b11;
3774
     else
3775 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
3776 40 unneback
`define MODULE dff
3777
    `BASE`MODULE # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
3778
    `BASE`MODULE # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
3779
`undef MODULE
3780 27 unneback
endmodule // async_compb
3781 40 unneback
`endif
3782 6 unneback
 
3783 40 unneback
`ifdef FIFO_1R1W_ASYNC
3784
`define MODULE fifo_1r1w_async
3785
module `BASE`MODULE (
3786
`undef MODULE
3787 6 unneback
    d, wr, fifo_full, wr_clk, wr_rst,
3788
    q, rd, fifo_empty, rd_clk, rd_rst
3789
    );
3790
 
3791
parameter data_width = 18;
3792
parameter addr_width = 4;
3793
 
3794
// write side
3795
input  [data_width-1:0] d;
3796
input                   wr;
3797
output                  fifo_full;
3798
input                   wr_clk;
3799
input                   wr_rst;
3800
// read side
3801
output [data_width-1:0] q;
3802
input                   rd;
3803
output                  fifo_empty;
3804
input                   rd_clk;
3805
input                   rd_rst;
3806
 
3807
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
3808 23 unneback
 
3809 40 unneback
`define MODULE cnt_gray_ce_bin
3810
`BASE`MODULE
3811 6 unneback
    # ( .length(addr_width))
3812
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
3813
 
3814 40 unneback
`BASE`MODULE
3815 6 unneback
    # (.length(addr_width))
3816 23 unneback
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
3817 40 unneback
`undef MODULE
3818 6 unneback
 
3819 40 unneback
`define MODULE dpram_1r1w
3820
`BASE`MODULE
3821 6 unneback
    # (.data_width(data_width), .addr_width(addr_width))
3822
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
3823 40 unneback
`undef MODULE
3824 6 unneback
 
3825 40 unneback
`define MODULE fifo_cmp_async
3826
`BASE`MODULE
3827 6 unneback
    # (.addr_width(addr_width))
3828
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
3829 40 unneback
`undef MODULE
3830 6 unneback
 
3831
endmodule
3832 40 unneback
`endif
3833 6 unneback
 
3834 40 unneback
`ifdef FIFO_2R2W_ASYNC
3835
`define MODULE fifo_2r2w_async
3836
module `BASE`MODULE (
3837
`undef MODULE
3838 6 unneback
    // a side
3839
    a_d, a_wr, a_fifo_full,
3840
    a_q, a_rd, a_fifo_empty,
3841
    a_clk, a_rst,
3842
    // b side
3843
    b_d, b_wr, b_fifo_full,
3844
    b_q, b_rd, b_fifo_empty,
3845
    b_clk, b_rst
3846
    );
3847
 
3848
parameter data_width = 18;
3849
parameter addr_width = 4;
3850
 
3851
// a side
3852
input  [data_width-1:0] a_d;
3853
input                   a_wr;
3854
output                  a_fifo_full;
3855
output [data_width-1:0] a_q;
3856
input                   a_rd;
3857
output                  a_fifo_empty;
3858
input                   a_clk;
3859
input                   a_rst;
3860
 
3861
// b side
3862
input  [data_width-1:0] b_d;
3863
input                   b_wr;
3864
output                  b_fifo_full;
3865
output [data_width-1:0] b_q;
3866
input                   b_rd;
3867
output                  b_fifo_empty;
3868
input                   b_clk;
3869
input                   b_rst;
3870
 
3871 40 unneback
`define MODULE fifo_1r1w_async
3872
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
3873 6 unneback
vl_fifo_1r1w_async_a (
3874
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
3875
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
3876
    );
3877
 
3878 40 unneback
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
3879 6 unneback
vl_fifo_1r1w_async_b (
3880
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
3881
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
3882
    );
3883 40 unneback
`undef MODULE
3884
 
3885 6 unneback
endmodule
3886 40 unneback
`endif
3887 6 unneback
 
3888 40 unneback
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
3889
`define MODULE fifo_2r2w_async_simplex
3890
module `BASE`MODULE (
3891
`undef MODULE
3892 6 unneback
    // a side
3893
    a_d, a_wr, a_fifo_full,
3894
    a_q, a_rd, a_fifo_empty,
3895
    a_clk, a_rst,
3896
    // b side
3897
    b_d, b_wr, b_fifo_full,
3898
    b_q, b_rd, b_fifo_empty,
3899
    b_clk, b_rst
3900
    );
3901
 
3902
parameter data_width = 18;
3903
parameter addr_width = 4;
3904
 
3905
// a side
3906
input  [data_width-1:0] a_d;
3907
input                   a_wr;
3908
output                  a_fifo_full;
3909
output [data_width-1:0] a_q;
3910
input                   a_rd;
3911
output                  a_fifo_empty;
3912
input                   a_clk;
3913
input                   a_rst;
3914
 
3915
// b side
3916
input  [data_width-1:0] b_d;
3917
input                   b_wr;
3918
output                  b_fifo_full;
3919
output [data_width-1:0] b_q;
3920
input                   b_rd;
3921
output                  b_fifo_empty;
3922
input                   b_clk;
3923
input                   b_rst;
3924
 
3925
// adr_gen
3926
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
3927
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
3928
// dpram
3929
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
3930
 
3931 40 unneback
`define MODULE cnt_gray_ce_bin
3932
`BASE`MODULE
3933 6 unneback
    # ( .length(addr_width))
3934
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
3935
 
3936 40 unneback
`BASE`MODULE
3937 6 unneback
    # (.length(addr_width))
3938
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
3939
 
3940 40 unneback
`BASE`MODULE
3941 6 unneback
    # ( .length(addr_width))
3942
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
3943
 
3944 40 unneback
`BASE`MODULE
3945 6 unneback
    # (.length(addr_width))
3946
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
3947 40 unneback
`undef MODULE
3948 6 unneback
 
3949
// mux read or write adr to DPRAM
3950
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
3951
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
3952
 
3953 40 unneback
`define MODULE dpram_2r2w
3954
`BASE`MODULE
3955 6 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
3956
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
3957
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
3958 40 unneback
`undef MODULE
3959 6 unneback
 
3960 40 unneback
`define MODULE fifo_cmp_async
3961
`BASE`MODULE
3962 6 unneback
    # (.addr_width(addr_width))
3963
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
3964
 
3965 40 unneback
`BASE`MODULE
3966 6 unneback
    # (.addr_width(addr_width))
3967
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
3968 40 unneback
`undef MODULE
3969 6 unneback
 
3970
endmodule
3971 40 unneback
`endif
3972 12 unneback
//////////////////////////////////////////////////////////////////////
3973
////                                                              ////
3974
////  Versatile library, wishbone stuff                           ////
3975
////                                                              ////
3976
////  Description                                                 ////
3977
////  Wishbone compliant modules                                  ////
3978
////                                                              ////
3979
////                                                              ////
3980
////  To Do:                                                      ////
3981
////   -                                                          ////
3982
////                                                              ////
3983
////  Author(s):                                                  ////
3984
////      - Michael Unneback, unneback@opencores.org              ////
3985
////        ORSoC AB                                              ////
3986
////                                                              ////
3987
//////////////////////////////////////////////////////////////////////
3988
////                                                              ////
3989
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
3990
////                                                              ////
3991
//// This source file may be used and distributed without         ////
3992
//// restriction provided that this copyright statement is not    ////
3993
//// removed from the file and that any derivative work contains  ////
3994
//// the original copyright notice and the associated disclaimer. ////
3995
////                                                              ////
3996
//// This source file is free software; you can redistribute it   ////
3997
//// and/or modify it under the terms of the GNU Lesser General   ////
3998
//// Public License as published by the Free Software Foundation; ////
3999
//// either version 2.1 of the License, or (at your option) any   ////
4000
//// later version.                                               ////
4001
////                                                              ////
4002
//// This source is distributed in the hope that it will be       ////
4003
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
4004
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
4005
//// PURPOSE.  See the GNU Lesser General Public License for more ////
4006
//// details.                                                     ////
4007
////                                                              ////
4008
//// You should have received a copy of the GNU Lesser General    ////
4009
//// Public License along with this source; if not, download it   ////
4010
//// from http://www.opencores.org/lgpl.shtml                     ////
4011
////                                                              ////
4012
//////////////////////////////////////////////////////////////////////
4013
 
4014 40 unneback
`ifdef WB3WB3_BRIDGE
4015 12 unneback
// async wb3 - wb3 bridge
4016
`timescale 1ns/1ns
4017 40 unneback
`define MODULE wb3wb3_bridge
4018
module `BASE`MODULE (
4019
`undef MODULE
4020 12 unneback
        // wishbone slave side
4021
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
4022
        // wishbone master side
4023
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
4024
 
4025
input [31:0] wbs_dat_i;
4026
input [31:2] wbs_adr_i;
4027
input [3:0]  wbs_sel_i;
4028
input [1:0]  wbs_bte_i;
4029
input [2:0]  wbs_cti_i;
4030
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
4031
output [31:0] wbs_dat_o;
4032 14 unneback
output wbs_ack_o;
4033 12 unneback
input wbs_clk, wbs_rst;
4034
 
4035
output [31:0] wbm_dat_o;
4036
output reg [31:2] wbm_adr_o;
4037
output [3:0]  wbm_sel_o;
4038
output reg [1:0]  wbm_bte_o;
4039
output reg [2:0]  wbm_cti_o;
4040 14 unneback
output reg wbm_we_o;
4041
output wbm_cyc_o;
4042 12 unneback
output wbm_stb_o;
4043
input [31:0]  wbm_dat_i;
4044
input wbm_ack_i;
4045
input wbm_clk, wbm_rst;
4046
 
4047
parameter addr_width = 4;
4048
 
4049
// bte
4050
parameter linear       = 2'b00;
4051
parameter wrap4        = 2'b01;
4052
parameter wrap8        = 2'b10;
4053
parameter wrap16       = 2'b11;
4054
// cti
4055
parameter classic      = 3'b000;
4056
parameter incburst     = 3'b010;
4057
parameter endofburst   = 3'b111;
4058
 
4059
parameter wbs_adr  = 1'b0;
4060
parameter wbs_data = 1'b1;
4061
 
4062 33 unneback
parameter wbm_adr0      = 2'b00;
4063
parameter wbm_adr1      = 2'b01;
4064
parameter wbm_data      = 2'b10;
4065
parameter wbm_data_wait = 2'b11;
4066 12 unneback
 
4067
reg [1:0] wbs_bte_reg;
4068
reg wbs;
4069
wire wbs_eoc_alert, wbm_eoc_alert;
4070
reg wbs_eoc, wbm_eoc;
4071
reg [1:0] wbm;
4072
 
4073 14 unneback
wire [1:16] wbs_count, wbm_count;
4074 12 unneback
 
4075
wire [35:0] a_d, a_q, b_d, b_q;
4076
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
4077
reg a_rd_reg;
4078
wire b_rd_adr, b_rd_data;
4079 14 unneback
wire b_rd_data_reg;
4080
wire [35:0] temp;
4081 12 unneback
 
4082
`define WE 5
4083
`define BTE 4:3
4084
`define CTI 2:0
4085
 
4086
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
4087
always @ (posedge wbs_clk or posedge wbs_rst)
4088
if (wbs_rst)
4089
        wbs_eoc <= 1'b0;
4090
else
4091
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
4092
                wbs_eoc <= wbs_bte_i==linear;
4093
        else if (wbs_eoc_alert & (a_rd | a_wr))
4094
                wbs_eoc <= 1'b1;
4095
 
4096 40 unneback
`define MODULE cnt_shreg_ce_clear
4097
`BASE`MODULE # ( .length(16))
4098
`undef MODULE
4099 12 unneback
    cnt0 (
4100
        .cke(wbs_ack_o),
4101
        .clear(wbs_eoc),
4102
        .q(wbs_count),
4103
        .rst(wbs_rst),
4104
        .clk(wbs_clk));
4105
 
4106
always @ (posedge wbs_clk or posedge wbs_rst)
4107
if (wbs_rst)
4108
        wbs <= wbs_adr;
4109
else
4110
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & !a_fifo_full)
4111
                wbs <= wbs_data;
4112
        else if (wbs_eoc & wbs_ack_o)
4113
                wbs <= wbs_adr;
4114
 
4115
// wbs FIFO
4116
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,wbs_bte_i,wbs_cti_i} : {wbs_dat_i,wbs_sel_i};
4117
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & !a_fifo_full :
4118
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
4119
              1'b0;
4120
assign a_rd = !a_fifo_empty;
4121
always @ (posedge wbs_clk or posedge wbs_rst)
4122
if (wbs_rst)
4123
        a_rd_reg <= 1'b0;
4124
else
4125
        a_rd_reg <= a_rd;
4126
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
4127
 
4128
assign wbs_dat_o = a_q[35:4];
4129
 
4130
always @ (posedge wbs_clk or posedge wbs_rst)
4131
if (wbs_rst)
4132 13 unneback
        wbs_bte_reg <= 2'b00;
4133 12 unneback
else
4134 13 unneback
        wbs_bte_reg <= wbs_bte_i;
4135 12 unneback
 
4136
// wbm FIFO
4137
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
4138
always @ (posedge wbm_clk or posedge wbm_rst)
4139
if (wbm_rst)
4140
        wbm_eoc <= 1'b0;
4141
else
4142
        if (wbm==wbm_adr0 & !b_fifo_empty)
4143
                wbm_eoc <= b_q[`BTE] == linear;
4144
        else if (wbm_eoc_alert & wbm_ack_i)
4145
                wbm_eoc <= 1'b1;
4146
 
4147
always @ (posedge wbm_clk or posedge wbm_rst)
4148
if (wbm_rst)
4149
        wbm <= wbm_adr0;
4150
else
4151 33 unneback
/*
4152 12 unneback
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
4153
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
4154
        (wbm==wbm_adr1 & !wbm_we_o) |
4155
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
4156
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
4157 33 unneback
*/
4158
    case (wbm)
4159
    wbm_adr0:
4160
        if (!b_fifo_empty)
4161
            wbm <= wbm_adr1;
4162
    wbm_adr1:
4163
        if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
4164
            wbm <= wbm_data;
4165
    wbm_data:
4166
        if (wbm_ack_i & wbm_eoc)
4167
            wbm <= wbm_adr0;
4168
        else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
4169
            wbm <= wbm_data_wait;
4170
    wbm_data_wait:
4171
        if (!b_fifo_empty)
4172
            wbm <= wbm_data;
4173
    endcase
4174 12 unneback
 
4175
assign b_d = {wbm_dat_i,4'b1111};
4176
assign b_wr = !wbm_we_o & wbm_ack_i;
4177
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
4178
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
4179
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
4180 33 unneback
                   (wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
4181 12 unneback
                   1'b0;
4182
assign b_rd = b_rd_adr | b_rd_data;
4183
 
4184 40 unneback
`define MODULE dff
4185
`BASE`MODULE dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
4186
`undef MODULE
4187
`define MODULE dff_ce
4188
`BASE`MODULE # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
4189
`undef MODULE
4190 12 unneback
 
4191
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
4192
 
4193 40 unneback
`define MODULE cnt_shreg_ce_clear
4194 18 unneback
vl_cnt_shreg_ce_clear # ( .length(16))
4195 40 unneback
`undef MODULE
4196 12 unneback
    cnt1 (
4197
        .cke(wbm_ack_i),
4198
        .clear(wbm_eoc),
4199
        .q(wbm_count),
4200
        .rst(wbm_rst),
4201
        .clk(wbm_clk));
4202
 
4203 33 unneback
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
4204
assign wbm_stb_o = (wbm==wbm_data);
4205 12 unneback
 
4206
always @ (posedge wbm_clk or posedge wbm_rst)
4207
if (wbm_rst)
4208
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
4209
else begin
4210
        if (wbm==wbm_adr0 & !b_fifo_empty)
4211
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
4212
        else if (wbm_eoc_alert & wbm_ack_i)
4213
                wbm_cti_o <= endofburst;
4214
end
4215
 
4216
//async_fifo_dw_simplex_top
4217 40 unneback
`define MODULE fifo_2r2w_async_simplex
4218
`BASE`MODULE
4219
`undef MODULE
4220 12 unneback
# ( .data_width(36), .addr_width(addr_width))
4221
fifo (
4222
    // a side
4223
    .a_d(a_d),
4224
    .a_wr(a_wr),
4225
    .a_fifo_full(a_fifo_full),
4226
    .a_q(a_q),
4227
    .a_rd(a_rd),
4228
    .a_fifo_empty(a_fifo_empty),
4229
    .a_clk(wbs_clk),
4230
    .a_rst(wbs_rst),
4231
    // b side
4232
    .b_d(b_d),
4233
    .b_wr(b_wr),
4234
    .b_fifo_full(b_fifo_full),
4235
    .b_q(b_q),
4236
    .b_rd(b_rd),
4237
    .b_fifo_empty(b_fifo_empty),
4238
    .b_clk(wbm_clk),
4239
    .b_rst(wbm_rst)
4240
    );
4241
 
4242
endmodule
4243 40 unneback
`undef WE
4244
`undef BTE
4245
`undef CTI
4246
`endif
4247 17 unneback
 
4248 40 unneback
`ifdef WB3_ARBITER_TYPE1
4249
`define MODULE wb3_arbiter_type1
4250 39 unneback
module vl_wb3_arbiter_type1 (
4251 40 unneback
`undef MODULE
4252 39 unneback
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
4253
    wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
4254
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
4255
    wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
4256
    wb_clk, wb_rst
4257
);
4258
 
4259
parameter nr_of_ports = 3;
4260
parameter adr_size = 26;
4261
parameter adr_lo   = 2;
4262
parameter dat_size = 32;
4263
parameter sel_size = dat_size/8;
4264
 
4265
localparam aw = (adr_size - adr_lo) * nr_of_ports;
4266
localparam dw = dat_size * nr_of_ports;
4267
localparam sw = sel_size * nr_of_ports;
4268
localparam cw = 3 * nr_of_ports;
4269
localparam bw = 2 * nr_of_ports;
4270
 
4271
input  [dw-1:0] wbm_dat_o;
4272
input  [aw-1:0] wbm_adr_o;
4273
input  [sw-1:0] wbm_sel_o;
4274
input  [cw-1:0] wbm_cti_o;
4275
input  [bw-1:0] wbm_bte_o;
4276
input  [nr_of_ports-1:0] wbm_we_o, wbm_stb_o, wbm_cyc_o;
4277
output [dw-1:0] wbm_dat_i;
4278
output [nr_of_ports-1:0] wbm_ack_i, wbm_err_i, wbm_rty_i;
4279
 
4280
output [dat_size-1:0] wbs_dat_i;
4281
output [adr_size-1:adr_lo] wbs_adr_i;
4282
output [sel_size-1:0] wbs_sel_i;
4283
output [2:0] wbs_cti_i;
4284
output [1:0] wbs_bte_i;
4285
output wbs_we_i, wbs_stb_i, wbs_cyc_i;
4286
input  [dat_size-1:0] wbs_dat_o;
4287
input  wbs_ack_o, wbs_err_o, wbs_rty_o;
4288
 
4289
input wb_clk, wb_rst;
4290
 
4291
wire [nr_of_ports-1:0] select;
4292
wire [nr_of_ports-1:0] state;
4293
wire [nr_of_ports-1:0] eoc; // end-of-cycle
4294
wire [nr_of_ports-1:0] sel;
4295
wire idle;
4296
 
4297
genvar i;
4298
 
4299
assign idle = !(|state);
4300
 
4301
generate
4302
if (nr_of_ports == 2) begin
4303
 
4304
    wire [2:0] wbm1_cti_o, wbm0_cti_o;
4305
 
4306
    assign {wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
4307
 
4308
    assign select = (idle) ? {wbm_cyc_o[1],!wbm_cyc_o[1] & wbm_cyc_o[0]} : 2'b00;
4309
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
4310
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
4311
 
4312
end
4313
endgenerate
4314
 
4315
generate
4316
if (nr_of_ports == 3) begin
4317
 
4318
    wire [2:0] wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
4319
 
4320
    assign {wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
4321
 
4322
    assign select = (idle) ? {wbm_cyc_o[2],!wbm_cyc_o[2] & wbm_cyc_o[1],wbm_cyc_o[2:1]==2'b00 & wbm_cyc_o[0]} : 3'b000;
4323
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
4324
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
4325
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
4326
 
4327
end
4328
endgenerate
4329
 
4330
generate
4331
for (i=0;i<nr_of_ports;i=i+1) begin
4332
    vl_spr sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));
4333
end
4334
endgenerate
4335
 
4336
    assign sel = select | state;
4337
 
4338 40 unneback
`define MODULE mux_andor
4339
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i));
4340
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(adr_size-adr_lo)) mux1 ( .a(wbm_adr_o), .sel(sel), .dout(wbs_adr_i));
4341
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(sel_size)) mux2 ( .a(wbm_sel_o), .sel(sel), .dout(wbs_sel_i));
4342
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(3)) mux3 ( .a(wbm_cti_o), .sel(sel), .dout(wbs_cti_i));
4343
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(2)) mux4 ( .a(wbm_bte_o), .sel(sel), .dout(wbs_bte_i));
4344
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux5 ( .a(wbm_we_o), .sel(sel), .dout(wbs_we_i));
4345
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux6 ( .a(wbm_stb_o), .sel(sel), .dout(wbs_stb_i));
4346
`undef MODULE
4347 39 unneback
    assign wbs_cyc_i = |sel;
4348
 
4349
    assign wbm_dat_i = {nr_of_ports{wbs_dat_o}};
4350
    assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
4351
    assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
4352
    assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
4353
 
4354
endmodule
4355 40 unneback
`endif
4356 39 unneback
 
4357 40 unneback
`ifdef WB_BOOT_ROM
4358 17 unneback
// WB ROM
4359 40 unneback
`define MODULE wb_boot_rom
4360
module `BASE`MODULE (
4361
`undef MODULE
4362 17 unneback
    wb_adr_i, wb_stb_i, wb_cyc_i,
4363 18 unneback
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
4364 17 unneback
 
4365 18 unneback
    parameter adr_hi = 31;
4366
    parameter adr_lo = 28;
4367
    parameter adr_sel = 4'hf;
4368
    parameter addr_width = 5;
4369 33 unneback
/*
4370 17 unneback
`ifndef BOOT_ROM
4371
`define BOOT_ROM "boot_rom.v"
4372
`endif
4373 33 unneback
*/
4374 18 unneback
    input [adr_hi:2]    wb_adr_i;
4375
    input               wb_stb_i;
4376
    input               wb_cyc_i;
4377
    output [31:0]        wb_dat_o;
4378
    output              wb_ack_o;
4379
    output              hit_o;
4380
    input               wb_clk;
4381
    input               wb_rst;
4382
 
4383
    wire hit;
4384
    reg [31:0] wb_dat;
4385
    reg wb_ack;
4386
 
4387
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
4388 17 unneback
 
4389
always @ (posedge wb_clk or posedge wb_rst)
4390
    if (wb_rst)
4391 18 unneback
        wb_dat <= 32'h15000000;
4392 17 unneback
    else
4393 18 unneback
         case (wb_adr_i[addr_width-1:2])
4394 33 unneback
`ifdef BOOT_ROM
4395 17 unneback
`include `BOOT_ROM
4396 33 unneback
`endif
4397 17 unneback
           /*
4398
            // Zero r0 and jump to 0x00000100
4399 18 unneback
 
4400
            1 : wb_dat <= 32'hA8200000;
4401
            2 : wb_dat <= 32'hA8C00100;
4402
            3 : wb_dat <= 32'h44003000;
4403
            4 : wb_dat <= 32'h15000000;
4404 17 unneback
            */
4405
           default:
4406 18 unneback
             wb_dat <= 32'h00000000;
4407 17 unneback
 
4408
         endcase // case (wb_adr_i)
4409
 
4410
 
4411
always @ (posedge wb_clk or posedge wb_rst)
4412
    if (wb_rst)
4413 18 unneback
        wb_ack <= 1'b0;
4414 17 unneback
    else
4415 18 unneback
        wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
4416 17 unneback
 
4417 18 unneback
assign hit_o = hit;
4418
assign wb_dat_o = wb_dat & {32{wb_ack}};
4419
assign wb_ack_o = wb_ack;
4420
 
4421 17 unneback
endmodule
4422 40 unneback
`endif
4423 32 unneback
 
4424 40 unneback
`ifdef WB_DPRAM
4425
`define MODULE wb_dpram
4426
module `BASE`MODULE (
4427
`undef MODULE
4428 32 unneback
        // wishbone slave side a
4429
        wbsa_dat_i, wbsa_adr_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o,
4430
        wbsa_clk, wbsa_rst,
4431
        // wishbone slave side a
4432
        wbsb_dat_i, wbsb_adr_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o,
4433
        wbsb_clk, wbsb_rst);
4434
 
4435
parameter data_width = 32;
4436
parameter addr_width = 8;
4437
 
4438
parameter dat_o_mask_a = 1;
4439
parameter dat_o_mask_b = 1;
4440
 
4441
input [31:0] wbsa_dat_i;
4442
input [addr_width-1:2] wbsa_adr_i;
4443
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
4444
output [31:0] wbsa_dat_o;
4445
output wbsa_ack_o;
4446
input wbsa_clk, wbsa_rst;
4447
 
4448
input [31:0] wbsb_dat_i;
4449
input [addr_width-1:2] wbsb_adr_i;
4450
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
4451
output [31:0] wbsb_dat_o;
4452
output wbsb_ack_o;
4453
input wbsb_clk, wbsb_rst;
4454
 
4455
wire wbsa_dat_tmp, wbsb_dat_tmp;
4456
 
4457 40 unneback
`define MODULE dpram_2r2w
4458
`BASE`MODULE # (
4459
`undef MODULE
4460 33 unneback
    .data_width(data_width), .addr_width(addr_width) )
4461 32 unneback
dpram0(
4462
    .d_a(wbsa_dat_i),
4463
    .q_a(wbsa_dat_tmp),
4464
    .adr_a(wbsa_adr_i),
4465
    .we_a(wbsa_we_i),
4466
    .clk_a(wbsa_clk),
4467
    .d_b(wbsb_dat_i),
4468
    .q_b(wbsb_dat_tmp),
4469
    .adr_b(wbsb_adr_i),
4470
    .we_b(wbsb_we_i),
4471
    .clk_b(wbsb_clk) );
4472
 
4473 33 unneback
generate if (dat_o_mask_a==1)
4474 32 unneback
    assign wbsa_dat_o = wbsa_dat_tmp & {data_width{wbsa_ack_o}};
4475
endgenerate
4476 33 unneback
generate if (dat_o_mask_a==0)
4477 32 unneback
    assign wbsa_dat_o = wbsa_dat_tmp;
4478
endgenerate
4479
 
4480 33 unneback
generate if (dat_o_mask_b==1)
4481 32 unneback
    assign wbsb_dat_o = wbsb_dat_tmp & {data_width{wbsb_ack_o}};
4482
endgenerate
4483 33 unneback
generate if (dat_o_mask_b==0)
4484 32 unneback
    assign wbsb_dat_o = wbsb_dat_tmp;
4485
endgenerate
4486
 
4487 40 unneback
`define MODULE spr
4488
`BASE`MODULE ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
4489
`BASE`MODULE ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
4490
`undef MODULE
4491 32 unneback
 
4492
endmodule
4493 40 unneback
`endif
4494 18 unneback
//////////////////////////////////////////////////////////////////////
4495
////                                                              ////
4496
////  Arithmetic functions                                        ////
4497
////                                                              ////
4498
////  Description                                                 ////
4499
////  Arithmetic functions for ALU and DSP                        ////
4500
////                                                              ////
4501
////                                                              ////
4502
////  To Do:                                                      ////
4503
////   -                                                          ////
4504
////                                                              ////
4505
////  Author(s):                                                  ////
4506
////      - Michael Unneback, unneback@opencores.org              ////
4507
////        ORSoC AB                                              ////
4508
////                                                              ////
4509
//////////////////////////////////////////////////////////////////////
4510
////                                                              ////
4511
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
4512
////                                                              ////
4513
//// This source file may be used and distributed without         ////
4514
//// restriction provided that this copyright statement is not    ////
4515
//// removed from the file and that any derivative work contains  ////
4516
//// the original copyright notice and the associated disclaimer. ////
4517
////                                                              ////
4518
//// This source file is free software; you can redistribute it   ////
4519
//// and/or modify it under the terms of the GNU Lesser General   ////
4520
//// Public License as published by the Free Software Foundation; ////
4521
//// either version 2.1 of the License, or (at your option) any   ////
4522
//// later version.                                               ////
4523
////                                                              ////
4524
//// This source is distributed in the hope that it will be       ////
4525
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
4526
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
4527
//// PURPOSE.  See the GNU Lesser General Public License for more ////
4528
//// details.                                                     ////
4529
////                                                              ////
4530
//// You should have received a copy of the GNU Lesser General    ////
4531
//// Public License along with this source; if not, download it   ////
4532
//// from http://www.opencores.org/lgpl.shtml                     ////
4533
////                                                              ////
4534
//////////////////////////////////////////////////////////////////////
4535
 
4536 40 unneback
`ifdef MULTS
4537 18 unneback
// signed multiplication
4538 40 unneback
`define MODULE mults
4539
module `BASE`MODULE (a,b,p);
4540
`undef MODULE
4541 18 unneback
parameter operand_a_width = 18;
4542
parameter operand_b_width = 18;
4543
parameter result_hi = 35;
4544
parameter result_lo = 0;
4545
input [operand_a_width-1:0] a;
4546
input [operand_b_width-1:0] b;
4547
output [result_hi:result_lo] p;
4548
wire signed [operand_a_width-1:0] ai;
4549
wire signed [operand_b_width-1:0] bi;
4550
wire signed [operand_a_width+operand_b_width-1:0] result;
4551
 
4552
    assign ai = a;
4553
    assign bi = b;
4554
    assign result = ai * bi;
4555
    assign p = result[result_hi:result_lo];
4556
 
4557
endmodule
4558 40 unneback
`endif
4559
`ifdef MULTS18X18
4560
`define MODULE mults18x18
4561
module `BASE`MODULE (a,b,p);
4562
`undef MODULE
4563 18 unneback
input [17:0] a,b;
4564
output [35:0] p;
4565
vl_mult
4566
    # (.operand_a_width(18), .operand_b_width(18))
4567
    mult0 (.a(a), .b(b), .p(p));
4568
endmodule
4569 40 unneback
`endif
4570 18 unneback
 
4571 40 unneback
`ifdef MULT
4572
`define MODULE mult
4573 18 unneback
// unsigned multiplication
4574 40 unneback
module `BASE`MODULE (a,b,p);
4575
`undef MODULE
4576 18 unneback
parameter operand_a_width = 18;
4577
parameter operand_b_width = 18;
4578
parameter result_hi = 35;
4579
parameter result_lo = 0;
4580
input [operand_a_width-1:0] a;
4581
input [operand_b_width-1:0] b;
4582
output [result_hi:result_hi] p;
4583
 
4584
wire [operand_a_width+operand_b_width-1:0] result;
4585
 
4586
    assign result = a * b;
4587
    assign p = result[result_hi:result_lo];
4588
 
4589
endmodule
4590 40 unneback
`endif
4591 18 unneback
 
4592 40 unneback
`ifdef SHIFT_UNIT_32
4593
`define MODULE shift_unit_32
4594 18 unneback
// shift unit
4595
// supporting the following shift functions
4596
//   SLL
4597
//   SRL
4598
//   SRA
4599
`define SHIFT_UNIT_MULT # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7))
4600 40 unneback
module `BASE`MODULE( din, s, dout, opcode);
4601
`undef MODULE
4602 18 unneback
input [31:0] din; // data in operand
4603
input [4:0] s; // shift operand
4604
input [1:0] opcode;
4605
output [31:0] dout;
4606
 
4607
parameter opcode_sll = 2'b00;
4608
//parameter opcode_srl = 2'b01;
4609
parameter opcode_sra = 2'b10;
4610
//parameter opcode_ror = 2'b11;
4611
 
4612
wire sll, sra;
4613
assign sll = opcode == opcode_sll;
4614
assign sra = opcode == opcode_sra;
4615
 
4616
wire [15:1] s1;
4617
wire [3:0] sign;
4618
wire [7:0] tmp [0:3];
4619
 
4620
// first stage is multiplier based
4621
// shift operand as fractional 8.7
4622
assign s1[15] = sll & s[2:0]==3'd7;
4623
assign s1[14] = sll & s[2:0]==3'd6;
4624
assign s1[13] = sll & s[2:0]==3'd5;
4625
assign s1[12] = sll & s[2:0]==3'd4;
4626
assign s1[11] = sll & s[2:0]==3'd3;
4627
assign s1[10] = sll & s[2:0]==3'd2;
4628
assign s1[ 9] = sll & s[2:0]==3'd1;
4629
assign s1[ 8] = s[2:0]==3'd0;
4630
assign s1[ 7] = !sll & s[2:0]==3'd1;
4631
assign s1[ 6] = !sll & s[2:0]==3'd2;
4632
assign s1[ 5] = !sll & s[2:0]==3'd3;
4633
assign s1[ 4] = !sll & s[2:0]==3'd4;
4634
assign s1[ 3] = !sll & s[2:0]==3'd5;
4635
assign s1[ 2] = !sll & s[2:0]==3'd6;
4636
assign s1[ 1] = !sll & s[2:0]==3'd7;
4637
 
4638
assign sign[3] = din[31] & sra;
4639
assign sign[2] = sign[3] & (&din[31:24]);
4640
assign sign[1] = sign[2] & (&din[23:16]);
4641
assign sign[0] = sign[1] & (&din[15:8]);
4642 40 unneback
`define MODULE mults
4643
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte3 ( .a({sign[3], {8{sign[3]}},din[31:24], din[23:16]}), .b({1'b0,s1}), .p(tmp[3]));
4644
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte2 ( .a({sign[2], din[31:24]  ,din[23:16],  din[15:8]}), .b({1'b0,s1}), .p(tmp[2]));
4645
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte1 ( .a({sign[1], din[23:16]  ,din[15:8],   din[7:0]}), .b({1'b0,s1}), .p(tmp[1]));
4646
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte0 ( .a({sign[0], din[15:8]   ,din[7:0],    8'h00}),      .b({1'b0,s1}), .p(tmp[0]));
4647
`undef MODULE
4648 18 unneback
// second stage is multiplexer based
4649
// shift on byte level
4650
 
4651
// mux byte 3
4652
assign dout[31:24] = (s[4:3]==2'b00) ? tmp[3] :
4653
                     (sll & s[4:3]==2'b01) ? tmp[2] :
4654
                     (sll & s[4:3]==2'b10) ? tmp[1] :
4655
                     (sll & s[4:3]==2'b11) ? tmp[0] :
4656
                     {8{sign[3]}};
4657
 
4658
// mux byte 2
4659
assign dout[23:16] = (s[4:3]==2'b00) ? tmp[2] :
4660
                     (sll & s[4:3]==2'b01) ? tmp[1] :
4661
                     (sll & s[4:3]==2'b10) ? tmp[0] :
4662
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
4663
                     (s[4:3]==2'b01) ? tmp[3] :
4664
                     {8{sign[3]}};
4665
 
4666
// mux byte 1
4667
assign dout[15:8]  = (s[4:3]==2'b00) ? tmp[1] :
4668
                     (sll & s[4:3]==2'b01) ? tmp[0] :
4669
                     (sll & s[4:3]==2'b10) ? {8{1'b0}} :
4670
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
4671
                     (s[4:3]==2'b01) ? tmp[2] :
4672
                     (s[4:3]==2'b10) ? tmp[3] :
4673
                     {8{sign[3]}};
4674
 
4675
// mux byte 0
4676
assign dout[7:0]   = (s[4:3]==2'b00) ? tmp[0] :
4677
                     (sll) ?  {8{1'b0}}:
4678
                     (s[4:3]==2'b01) ? tmp[1] :
4679
                     (s[4:3]==2'b10) ? tmp[2] :
4680
                     tmp[3];
4681
 
4682
endmodule
4683 40 unneback
`endif
4684 18 unneback
 
4685 40 unneback
`ifdef LOGIC_UNIT
4686 18 unneback
// logic unit
4687
// supporting the following logic functions
4688
//    a and b
4689
//    a or  b
4690
//    a xor b
4691
//    not b
4692 40 unneback
`define MODULE logic_unit
4693
module `BASE`MODULE( a, b, result, opcode);
4694
`undef MODULE
4695 18 unneback
parameter width = 32;
4696
parameter opcode_and = 2'b00;
4697
parameter opcode_or  = 2'b01;
4698
parameter opcode_xor = 2'b10;
4699
input [width-1:0] a,b;
4700
output [width-1:0] result;
4701
input [1:0] opcode;
4702
 
4703
assign result = (opcode==opcode_and) ? a & b :
4704
                (opcode==opcode_or)  ? a | b :
4705
                (opcode==opcode_xor) ? a ^ b :
4706
                b;
4707
 
4708
endmodule
4709
 
4710
module vl_arith_unit ( a, b, c_in, add_sub, sign, result, c_out, z, ovfl);
4711
parameter width = 32;
4712
parameter opcode_add = 1'b0;
4713
parameter opcode_sub = 1'b1;
4714
input [width-1:0] a,b;
4715
input c_in, add_sub, sign;
4716
output [width-1:0] result;
4717
output c_out, z, ovfl;
4718
 
4719
assign {c_out,result} = {(a[width-1] & sign),a} + ({a[width-1] & sign,b} ^ {(width+1){(add_sub==opcode_sub)}}) + {{(width-1){1'b0}},(c_in | (add_sub==opcode_sub))};
4720
assign z = (result=={width{1'b0}});
4721
assign ovfl = ( a[width-1] &  b[width-1] & ~result[width-1]) |
4722
               (~a[width-1] & ~b[width-1] &  result[width-1]);
4723
endmodule
4724 40 unneback
`endif

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