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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Blame information for rev 42

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1 40 unneback
`ifndef BASE
2
`define BASE vl_
3
`endif
4
 
5
`ifdef ALL
6
 
7
`define GBUF
8
`define SYNC_RST
9
`define PLL
10
 
11
`define MULTS
12
`define MULTS18X18
13
`define MULT
14
`define SHIFT_UNIT_32
15
`define LOGIC_UNIT
16
 
17
`define CNT_SHREG_WRAP
18
`define CNT_SHREG_CE_WRAP
19
`define CNT_SHREG_CE_CLEAR
20
`define CNT_SHREG_CE_CLEAR_WRAP
21
 
22
`define MUX_ANDOR
23
`define MUX2_ANDOR
24
`define MUX3_ANDOR
25
`define MUX4_ANDOR
26
`define MUX5_ANDOR
27
`define MUX6_ANDOR
28
 
29
`define ROM_INIT
30
`define RAM
31
`define RAM_BE
32
`define DPRAM_1R1W
33
`define DPRAM_2R1W
34
`define DPRAM_2R2W
35
`define FIFO_1R1W_FILL_LEVEL_SYNC
36
`define FIFO_2R2W_SYNC_SIMPLEX
37
`define FIFO_CMP_ASYNC
38
`define FIFO_1R1W_ASYNC
39
`define FIFO_2R2W_ASYNC
40
`define FIFO_2R2W_ASYNC_SIMPLEX
41
 
42
`define DFF
43
`define DFF_ARRAY
44
`define DFF_CE
45
`define DFF_CE_CLEAR
46
`define DF_CE_SET
47
`define SPR
48
`define SRP
49
`define DFF_SR
50
`define LATCH
51
`define SHREG
52
`define SHREG_CE
53
`define DELAY
54
`define DELAY_EMPTYFLAG
55
 
56
`define WB3WB3_BRIDGE
57
`define WB3_ARBITER_TYPE1
58
`define WB_BOOT_ROM
59
`define WB_DPRAM
60
 
61
`endif
62
 
63
`ifdef PLL
64
`ifndef SYNC_RST
65
`define SYNC_RST
66
`endif
67
`endif
68
 
69
`ifdef SYNC_RST
70
`ifndef GBUF
71
`define GBUF
72
`endif
73
`endif
74
 
75
`ifdef WB_DPRAM
76
`ifndef DPRAM_2R2W
77
`define DPRAM_2R2W
78
`endif
79
`ifndef SPR
80
`define SPR
81
`endif
82
`endif
83
 
84
`ifdef WB3_ARBITER_TYPE1
85 42 unneback
`ifndef SPR
86
`define SPR
87
`endif
88 40 unneback
`ifndef MUX_ANDOR
89
`define MUX_ANDOR
90
`endif
91
`endif
92
 
93
`ifdef WB3WB3_BRIDGE
94
`ifndef CNT_SHREG_CE_CLEAR
95
`define CNT_SHREG_CE_CLEAR
96
`endif
97
`ifndef DFF
98
`define DFF
99
`endif
100
`ifndef DFF_CE
101
`define DFF_CE
102
`endif
103
`ifndef CNT_SHREG_CE_CLEAR
104
`define CNT_SHREG_CE_CLEAR
105
`endif
106
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
107
`define FIFO_2R2W_ASYNC_SIMPLEX
108
`endif
109
`endif
110
 
111
`ifdef MULTS18X18
112
`ifndef MULTS
113
`define MULTS
114
`endif
115
`endif
116
 
117
`ifdef SHIFT_UNIT_32
118
`ifndef MULTS
119
`define MULTS
120
`endif
121
`endif
122
 
123
`ifdef MUX2_ANDOR
124
`ifndef MUX_ANDOR
125
`define MUX_ANDOR
126
`endif
127
`endif
128
 
129
`ifdef MUX3_ANDOR
130
`ifndef MUX_ANDOR
131
`define MUX_ANDOR
132
`endif
133
`endif
134
 
135
`ifdef MUX4_ANDOR
136
`ifndef MUX_ANDOR
137
`define MUX_ANDOR
138
`endif
139
`endif
140
 
141
`ifdef MUX5_ANDOR
142
`ifndef MUX_ANDOR
143
`define MUX_ANDOR
144
`endif
145
`endif
146
 
147
`ifdef MUX6_ANDOR
148
`ifndef MUX_ANDOR
149
`define MUX_ANDOR
150
`endif
151
`endif
152
 
153
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
154
`ifndef CNT_BIN_CE
155
`define CNT_BIN_CE
156
`endif
157
`ifndef DPRAM_1R1W
158
`define DPRAM_1R1W
159
`endif
160
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
161
`define CNT_BIN_CE_REW_Q_ZQ_L1
162
`endif
163
`endif
164
 
165
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
166
`ifndef CNT_LFSR_CE
167
`define CNT_LFSR_CE
168
`endif
169
`ifndef DPRAM_2R2W
170
`define DPRAM_2R2W
171
`endif
172
`ifndef CNT_BIN_CE_REW_ZQ_L1
173
`define CNT_BIN_CE_REW_ZQ_L1
174
`endif
175
`endif
176
 
177
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
178
`ifndef CNT_GRAY_CE_BIN
179
`define CNT_GRAY_CE_BIN
180
`endif
181
`ifndef DPRAM_2R2W
182
`define DPRAM_2R2W
183
`endif
184
`ifndef FIFO_CMP_ASYNC
185
`define FIFO_CMP_ASYNC
186
`endif
187
`endif
188
 
189
`ifdef FIFO_2R2W_ASYNC
190
`ifndef FIFO_1R1W_ASYNC
191
`define FIFO_1R1W_ASYNC
192
`endif
193
`endif
194
 
195
`ifdef FIFO_1R1W_ASYNC
196
`ifndef CNT_GRAY_CE_BIN
197
`define CNT_GRAY_CE_BIN
198
`endif
199
`ifndef DPRAM_1R1W
200
`define DPRAM_1R1W
201
`endif
202
`ifndef FIFO_CMP_ASYNC
203
`define FIFO_CMP_ASYNC
204
`endif
205
`endif
206
 
207
`ifdef FIFO_CMP_ASYNC
208
`ifndef DFF_SR
209
`define DFF_SR
210
`endif
211
`ifndef DFF
212
`define DFF
213
`endif
214
`endif
215 6 unneback
//////////////////////////////////////////////////////////////////////
216
////                                                              ////
217
////  Versatile library, clock and reset                          ////
218
////                                                              ////
219
////  Description                                                 ////
220
////  Logic related to clock and reset                            ////
221
////                                                              ////
222
////                                                              ////
223
////  To Do:                                                      ////
224
////   - add more different registers                             ////
225
////                                                              ////
226
////  Author(s):                                                  ////
227
////      - Michael Unneback, unneback@opencores.org              ////
228
////        ORSoC AB                                              ////
229
////                                                              ////
230
//////////////////////////////////////////////////////////////////////
231
////                                                              ////
232
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
233
////                                                              ////
234
//// This source file may be used and distributed without         ////
235
//// restriction provided that this copyright statement is not    ////
236
//// removed from the file and that any derivative work contains  ////
237
//// the original copyright notice and the associated disclaimer. ////
238
////                                                              ////
239
//// This source file is free software; you can redistribute it   ////
240
//// and/or modify it under the terms of the GNU Lesser General   ////
241
//// Public License as published by the Free Software Foundation; ////
242
//// either version 2.1 of the License, or (at your option) any   ////
243
//// later version.                                               ////
244
////                                                              ////
245
//// This source is distributed in the hope that it will be       ////
246
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
247
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
248
//// PURPOSE.  See the GNU Lesser General Public License for more ////
249
//// details.                                                     ////
250
////                                                              ////
251
//// You should have received a copy of the GNU Lesser General    ////
252
//// Public License along with this source; if not, download it   ////
253
//// from http://www.opencores.org/lgpl.shtml                     ////
254
////                                                              ////
255
//////////////////////////////////////////////////////////////////////
256
 
257
// Global buffer
258
// usage:
259
// use to enable global buffers for high fan out signals such as clock and reset
260
 
261
`ifdef ACTEL
262 40 unneback
`ifdef GBUF
263 6 unneback
`timescale 1 ns/100 ps
264
// Version: 8.4 8.4.0.33
265
module gbuf(GL,CLK);
266
output GL;
267
input  CLK;
268
 
269
    wire GND;
270
 
271
    GND GND_1_net(.Y(GND));
272
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
273
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
274
 
275
endmodule
276
`timescale 1 ns/1 ns
277 40 unneback
`define MODULE gbuf
278
module `BASE`MODULE ( i, o);
279
`undef MODULE
280 6 unneback
input i;
281
output o;
282
`ifdef SIM_GBUF
283
assign o=i;
284
`else
285
gbuf gbuf_i0 ( .CLK(i), .GL(o));
286
`endif
287
endmodule
288 40 unneback
`endif
289 33 unneback
 
290 6 unneback
`else
291 33 unneback
 
292 40 unneback
`ifdef ALTERA
293
`ifdef GBUF
294 21 unneback
//altera
295 40 unneback
`define MODULE gbuf
296
module `BASE`MODULE ( i, o);
297
`undef MODULE
298 33 unneback
input i;
299
output o;
300
assign o = i;
301
endmodule
302 40 unneback
`endif
303 33 unneback
 
304 6 unneback
`else
305
 
306 40 unneback
`ifdef GBUF
307 6 unneback
`timescale 1 ns/100 ps
308 40 unneback
`define MODULE
309
module `BASE`MODULE ( i, o);
310
`undef MODULE
311 6 unneback
input i;
312
output o;
313
assign o = i;
314
endmodule
315 40 unneback
`endif
316 6 unneback
`endif // ALTERA
317
`endif //ACTEL
318
 
319 40 unneback
`ifdef SYNC_RST
320 6 unneback
// sync reset
321 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
322 6 unneback
// output active high global reset sync with two DFFs 
323
`timescale 1 ns/100 ps
324 40 unneback
`define MODULE sync_rst
325
module `BASE`MODULE ( rst_n_i, rst_o, clk);
326
`undef MODULE
327 6 unneback
input rst_n_i, clk;
328
output rst_o;
329 18 unneback
reg [1:0] tmp;
330 6 unneback
always @ (posedge clk or negedge rst_n_i)
331
if (!rst_n_i)
332 17 unneback
        tmp <= 2'b11;
333 6 unneback
else
334 33 unneback
        tmp <= {1'b0,tmp[1]};
335 40 unneback
`define MODULE gbuf
336
`BASE`MODULE buf_i0( .i(tmp[0]), .o(rst_o));
337
`undef MODULE
338 6 unneback
endmodule
339 40 unneback
`endif
340 6 unneback
 
341 40 unneback
`ifdef PLL
342 6 unneback
// vl_pll
343
`ifdef ACTEL
344 32 unneback
///////////////////////////////////////////////////////////////////////////////
345 17 unneback
`timescale 1 ps/1 ps
346 40 unneback
`define MODULE pll
347
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
348
`undef MODULE
349 6 unneback
parameter index = 0;
350
parameter number_of_clk = 1;
351 17 unneback
parameter period_time_0 = 20000;
352
parameter period_time_1 = 20000;
353
parameter period_time_2 = 20000;
354
parameter lock_delay = 2000000;
355 6 unneback
input clk_i, rst_n_i;
356
output lock;
357
output reg [0:number_of_clk-1] clk_o;
358
output [0:number_of_clk-1] rst_o;
359
 
360
`ifdef SIM_PLL
361
 
362
always
363
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
364
 
365
generate if (number_of_clk > 1)
366
always
367
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
368
endgenerate
369
 
370
generate if (number_of_clk > 2)
371
always
372
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
373
endgenerate
374
 
375
genvar i;
376
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
377
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
378
end
379
endgenerate
380
 
381
assign #lock_delay lock = rst_n_i;
382
 
383
endmodule
384
`else
385
generate if (number_of_clk==1 & index==0) begin
386
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
387
end
388
endgenerate // index==0
389
generate if (number_of_clk==1 & index==1) begin
390
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
391
end
392
endgenerate // index==1
393
generate if (number_of_clk==1 & index==2) begin
394
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
395
end
396
endgenerate // index==2
397
generate if (number_of_clk==1 & index==3) begin
398
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
399
end
400
endgenerate // index==0
401
 
402
generate if (number_of_clk==2 & index==0) begin
403
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
404
end
405
endgenerate // index==0
406
generate if (number_of_clk==2 & index==1) begin
407
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
408
end
409
endgenerate // index==1
410
generate if (number_of_clk==2 & index==2) begin
411
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
412
end
413
endgenerate // index==2
414
generate if (number_of_clk==2 & index==3) begin
415
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
416
end
417
endgenerate // index==0
418
 
419
generate if (number_of_clk==3 & index==0) begin
420
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
421
end
422
endgenerate // index==0
423
generate if (number_of_clk==3 & index==1) begin
424
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
425
end
426
endgenerate // index==1
427
generate if (number_of_clk==3 & index==2) begin
428
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
429
end
430
endgenerate // index==2
431
generate if (number_of_clk==3 & index==3) begin
432
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
433
end
434
endgenerate // index==0
435
 
436
genvar i;
437
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
438 40 unneback
`define MODULE sync_rst
439
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
440
`undef MODULE
441 6 unneback
end
442
endgenerate
443
endmodule
444
`endif
445 32 unneback
///////////////////////////////////////////////////////////////////////////////
446 6 unneback
 
447
`else
448
 
449 32 unneback
///////////////////////////////////////////////////////////////////////////////
450 6 unneback
`ifdef ALTERA
451
 
452 32 unneback
`timescale 1 ps/1 ps
453 40 unneback
`define MODULE pll
454
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
455
`undef MODULE
456 32 unneback
parameter index = 0;
457
parameter number_of_clk = 1;
458
parameter period_time_0 = 20000;
459
parameter period_time_1 = 20000;
460
parameter period_time_2 = 20000;
461
parameter period_time_3 = 20000;
462
parameter period_time_4 = 20000;
463
parameter lock_delay = 2000000;
464
input clk_i, rst_n_i;
465
output lock;
466
output reg [0:number_of_clk-1] clk_o;
467
output [0:number_of_clk-1] rst_o;
468
 
469
`ifdef SIM_PLL
470
 
471
always
472
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
473
 
474
generate if (number_of_clk > 1)
475
always
476
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
477
endgenerate
478
 
479
generate if (number_of_clk > 2)
480
always
481
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
482
endgenerate
483
 
484 33 unneback
generate if (number_of_clk > 3)
485 32 unneback
always
486
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
487
endgenerate
488
 
489 33 unneback
generate if (number_of_clk > 4)
490 32 unneback
always
491
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
492
endgenerate
493
 
494
genvar i;
495
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
496
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
497
end
498
endgenerate
499
 
500 33 unneback
//assign #lock_delay lock = rst_n_i;
501
assign lock = rst_n_i;
502 32 unneback
 
503
endmodule
504 6 unneback
`else
505
 
506 33 unneback
`ifdef VL_PLL0
507
`ifdef VL_PLL0_CLK1
508
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
509
`endif
510
`ifdef VL_PLL0_CLK2
511
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
512
`endif
513
`ifdef VL_PLL0_CLK3
514
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
515
`endif
516
`ifdef VL_PLL0_CLK4
517
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
518
`endif
519
`ifdef VL_PLL0_CLK5
520
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
521
`endif
522
`endif
523 32 unneback
 
524 33 unneback
`ifdef VL_PLL1
525
`ifdef VL_PLL1_CLK1
526
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
527
`endif
528
`ifdef VL_PLL1_CLK2
529
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
530
`endif
531
`ifdef VL_PLL1_CLK3
532
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
533
`endif
534
`ifdef VL_PLL1_CLK4
535
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
536
`endif
537
`ifdef VL_PLL1_CLK5
538
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
539
`endif
540
`endif
541 32 unneback
 
542 33 unneback
`ifdef VL_PLL2
543
`ifdef VL_PLL2_CLK1
544
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
545
`endif
546
`ifdef VL_PLL2_CLK2
547
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
548
`endif
549
`ifdef VL_PLL2_CLK3
550
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
551
`endif
552
`ifdef VL_PLL2_CLK4
553
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
554
`endif
555
`ifdef VL_PLL2_CLK5
556
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
557
`endif
558
`endif
559 32 unneback
 
560 33 unneback
`ifdef VL_PLL3
561
`ifdef VL_PLL3_CLK1
562
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
563
`endif
564
`ifdef VL_PLL3_CLK2
565
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
566
`endif
567
`ifdef VL_PLL3_CLK3
568
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
569
`endif
570
`ifdef VL_PLL3_CLK4
571
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
572
`endif
573
`ifdef VL_PLL3_CLK5
574
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
575
`endif
576
`endif
577 32 unneback
 
578
genvar i;
579
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
580 40 unneback
`define MODULE sync_rst
581
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
582
`undef MODULE
583 32 unneback
end
584
endgenerate
585
endmodule
586
`endif
587
///////////////////////////////////////////////////////////////////////////////
588
 
589
`else
590
 
591 6 unneback
// generic PLL
592 17 unneback
`timescale 1 ps/1 ps
593 40 unneback
`define MODULE pll
594
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
595
`undef MODULE
596 6 unneback
parameter index = 0;
597
parameter number_of_clk = 1;
598 17 unneback
parameter period_time_0 = 20000;
599
parameter period_time_1 = 20000;
600
parameter period_time_2 = 20000;
601 6 unneback
parameter lock_delay = 2000;
602
input clk_i, rst_n_i;
603
output lock;
604
output reg [0:number_of_clk-1] clk_o;
605
output [0:number_of_clk-1] rst_o;
606
 
607
always
608
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
609
 
610
generate if (number_of_clk > 1)
611
always
612
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
613
endgenerate
614
 
615
generate if (number_of_clk > 2)
616
always
617
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
618
endgenerate
619
 
620
genvar i;
621
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
622 40 unneback
`define MODULE sync_rst
623
     `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
624
`undef MODULE
625 6 unneback
end
626
endgenerate
627
 
628
assign #lock_delay lock = rst_n_i;
629
 
630
endmodule
631
 
632
`endif //altera
633 17 unneback
`endif //actel
634 40 unneback
`undef MODULE
635
`endif//////////////////////////////////////////////////////////////////////
636 6 unneback
////                                                              ////
637
////  Versatile library, registers                                ////
638
////                                                              ////
639
////  Description                                                 ////
640
////  Different type of registers                                 ////
641
////                                                              ////
642
////                                                              ////
643
////  To Do:                                                      ////
644
////   - add more different registers                             ////
645
////                                                              ////
646
////  Author(s):                                                  ////
647
////      - Michael Unneback, unneback@opencores.org              ////
648
////        ORSoC AB                                              ////
649
////                                                              ////
650
//////////////////////////////////////////////////////////////////////
651
////                                                              ////
652
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
653
////                                                              ////
654
//// This source file may be used and distributed without         ////
655
//// restriction provided that this copyright statement is not    ////
656
//// removed from the file and that any derivative work contains  ////
657
//// the original copyright notice and the associated disclaimer. ////
658
////                                                              ////
659
//// This source file is free software; you can redistribute it   ////
660
//// and/or modify it under the terms of the GNU Lesser General   ////
661
//// Public License as published by the Free Software Foundation; ////
662
//// either version 2.1 of the License, or (at your option) any   ////
663
//// later version.                                               ////
664
////                                                              ////
665
//// This source is distributed in the hope that it will be       ////
666
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
667
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
668
//// PURPOSE.  See the GNU Lesser General Public License for more ////
669
//// details.                                                     ////
670
////                                                              ////
671
//// You should have received a copy of the GNU Lesser General    ////
672
//// Public License along with this source; if not, download it   ////
673
//// from http://www.opencores.org/lgpl.shtml                     ////
674
////                                                              ////
675
//////////////////////////////////////////////////////////////////////
676
 
677 40 unneback
`ifdef DFF
678
`define MODULE dff
679
module `BASE`MODULE ( d, q, clk, rst);
680
`undef MODULE
681 6 unneback
        parameter width = 1;
682
        parameter reset_value = 0;
683
 
684
        input [width-1:0] d;
685
        input clk, rst;
686
        output reg [width-1:0] q;
687
 
688
        always @ (posedge clk or posedge rst)
689
        if (rst)
690
                q <= reset_value;
691
        else
692
                q <= d;
693
 
694
endmodule
695 40 unneback
`endif
696 6 unneback
 
697 40 unneback
`ifdef DFF_ARRAY
698
`define MODULE dff_array
699
module `BASE`MODULE ( d, q, clk, rst);
700
`undef MODULE
701 6 unneback
 
702
        parameter width = 1;
703
        parameter depth = 2;
704
        parameter reset_value = 1'b0;
705
 
706
        input [width-1:0] d;
707
        input clk, rst;
708
        output [width-1:0] q;
709
        reg  [0:depth-1] q_tmp [width-1:0];
710
        integer i;
711
        always @ (posedge clk or posedge rst)
712
        if (rst) begin
713
            for (i=0;i<depth;i=i+1)
714
                q_tmp[i] <= {width{reset_value}};
715
        end else begin
716
            q_tmp[0] <= d;
717
            for (i=1;i<depth;i=i+1)
718
                q_tmp[i] <= q_tmp[i-1];
719
        end
720
 
721
    assign q = q_tmp[depth-1];
722
 
723
endmodule
724 40 unneback
`endif
725 6 unneback
 
726 40 unneback
`ifdef DFF_CE
727
`define MODULE dff_ce
728
module `BASE`MODULE ( d, ce, q, clk, rst);
729
`undef MODULE
730 6 unneback
 
731
        parameter width = 1;
732
        parameter reset_value = 0;
733
 
734
        input [width-1:0] d;
735
        input ce, clk, rst;
736
        output reg [width-1:0] q;
737
 
738
        always @ (posedge clk or posedge rst)
739
        if (rst)
740
                q <= reset_value;
741
        else
742
                if (ce)
743
                        q <= d;
744
 
745
endmodule
746 40 unneback
`endif
747 6 unneback
 
748 40 unneback
`ifdef DFF_CE_CLEAR
749
`define MODULE dff_ce_clear
750
module `BASE`MODULE ( d, ce, clear, q, clk, rst);
751
`undef MODULE
752 8 unneback
 
753
        parameter width = 1;
754
        parameter reset_value = 0;
755
 
756
        input [width-1:0] d;
757 10 unneback
        input ce, clear, clk, rst;
758 8 unneback
        output reg [width-1:0] q;
759
 
760
        always @ (posedge clk or posedge rst)
761
        if (rst)
762
            q <= reset_value;
763
        else
764
            if (ce)
765
                if (clear)
766
                    q <= {width{1'b0}};
767
                else
768
                    q <= d;
769
 
770
endmodule
771 40 unneback
`endif
772 8 unneback
 
773 40 unneback
`ifdef DF_CE_SET
774
`define MODULE dff_ce_set
775
module `BASE`MODULE ( d, ce, set, q, clk, rst);
776
`undef MODULE
777 24 unneback
 
778
        parameter width = 1;
779
        parameter reset_value = 0;
780
 
781
        input [width-1:0] d;
782
        input ce, set, clk, rst;
783
        output reg [width-1:0] q;
784
 
785
        always @ (posedge clk or posedge rst)
786
        if (rst)
787
            q <= reset_value;
788
        else
789
            if (ce)
790
                if (set)
791
                    q <= {width{1'b1}};
792
                else
793
                    q <= d;
794
 
795
endmodule
796 40 unneback
`endif
797 24 unneback
 
798 40 unneback
`ifdef SPR
799
`define MODULE spr
800
module `BASE`MODULE ( sp, r, q, clk, rst);
801
`undef MODULE
802
 
803 29 unneback
        parameter width = 1;
804
        parameter reset_value = 0;
805
 
806
        input sp, r;
807
        output reg q;
808
        input clk, rst;
809
 
810
        always @ (posedge clk or posedge rst)
811
        if (rst)
812
            q <= reset_value;
813
        else
814
            if (sp)
815
                q <= 1'b1;
816
            else if (r)
817
                q <= 1'b0;
818
 
819
endmodule
820 40 unneback
`endif
821 29 unneback
 
822 40 unneback
`ifdef SRP
823
`define MODULE srp
824
module `BASE`MODULE ( s, rp, q, clk, rst);
825
`undef MODULE
826
 
827 29 unneback
        parameter width = 1;
828
        parameter reset_value = 0;
829
 
830
        input s, rp;
831
        output reg q;
832
        input clk, rst;
833
 
834
        always @ (posedge clk or posedge rst)
835
        if (rst)
836
            q <= reset_value;
837
        else
838
            if (rp)
839
                q <= 1'b0;
840
            else if (s)
841
                q <= 1'b1;
842
 
843
endmodule
844 40 unneback
`endif
845 29 unneback
 
846 40 unneback
`ifdef ALTERA
847 29 unneback
 
848 40 unneback
`ifdef DFF_SR
849 6 unneback
// megafunction wizard: %LPM_FF%
850
// GENERATION: STANDARD
851
// VERSION: WM1.0
852
// MODULE: lpm_ff 
853
 
854
// ============================================================
855
// File Name: dff_sr.v
856
// Megafunction Name(s):
857
//                      lpm_ff
858
//
859
// Simulation Library Files(s):
860
//                      lpm
861
// ============================================================
862
// ************************************************************
863
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
864
//
865
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
866
// ************************************************************
867
 
868
 
869
//Copyright (C) 1991-2010 Altera Corporation
870
//Your use of Altera Corporation's design tools, logic functions 
871
//and other software and tools, and its AMPP partner logic 
872
//functions, and any output files from any of the foregoing 
873
//(including device programming or simulation files), and any 
874
//associated documentation or information are expressly subject 
875
//to the terms and conditions of the Altera Program License 
876
//Subscription Agreement, Altera MegaCore Function License 
877
//Agreement, or other applicable license agreement, including, 
878
//without limitation, that your use is for the sole purpose of 
879
//programming logic devices manufactured by Altera and sold by 
880
//Altera or its authorized distributors.  Please refer to the 
881
//applicable agreement for further details.
882
 
883
 
884
// synopsys translate_off
885
`timescale 1 ps / 1 ps
886
// synopsys translate_on
887 40 unneback
`define MODULE dff_sr
888
module `BASE`MODULE (
889
`undef MODULE
890
 
891 6 unneback
        aclr,
892
        aset,
893
        clock,
894
        data,
895
        q);
896
 
897
        input     aclr;
898
        input     aset;
899
        input     clock;
900
        input     data;
901
        output    q;
902
 
903
        wire [0:0] sub_wire0;
904
        wire [0:0] sub_wire1 = sub_wire0[0:0];
905
        wire  q = sub_wire1;
906
        wire  sub_wire2 = data;
907
        wire  sub_wire3 = sub_wire2;
908
 
909
        lpm_ff  lpm_ff_component (
910
                                .aclr (aclr),
911
                                .clock (clock),
912
                                .data (sub_wire3),
913
                                .aset (aset),
914
                                .q (sub_wire0)
915
                                // synopsys translate_off
916
                                ,
917
                                .aload (),
918
                                .enable (),
919
                                .sclr (),
920
                                .sload (),
921
                                .sset ()
922
                                // synopsys translate_on
923
                                );
924
        defparam
925
                lpm_ff_component.lpm_fftype = "DFF",
926
                lpm_ff_component.lpm_type = "LPM_FF",
927
                lpm_ff_component.lpm_width = 1;
928
 
929
 
930
endmodule
931
 
932
// ============================================================
933
// CNX file retrieval info
934
// ============================================================
935
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
936
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
937
// Retrieval info: PRIVATE: ASET NUMERIC "1"
938
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
939
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
940
// Retrieval info: PRIVATE: DFF NUMERIC "1"
941
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
942
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
943
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
944
// Retrieval info: PRIVATE: SSET NUMERIC "0"
945
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
946
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
947
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
948
// Retrieval info: PRIVATE: nBit NUMERIC "1"
949
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
950
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
951
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
952
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
953
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
954
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
955
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
956
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
957
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
958
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
959
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
960
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
961
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
962
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
963
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
964
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
965
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
966
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
967
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
968
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
969
// Retrieval info: LIB_FILE: lpm
970 40 unneback
`endif
971 6 unneback
 
972
`else
973
 
974 40 unneback
`ifdef DFF_SR
975
`define MODULE dff_sr
976
module `BASE`MODULE ( aclr, aset, clock, data, q);
977
`undef MODULE
978 6 unneback
 
979
    input         aclr;
980
    input         aset;
981
    input         clock;
982
    input         data;
983
    output reg    q;
984
 
985
   always @ (posedge clock or posedge aclr or posedge aset)
986
     if (aclr)
987
       q <= 1'b0;
988
     else if (aset)
989
       q <= 1'b1;
990
     else
991
       q <= data;
992
 
993
endmodule
994 40 unneback
`endif
995 6 unneback
 
996
`endif
997
 
998
// LATCH
999
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
1000
`ifdef ALTERA
1001 40 unneback
 
1002
`ifdef LATCH
1003
`define MODULE latch
1004
module `BASE`MODULE ( d, le, q, clk);
1005
`undef MODULE
1006 6 unneback
input d, le;
1007
output q;
1008
input clk;
1009
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
1010
endmodule
1011 40 unneback
`endif
1012
 
1013 6 unneback
`else
1014 40 unneback
 
1015
`ifdef LATCH
1016
`define MODULE latch
1017
module `BASE`MODULE ( d, le, q, clk);
1018
`undef MODULE
1019 6 unneback
input d, le;
1020
output q;
1021
input clk;/*
1022
   always @ (posedge direction_set or posedge direction_clr)
1023
     if (direction_clr)
1024
       direction <= going_empty;
1025
     else
1026
       direction <= going_full;*/
1027
endmodule
1028 15 unneback
`endif
1029
 
1030 40 unneback
`endif
1031
 
1032
`ifdef SHREG
1033
`define MODULE shreg
1034
module `BASE`MODULE ( d, q, clk, rst);
1035
`undef MODULE
1036
 
1037 17 unneback
parameter depth = 10;
1038
input d;
1039
output q;
1040
input clk, rst;
1041
 
1042
reg [1:depth] dffs;
1043
 
1044
always @ (posedge clk or posedge rst)
1045
if (rst)
1046
    dffs <= {depth{1'b0}};
1047
else
1048
    dffs <= {d,dffs[1:depth-1]};
1049
assign q = dffs[depth];
1050
endmodule
1051 40 unneback
`endif
1052 17 unneback
 
1053 40 unneback
`ifdef SHREG_CE
1054
`define MODULE shreg_ce
1055
module `BASE`MODULE ( d, ce, q, clk, rst);
1056
`undef MODULE
1057 17 unneback
parameter depth = 10;
1058
input d, ce;
1059
output q;
1060
input clk, rst;
1061
 
1062
reg [1:depth] dffs;
1063
 
1064
always @ (posedge clk or posedge rst)
1065
if (rst)
1066
    dffs <= {depth{1'b0}};
1067
else
1068
    if (ce)
1069
        dffs <= {d,dffs[1:depth-1]};
1070
assign q = dffs[depth];
1071
endmodule
1072 40 unneback
`endif
1073 17 unneback
 
1074 40 unneback
`ifdef DELAY
1075
`define MODULE delay
1076
module `BASE`MODULE ( d, q, clk, rst);
1077
`undef MODULE
1078 15 unneback
parameter depth = 10;
1079
input d;
1080
output q;
1081
input clk, rst;
1082
 
1083
reg [1:depth] dffs;
1084
 
1085
always @ (posedge clk or posedge rst)
1086
if (rst)
1087
    dffs <= {depth{1'b0}};
1088
else
1089
    dffs <= {d,dffs[1:depth-1]};
1090
assign q = dffs[depth];
1091 17 unneback
endmodule
1092 40 unneback
`endif
1093 17 unneback
 
1094 40 unneback
`ifdef DELAY_EMPTYFLAG
1095
`define MODULE delay_emptyflag
1096 41 unneback
module `BASE`MODULE ( d, q, emptyflag, clk, rst);
1097 40 unneback
`undef MODULE
1098 17 unneback
parameter depth = 10;
1099
input d;
1100
output q, emptyflag;
1101
input clk, rst;
1102
 
1103
reg [1:depth] dffs;
1104
 
1105
always @ (posedge clk or posedge rst)
1106
if (rst)
1107
    dffs <= {depth{1'b0}};
1108
else
1109
    dffs <= {d,dffs[1:depth-1]};
1110
assign q = dffs[depth];
1111
assign emptyflag = !(|dffs);
1112
endmodule
1113 40 unneback
`endif
1114 17 unneback
//////////////////////////////////////////////////////////////////////
1115 6 unneback
////                                                              ////
1116 18 unneback
////  Logic functions                                             ////
1117
////                                                              ////
1118
////  Description                                                 ////
1119
////  Logic functions such as multiplexers                        ////
1120
////                                                              ////
1121
////                                                              ////
1122
////  To Do:                                                      ////
1123
////   -                                                          ////
1124
////                                                              ////
1125
////  Author(s):                                                  ////
1126
////      - Michael Unneback, unneback@opencores.org              ////
1127
////        ORSoC AB                                              ////
1128
////                                                              ////
1129
//////////////////////////////////////////////////////////////////////
1130
////                                                              ////
1131
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1132
////                                                              ////
1133
//// This source file may be used and distributed without         ////
1134
//// restriction provided that this copyright statement is not    ////
1135
//// removed from the file and that any derivative work contains  ////
1136
//// the original copyright notice and the associated disclaimer. ////
1137
////                                                              ////
1138
//// This source file is free software; you can redistribute it   ////
1139
//// and/or modify it under the terms of the GNU Lesser General   ////
1140
//// Public License as published by the Free Software Foundation; ////
1141
//// either version 2.1 of the License, or (at your option) any   ////
1142
//// later version.                                               ////
1143
////                                                              ////
1144
//// This source is distributed in the hope that it will be       ////
1145
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1146
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1147
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1148
//// details.                                                     ////
1149
////                                                              ////
1150
//// You should have received a copy of the GNU Lesser General    ////
1151
//// Public License along with this source; if not, download it   ////
1152
//// from http://www.opencores.org/lgpl.shtml                     ////
1153
////                                                              ////
1154
//////////////////////////////////////////////////////////////////////
1155 40 unneback
`ifdef MUX_ANDOR
1156
`define MODULE mux_andor
1157
module `BASE`MODULE ( a, sel, dout);
1158
`undef MODULE
1159 36 unneback
 
1160
parameter width = 32;
1161
parameter nr_of_ports = 4;
1162
 
1163
input [nr_of_ports*width-1:0] a;
1164
input [nr_of_ports-1:0] sel;
1165
output reg [width-1:0] dout;
1166
 
1167 38 unneback
integer i,j;
1168
 
1169 36 unneback
always @ (a, sel)
1170
begin
1171
    dout = a[width-1:0] & {width{sel[0]}};
1172 42 unneback
    for (i=1;i<nr_of_ports;i=i+1)
1173
        for (j=0;j<width;j=j+1)
1174
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
1175 36 unneback
end
1176
 
1177
endmodule
1178 40 unneback
`endif
1179 36 unneback
 
1180 40 unneback
`ifdef MUX2_ANDOR
1181
`define MODULE mux2_andor
1182
module `BASE`MODULE ( a1, a0, sel, dout);
1183
`undef MODULE
1184 18 unneback
 
1185 34 unneback
parameter width = 32;
1186 35 unneback
localparam nr_of_ports = 2;
1187 34 unneback
input [width-1:0] a1, a0;
1188
input [nr_of_ports-1:0] sel;
1189
output [width-1:0] dout;
1190
 
1191 40 unneback
`define MODULE mux_andor
1192
`BASE`MODULE
1193 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1194 36 unneback
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
1195 40 unneback
`undef MODULE
1196
 
1197 34 unneback
endmodule
1198 40 unneback
`endif
1199 34 unneback
 
1200 40 unneback
`ifdef MUX3_ANDOR
1201
`define MODULE mux3_andor
1202
module `BASE`MODULE ( a2, a1, a0, sel, dout);
1203
`undef MODULE
1204 34 unneback
 
1205
parameter width = 32;
1206 35 unneback
localparam nr_of_ports = 3;
1207 34 unneback
input [width-1:0] a2, a1, a0;
1208
input [nr_of_ports-1:0] sel;
1209
output [width-1:0] dout;
1210
 
1211 40 unneback
`define MODULE mux_andor
1212
`BASE`MODULE
1213 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1214 36 unneback
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
1215 40 unneback
`undef MODULE
1216 34 unneback
endmodule
1217 40 unneback
`endif
1218 34 unneback
 
1219 40 unneback
`ifdef MUX4_ANDOR
1220
`define MODULE mux4_andor
1221
module `BASE`MODULE ( a3, a2, a1, a0, sel, dout);
1222
`undef MODULE
1223 18 unneback
 
1224
parameter width = 32;
1225 35 unneback
localparam nr_of_ports = 4;
1226 18 unneback
input [width-1:0] a3, a2, a1, a0;
1227
input [nr_of_ports-1:0] sel;
1228 22 unneback
output [width-1:0] dout;
1229 18 unneback
 
1230 40 unneback
`define MODULE mux_andor
1231
`BASE`MODULE
1232 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1233 36 unneback
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
1234 40 unneback
`undef MODULE
1235 18 unneback
 
1236
endmodule
1237 40 unneback
`endif
1238 18 unneback
 
1239 40 unneback
`ifdef MUX5_ANDOR
1240
`define MODULE mux5_andor
1241
module `BASE`MODULE ( a4, a3, a2, a1, a0, sel, dout);
1242
`undef MODULE
1243 18 unneback
 
1244
parameter width = 32;
1245 35 unneback
localparam nr_of_ports = 5;
1246 18 unneback
input [width-1:0] a4, a3, a2, a1, a0;
1247
input [nr_of_ports-1:0] sel;
1248 22 unneback
output [width-1:0] dout;
1249 18 unneback
 
1250 40 unneback
`define MODULE mux_andor
1251
`BASE`MODULE
1252 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1253 36 unneback
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1254 40 unneback
`undef MODULE
1255 18 unneback
 
1256
endmodule
1257 40 unneback
`endif
1258 18 unneback
 
1259 40 unneback
`ifdef MUX6_ANDOR
1260
`define MODULE mux6_andor
1261
module `BASE`MODULE ( a5, a4, a3, a2, a1, a0, sel, dout);
1262
`undef MODULE
1263 18 unneback
 
1264
parameter width = 32;
1265 35 unneback
localparam nr_of_ports = 6;
1266 18 unneback
input [width-1:0] a5, a4, a3, a2, a1, a0;
1267
input [nr_of_ports-1:0] sel;
1268 22 unneback
output [width-1:0] dout;
1269 18 unneback
 
1270 40 unneback
`define MODULE mux_andor
1271
`BASE`MODULE
1272 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1273 36 unneback
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1274 40 unneback
`undef MODULE
1275 18 unneback
 
1276
endmodule
1277 40 unneback
`endif
1278
`ifdef CNT_BIN
1279 18 unneback
//////////////////////////////////////////////////////////////////////
1280
////                                                              ////
1281 6 unneback
////  Versatile counter                                           ////
1282
////                                                              ////
1283
////  Description                                                 ////
1284
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1285
////  counter                                                     ////
1286
////                                                              ////
1287
////  To Do:                                                      ////
1288
////   - add LFSR with more taps                                  ////
1289
////                                                              ////
1290
////  Author(s):                                                  ////
1291
////      - Michael Unneback, unneback@opencores.org              ////
1292
////        ORSoC AB                                              ////
1293
////                                                              ////
1294
//////////////////////////////////////////////////////////////////////
1295
////                                                              ////
1296
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1297
////                                                              ////
1298
//// This source file may be used and distributed without         ////
1299
//// restriction provided that this copyright statement is not    ////
1300
//// removed from the file and that any derivative work contains  ////
1301
//// the original copyright notice and the associated disclaimer. ////
1302
////                                                              ////
1303
//// This source file is free software; you can redistribute it   ////
1304
//// and/or modify it under the terms of the GNU Lesser General   ////
1305
//// Public License as published by the Free Software Foundation; ////
1306
//// either version 2.1 of the License, or (at your option) any   ////
1307
//// later version.                                               ////
1308
////                                                              ////
1309
//// This source is distributed in the hope that it will be       ////
1310
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1311
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1312
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1313
//// details.                                                     ////
1314
////                                                              ////
1315
//// You should have received a copy of the GNU Lesser General    ////
1316
//// Public License along with this source; if not, download it   ////
1317
//// from http://www.opencores.org/lgpl.shtml                     ////
1318
////                                                              ////
1319
//////////////////////////////////////////////////////////////////////
1320
 
1321
// binary counter
1322 22 unneback
 
1323 40 unneback
`define MODULE cnt_bin
1324
module `BASE`MODULE (
1325
`undef MODULE
1326
 q, rst, clk);
1327
 
1328 22 unneback
   parameter length = 4;
1329
   output [length:1] q;
1330
   input rst;
1331
   input clk;
1332
 
1333
   parameter clear_value = 0;
1334
   parameter set_value = 1;
1335
   parameter wrap_value = 0;
1336
   parameter level1_value = 15;
1337
 
1338
   reg  [length:1] qi;
1339
   wire [length:1] q_next;
1340
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1341
 
1342
   always @ (posedge clk or posedge rst)
1343
     if (rst)
1344
       qi <= {length{1'b0}};
1345
     else
1346
       qi <= q_next;
1347
 
1348
   assign q = qi;
1349
 
1350
endmodule
1351 40 unneback
`endif
1352
`ifdef CNT_BIN_CLEAR
1353 22 unneback
//////////////////////////////////////////////////////////////////////
1354
////                                                              ////
1355
////  Versatile counter                                           ////
1356
////                                                              ////
1357
////  Description                                                 ////
1358
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1359
////  counter                                                     ////
1360
////                                                              ////
1361
////  To Do:                                                      ////
1362
////   - add LFSR with more taps                                  ////
1363
////                                                              ////
1364
////  Author(s):                                                  ////
1365
////      - Michael Unneback, unneback@opencores.org              ////
1366
////        ORSoC AB                                              ////
1367
////                                                              ////
1368
//////////////////////////////////////////////////////////////////////
1369
////                                                              ////
1370
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1371
////                                                              ////
1372
//// This source file may be used and distributed without         ////
1373
//// restriction provided that this copyright statement is not    ////
1374
//// removed from the file and that any derivative work contains  ////
1375
//// the original copyright notice and the associated disclaimer. ////
1376
////                                                              ////
1377
//// This source file is free software; you can redistribute it   ////
1378
//// and/or modify it under the terms of the GNU Lesser General   ////
1379
//// Public License as published by the Free Software Foundation; ////
1380
//// either version 2.1 of the License, or (at your option) any   ////
1381
//// later version.                                               ////
1382
////                                                              ////
1383
//// This source is distributed in the hope that it will be       ////
1384
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1385
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1386
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1387
//// details.                                                     ////
1388
////                                                              ////
1389
//// You should have received a copy of the GNU Lesser General    ////
1390
//// Public License along with this source; if not, download it   ////
1391
//// from http://www.opencores.org/lgpl.shtml                     ////
1392
////                                                              ////
1393
//////////////////////////////////////////////////////////////////////
1394
 
1395
// binary counter
1396
 
1397 40 unneback
`define MODULE cnt_bin_clear
1398
module `BASE`MODULE (
1399
`undef MODULE
1400
 clear, q, rst, clk);
1401
 
1402 22 unneback
   parameter length = 4;
1403
   input clear;
1404
   output [length:1] q;
1405
   input rst;
1406
   input clk;
1407
 
1408
   parameter clear_value = 0;
1409
   parameter set_value = 1;
1410
   parameter wrap_value = 0;
1411
   parameter level1_value = 15;
1412
 
1413
   reg  [length:1] qi;
1414
   wire [length:1] q_next;
1415
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1416
 
1417
   always @ (posedge clk or posedge rst)
1418
     if (rst)
1419
       qi <= {length{1'b0}};
1420
     else
1421
       qi <= q_next;
1422
 
1423
   assign q = qi;
1424
 
1425
endmodule
1426 40 unneback
`endif
1427
`ifdef CNT_BIN_CE
1428 22 unneback
//////////////////////////////////////////////////////////////////////
1429
////                                                              ////
1430
////  Versatile counter                                           ////
1431
////                                                              ////
1432
////  Description                                                 ////
1433
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1434
////  counter                                                     ////
1435
////                                                              ////
1436
////  To Do:                                                      ////
1437
////   - add LFSR with more taps                                  ////
1438
////                                                              ////
1439
////  Author(s):                                                  ////
1440
////      - Michael Unneback, unneback@opencores.org              ////
1441
////        ORSoC AB                                              ////
1442
////                                                              ////
1443
//////////////////////////////////////////////////////////////////////
1444
////                                                              ////
1445
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1446
////                                                              ////
1447
//// This source file may be used and distributed without         ////
1448
//// restriction provided that this copyright statement is not    ////
1449
//// removed from the file and that any derivative work contains  ////
1450
//// the original copyright notice and the associated disclaimer. ////
1451
////                                                              ////
1452
//// This source file is free software; you can redistribute it   ////
1453
//// and/or modify it under the terms of the GNU Lesser General   ////
1454
//// Public License as published by the Free Software Foundation; ////
1455
//// either version 2.1 of the License, or (at your option) any   ////
1456
//// later version.                                               ////
1457
////                                                              ////
1458
//// This source is distributed in the hope that it will be       ////
1459
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1460
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1461
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1462
//// details.                                                     ////
1463
////                                                              ////
1464
//// You should have received a copy of the GNU Lesser General    ////
1465
//// Public License along with this source; if not, download it   ////
1466
//// from http://www.opencores.org/lgpl.shtml                     ////
1467
////                                                              ////
1468
//////////////////////////////////////////////////////////////////////
1469
 
1470
// binary counter
1471 6 unneback
 
1472 40 unneback
`define MODULE cnt_bin_ce
1473
module `BASE`MODULE (
1474
`undef MODULE
1475
 cke, q, rst, clk);
1476
 
1477 6 unneback
   parameter length = 4;
1478
   input cke;
1479
   output [length:1] q;
1480
   input rst;
1481
   input clk;
1482
 
1483
   parameter clear_value = 0;
1484
   parameter set_value = 1;
1485
   parameter wrap_value = 0;
1486
   parameter level1_value = 15;
1487
 
1488
   reg  [length:1] qi;
1489
   wire [length:1] q_next;
1490
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1491
 
1492
   always @ (posedge clk or posedge rst)
1493
     if (rst)
1494
       qi <= {length{1'b0}};
1495
     else
1496
     if (cke)
1497
       qi <= q_next;
1498
 
1499
   assign q = qi;
1500
 
1501
endmodule
1502 40 unneback
`endif
1503
`ifdef CNT_BIN_CE_CLEAR
1504 6 unneback
//////////////////////////////////////////////////////////////////////
1505
////                                                              ////
1506
////  Versatile counter                                           ////
1507
////                                                              ////
1508
////  Description                                                 ////
1509
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1510
////  counter                                                     ////
1511
////                                                              ////
1512
////  To Do:                                                      ////
1513
////   - add LFSR with more taps                                  ////
1514
////                                                              ////
1515
////  Author(s):                                                  ////
1516
////      - Michael Unneback, unneback@opencores.org              ////
1517
////        ORSoC AB                                              ////
1518
////                                                              ////
1519
//////////////////////////////////////////////////////////////////////
1520
////                                                              ////
1521
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1522
////                                                              ////
1523
//// This source file may be used and distributed without         ////
1524
//// restriction provided that this copyright statement is not    ////
1525
//// removed from the file and that any derivative work contains  ////
1526
//// the original copyright notice and the associated disclaimer. ////
1527
////                                                              ////
1528
//// This source file is free software; you can redistribute it   ////
1529
//// and/or modify it under the terms of the GNU Lesser General   ////
1530
//// Public License as published by the Free Software Foundation; ////
1531
//// either version 2.1 of the License, or (at your option) any   ////
1532
//// later version.                                               ////
1533
////                                                              ////
1534
//// This source is distributed in the hope that it will be       ////
1535
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1536
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1537
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1538
//// details.                                                     ////
1539
////                                                              ////
1540
//// You should have received a copy of the GNU Lesser General    ////
1541
//// Public License along with this source; if not, download it   ////
1542
//// from http://www.opencores.org/lgpl.shtml                     ////
1543
////                                                              ////
1544
//////////////////////////////////////////////////////////////////////
1545
 
1546
// binary counter
1547
 
1548 40 unneback
`define MODULE cnt_bin_ce_clear
1549
module `BASE`MODULE (
1550
`undef MODULE
1551
 clear, cke, q, rst, clk);
1552
 
1553 6 unneback
   parameter length = 4;
1554
   input clear;
1555
   input cke;
1556
   output [length:1] q;
1557
   input rst;
1558
   input clk;
1559
 
1560
   parameter clear_value = 0;
1561
   parameter set_value = 1;
1562
   parameter wrap_value = 0;
1563
   parameter level1_value = 15;
1564
 
1565
   reg  [length:1] qi;
1566
   wire [length:1] q_next;
1567
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1568
 
1569
   always @ (posedge clk or posedge rst)
1570
     if (rst)
1571
       qi <= {length{1'b0}};
1572
     else
1573
     if (cke)
1574
       qi <= q_next;
1575
 
1576
   assign q = qi;
1577
 
1578
endmodule
1579 40 unneback
`endif
1580
`ifdef CNT_BIN_CE_CLEAR_L1_L2
1581 6 unneback
//////////////////////////////////////////////////////////////////////
1582
////                                                              ////
1583
////  Versatile counter                                           ////
1584
////                                                              ////
1585
////  Description                                                 ////
1586
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1587
////  counter                                                     ////
1588
////                                                              ////
1589
////  To Do:                                                      ////
1590
////   - add LFSR with more taps                                  ////
1591
////                                                              ////
1592
////  Author(s):                                                  ////
1593
////      - Michael Unneback, unneback@opencores.org              ////
1594
////        ORSoC AB                                              ////
1595
////                                                              ////
1596
//////////////////////////////////////////////////////////////////////
1597
////                                                              ////
1598
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1599
////                                                              ////
1600
//// This source file may be used and distributed without         ////
1601
//// restriction provided that this copyright statement is not    ////
1602
//// removed from the file and that any derivative work contains  ////
1603
//// the original copyright notice and the associated disclaimer. ////
1604
////                                                              ////
1605
//// This source file is free software; you can redistribute it   ////
1606
//// and/or modify it under the terms of the GNU Lesser General   ////
1607
//// Public License as published by the Free Software Foundation; ////
1608
//// either version 2.1 of the License, or (at your option) any   ////
1609
//// later version.                                               ////
1610
////                                                              ////
1611
//// This source is distributed in the hope that it will be       ////
1612
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1613
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1614
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1615
//// details.                                                     ////
1616
////                                                              ////
1617
//// You should have received a copy of the GNU Lesser General    ////
1618
//// Public License along with this source; if not, download it   ////
1619
//// from http://www.opencores.org/lgpl.shtml                     ////
1620
////                                                              ////
1621
//////////////////////////////////////////////////////////////////////
1622
 
1623
// binary counter
1624 29 unneback
 
1625 40 unneback
`define MODULE cnt_bin_ce_clear_l1_l2
1626
module `BASE`MODULE (
1627
`undef MODULE
1628
 clear, cke, q, level1, level2, rst, clk);
1629
 
1630 29 unneback
   parameter length = 4;
1631
   input clear;
1632
   input cke;
1633
   output [length:1] q;
1634
   output reg level1;
1635
   output reg level2;
1636
   input rst;
1637
   input clk;
1638
 
1639
   parameter clear_value = 0;
1640
   parameter set_value = 1;
1641 30 unneback
   parameter wrap_value = 15;
1642
   parameter level1_value = 8;
1643
   parameter level2_value = 15;
1644 29 unneback
 
1645
   wire rew;
1646 30 unneback
   assign rew = 1'b0;
1647 29 unneback
   reg  [length:1] qi;
1648
   wire [length:1] q_next;
1649
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1650
 
1651
   always @ (posedge clk or posedge rst)
1652
     if (rst)
1653
       qi <= {length{1'b0}};
1654
     else
1655
     if (cke)
1656
       qi <= q_next;
1657
 
1658
   assign q = qi;
1659
 
1660
 
1661
    always @ (posedge clk or posedge rst)
1662
    if (rst)
1663
        level1 <= 1'b0;
1664
    else
1665
    if (cke)
1666
    if (clear)
1667
        level1 <= 1'b0;
1668
    else if (q_next == level1_value)
1669
        level1 <= 1'b1;
1670
    else if (qi == level1_value & rew)
1671
        level1 <= 1'b0;
1672
 
1673
    always @ (posedge clk or posedge rst)
1674
    if (rst)
1675
        level2 <= 1'b0;
1676
    else
1677
    if (cke)
1678
    if (clear)
1679
        level2 <= 1'b0;
1680
    else if (q_next == level2_value)
1681
        level2 <= 1'b1;
1682
    else if (qi == level2_value & rew)
1683
        level2 <= 1'b0;
1684
endmodule
1685 40 unneback
`endif
1686
`ifdef CNT_BIN_CE_CLEAR_SET_REW
1687 29 unneback
//////////////////////////////////////////////////////////////////////
1688
////                                                              ////
1689
////  Versatile counter                                           ////
1690
////                                                              ////
1691
////  Description                                                 ////
1692
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1693
////  counter                                                     ////
1694
////                                                              ////
1695
////  To Do:                                                      ////
1696
////   - add LFSR with more taps                                  ////
1697
////                                                              ////
1698
////  Author(s):                                                  ////
1699
////      - Michael Unneback, unneback@opencores.org              ////
1700
////        ORSoC AB                                              ////
1701
////                                                              ////
1702
//////////////////////////////////////////////////////////////////////
1703
////                                                              ////
1704
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1705
////                                                              ////
1706
//// This source file may be used and distributed without         ////
1707
//// restriction provided that this copyright statement is not    ////
1708
//// removed from the file and that any derivative work contains  ////
1709
//// the original copyright notice and the associated disclaimer. ////
1710
////                                                              ////
1711
//// This source file is free software; you can redistribute it   ////
1712
//// and/or modify it under the terms of the GNU Lesser General   ////
1713
//// Public License as published by the Free Software Foundation; ////
1714
//// either version 2.1 of the License, or (at your option) any   ////
1715
//// later version.                                               ////
1716
////                                                              ////
1717
//// This source is distributed in the hope that it will be       ////
1718
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1719
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1720
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1721
//// details.                                                     ////
1722
////                                                              ////
1723
//// You should have received a copy of the GNU Lesser General    ////
1724
//// Public License along with this source; if not, download it   ////
1725
//// from http://www.opencores.org/lgpl.shtml                     ////
1726
////                                                              ////
1727
//////////////////////////////////////////////////////////////////////
1728
 
1729
// binary counter
1730 6 unneback
 
1731 40 unneback
`define MODULE cnt_bin_ce_clear_set_rew
1732
module `BASE`MODULE (
1733
`undef MODULE
1734
 clear, set, cke, rew, q, rst, clk);
1735
 
1736 6 unneback
   parameter length = 4;
1737
   input clear;
1738
   input set;
1739
   input cke;
1740
   input rew;
1741
   output [length:1] q;
1742
   input rst;
1743
   input clk;
1744
 
1745
   parameter clear_value = 0;
1746
   parameter set_value = 1;
1747
   parameter wrap_value = 0;
1748
   parameter level1_value = 15;
1749
 
1750
   reg  [length:1] qi;
1751
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1752
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
1753
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
1754
   assign q_next = rew ? q_next_rew : q_next_fw;
1755
 
1756
   always @ (posedge clk or posedge rst)
1757
     if (rst)
1758
       qi <= {length{1'b0}};
1759
     else
1760
     if (cke)
1761
       qi <= q_next;
1762
 
1763
   assign q = qi;
1764
 
1765
endmodule
1766 40 unneback
`endif
1767
`ifdef CNT_BIN_CE_REW_L1
1768 6 unneback
//////////////////////////////////////////////////////////////////////
1769
////                                                              ////
1770
////  Versatile counter                                           ////
1771
////                                                              ////
1772
////  Description                                                 ////
1773
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1774
////  counter                                                     ////
1775
////                                                              ////
1776
////  To Do:                                                      ////
1777
////   - add LFSR with more taps                                  ////
1778
////                                                              ////
1779
////  Author(s):                                                  ////
1780
////      - Michael Unneback, unneback@opencores.org              ////
1781
////        ORSoC AB                                              ////
1782
////                                                              ////
1783
//////////////////////////////////////////////////////////////////////
1784
////                                                              ////
1785
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1786
////                                                              ////
1787
//// This source file may be used and distributed without         ////
1788
//// restriction provided that this copyright statement is not    ////
1789
//// removed from the file and that any derivative work contains  ////
1790
//// the original copyright notice and the associated disclaimer. ////
1791
////                                                              ////
1792
//// This source file is free software; you can redistribute it   ////
1793
//// and/or modify it under the terms of the GNU Lesser General   ////
1794
//// Public License as published by the Free Software Foundation; ////
1795
//// either version 2.1 of the License, or (at your option) any   ////
1796
//// later version.                                               ////
1797
////                                                              ////
1798
//// This source is distributed in the hope that it will be       ////
1799
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1800
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1801
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1802
//// details.                                                     ////
1803
////                                                              ////
1804
//// You should have received a copy of the GNU Lesser General    ////
1805
//// Public License along with this source; if not, download it   ////
1806
//// from http://www.opencores.org/lgpl.shtml                     ////
1807
////                                                              ////
1808
//////////////////////////////////////////////////////////////////////
1809
 
1810
// binary counter
1811
 
1812 40 unneback
`define MODULE cnt_bin_ce_rew_l1
1813
module `BASE`MODULE (
1814
`undef MODULE
1815
 cke, rew, level1, rst, clk);
1816
 
1817 6 unneback
   parameter length = 4;
1818
   input cke;
1819
   input rew;
1820
   output reg level1;
1821
   input rst;
1822
   input clk;
1823
 
1824
   parameter clear_value = 0;
1825
   parameter set_value = 1;
1826
   parameter wrap_value = 1;
1827
   parameter level1_value = 15;
1828
 
1829 29 unneback
   wire clear;
1830 30 unneback
   assign clear = 1'b0;
1831 6 unneback
   reg  [length:1] qi;
1832
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1833
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1834
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1835
   assign q_next = rew ? q_next_rew : q_next_fw;
1836
 
1837
   always @ (posedge clk or posedge rst)
1838
     if (rst)
1839
       qi <= {length{1'b0}};
1840
     else
1841
     if (cke)
1842
       qi <= q_next;
1843
 
1844
 
1845
 
1846
    always @ (posedge clk or posedge rst)
1847
    if (rst)
1848
        level1 <= 1'b0;
1849
    else
1850
    if (cke)
1851 29 unneback
    if (clear)
1852
        level1 <= 1'b0;
1853
    else if (q_next == level1_value)
1854 6 unneback
        level1 <= 1'b1;
1855
    else if (qi == level1_value & rew)
1856
        level1 <= 1'b0;
1857
endmodule
1858 40 unneback
`endif
1859
`ifdef CNT_BIN_CE_REW_ZQ_L1
1860 6 unneback
//////////////////////////////////////////////////////////////////////
1861
////                                                              ////
1862
////  Versatile counter                                           ////
1863
////                                                              ////
1864
////  Description                                                 ////
1865
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1866
////  counter                                                     ////
1867
////                                                              ////
1868
////  To Do:                                                      ////
1869
////   - add LFSR with more taps                                  ////
1870
////                                                              ////
1871
////  Author(s):                                                  ////
1872
////      - Michael Unneback, unneback@opencores.org              ////
1873
////        ORSoC AB                                              ////
1874
////                                                              ////
1875
//////////////////////////////////////////////////////////////////////
1876
////                                                              ////
1877
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1878
////                                                              ////
1879
//// This source file may be used and distributed without         ////
1880
//// restriction provided that this copyright statement is not    ////
1881
//// removed from the file and that any derivative work contains  ////
1882
//// the original copyright notice and the associated disclaimer. ////
1883
////                                                              ////
1884
//// This source file is free software; you can redistribute it   ////
1885
//// and/or modify it under the terms of the GNU Lesser General   ////
1886
//// Public License as published by the Free Software Foundation; ////
1887
//// either version 2.1 of the License, or (at your option) any   ////
1888
//// later version.                                               ////
1889
////                                                              ////
1890
//// This source is distributed in the hope that it will be       ////
1891
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1892
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1893
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1894
//// details.                                                     ////
1895
////                                                              ////
1896
//// You should have received a copy of the GNU Lesser General    ////
1897
//// Public License along with this source; if not, download it   ////
1898
//// from http://www.opencores.org/lgpl.shtml                     ////
1899
////                                                              ////
1900
//////////////////////////////////////////////////////////////////////
1901
 
1902 25 unneback
// binary counter
1903
 
1904 40 unneback
`define MODULE cnt_bin_ce_rew_zq_l1
1905
module `BASE`MODULE (
1906
`undef MODULE
1907
 cke, rew, zq, level1, rst, clk);
1908
 
1909 25 unneback
   parameter length = 4;
1910
   input cke;
1911
   input rew;
1912
   output reg zq;
1913
   output reg level1;
1914
   input rst;
1915
   input clk;
1916
 
1917
   parameter clear_value = 0;
1918
   parameter set_value = 1;
1919
   parameter wrap_value = 1;
1920
   parameter level1_value = 15;
1921
 
1922 29 unneback
   wire clear;
1923 30 unneback
   assign clear = 1'b0;
1924 25 unneback
   reg  [length:1] qi;
1925
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1926
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1927
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1928
   assign q_next = rew ? q_next_rew : q_next_fw;
1929
 
1930
   always @ (posedge clk or posedge rst)
1931
     if (rst)
1932
       qi <= {length{1'b0}};
1933
     else
1934
     if (cke)
1935
       qi <= q_next;
1936
 
1937
 
1938
 
1939
   always @ (posedge clk or posedge rst)
1940
     if (rst)
1941
       zq <= 1'b1;
1942
     else
1943
     if (cke)
1944
       zq <= q_next == {length{1'b0}};
1945
 
1946
    always @ (posedge clk or posedge rst)
1947
    if (rst)
1948
        level1 <= 1'b0;
1949
    else
1950
    if (cke)
1951 29 unneback
    if (clear)
1952
        level1 <= 1'b0;
1953
    else if (q_next == level1_value)
1954 25 unneback
        level1 <= 1'b1;
1955
    else if (qi == level1_value & rew)
1956
        level1 <= 1'b0;
1957
endmodule
1958 40 unneback
`endif
1959
`ifdef CNT_BIN_CE_REW_Q_ZQ_L1
1960 25 unneback
//////////////////////////////////////////////////////////////////////
1961
////                                                              ////
1962
////  Versatile counter                                           ////
1963
////                                                              ////
1964
////  Description                                                 ////
1965
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1966
////  counter                                                     ////
1967
////                                                              ////
1968
////  To Do:                                                      ////
1969
////   - add LFSR with more taps                                  ////
1970
////                                                              ////
1971
////  Author(s):                                                  ////
1972
////      - Michael Unneback, unneback@opencores.org              ////
1973
////        ORSoC AB                                              ////
1974
////                                                              ////
1975
//////////////////////////////////////////////////////////////////////
1976
////                                                              ////
1977
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1978
////                                                              ////
1979
//// This source file may be used and distributed without         ////
1980
//// restriction provided that this copyright statement is not    ////
1981
//// removed from the file and that any derivative work contains  ////
1982
//// the original copyright notice and the associated disclaimer. ////
1983
////                                                              ////
1984
//// This source file is free software; you can redistribute it   ////
1985
//// and/or modify it under the terms of the GNU Lesser General   ////
1986
//// Public License as published by the Free Software Foundation; ////
1987
//// either version 2.1 of the License, or (at your option) any   ////
1988
//// later version.                                               ////
1989
////                                                              ////
1990
//// This source is distributed in the hope that it will be       ////
1991
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1992
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1993
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1994
//// details.                                                     ////
1995
////                                                              ////
1996
//// You should have received a copy of the GNU Lesser General    ////
1997
//// Public License along with this source; if not, download it   ////
1998
//// from http://www.opencores.org/lgpl.shtml                     ////
1999
////                                                              ////
2000
//////////////////////////////////////////////////////////////////////
2001
 
2002
// binary counter
2003
 
2004 40 unneback
`define MODULE cnt_bin_ce_rew_q_zq_l1
2005
module `BASE`MODULE (
2006
`undef MODULE
2007
 cke, rew, q, zq, level1, rst, clk);
2008
 
2009 25 unneback
   parameter length = 4;
2010
   input cke;
2011
   input rew;
2012
   output [length:1] q;
2013
   output reg zq;
2014
   output reg level1;
2015
   input rst;
2016
   input clk;
2017
 
2018
   parameter clear_value = 0;
2019
   parameter set_value = 1;
2020
   parameter wrap_value = 1;
2021
   parameter level1_value = 15;
2022
 
2023 29 unneback
   wire clear;
2024 30 unneback
   assign clear = 1'b0;
2025 25 unneback
   reg  [length:1] qi;
2026
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2027
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2028
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2029
   assign q_next = rew ? q_next_rew : q_next_fw;
2030
 
2031
   always @ (posedge clk or posedge rst)
2032
     if (rst)
2033
       qi <= {length{1'b0}};
2034
     else
2035
     if (cke)
2036
       qi <= q_next;
2037
 
2038
   assign q = qi;
2039
 
2040
 
2041
   always @ (posedge clk or posedge rst)
2042
     if (rst)
2043
       zq <= 1'b1;
2044
     else
2045
     if (cke)
2046
       zq <= q_next == {length{1'b0}};
2047
 
2048
    always @ (posedge clk or posedge rst)
2049
    if (rst)
2050
        level1 <= 1'b0;
2051
    else
2052
    if (cke)
2053 29 unneback
    if (clear)
2054
        level1 <= 1'b0;
2055
    else if (q_next == level1_value)
2056 25 unneback
        level1 <= 1'b1;
2057
    else if (qi == level1_value & rew)
2058
        level1 <= 1'b0;
2059
endmodule
2060 40 unneback
`endif
2061
`ifdef CNT_LFSR_ZQ
2062 25 unneback
//////////////////////////////////////////////////////////////////////
2063
////                                                              ////
2064
////  Versatile counter                                           ////
2065
////                                                              ////
2066
////  Description                                                 ////
2067
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2068
////  counter                                                     ////
2069
////                                                              ////
2070
////  To Do:                                                      ////
2071
////   - add LFSR with more taps                                  ////
2072
////                                                              ////
2073
////  Author(s):                                                  ////
2074
////      - Michael Unneback, unneback@opencores.org              ////
2075
////        ORSoC AB                                              ////
2076
////                                                              ////
2077
//////////////////////////////////////////////////////////////////////
2078
////                                                              ////
2079
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2080
////                                                              ////
2081
//// This source file may be used and distributed without         ////
2082
//// restriction provided that this copyright statement is not    ////
2083
//// removed from the file and that any derivative work contains  ////
2084
//// the original copyright notice and the associated disclaimer. ////
2085
////                                                              ////
2086
//// This source file is free software; you can redistribute it   ////
2087
//// and/or modify it under the terms of the GNU Lesser General   ////
2088
//// Public License as published by the Free Software Foundation; ////
2089
//// either version 2.1 of the License, or (at your option) any   ////
2090
//// later version.                                               ////
2091
////                                                              ////
2092
//// This source is distributed in the hope that it will be       ////
2093
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2094
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2095
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2096
//// details.                                                     ////
2097
////                                                              ////
2098
//// You should have received a copy of the GNU Lesser General    ////
2099
//// Public License along with this source; if not, download it   ////
2100
//// from http://www.opencores.org/lgpl.shtml                     ////
2101
////                                                              ////
2102
//////////////////////////////////////////////////////////////////////
2103
 
2104 6 unneback
// LFSR counter
2105
 
2106 40 unneback
`define MODULE cnt_lfsr_zq
2107
module `BASE`MODULE (
2108
`undef MODULE
2109
 zq, rst, clk);
2110
 
2111 6 unneback
   parameter length = 4;
2112
   output reg zq;
2113
   input rst;
2114
   input clk;
2115
 
2116
   parameter clear_value = 0;
2117
   parameter set_value = 1;
2118
   parameter wrap_value = 8;
2119
   parameter level1_value = 15;
2120
 
2121
   reg  [length:1] qi;
2122
   reg lfsr_fb;
2123
   wire [length:1] q_next;
2124
   reg [32:1] polynom;
2125
   integer i;
2126
 
2127
   always @ (qi)
2128
   begin
2129
        case (length)
2130
         2: polynom = 32'b11;                               // 0x3
2131
         3: polynom = 32'b110;                              // 0x6
2132
         4: polynom = 32'b1100;                             // 0xC
2133
         5: polynom = 32'b10100;                            // 0x14
2134
         6: polynom = 32'b110000;                           // 0x30
2135
         7: polynom = 32'b1100000;                          // 0x60
2136
         8: polynom = 32'b10111000;                         // 0xb8
2137
         9: polynom = 32'b100010000;                        // 0x110
2138
        10: polynom = 32'b1001000000;                       // 0x240
2139
        11: polynom = 32'b10100000000;                      // 0x500
2140
        12: polynom = 32'b100000101001;                     // 0x829
2141
        13: polynom = 32'b1000000001100;                    // 0x100C
2142
        14: polynom = 32'b10000000010101;                   // 0x2015
2143
        15: polynom = 32'b110000000000000;                  // 0x6000
2144
        16: polynom = 32'b1101000000001000;                 // 0xD008
2145
        17: polynom = 32'b10010000000000000;                // 0x12000
2146
        18: polynom = 32'b100000010000000000;               // 0x20400
2147
        19: polynom = 32'b1000000000000100011;              // 0x40023
2148 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2149 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2150
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2151
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2152
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2153
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2154
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2155
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2156
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2157
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2158
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2159
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2160
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2161
        default: polynom = 32'b0;
2162
        endcase
2163
        lfsr_fb = qi[length];
2164
        for (i=length-1; i>=1; i=i-1) begin
2165
            if (polynom[i])
2166
                lfsr_fb = lfsr_fb  ~^ qi[i];
2167
        end
2168
    end
2169
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2170
 
2171
   always @ (posedge clk or posedge rst)
2172
     if (rst)
2173
       qi <= {length{1'b0}};
2174
     else
2175
       qi <= q_next;
2176
 
2177
 
2178
 
2179
   always @ (posedge clk or posedge rst)
2180
     if (rst)
2181
       zq <= 1'b1;
2182
     else
2183
       zq <= q_next == {length{1'b0}};
2184
endmodule
2185 40 unneback
`endif
2186
`ifdef CNT_LFSR_CE_ZQ
2187 6 unneback
//////////////////////////////////////////////////////////////////////
2188
////                                                              ////
2189
////  Versatile counter                                           ////
2190
////                                                              ////
2191
////  Description                                                 ////
2192
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2193
////  counter                                                     ////
2194
////                                                              ////
2195
////  To Do:                                                      ////
2196
////   - add LFSR with more taps                                  ////
2197
////                                                              ////
2198
////  Author(s):                                                  ////
2199
////      - Michael Unneback, unneback@opencores.org              ////
2200
////        ORSoC AB                                              ////
2201
////                                                              ////
2202
//////////////////////////////////////////////////////////////////////
2203
////                                                              ////
2204
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2205
////                                                              ////
2206
//// This source file may be used and distributed without         ////
2207
//// restriction provided that this copyright statement is not    ////
2208
//// removed from the file and that any derivative work contains  ////
2209
//// the original copyright notice and the associated disclaimer. ////
2210
////                                                              ////
2211
//// This source file is free software; you can redistribute it   ////
2212
//// and/or modify it under the terms of the GNU Lesser General   ////
2213
//// Public License as published by the Free Software Foundation; ////
2214
//// either version 2.1 of the License, or (at your option) any   ////
2215
//// later version.                                               ////
2216
////                                                              ////
2217
//// This source is distributed in the hope that it will be       ////
2218
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2219
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2220
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2221
//// details.                                                     ////
2222
////                                                              ////
2223
//// You should have received a copy of the GNU Lesser General    ////
2224
//// Public License along with this source; if not, download it   ////
2225
//// from http://www.opencores.org/lgpl.shtml                     ////
2226
////                                                              ////
2227
//////////////////////////////////////////////////////////////////////
2228
 
2229
// LFSR counter
2230
 
2231 40 unneback
`define MODULE cnt_lfsr_ce_zq
2232
module `BASE`MODULE (
2233
`undef MODULE
2234
 cke, zq, rst, clk);
2235
 
2236 6 unneback
   parameter length = 4;
2237
   input cke;
2238
   output reg zq;
2239
   input rst;
2240
   input clk;
2241
 
2242
   parameter clear_value = 0;
2243
   parameter set_value = 1;
2244
   parameter wrap_value = 8;
2245
   parameter level1_value = 15;
2246
 
2247
   reg  [length:1] qi;
2248
   reg lfsr_fb;
2249
   wire [length:1] q_next;
2250
   reg [32:1] polynom;
2251
   integer i;
2252
 
2253
   always @ (qi)
2254
   begin
2255
        case (length)
2256
         2: polynom = 32'b11;                               // 0x3
2257
         3: polynom = 32'b110;                              // 0x6
2258
         4: polynom = 32'b1100;                             // 0xC
2259
         5: polynom = 32'b10100;                            // 0x14
2260
         6: polynom = 32'b110000;                           // 0x30
2261
         7: polynom = 32'b1100000;                          // 0x60
2262
         8: polynom = 32'b10111000;                         // 0xb8
2263
         9: polynom = 32'b100010000;                        // 0x110
2264
        10: polynom = 32'b1001000000;                       // 0x240
2265
        11: polynom = 32'b10100000000;                      // 0x500
2266
        12: polynom = 32'b100000101001;                     // 0x829
2267
        13: polynom = 32'b1000000001100;                    // 0x100C
2268
        14: polynom = 32'b10000000010101;                   // 0x2015
2269
        15: polynom = 32'b110000000000000;                  // 0x6000
2270
        16: polynom = 32'b1101000000001000;                 // 0xD008
2271
        17: polynom = 32'b10010000000000000;                // 0x12000
2272
        18: polynom = 32'b100000010000000000;               // 0x20400
2273
        19: polynom = 32'b1000000000000100011;              // 0x40023
2274 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2275 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2276
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2277
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2278
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2279
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2280
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2281
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2282
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2283
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2284
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2285
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2286
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2287
        default: polynom = 32'b0;
2288
        endcase
2289
        lfsr_fb = qi[length];
2290
        for (i=length-1; i>=1; i=i-1) begin
2291
            if (polynom[i])
2292
                lfsr_fb = lfsr_fb  ~^ qi[i];
2293
        end
2294
    end
2295
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2296
 
2297
   always @ (posedge clk or posedge rst)
2298
     if (rst)
2299
       qi <= {length{1'b0}};
2300
     else
2301
     if (cke)
2302
       qi <= q_next;
2303
 
2304
 
2305
 
2306
   always @ (posedge clk or posedge rst)
2307
     if (rst)
2308
       zq <= 1'b1;
2309
     else
2310
     if (cke)
2311
       zq <= q_next == {length{1'b0}};
2312
endmodule
2313 40 unneback
`endif
2314
`ifdef CNT_LFSR_CE_Q
2315 6 unneback
//////////////////////////////////////////////////////////////////////
2316
////                                                              ////
2317
////  Versatile counter                                           ////
2318
////                                                              ////
2319
////  Description                                                 ////
2320
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2321
////  counter                                                     ////
2322
////                                                              ////
2323
////  To Do:                                                      ////
2324
////   - add LFSR with more taps                                  ////
2325
////                                                              ////
2326
////  Author(s):                                                  ////
2327
////      - Michael Unneback, unneback@opencores.org              ////
2328
////        ORSoC AB                                              ////
2329
////                                                              ////
2330
//////////////////////////////////////////////////////////////////////
2331
////                                                              ////
2332
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2333
////                                                              ////
2334
//// This source file may be used and distributed without         ////
2335
//// restriction provided that this copyright statement is not    ////
2336
//// removed from the file and that any derivative work contains  ////
2337
//// the original copyright notice and the associated disclaimer. ////
2338
////                                                              ////
2339
//// This source file is free software; you can redistribute it   ////
2340
//// and/or modify it under the terms of the GNU Lesser General   ////
2341
//// Public License as published by the Free Software Foundation; ////
2342
//// either version 2.1 of the License, or (at your option) any   ////
2343
//// later version.                                               ////
2344
////                                                              ////
2345
//// This source is distributed in the hope that it will be       ////
2346
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2347
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2348
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2349
//// details.                                                     ////
2350
////                                                              ////
2351
//// You should have received a copy of the GNU Lesser General    ////
2352
//// Public License along with this source; if not, download it   ////
2353
//// from http://www.opencores.org/lgpl.shtml                     ////
2354
////                                                              ////
2355
//////////////////////////////////////////////////////////////////////
2356 22 unneback
 
2357
// LFSR counter
2358 27 unneback
 
2359 40 unneback
`define MODULE cnt_lfsr_ce_q
2360
module `BASE`MODULE (
2361
`undef MODULE
2362
 cke, q, rst, clk);
2363
 
2364 27 unneback
   parameter length = 4;
2365
   input cke;
2366
   output [length:1] q;
2367
   input rst;
2368
   input clk;
2369
 
2370
   parameter clear_value = 0;
2371
   parameter set_value = 1;
2372
   parameter wrap_value = 8;
2373
   parameter level1_value = 15;
2374
 
2375
   reg  [length:1] qi;
2376
   reg lfsr_fb;
2377
   wire [length:1] q_next;
2378
   reg [32:1] polynom;
2379
   integer i;
2380
 
2381
   always @ (qi)
2382
   begin
2383
        case (length)
2384
         2: polynom = 32'b11;                               // 0x3
2385
         3: polynom = 32'b110;                              // 0x6
2386
         4: polynom = 32'b1100;                             // 0xC
2387
         5: polynom = 32'b10100;                            // 0x14
2388
         6: polynom = 32'b110000;                           // 0x30
2389
         7: polynom = 32'b1100000;                          // 0x60
2390
         8: polynom = 32'b10111000;                         // 0xb8
2391
         9: polynom = 32'b100010000;                        // 0x110
2392
        10: polynom = 32'b1001000000;                       // 0x240
2393
        11: polynom = 32'b10100000000;                      // 0x500
2394
        12: polynom = 32'b100000101001;                     // 0x829
2395
        13: polynom = 32'b1000000001100;                    // 0x100C
2396
        14: polynom = 32'b10000000010101;                   // 0x2015
2397
        15: polynom = 32'b110000000000000;                  // 0x6000
2398
        16: polynom = 32'b1101000000001000;                 // 0xD008
2399
        17: polynom = 32'b10010000000000000;                // 0x12000
2400
        18: polynom = 32'b100000010000000000;               // 0x20400
2401
        19: polynom = 32'b1000000000000100011;              // 0x40023
2402 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2403 27 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2404
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2405
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2406
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2407
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2408
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2409
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2410
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2411
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2412
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2413
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2414
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2415
        default: polynom = 32'b0;
2416
        endcase
2417
        lfsr_fb = qi[length];
2418
        for (i=length-1; i>=1; i=i-1) begin
2419
            if (polynom[i])
2420
                lfsr_fb = lfsr_fb  ~^ qi[i];
2421
        end
2422
    end
2423
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2424
 
2425
   always @ (posedge clk or posedge rst)
2426
     if (rst)
2427
       qi <= {length{1'b0}};
2428
     else
2429
     if (cke)
2430
       qi <= q_next;
2431
 
2432
   assign q = qi;
2433
 
2434
endmodule
2435 40 unneback
`endif
2436
`ifdef CNT_LFSR_CE_CLEAR_Q
2437 27 unneback
//////////////////////////////////////////////////////////////////////
2438
////                                                              ////
2439
////  Versatile counter                                           ////
2440
////                                                              ////
2441
////  Description                                                 ////
2442
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2443
////  counter                                                     ////
2444
////                                                              ////
2445
////  To Do:                                                      ////
2446
////   - add LFSR with more taps                                  ////
2447
////                                                              ////
2448
////  Author(s):                                                  ////
2449
////      - Michael Unneback, unneback@opencores.org              ////
2450
////        ORSoC AB                                              ////
2451
////                                                              ////
2452
//////////////////////////////////////////////////////////////////////
2453
////                                                              ////
2454
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2455
////                                                              ////
2456
//// This source file may be used and distributed without         ////
2457
//// restriction provided that this copyright statement is not    ////
2458
//// removed from the file and that any derivative work contains  ////
2459
//// the original copyright notice and the associated disclaimer. ////
2460
////                                                              ////
2461
//// This source file is free software; you can redistribute it   ////
2462
//// and/or modify it under the terms of the GNU Lesser General   ////
2463
//// Public License as published by the Free Software Foundation; ////
2464
//// either version 2.1 of the License, or (at your option) any   ////
2465
//// later version.                                               ////
2466
////                                                              ////
2467
//// This source is distributed in the hope that it will be       ////
2468
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2469
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2470
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2471
//// details.                                                     ////
2472
////                                                              ////
2473
//// You should have received a copy of the GNU Lesser General    ////
2474
//// Public License along with this source; if not, download it   ////
2475
//// from http://www.opencores.org/lgpl.shtml                     ////
2476
////                                                              ////
2477
//////////////////////////////////////////////////////////////////////
2478
 
2479
// LFSR counter
2480
 
2481 40 unneback
`define MODULE cnt_lfsr_ce_clear_q
2482
module `BASE`MODULE (
2483
`undef MODULE
2484
 clear, cke, q, rst, clk);
2485
 
2486 27 unneback
   parameter length = 4;
2487
   input clear;
2488
   input cke;
2489
   output [length:1] q;
2490
   input rst;
2491
   input clk;
2492
 
2493
   parameter clear_value = 0;
2494
   parameter set_value = 1;
2495
   parameter wrap_value = 8;
2496
   parameter level1_value = 15;
2497
 
2498
   reg  [length:1] qi;
2499
   reg lfsr_fb;
2500
   wire [length:1] q_next;
2501
   reg [32:1] polynom;
2502
   integer i;
2503
 
2504
   always @ (qi)
2505
   begin
2506
        case (length)
2507
         2: polynom = 32'b11;                               // 0x3
2508
         3: polynom = 32'b110;                              // 0x6
2509
         4: polynom = 32'b1100;                             // 0xC
2510
         5: polynom = 32'b10100;                            // 0x14
2511
         6: polynom = 32'b110000;                           // 0x30
2512
         7: polynom = 32'b1100000;                          // 0x60
2513
         8: polynom = 32'b10111000;                         // 0xb8
2514
         9: polynom = 32'b100010000;                        // 0x110
2515
        10: polynom = 32'b1001000000;                       // 0x240
2516
        11: polynom = 32'b10100000000;                      // 0x500
2517
        12: polynom = 32'b100000101001;                     // 0x829
2518
        13: polynom = 32'b1000000001100;                    // 0x100C
2519
        14: polynom = 32'b10000000010101;                   // 0x2015
2520
        15: polynom = 32'b110000000000000;                  // 0x6000
2521
        16: polynom = 32'b1101000000001000;                 // 0xD008
2522
        17: polynom = 32'b10010000000000000;                // 0x12000
2523
        18: polynom = 32'b100000010000000000;               // 0x20400
2524
        19: polynom = 32'b1000000000000100011;              // 0x40023
2525 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2526 27 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2527
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2528
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2529
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2530
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2531
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2532
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2533
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2534
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2535
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2536
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2537
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2538
        default: polynom = 32'b0;
2539
        endcase
2540
        lfsr_fb = qi[length];
2541
        for (i=length-1; i>=1; i=i-1) begin
2542
            if (polynom[i])
2543
                lfsr_fb = lfsr_fb  ~^ qi[i];
2544
        end
2545
    end
2546
   assign q_next =  clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2547
 
2548
   always @ (posedge clk or posedge rst)
2549
     if (rst)
2550
       qi <= {length{1'b0}};
2551
     else
2552
     if (cke)
2553
       qi <= q_next;
2554
 
2555
   assign q = qi;
2556
 
2557
endmodule
2558 40 unneback
`endif
2559
`ifdef CNT_LFSR_CE_Q_ZQ
2560 27 unneback
//////////////////////////////////////////////////////////////////////
2561
////                                                              ////
2562
////  Versatile counter                                           ////
2563
////                                                              ////
2564
////  Description                                                 ////
2565
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2566
////  counter                                                     ////
2567
////                                                              ////
2568
////  To Do:                                                      ////
2569
////   - add LFSR with more taps                                  ////
2570
////                                                              ////
2571
////  Author(s):                                                  ////
2572
////      - Michael Unneback, unneback@opencores.org              ////
2573
////        ORSoC AB                                              ////
2574
////                                                              ////
2575
//////////////////////////////////////////////////////////////////////
2576
////                                                              ////
2577
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2578
////                                                              ////
2579
//// This source file may be used and distributed without         ////
2580
//// restriction provided that this copyright statement is not    ////
2581
//// removed from the file and that any derivative work contains  ////
2582
//// the original copyright notice and the associated disclaimer. ////
2583
////                                                              ////
2584
//// This source file is free software; you can redistribute it   ////
2585
//// and/or modify it under the terms of the GNU Lesser General   ////
2586
//// Public License as published by the Free Software Foundation; ////
2587
//// either version 2.1 of the License, or (at your option) any   ////
2588
//// later version.                                               ////
2589
////                                                              ////
2590
//// This source is distributed in the hope that it will be       ////
2591
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2592
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2593
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2594
//// details.                                                     ////
2595
////                                                              ////
2596
//// You should have received a copy of the GNU Lesser General    ////
2597
//// Public License along with this source; if not, download it   ////
2598
//// from http://www.opencores.org/lgpl.shtml                     ////
2599
////                                                              ////
2600
//////////////////////////////////////////////////////////////////////
2601
 
2602
// LFSR counter
2603 22 unneback
 
2604 40 unneback
`define MODULE cnt_lfsr_ce_q_zq
2605
module `BASE`MODULE (
2606
`undef MODULE
2607
 cke, q, zq, rst, clk);
2608
 
2609 22 unneback
   parameter length = 4;
2610
   input cke;
2611
   output [length:1] q;
2612
   output reg zq;
2613
   input rst;
2614
   input clk;
2615
 
2616
   parameter clear_value = 0;
2617
   parameter set_value = 1;
2618
   parameter wrap_value = 8;
2619
   parameter level1_value = 15;
2620
 
2621
   reg  [length:1] qi;
2622
   reg lfsr_fb;
2623
   wire [length:1] q_next;
2624
   reg [32:1] polynom;
2625
   integer i;
2626
 
2627
   always @ (qi)
2628
   begin
2629
        case (length)
2630
         2: polynom = 32'b11;                               // 0x3
2631
         3: polynom = 32'b110;                              // 0x6
2632
         4: polynom = 32'b1100;                             // 0xC
2633
         5: polynom = 32'b10100;                            // 0x14
2634
         6: polynom = 32'b110000;                           // 0x30
2635
         7: polynom = 32'b1100000;                          // 0x60
2636
         8: polynom = 32'b10111000;                         // 0xb8
2637
         9: polynom = 32'b100010000;                        // 0x110
2638
        10: polynom = 32'b1001000000;                       // 0x240
2639
        11: polynom = 32'b10100000000;                      // 0x500
2640
        12: polynom = 32'b100000101001;                     // 0x829
2641
        13: polynom = 32'b1000000001100;                    // 0x100C
2642
        14: polynom = 32'b10000000010101;                   // 0x2015
2643
        15: polynom = 32'b110000000000000;                  // 0x6000
2644
        16: polynom = 32'b1101000000001000;                 // 0xD008
2645
        17: polynom = 32'b10010000000000000;                // 0x12000
2646
        18: polynom = 32'b100000010000000000;               // 0x20400
2647
        19: polynom = 32'b1000000000000100011;              // 0x40023
2648 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2649 22 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2650
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2651
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2652
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2653
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2654
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2655
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2656
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2657
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2658
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2659
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2660
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2661
        default: polynom = 32'b0;
2662
        endcase
2663
        lfsr_fb = qi[length];
2664
        for (i=length-1; i>=1; i=i-1) begin
2665
            if (polynom[i])
2666
                lfsr_fb = lfsr_fb  ~^ qi[i];
2667
        end
2668
    end
2669
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2670
 
2671
   always @ (posedge clk or posedge rst)
2672
     if (rst)
2673
       qi <= {length{1'b0}};
2674
     else
2675
     if (cke)
2676
       qi <= q_next;
2677
 
2678
   assign q = qi;
2679
 
2680
 
2681
   always @ (posedge clk or posedge rst)
2682
     if (rst)
2683
       zq <= 1'b1;
2684
     else
2685
     if (cke)
2686
       zq <= q_next == {length{1'b0}};
2687
endmodule
2688 40 unneback
`endif
2689
`ifdef CNT_LFSR_CE_REW_L1
2690 22 unneback
//////////////////////////////////////////////////////////////////////
2691
////                                                              ////
2692
////  Versatile counter                                           ////
2693
////                                                              ////
2694
////  Description                                                 ////
2695
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2696
////  counter                                                     ////
2697
////                                                              ////
2698
////  To Do:                                                      ////
2699
////   - add LFSR with more taps                                  ////
2700
////                                                              ////
2701
////  Author(s):                                                  ////
2702
////      - Michael Unneback, unneback@opencores.org              ////
2703
////        ORSoC AB                                              ////
2704
////                                                              ////
2705
//////////////////////////////////////////////////////////////////////
2706
////                                                              ////
2707
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2708
////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
2731 6 unneback
 
2732
// LFSR counter
2733
 
2734 40 unneback
`define MODULE cnt_lfsr_ce_rew_l1
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module `BASE`MODULE (
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`undef MODULE
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 cke, rew, level1, rst, clk);
2738
 
2739 6 unneback
   parameter length = 4;
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   input cke;
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   input rew;
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   output reg level1;
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   input rst;
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   input clk;
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2746
   parameter clear_value = 0;
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   parameter set_value = 1;
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   parameter wrap_value = 8;
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   parameter level1_value = 15;
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2751 29 unneback
   wire clear;
2752 30 unneback
   assign clear = 1'b0;
2753 6 unneback
   reg  [length:1] qi;
2754
   reg lfsr_fb, lfsr_fb_rew;
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   wire  [length:1] q_next, q_next_fw, q_next_rew;
2756
   reg [32:1] polynom_rew;
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   integer j;
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   reg [32:1] polynom;
2759
   integer i;
2760
 
2761
   always @ (qi)
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   begin
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        case (length)
2764
         2: polynom = 32'b11;                               // 0x3
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         3: polynom = 32'b110;                              // 0x6
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         4: polynom = 32'b1100;                             // 0xC
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         5: polynom = 32'b10100;                            // 0x14
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         6: polynom = 32'b110000;                           // 0x30
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         7: polynom = 32'b1100000;                          // 0x60
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         8: polynom = 32'b10111000;                         // 0xb8
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         9: polynom = 32'b100010000;                        // 0x110
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        10: polynom = 32'b1001000000;                       // 0x240
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        11: polynom = 32'b10100000000;                      // 0x500
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        12: polynom = 32'b100000101001;                     // 0x829
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        13: polynom = 32'b1000000001100;                    // 0x100C
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        14: polynom = 32'b10000000010101;                   // 0x2015
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        15: polynom = 32'b110000000000000;                  // 0x6000
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        16: polynom = 32'b1101000000001000;                 // 0xD008
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        17: polynom = 32'b10010000000000000;                // 0x12000
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        18: polynom = 32'b100000010000000000;               // 0x20400
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        19: polynom = 32'b1000000000000100011;              // 0x40023
2782 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2783 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
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        22: polynom = 32'b1100000000000000000000;           // 0x300000
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        23: polynom = 32'b10000100000000000000000;          // 0x420000
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        24: polynom = 32'b111000010000000000000000;         // 0xE10000
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        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
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        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
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        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
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        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
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        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
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        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
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        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
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        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
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        default: polynom = 32'b0;
2796
        endcase
2797
        lfsr_fb = qi[length];
2798
        for (i=length-1; i>=1; i=i-1) begin
2799
            if (polynom[i])
2800
                lfsr_fb = lfsr_fb  ~^ qi[i];
2801
        end
2802
    end
2803
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
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   always @ (qi)
2805
   begin
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        case (length)
2807
         2: polynom_rew = 32'b11;
2808
         3