OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Blame information for rev 42

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 40 unneback
`ifndef BASE
2
`define BASE vl_
3
`endif
4
 
5
`ifdef ALL
6
 
7
`define GBUF
8
`define SYNC_RST
9
`define PLL
10
 
11
`define MULTS
12
`define MULTS18X18
13
`define MULT
14
`define SHIFT_UNIT_32
15
`define LOGIC_UNIT
16
 
17
`define CNT_SHREG_WRAP
18
`define CNT_SHREG_CE_WRAP
19
`define CNT_SHREG_CE_CLEAR
20
`define CNT_SHREG_CE_CLEAR_WRAP
21
 
22
`define MUX_ANDOR
23
`define MUX2_ANDOR
24
`define MUX3_ANDOR
25
`define MUX4_ANDOR
26
`define MUX5_ANDOR
27
`define MUX6_ANDOR
28
 
29
`define ROM_INIT
30
`define RAM
31
`define RAM_BE
32
`define DPRAM_1R1W
33
`define DPRAM_2R1W
34
`define DPRAM_2R2W
35
`define FIFO_1R1W_FILL_LEVEL_SYNC
36
`define FIFO_2R2W_SYNC_SIMPLEX
37
`define FIFO_CMP_ASYNC
38
`define FIFO_1R1W_ASYNC
39
`define FIFO_2R2W_ASYNC
40
`define FIFO_2R2W_ASYNC_SIMPLEX
41
 
42
`define DFF
43
`define DFF_ARRAY
44
`define DFF_CE
45
`define DFF_CE_CLEAR
46
`define DF_CE_SET
47
`define SPR
48
`define SRP
49
`define DFF_SR
50
`define LATCH
51
`define SHREG
52
`define SHREG_CE
53
`define DELAY
54
`define DELAY_EMPTYFLAG
55
 
56
`define WB3WB3_BRIDGE
57
`define WB3_ARBITER_TYPE1
58
`define WB_BOOT_ROM
59
`define WB_DPRAM
60
 
61
`endif
62
 
63
`ifdef PLL
64
`ifndef SYNC_RST
65
`define SYNC_RST
66
`endif
67
`endif
68
 
69
`ifdef SYNC_RST
70
`ifndef GBUF
71
`define GBUF
72
`endif
73
`endif
74
 
75
`ifdef WB_DPRAM
76
`ifndef DPRAM_2R2W
77
`define DPRAM_2R2W
78
`endif
79
`ifndef SPR
80
`define SPR
81
`endif
82
`endif
83
 
84
`ifdef WB3_ARBITER_TYPE1
85 42 unneback
`ifndef SPR
86
`define SPR
87
`endif
88 40 unneback
`ifndef MUX_ANDOR
89
`define MUX_ANDOR
90
`endif
91
`endif
92
 
93
`ifdef WB3WB3_BRIDGE
94
`ifndef CNT_SHREG_CE_CLEAR
95
`define CNT_SHREG_CE_CLEAR
96
`endif
97
`ifndef DFF
98
`define DFF
99
`endif
100
`ifndef DFF_CE
101
`define DFF_CE
102
`endif
103
`ifndef CNT_SHREG_CE_CLEAR
104
`define CNT_SHREG_CE_CLEAR
105
`endif
106
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
107
`define FIFO_2R2W_ASYNC_SIMPLEX
108
`endif
109
`endif
110
 
111
`ifdef MULTS18X18
112
`ifndef MULTS
113
`define MULTS
114
`endif
115
`endif
116
 
117
`ifdef SHIFT_UNIT_32
118
`ifndef MULTS
119
`define MULTS
120
`endif
121
`endif
122
 
123
`ifdef MUX2_ANDOR
124
`ifndef MUX_ANDOR
125
`define MUX_ANDOR
126
`endif
127
`endif
128
 
129
`ifdef MUX3_ANDOR
130
`ifndef MUX_ANDOR
131
`define MUX_ANDOR
132
`endif
133
`endif
134
 
135
`ifdef MUX4_ANDOR
136
`ifndef MUX_ANDOR
137
`define MUX_ANDOR
138
`endif
139
`endif
140
 
141
`ifdef MUX5_ANDOR
142
`ifndef MUX_ANDOR
143
`define MUX_ANDOR
144
`endif
145
`endif
146
 
147
`ifdef MUX6_ANDOR
148
`ifndef MUX_ANDOR
149
`define MUX_ANDOR
150
`endif
151
`endif
152
 
153
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
154
`ifndef CNT_BIN_CE
155
`define CNT_BIN_CE
156
`endif
157
`ifndef DPRAM_1R1W
158
`define DPRAM_1R1W
159
`endif
160
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
161
`define CNT_BIN_CE_REW_Q_ZQ_L1
162
`endif
163
`endif
164
 
165
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
166
`ifndef CNT_LFSR_CE
167
`define CNT_LFSR_CE
168
`endif
169
`ifndef DPRAM_2R2W
170
`define DPRAM_2R2W
171
`endif
172
`ifndef CNT_BIN_CE_REW_ZQ_L1
173
`define CNT_BIN_CE_REW_ZQ_L1
174
`endif
175
`endif
176
 
177
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
178
`ifndef CNT_GRAY_CE_BIN
179
`define CNT_GRAY_CE_BIN
180
`endif
181
`ifndef DPRAM_2R2W
182
`define DPRAM_2R2W
183
`endif
184
`ifndef FIFO_CMP_ASYNC
185
`define FIFO_CMP_ASYNC
186
`endif
187
`endif
188
 
189
`ifdef FIFO_2R2W_ASYNC
190
`ifndef FIFO_1R1W_ASYNC
191
`define FIFO_1R1W_ASYNC
192
`endif
193
`endif
194
 
195
`ifdef FIFO_1R1W_ASYNC
196
`ifndef CNT_GRAY_CE_BIN
197
`define CNT_GRAY_CE_BIN
198
`endif
199
`ifndef DPRAM_1R1W
200
`define DPRAM_1R1W
201
`endif
202
`ifndef FIFO_CMP_ASYNC
203
`define FIFO_CMP_ASYNC
204
`endif
205
`endif
206
 
207
`ifdef FIFO_CMP_ASYNC
208
`ifndef DFF_SR
209
`define DFF_SR
210
`endif
211
`ifndef DFF
212
`define DFF
213
`endif
214
`endif
215 6 unneback
//////////////////////////////////////////////////////////////////////
216
////                                                              ////
217
////  Versatile library, clock and reset                          ////
218
////                                                              ////
219
////  Description                                                 ////
220
////  Logic related to clock and reset                            ////
221
////                                                              ////
222
////                                                              ////
223
////  To Do:                                                      ////
224
////   - add more different registers                             ////
225
////                                                              ////
226
////  Author(s):                                                  ////
227
////      - Michael Unneback, unneback@opencores.org              ////
228
////        ORSoC AB                                              ////
229
////                                                              ////
230
//////////////////////////////////////////////////////////////////////
231
////                                                              ////
232
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
233
////                                                              ////
234
//// This source file may be used and distributed without         ////
235
//// restriction provided that this copyright statement is not    ////
236
//// removed from the file and that any derivative work contains  ////
237
//// the original copyright notice and the associated disclaimer. ////
238
////                                                              ////
239
//// This source file is free software; you can redistribute it   ////
240
//// and/or modify it under the terms of the GNU Lesser General   ////
241
//// Public License as published by the Free Software Foundation; ////
242
//// either version 2.1 of the License, or (at your option) any   ////
243
//// later version.                                               ////
244
////                                                              ////
245
//// This source is distributed in the hope that it will be       ////
246
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
247
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
248
//// PURPOSE.  See the GNU Lesser General Public License for more ////
249
//// details.                                                     ////
250
////                                                              ////
251
//// You should have received a copy of the GNU Lesser General    ////
252
//// Public License along with this source; if not, download it   ////
253
//// from http://www.opencores.org/lgpl.shtml                     ////
254
////                                                              ////
255
//////////////////////////////////////////////////////////////////////
256
 
257
// Global buffer
258
// usage:
259
// use to enable global buffers for high fan out signals such as clock and reset
260
 
261
`ifdef ACTEL
262 40 unneback
`ifdef GBUF
263 6 unneback
`timescale 1 ns/100 ps
264
// Version: 8.4 8.4.0.33
265
module gbuf(GL,CLK);
266
output GL;
267
input  CLK;
268
 
269
    wire GND;
270
 
271
    GND GND_1_net(.Y(GND));
272
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
273
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
274
 
275
endmodule
276
`timescale 1 ns/1 ns
277 40 unneback
`define MODULE gbuf
278
module `BASE`MODULE ( i, o);
279
`undef MODULE
280 6 unneback
input i;
281
output o;
282
`ifdef SIM_GBUF
283
assign o=i;
284
`else
285
gbuf gbuf_i0 ( .CLK(i), .GL(o));
286
`endif
287
endmodule
288 40 unneback
`endif
289 33 unneback
 
290 6 unneback
`else
291 33 unneback
 
292 40 unneback
`ifdef ALTERA
293
`ifdef GBUF
294 21 unneback
//altera
295 40 unneback
`define MODULE gbuf
296
module `BASE`MODULE ( i, o);
297
`undef MODULE
298 33 unneback
input i;
299
output o;
300
assign o = i;
301
endmodule
302 40 unneback
`endif
303 33 unneback
 
304 6 unneback
`else
305
 
306 40 unneback
`ifdef GBUF
307 6 unneback
`timescale 1 ns/100 ps
308 40 unneback
`define MODULE
309
module `BASE`MODULE ( i, o);
310
`undef MODULE
311 6 unneback
input i;
312
output o;
313
assign o = i;
314
endmodule
315 40 unneback
`endif
316 6 unneback
`endif // ALTERA
317
`endif //ACTEL
318
 
319 40 unneback
`ifdef SYNC_RST
320 6 unneback
// sync reset
321 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
322 6 unneback
// output active high global reset sync with two DFFs 
323
`timescale 1 ns/100 ps
324 40 unneback
`define MODULE sync_rst
325
module `BASE`MODULE ( rst_n_i, rst_o, clk);
326
`undef MODULE
327 6 unneback
input rst_n_i, clk;
328
output rst_o;
329 18 unneback
reg [1:0] tmp;
330 6 unneback
always @ (posedge clk or negedge rst_n_i)
331
if (!rst_n_i)
332 17 unneback
        tmp <= 2'b11;
333 6 unneback
else
334 33 unneback
        tmp <= {1'b0,tmp[1]};
335 40 unneback
`define MODULE gbuf
336
`BASE`MODULE buf_i0( .i(tmp[0]), .o(rst_o));
337
`undef MODULE
338 6 unneback
endmodule
339 40 unneback
`endif
340 6 unneback
 
341 40 unneback
`ifdef PLL
342 6 unneback
// vl_pll
343
`ifdef ACTEL
344 32 unneback
///////////////////////////////////////////////////////////////////////////////
345 17 unneback
`timescale 1 ps/1 ps
346 40 unneback
`define MODULE pll
347
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
348
`undef MODULE
349 6 unneback
parameter index = 0;
350
parameter number_of_clk = 1;
351 17 unneback
parameter period_time_0 = 20000;
352
parameter period_time_1 = 20000;
353
parameter period_time_2 = 20000;
354
parameter lock_delay = 2000000;
355 6 unneback
input clk_i, rst_n_i;
356
output lock;
357
output reg [0:number_of_clk-1] clk_o;
358
output [0:number_of_clk-1] rst_o;
359
 
360
`ifdef SIM_PLL
361
 
362
always
363
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
364
 
365
generate if (number_of_clk > 1)
366
always
367
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
368
endgenerate
369
 
370
generate if (number_of_clk > 2)
371
always
372
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
373
endgenerate
374
 
375
genvar i;
376
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
377
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
378
end
379
endgenerate
380
 
381
assign #lock_delay lock = rst_n_i;
382
 
383
endmodule
384
`else
385
generate if (number_of_clk==1 & index==0) begin
386
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
387
end
388
endgenerate // index==0
389
generate if (number_of_clk==1 & index==1) begin
390
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
391
end
392
endgenerate // index==1
393
generate if (number_of_clk==1 & index==2) begin
394
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
395
end
396
endgenerate // index==2
397
generate if (number_of_clk==1 & index==3) begin
398
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
399
end
400
endgenerate // index==0
401
 
402
generate if (number_of_clk==2 & index==0) begin
403
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
404
end
405
endgenerate // index==0
406
generate if (number_of_clk==2 & index==1) begin
407
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
408
end
409
endgenerate // index==1
410
generate if (number_of_clk==2 & index==2) begin
411
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
412
end
413
endgenerate // index==2
414
generate if (number_of_clk==2 & index==3) begin
415
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
416
end
417
endgenerate // index==0
418
 
419
generate if (number_of_clk==3 & index==0) begin
420
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
421
end
422
endgenerate // index==0
423
generate if (number_of_clk==3 & index==1) begin
424
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
425
end
426
endgenerate // index==1
427
generate if (number_of_clk==3 & index==2) begin
428
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
429
end
430
endgenerate // index==2
431
generate if (number_of_clk==3 & index==3) begin
432
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
433
end
434
endgenerate // index==0
435
 
436
genvar i;
437
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
438 40 unneback
`define MODULE sync_rst
439
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
440
`undef MODULE
441 6 unneback
end
442
endgenerate
443
endmodule
444
`endif
445 32 unneback
///////////////////////////////////////////////////////////////////////////////
446 6 unneback
 
447
`else
448
 
449 32 unneback
///////////////////////////////////////////////////////////////////////////////
450 6 unneback
`ifdef ALTERA
451
 
452 32 unneback
`timescale 1 ps/1 ps
453 40 unneback
`define MODULE pll
454
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
455
`undef MODULE
456 32 unneback
parameter index = 0;
457
parameter number_of_clk = 1;
458
parameter period_time_0 = 20000;
459
parameter period_time_1 = 20000;
460
parameter period_time_2 = 20000;
461
parameter period_time_3 = 20000;
462
parameter period_time_4 = 20000;
463
parameter lock_delay = 2000000;
464
input clk_i, rst_n_i;
465
output lock;
466
output reg [0:number_of_clk-1] clk_o;
467
output [0:number_of_clk-1] rst_o;
468
 
469
`ifdef SIM_PLL
470
 
471
always
472
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
473
 
474
generate if (number_of_clk > 1)
475
always
476
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
477
endgenerate
478
 
479
generate if (number_of_clk > 2)
480
always
481
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
482
endgenerate
483
 
484 33 unneback
generate if (number_of_clk > 3)
485 32 unneback
always
486
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
487
endgenerate
488
 
489 33 unneback
generate if (number_of_clk > 4)
490 32 unneback
always
491
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
492
endgenerate
493
 
494
genvar i;
495
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
496
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
497
end
498
endgenerate
499
 
500 33 unneback
//assign #lock_delay lock = rst_n_i;
501
assign lock = rst_n_i;
502 32 unneback
 
503
endmodule
504 6 unneback
`else
505
 
506 33 unneback
`ifdef VL_PLL0
507
`ifdef VL_PLL0_CLK1
508
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
509
`endif
510
`ifdef VL_PLL0_CLK2
511
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
512
`endif
513
`ifdef VL_PLL0_CLK3
514
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
515
`endif
516
`ifdef VL_PLL0_CLK4
517
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
518
`endif
519
`ifdef VL_PLL0_CLK5
520
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
521
`endif
522
`endif
523 32 unneback
 
524 33 unneback
`ifdef VL_PLL1
525
`ifdef VL_PLL1_CLK1
526
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
527
`endif
528
`ifdef VL_PLL1_CLK2
529
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
530
`endif
531
`ifdef VL_PLL1_CLK3
532
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
533
`endif
534
`ifdef VL_PLL1_CLK4
535
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
536
`endif
537
`ifdef VL_PLL1_CLK5
538
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
539
`endif
540
`endif
541 32 unneback
 
542 33 unneback
`ifdef VL_PLL2
543
`ifdef VL_PLL2_CLK1
544
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
545
`endif
546
`ifdef VL_PLL2_CLK2
547
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
548
`endif
549
`ifdef VL_PLL2_CLK3
550
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
551
`endif
552
`ifdef VL_PLL2_CLK4
553
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
554
`endif
555
`ifdef VL_PLL2_CLK5
556
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
557
`endif
558
`endif
559 32 unneback
 
560 33 unneback
`ifdef VL_PLL3
561
`ifdef VL_PLL3_CLK1
562
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
563
`endif
564
`ifdef VL_PLL3_CLK2
565
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
566
`endif
567
`ifdef VL_PLL3_CLK3
568
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
569
`endif
570
`ifdef VL_PLL3_CLK4
571
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
572
`endif
573
`ifdef VL_PLL3_CLK5
574
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
575
`endif
576
`endif
577 32 unneback
 
578
genvar i;
579
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
580 40 unneback
`define MODULE sync_rst
581
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
582
`undef MODULE
583 32 unneback
end
584
endgenerate
585
endmodule
586
`endif
587
///////////////////////////////////////////////////////////////////////////////
588
 
589
`else
590
 
591 6 unneback
// generic PLL
592 17 unneback
`timescale 1 ps/1 ps
593 40 unneback
`define MODULE pll
594
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
595
`undef MODULE
596 6 unneback
parameter index = 0;
597
parameter number_of_clk = 1;
598 17 unneback
parameter period_time_0 = 20000;
599
parameter period_time_1 = 20000;
600
parameter period_time_2 = 20000;
601 6 unneback
parameter lock_delay = 2000;
602
input clk_i, rst_n_i;
603
output lock;
604
output reg [0:number_of_clk-1] clk_o;
605
output [0:number_of_clk-1] rst_o;
606
 
607
always
608
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
609
 
610
generate if (number_of_clk > 1)
611
always
612
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
613
endgenerate
614
 
615
generate if (number_of_clk > 2)
616
always
617
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
618
endgenerate
619
 
620
genvar i;
621
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
622 40 unneback
`define MODULE sync_rst
623
     `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
624
`undef MODULE
625 6 unneback
end
626
endgenerate
627
 
628
assign #lock_delay lock = rst_n_i;
629
 
630
endmodule
631
 
632
`endif //altera
633 17 unneback
`endif //actel
634 40 unneback
`undef MODULE
635
`endif//////////////////////////////////////////////////////////////////////
636 6 unneback
////                                                              ////
637
////  Versatile library, registers                                ////
638
////                                                              ////
639
////  Description                                                 ////
640
////  Different type of registers                                 ////
641
////                                                              ////
642
////                                                              ////
643
////  To Do:                                                      ////
644
////   - add more different registers                             ////
645
////                                                              ////
646
////  Author(s):                                                  ////
647
////      - Michael Unneback, unneback@opencores.org              ////
648
////        ORSoC AB                                              ////
649
////                                                              ////
650
//////////////////////////////////////////////////////////////////////
651
////                                                              ////
652
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
653
////                                                              ////
654
//// This source file may be used and distributed without         ////
655
//// restriction provided that this copyright statement is not    ////
656
//// removed from the file and that any derivative work contains  ////
657
//// the original copyright notice and the associated disclaimer. ////
658
////                                                              ////
659
//// This source file is free software; you can redistribute it   ////
660
//// and/or modify it under the terms of the GNU Lesser General   ////
661
//// Public License as published by the Free Software Foundation; ////
662
//// either version 2.1 of the License, or (at your option) any   ////
663
//// later version.                                               ////
664
////                                                              ////
665
//// This source is distributed in the hope that it will be       ////
666
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
667
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
668
//// PURPOSE.  See the GNU Lesser General Public License for more ////
669
//// details.                                                     ////
670
////                                                              ////
671
//// You should have received a copy of the GNU Lesser General    ////
672
//// Public License along with this source; if not, download it   ////
673
//// from http://www.opencores.org/lgpl.shtml                     ////
674
////                                                              ////
675
//////////////////////////////////////////////////////////////////////
676
 
677 40 unneback
`ifdef DFF
678
`define MODULE dff
679
module `BASE`MODULE ( d, q, clk, rst);
680
`undef MODULE
681 6 unneback
        parameter width = 1;
682
        parameter reset_value = 0;
683
 
684
        input [width-1:0] d;
685
        input clk, rst;
686
        output reg [width-1:0] q;
687
 
688
        always @ (posedge clk or posedge rst)
689
        if (rst)
690
                q <= reset_value;
691
        else
692
                q <= d;
693
 
694
endmodule
695 40 unneback
`endif
696 6 unneback
 
697 40 unneback
`ifdef DFF_ARRAY
698
`define MODULE dff_array
699
module `BASE`MODULE ( d, q, clk, rst);
700
`undef MODULE
701 6 unneback
 
702
        parameter width = 1;
703
        parameter depth = 2;
704
        parameter reset_value = 1'b0;
705
 
706
        input [width-1:0] d;
707
        input clk, rst;
708
        output [width-1:0] q;
709
        reg  [0:depth-1] q_tmp [width-1:0];
710
        integer i;
711
        always @ (posedge clk or posedge rst)
712
        if (rst) begin
713
            for (i=0;i<depth;i=i+1)
714
                q_tmp[i] <= {width{reset_value}};
715
        end else begin
716
            q_tmp[0] <= d;
717
            for (i=1;i<depth;i=i+1)
718
                q_tmp[i] <= q_tmp[i-1];
719
        end
720
 
721
    assign q = q_tmp[depth-1];
722
 
723
endmodule
724 40 unneback
`endif
725 6 unneback
 
726 40 unneback
`ifdef DFF_CE
727
`define MODULE dff_ce
728
module `BASE`MODULE ( d, ce, q, clk, rst);
729
`undef MODULE
730 6 unneback
 
731
        parameter width = 1;
732
        parameter reset_value = 0;
733
 
734
        input [width-1:0] d;
735
        input ce, clk, rst;
736
        output reg [width-1:0] q;
737
 
738
        always @ (posedge clk or posedge rst)
739
        if (rst)
740
                q <= reset_value;
741
        else
742
                if (ce)
743
                        q <= d;
744
 
745
endmodule
746 40 unneback
`endif
747 6 unneback
 
748 40 unneback
`ifdef DFF_CE_CLEAR
749
`define MODULE dff_ce_clear
750
module `BASE`MODULE ( d, ce, clear, q, clk, rst);
751
`undef MODULE
752 8 unneback
 
753
        parameter width = 1;
754
        parameter reset_value = 0;
755
 
756
        input [width-1:0] d;
757 10 unneback
        input ce, clear, clk, rst;
758 8 unneback
        output reg [width-1:0] q;
759
 
760
        always @ (posedge clk or posedge rst)
761
        if (rst)
762
            q <= reset_value;
763
        else
764
            if (ce)
765
                if (clear)
766
                    q <= {width{1'b0}};
767
                else
768
                    q <= d;
769
 
770
endmodule
771 40 unneback
`endif
772 8 unneback
 
773 40 unneback
`ifdef DF_CE_SET
774
`define MODULE dff_ce_set
775
module `BASE`MODULE ( d, ce, set, q, clk, rst);
776
`undef MODULE
777 24 unneback
 
778
        parameter width = 1;
779
        parameter reset_value = 0;
780
 
781
        input [width-1:0] d;
782
        input ce, set, clk, rst;
783
        output reg [width-1:0] q;
784
 
785
        always @ (posedge clk or posedge rst)
786
        if (rst)
787
            q <= reset_value;
788
        else
789
            if (ce)
790
                if (set)
791
                    q <= {width{1'b1}};
792
                else
793
                    q <= d;
794
 
795
endmodule
796 40 unneback
`endif
797 24 unneback
 
798 40 unneback
`ifdef SPR
799
`define MODULE spr
800
module `BASE`MODULE ( sp, r, q, clk, rst);
801
`undef MODULE
802
 
803 29 unneback
        parameter width = 1;
804
        parameter reset_value = 0;
805
 
806
        input sp, r;
807
        output reg q;
808
        input clk, rst;
809
 
810
        always @ (posedge clk or posedge rst)
811
        if (rst)
812
            q <= reset_value;
813
        else
814
            if (sp)
815
                q <= 1'b1;
816
            else if (r)
817
                q <= 1'b0;
818
 
819
endmodule
820 40 unneback
`endif
821 29 unneback
 
822 40 unneback
`ifdef SRP
823
`define MODULE srp
824
module `BASE`MODULE ( s, rp, q, clk, rst);
825
`undef MODULE
826
 
827 29 unneback
        parameter width = 1;
828
        parameter reset_value = 0;
829
 
830
        input s, rp;
831
        output reg q;
832
        input clk, rst;
833
 
834
        always @ (posedge clk or posedge rst)
835
        if (rst)
836
            q <= reset_value;
837
        else
838
            if (rp)
839
                q <= 1'b0;
840
            else if (s)
841
                q <= 1'b1;
842
 
843
endmodule
844 40 unneback
`endif
845 29 unneback
 
846 40 unneback
`ifdef ALTERA
847 29 unneback
 
848 40 unneback
`ifdef DFF_SR
849 6 unneback
// megafunction wizard: %LPM_FF%
850
// GENERATION: STANDARD
851
// VERSION: WM1.0
852
// MODULE: lpm_ff 
853
 
854
// ============================================================
855
// File Name: dff_sr.v
856
// Megafunction Name(s):
857
//                      lpm_ff
858
//
859
// Simulation Library Files(s):
860
//                      lpm
861
// ============================================================
862
// ************************************************************
863
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
864
//
865
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
866
// ************************************************************
867
 
868
 
869
//Copyright (C) 1991-2010 Altera Corporation
870
//Your use of Altera Corporation's design tools, logic functions 
871
//and other software and tools, and its AMPP partner logic 
872
//functions, and any output files from any of the foregoing 
873
//(including device programming or simulation files), and any 
874
//associated documentation or information are expressly subject 
875
//to the terms and conditions of the Altera Program License 
876
//Subscription Agreement, Altera MegaCore Function License 
877
//Agreement, or other applicable license agreement, including, 
878
//without limitation, that your use is for the sole purpose of 
879
//programming logic devices manufactured by Altera and sold by 
880
//Altera or its authorized distributors.  Please refer to the 
881
//applicable agreement for further details.
882
 
883
 
884
// synopsys translate_off
885
`timescale 1 ps / 1 ps
886
// synopsys translate_on
887 40 unneback
`define MODULE dff_sr
888
module `BASE`MODULE (
889
`undef MODULE
890
 
891 6 unneback
        aclr,
892
        aset,
893
        clock,
894
        data,
895
        q);
896
 
897
        input     aclr;
898
        input     aset;
899
        input     clock;
900
        input     data;
901
        output    q;
902
 
903
        wire [0:0] sub_wire0;
904
        wire [0:0] sub_wire1 = sub_wire0[0:0];
905
        wire  q = sub_wire1;
906
        wire  sub_wire2 = data;
907
        wire  sub_wire3 = sub_wire2;
908
 
909
        lpm_ff  lpm_ff_component (
910
                                .aclr (aclr),
911
                                .clock (clock),
912
                                .data (sub_wire3),
913
                                .aset (aset),
914
                                .q (sub_wire0)
915
                                // synopsys translate_off
916
                                ,
917
                                .aload (),
918
                                .enable (),
919
                                .sclr (),
920
                                .sload (),
921
                                .sset ()
922
                                // synopsys translate_on
923
                                );
924
        defparam
925
                lpm_ff_component.lpm_fftype = "DFF",
926
                lpm_ff_component.lpm_type = "LPM_FF",
927
                lpm_ff_component.lpm_width = 1;
928
 
929
 
930
endmodule
931
 
932
// ============================================================
933
// CNX file retrieval info
934
// ============================================================
935
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
936
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
937
// Retrieval info: PRIVATE: ASET NUMERIC "1"
938
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
939
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
940
// Retrieval info: PRIVATE: DFF NUMERIC "1"
941
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
942
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
943
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
944
// Retrieval info: PRIVATE: SSET NUMERIC "0"
945
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
946
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
947
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
948
// Retrieval info: PRIVATE: nBit NUMERIC "1"
949
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
950
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
951
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
952
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
953
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
954
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
955
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
956
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
957
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
958
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
959
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
960
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
961
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
962
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
963
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
964
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
965
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
966
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
967
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
968
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
969
// Retrieval info: LIB_FILE: lpm
970 40 unneback
`endif
971 6 unneback
 
972
`else
973
 
974 40 unneback
`ifdef DFF_SR
975
`define MODULE dff_sr
976
module `BASE`MODULE ( aclr, aset, clock, data, q);
977
`undef MODULE
978 6 unneback
 
979
    input         aclr;
980
    input         aset;
981
    input         clock;
982
    input         data;
983
    output reg    q;
984
 
985
   always @ (posedge clock or posedge aclr or posedge aset)
986
     if (aclr)
987
       q <= 1'b0;
988
     else if (aset)
989
       q <= 1'b1;
990
     else
991
       q <= data;
992
 
993
endmodule
994 40 unneback
`endif
995 6 unneback
 
996
`endif
997
 
998
// LATCH
999
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
1000
`ifdef ALTERA
1001 40 unneback
 
1002
`ifdef LATCH
1003
`define MODULE latch
1004
module `BASE`MODULE ( d, le, q, clk);
1005
`undef MODULE
1006 6 unneback
input d, le;
1007
output q;
1008
input clk;
1009
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
1010
endmodule
1011 40 unneback
`endif
1012
 
1013 6 unneback
`else
1014 40 unneback
 
1015
`ifdef LATCH
1016
`define MODULE latch
1017
module `BASE`MODULE ( d, le, q, clk);
1018
`undef MODULE
1019 6 unneback
input d, le;
1020
output q;
1021
input clk;/*
1022
   always @ (posedge direction_set or posedge direction_clr)
1023
     if (direction_clr)
1024
       direction <= going_empty;
1025
     else
1026
       direction <= going_full;*/
1027
endmodule
1028 15 unneback
`endif
1029
 
1030 40 unneback
`endif
1031
 
1032
`ifdef SHREG
1033
`define MODULE shreg
1034
module `BASE`MODULE ( d, q, clk, rst);
1035
`undef MODULE
1036
 
1037 17 unneback
parameter depth = 10;
1038
input d;
1039
output q;
1040
input clk, rst;
1041
 
1042
reg [1:depth] dffs;
1043
 
1044
always @ (posedge clk or posedge rst)
1045
if (rst)
1046
    dffs <= {depth{1'b0}};
1047
else
1048
    dffs <= {d,dffs[1:depth-1]};
1049
assign q = dffs[depth];
1050
endmodule
1051 40 unneback
`endif
1052 17 unneback
 
1053 40 unneback
`ifdef SHREG_CE
1054
`define MODULE shreg_ce
1055
module `BASE`MODULE ( d, ce, q, clk, rst);
1056
`undef MODULE
1057 17 unneback
parameter depth = 10;
1058
input d, ce;
1059
output q;
1060
input clk, rst;
1061
 
1062
reg [1:depth] dffs;
1063
 
1064
always @ (posedge clk or posedge rst)
1065
if (rst)
1066
    dffs <= {depth{1'b0}};
1067
else
1068
    if (ce)
1069
        dffs <= {d,dffs[1:depth-1]};
1070
assign q = dffs[depth];
1071
endmodule
1072 40 unneback
`endif
1073 17 unneback
 
1074 40 unneback
`ifdef DELAY
1075
`define MODULE delay
1076
module `BASE`MODULE ( d, q, clk, rst);
1077
`undef MODULE
1078 15 unneback
parameter depth = 10;
1079
input d;
1080
output q;
1081
input clk, rst;
1082
 
1083
reg [1:depth] dffs;
1084
 
1085
always @ (posedge clk or posedge rst)
1086
if (rst)
1087
    dffs <= {depth{1'b0}};
1088
else
1089
    dffs <= {d,dffs[1:depth-1]};
1090
assign q = dffs[depth];
1091 17 unneback
endmodule
1092 40 unneback
`endif
1093 17 unneback
 
1094 40 unneback
`ifdef DELAY_EMPTYFLAG
1095
`define MODULE delay_emptyflag
1096 41 unneback
module `BASE`MODULE ( d, q, emptyflag, clk, rst);
1097 40 unneback
`undef MODULE
1098 17 unneback
parameter depth = 10;
1099
input d;
1100
output q, emptyflag;
1101
input clk, rst;
1102
 
1103
reg [1:depth] dffs;
1104
 
1105
always @ (posedge clk or posedge rst)
1106
if (rst)
1107
    dffs <= {depth{1'b0}};
1108
else
1109
    dffs <= {d,dffs[1:depth-1]};
1110
assign q = dffs[depth];
1111
assign emptyflag = !(|dffs);
1112
endmodule
1113 40 unneback
`endif
1114 17 unneback
//////////////////////////////////////////////////////////////////////
1115 6 unneback
////                                                              ////
1116 18 unneback
////  Logic functions                                             ////
1117
////                                                              ////
1118
////  Description                                                 ////
1119
////  Logic functions such as multiplexers                        ////
1120
////                                                              ////
1121
////                                                              ////
1122
////  To Do:                                                      ////
1123
////   -                                                          ////
1124
////                                                              ////
1125
////  Author(s):                                                  ////
1126
////      - Michael Unneback, unneback@opencores.org              ////
1127
////        ORSoC AB                                              ////
1128
////                                                              ////
1129
//////////////////////////////////////////////////////////////////////
1130
////                                                              ////
1131
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1132
////                                                              ////
1133
//// This source file may be used and distributed without         ////
1134
//// restriction provided that this copyright statement is not    ////
1135
//// removed from the file and that any derivative work contains  ////
1136
//// the original copyright notice and the associated disclaimer. ////
1137
////                                                              ////
1138
//// This source file is free software; you can redistribute it   ////
1139
//// and/or modify it under the terms of the GNU Lesser General   ////
1140
//// Public License as published by the Free Software Foundation; ////
1141
//// either version 2.1 of the License, or (at your option) any   ////
1142
//// later version.                                               ////
1143
////                                                              ////
1144
//// This source is distributed in the hope that it will be       ////
1145
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1146
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1147
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1148
//// details.                                                     ////
1149
////                                                              ////
1150
//// You should have received a copy of the GNU Lesser General    ////
1151
//// Public License along with this source; if not, download it   ////
1152
//// from http://www.opencores.org/lgpl.shtml                     ////
1153
////                                                              ////
1154
//////////////////////////////////////////////////////////////////////
1155 40 unneback
`ifdef MUX_ANDOR
1156
`define MODULE mux_andor
1157
module `BASE`MODULE ( a, sel, dout);
1158
`undef MODULE
1159 36 unneback
 
1160
parameter width = 32;
1161
parameter nr_of_ports = 4;
1162
 
1163
input [nr_of_ports*width-1:0] a;
1164
input [nr_of_ports-1:0] sel;
1165
output reg [width-1:0] dout;
1166
 
1167 38 unneback
integer i,j;
1168
 
1169 36 unneback
always @ (a, sel)
1170
begin
1171
    dout = a[width-1:0] & {width{sel[0]}};
1172 42 unneback
    for (i=1;i<nr_of_ports;i=i+1)
1173
        for (j=0;j<width;j=j+1)
1174
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
1175 36 unneback
end
1176
 
1177
endmodule
1178 40 unneback
`endif
1179 36 unneback
 
1180 40 unneback
`ifdef MUX2_ANDOR
1181
`define MODULE mux2_andor
1182
module `BASE`MODULE ( a1, a0, sel, dout);
1183
`undef MODULE
1184 18 unneback
 
1185 34 unneback
parameter width = 32;
1186 35 unneback
localparam nr_of_ports = 2;
1187 34 unneback
input [width-1:0] a1, a0;
1188
input [nr_of_ports-1:0] sel;
1189
output [width-1:0] dout;
1190
 
1191 40 unneback
`define MODULE mux_andor
1192
`BASE`MODULE
1193 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1194 36 unneback
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
1195 40 unneback
`undef MODULE
1196
 
1197 34 unneback
endmodule
1198 40 unneback
`endif
1199 34 unneback
 
1200 40 unneback
`ifdef MUX3_ANDOR
1201
`define MODULE mux3_andor
1202
module `BASE`MODULE ( a2, a1, a0, sel, dout);
1203
`undef MODULE
1204 34 unneback
 
1205
parameter width = 32;
1206 35 unneback
localparam nr_of_ports = 3;
1207 34 unneback
input [width-1:0] a2, a1, a0;
1208
input [nr_of_ports-1:0] sel;
1209
output [width-1:0] dout;
1210
 
1211 40 unneback
`define MODULE mux_andor
1212
`BASE`MODULE
1213 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1214 36 unneback
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
1215 40 unneback
`undef MODULE
1216 34 unneback
endmodule
1217 40 unneback
`endif
1218 34 unneback
 
1219 40 unneback
`ifdef MUX4_ANDOR
1220
`define MODULE mux4_andor
1221
module `BASE`MODULE ( a3, a2, a1, a0, sel, dout);
1222
`undef MODULE
1223 18 unneback
 
1224
parameter width = 32;
1225 35 unneback
localparam nr_of_ports = 4;
1226 18 unneback
input [width-1:0] a3, a2, a1, a0;
1227
input [nr_of_ports-1:0] sel;
1228 22 unneback
output [width-1:0] dout;
1229 18 unneback
 
1230 40 unneback
`define MODULE mux_andor
1231
`BASE`MODULE
1232 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1233 36 unneback
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
1234 40 unneback
`undef MODULE
1235 18 unneback
 
1236
endmodule
1237 40 unneback
`endif
1238 18 unneback
 
1239 40 unneback
`ifdef MUX5_ANDOR
1240
`define MODULE mux5_andor
1241
module `BASE`MODULE ( a4, a3, a2, a1, a0, sel, dout);
1242
`undef MODULE
1243 18 unneback
 
1244
parameter width = 32;
1245 35 unneback
localparam nr_of_ports = 5;
1246 18 unneback
input [width-1:0] a4, a3, a2, a1, a0;
1247
input [nr_of_ports-1:0] sel;
1248 22 unneback
output [width-1:0] dout;
1249 18 unneback
 
1250 40 unneback
`define MODULE mux_andor
1251
`BASE`MODULE
1252 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1253 36 unneback
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1254 40 unneback
`undef MODULE
1255 18 unneback
 
1256
endmodule
1257 40 unneback
`endif
1258 18 unneback
 
1259 40 unneback
`ifdef MUX6_ANDOR
1260
`define MODULE mux6_andor
1261
module `BASE`MODULE ( a5, a4, a3, a2, a1, a0, sel, dout);
1262
`undef MODULE
1263 18 unneback
 
1264
parameter width = 32;
1265 35 unneback
localparam nr_of_ports = 6;
1266 18 unneback
input [width-1:0] a5, a4, a3, a2, a1, a0;
1267
input [nr_of_ports-1:0] sel;
1268 22 unneback
output [width-1:0] dout;
1269 18 unneback
 
1270 40 unneback
`define MODULE mux_andor
1271
`BASE`MODULE
1272 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1273 36 unneback
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1274 40 unneback
`undef MODULE
1275 18 unneback
 
1276
endmodule
1277 40 unneback
`endif
1278
`ifdef CNT_BIN
1279 18 unneback
//////////////////////////////////////////////////////////////////////
1280
////                                                              ////
1281 6 unneback
////  Versatile counter                                           ////
1282
////                                                              ////
1283
////  Description                                                 ////
1284
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1285
////  counter                                                     ////
1286
////                                                              ////
1287
////  To Do:                                                      ////
1288
////   - add LFSR with more taps                                  ////
1289
////                                                              ////
1290
////  Author(s):                                                  ////
1291
////      - Michael Unneback, unneback@opencores.org              ////
1292
////        ORSoC AB                                              ////
1293
////                                                              ////
1294
//////////////////////////////////////////////////////////////////////
1295
////                                                              ////
1296
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1297
////                                                              ////
1298
//// This source file may be used and distributed without         ////
1299
//// restriction provided that this copyright statement is not    ////
1300
//// removed from the file and that any derivative work contains  ////
1301
//// the original copyright notice and the associated disclaimer. ////
1302
////                                                              ////
1303
//// This source file is free software; you can redistribute it   ////
1304
//// and/or modify it under the terms of the GNU Lesser General   ////
1305
//// Public License as published by the Free Software Foundation; ////
1306
//// either version 2.1 of the License, or (at your option) any   ////
1307
//// later version.                                               ////
1308
////                                                              ////
1309
//// This source is distributed in the hope that it will be       ////
1310
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1311
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1312
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1313
//// details.                                                     ////
1314
////                                                              ////
1315
//// You should have received a copy of the GNU Lesser General    ////
1316
//// Public License along with this source; if not, download it   ////
1317
//// from http://www.opencores.org/lgpl.shtml                     ////
1318
////                                                              ////
1319
//////////////////////////////////////////////////////////////////////
1320
 
1321
// binary counter
1322 22 unneback
 
1323 40 unneback
`define MODULE cnt_bin
1324
module `BASE`MODULE (
1325
`undef MODULE
1326
 q, rst, clk);
1327
 
1328 22 unneback
   parameter length = 4;
1329
   output [length:1] q;
1330
   input rst;
1331
   input clk;
1332
 
1333
   parameter clear_value = 0;
1334
   parameter set_value = 1;
1335
   parameter wrap_value = 0;
1336
   parameter level1_value = 15;
1337
 
1338
   reg  [length:1] qi;
1339
   wire [length:1] q_next;
1340
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1341
 
1342
   always @ (posedge clk or posedge rst)
1343
     if (rst)
1344
       qi <= {length{1'b0}};
1345
     else
1346
       qi <= q_next;
1347
 
1348
   assign q = qi;
1349
 
1350
endmodule
1351 40 unneback
`endif
1352
`ifdef CNT_BIN_CLEAR
1353 22 unneback
//////////////////////////////////////////////////////////////////////
1354
////                                                              ////
1355
////  Versatile counter                                           ////
1356
////                                                              ////
1357
////  Description                                                 ////
1358
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1359
////  counter                                                     ////
1360
////                                                              ////
1361
////  To Do:                                                      ////
1362
////   - add LFSR with more taps                                  ////
1363
////                                                              ////
1364
////  Author(s):                                                  ////
1365
////      - Michael Unneback, unneback@opencores.org              ////
1366
////        ORSoC AB                                              ////
1367
////                                                              ////
1368
//////////////////////////////////////////////////////////////////////
1369
////                                                              ////
1370
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1371
////                                                              ////
1372
//// This source file may be used and distributed without         ////
1373
//// restriction provided that this copyright statement is not    ////
1374
//// removed from the file and that any derivative work contains  ////
1375
//// the original copyright notice and the associated disclaimer. ////
1376
////                                                              ////
1377
//// This source file is free software; you can redistribute it   ////
1378
//// and/or modify it under the terms of the GNU Lesser General   ////
1379
//// Public License as published by the Free Software Foundation; ////
1380
//// either version 2.1 of the License, or (at your option) any   ////
1381
//// later version.                                               ////
1382
////                                                              ////
1383
//// This source is distributed in the hope that it will be       ////
1384
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1385
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1386
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1387
//// details.                                                     ////
1388
////                                                              ////
1389
//// You should have received a copy of the GNU Lesser General    ////
1390
//// Public License along with this source; if not, download it   ////
1391
//// from http://www.opencores.org/lgpl.shtml                     ////
1392
////                                                              ////
1393
//////////////////////////////////////////////////////////////////////
1394
 
1395
// binary counter
1396
 
1397 40 unneback
`define MODULE cnt_bin_clear
1398
module `BASE`MODULE (
1399
`undef MODULE
1400
 clear, q, rst, clk);
1401
 
1402 22 unneback
   parameter length = 4;
1403
   input clear;
1404
   output [length:1] q;
1405
   input rst;
1406
   input clk;
1407
 
1408
   parameter clear_value = 0;
1409
   parameter set_value = 1;
1410
   parameter wrap_value = 0;
1411
   parameter level1_value = 15;
1412
 
1413
   reg  [length:1] qi;
1414
   wire [length:1] q_next;
1415
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1416
 
1417
   always @ (posedge clk or posedge rst)
1418
     if (rst)
1419
       qi <= {length{1'b0}};
1420
     else
1421
       qi <= q_next;
1422
 
1423
   assign q = qi;
1424
 
1425
endmodule
1426 40 unneback
`endif
1427
`ifdef CNT_BIN_CE
1428 22 unneback
//////////////////////////////////////////////////////////////////////
1429
////                                                              ////
1430
////  Versatile counter                                           ////
1431
////                                                              ////
1432
////  Description                                                 ////
1433
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1434
////  counter                                                     ////
1435
////                                                              ////
1436
////  To Do:                                                      ////
1437
////   - add LFSR with more taps                                  ////
1438
////                                                              ////
1439
////  Author(s):                                                  ////
1440
////      - Michael Unneback, unneback@opencores.org              ////
1441
////        ORSoC AB                                              ////
1442
////                                                              ////
1443
//////////////////////////////////////////////////////////////////////
1444
////                                                              ////
1445
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1446
////                                                              ////
1447
//// This source file may be used and distributed without         ////
1448
//// restriction provided that this copyright statement is not    ////
1449
//// removed from the file and that any derivative work contains  ////
1450
//// the original copyright notice and the associated disclaimer. ////
1451
////                                                              ////
1452
//// This source file is free software; you can redistribute it   ////
1453
//// and/or modify it under the terms of the GNU Lesser General   ////
1454
//// Public License as published by the Free Software Foundation; ////
1455
//// either version 2.1 of the License, or (at your option) any   ////
1456
//// later version.                                               ////
1457
////                                                              ////
1458
//// This source is distributed in the hope that it will be       ////
1459
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1460
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1461
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1462
//// details.                                                     ////
1463
////                                                              ////
1464
//// You should have received a copy of the GNU Lesser General    ////
1465
//// Public License along with this source; if not, download it   ////
1466
//// from http://www.opencores.org/lgpl.shtml                     ////
1467
////                                                              ////
1468
//////////////////////////////////////////////////////////////////////
1469
 
1470
// binary counter
1471 6 unneback
 
1472 40 unneback
`define MODULE cnt_bin_ce
1473
module `BASE`MODULE (
1474
`undef MODULE
1475
 cke, q, rst, clk);
1476
 
1477 6 unneback
   parameter length = 4;
1478
   input cke;
1479
   output [length:1] q;
1480
   input rst;
1481
   input clk;
1482
 
1483
   parameter clear_value = 0;
1484
   parameter set_value = 1;
1485
   parameter wrap_value = 0;
1486
   parameter level1_value = 15;
1487
 
1488
   reg  [length:1] qi;
1489
   wire [length:1] q_next;
1490
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1491
 
1492
   always @ (posedge clk or posedge rst)
1493
     if (rst)
1494
       qi <= {length{1'b0}};
1495
     else
1496
     if (cke)
1497
       qi <= q_next;
1498
 
1499
   assign q = qi;
1500
 
1501
endmodule
1502 40 unneback
`endif
1503
`ifdef CNT_BIN_CE_CLEAR
1504 6 unneback
//////////////////////////////////////////////////////////////////////
1505
////                                                              ////
1506
////  Versatile counter                                           ////
1507
////                                                              ////
1508
////  Description                                                 ////
1509
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1510
////  counter                                                     ////
1511
////                                                              ////
1512
////  To Do:                                                      ////
1513
////   - add LFSR with more taps                                  ////
1514
////                                                              ////
1515
////  Author(s):                                                  ////
1516
////      - Michael Unneback, unneback@opencores.org              ////
1517
////        ORSoC AB                                              ////
1518
////                                                              ////
1519
//////////////////////////////////////////////////////////////////////
1520
////                                                              ////
1521
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1522
////                                                              ////
1523
//// This source file may be used and distributed without         ////
1524
//// restriction provided that this copyright statement is not    ////
1525
//// removed from the file and that any derivative work contains  ////
1526
//// the original copyright notice and the associated disclaimer. ////
1527
////                                                              ////
1528
//// This source file is free software; you can redistribute it   ////
1529
//// and/or modify it under the terms of the GNU Lesser General   ////
1530
//// Public License as published by the Free Software Foundation; ////
1531
//// either version 2.1 of the License, or (at your option) any   ////
1532
//// later version.                                               ////
1533
////                                                              ////
1534
//// This source is distributed in the hope that it will be       ////
1535
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1536
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1537
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1538
//// details.                                                     ////
1539
////                                                              ////
1540
//// You should have received a copy of the GNU Lesser General    ////
1541
//// Public License along with this source; if not, download it   ////
1542
//// from http://www.opencores.org/lgpl.shtml                     ////
1543
////                                                              ////
1544
//////////////////////////////////////////////////////////////////////
1545
 
1546
// binary counter
1547
 
1548 40 unneback
`define MODULE cnt_bin_ce_clear
1549
module `BASE`MODULE (
1550
`undef MODULE
1551
 clear, cke, q, rst, clk);
1552
 
1553 6 unneback
   parameter length = 4;
1554
   input clear;
1555
   input cke;
1556
   output [length:1] q;
1557
   input rst;
1558
   input clk;
1559
 
1560
   parameter clear_value = 0;
1561
   parameter set_value = 1;
1562
   parameter wrap_value = 0;
1563
   parameter level1_value = 15;
1564
 
1565
   reg  [length:1] qi;
1566
   wire [length:1] q_next;
1567
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1568
 
1569
   always @ (posedge clk or posedge rst)
1570
     if (rst)
1571
       qi <= {length{1'b0}};
1572
     else
1573
     if (cke)
1574
       qi <= q_next;
1575
 
1576
   assign q = qi;
1577
 
1578
endmodule
1579 40 unneback
`endif
1580
`ifdef CNT_BIN_CE_CLEAR_L1_L2
1581 6 unneback
//////////////////////////////////////////////////////////////////////
1582
////                                                              ////
1583
////  Versatile counter                                           ////
1584
////                                                              ////
1585
////  Description                                                 ////
1586
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1587
////  counter                                                     ////
1588
////                                                              ////
1589
////  To Do:                                                      ////
1590
////   - add LFSR with more taps                                  ////
1591
////                                                              ////
1592
////  Author(s):                                                  ////
1593
////      - Michael Unneback, unneback@opencores.org              ////
1594
////        ORSoC AB                                              ////
1595
////                                                              ////
1596
//////////////////////////////////////////////////////////////////////
1597
////                                                              ////
1598
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1599
////                                                              ////
1600
//// This source file may be used and distributed without         ////
1601
//// restriction provided that this copyright statement is not    ////
1602
//// removed from the file and that any derivative work contains  ////
1603
//// the original copyright notice and the associated disclaimer. ////
1604
////                                                              ////
1605
//// This source file is free software; you can redistribute it   ////
1606
//// and/or modify it under the terms of the GNU Lesser General   ////
1607
//// Public License as published by the Free Software Foundation; ////
1608
//// either version 2.1 of the License, or (at your option) any   ////
1609
//// later version.                                               ////
1610
////                                                              ////
1611
//// This source is distributed in the hope that it will be       ////
1612
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1613
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1614
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1615
//// details.                                                     ////
1616
////                                                              ////
1617
//// You should have received a copy of the GNU Lesser General    ////
1618
//// Public License along with this source; if not, download it   ////
1619
//// from http://www.opencores.org/lgpl.shtml                     ////
1620
////                                                              ////
1621
//////////////////////////////////////////////////////////////////////
1622
 
1623
// binary counter
1624 29 unneback
 
1625 40 unneback
`define MODULE cnt_bin_ce_clear_l1_l2
1626
module `BASE`MODULE (
1627
`undef MODULE
1628
 clear, cke, q, level1, level2, rst, clk);
1629
 
1630 29 unneback
   parameter length = 4;
1631
   input clear;
1632
   input cke;
1633
   output [length:1] q;
1634
   output reg level1;
1635
   output reg level2;
1636
   input rst;
1637
   input clk;
1638
 
1639
   parameter clear_value = 0;
1640
   parameter set_value = 1;
1641 30 unneback
   parameter wrap_value = 15;
1642
   parameter level1_value = 8;
1643
   parameter level2_value = 15;
1644 29 unneback
 
1645
   wire rew;
1646 30 unneback
   assign rew = 1'b0;
1647 29 unneback
   reg  [length:1] qi;
1648
   wire [length:1] q_next;
1649
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1650
 
1651
   always @ (posedge clk or posedge rst)
1652
     if (rst)
1653
       qi <= {length{1'b0}};
1654
     else
1655
     if (cke)
1656
       qi <= q_next;
1657
 
1658
   assign q = qi;
1659
 
1660
 
1661
    always @ (posedge clk or posedge rst)
1662
    if (rst)
1663
        level1 <= 1'b0;
1664
    else
1665
    if (cke)
1666
    if (clear)
1667
        level1 <= 1'b0;
1668
    else if (q_next == level1_value)
1669
        level1 <= 1'b1;
1670
    else if (qi == level1_value & rew)
1671
        level1 <= 1'b0;
1672
 
1673
    always @ (posedge clk or posedge rst)
1674
    if (rst)
1675
        level2 <= 1'b0;
1676
    else
1677
    if (cke)
1678
    if (clear)
1679
        level2 <= 1'b0;
1680
    else if (q_next == level2_value)
1681
        level2 <= 1'b1;
1682
    else if (qi == level2_value & rew)
1683
        level2 <= 1'b0;
1684
endmodule
1685 40 unneback
`endif
1686
`ifdef CNT_BIN_CE_CLEAR_SET_REW
1687 29 unneback
//////////////////////////////////////////////////////////////////////
1688
////                                                              ////
1689
////  Versatile counter                                           ////
1690
////                                                              ////
1691
////  Description                                                 ////
1692
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1693
////  counter                                                     ////
1694
////                                                              ////
1695
////  To Do:                                                      ////
1696
////   - add LFSR with more taps                                  ////
1697
////                                                              ////
1698
////  Author(s):                                                  ////
1699
////      - Michael Unneback, unneback@opencores.org              ////
1700
////        ORSoC AB                                              ////
1701
////                                                              ////
1702
//////////////////////////////////////////////////////////////////////
1703
////                                                              ////
1704
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1705
////                                                              ////
1706
//// This source file may be used and distributed without         ////
1707
//// restriction provided that this copyright statement is not    ////
1708
//// removed from the file and that any derivative work contains  ////
1709
//// the original copyright notice and the associated disclaimer. ////
1710
////                                                              ////
1711
//// This source file is free software; you can redistribute it   ////
1712
//// and/or modify it under the terms of the GNU Lesser General   ////
1713
//// Public License as published by the Free Software Foundation; ////
1714
//// either version 2.1 of the License, or (at your option) any   ////
1715
//// later version.                                               ////
1716
////                                                              ////
1717
//// This source is distributed in the hope that it will be       ////
1718
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1719
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1720
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1721
//// details.                                                     ////
1722
////                                                              ////
1723
//// You should have received a copy of the GNU Lesser General    ////
1724
//// Public License along with this source; if not, download it   ////
1725
//// from http://www.opencores.org/lgpl.shtml                     ////
1726
////                                                              ////
1727
//////////////////////////////////////////////////////////////////////
1728
 
1729
// binary counter
1730 6 unneback
 
1731 40 unneback
`define MODULE cnt_bin_ce_clear_set_rew
1732
module `BASE`MODULE (
1733
`undef MODULE
1734
 clear, set, cke, rew, q, rst, clk);
1735
 
1736 6 unneback
   parameter length = 4;
1737
   input clear;
1738
   input set;
1739
   input cke;
1740
   input rew;
1741
   output [length:1] q;
1742
   input rst;
1743
   input clk;
1744
 
1745
   parameter clear_value = 0;
1746
   parameter set_value = 1;
1747
   parameter wrap_value = 0;
1748
   parameter level1_value = 15;
1749
 
1750
   reg  [length:1] qi;
1751
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1752
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
1753
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
1754
   assign q_next = rew ? q_next_rew : q_next_fw;
1755
 
1756
   always @ (posedge clk or posedge rst)
1757
     if (rst)
1758
       qi <= {length{1'b0}};
1759
     else
1760
     if (cke)
1761
       qi <= q_next;
1762
 
1763
   assign q = qi;
1764
 
1765
endmodule
1766 40 unneback
`endif
1767
`ifdef CNT_BIN_CE_REW_L1
1768 6 unneback
//////////////////////////////////////////////////////////////////////
1769
////                                                              ////
1770
////  Versatile counter                                           ////
1771
////                                                              ////
1772
////  Description                                                 ////
1773
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1774
////  counter                                                     ////
1775
////                                                              ////
1776
////  To Do:                                                      ////
1777
////   - add LFSR with more taps                                  ////
1778
////                                                              ////
1779
////  Author(s):                                                  ////
1780
////      - Michael Unneback, unneback@opencores.org              ////
1781
////        ORSoC AB                                              ////
1782
////                                                              ////
1783
//////////////////////////////////////////////////////////////////////
1784
////                                                              ////
1785
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1786
////                                                              ////
1787
//// This source file may be used and distributed without         ////
1788
//// restriction provided that this copyright statement is not    ////
1789
//// removed from the file and that any derivative work contains  ////
1790
//// the original copyright notice and the associated disclaimer. ////
1791
////                                                              ////
1792
//// This source file is free software; you can redistribute it   ////
1793
//// and/or modify it under the terms of the GNU Lesser General   ////
1794
//// Public License as published by the Free Software Foundation; ////
1795
//// either version 2.1 of the License, or (at your option) any   ////
1796
//// later version.                                               ////
1797
////                                                              ////
1798
//// This source is distributed in the hope that it will be       ////
1799
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1800
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1801
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1802
//// details.                                                     ////
1803
////                                                              ////
1804
//// You should have received a copy of the GNU Lesser General    ////
1805
//// Public License along with this source; if not, download it   ////
1806
//// from http://www.opencores.org/lgpl.shtml                     ////
1807
////                                                              ////
1808
//////////////////////////////////////////////////////////////////////
1809
 
1810
// binary counter
1811
 
1812 40 unneback
`define MODULE cnt_bin_ce_rew_l1
1813
module `BASE`MODULE (
1814
`undef MODULE
1815
 cke, rew, level1, rst, clk);
1816
 
1817 6 unneback
   parameter length = 4;
1818
   input cke;
1819
   input rew;
1820
   output reg level1;
1821
   input rst;
1822
   input clk;
1823
 
1824
   parameter clear_value = 0;
1825
   parameter set_value = 1;
1826
   parameter wrap_value = 1;
1827
   parameter level1_value = 15;
1828
 
1829 29 unneback
   wire clear;
1830 30 unneback
   assign clear = 1'b0;
1831 6 unneback
   reg  [length:1] qi;
1832
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1833
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1834
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1835
   assign q_next = rew ? q_next_rew : q_next_fw;
1836
 
1837
   always @ (posedge clk or posedge rst)
1838
     if (rst)
1839
       qi <= {length{1'b0}};
1840
     else
1841
     if (cke)
1842
       qi <= q_next;
1843
 
1844
 
1845
 
1846
    always @ (posedge clk or posedge rst)
1847
    if (rst)
1848
        level1 <= 1'b0;
1849
    else
1850
    if (cke)
1851 29 unneback
    if (clear)
1852
        level1 <= 1'b0;
1853
    else if (q_next == level1_value)
1854 6 unneback
        level1 <= 1'b1;
1855
    else if (qi == level1_value & rew)
1856
        level1 <= 1'b0;
1857
endmodule
1858 40 unneback
`endif
1859
`ifdef CNT_BIN_CE_REW_ZQ_L1
1860 6 unneback
//////////////////////////////////////////////////////////////////////
1861
////                                                              ////
1862
////  Versatile counter                                           ////
1863
////                                                              ////
1864
////  Description                                                 ////
1865
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1866
////  counter                                                     ////
1867
////                                                              ////
1868
////  To Do:                                                      ////
1869
////   - add LFSR with more taps                                  ////
1870
////                                                              ////
1871
////  Author(s):                                                  ////
1872
////      - Michael Unneback, unneback@opencores.org              ////
1873
////        ORSoC AB                                              ////
1874
////                                                              ////
1875
//////////////////////////////////////////////////////////////////////
1876
////                                                              ////
1877
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1878
////                                                              ////
1879
//// This source file may be used and distributed without         ////
1880
//// restriction provided that this copyright statement is not    ////
1881
//// removed from the file and that any derivative work contains  ////
1882
//// the original copyright notice and the associated disclaimer. ////
1883
////                                                              ////
1884
//// This source file is free software; you can redistribute it   ////
1885
//// and/or modify it under the terms of the GNU Lesser General   ////
1886
//// Public License as published by the Free Software Foundation; ////
1887
//// either version 2.1 of the License, or (at your option) any   ////
1888
//// later version.                                               ////
1889
////                                                              ////
1890
//// This source is distributed in the hope that it will be       ////
1891
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1892
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1893
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1894
//// details.                                                     ////
1895
////                                                              ////
1896
//// You should have received a copy of the GNU Lesser General    ////
1897
//// Public License along with this source; if not, download it   ////
1898
//// from http://www.opencores.org/lgpl.shtml                     ////
1899
////                                                              ////
1900
//////////////////////////////////////////////////////////////////////
1901
 
1902 25 unneback
// binary counter
1903
 
1904 40 unneback
`define MODULE cnt_bin_ce_rew_zq_l1
1905
module `BASE`MODULE (
1906
`undef MODULE
1907
 cke, rew, zq, level1, rst, clk);
1908
 
1909 25 unneback
   parameter length = 4;
1910
   input cke;
1911
   input rew;
1912
   output reg zq;
1913
   output reg level1;
1914
   input rst;
1915
   input clk;
1916
 
1917
   parameter clear_value = 0;
1918
   parameter set_value = 1;
1919
   parameter wrap_value = 1;
1920
   parameter level1_value = 15;
1921
 
1922 29 unneback
   wire clear;
1923 30 unneback
   assign clear = 1'b0;
1924 25 unneback
   reg  [length:1] qi;
1925
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1926
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1927
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1928
   assign q_next = rew ? q_next_rew : q_next_fw;
1929
 
1930
   always @ (posedge clk or posedge rst)
1931
     if (rst)
1932
       qi <= {length{1'b0}};
1933
     else
1934
     if (cke)
1935
       qi <= q_next;
1936
 
1937
 
1938
 
1939
   always @ (posedge clk or posedge rst)
1940
     if (rst)
1941
       zq <= 1'b1;
1942
     else
1943
     if (cke)
1944
       zq <= q_next == {length{1'b0}};
1945
 
1946
    always @ (posedge clk or posedge rst)
1947
    if (rst)
1948
        level1 <= 1'b0;
1949
    else
1950
    if (cke)
1951 29 unneback
    if (clear)
1952
        level1 <= 1'b0;
1953
    else if (q_next == level1_value)
1954 25 unneback
        level1 <= 1'b1;
1955
    else if (qi == level1_value & rew)
1956
        level1 <= 1'b0;
1957
endmodule
1958 40 unneback
`endif
1959
`ifdef CNT_BIN_CE_REW_Q_ZQ_L1
1960 25 unneback
//////////////////////////////////////////////////////////////////////
1961
////                                                              ////
1962
////  Versatile counter                                           ////
1963
////                                                              ////
1964
////  Description                                                 ////
1965
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1966
////  counter                                                     ////
1967
////                                                              ////
1968
////  To Do:                                                      ////
1969
////   - add LFSR with more taps                                  ////
1970
////                                                              ////
1971
////  Author(s):                                                  ////
1972
////      - Michael Unneback, unneback@opencores.org              ////
1973
////        ORSoC AB                                              ////
1974
////                                                              ////
1975
//////////////////////////////////////////////////////////////////////
1976
////                                                              ////
1977
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1978
////                                                              ////
1979
//// This source file may be used and distributed without         ////
1980
//// restriction provided that this copyright statement is not    ////
1981
//// removed from the file and that any derivative work contains  ////
1982
//// the original copyright notice and the associated disclaimer. ////
1983
////                                                              ////
1984
//// This source file is free software; you can redistribute it   ////
1985
//// and/or modify it under the terms of the GNU Lesser General   ////
1986
//// Public License as published by the Free Software Foundation; ////
1987
//// either version 2.1 of the License, or (at your option) any   ////
1988
//// later version.                                               ////
1989
////                                                              ////
1990
//// This source is distributed in the hope that it will be       ////
1991
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1992
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1993
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1994
//// details.                                                     ////
1995
////                                                              ////
1996
//// You should have received a copy of the GNU Lesser General    ////
1997
//// Public License along with this source; if not, download it   ////
1998
//// from http://www.opencores.org/lgpl.shtml                     ////
1999
////                                                              ////
2000
//////////////////////////////////////////////////////////////////////
2001
 
2002
// binary counter
2003
 
2004 40 unneback
`define MODULE cnt_bin_ce_rew_q_zq_l1
2005
module `BASE`MODULE (
2006
`undef MODULE
2007
 cke, rew, q, zq, level1, rst, clk);
2008
 
2009 25 unneback
   parameter length = 4;
2010
   input cke;
2011
   input rew;
2012
   output [length:1] q;
2013
   output reg zq;
2014
   output reg level1;
2015
   input rst;
2016
   input clk;
2017
 
2018
   parameter clear_value = 0;
2019
   parameter set_value = 1;
2020
   parameter wrap_value = 1;
2021
   parameter level1_value = 15;
2022
 
2023 29 unneback
   wire clear;
2024 30 unneback
   assign clear = 1'b0;
2025 25 unneback
   reg  [length:1] qi;
2026
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2027
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2028
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2029
   assign q_next = rew ? q_next_rew : q_next_fw;
2030
 
2031
   always @ (posedge clk or posedge rst)
2032
     if (rst)
2033
       qi <= {length{1'b0}};
2034
     else
2035
     if (cke)
2036
       qi <= q_next;
2037
 
2038
   assign q = qi;
2039
 
2040
 
2041
   always @ (posedge clk or posedge rst)
2042
     if (rst)
2043
       zq <= 1'b1;
2044
     else
2045
     if (cke)
2046
       zq <= q_next == {length{1'b0}};
2047
 
2048
    always @ (posedge clk or posedge rst)
2049
    if (rst)
2050
        level1 <= 1'b0;
2051
    else
2052
    if (cke)
2053 29 unneback
    if (clear)
2054
        level1 <= 1'b0;
2055
    else if (q_next == level1_value)
2056 25 unneback
        level1 <= 1'b1;
2057
    else if (qi == level1_value & rew)
2058
        level1 <= 1'b0;
2059
endmodule
2060 40 unneback
`endif
2061
`ifdef CNT_LFSR_ZQ
2062 25 unneback
//////////////////////////////////////////////////////////////////////
2063
////                                                              ////
2064
////  Versatile counter                                           ////
2065
////                                                              ////
2066
////  Description                                                 ////
2067
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2068
////  counter                                                     ////
2069
////                                                              ////
2070
////  To Do:                                                      ////
2071
////   - add LFSR with more taps                                  ////
2072
////                                                              ////
2073
////  Author(s):                                                  ////
2074
////      - Michael Unneback, unneback@opencores.org              ////
2075
////        ORSoC AB                                              ////
2076
////                                                              ////
2077
//////////////////////////////////////////////////////////////////////
2078
////                                                              ////
2079
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2080
////                                                              ////
2081
//// This source file may be used and distributed without         ////
2082
//// restriction provided that this copyright statement is not    ////
2083
//// removed from the file and that any derivative work contains  ////
2084
//// the original copyright notice and the associated disclaimer. ////
2085
////                                                              ////
2086
//// This source file is free software; you can redistribute it   ////
2087
//// and/or modify it under the terms of the GNU Lesser General   ////
2088
//// Public License as published by the Free Software Foundation; ////
2089
//// either version 2.1 of the License, or (at your option) any   ////
2090
//// later version.                                               ////
2091
////                                                              ////
2092
//// This source is distributed in the hope that it will be       ////
2093
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2094
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2095
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2096
//// details.                                                     ////
2097
////                                                              ////
2098
//// You should have received a copy of the GNU Lesser General    ////
2099
//// Public License along with this source; if not, download it   ////
2100
//// from http://www.opencores.org/lgpl.shtml                     ////
2101
////                                                              ////
2102
//////////////////////////////////////////////////////////////////////
2103
 
2104 6 unneback
// LFSR counter
2105
 
2106 40 unneback
`define MODULE cnt_lfsr_zq
2107
module `BASE`MODULE (
2108
`undef MODULE
2109
 zq, rst, clk);
2110
 
2111 6 unneback
   parameter length = 4;
2112
   output reg zq;
2113
   input rst;
2114
   input clk;
2115
 
2116
   parameter clear_value = 0;
2117
   parameter set_value = 1;
2118
   parameter wrap_value = 8;
2119
   parameter level1_value = 15;
2120
 
2121
   reg  [length:1] qi;
2122
   reg lfsr_fb;
2123
   wire [length:1] q_next;
2124
   reg [32:1] polynom;
2125
   integer i;
2126
 
2127
   always @ (qi)
2128
   begin
2129
        case (length)
2130
         2: polynom = 32'b11;                               // 0x3
2131
         3: polynom = 32'b110;                              // 0x6
2132
         4: polynom = 32'b1100;                             // 0xC
2133
         5: polynom = 32'b10100;                            // 0x14
2134
         6: polynom = 32'b110000;                           // 0x30
2135
         7: polynom = 32'b1100000;                          // 0x60
2136
         8: polynom = 32'b10111000;                         // 0xb8
2137
         9: polynom = 32'b100010000;                        // 0x110
2138
        10: polynom = 32'b1001000000;                       // 0x240
2139
        11: polynom = 32'b10100000000;                      // 0x500
2140
        12: polynom = 32'b100000101001;                     // 0x829
2141
        13: polynom = 32'b1000000001100;                    // 0x100C
2142
        14: polynom = 32'b10000000010101;                   // 0x2015
2143
        15: polynom = 32'b110000000000000;                  // 0x6000
2144
        16: polynom = 32'b1101000000001000;                 // 0xD008
2145
        17: polynom = 32'b10010000000000000;                // 0x12000
2146
        18: polynom = 32'b100000010000000000;               // 0x20400
2147
        19: polynom = 32'b1000000000000100011;              // 0x40023
2148 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2149 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2150
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2151
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2152
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2153
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2154
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2155
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2156
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2157
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2158
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2159
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2160
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2161
        default: polynom = 32'b0;
2162
        endcase
2163
        lfsr_fb = qi[length];
2164
        for (i=length-1; i>=1; i=i-1) begin
2165
            if (polynom[i])
2166
                lfsr_fb = lfsr_fb  ~^ qi[i];
2167
        end
2168
    end
2169
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2170
 
2171
   always @ (posedge clk or posedge rst)
2172
     if (rst)
2173
       qi <= {length{1'b0}};
2174
     else
2175
       qi <= q_next;
2176
 
2177
 
2178
 
2179
   always @ (posedge clk or posedge rst)
2180
     if (rst)
2181
       zq <= 1'b1;
2182
     else
2183
       zq <= q_next == {length{1'b0}};
2184
endmodule
2185 40 unneback
`endif
2186
`ifdef CNT_LFSR_CE_ZQ
2187 6 unneback
//////////////////////////////////////////////////////////////////////
2188
////                                                              ////
2189
////  Versatile counter                                           ////
2190
////                                                              ////
2191
////  Description                                                 ////
2192
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2193
////  counter                                                     ////
2194
////                                                              ////
2195
////  To Do:                                                      ////
2196
////   - add LFSR with more taps                                  ////
2197
////                                                              ////
2198
////  Author(s):                                                  ////
2199
////      - Michael Unneback, unneback@opencores.org              ////
2200
////        ORSoC AB                                              ////
2201
////                                                              ////
2202
//////////////////////////////////////////////////////////////////////
2203
////                                                              ////
2204
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2205
////                                                              ////
2206
//// This source file may be used and distributed without         ////
2207
//// restriction provided that this copyright statement is not    ////
2208
//// removed from the file and that any derivative work contains  ////
2209
//// the original copyright notice and the associated disclaimer. ////
2210
////                                                              ////
2211
//// This source file is free software; you can redistribute it   ////
2212
//// and/or modify it under the terms of the GNU Lesser General   ////
2213
//// Public License as published by the Free Software Foundation; ////
2214
//// either version 2.1 of the License, or (at your option) any   ////
2215
//// later version.                                               ////
2216
////                                                              ////
2217
//// This source is distributed in the hope that it will be       ////
2218
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2219
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2220
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2221
//// details.                                                     ////
2222
////                                                              ////
2223
//// You should have received a copy of the GNU Lesser General    ////
2224
//// Public License along with this source; if not, download it   ////
2225
//// from http://www.opencores.org/lgpl.shtml                     ////
2226
////                                                              ////
2227
//////////////////////////////////////////////////////////////////////
2228
 
2229
// LFSR counter
2230
 
2231 40 unneback
`define MODULE cnt_lfsr_ce_zq
2232
module `BASE`MODULE (
2233
`undef MODULE
2234
 cke, zq, rst, clk);
2235
 
2236 6 unneback
   parameter length = 4;
2237
   input cke;
2238
   output reg zq;
2239
   input rst;
2240
   input clk;
2241
 
2242
   parameter clear_value = 0;
2243
   parameter set_value = 1;
2244
   parameter wrap_value = 8;
2245
   parameter level1_value = 15;
2246
 
2247
   reg  [length:1] qi;
2248
   reg lfsr_fb;
2249
   wire [length:1] q_next;
2250
   reg [32:1] polynom;
2251
   integer i;
2252
 
2253
   always @ (qi)
2254
   begin
2255
        case (length)
2256
         2: polynom = 32'b11;                               // 0x3
2257
         3: polynom = 32'b110;                              // 0x6
2258
         4: polynom = 32'b1100;                             // 0xC
2259
         5: polynom = 32'b10100;                            // 0x14
2260
         6: polynom = 32'b110000;                           // 0x30
2261
         7: polynom = 32'b1100000;                          // 0x60
2262
         8: polynom = 32'b10111000;                         // 0xb8
2263
         9: polynom = 32'b100010000;                        // 0x110
2264
        10: polynom = 32'b1001000000;                       // 0x240
2265
        11: polynom = 32'b10100000000;                      // 0x500
2266
        12: polynom = 32'b100000101001;                     // 0x829
2267
        13: polynom = 32'b1000000001100;                    // 0x100C
2268
        14: polynom = 32'b10000000010101;                   // 0x2015
2269
        15: polynom = 32'b110000000000000;                  // 0x6000
2270
        16: polynom = 32'b1101000000001000;                 // 0xD008
2271
        17: polynom = 32'b10010000000000000;                // 0x12000
2272
        18: polynom = 32'b100000010000000000;               // 0x20400
2273
        19: polynom = 32'b1000000000000100011;              // 0x40023
2274 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2275 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2276
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2277
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2278
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2279
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2280
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2281
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2282
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2283
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2284
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2285
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2286
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2287
        default: polynom = 32'b0;
2288
        endcase
2289
        lfsr_fb = qi[length];
2290
        for (i=length-1; i>=1; i=i-1) begin
2291
            if (polynom[i])
2292
                lfsr_fb = lfsr_fb  ~^ qi[i];
2293
        end
2294
    end
2295
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2296
 
2297
   always @ (posedge clk or posedge rst)
2298
     if (rst)
2299
       qi <= {length{1'b0}};
2300
     else
2301
     if (cke)
2302
       qi <= q_next;
2303
 
2304
 
2305
 
2306
   always @ (posedge clk or posedge rst)
2307
     if (rst)
2308
       zq <= 1'b1;
2309
     else
2310
     if (cke)
2311
       zq <= q_next == {length{1'b0}};
2312
endmodule
2313 40 unneback
`endif
2314
`ifdef CNT_LFSR_CE_Q
2315 6 unneback
//////////////////////////////////////////////////////////////////////
2316
////                                                              ////
2317
////  Versatile counter                                           ////
2318
////                                                              ////
2319
////  Description                                                 ////
2320
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2321
////  counter                                                     ////
2322
////                                                              ////
2323
////  To Do:                                                      ////
2324
////   - add LFSR with more taps                                  ////
2325
////                                                              ////
2326
////  Author(s):                                                  ////
2327
////      - Michael Unneback, unneback@opencores.org              ////
2328
////        ORSoC AB                                              ////
2329
////                                                              ////
2330
//////////////////////////////////////////////////////////////////////
2331
////                                                              ////
2332
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2333
////                                                              ////
2334
//// This source file may be used and distributed without         ////
2335
//// restriction provided that this copyright statement is not    ////
2336
//// removed from the file and that any derivative work contains  ////
2337
//// the original copyright notice and the associated disclaimer. ////
2338
////                                                              ////
2339
//// This source file is free software; you can redistribute it   ////
2340
//// and/or modify it under the terms of the GNU Lesser General   ////
2341
//// Public License as published by the Free Software Foundation; ////
2342
//// either version 2.1 of the License, or (at your option) any   ////
2343
//// later version.                                               ////
2344
////                                                              ////
2345
//// This source is distributed in the hope that it will be       ////
2346
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2347
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2348
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2349
//// details.                                                     ////
2350
////                                                              ////
2351
//// You should have received a copy of the GNU Lesser General    ////
2352
//// Public License along with this source; if not, download it   ////
2353
//// from http://www.opencores.org/lgpl.shtml                     ////
2354
////                                                              ////
2355
//////////////////////////////////////////////////////////////////////
2356 22 unneback
 
2357
// LFSR counter
2358 27 unneback
 
2359 40 unneback
`define MODULE cnt_lfsr_ce_q
2360
module `BASE`MODULE (
2361
`undef MODULE
2362
 cke, q, rst, clk);
2363
 
2364 27 unneback
   parameter length = 4;
2365
   input cke;
2366
   output [length:1] q;
2367
   input rst;
2368
   input clk;
2369
 
2370
   parameter clear_value = 0;
2371
   parameter set_value = 1;
2372
   parameter wrap_value = 8;
2373
   parameter level1_value = 15;
2374
 
2375
   reg  [length:1] qi;
2376
   reg lfsr_fb;
2377
   wire [length:1] q_next;
2378
   reg [32:1] polynom;
2379
   integer i;
2380
 
2381
   always @ (qi)
2382
   begin
2383
        case (length)
2384
         2: polynom = 32'b11;                               // 0x3
2385
         3: polynom = 32'b110;                              // 0x6
2386
         4: polynom = 32'b1100;                             // 0xC
2387
         5: polynom = 32'b10100;                            // 0x14
2388
         6: polynom = 32'b110000;                           // 0x30
2389
         7: polynom = 32'b1100000;                          // 0x60
2390
         8: polynom = 32'b10111000;                         // 0xb8
2391
         9: polynom = 32'b100010000;                        // 0x110
2392
        10: polynom = 32'b1001000000;                       // 0x240
2393
        11: polynom = 32'b10100000000;                      // 0x500
2394
        12: polynom = 32'b100000101001;                     // 0x829
2395
        13: polynom = 32'b1000000001100;                    // 0x100C
2396
        14: polynom = 32'b10000000010101;                   // 0x2015
2397
        15: polynom = 32'b110000000000000;                  // 0x6000
2398
        16: polynom = 32'b1101000000001000;                 // 0xD008
2399
        17: polynom = 32'b10010000000000000;                // 0x12000
2400
        18: polynom = 32'b100000010000000000;               // 0x20400
2401
        19: polynom = 32'b1000000000000100011;              // 0x40023
2402 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2403 27 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2404
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2405
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2406
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2407
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2408
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2409
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2410
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2411
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2412
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2413
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2414
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2415
        default: polynom = 32'b0;
2416
        endcase
2417
        lfsr_fb = qi[length];
2418
        for (i=length-1; i>=1; i=i-1) begin
2419
            if (polynom[i])
2420
                lfsr_fb = lfsr_fb  ~^ qi[i];
2421
        end
2422
    end
2423
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2424
 
2425
   always @ (posedge clk or posedge rst)
2426
     if (rst)
2427
       qi <= {length{1'b0}};
2428
     else
2429
     if (cke)
2430
       qi <= q_next;
2431
 
2432
   assign q = qi;
2433
 
2434
endmodule
2435 40 unneback
`endif
2436
`ifdef CNT_LFSR_CE_CLEAR_Q
2437 27 unneback
//////////////////////////////////////////////////////////////////////
2438
////                                                              ////
2439
////  Versatile counter                                           ////
2440
////                                                              ////
2441
////  Description                                                 ////
2442
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2443
////  counter                                                     ////
2444
////                                                              ////
2445
////  To Do:                                                      ////
2446
////   - add LFSR with more taps                                  ////
2447
////                                                              ////
2448
////  Author(s):                                                  ////
2449
////      - Michael Unneback, unneback@opencores.org              ////
2450
////        ORSoC AB                                              ////
2451
////                                                              ////
2452
//////////////////////////////////////////////////////////////////////
2453
////                                                              ////
2454
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2455
////                                                              ////
2456
//// This source file may be used and distributed without         ////
2457
//// restriction provided that this copyright statement is not    ////
2458
//// removed from the file and that any derivative work contains  ////
2459
//// the original copyright notice and the associated disclaimer. ////
2460
////                                                              ////
2461
//// This source file is free software; you can redistribute it   ////
2462
//// and/or modify it under the terms of the GNU Lesser General   ////
2463
//// Public License as published by the Free Software Foundation; ////
2464
//// either version 2.1 of the License, or (at your option) any   ////
2465
//// later version.                                               ////
2466
////                                                              ////
2467
//// This source is distributed in the hope that it will be       ////
2468
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2469
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2470
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2471
//// details.                                                     ////
2472
////                                                              ////
2473
//// You should have received a copy of the GNU Lesser General    ////
2474
//// Public License along with this source; if not, download it   ////
2475
//// from http://www.opencores.org/lgpl.shtml                     ////
2476
////                                                              ////
2477
//////////////////////////////////////////////////////////////////////
2478
 
2479
// LFSR counter
2480
 
2481 40 unneback
`define MODULE cnt_lfsr_ce_clear_q
2482
module `BASE`MODULE (
2483
`undef MODULE
2484
 clear, cke, q, rst, clk);
2485
 
2486 27 unneback
   parameter length = 4;
2487
   input clear;
2488
   input cke;
2489
   output [length:1] q;
2490
   input rst;
2491
   input clk;
2492
 
2493
   parameter clear_value = 0;
2494
   parameter set_value = 1;
2495
   parameter wrap_value = 8;
2496
   parameter level1_value = 15;
2497
 
2498
   reg  [length:1] qi;
2499
   reg lfsr_fb;
2500
   wire [length:1] q_next;
2501
   reg [32:1] polynom;
2502
   integer i;
2503
 
2504
   always @ (qi)
2505
   begin
2506
        case (length)
2507
         2: polynom = 32'b11;                               // 0x3
2508
         3: polynom = 32'b110;                              // 0x6
2509
         4: polynom = 32'b1100;                             // 0xC
2510
         5: polynom = 32'b10100;                            // 0x14
2511
         6: polynom = 32'b110000;                           // 0x30
2512
         7: polynom = 32'b1100000;                          // 0x60
2513
         8: polynom = 32'b10111000;                         // 0xb8
2514
         9: polynom = 32'b100010000;                        // 0x110
2515
        10: polynom = 32'b1001000000;                       // 0x240
2516
        11: polynom = 32'b10100000000;                      // 0x500
2517
        12: polynom = 32'b100000101001;                     // 0x829
2518
        13: polynom = 32'b1000000001100;                    // 0x100C
2519
        14: polynom = 32'b10000000010101;                   // 0x2015
2520
        15: polynom = 32'b110000000000000;                  // 0x6000
2521
        16: polynom = 32'b1101000000001000;                 // 0xD008
2522
        17: polynom = 32'b10010000000000000;                // 0x12000
2523
        18: polynom = 32'b100000010000000000;               // 0x20400
2524
        19: polynom = 32'b1000000000000100011;              // 0x40023
2525 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2526 27 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2527
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2528
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2529
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2530
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2531
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2532
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2533
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2534
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2535
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2536
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2537
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2538
        default: polynom = 32'b0;
2539
        endcase
2540
        lfsr_fb = qi[length];
2541
        for (i=length-1; i>=1; i=i-1) begin
2542
            if (polynom[i])
2543
                lfsr_fb = lfsr_fb  ~^ qi[i];
2544
        end
2545
    end
2546
   assign q_next =  clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2547
 
2548
   always @ (posedge clk or posedge rst)
2549
     if (rst)
2550
       qi <= {length{1'b0}};
2551
     else
2552
     if (cke)
2553
       qi <= q_next;
2554
 
2555
   assign q = qi;
2556
 
2557
endmodule
2558 40 unneback
`endif
2559
`ifdef CNT_LFSR_CE_Q_ZQ
2560 27 unneback
//////////////////////////////////////////////////////////////////////
2561
////                                                              ////
2562
////  Versatile counter                                           ////
2563
////                                                              ////
2564
////  Description                                                 ////
2565
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2566
////  counter                                                     ////
2567
////                                                              ////
2568
////  To Do:                                                      ////
2569
////   - add LFSR with more taps                                  ////
2570
////                                                              ////
2571
////  Author(s):                                                  ////
2572
////      - Michael Unneback, unneback@opencores.org              ////
2573
////        ORSoC AB                                              ////
2574
////                                                              ////
2575
//////////////////////////////////////////////////////////////////////
2576
////                                                              ////
2577
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2578
////                                                              ////
2579
//// This source file may be used and distributed without         ////
2580
//// restriction provided that this copyright statement is not    ////
2581
//// removed from the file and that any derivative work contains  ////
2582
//// the original copyright notice and the associated disclaimer. ////
2583
////                                                              ////
2584
//// This source file is free software; you can redistribute it   ////
2585
//// and/or modify it under the terms of the GNU Lesser General   ////
2586
//// Public License as published by the Free Software Foundation; ////
2587
//// either version 2.1 of the License, or (at your option) any   ////
2588
//// later version.                                               ////
2589
////                                                              ////
2590
//// This source is distributed in the hope that it will be       ////
2591
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2592
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2593
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2594
//// details.                                                     ////
2595
////                                                              ////
2596
//// You should have received a copy of the GNU Lesser General    ////
2597
//// Public License along with this source; if not, download it   ////
2598
//// from http://www.opencores.org/lgpl.shtml                     ////
2599
////                                                              ////
2600
//////////////////////////////////////////////////////////////////////
2601
 
2602
// LFSR counter
2603 22 unneback
 
2604 40 unneback
`define MODULE cnt_lfsr_ce_q_zq
2605
module `BASE`MODULE (
2606
`undef MODULE
2607
 cke, q, zq, rst, clk);
2608
 
2609 22 unneback
   parameter length = 4;
2610
   input cke;
2611
   output [length:1] q;
2612
   output reg zq;
2613
   input rst;
2614
   input clk;
2615
 
2616
   parameter clear_value = 0;
2617
   parameter set_value = 1;
2618
   parameter wrap_value = 8;
2619
   parameter level1_value = 15;
2620
 
2621
   reg  [length:1] qi;
2622
   reg lfsr_fb;
2623
   wire [length:1] q_next;
2624
   reg [32:1] polynom;
2625
   integer i;
2626
 
2627
   always @ (qi)
2628
   begin
2629
        case (length)
2630
         2: polynom = 32'b11;                               // 0x3
2631
         3: polynom = 32'b110;                              // 0x6
2632
         4: polynom = 32'b1100;                             // 0xC
2633
         5: polynom = 32'b10100;                            // 0x14
2634
         6: polynom = 32'b110000;                           // 0x30
2635
         7: polynom = 32'b1100000;                          // 0x60
2636
         8: polynom = 32'b10111000;                         // 0xb8
2637
         9: polynom = 32'b100010000;                        // 0x110
2638
        10: polynom = 32'b1001000000;                       // 0x240
2639
        11: polynom = 32'b10100000000;                      // 0x500
2640
        12: polynom = 32'b100000101001;                     // 0x829
2641
        13: polynom = 32'b1000000001100;                    // 0x100C
2642
        14: polynom = 32'b10000000010101;                   // 0x2015
2643
        15: polynom = 32'b110000000000000;                  // 0x6000
2644
        16: polynom = 32'b1101000000001000;                 // 0xD008
2645
        17: polynom = 32'b10010000000000000;                // 0x12000
2646
        18: polynom = 32'b100000010000000000;               // 0x20400
2647
        19: polynom = 32'b1000000000000100011;              // 0x40023
2648 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2649 22 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2650
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2651
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2652
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2653
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2654
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2655
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2656
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2657
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2658
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2659
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2660
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2661
        default: polynom = 32'b0;
2662
        endcase
2663
        lfsr_fb = qi[length];
2664
        for (i=length-1; i>=1; i=i-1) begin
2665
            if (polynom[i])
2666
                lfsr_fb = lfsr_fb  ~^ qi[i];
2667
        end
2668
    end
2669
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2670
 
2671
   always @ (posedge clk or posedge rst)
2672
     if (rst)
2673
       qi <= {length{1'b0}};
2674
     else
2675
     if (cke)
2676
       qi <= q_next;
2677
 
2678
   assign q = qi;
2679
 
2680
 
2681
   always @ (posedge clk or posedge rst)
2682
     if (rst)
2683
       zq <= 1'b1;
2684
     else
2685
     if (cke)
2686
       zq <= q_next == {length{1'b0}};
2687
endmodule
2688 40 unneback
`endif
2689
`ifdef CNT_LFSR_CE_REW_L1
2690 22 unneback
//////////////////////////////////////////////////////////////////////
2691
////                                                              ////
2692
////  Versatile counter                                           ////
2693
////                                                              ////
2694
////  Description                                                 ////
2695
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2696
////  counter                                                     ////
2697
////                                                              ////
2698
////  To Do:                                                      ////
2699
////   - add LFSR with more taps                                  ////
2700
////                                                              ////
2701
////  Author(s):                                                  ////
2702
////      - Michael Unneback, unneback@opencores.org              ////
2703
////        ORSoC AB                                              ////
2704
////                                                              ////
2705
//////////////////////////////////////////////////////////////////////
2706
////                                                              ////
2707
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2708
////                                                              ////
2709
//// This source file may be used and distributed without         ////
2710
//// restriction provided that this copyright statement is not    ////
2711
//// removed from the file and that any derivative work contains  ////
2712
//// the original copyright notice and the associated disclaimer. ////
2713
////                                                              ////
2714
//// This source file is free software; you can redistribute it   ////
2715
//// and/or modify it under the terms of the GNU Lesser General   ////
2716
//// Public License as published by the Free Software Foundation; ////
2717
//// either version 2.1 of the License, or (at your option) any   ////
2718
//// later version.                                               ////
2719
////                                                              ////
2720
//// This source is distributed in the hope that it will be       ////
2721
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2722
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2723
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2724
//// details.                                                     ////
2725
////                                                              ////
2726
//// You should have received a copy of the GNU Lesser General    ////
2727
//// Public License along with this source; if not, download it   ////
2728
//// from http://www.opencores.org/lgpl.shtml                     ////
2729
////                                                              ////
2730
//////////////////////////////////////////////////////////////////////
2731 6 unneback
 
2732
// LFSR counter
2733
 
2734 40 unneback
`define MODULE cnt_lfsr_ce_rew_l1
2735
module `BASE`MODULE (
2736
`undef MODULE
2737
 cke, rew, level1, rst, clk);
2738
 
2739 6 unneback
   parameter length = 4;
2740
   input cke;
2741
   input rew;
2742
   output reg level1;
2743
   input rst;
2744
   input clk;
2745
 
2746
   parameter clear_value = 0;
2747
   parameter set_value = 1;
2748
   parameter wrap_value = 8;
2749
   parameter level1_value = 15;
2750
 
2751 29 unneback
   wire clear;
2752 30 unneback
   assign clear = 1'b0;
2753 6 unneback
   reg  [length:1] qi;
2754
   reg lfsr_fb, lfsr_fb_rew;
2755
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2756
   reg [32:1] polynom_rew;
2757
   integer j;
2758
   reg [32:1] polynom;
2759
   integer i;
2760
 
2761
   always @ (qi)
2762
   begin
2763
        case (length)
2764
         2: polynom = 32'b11;                               // 0x3
2765
         3: polynom = 32'b110;                              // 0x6
2766
         4: polynom = 32'b1100;                             // 0xC
2767
         5: polynom = 32'b10100;                            // 0x14
2768
         6: polynom = 32'b110000;                           // 0x30
2769
         7: polynom = 32'b1100000;                          // 0x60
2770
         8: polynom = 32'b10111000;                         // 0xb8
2771
         9: polynom = 32'b100010000;                        // 0x110
2772
        10: polynom = 32'b1001000000;                       // 0x240
2773
        11: polynom = 32'b10100000000;                      // 0x500
2774
        12: polynom = 32'b100000101001;                     // 0x829
2775
        13: polynom = 32'b1000000001100;                    // 0x100C
2776
        14: polynom = 32'b10000000010101;                   // 0x2015
2777
        15: polynom = 32'b110000000000000;                  // 0x6000
2778
        16: polynom = 32'b1101000000001000;                 // 0xD008
2779
        17: polynom = 32'b10010000000000000;                // 0x12000
2780
        18: polynom = 32'b100000010000000000;               // 0x20400
2781
        19: polynom = 32'b1000000000000100011;              // 0x40023
2782 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2783 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2784
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2785
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2786
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2787
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2788
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2789
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2790
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2791
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2792
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2793
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2794
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2795
        default: polynom = 32'b0;
2796
        endcase
2797
        lfsr_fb = qi[length];
2798
        for (i=length-1; i>=1; i=i-1) begin
2799
            if (polynom[i])
2800
                lfsr_fb = lfsr_fb  ~^ qi[i];
2801
        end
2802
    end
2803
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2804
   always @ (qi)
2805
   begin
2806
        case (length)
2807
         2: polynom_rew = 32'b11;
2808
         3: polynom_rew = 32'b110;
2809
         4: polynom_rew = 32'b1100;
2810
         5: polynom_rew = 32'b10100;
2811
         6: polynom_rew = 32'b110000;
2812
         7: polynom_rew = 32'b1100000;
2813
         8: polynom_rew = 32'b10111000;
2814
         9: polynom_rew = 32'b100010000;
2815
        10: polynom_rew = 32'b1001000000;
2816
        11: polynom_rew = 32'b10100000000;
2817
        12: polynom_rew = 32'b100000101001;
2818
        13: polynom_rew = 32'b1000000001100;
2819
        14: polynom_rew = 32'b10000000010101;
2820
        15: polynom_rew = 32'b110000000000000;
2821
        16: polynom_rew = 32'b1101000000001000;
2822
        17: polynom_rew = 32'b10010000000000000;
2823
        18: polynom_rew = 32'b100000010000000000;
2824
        19: polynom_rew = 32'b1000000000000100011;
2825
        20: polynom_rew = 32'b10000010000000000000;
2826
        21: polynom_rew = 32'b101000000000000000000;
2827
        22: polynom_rew = 32'b1100000000000000000000;
2828
        23: polynom_rew = 32'b10000100000000000000000;
2829
        24: polynom_rew = 32'b111000010000000000000000;
2830
        25: polynom_rew = 32'b1001000000000000000000000;
2831
        26: polynom_rew = 32'b10000000000000000000100011;
2832
        27: polynom_rew = 32'b100000000000000000000010011;
2833
        28: polynom_rew = 32'b1100100000000000000000000000;
2834
        29: polynom_rew = 32'b10100000000000000000000000000;
2835
        30: polynom_rew = 32'b100000000000000000000000101001;
2836
        31: polynom_rew = 32'b1001000000000000000000000000000;
2837
        32: polynom_rew = 32'b10000000001000000000000000000011;
2838
        default: polynom_rew = 32'b0;
2839
        endcase
2840
        // rotate left
2841
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
2842
        lfsr_fb_rew = qi[length];
2843
        for (i=length-1; i>=1; i=i-1) begin
2844
            if (polynom_rew[i])
2845
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
2846
        end
2847
    end
2848
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
2849
   assign q_next = rew ? q_next_rew : q_next_fw;
2850
 
2851
   always @ (posedge clk or posedge rst)
2852
     if (rst)
2853
       qi <= {length{1'b0}};
2854
     else
2855
     if (cke)
2856
       qi <= q_next;
2857
 
2858
 
2859
 
2860
    always @ (posedge clk or posedge rst)
2861
    if (rst)
2862
        level1 <= 1'b0;
2863
    else
2864
    if (cke)
2865 29 unneback
    if (clear)
2866
        level1 <= 1'b0;
2867
    else if (q_next == level1_value)
2868 6 unneback
        level1 <= 1'b1;
2869
    else if (qi == level1_value & rew)
2870
        level1 <= 1'b0;
2871
endmodule
2872 40 unneback
`endif
2873
`ifdef CNT_GRAY
2874 6 unneback
//////////////////////////////////////////////////////////////////////
2875
////                                                              ////
2876
////  Versatile counter                                           ////
2877
////                                                              ////
2878
////  Description                                                 ////
2879
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2880
////  counter                                                     ////
2881
////                                                              ////
2882
////  To Do:                                                      ////
2883
////   - add LFSR with more taps                                  ////
2884
////                                                              ////
2885
////  Author(s):                                                  ////
2886
////      - Michael Unneback, unneback@opencores.org              ////
2887
////        ORSoC AB                                              ////
2888
////                                                              ////
2889
//////////////////////////////////////////////////////////////////////
2890
////                                                              ////
2891
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2892
////                                                              ////
2893
//// This source file may be used and distributed without         ////
2894
//// restriction provided that this copyright statement is not    ////
2895
//// removed from the file and that any derivative work contains  ////
2896
//// the original copyright notice and the associated disclaimer. ////
2897
////                                                              ////
2898
//// This source file is free software; you can redistribute it   ////
2899
//// and/or modify it under the terms of the GNU Lesser General   ////
2900
//// Public License as published by the Free Software Foundation; ////
2901
//// either version 2.1 of the License, or (at your option) any   ////
2902
//// later version.                                               ////
2903
////                                                              ////
2904
//// This source is distributed in the hope that it will be       ////
2905
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2906
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2907
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2908
//// details.                                                     ////
2909
////                                                              ////
2910
//// You should have received a copy of the GNU Lesser General    ////
2911
//// Public License along with this source; if not, download it   ////
2912
//// from http://www.opencores.org/lgpl.shtml                     ////
2913
////                                                              ////
2914
//////////////////////////////////////////////////////////////////////
2915
 
2916
// GRAY counter
2917
 
2918 40 unneback
`define MODULE cnt_gray
2919
module `BASE`MODULE (
2920
`undef MODULE
2921
 q, rst, clk);
2922
 
2923 6 unneback
   parameter length = 4;
2924
   output reg [length:1] q;
2925
   input rst;
2926
   input clk;
2927
 
2928
   parameter clear_value = 0;
2929
   parameter set_value = 1;
2930
   parameter wrap_value = 8;
2931
   parameter level1_value = 15;
2932
 
2933
   reg  [length:1] qi;
2934
   wire [length:1] q_next;
2935
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2936
 
2937
   always @ (posedge clk or posedge rst)
2938
     if (rst)
2939
       qi <= {length{1'b0}};
2940
     else
2941
       qi <= q_next;
2942
 
2943
   always @ (posedge clk or posedge rst)
2944
     if (rst)
2945
       q <= {length{1'b0}};
2946
     else
2947
         q <= (q_next>>1) ^ q_next;
2948
 
2949
endmodule
2950 40 unneback
`endif
2951
`ifdef CNT_GRAY_CE
2952 6 unneback
//////////////////////////////////////////////////////////////////////
2953
////                                                              ////
2954
////  Versatile counter                                           ////
2955
////                                                              ////
2956
////  Description                                                 ////
2957
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2958
////  counter                                                     ////
2959
////                                                              ////
2960
////  To Do:                                                      ////
2961
////   - add LFSR with more taps                                  ////
2962
////                                                              ////
2963
////  Author(s):                                                  ////
2964
////      - Michael Unneback, unneback@opencores.org              ////
2965
////        ORSoC AB                                              ////
2966
////                                                              ////
2967
//////////////////////////////////////////////////////////////////////
2968
////                                                              ////
2969
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2970
////                                                              ////
2971
//// This source file may be used and distributed without         ////
2972
//// restriction provided that this copyright statement is not    ////
2973
//// removed from the file and that any derivative work contains  ////
2974
//// the original copyright notice and the associated disclaimer. ////
2975
////                                                              ////
2976
//// This source file is free software; you can redistribute it   ////
2977
//// and/or modify it under the terms of the GNU Lesser General   ////
2978
//// Public License as published by the Free Software Foundation; ////
2979
//// either version 2.1 of the License, or (at your option) any   ////
2980
//// later version.                                               ////
2981
////                                                              ////
2982
//// This source is distributed in the hope that it will be       ////
2983
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2984
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2985
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2986
//// details.                                                     ////
2987
////                                                              ////
2988
//// You should have received a copy of the GNU Lesser General    ////
2989
//// Public License along with this source; if not, download it   ////
2990
//// from http://www.opencores.org/lgpl.shtml                     ////
2991
////                                                              ////
2992
//////////////////////////////////////////////////////////////////////
2993
 
2994
// GRAY counter
2995
 
2996 40 unneback
`define MODULE cnt_gray_ce
2997
module `BASE`MODULE (
2998
`undef MODULE
2999
 cke, q, rst, clk);
3000
 
3001 6 unneback
   parameter length = 4;
3002
   input cke;
3003
   output reg [length:1] q;
3004
   input rst;
3005
   input clk;
3006
 
3007
   parameter clear_value = 0;
3008
   parameter set_value = 1;
3009
   parameter wrap_value = 8;
3010
   parameter level1_value = 15;
3011
 
3012
   reg  [length:1] qi;
3013
   wire [length:1] q_next;
3014
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3015
 
3016
   always @ (posedge clk or posedge rst)
3017
     if (rst)
3018
       qi <= {length{1'b0}};
3019
     else
3020
     if (cke)
3021
       qi <= q_next;
3022
 
3023
   always @ (posedge clk or posedge rst)
3024
     if (rst)
3025
       q <= {length{1'b0}};
3026
     else
3027
       if (cke)
3028
         q <= (q_next>>1) ^ q_next;
3029
 
3030
endmodule
3031 40 unneback
`endif
3032
`ifdef CNT_GRAY_CE_BIN
3033 6 unneback
//////////////////////////////////////////////////////////////////////
3034
////                                                              ////
3035
////  Versatile counter                                           ////
3036
////                                                              ////
3037
////  Description                                                 ////
3038
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3039
////  counter                                                     ////
3040
////                                                              ////
3041
////  To Do:                                                      ////
3042
////   - add LFSR with more taps                                  ////
3043
////                                                              ////
3044
////  Author(s):                                                  ////
3045
////      - Michael Unneback, unneback@opencores.org              ////
3046
////        ORSoC AB                                              ////
3047
////                                                              ////
3048
//////////////////////////////////////////////////////////////////////
3049
////                                                              ////
3050
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3051
////                                                              ////
3052
//// This source file may be used and distributed without         ////
3053
//// restriction provided that this copyright statement is not    ////
3054
//// removed from the file and that any derivative work contains  ////
3055
//// the original copyright notice and the associated disclaimer. ////
3056
////                                                              ////
3057
//// This source file is free software; you can redistribute it   ////
3058
//// and/or modify it under the terms of the GNU Lesser General   ////
3059
//// Public License as published by the Free Software Foundation; ////
3060
//// either version 2.1 of the License, or (at your option) any   ////
3061
//// later version.                                               ////
3062
////                                                              ////
3063
//// This source is distributed in the hope that it will be       ////
3064
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3065
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3066
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3067
//// details.                                                     ////
3068
////                                                              ////
3069
//// You should have received a copy of the GNU Lesser General    ////
3070
//// Public License along with this source; if not, download it   ////
3071
//// from http://www.opencores.org/lgpl.shtml                     ////
3072
////                                                              ////
3073
//////////////////////////////////////////////////////////////////////
3074
 
3075
// GRAY counter
3076
 
3077 40 unneback
`define MODULE cnt_gray_ce_bin
3078
module `BASE`MODULE (
3079
`undef MODULE
3080
 cke, q, q_bin, rst, clk);
3081
 
3082 6 unneback
   parameter length = 4;
3083
   input cke;
3084
   output reg [length:1] q;
3085
   output [length:1] q_bin;
3086
   input rst;
3087
   input clk;
3088
 
3089
   parameter clear_value = 0;
3090
   parameter set_value = 1;
3091
   parameter wrap_value = 8;
3092
   parameter level1_value = 15;
3093
 
3094
   reg  [length:1] qi;
3095
   wire [length:1] q_next;
3096
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3097
 
3098
   always @ (posedge clk or posedge rst)
3099
     if (rst)
3100
       qi <= {length{1'b0}};
3101
     else
3102
     if (cke)
3103
       qi <= q_next;
3104
 
3105
   always @ (posedge clk or posedge rst)
3106
     if (rst)
3107
       q <= {length{1'b0}};
3108
     else
3109
       if (cke)
3110
         q <= (q_next>>1) ^ q_next;
3111
 
3112
   assign q_bin = qi;
3113
 
3114
endmodule
3115 40 unneback
`endif
3116 6 unneback
//////////////////////////////////////////////////////////////////////
3117
////                                                              ////
3118
////  Versatile library, counters                                 ////
3119
////                                                              ////
3120
////  Description                                                 ////
3121
////  counters                                                    ////
3122
////                                                              ////
3123
////                                                              ////
3124
////  To Do:                                                      ////
3125
////   - add more counters                                        ////
3126
////                                                              ////
3127
////  Author(s):                                                  ////
3128
////      - Michael Unneback, unneback@opencores.org              ////
3129
////        ORSoC AB                                              ////
3130
////                                                              ////
3131
//////////////////////////////////////////////////////////////////////
3132
////                                                              ////
3133
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
3134
////                                                              ////
3135
//// This source file may be used and distributed without         ////
3136
//// restriction provided that this copyright statement is not    ////
3137
//// removed from the file and that any derivative work contains  ////
3138
//// the original copyright notice and the associated disclaimer. ////
3139
////                                                              ////
3140
//// This source file is free software; you can redistribute it   ////
3141
//// and/or modify it under the terms of the GNU Lesser General   ////
3142
//// Public License as published by the Free Software Foundation; ////
3143
//// either version 2.1 of the License, or (at your option) any   ////
3144
//// later version.                                               ////
3145
////                                                              ////
3146
//// This source is distributed in the hope that it will be       ////
3147
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3148
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3149
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3150
//// details.                                                     ////
3151
////                                                              ////
3152
//// You should have received a copy of the GNU Lesser General    ////
3153
//// Public License along with this source; if not, download it   ////
3154
//// from http://www.opencores.org/lgpl.shtml                     ////
3155
////                                                              ////
3156
//////////////////////////////////////////////////////////////////////
3157
 
3158 40 unneback
`ifdef CNT_SHREG_WRAP
3159
`define MODULE cnt_shreg_wrap
3160
module `BASE`MODULE ( q, rst, clk);
3161
`undef MODULE
3162 6 unneback
 
3163
   parameter length = 4;
3164
   output reg [0:length-1] q;
3165
   input rst;
3166
   input clk;
3167
 
3168
    always @ (posedge clk or posedge rst)
3169
    if (rst)
3170
        q <= {1'b1,{length-1{1'b0}}};
3171
    else
3172
        q <= {q[length-1],q[0:length-2]};
3173
 
3174
endmodule
3175 40 unneback
`endif
3176 6 unneback
 
3177 40 unneback
`ifdef CNT_SHREG_CE_WRAP
3178
`define MODULE cnt_shreg_ce_wrap
3179
module `BASE`MODULE ( cke, q, rst, clk);
3180
`undef MODULE
3181 6 unneback
 
3182
   parameter length = 4;
3183
   input cke;
3184
   output reg [0:length-1] q;
3185
   input rst;
3186
   input clk;
3187
 
3188
    always @ (posedge clk or posedge rst)
3189
    if (rst)
3190
        q <= {1'b1,{length-1{1'b0}}};
3191
    else
3192
        if (cke)
3193
            q <= {q[length-1],q[0:length-2]};
3194
 
3195
endmodule
3196 40 unneback
`endif
3197 6 unneback
 
3198 40 unneback
`ifdef CNT_SHREG_CE_CLEAR
3199
`define MODULE cnt_shreg_ce_clear
3200
module `BASE`MODULE ( cke, clear, q, rst, clk);
3201
`undef MODULE
3202 6 unneback
 
3203
   parameter length = 4;
3204
   input cke, clear;
3205
   output reg [0:length-1] q;
3206
   input rst;
3207
   input clk;
3208
 
3209
    always @ (posedge clk or posedge rst)
3210
    if (rst)
3211
        q <= {1'b1,{length-1{1'b0}}};
3212
    else
3213
        if (cke)
3214
            if (clear)
3215
                q <= {1'b1,{length-1{1'b0}}};
3216
            else
3217
                q <= q >> 1;
3218
 
3219
endmodule
3220 40 unneback
`endif
3221 6 unneback
 
3222 40 unneback
`ifdef CNT_SHREG_CE_CLEAR_WRAP
3223
`define MODULE cnt_shreg_ce_clear_wrap
3224
module `BASE`MODULE ( cke, clear, q, rst, clk);
3225
`undef MODULE
3226 6 unneback
 
3227
   parameter length = 4;
3228
   input cke, clear;
3229
   output reg [0:length-1] q;
3230
   input rst;
3231
   input clk;
3232
 
3233
    always @ (posedge clk or posedge rst)
3234
    if (rst)
3235
        q <= {1'b1,{length-1{1'b0}}};
3236
    else
3237
        if (cke)
3238
            if (clear)
3239
                q <= {1'b1,{length-1{1'b0}}};
3240
            else
3241
            q <= {q[length-1],q[0:length-2]};
3242
 
3243
endmodule
3244 40 unneback
`endif
3245 6 unneback
//////////////////////////////////////////////////////////////////////
3246
////                                                              ////
3247
////  Versatile library, memories                                 ////
3248
////                                                              ////
3249
////  Description                                                 ////
3250
////  memories                                                    ////
3251
////                                                              ////
3252
////                                                              ////
3253
////  To Do:                                                      ////
3254
////   - add more memory types                                    ////
3255
////                                                              ////
3256
////  Author(s):                                                  ////
3257
////      - Michael Unneback, unneback@opencores.org              ////
3258
////        ORSoC AB                                              ////
3259
////                                                              ////
3260
//////////////////////////////////////////////////////////////////////
3261
////                                                              ////
3262
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
3263
////                                                              ////
3264
//// This source file may be used and distributed without         ////
3265
//// restriction provided that this copyright statement is not    ////
3266
//// removed from the file and that any derivative work contains  ////
3267
//// the original copyright notice and the associated disclaimer. ////
3268
////                                                              ////
3269
//// This source file is free software; you can redistribute it   ////
3270
//// and/or modify it under the terms of the GNU Lesser General   ////
3271
//// Public License as published by the Free Software Foundation; ////
3272
//// either version 2.1 of the License, or (at your option) any   ////
3273
//// later version.                                               ////
3274
////                                                              ////
3275
//// This source is distributed in the hope that it will be       ////
3276
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3277
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3278
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3279
//// details.                                                     ////
3280
////                                                              ////
3281
//// You should have received a copy of the GNU Lesser General    ////
3282
//// Public License along with this source; if not, download it   ////
3283
//// from http://www.opencores.org/lgpl.shtml                     ////
3284
////                                                              ////
3285
//////////////////////////////////////////////////////////////////////
3286
 
3287 40 unneback
`ifdef ROM_INIT
3288 6 unneback
/// ROM
3289 40 unneback
`define MODULE rom_init
3290
module `BASE`MODULE ( adr, q, clk);
3291
`undef MODULE
3292 6 unneback
 
3293 7 unneback
   parameter data_width = 32;
3294
   parameter addr_width = 8;
3295
   input [(addr_width-1):0]       adr;
3296
   output reg [(data_width-1):0] q;
3297
   input                         clk;
3298
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
3299
   parameter memory_file = "vl_rom.vmem";
3300
   initial
3301
     begin
3302
        $readmemh(memory_file, rom);
3303
     end
3304
 
3305
   always @ (posedge clk)
3306
     q <= rom[adr];
3307 6 unneback
 
3308 7 unneback
endmodule
3309 40 unneback
`endif
3310 7 unneback
 
3311 14 unneback
/*
3312 7 unneback
module vl_rom ( adr, q, clk);
3313
 
3314 6 unneback
parameter data_width = 32;
3315
parameter addr_width = 4;
3316
 
3317
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
3318
    {32'h18000000},
3319
    {32'hA8200000},
3320
    {32'hA8200000},
3321
    {32'hA8200000},
3322
    {32'h44003000},
3323
    {32'h15000000},
3324
    {32'h15000000},
3325
    {32'h15000000},
3326
    {32'h15000000},
3327
    {32'h15000000},
3328
    {32'h15000000},
3329
    {32'h15000000},
3330
    {32'h15000000},
3331
    {32'h15000000},
3332
    {32'h15000000},
3333
    {32'h15000000}};
3334
 
3335 7 unneback
input [addr_width-1:0] adr;
3336 6 unneback
output reg [data_width-1:0] q;
3337
input clk;
3338
 
3339
always @ (posedge clk)
3340 7 unneback
    q <= data[adr];
3341 6 unneback
 
3342
endmodule
3343 14 unneback
*/
3344 40 unneback
 
3345
`ifdef RAM
3346
`define MODULE ram
3347 6 unneback
// Single port RAM
3348 40 unneback
module `BASE`MODULE ( d, adr, we, q, clk);
3349
`undef MODULE
3350 6 unneback
 
3351
   parameter data_width = 32;
3352
   parameter addr_width = 8;
3353
   input [(data_width-1):0]      d;
3354
   input [(addr_width-1):0]       adr;
3355
   input                         we;
3356 7 unneback
   output reg [(data_width-1):0] q;
3357 6 unneback
   input                         clk;
3358
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
3359 7 unneback
   parameter init = 0;
3360
   parameter memory_file = "vl_ram.vmem";
3361
   generate if (init) begin : init_mem
3362
   initial
3363
     begin
3364
        $readmemh(memory_file, ram);
3365
     end
3366
   end
3367
   endgenerate
3368
 
3369 6 unneback
   always @ (posedge clk)
3370
   begin
3371
   if (we)
3372
     ram[adr] <= d;
3373
   q <= ram[adr];
3374
   end
3375
 
3376
endmodule
3377 40 unneback
`endif
3378 6 unneback
 
3379 40 unneback
`ifdef RAM_BE
3380
`define MODULE ram_be
3381
module `BASE`MODULE ( d, adr, be, we, q, clk);
3382
`undef MODULE
3383
 
3384 7 unneback
   parameter data_width = 32;
3385
   parameter addr_width = 8;
3386
   input [(data_width-1):0]      d;
3387
   input [(addr_width-1):0]       adr;
3388
   input [(addr_width/4)-1:0]    be;
3389
   input                         we;
3390
   output reg [(data_width-1):0] q;
3391
   input                         clk;
3392
 
3393
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
3394
 
3395
   parameter init = 0;
3396
   parameter memory_file = "vl_ram.vmem";
3397
   generate if (init) begin : init_mem
3398
   initial
3399
     begin
3400
        $readmemh(memory_file, ram);
3401
     end
3402
   end
3403
   endgenerate
3404
 
3405
   genvar i;
3406
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
3407
      always @ (posedge clk)
3408
      if (we & be[i])
3409
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
3410
   end
3411
   endgenerate
3412
 
3413
   always @ (posedge clk)
3414
      q <= ram[adr];
3415
 
3416
endmodule
3417 40 unneback
`endif
3418 7 unneback
 
3419 6 unneback
// Dual port RAM
3420
 
3421
// ACTEL FPGA should not use logic to handle rw collision
3422
`ifdef ACTEL
3423
        `define SYN /*synthesis syn_ramstyle = "no_rw_check"*/
3424
`else
3425
        `define SYN
3426
`endif
3427
 
3428 40 unneback
`ifdef DPRAM_1R1W
3429
`define MODULE dpram_1r1w
3430
module `BASE`MODULE ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
3431
`undef MODULE
3432 6 unneback
   parameter data_width = 32;
3433
   parameter addr_width = 8;
3434
   input [(data_width-1):0]      d_a;
3435
   input [(addr_width-1):0]       adr_a;
3436
   input [(addr_width-1):0]       adr_b;
3437
   input                         we_a;
3438
   output [(data_width-1):0]      q_b;
3439
   input                         clk_a, clk_b;
3440
   reg [(addr_width-1):0]         adr_b_reg;
3441
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
3442 7 unneback
 
3443
   parameter init = 0;
3444
   parameter memory_file = "vl_ram.vmem";
3445
   generate if (init) begin : init_mem
3446
   initial
3447
     begin
3448
        $readmemh(memory_file, ram);
3449
     end
3450
   end
3451
   endgenerate
3452
 
3453 6 unneback
   always @ (posedge clk_a)
3454
   if (we_a)
3455
     ram[adr_a] <= d_a;
3456
   always @ (posedge clk_b)
3457
   adr_b_reg <= adr_b;
3458
   assign q_b = ram[adr_b_reg];
3459 40 unneback
 
3460 6 unneback
endmodule
3461 40 unneback
`endif
3462 6 unneback
 
3463 40 unneback
`ifdef DPRAM_2R1W
3464
`define MODULE dpram_2r1w
3465
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
3466
`undef MODULE
3467
 
3468 6 unneback
   parameter data_width = 32;
3469
   parameter addr_width = 8;
3470
   input [(data_width-1):0]      d_a;
3471
   input [(addr_width-1):0]       adr_a;
3472
   input [(addr_width-1):0]       adr_b;
3473
   input                         we_a;
3474
   output [(data_width-1):0]      q_b;
3475
   output reg [(data_width-1):0] q_a;
3476
   input                         clk_a, clk_b;
3477
   reg [(data_width-1):0]         q_b;
3478
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
3479 7 unneback
 
3480
   parameter init = 0;
3481
   parameter memory_file = "vl_ram.vmem";
3482
   generate if (init) begin : init_mem
3483
   initial
3484
     begin
3485
        $readmemh(memory_file, ram);
3486
     end
3487
   end
3488
   endgenerate
3489
 
3490 6 unneback
   always @ (posedge clk_a)
3491
     begin
3492
        q_a <= ram[adr_a];
3493
        if (we_a)
3494
             ram[adr_a] <= d_a;
3495
     end
3496
   always @ (posedge clk_b)
3497
          q_b <= ram[adr_b];
3498
endmodule
3499 40 unneback
`endif
3500 6 unneback
 
3501 40 unneback
`ifdef DPRAM_2R2W
3502
`define MODULE dpram_2r2w
3503
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
3504
`undef MODULE
3505
 
3506 6 unneback
   parameter data_width = 32;
3507
   parameter addr_width = 8;
3508
   input [(data_width-1):0]      d_a;
3509
   input [(addr_width-1):0]       adr_a;
3510
   input [(addr_width-1):0]       adr_b;
3511
   input                         we_a;
3512
   output [(data_width-1):0]      q_b;
3513
   input [(data_width-1):0]       d_b;
3514
   output reg [(data_width-1):0] q_a;
3515
   input                         we_b;
3516
   input                         clk_a, clk_b;
3517
   reg [(data_width-1):0]         q_b;
3518
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
3519 7 unneback
 
3520
   parameter init = 0;
3521
   parameter memory_file = "vl_ram.vmem";
3522
   generate if (init) begin : init_mem
3523
   initial
3524
     begin
3525
        $readmemh(memory_file, ram);
3526
     end
3527
   end
3528
   endgenerate
3529
 
3530 6 unneback
   always @ (posedge clk_a)
3531
     begin
3532
        q_a <= ram[adr_a];
3533
        if (we_a)
3534
             ram[adr_a] <= d_a;
3535
     end
3536
   always @ (posedge clk_b)
3537
     begin
3538
        q_b <= ram[adr_b];
3539
        if (we_b)
3540
          ram[adr_b] <= d_b;
3541
     end
3542
endmodule
3543 40 unneback
`endif
3544 6 unneback
 
3545
// Content addresable memory, CAM
3546
 
3547 40 unneback
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
3548 6 unneback
// FIFO
3549 40 unneback
`define MODULE fifo_1r1w_fill_level_sync
3550
module `BASE`MODULE (
3551
`undef MODULE
3552 25 unneback
    d, wr, fifo_full,
3553
    q, rd, fifo_empty,
3554
    fill_level,
3555
    clk, rst
3556
    );
3557
 
3558
parameter data_width = 18;
3559
parameter addr_width = 4;
3560 6 unneback
 
3561 25 unneback
// write side
3562
input  [data_width-1:0] d;
3563
input                   wr;
3564
output                  fifo_full;
3565
// read side
3566
output [data_width-1:0] q;
3567
input                   rd;
3568
output                  fifo_empty;
3569
// common
3570
output [addr_width:0]   fill_level;
3571
input rst, clk;
3572
 
3573
wire [addr_width:1] wadr, radr;
3574
 
3575 40 unneback
`define MODULE cnt_bin_ce
3576
`BASE`MODULE
3577 25 unneback
    # ( .length(addr_width))
3578
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
3579 40 unneback
`BASE`MODULE
3580 25 unneback
    # (.length(addr_width))
3581
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
3582 40 unneback
`undef MODULE
3583 25 unneback
 
3584 40 unneback
`define MODULE dpram_1r1w
3585
`BASE`MODULE
3586 25 unneback
    # (.data_width(data_width), .addr_width(addr_width))
3587
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
3588 40 unneback
`undef MODULE
3589 25 unneback
 
3590 40 unneback
`define MODULE cnt_bin_ce_rew_q_zq_l1
3591
`BASE`MODULE
3592 27 unneback
    # (.length(addr_width+1), .level1_value(1<<addr_width))
3593 25 unneback
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
3594 40 unneback
`undef MODULE
3595 25 unneback
endmodule
3596 40 unneback
`endif
3597 25 unneback
 
3598 40 unneback
`ifdef FIFO_2R2W_SYNC_SIMPLEX
3599 27 unneback
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
3600
// RAM is supposed to be larger than the two FIFOs
3601
// LFSR counters used adr pointers
3602 40 unneback
`define MODULE fifo_2r2w_sync_simplex
3603
module `BASE`MODULE (
3604
`undef MODULE
3605 27 unneback
    // a side
3606
    a_d, a_wr, a_fifo_full,
3607
    a_q, a_rd, a_fifo_empty,
3608
    a_fill_level,
3609
    // b side
3610
    b_d, b_wr, b_fifo_full,
3611
    b_q, b_rd, b_fifo_empty,
3612
    b_fill_level,
3613
    // common
3614
    clk, rst
3615
    );
3616
parameter data_width = 8;
3617
parameter addr_width = 5;
3618
parameter fifo_full_level = (1<<addr_width)-1;
3619
 
3620
// a side
3621
input  [data_width-1:0] a_d;
3622
input                   a_wr;
3623
output                  a_fifo_full;
3624
output [data_width-1:0] a_q;
3625
input                   a_rd;
3626
output                  a_fifo_empty;
3627
output [addr_width-1:0] a_fill_level;
3628
 
3629
// b side
3630
input  [data_width-1:0] b_d;
3631
input                   b_wr;
3632
output                  b_fifo_full;
3633
output [data_width-1:0] b_q;
3634
input                   b_rd;
3635
output                  b_fifo_empty;
3636
output [addr_width-1:0] b_fill_level;
3637
 
3638
input                   clk;
3639
input                   rst;
3640
 
3641
// adr_gen
3642
wire [addr_width:1] a_wadr, a_radr;
3643
wire [addr_width:1] b_wadr, b_radr;
3644
// dpram
3645
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
3646
 
3647 40 unneback
`define MODULE cnt_lfsr_ce
3648
`BASE`MODULE
3649 27 unneback
    # ( .length(addr_width))
3650
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
3651
 
3652 40 unneback
`BASE`MODULE
3653 27 unneback
    # (.length(addr_width))
3654
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
3655
 
3656 40 unneback
`BASE`MODULE
3657 27 unneback
    # ( .length(addr_width))
3658
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
3659
 
3660 40 unneback
`BASE`MODULE
3661 27 unneback
    # (.length(addr_width))
3662
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
3663 40 unneback
`undef MODULE
3664 27 unneback
 
3665
// mux read or write adr to DPRAM
3666
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
3667
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
3668
 
3669 40 unneback
`define MODULE dpram_2r2w
3670
`BASE`MODULE
3671 27 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
3672
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
3673
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
3674 40 unneback
`undef MODULE
3675
 
3676
`define MODULE cnt_bin_ce_rew_zq_l1
3677
`BASE`MODULE
3678 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
3679 27 unneback
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
3680
 
3681 40 unneback
`BASE`MODULE
3682 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
3683 27 unneback
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
3684 40 unneback
`undef MODULE
3685 27 unneback
 
3686
endmodule
3687 40 unneback
`endif
3688 27 unneback
 
3689 40 unneback
`ifdef FIFO_CMP_ASYNC
3690
`define MODULE fifo_cmp_async
3691
module `BASE`MODULE ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
3692
`undef MODULE
3693 6 unneback
 
3694 11 unneback
   parameter addr_width = 4;
3695
   parameter N = addr_width-1;
3696 6 unneback
 
3697
   parameter Q1 = 2'b00;
3698
   parameter Q2 = 2'b01;
3699
   parameter Q3 = 2'b11;
3700
   parameter Q4 = 2'b10;
3701
 
3702
   parameter going_empty = 1'b0;
3703
   parameter going_full  = 1'b1;
3704
 
3705
   input [N:0]  wptr, rptr;
3706 14 unneback
   output       fifo_empty;
3707 6 unneback
   output       fifo_full;
3708
   input        wclk, rclk, rst;
3709
 
3710
`ifndef GENERATE_DIRECTION_AS_LATCH
3711
   wire direction;
3712
`endif
3713
`ifdef GENERATE_DIRECTION_AS_LATCH
3714
   reg direction;
3715
`endif
3716
   reg  direction_set, direction_clr;
3717
 
3718
   wire async_empty, async_full;
3719
   wire fifo_full2;
3720 14 unneback
   wire fifo_empty2;
3721 6 unneback
 
3722
   // direction_set
3723
   always @ (wptr[N:N-1] or rptr[N:N-1])
3724
     case ({wptr[N:N-1],rptr[N:N-1]})
3725
       {Q1,Q2} : direction_set <= 1'b1;
3726
       {Q2,Q3} : direction_set <= 1'b1;
3727
       {Q3,Q4} : direction_set <= 1'b1;
3728
       {Q4,Q1} : direction_set <= 1'b1;
3729
       default : direction_set <= 1'b0;
3730
     endcase
3731
 
3732
   // direction_clear
3733
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
3734
     if (rst)
3735
       direction_clr <= 1'b1;
3736
     else
3737
       case ({wptr[N:N-1],rptr[N:N-1]})
3738
         {Q2,Q1} : direction_clr <= 1'b1;
3739
         {Q3,Q2} : direction_clr <= 1'b1;
3740
         {Q4,Q3} : direction_clr <= 1'b1;
3741
         {Q1,Q4} : direction_clr <= 1'b1;
3742
         default : direction_clr <= 1'b0;
3743
       endcase
3744
 
3745 40 unneback
`define MODULE dff_sr
3746 6 unneback
`ifndef GENERATE_DIRECTION_AS_LATCH
3747 40 unneback
    `BASE`MODULE dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
3748 6 unneback
`endif
3749
 
3750
`ifdef GENERATE_DIRECTION_AS_LATCH
3751
   always @ (posedge direction_set or posedge direction_clr)
3752
     if (direction_clr)
3753
       direction <= going_empty;
3754
     else
3755
       direction <= going_full;
3756
`endif
3757
 
3758
   assign async_empty = (wptr == rptr) && (direction==going_empty);
3759
   assign async_full  = (wptr == rptr) && (direction==going_full);
3760
 
3761 40 unneback
    `BASE`MODULE dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
3762
    `BASE`MODULE dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
3763
`undef MODULE
3764 6 unneback
 
3765
/*
3766
   always @ (posedge wclk or posedge rst or posedge async_full)
3767
     if (rst)
3768
       {fifo_full, fifo_full2} <= 2'b00;
3769
     else if (async_full)
3770
       {fifo_full, fifo_full2} <= 2'b11;
3771
     else
3772
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
3773
*/
3774 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
3775 6 unneback
     if (async_empty)
3776
       {fifo_empty, fifo_empty2} <= 2'b11;
3777
     else
3778 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
3779 40 unneback
`define MODULE dff
3780
    `BASE`MODULE # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
3781
    `BASE`MODULE # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
3782
`undef MODULE
3783 27 unneback
endmodule // async_compb
3784 40 unneback
`endif
3785 6 unneback
 
3786 40 unneback
`ifdef FIFO_1R1W_ASYNC
3787
`define MODULE fifo_1r1w_async
3788
module `BASE`MODULE (
3789
`undef MODULE
3790 6 unneback
    d, wr, fifo_full, wr_clk, wr_rst,
3791
    q, rd, fifo_empty, rd_clk, rd_rst
3792
    );
3793
 
3794
parameter data_width = 18;
3795
parameter addr_width = 4;
3796
 
3797
// write side
3798
input  [data_width-1:0] d;
3799
input                   wr;
3800
output                  fifo_full;
3801
input                   wr_clk;
3802
input                   wr_rst;
3803
// read side
3804
output [data_width-1:0] q;
3805
input                   rd;
3806
output                  fifo_empty;
3807
input                   rd_clk;
3808
input                   rd_rst;
3809
 
3810
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
3811 23 unneback
 
3812 40 unneback
`define MODULE cnt_gray_ce_bin
3813
`BASE`MODULE
3814 6 unneback
    # ( .length(addr_width))
3815
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
3816
 
3817 40 unneback
`BASE`MODULE
3818 6 unneback
    # (.length(addr_width))
3819 23 unneback
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
3820 40 unneback
`undef MODULE
3821 6 unneback
 
3822 40 unneback
`define MODULE dpram_1r1w
3823
`BASE`MODULE
3824 6 unneback
    # (.data_width(data_width), .addr_width(addr_width))
3825
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
3826 40 unneback
`undef MODULE
3827 6 unneback
 
3828 40 unneback
`define MODULE fifo_cmp_async
3829
`BASE`MODULE
3830 6 unneback
    # (.addr_width(addr_width))
3831
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
3832 40 unneback
`undef MODULE
3833 6 unneback
 
3834
endmodule
3835 40 unneback
`endif
3836 6 unneback
 
3837 40 unneback
`ifdef FIFO_2R2W_ASYNC
3838
`define MODULE fifo_2r2w_async
3839
module `BASE`MODULE (
3840
`undef MODULE
3841 6 unneback
    // a side
3842
    a_d, a_wr, a_fifo_full,
3843
    a_q, a_rd, a_fifo_empty,
3844
    a_clk, a_rst,
3845
    // b side
3846
    b_d, b_wr, b_fifo_full,
3847
    b_q, b_rd, b_fifo_empty,
3848
    b_clk, b_rst
3849
    );
3850
 
3851
parameter data_width = 18;
3852
parameter addr_width = 4;
3853
 
3854
// a side
3855
input  [data_width-1:0] a_d;
3856
input                   a_wr;
3857
output                  a_fifo_full;
3858
output [data_width-1:0] a_q;
3859
input                   a_rd;
3860
output                  a_fifo_empty;
3861
input                   a_clk;
3862
input                   a_rst;
3863
 
3864
// b side
3865
input  [data_width-1:0] b_d;
3866
input                   b_wr;
3867
output                  b_fifo_full;
3868
output [data_width-1:0] b_q;
3869
input                   b_rd;
3870
output                  b_fifo_empty;
3871
input                   b_clk;
3872
input                   b_rst;
3873
 
3874 40 unneback
`define MODULE fifo_1r1w_async
3875
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
3876 6 unneback
vl_fifo_1r1w_async_a (
3877
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
3878
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
3879
    );
3880
 
3881 40 unneback
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
3882 6 unneback
vl_fifo_1r1w_async_b (
3883
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
3884
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
3885
    );
3886 40 unneback
`undef MODULE
3887
 
3888 6 unneback
endmodule
3889 40 unneback
`endif
3890 6 unneback
 
3891 40 unneback
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
3892
`define MODULE fifo_2r2w_async_simplex
3893
module `BASE`MODULE (
3894
`undef MODULE
3895 6 unneback
    // a side
3896
    a_d, a_wr, a_fifo_full,
3897
    a_q, a_rd, a_fifo_empty,
3898
    a_clk, a_rst,
3899
    // b side
3900
    b_d, b_wr, b_fifo_full,
3901
    b_q, b_rd, b_fifo_empty,
3902
    b_clk, b_rst
3903
    );
3904
 
3905
parameter data_width = 18;
3906
parameter addr_width = 4;
3907
 
3908
// a side
3909
input  [data_width-1:0] a_d;
3910
input                   a_wr;
3911
output                  a_fifo_full;
3912
output [data_width-1:0] a_q;
3913
input                   a_rd;
3914
output                  a_fifo_empty;
3915
input                   a_clk;
3916
input                   a_rst;
3917
 
3918
// b side
3919
input  [data_width-1:0] b_d;
3920
input                   b_wr;
3921
output                  b_fifo_full;
3922
output [data_width-1:0] b_q;
3923
input                   b_rd;
3924
output                  b_fifo_empty;
3925
input                   b_clk;
3926
input                   b_rst;
3927
 
3928
// adr_gen
3929
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
3930
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
3931
// dpram
3932
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
3933
 
3934 40 unneback
`define MODULE cnt_gray_ce_bin
3935
`BASE`MODULE
3936 6 unneback
    # ( .length(addr_width))
3937
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
3938
 
3939 40 unneback
`BASE`MODULE
3940 6 unneback
    # (.length(addr_width))
3941
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
3942
 
3943 40 unneback
`BASE`MODULE
3944 6 unneback
    # ( .length(addr_width))
3945
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
3946
 
3947 40 unneback
`BASE`MODULE
3948 6 unneback
    # (.length(addr_width))
3949
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
3950 40 unneback
`undef MODULE
3951 6 unneback
 
3952
// mux read or write adr to DPRAM
3953
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
3954
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
3955
 
3956 40 unneback
`define MODULE dpram_2r2w
3957
`BASE`MODULE
3958 6 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
3959
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
3960
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
3961 40 unneback
`undef MODULE
3962 6 unneback
 
3963 40 unneback
`define MODULE fifo_cmp_async
3964
`BASE`MODULE
3965 6 unneback
    # (.addr_width(addr_width))
3966
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
3967
 
3968 40 unneback
`BASE`MODULE
3969 6 unneback
    # (.addr_width(addr_width))
3970
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
3971 40 unneback
`undef MODULE
3972 6 unneback
 
3973
endmodule
3974 40 unneback
`endif
3975 12 unneback
//////////////////////////////////////////////////////////////////////
3976
////                                                              ////
3977
////  Versatile library, wishbone stuff                           ////
3978
////                                                              ////
3979
////  Description                                                 ////
3980
////  Wishbone compliant modules                                  ////
3981
////                                                              ////
3982
////                                                              ////
3983
////  To Do:                                                      ////
3984
////   -                                                          ////
3985
////                                                              ////
3986
////  Author(s):                                                  ////
3987
////      - Michael Unneback, unneback@opencores.org              ////
3988
////        ORSoC AB                                              ////
3989
////                                                              ////
3990
//////////////////////////////////////////////////////////////////////
3991
////                                                              ////
3992
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
3993
////                                                              ////
3994
//// This source file may be used and distributed without         ////
3995
//// restriction provided that this copyright statement is not    ////
3996
//// removed from the file and that any derivative work contains  ////
3997
//// the original copyright notice and the associated disclaimer. ////
3998
////                                                              ////
3999
//// This source file is free software; you can redistribute it   ////
4000
//// and/or modify it under the terms of the GNU Lesser General   ////
4001
//// Public License as published by the Free Software Foundation; ////
4002
//// either version 2.1 of the License, or (at your option) any   ////
4003
//// later version.                                               ////
4004
////                                                              ////
4005
//// This source is distributed in the hope that it will be       ////
4006
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
4007
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
4008
//// PURPOSE.  See the GNU Lesser General Public License for more ////
4009
//// details.                                                     ////
4010
////                                                              ////
4011
//// You should have received a copy of the GNU Lesser General    ////
4012
//// Public License along with this source; if not, download it   ////
4013
//// from http://www.opencores.org/lgpl.shtml                     ////
4014
////                                                              ////
4015
//////////////////////////////////////////////////////////////////////
4016
 
4017 40 unneback
`ifdef WB3WB3_BRIDGE
4018 12 unneback
// async wb3 - wb3 bridge
4019
`timescale 1ns/1ns
4020 40 unneback
`define MODULE wb3wb3_bridge
4021
module `BASE`MODULE (
4022
`undef MODULE
4023 12 unneback
        // wishbone slave side
4024
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
4025
        // wishbone master side
4026
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
4027
 
4028
input [31:0] wbs_dat_i;
4029
input [31:2] wbs_adr_i;
4030
input [3:0]  wbs_sel_i;
4031
input [1:0]  wbs_bte_i;
4032
input [2:0]  wbs_cti_i;
4033
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
4034
output [31:0] wbs_dat_o;
4035 14 unneback
output wbs_ack_o;
4036 12 unneback
input wbs_clk, wbs_rst;
4037
 
4038
output [31:0] wbm_dat_o;
4039
output reg [31:2] wbm_adr_o;
4040
output [3:0]  wbm_sel_o;
4041
output reg [1:0]  wbm_bte_o;
4042
output reg [2:0]  wbm_cti_o;
4043 14 unneback
output reg wbm_we_o;
4044
output wbm_cyc_o;
4045 12 unneback
output wbm_stb_o;
4046
input [31:0]  wbm_dat_i;
4047
input wbm_ack_i;
4048
input wbm_clk, wbm_rst;
4049
 
4050
parameter addr_width = 4;
4051
 
4052
// bte
4053
parameter linear       = 2'b00;
4054
parameter wrap4        = 2'b01;
4055
parameter wrap8        = 2'b10;
4056
parameter wrap16       = 2'b11;
4057
// cti
4058
parameter classic      = 3'b000;
4059
parameter incburst     = 3'b010;
4060
parameter endofburst   = 3'b111;
4061
 
4062
parameter wbs_adr  = 1'b0;
4063
parameter wbs_data = 1'b1;
4064
 
4065 33 unneback
parameter wbm_adr0      = 2'b00;
4066
parameter wbm_adr1      = 2'b01;
4067
parameter wbm_data      = 2'b10;
4068
parameter wbm_data_wait = 2'b11;
4069 12 unneback
 
4070
reg [1:0] wbs_bte_reg;
4071
reg wbs;
4072
wire wbs_eoc_alert, wbm_eoc_alert;
4073
reg wbs_eoc, wbm_eoc;
4074
reg [1:0] wbm;
4075
 
4076 14 unneback
wire [1:16] wbs_count, wbm_count;
4077 12 unneback
 
4078
wire [35:0] a_d, a_q, b_d, b_q;
4079
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
4080
reg a_rd_reg;
4081
wire b_rd_adr, b_rd_data;
4082 14 unneback
wire b_rd_data_reg;
4083
wire [35:0] temp;
4084 12 unneback
 
4085
`define WE 5
4086
`define BTE 4:3
4087
`define CTI 2:0
4088
 
4089
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
4090
always @ (posedge wbs_clk or posedge wbs_rst)
4091
if (wbs_rst)
4092
        wbs_eoc <= 1'b0;
4093
else
4094
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
4095
                wbs_eoc <= wbs_bte_i==linear;
4096
        else if (wbs_eoc_alert & (a_rd | a_wr))
4097
                wbs_eoc <= 1'b1;
4098
 
4099 40 unneback
`define MODULE cnt_shreg_ce_clear
4100
`BASE`MODULE # ( .length(16))
4101
`undef MODULE
4102 12 unneback
    cnt0 (
4103
        .cke(wbs_ack_o),
4104
        .clear(wbs_eoc),
4105
        .q(wbs_count),
4106
        .rst(wbs_rst),
4107
        .clk(wbs_clk));
4108
 
4109
always @ (posedge wbs_clk or posedge wbs_rst)
4110
if (wbs_rst)
4111
        wbs <= wbs_adr;
4112
else
4113
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & !a_fifo_full)
4114
                wbs <= wbs_data;
4115
        else if (wbs_eoc & wbs_ack_o)
4116
                wbs <= wbs_adr;
4117
 
4118
// wbs FIFO
4119
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,wbs_bte_i,wbs_cti_i} : {wbs_dat_i,wbs_sel_i};
4120
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & !a_fifo_full :
4121
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
4122
              1'b0;
4123
assign a_rd = !a_fifo_empty;
4124
always @ (posedge wbs_clk or posedge wbs_rst)
4125
if (wbs_rst)
4126
        a_rd_reg <= 1'b0;
4127
else
4128
        a_rd_reg <= a_rd;
4129
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
4130
 
4131
assign wbs_dat_o = a_q[35:4];
4132
 
4133
always @ (posedge wbs_clk or posedge wbs_rst)
4134
if (wbs_rst)
4135 13 unneback
        wbs_bte_reg <= 2'b00;
4136 12 unneback
else
4137 13 unneback
        wbs_bte_reg <= wbs_bte_i;
4138 12 unneback
 
4139
// wbm FIFO
4140
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
4141
always @ (posedge wbm_clk or posedge wbm_rst)
4142
if (wbm_rst)
4143
        wbm_eoc <= 1'b0;
4144
else
4145
        if (wbm==wbm_adr0 & !b_fifo_empty)
4146
                wbm_eoc <= b_q[`BTE] == linear;
4147
        else if (wbm_eoc_alert & wbm_ack_i)
4148
                wbm_eoc <= 1'b1;
4149
 
4150
always @ (posedge wbm_clk or posedge wbm_rst)
4151
if (wbm_rst)
4152
        wbm <= wbm_adr0;
4153
else
4154 33 unneback
/*
4155 12 unneback
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
4156
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
4157
        (wbm==wbm_adr1 & !wbm_we_o) |
4158
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
4159
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
4160 33 unneback
*/
4161
    case (wbm)
4162
    wbm_adr0:
4163
        if (!b_fifo_empty)
4164
            wbm <= wbm_adr1;
4165
    wbm_adr1:
4166
        if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
4167
            wbm <= wbm_data;
4168
    wbm_data:
4169
        if (wbm_ack_i & wbm_eoc)
4170
            wbm <= wbm_adr0;
4171
        else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
4172
            wbm <= wbm_data_wait;
4173
    wbm_data_wait:
4174
        if (!b_fifo_empty)
4175
            wbm <= wbm_data;
4176
    endcase
4177 12 unneback
 
4178
assign b_d = {wbm_dat_i,4'b1111};
4179
assign b_wr = !wbm_we_o & wbm_ack_i;
4180
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
4181
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
4182
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
4183 33 unneback
                   (wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
4184 12 unneback
                   1'b0;
4185
assign b_rd = b_rd_adr | b_rd_data;
4186
 
4187 40 unneback
`define MODULE dff
4188
`BASE`MODULE dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
4189
`undef MODULE
4190
`define MODULE dff_ce
4191
`BASE`MODULE # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
4192
`undef MODULE
4193 12 unneback
 
4194
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
4195
 
4196 40 unneback
`define MODULE cnt_shreg_ce_clear
4197 42 unneback
`BASE`MODULE # ( .length(16))
4198 40 unneback
`undef MODULE
4199 12 unneback
    cnt1 (
4200
        .cke(wbm_ack_i),
4201
        .clear(wbm_eoc),
4202
        .q(wbm_count),
4203
        .rst(wbm_rst),
4204
        .clk(wbm_clk));
4205
 
4206 33 unneback
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
4207
assign wbm_stb_o = (wbm==wbm_data);
4208 12 unneback
 
4209
always @ (posedge wbm_clk or posedge wbm_rst)
4210
if (wbm_rst)
4211
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
4212
else begin
4213
        if (wbm==wbm_adr0 & !b_fifo_empty)
4214
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
4215
        else if (wbm_eoc_alert & wbm_ack_i)
4216
                wbm_cti_o <= endofburst;
4217
end
4218
 
4219
//async_fifo_dw_simplex_top
4220 40 unneback
`define MODULE fifo_2r2w_async_simplex
4221
`BASE`MODULE
4222
`undef MODULE
4223 12 unneback
# ( .data_width(36), .addr_width(addr_width))
4224
fifo (
4225
    // a side
4226
    .a_d(a_d),
4227
    .a_wr(a_wr),
4228
    .a_fifo_full(a_fifo_full),
4229
    .a_q(a_q),
4230
    .a_rd(a_rd),
4231
    .a_fifo_empty(a_fifo_empty),
4232
    .a_clk(wbs_clk),
4233
    .a_rst(wbs_rst),
4234
    // b side
4235
    .b_d(b_d),
4236
    .b_wr(b_wr),
4237
    .b_fifo_full(b_fifo_full),
4238
    .b_q(b_q),
4239
    .b_rd(b_rd),
4240
    .b_fifo_empty(b_fifo_empty),
4241
    .b_clk(wbm_clk),
4242
    .b_rst(wbm_rst)
4243
    );
4244
 
4245
endmodule
4246 40 unneback
`undef WE
4247
`undef BTE
4248
`undef CTI
4249
`endif
4250 17 unneback
 
4251 40 unneback
`ifdef WB3_ARBITER_TYPE1
4252
`define MODULE wb3_arbiter_type1
4253 42 unneback
module `BASE`MODULE (
4254 40 unneback
`undef MODULE
4255 39 unneback
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
4256
    wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
4257
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
4258
    wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
4259
    wb_clk, wb_rst
4260
);
4261
 
4262
parameter nr_of_ports = 3;
4263
parameter adr_size = 26;
4264
parameter adr_lo   = 2;
4265
parameter dat_size = 32;
4266
parameter sel_size = dat_size/8;
4267
 
4268
localparam aw = (adr_size - adr_lo) * nr_of_ports;
4269
localparam dw = dat_size * nr_of_ports;
4270
localparam sw = sel_size * nr_of_ports;
4271
localparam cw = 3 * nr_of_ports;
4272
localparam bw = 2 * nr_of_ports;
4273
 
4274
input  [dw-1:0] wbm_dat_o;
4275
input  [aw-1:0] wbm_adr_o;
4276
input  [sw-1:0] wbm_sel_o;
4277
input  [cw-1:0] wbm_cti_o;
4278
input  [bw-1:0] wbm_bte_o;
4279
input  [nr_of_ports-1:0] wbm_we_o, wbm_stb_o, wbm_cyc_o;
4280
output [dw-1:0] wbm_dat_i;
4281
output [nr_of_ports-1:0] wbm_ack_i, wbm_err_i, wbm_rty_i;
4282
 
4283
output [dat_size-1:0] wbs_dat_i;
4284
output [adr_size-1:adr_lo] wbs_adr_i;
4285
output [sel_size-1:0] wbs_sel_i;
4286
output [2:0] wbs_cti_i;
4287
output [1:0] wbs_bte_i;
4288
output wbs_we_i, wbs_stb_i, wbs_cyc_i;
4289
input  [dat_size-1:0] wbs_dat_o;
4290
input  wbs_ack_o, wbs_err_o, wbs_rty_o;
4291
 
4292
input wb_clk, wb_rst;
4293
 
4294
wire [nr_of_ports-1:0] select;
4295
wire [nr_of_ports-1:0] state;
4296
wire [nr_of_ports-1:0] eoc; // end-of-cycle
4297
wire [nr_of_ports-1:0] sel;
4298
wire idle;
4299
 
4300
genvar i;
4301
 
4302
assign idle = !(|state);
4303
 
4304
generate
4305
if (nr_of_ports == 2) begin
4306
 
4307
    wire [2:0] wbm1_cti_o, wbm0_cti_o;
4308
 
4309
    assign {wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
4310
 
4311
    assign select = (idle) ? {wbm_cyc_o[1],!wbm_cyc_o[1] & wbm_cyc_o[0]} : 2'b00;
4312
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
4313
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
4314
 
4315
end
4316
endgenerate
4317
 
4318
generate
4319
if (nr_of_ports == 3) begin
4320
 
4321
    wire [2:0] wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
4322
 
4323
    assign {wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
4324
 
4325
    assign select = (idle) ? {wbm_cyc_o[2],!wbm_cyc_o[2] & wbm_cyc_o[1],wbm_cyc_o[2:1]==2'b00 & wbm_cyc_o[0]} : 3'b000;
4326
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
4327
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
4328
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
4329
 
4330
end
4331
endgenerate
4332
 
4333
generate
4334
for (i=0;i<nr_of_ports;i=i+1) begin
4335 42 unneback
`define MODULE spr
4336
    `BASE`MODULE sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));
4337
`undef MODULE
4338 39 unneback
end
4339
endgenerate
4340
 
4341
    assign sel = select | state;
4342
 
4343 40 unneback
`define MODULE mux_andor
4344
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i));
4345
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(adr_size-adr_lo)) mux1 ( .a(wbm_adr_o), .sel(sel), .dout(wbs_adr_i));
4346
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(sel_size)) mux2 ( .a(wbm_sel_o), .sel(sel), .dout(wbs_sel_i));
4347
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(3)) mux3 ( .a(wbm_cti_o), .sel(sel), .dout(wbs_cti_i));
4348
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(2)) mux4 ( .a(wbm_bte_o), .sel(sel), .dout(wbs_bte_i));
4349
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux5 ( .a(wbm_we_o), .sel(sel), .dout(wbs_we_i));
4350
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux6 ( .a(wbm_stb_o), .sel(sel), .dout(wbs_stb_i));
4351
`undef MODULE
4352 39 unneback
    assign wbs_cyc_i = |sel;
4353
 
4354
    assign wbm_dat_i = {nr_of_ports{wbs_dat_o}};
4355
    assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
4356
    assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
4357
    assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
4358
 
4359
endmodule
4360 40 unneback
`endif
4361 39 unneback
 
4362 40 unneback
`ifdef WB_BOOT_ROM
4363 17 unneback
// WB ROM
4364 40 unneback
`define MODULE wb_boot_rom
4365
module `BASE`MODULE (
4366
`undef MODULE
4367 17 unneback
    wb_adr_i, wb_stb_i, wb_cyc_i,
4368 18 unneback
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
4369 17 unneback
 
4370 18 unneback
    parameter adr_hi = 31;
4371
    parameter adr_lo = 28;
4372
    parameter adr_sel = 4'hf;
4373
    parameter addr_width = 5;
4374 33 unneback
/*
4375 17 unneback
`ifndef BOOT_ROM
4376
`define BOOT_ROM "boot_rom.v"
4377
`endif
4378 33 unneback
*/
4379 18 unneback
    input [adr_hi:2]    wb_adr_i;
4380
    input               wb_stb_i;
4381
    input               wb_cyc_i;
4382
    output [31:0]        wb_dat_o;
4383
    output              wb_ack_o;
4384
    output              hit_o;
4385
    input               wb_clk;
4386
    input               wb_rst;
4387
 
4388
    wire hit;
4389
    reg [31:0] wb_dat;
4390
    reg wb_ack;
4391
 
4392
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
4393 17 unneback
 
4394
always @ (posedge wb_clk or posedge wb_rst)
4395
    if (wb_rst)
4396 18 unneback
        wb_dat <= 32'h15000000;
4397 17 unneback
    else
4398 18 unneback
         case (wb_adr_i[addr_width-1:2])
4399 33 unneback
`ifdef BOOT_ROM
4400 17 unneback
`include `BOOT_ROM
4401 33 unneback
`endif
4402 17 unneback
           /*
4403
            // Zero r0 and jump to 0x00000100
4404 18 unneback
 
4405
            1 : wb_dat <= 32'hA8200000;
4406
            2 : wb_dat <= 32'hA8C00100;
4407
            3 : wb_dat <= 32'h44003000;
4408
            4 : wb_dat <= 32'h15000000;
4409 17 unneback
            */
4410
           default:
4411 18 unneback
             wb_dat <= 32'h00000000;
4412 17 unneback
 
4413
         endcase // case (wb_adr_i)
4414
 
4415
 
4416
always @ (posedge wb_clk or posedge wb_rst)
4417
    if (wb_rst)
4418 18 unneback
        wb_ack <= 1'b0;
4419 17 unneback
    else
4420 18 unneback
        wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
4421 17 unneback
 
4422 18 unneback
assign hit_o = hit;
4423
assign wb_dat_o = wb_dat & {32{wb_ack}};
4424
assign wb_ack_o = wb_ack;
4425
 
4426 17 unneback
endmodule
4427 40 unneback
`endif
4428 32 unneback
 
4429 40 unneback
`ifdef WB_DPRAM
4430
`define MODULE wb_dpram
4431
module `BASE`MODULE (
4432
`undef MODULE
4433 32 unneback
        // wishbone slave side a
4434
        wbsa_dat_i, wbsa_adr_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o,
4435
        wbsa_clk, wbsa_rst,
4436
        // wishbone slave side a
4437
        wbsb_dat_i, wbsb_adr_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o,
4438
        wbsb_clk, wbsb_rst);
4439
 
4440
parameter data_width = 32;
4441
parameter addr_width = 8;
4442
 
4443
parameter dat_o_mask_a = 1;
4444
parameter dat_o_mask_b = 1;
4445
 
4446
input [31:0] wbsa_dat_i;
4447
input [addr_width-1:2] wbsa_adr_i;
4448
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
4449
output [31:0] wbsa_dat_o;
4450
output wbsa_ack_o;
4451
input wbsa_clk, wbsa_rst;
4452
 
4453
input [31:0] wbsb_dat_i;
4454
input [addr_width-1:2] wbsb_adr_i;
4455
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
4456
output [31:0] wbsb_dat_o;
4457
output wbsb_ack_o;
4458
input wbsb_clk, wbsb_rst;
4459
 
4460
wire wbsa_dat_tmp, wbsb_dat_tmp;
4461
 
4462 40 unneback
`define MODULE dpram_2r2w
4463
`BASE`MODULE # (
4464
`undef MODULE
4465 33 unneback
    .data_width(data_width), .addr_width(addr_width) )
4466 32 unneback
dpram0(
4467
    .d_a(wbsa_dat_i),
4468
    .q_a(wbsa_dat_tmp),
4469
    .adr_a(wbsa_adr_i),
4470
    .we_a(wbsa_we_i),
4471
    .clk_a(wbsa_clk),
4472
    .d_b(wbsb_dat_i),
4473
    .q_b(wbsb_dat_tmp),
4474
    .adr_b(wbsb_adr_i),
4475
    .we_b(wbsb_we_i),
4476
    .clk_b(wbsb_clk) );
4477
 
4478 33 unneback
generate if (dat_o_mask_a==1)
4479 32 unneback
    assign wbsa_dat_o = wbsa_dat_tmp & {data_width{wbsa_ack_o}};
4480
endgenerate
4481 33 unneback
generate if (dat_o_mask_a==0)
4482 32 unneback
    assign wbsa_dat_o = wbsa_dat_tmp;
4483
endgenerate
4484
 
4485 33 unneback
generate if (dat_o_mask_b==1)
4486 32 unneback
    assign wbsb_dat_o = wbsb_dat_tmp & {data_width{wbsb_ack_o}};
4487
endgenerate
4488 33 unneback
generate if (dat_o_mask_b==0)
4489 32 unneback
    assign wbsb_dat_o = wbsb_dat_tmp;
4490
endgenerate
4491
 
4492 40 unneback
`define MODULE spr
4493
`BASE`MODULE ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
4494
`BASE`MODULE ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
4495
`undef MODULE
4496 32 unneback
 
4497
endmodule
4498 40 unneback
`endif
4499 18 unneback
//////////////////////////////////////////////////////////////////////
4500
////                                                              ////
4501
////  Arithmetic functions                                        ////
4502
////                                                              ////
4503
////  Description                                                 ////
4504
////  Arithmetic functions for ALU and DSP                        ////
4505
////                                                              ////
4506
////                                                              ////
4507
////  To Do:                                                      ////
4508
////   -                                                          ////
4509
////                                                              ////
4510
////  Author(s):                                                  ////
4511
////      - Michael Unneback, unneback@opencores.org              ////
4512
////        ORSoC AB                                              ////
4513
////                                                              ////
4514
//////////////////////////////////////////////////////////////////////
4515
////                                                              ////
4516
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
4517
////                                                              ////
4518
//// This source file may be used and distributed without         ////
4519
//// restriction provided that this copyright statement is not    ////
4520
//// removed from the file and that any derivative work contains  ////
4521
//// the original copyright notice and the associated disclaimer. ////
4522
////                                                              ////
4523
//// This source file is free software; you can redistribute it   ////
4524
//// and/or modify it under the terms of the GNU Lesser General   ////
4525
//// Public License as published by the Free Software Foundation; ////
4526
//// either version 2.1 of the License, or (at your option) any   ////
4527
//// later version.                                               ////
4528
////                                                              ////
4529
//// This source is distributed in the hope that it will be       ////
4530
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
4531
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
4532
//// PURPOSE.  See the GNU Lesser General Public License for more ////
4533
//// details.                                                     ////
4534
////                                                              ////
4535
//// You should have received a copy of the GNU Lesser General    ////
4536
//// Public License along with this source; if not, download it   ////
4537
//// from http://www.opencores.org/lgpl.shtml                     ////
4538
////                                                              ////
4539
//////////////////////////////////////////////////////////////////////
4540
 
4541 40 unneback
`ifdef MULTS
4542 18 unneback
// signed multiplication
4543 40 unneback
`define MODULE mults
4544
module `BASE`MODULE (a,b,p);
4545
`undef MODULE
4546 18 unneback
parameter operand_a_width = 18;
4547
parameter operand_b_width = 18;
4548
parameter result_hi = 35;
4549
parameter result_lo = 0;
4550
input [operand_a_width-1:0] a;
4551
input [operand_b_width-1:0] b;
4552
output [result_hi:result_lo] p;
4553
wire signed [operand_a_width-1:0] ai;
4554
wire signed [operand_b_width-1:0] bi;
4555
wire signed [operand_a_width+operand_b_width-1:0] result;
4556
 
4557
    assign ai = a;
4558
    assign bi = b;
4559
    assign result = ai * bi;
4560
    assign p = result[result_hi:result_lo];
4561
 
4562
endmodule
4563 40 unneback
`endif
4564
`ifdef MULTS18X18
4565
`define MODULE mults18x18
4566
module `BASE`MODULE (a,b,p);
4567
`undef MODULE
4568 18 unneback
input [17:0] a,b;
4569
output [35:0] p;
4570
vl_mult
4571
    # (.operand_a_width(18), .operand_b_width(18))
4572
    mult0 (.a(a), .b(b), .p(p));
4573
endmodule
4574 40 unneback
`endif
4575 18 unneback
 
4576 40 unneback
`ifdef MULT
4577
`define MODULE mult
4578 18 unneback
// unsigned multiplication
4579 40 unneback
module `BASE`MODULE (a,b,p);
4580
`undef MODULE
4581 18 unneback
parameter operand_a_width = 18;
4582
parameter operand_b_width = 18;
4583
parameter result_hi = 35;
4584
parameter result_lo = 0;
4585
input [operand_a_width-1:0] a;
4586
input [operand_b_width-1:0] b;
4587
output [result_hi:result_hi] p;
4588
 
4589
wire [operand_a_width+operand_b_width-1:0] result;
4590
 
4591
    assign result = a * b;
4592
    assign p = result[result_hi:result_lo];
4593
 
4594
endmodule
4595 40 unneback
`endif
4596 18 unneback
 
4597 40 unneback
`ifdef SHIFT_UNIT_32
4598
`define MODULE shift_unit_32
4599 18 unneback
// shift unit
4600
// supporting the following shift functions
4601
//   SLL
4602
//   SRL
4603
//   SRA
4604
`define SHIFT_UNIT_MULT # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7))
4605 40 unneback
module `BASE`MODULE( din, s, dout, opcode);
4606
`undef MODULE
4607 18 unneback
input [31:0] din; // data in operand
4608
input [4:0] s; // shift operand
4609
input [1:0] opcode;
4610
output [31:0] dout;
4611
 
4612
parameter opcode_sll = 2'b00;
4613
//parameter opcode_srl = 2'b01;
4614
parameter opcode_sra = 2'b10;
4615
//parameter opcode_ror = 2'b11;
4616
 
4617
wire sll, sra;
4618
assign sll = opcode == opcode_sll;
4619
assign sra = opcode == opcode_sra;
4620
 
4621
wire [15:1] s1;
4622
wire [3:0] sign;
4623
wire [7:0] tmp [0:3];
4624
 
4625
// first stage is multiplier based
4626
// shift operand as fractional 8.7
4627
assign s1[15] = sll & s[2:0]==3'd7;
4628
assign s1[14] = sll & s[2:0]==3'd6;
4629
assign s1[13] = sll & s[2:0]==3'd5;
4630
assign s1[12] = sll & s[2:0]==3'd4;
4631
assign s1[11] = sll & s[2:0]==3'd3;
4632
assign s1[10] = sll & s[2:0]==3'd2;
4633
assign s1[ 9] = sll & s[2:0]==3'd1;
4634
assign s1[ 8] = s[2:0]==3'd0;
4635
assign s1[ 7] = !sll & s[2:0]==3'd1;
4636
assign s1[ 6] = !sll & s[2:0]==3'd2;
4637
assign s1[ 5] = !sll & s[2:0]==3'd3;
4638
assign s1[ 4] = !sll & s[2:0]==3'd4;
4639
assign s1[ 3] = !sll & s[2:0]==3'd5;
4640
assign s1[ 2] = !sll & s[2:0]==3'd6;
4641
assign s1[ 1] = !sll & s[2:0]==3'd7;
4642
 
4643
assign sign[3] = din[31] & sra;
4644
assign sign[2] = sign[3] & (&din[31:24]);
4645
assign sign[1] = sign[2] & (&din[23:16]);
4646
assign sign[0] = sign[1] & (&din[15:8]);
4647 40 unneback
`define MODULE mults
4648
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte3 ( .a({sign[3], {8{sign[3]}},din[31:24], din[23:16]}), .b({1'b0,s1}), .p(tmp[3]));
4649
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte2 ( .a({sign[2], din[31:24]  ,din[23:16],  din[15:8]}), .b({1'b0,s1}), .p(tmp[2]));
4650
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte1 ( .a({sign[1], din[23:16]  ,din[15:8],   din[7:0]}), .b({1'b0,s1}), .p(tmp[1]));
4651
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte0 ( .a({sign[0], din[15:8]   ,din[7:0],    8'h00}),      .b({1'b0,s1}), .p(tmp[0]));
4652
`undef MODULE
4653 18 unneback
// second stage is multiplexer based
4654
// shift on byte level
4655
 
4656
// mux byte 3
4657
assign dout[31:24] = (s[4:3]==2'b00) ? tmp[3] :
4658
                     (sll & s[4:3]==2'b01) ? tmp[2] :
4659
                     (sll & s[4:3]==2'b10) ? tmp[1] :
4660
                     (sll & s[4:3]==2'b11) ? tmp[0] :
4661
                     {8{sign[3]}};
4662
 
4663
// mux byte 2
4664
assign dout[23:16] = (s[4:3]==2'b00) ? tmp[2] :
4665
                     (sll & s[4:3]==2'b01) ? tmp[1] :
4666
                     (sll & s[4:3]==2'b10) ? tmp[0] :
4667
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
4668
                     (s[4:3]==2'b01) ? tmp[3] :
4669
                     {8{sign[3]}};
4670
 
4671
// mux byte 1
4672
assign dout[15:8]  = (s[4:3]==2'b00) ? tmp[1] :
4673
                     (sll & s[4:3]==2'b01) ? tmp[0] :
4674
                     (sll & s[4:3]==2'b10) ? {8{1'b0}} :
4675
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
4676
                     (s[4:3]==2'b01) ? tmp[2] :
4677
                     (s[4:3]==2'b10) ? tmp[3] :
4678
                     {8{sign[3]}};
4679
 
4680
// mux byte 0
4681
assign dout[7:0]   = (s[4:3]==2'b00) ? tmp[0] :
4682
                     (sll) ?  {8{1'b0}}:
4683
                     (s[4:3]==2'b01) ? tmp[1] :
4684
                     (s[4:3]==2'b10) ? tmp[2] :
4685
                     tmp[3];
4686
 
4687
endmodule
4688 40 unneback
`endif
4689 18 unneback
 
4690 40 unneback
`ifdef LOGIC_UNIT
4691 18 unneback
// logic unit
4692
// supporting the following logic functions
4693
//    a and b
4694
//    a or  b
4695
//    a xor b
4696
//    not b
4697 40 unneback
`define MODULE logic_unit
4698
module `BASE`MODULE( a, b, result, opcode);
4699
`undef MODULE
4700 18 unneback
parameter width = 32;
4701
parameter opcode_and = 2'b00;
4702
parameter opcode_or  = 2'b01;
4703
parameter opcode_xor = 2'b10;
4704
input [width-1:0] a,b;
4705
output [width-1:0] result;
4706
input [1:0] opcode;
4707
 
4708
assign result = (opcode==opcode_and) ? a & b :
4709
                (opcode==opcode_or)  ? a | b :
4710
                (opcode==opcode_xor) ? a ^ b :
4711
                b;
4712
 
4713
endmodule
4714
 
4715
module vl_arith_unit ( a, b, c_in, add_sub, sign, result, c_out, z, ovfl);
4716
parameter width = 32;
4717
parameter opcode_add = 1'b0;
4718
parameter opcode_sub = 1'b1;
4719
input [width-1:0] a,b;
4720
input c_in, add_sub, sign;
4721
output [width-1:0] result;
4722
output c_out, z, ovfl;
4723
 
4724
assign {c_out,result} = {(a[width-1] & sign),a} + ({a[width-1] & sign,b} ^ {(width+1){(add_sub==opcode_sub)}}) + {{(width-1){1'b0}},(c_in | (add_sub==opcode_sub))};
4725
assign z = (result=={width{1'b0}});
4726
assign ovfl = ( a[width-1] &  b[width-1] & ~result[width-1]) |
4727
               (~a[width-1] & ~b[width-1] &  result[width-1]);
4728
endmodule
4729 40 unneback
`endif

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.