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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Blame information for rev 44

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Line No. Rev Author Line
1 40 unneback
`ifndef BASE
2
`define BASE vl_
3
`endif
4
 
5 44 unneback
`ifdef ACTEL
6
`define SYN_KEEP /*synthesis syn_keep = 1*/
7
`endif
8
 
9 40 unneback
`ifdef ALL
10
 
11
`define GBUF
12
`define SYNC_RST
13
`define PLL
14
 
15
`define MULTS
16
`define MULTS18X18
17
`define MULT
18
`define SHIFT_UNIT_32
19
`define LOGIC_UNIT
20
 
21
`define CNT_SHREG_WRAP
22
`define CNT_SHREG_CE_WRAP
23
`define CNT_SHREG_CE_CLEAR
24
`define CNT_SHREG_CE_CLEAR_WRAP
25
 
26
`define MUX_ANDOR
27
`define MUX2_ANDOR
28
`define MUX3_ANDOR
29
`define MUX4_ANDOR
30
`define MUX5_ANDOR
31
`define MUX6_ANDOR
32 43 unneback
`define PARITY
33 40 unneback
 
34
`define ROM_INIT
35
`define RAM
36
`define RAM_BE
37
`define DPRAM_1R1W
38
`define DPRAM_2R1W
39
`define DPRAM_2R2W
40
`define FIFO_1R1W_FILL_LEVEL_SYNC
41
`define FIFO_2R2W_SYNC_SIMPLEX
42
`define FIFO_CMP_ASYNC
43
`define FIFO_1R1W_ASYNC
44
`define FIFO_2R2W_ASYNC
45
`define FIFO_2R2W_ASYNC_SIMPLEX
46
 
47
`define DFF
48
`define DFF_ARRAY
49
`define DFF_CE
50
`define DFF_CE_CLEAR
51
`define DF_CE_SET
52
`define SPR
53
`define SRP
54
`define DFF_SR
55
`define LATCH
56
`define SHREG
57
`define SHREG_CE
58
`define DELAY
59
`define DELAY_EMPTYFLAG
60
 
61
`define WB3WB3_BRIDGE
62
`define WB3_ARBITER_TYPE1
63
`define WB_BOOT_ROM
64
`define WB_DPRAM
65
 
66 44 unneback
`define IO_DFF_OE
67
`define O_DFF
68
 
69 40 unneback
`endif
70
 
71
`ifdef PLL
72
`ifndef SYNC_RST
73
`define SYNC_RST
74
`endif
75
`endif
76
 
77
`ifdef SYNC_RST
78
`ifndef GBUF
79
`define GBUF
80
`endif
81
`endif
82
 
83
`ifdef WB_DPRAM
84
`ifndef DPRAM_2R2W
85
`define DPRAM_2R2W
86
`endif
87
`ifndef SPR
88
`define SPR
89
`endif
90
`endif
91
 
92
`ifdef WB3_ARBITER_TYPE1
93 42 unneback
`ifndef SPR
94
`define SPR
95
`endif
96 40 unneback
`ifndef MUX_ANDOR
97
`define MUX_ANDOR
98
`endif
99
`endif
100
 
101
`ifdef WB3WB3_BRIDGE
102
`ifndef CNT_SHREG_CE_CLEAR
103
`define CNT_SHREG_CE_CLEAR
104
`endif
105
`ifndef DFF
106
`define DFF
107
`endif
108
`ifndef DFF_CE
109
`define DFF_CE
110
`endif
111
`ifndef CNT_SHREG_CE_CLEAR
112
`define CNT_SHREG_CE_CLEAR
113
`endif
114
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
115
`define FIFO_2R2W_ASYNC_SIMPLEX
116
`endif
117
`endif
118
 
119
`ifdef MULTS18X18
120
`ifndef MULTS
121
`define MULTS
122
`endif
123
`endif
124
 
125
`ifdef SHIFT_UNIT_32
126
`ifndef MULTS
127
`define MULTS
128
`endif
129
`endif
130
 
131
`ifdef MUX2_ANDOR
132
`ifndef MUX_ANDOR
133
`define MUX_ANDOR
134
`endif
135
`endif
136
 
137
`ifdef MUX3_ANDOR
138
`ifndef MUX_ANDOR
139
`define MUX_ANDOR
140
`endif
141
`endif
142
 
143
`ifdef MUX4_ANDOR
144
`ifndef MUX_ANDOR
145
`define MUX_ANDOR
146
`endif
147
`endif
148
 
149
`ifdef MUX5_ANDOR
150
`ifndef MUX_ANDOR
151
`define MUX_ANDOR
152
`endif
153
`endif
154
 
155
`ifdef MUX6_ANDOR
156
`ifndef MUX_ANDOR
157
`define MUX_ANDOR
158
`endif
159
`endif
160
 
161
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
162
`ifndef CNT_BIN_CE
163
`define CNT_BIN_CE
164
`endif
165
`ifndef DPRAM_1R1W
166
`define DPRAM_1R1W
167
`endif
168
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
169
`define CNT_BIN_CE_REW_Q_ZQ_L1
170
`endif
171
`endif
172
 
173
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
174
`ifndef CNT_LFSR_CE
175
`define CNT_LFSR_CE
176
`endif
177
`ifndef DPRAM_2R2W
178
`define DPRAM_2R2W
179
`endif
180
`ifndef CNT_BIN_CE_REW_ZQ_L1
181
`define CNT_BIN_CE_REW_ZQ_L1
182
`endif
183
`endif
184
 
185
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
186
`ifndef CNT_GRAY_CE_BIN
187
`define CNT_GRAY_CE_BIN
188
`endif
189
`ifndef DPRAM_2R2W
190
`define DPRAM_2R2W
191
`endif
192
`ifndef FIFO_CMP_ASYNC
193
`define FIFO_CMP_ASYNC
194
`endif
195
`endif
196
 
197
`ifdef FIFO_2R2W_ASYNC
198
`ifndef FIFO_1R1W_ASYNC
199
`define FIFO_1R1W_ASYNC
200
`endif
201
`endif
202
 
203
`ifdef FIFO_1R1W_ASYNC
204
`ifndef CNT_GRAY_CE_BIN
205
`define CNT_GRAY_CE_BIN
206
`endif
207
`ifndef DPRAM_1R1W
208
`define DPRAM_1R1W
209
`endif
210
`ifndef FIFO_CMP_ASYNC
211
`define FIFO_CMP_ASYNC
212
`endif
213
`endif
214
 
215
`ifdef FIFO_CMP_ASYNC
216
`ifndef DFF_SR
217
`define DFF_SR
218
`endif
219
`ifndef DFF
220
`define DFF
221
`endif
222
`endif
223 6 unneback
//////////////////////////////////////////////////////////////////////
224
////                                                              ////
225
////  Versatile library, clock and reset                          ////
226
////                                                              ////
227
////  Description                                                 ////
228
////  Logic related to clock and reset                            ////
229
////                                                              ////
230
////                                                              ////
231
////  To Do:                                                      ////
232
////   - add more different registers                             ////
233
////                                                              ////
234
////  Author(s):                                                  ////
235
////      - Michael Unneback, unneback@opencores.org              ////
236
////        ORSoC AB                                              ////
237
////                                                              ////
238
//////////////////////////////////////////////////////////////////////
239
////                                                              ////
240
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
241
////                                                              ////
242
//// This source file may be used and distributed without         ////
243
//// restriction provided that this copyright statement is not    ////
244
//// removed from the file and that any derivative work contains  ////
245
//// the original copyright notice and the associated disclaimer. ////
246
////                                                              ////
247
//// This source file is free software; you can redistribute it   ////
248
//// and/or modify it under the terms of the GNU Lesser General   ////
249
//// Public License as published by the Free Software Foundation; ////
250
//// either version 2.1 of the License, or (at your option) any   ////
251
//// later version.                                               ////
252
////                                                              ////
253
//// This source is distributed in the hope that it will be       ////
254
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
255
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
256
//// PURPOSE.  See the GNU Lesser General Public License for more ////
257
//// details.                                                     ////
258
////                                                              ////
259
//// You should have received a copy of the GNU Lesser General    ////
260
//// Public License along with this source; if not, download it   ////
261
//// from http://www.opencores.org/lgpl.shtml                     ////
262
////                                                              ////
263
//////////////////////////////////////////////////////////////////////
264
 
265
// Global buffer
266
// usage:
267
// use to enable global buffers for high fan out signals such as clock and reset
268
 
269
`ifdef ACTEL
270 40 unneback
`ifdef GBUF
271 6 unneback
`timescale 1 ns/100 ps
272
// Version: 8.4 8.4.0.33
273
module gbuf(GL,CLK);
274
output GL;
275
input  CLK;
276
 
277
    wire GND;
278
 
279
    GND GND_1_net(.Y(GND));
280
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
281
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
282
 
283
endmodule
284
`timescale 1 ns/1 ns
285 40 unneback
`define MODULE gbuf
286
module `BASE`MODULE ( i, o);
287
`undef MODULE
288 6 unneback
input i;
289
output o;
290
`ifdef SIM_GBUF
291
assign o=i;
292
`else
293
gbuf gbuf_i0 ( .CLK(i), .GL(o));
294
`endif
295
endmodule
296 40 unneback
`endif
297 33 unneback
 
298 6 unneback
`else
299 33 unneback
 
300 40 unneback
`ifdef ALTERA
301
`ifdef GBUF
302 21 unneback
//altera
303 40 unneback
`define MODULE gbuf
304
module `BASE`MODULE ( i, o);
305
`undef MODULE
306 33 unneback
input i;
307
output o;
308
assign o = i;
309
endmodule
310 40 unneback
`endif
311 33 unneback
 
312 6 unneback
`else
313
 
314 40 unneback
`ifdef GBUF
315 6 unneback
`timescale 1 ns/100 ps
316 40 unneback
`define MODULE
317
module `BASE`MODULE ( i, o);
318
`undef MODULE
319 6 unneback
input i;
320
output o;
321
assign o = i;
322
endmodule
323 40 unneback
`endif
324 6 unneback
`endif // ALTERA
325
`endif //ACTEL
326
 
327 40 unneback
`ifdef SYNC_RST
328 6 unneback
// sync reset
329 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
330 6 unneback
// output active high global reset sync with two DFFs 
331
`timescale 1 ns/100 ps
332 40 unneback
`define MODULE sync_rst
333
module `BASE`MODULE ( rst_n_i, rst_o, clk);
334
`undef MODULE
335 6 unneback
input rst_n_i, clk;
336
output rst_o;
337 18 unneback
reg [1:0] tmp;
338 6 unneback
always @ (posedge clk or negedge rst_n_i)
339
if (!rst_n_i)
340 17 unneback
        tmp <= 2'b11;
341 6 unneback
else
342 33 unneback
        tmp <= {1'b0,tmp[1]};
343 40 unneback
`define MODULE gbuf
344
`BASE`MODULE buf_i0( .i(tmp[0]), .o(rst_o));
345
`undef MODULE
346 6 unneback
endmodule
347 40 unneback
`endif
348 6 unneback
 
349 40 unneback
`ifdef PLL
350 6 unneback
// vl_pll
351
`ifdef ACTEL
352 32 unneback
///////////////////////////////////////////////////////////////////////////////
353 17 unneback
`timescale 1 ps/1 ps
354 40 unneback
`define MODULE pll
355
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
356
`undef MODULE
357 6 unneback
parameter index = 0;
358
parameter number_of_clk = 1;
359 17 unneback
parameter period_time_0 = 20000;
360
parameter period_time_1 = 20000;
361
parameter period_time_2 = 20000;
362
parameter lock_delay = 2000000;
363 6 unneback
input clk_i, rst_n_i;
364
output lock;
365
output reg [0:number_of_clk-1] clk_o;
366
output [0:number_of_clk-1] rst_o;
367
 
368
`ifdef SIM_PLL
369
 
370
always
371
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
372
 
373
generate if (number_of_clk > 1)
374
always
375
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
376
endgenerate
377
 
378
generate if (number_of_clk > 2)
379
always
380
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
381
endgenerate
382
 
383
genvar i;
384
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
385
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
386
end
387
endgenerate
388
 
389
assign #lock_delay lock = rst_n_i;
390
 
391
endmodule
392
`else
393
generate if (number_of_clk==1 & index==0) begin
394
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
395
end
396
endgenerate // index==0
397
generate if (number_of_clk==1 & index==1) begin
398
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
399
end
400
endgenerate // index==1
401
generate if (number_of_clk==1 & index==2) begin
402
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
403
end
404
endgenerate // index==2
405
generate if (number_of_clk==1 & index==3) begin
406
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
407
end
408
endgenerate // index==0
409
 
410
generate if (number_of_clk==2 & index==0) begin
411
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
412
end
413
endgenerate // index==0
414
generate if (number_of_clk==2 & index==1) begin
415
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
416
end
417
endgenerate // index==1
418
generate if (number_of_clk==2 & index==2) begin
419
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
420
end
421
endgenerate // index==2
422
generate if (number_of_clk==2 & index==3) begin
423
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
424
end
425
endgenerate // index==0
426
 
427
generate if (number_of_clk==3 & index==0) begin
428
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
429
end
430
endgenerate // index==0
431
generate if (number_of_clk==3 & index==1) begin
432
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
433
end
434
endgenerate // index==1
435
generate if (number_of_clk==3 & index==2) begin
436
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
437
end
438
endgenerate // index==2
439
generate if (number_of_clk==3 & index==3) begin
440
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
441
end
442
endgenerate // index==0
443
 
444
genvar i;
445
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
446 40 unneback
`define MODULE sync_rst
447
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
448
`undef MODULE
449 6 unneback
end
450
endgenerate
451
endmodule
452
`endif
453 32 unneback
///////////////////////////////////////////////////////////////////////////////
454 6 unneback
 
455
`else
456
 
457 32 unneback
///////////////////////////////////////////////////////////////////////////////
458 6 unneback
`ifdef ALTERA
459
 
460 32 unneback
`timescale 1 ps/1 ps
461 40 unneback
`define MODULE pll
462
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
463
`undef MODULE
464 32 unneback
parameter index = 0;
465
parameter number_of_clk = 1;
466
parameter period_time_0 = 20000;
467
parameter period_time_1 = 20000;
468
parameter period_time_2 = 20000;
469
parameter period_time_3 = 20000;
470
parameter period_time_4 = 20000;
471
parameter lock_delay = 2000000;
472
input clk_i, rst_n_i;
473
output lock;
474
output reg [0:number_of_clk-1] clk_o;
475
output [0:number_of_clk-1] rst_o;
476
 
477
`ifdef SIM_PLL
478
 
479
always
480
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
481
 
482
generate if (number_of_clk > 1)
483
always
484
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
485
endgenerate
486
 
487
generate if (number_of_clk > 2)
488
always
489
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
490
endgenerate
491
 
492 33 unneback
generate if (number_of_clk > 3)
493 32 unneback
always
494
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
495
endgenerate
496
 
497 33 unneback
generate if (number_of_clk > 4)
498 32 unneback
always
499
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
500
endgenerate
501
 
502
genvar i;
503
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
504
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
505
end
506
endgenerate
507
 
508 33 unneback
//assign #lock_delay lock = rst_n_i;
509
assign lock = rst_n_i;
510 32 unneback
 
511
endmodule
512 6 unneback
`else
513
 
514 33 unneback
`ifdef VL_PLL0
515
`ifdef VL_PLL0_CLK1
516
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
517
`endif
518
`ifdef VL_PLL0_CLK2
519
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
520
`endif
521
`ifdef VL_PLL0_CLK3
522
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
523
`endif
524
`ifdef VL_PLL0_CLK4
525
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
526
`endif
527
`ifdef VL_PLL0_CLK5
528
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
529
`endif
530
`endif
531 32 unneback
 
532 33 unneback
`ifdef VL_PLL1
533
`ifdef VL_PLL1_CLK1
534
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
535
`endif
536
`ifdef VL_PLL1_CLK2
537
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
538
`endif
539
`ifdef VL_PLL1_CLK3
540
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
541
`endif
542
`ifdef VL_PLL1_CLK4
543
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
544
`endif
545
`ifdef VL_PLL1_CLK5
546
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
547
`endif
548
`endif
549 32 unneback
 
550 33 unneback
`ifdef VL_PLL2
551
`ifdef VL_PLL2_CLK1
552
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
553
`endif
554
`ifdef VL_PLL2_CLK2
555
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
556
`endif
557
`ifdef VL_PLL2_CLK3
558
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
559
`endif
560
`ifdef VL_PLL2_CLK4
561
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
562
`endif
563
`ifdef VL_PLL2_CLK5
564
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
565
`endif
566
`endif
567 32 unneback
 
568 33 unneback
`ifdef VL_PLL3
569
`ifdef VL_PLL3_CLK1
570
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
571
`endif
572
`ifdef VL_PLL3_CLK2
573
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
574
`endif
575
`ifdef VL_PLL3_CLK3
576
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
577
`endif
578
`ifdef VL_PLL3_CLK4
579
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
580
`endif
581
`ifdef VL_PLL3_CLK5
582
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
583
`endif
584
`endif
585 32 unneback
 
586
genvar i;
587
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
588 40 unneback
`define MODULE sync_rst
589
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
590
`undef MODULE
591 32 unneback
end
592
endgenerate
593
endmodule
594
`endif
595
///////////////////////////////////////////////////////////////////////////////
596
 
597
`else
598
 
599 6 unneback
// generic PLL
600 17 unneback
`timescale 1 ps/1 ps
601 40 unneback
`define MODULE pll
602
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
603
`undef MODULE
604 6 unneback
parameter index = 0;
605
parameter number_of_clk = 1;
606 17 unneback
parameter period_time_0 = 20000;
607
parameter period_time_1 = 20000;
608
parameter period_time_2 = 20000;
609 6 unneback
parameter lock_delay = 2000;
610
input clk_i, rst_n_i;
611
output lock;
612
output reg [0:number_of_clk-1] clk_o;
613
output [0:number_of_clk-1] rst_o;
614
 
615
always
616
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
617
 
618
generate if (number_of_clk > 1)
619
always
620
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
621
endgenerate
622
 
623
generate if (number_of_clk > 2)
624
always
625
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
626
endgenerate
627
 
628
genvar i;
629
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
630 40 unneback
`define MODULE sync_rst
631
     `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
632
`undef MODULE
633 6 unneback
end
634
endgenerate
635
 
636
assign #lock_delay lock = rst_n_i;
637
 
638
endmodule
639
 
640
`endif //altera
641 17 unneback
`endif //actel
642 40 unneback
`undef MODULE
643
`endif//////////////////////////////////////////////////////////////////////
644 6 unneback
////                                                              ////
645
////  Versatile library, registers                                ////
646
////                                                              ////
647
////  Description                                                 ////
648
////  Different type of registers                                 ////
649
////                                                              ////
650
////                                                              ////
651
////  To Do:                                                      ////
652
////   - add more different registers                             ////
653
////                                                              ////
654
////  Author(s):                                                  ////
655
////      - Michael Unneback, unneback@opencores.org              ////
656
////        ORSoC AB                                              ////
657
////                                                              ////
658
//////////////////////////////////////////////////////////////////////
659
////                                                              ////
660
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
661
////                                                              ////
662
//// This source file may be used and distributed without         ////
663
//// restriction provided that this copyright statement is not    ////
664
//// removed from the file and that any derivative work contains  ////
665
//// the original copyright notice and the associated disclaimer. ////
666
////                                                              ////
667
//// This source file is free software; you can redistribute it   ////
668
//// and/or modify it under the terms of the GNU Lesser General   ////
669
//// Public License as published by the Free Software Foundation; ////
670
//// either version 2.1 of the License, or (at your option) any   ////
671
//// later version.                                               ////
672
////                                                              ////
673
//// This source is distributed in the hope that it will be       ////
674
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
675
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
676
//// PURPOSE.  See the GNU Lesser General Public License for more ////
677
//// details.                                                     ////
678
////                                                              ////
679
//// You should have received a copy of the GNU Lesser General    ////
680
//// Public License along with this source; if not, download it   ////
681
//// from http://www.opencores.org/lgpl.shtml                     ////
682
////                                                              ////
683
//////////////////////////////////////////////////////////////////////
684
 
685 40 unneback
`ifdef DFF
686
`define MODULE dff
687
module `BASE`MODULE ( d, q, clk, rst);
688
`undef MODULE
689 6 unneback
        parameter width = 1;
690
        parameter reset_value = 0;
691
 
692
        input [width-1:0] d;
693
        input clk, rst;
694
        output reg [width-1:0] q;
695
 
696
        always @ (posedge clk or posedge rst)
697
        if (rst)
698
                q <= reset_value;
699
        else
700
                q <= d;
701
 
702
endmodule
703 40 unneback
`endif
704 6 unneback
 
705 40 unneback
`ifdef DFF_ARRAY
706
`define MODULE dff_array
707
module `BASE`MODULE ( d, q, clk, rst);
708
`undef MODULE
709 6 unneback
 
710
        parameter width = 1;
711
        parameter depth = 2;
712
        parameter reset_value = 1'b0;
713
 
714
        input [width-1:0] d;
715
        input clk, rst;
716
        output [width-1:0] q;
717
        reg  [0:depth-1] q_tmp [width-1:0];
718
        integer i;
719
        always @ (posedge clk or posedge rst)
720
        if (rst) begin
721
            for (i=0;i<depth;i=i+1)
722
                q_tmp[i] <= {width{reset_value}};
723
        end else begin
724
            q_tmp[0] <= d;
725
            for (i=1;i<depth;i=i+1)
726
                q_tmp[i] <= q_tmp[i-1];
727
        end
728
 
729
    assign q = q_tmp[depth-1];
730
 
731
endmodule
732 40 unneback
`endif
733 6 unneback
 
734 40 unneback
`ifdef DFF_CE
735
`define MODULE dff_ce
736
module `BASE`MODULE ( d, ce, q, clk, rst);
737
`undef MODULE
738 6 unneback
 
739
        parameter width = 1;
740
        parameter reset_value = 0;
741
 
742
        input [width-1:0] d;
743
        input ce, clk, rst;
744
        output reg [width-1:0] q;
745
 
746
        always @ (posedge clk or posedge rst)
747
        if (rst)
748
                q <= reset_value;
749
        else
750
                if (ce)
751
                        q <= d;
752
 
753
endmodule
754 40 unneback
`endif
755 6 unneback
 
756 40 unneback
`ifdef DFF_CE_CLEAR
757
`define MODULE dff_ce_clear
758
module `BASE`MODULE ( d, ce, clear, q, clk, rst);
759
`undef MODULE
760 8 unneback
 
761
        parameter width = 1;
762
        parameter reset_value = 0;
763
 
764
        input [width-1:0] d;
765 10 unneback
        input ce, clear, clk, rst;
766 8 unneback
        output reg [width-1:0] q;
767
 
768
        always @ (posedge clk or posedge rst)
769
        if (rst)
770
            q <= reset_value;
771
        else
772
            if (ce)
773
                if (clear)
774
                    q <= {width{1'b0}};
775
                else
776
                    q <= d;
777
 
778
endmodule
779 40 unneback
`endif
780 8 unneback
 
781 40 unneback
`ifdef DF_CE_SET
782
`define MODULE dff_ce_set
783
module `BASE`MODULE ( d, ce, set, q, clk, rst);
784
`undef MODULE
785 24 unneback
 
786
        parameter width = 1;
787
        parameter reset_value = 0;
788
 
789
        input [width-1:0] d;
790
        input ce, set, clk, rst;
791
        output reg [width-1:0] q;
792
 
793
        always @ (posedge clk or posedge rst)
794
        if (rst)
795
            q <= reset_value;
796
        else
797
            if (ce)
798
                if (set)
799
                    q <= {width{1'b1}};
800
                else
801
                    q <= d;
802
 
803
endmodule
804 40 unneback
`endif
805 24 unneback
 
806 40 unneback
`ifdef SPR
807
`define MODULE spr
808
module `BASE`MODULE ( sp, r, q, clk, rst);
809
`undef MODULE
810
 
811 29 unneback
        parameter width = 1;
812
        parameter reset_value = 0;
813
 
814
        input sp, r;
815
        output reg q;
816
        input clk, rst;
817
 
818
        always @ (posedge clk or posedge rst)
819
        if (rst)
820
            q <= reset_value;
821
        else
822
            if (sp)
823
                q <= 1'b1;
824
            else if (r)
825
                q <= 1'b0;
826
 
827
endmodule
828 40 unneback
`endif
829 29 unneback
 
830 40 unneback
`ifdef SRP
831
`define MODULE srp
832
module `BASE`MODULE ( s, rp, q, clk, rst);
833
`undef MODULE
834
 
835 29 unneback
        parameter width = 1;
836
        parameter reset_value = 0;
837
 
838
        input s, rp;
839
        output reg q;
840
        input clk, rst;
841
 
842
        always @ (posedge clk or posedge rst)
843
        if (rst)
844
            q <= reset_value;
845
        else
846
            if (rp)
847
                q <= 1'b0;
848
            else if (s)
849
                q <= 1'b1;
850
 
851
endmodule
852 40 unneback
`endif
853 29 unneback
 
854 40 unneback
`ifdef ALTERA
855 29 unneback
 
856 40 unneback
`ifdef DFF_SR
857 6 unneback
// megafunction wizard: %LPM_FF%
858
// GENERATION: STANDARD
859
// VERSION: WM1.0
860
// MODULE: lpm_ff 
861
 
862
// ============================================================
863
// File Name: dff_sr.v
864
// Megafunction Name(s):
865
//                      lpm_ff
866
//
867
// Simulation Library Files(s):
868
//                      lpm
869
// ============================================================
870
// ************************************************************
871
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
872
//
873
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
874
// ************************************************************
875
 
876
 
877
//Copyright (C) 1991-2010 Altera Corporation
878
//Your use of Altera Corporation's design tools, logic functions 
879
//and other software and tools, and its AMPP partner logic 
880
//functions, and any output files from any of the foregoing 
881
//(including device programming or simulation files), and any 
882
//associated documentation or information are expressly subject 
883
//to the terms and conditions of the Altera Program License 
884
//Subscription Agreement, Altera MegaCore Function License 
885
//Agreement, or other applicable license agreement, including, 
886
//without limitation, that your use is for the sole purpose of 
887
//programming logic devices manufactured by Altera and sold by 
888
//Altera or its authorized distributors.  Please refer to the 
889
//applicable agreement for further details.
890
 
891
 
892
// synopsys translate_off
893
`timescale 1 ps / 1 ps
894
// synopsys translate_on
895 40 unneback
`define MODULE dff_sr
896
module `BASE`MODULE (
897
`undef MODULE
898
 
899 6 unneback
        aclr,
900
        aset,
901
        clock,
902
        data,
903
        q);
904
 
905
        input     aclr;
906
        input     aset;
907
        input     clock;
908
        input     data;
909
        output    q;
910
 
911
        wire [0:0] sub_wire0;
912
        wire [0:0] sub_wire1 = sub_wire0[0:0];
913
        wire  q = sub_wire1;
914
        wire  sub_wire2 = data;
915
        wire  sub_wire3 = sub_wire2;
916
 
917
        lpm_ff  lpm_ff_component (
918
                                .aclr (aclr),
919
                                .clock (clock),
920
                                .data (sub_wire3),
921
                                .aset (aset),
922
                                .q (sub_wire0)
923
                                // synopsys translate_off
924
                                ,
925
                                .aload (),
926
                                .enable (),
927
                                .sclr (),
928
                                .sload (),
929
                                .sset ()
930
                                // synopsys translate_on
931
                                );
932
        defparam
933
                lpm_ff_component.lpm_fftype = "DFF",
934
                lpm_ff_component.lpm_type = "LPM_FF",
935
                lpm_ff_component.lpm_width = 1;
936
 
937
 
938
endmodule
939
 
940
// ============================================================
941
// CNX file retrieval info
942
// ============================================================
943
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
944
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
945
// Retrieval info: PRIVATE: ASET NUMERIC "1"
946
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
947
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
948
// Retrieval info: PRIVATE: DFF NUMERIC "1"
949
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
950
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
951
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
952
// Retrieval info: PRIVATE: SSET NUMERIC "0"
953
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
954
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
955
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
956
// Retrieval info: PRIVATE: nBit NUMERIC "1"
957
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
958
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
959
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
960
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
961
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
962
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
963
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
964
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
965
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
966
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
967
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
968
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
969
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
970
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
971
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
972
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
973
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
974
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
975
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
976
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
977
// Retrieval info: LIB_FILE: lpm
978 40 unneback
`endif
979 6 unneback
 
980
`else
981
 
982 40 unneback
`ifdef DFF_SR
983
`define MODULE dff_sr
984
module `BASE`MODULE ( aclr, aset, clock, data, q);
985
`undef MODULE
986 6 unneback
 
987
    input         aclr;
988
    input         aset;
989
    input         clock;
990
    input         data;
991
    output reg    q;
992
 
993
   always @ (posedge clock or posedge aclr or posedge aset)
994
     if (aclr)
995
       q <= 1'b0;
996
     else if (aset)
997
       q <= 1'b1;
998
     else
999
       q <= data;
1000
 
1001
endmodule
1002 40 unneback
`endif
1003 6 unneback
 
1004
`endif
1005
 
1006
// LATCH
1007
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
1008
`ifdef ALTERA
1009 40 unneback
 
1010
`ifdef LATCH
1011
`define MODULE latch
1012
module `BASE`MODULE ( d, le, q, clk);
1013
`undef MODULE
1014 6 unneback
input d, le;
1015
output q;
1016
input clk;
1017
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
1018
endmodule
1019 40 unneback
`endif
1020
 
1021 6 unneback
`else
1022 40 unneback
 
1023
`ifdef LATCH
1024
`define MODULE latch
1025
module `BASE`MODULE ( d, le, q, clk);
1026
`undef MODULE
1027 6 unneback
input d, le;
1028
output q;
1029
input clk;/*
1030
   always @ (posedge direction_set or posedge direction_clr)
1031
     if (direction_clr)
1032
       direction <= going_empty;
1033
     else
1034
       direction <= going_full;*/
1035
endmodule
1036 15 unneback
`endif
1037
 
1038 40 unneback
`endif
1039
 
1040
`ifdef SHREG
1041
`define MODULE shreg
1042
module `BASE`MODULE ( d, q, clk, rst);
1043
`undef MODULE
1044
 
1045 17 unneback
parameter depth = 10;
1046
input d;
1047
output q;
1048
input clk, rst;
1049
 
1050
reg [1:depth] dffs;
1051
 
1052
always @ (posedge clk or posedge rst)
1053
if (rst)
1054
    dffs <= {depth{1'b0}};
1055
else
1056
    dffs <= {d,dffs[1:depth-1]};
1057
assign q = dffs[depth];
1058
endmodule
1059 40 unneback
`endif
1060 17 unneback
 
1061 40 unneback
`ifdef SHREG_CE
1062
`define MODULE shreg_ce
1063
module `BASE`MODULE ( d, ce, q, clk, rst);
1064
`undef MODULE
1065 17 unneback
parameter depth = 10;
1066
input d, ce;
1067
output q;
1068
input clk, rst;
1069
 
1070
reg [1:depth] dffs;
1071
 
1072
always @ (posedge clk or posedge rst)
1073
if (rst)
1074
    dffs <= {depth{1'b0}};
1075
else
1076
    if (ce)
1077
        dffs <= {d,dffs[1:depth-1]};
1078
assign q = dffs[depth];
1079
endmodule
1080 40 unneback
`endif
1081 17 unneback
 
1082 40 unneback
`ifdef DELAY
1083
`define MODULE delay
1084
module `BASE`MODULE ( d, q, clk, rst);
1085
`undef MODULE
1086 15 unneback
parameter depth = 10;
1087
input d;
1088
output q;
1089
input clk, rst;
1090
 
1091
reg [1:depth] dffs;
1092
 
1093
always @ (posedge clk or posedge rst)
1094
if (rst)
1095
    dffs <= {depth{1'b0}};
1096
else
1097
    dffs <= {d,dffs[1:depth-1]};
1098
assign q = dffs[depth];
1099 17 unneback
endmodule
1100 40 unneback
`endif
1101 17 unneback
 
1102 40 unneback
`ifdef DELAY_EMPTYFLAG
1103
`define MODULE delay_emptyflag
1104 41 unneback
module `BASE`MODULE ( d, q, emptyflag, clk, rst);
1105 40 unneback
`undef MODULE
1106 17 unneback
parameter depth = 10;
1107
input d;
1108
output q, emptyflag;
1109
input clk, rst;
1110
 
1111
reg [1:depth] dffs;
1112
 
1113
always @ (posedge clk or posedge rst)
1114
if (rst)
1115
    dffs <= {depth{1'b0}};
1116
else
1117
    dffs <= {d,dffs[1:depth-1]};
1118
assign q = dffs[depth];
1119
assign emptyflag = !(|dffs);
1120
endmodule
1121 40 unneback
`endif
1122 17 unneback
//////////////////////////////////////////////////////////////////////
1123 6 unneback
////                                                              ////
1124 18 unneback
////  Logic functions                                             ////
1125
////                                                              ////
1126
////  Description                                                 ////
1127
////  Logic functions such as multiplexers                        ////
1128
////                                                              ////
1129
////                                                              ////
1130
////  To Do:                                                      ////
1131
////   -                                                          ////
1132
////                                                              ////
1133
////  Author(s):                                                  ////
1134
////      - Michael Unneback, unneback@opencores.org              ////
1135
////        ORSoC AB                                              ////
1136
////                                                              ////
1137
//////////////////////////////////////////////////////////////////////
1138
////                                                              ////
1139
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1140
////                                                              ////
1141
//// This source file may be used and distributed without         ////
1142
//// restriction provided that this copyright statement is not    ////
1143
//// removed from the file and that any derivative work contains  ////
1144
//// the original copyright notice and the associated disclaimer. ////
1145
////                                                              ////
1146
//// This source file is free software; you can redistribute it   ////
1147
//// and/or modify it under the terms of the GNU Lesser General   ////
1148
//// Public License as published by the Free Software Foundation; ////
1149
//// either version 2.1 of the License, or (at your option) any   ////
1150
//// later version.                                               ////
1151
////                                                              ////
1152
//// This source is distributed in the hope that it will be       ////
1153
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1154
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1155
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1156
//// details.                                                     ////
1157
////                                                              ////
1158
//// You should have received a copy of the GNU Lesser General    ////
1159
//// Public License along with this source; if not, download it   ////
1160
//// from http://www.opencores.org/lgpl.shtml                     ////
1161
////                                                              ////
1162
//////////////////////////////////////////////////////////////////////
1163 40 unneback
`ifdef MUX_ANDOR
1164
`define MODULE mux_andor
1165
module `BASE`MODULE ( a, sel, dout);
1166
`undef MODULE
1167 36 unneback
 
1168
parameter width = 32;
1169
parameter nr_of_ports = 4;
1170
 
1171
input [nr_of_ports*width-1:0] a;
1172
input [nr_of_ports-1:0] sel;
1173
output reg [width-1:0] dout;
1174
 
1175 38 unneback
integer i,j;
1176
 
1177 36 unneback
always @ (a, sel)
1178
begin
1179
    dout = a[width-1:0] & {width{sel[0]}};
1180 42 unneback
    for (i=1;i<nr_of_ports;i=i+1)
1181
        for (j=0;j<width;j=j+1)
1182
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
1183 36 unneback
end
1184
 
1185
endmodule
1186 40 unneback
`endif
1187 36 unneback
 
1188 40 unneback
`ifdef MUX2_ANDOR
1189
`define MODULE mux2_andor
1190
module `BASE`MODULE ( a1, a0, sel, dout);
1191
`undef MODULE
1192 18 unneback
 
1193 34 unneback
parameter width = 32;
1194 35 unneback
localparam nr_of_ports = 2;
1195 34 unneback
input [width-1:0] a1, a0;
1196
input [nr_of_ports-1:0] sel;
1197
output [width-1:0] dout;
1198
 
1199 40 unneback
`define MODULE mux_andor
1200
`BASE`MODULE
1201 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1202 36 unneback
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
1203 40 unneback
`undef MODULE
1204
 
1205 34 unneback
endmodule
1206 40 unneback
`endif
1207 34 unneback
 
1208 40 unneback
`ifdef MUX3_ANDOR
1209
`define MODULE mux3_andor
1210
module `BASE`MODULE ( a2, a1, a0, sel, dout);
1211
`undef MODULE
1212 34 unneback
 
1213
parameter width = 32;
1214 35 unneback
localparam nr_of_ports = 3;
1215 34 unneback
input [width-1:0] a2, a1, a0;
1216
input [nr_of_ports-1:0] sel;
1217
output [width-1:0] dout;
1218
 
1219 40 unneback
`define MODULE mux_andor
1220
`BASE`MODULE
1221 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1222 36 unneback
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
1223 40 unneback
`undef MODULE
1224 34 unneback
endmodule
1225 40 unneback
`endif
1226 34 unneback
 
1227 40 unneback
`ifdef MUX4_ANDOR
1228
`define MODULE mux4_andor
1229
module `BASE`MODULE ( a3, a2, a1, a0, sel, dout);
1230
`undef MODULE
1231 18 unneback
 
1232
parameter width = 32;
1233 35 unneback
localparam nr_of_ports = 4;
1234 18 unneback
input [width-1:0] a3, a2, a1, a0;
1235
input [nr_of_ports-1:0] sel;
1236 22 unneback
output [width-1:0] dout;
1237 18 unneback
 
1238 40 unneback
`define MODULE mux_andor
1239
`BASE`MODULE
1240 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1241 36 unneback
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
1242 40 unneback
`undef MODULE
1243 18 unneback
 
1244
endmodule
1245 40 unneback
`endif
1246 18 unneback
 
1247 40 unneback
`ifdef MUX5_ANDOR
1248
`define MODULE mux5_andor
1249
module `BASE`MODULE ( a4, a3, a2, a1, a0, sel, dout);
1250
`undef MODULE
1251 18 unneback
 
1252
parameter width = 32;
1253 35 unneback
localparam nr_of_ports = 5;
1254 18 unneback
input [width-1:0] a4, a3, a2, a1, a0;
1255
input [nr_of_ports-1:0] sel;
1256 22 unneback
output [width-1:0] dout;
1257 18 unneback
 
1258 40 unneback
`define MODULE mux_andor
1259
`BASE`MODULE
1260 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1261 36 unneback
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1262 40 unneback
`undef MODULE
1263 18 unneback
 
1264
endmodule
1265 40 unneback
`endif
1266 18 unneback
 
1267 40 unneback
`ifdef MUX6_ANDOR
1268
`define MODULE mux6_andor
1269
module `BASE`MODULE ( a5, a4, a3, a2, a1, a0, sel, dout);
1270
`undef MODULE
1271 18 unneback
 
1272
parameter width = 32;
1273 35 unneback
localparam nr_of_ports = 6;
1274 18 unneback
input [width-1:0] a5, a4, a3, a2, a1, a0;
1275
input [nr_of_ports-1:0] sel;
1276 22 unneback
output [width-1:0] dout;
1277 18 unneback
 
1278 40 unneback
`define MODULE mux_andor
1279
`BASE`MODULE
1280 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1281 36 unneback
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1282 40 unneback
`undef MODULE
1283 18 unneback
 
1284
endmodule
1285 40 unneback
`endif
1286 43 unneback
 
1287
`ifdef PARITY
1288
 
1289
`define MODULE parity_generate
1290
module `BASE`MODULE (data, parity);
1291
`undef MODULE
1292
parameter word_size = 32;
1293
parameter chunk_size = 8;
1294
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1295
input [word_size-1:0] data;
1296
output reg [word_size/chunk_size-1:0] parity;
1297
integer i,j;
1298
always @ (data)
1299
for (i=0;i<word_size/chunk_size;i=i+1) begin
1300
    parity[i] = parity_type;
1301
    for (j=0;j<chunk_size;j=j+1) begin
1302
        parity[i] = data[i+j] ^ parity[i];
1303
    end
1304
end
1305
endmodule
1306
 
1307
`define MODULE parity_check
1308
module `BASE`MODULE( data, parity, parity_error);
1309
`undef MODULE
1310
parameter word_size = 32;
1311
parameter chunk_size = 8;
1312
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1313
input [word_size-1:0] data;
1314
input [word_size/chunk_size-1:0] parity;
1315
output parity_error;
1316 44 unneback
reg [word_size/chunk_size-1:0] error_flag;
1317 43 unneback
integer i,j;
1318
always @ (data or parity)
1319
for (i=0;i<word_size/chunk_size;i=i+1) begin
1320
    error_flag[i] = parity[i] ^ parity_type;
1321
    for (j=0;j<chunk_size;j=j+1) begin
1322
        error_flag[i] = data[i+j] ^ error_flag[i];
1323
    end
1324
end
1325
assign parity_error = |error_flag;
1326
endmodule
1327
 
1328 44 unneback
`endif//////////////////////////////////////////////////////////////////////
1329
////                                                              ////
1330
////  IO functions                                                ////
1331
////                                                              ////
1332
////  Description                                                 ////
1333
////  IO functions such as IOB flip-flops                         ////
1334
////                                                              ////
1335
////                                                              ////
1336
////  To Do:                                                      ////
1337
////   -                                                          ////
1338
////                                                              ////
1339
////  Author(s):                                                  ////
1340
////      - Michael Unneback, unneback@opencores.org              ////
1341
////        ORSoC AB                                              ////
1342
////                                                              ////
1343 18 unneback
//////////////////////////////////////////////////////////////////////
1344
////                                                              ////
1345 44 unneback
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1346
////                                                              ////
1347
//// This source file may be used and distributed without         ////
1348
//// restriction provided that this copyright statement is not    ////
1349
//// removed from the file and that any derivative work contains  ////
1350
//// the original copyright notice and the associated disclaimer. ////
1351
////                                                              ////
1352
//// This source file is free software; you can redistribute it   ////
1353
//// and/or modify it under the terms of the GNU Lesser General   ////
1354
//// Public License as published by the Free Software Foundation; ////
1355
//// either version 2.1 of the License, or (at your option) any   ////
1356
//// later version.                                               ////
1357
////                                                              ////
1358
//// This source is distributed in the hope that it will be       ////
1359
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1360
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1361
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1362
//// details.                                                     ////
1363
////                                                              ////
1364
//// You should have received a copy of the GNU Lesser General    ////
1365
//// Public License along with this source; if not, download it   ////
1366
//// from http://www.opencores.org/lgpl.shtml                     ////
1367
////                                                              ////
1368
//////////////////////////////////////////////////////////////////////
1369
 
1370
`ifdef O_DFF
1371
`define MODULE o_dff
1372
module `BASE`MODULE (d_i, o_pad, clk, rst);
1373
`undef MODULE
1374
parameter width = 1;
1375
input [width-1:0]  d_i;
1376
output [width-1:0] o_pad;
1377
input clk, rst;
1378
wire [width-1:0] d_i_int `SYN_KEEP;
1379
assign d_i_int = d_i;
1380
genvar i;
1381
for (i=0;i<width;i=i+1) begin
1382
    always @ (posedge clk or posedge rst)
1383
    if (rst)
1384
        o_pad[i] <= 1'b0;
1385
    else
1386
        o_pad[i] <= d_i_int[i];
1387
end
1388
endgenerate
1389
endmodule
1390
`endif
1391
 
1392
`ifdef IO_DFF_OE
1393
`define MODULE io_dff_oe
1394
module `BASE`MODULE ( d_i, d_o, oe, io_pad, clk, rst);
1395
`undef MODULE
1396
parameter width = 1;
1397
input  [width-1:0] d_o;
1398
output reg [width-1:0] d_i;
1399
input oe;
1400
inout [width-1:0] io_pad;
1401
input clk, rst;
1402
wire [width-1:0] oe_d `SYN_KEEP;
1403
reg [width-1:0] oe_q;
1404
reg [width-1:0] d_o_q;
1405
assign oe_d = {width{oe}};
1406
genvar i;
1407
generate
1408
for (i=0;i<width;i=i+1) begin
1409
    always @ (posedge clk or posedge rst)
1410
    if (rst)
1411
        oe_q[i] <= 1'b0;
1412
    else
1413
        oe_q[i] <= oe_d[i];
1414
    always @ (posedge clk or posedge rst)
1415
    if (rst)
1416
        d_o_q[i] <= 1'b0;
1417
    else
1418
        d_o_q[i] <= d_o[i];
1419
    always @ (posedge clk or posedge rst)
1420
    if (rst)
1421
        d_i[i] <= 1'b0;
1422
    else
1423
        d_i[i] <= io_pad[i];
1424
    assign io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
1425
end
1426
endgenerate
1427
endmodule
1428
`endif
1429
`ifdef CNT_BIN
1430
//////////////////////////////////////////////////////////////////////
1431
////                                                              ////
1432 6 unneback
////  Versatile counter                                           ////
1433
////                                                              ////
1434
////  Description                                                 ////
1435
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1436
////  counter                                                     ////
1437
////                                                              ////
1438
////  To Do:                                                      ////
1439
////   - add LFSR with more taps                                  ////
1440
////                                                              ////
1441
////  Author(s):                                                  ////
1442
////      - Michael Unneback, unneback@opencores.org              ////
1443
////        ORSoC AB                                              ////
1444
////                                                              ////
1445
//////////////////////////////////////////////////////////////////////
1446
////                                                              ////
1447
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1448
////                                                              ////
1449
//// This source file may be used and distributed without         ////
1450
//// restriction provided that this copyright statement is not    ////
1451
//// removed from the file and that any derivative work contains  ////
1452
//// the original copyright notice and the associated disclaimer. ////
1453
////                                                              ////
1454
//// This source file is free software; you can redistribute it   ////
1455
//// and/or modify it under the terms of the GNU Lesser General   ////
1456
//// Public License as published by the Free Software Foundation; ////
1457
//// either version 2.1 of the License, or (at your option) any   ////
1458
//// later version.                                               ////
1459
////                                                              ////
1460
//// This source is distributed in the hope that it will be       ////
1461
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1462
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1463
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1464
//// details.                                                     ////
1465
////                                                              ////
1466
//// You should have received a copy of the GNU Lesser General    ////
1467
//// Public License along with this source; if not, download it   ////
1468
//// from http://www.opencores.org/lgpl.shtml                     ////
1469
////                                                              ////
1470
//////////////////////////////////////////////////////////////////////
1471
 
1472
// binary counter
1473 22 unneback
 
1474 40 unneback
`define MODULE cnt_bin
1475
module `BASE`MODULE (
1476
`undef MODULE
1477
 q, rst, clk);
1478
 
1479 22 unneback
   parameter length = 4;
1480
   output [length:1] q;
1481
   input rst;
1482
   input clk;
1483
 
1484
   parameter clear_value = 0;
1485
   parameter set_value = 1;
1486
   parameter wrap_value = 0;
1487
   parameter level1_value = 15;
1488
 
1489
   reg  [length:1] qi;
1490
   wire [length:1] q_next;
1491
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1492
 
1493
   always @ (posedge clk or posedge rst)
1494
     if (rst)
1495
       qi <= {length{1'b0}};
1496
     else
1497
       qi <= q_next;
1498
 
1499
   assign q = qi;
1500
 
1501
endmodule
1502 40 unneback
`endif
1503
`ifdef CNT_BIN_CLEAR
1504 22 unneback
//////////////////////////////////////////////////////////////////////
1505
////                                                              ////
1506
////  Versatile counter                                           ////
1507
////                                                              ////
1508
////  Description                                                 ////
1509
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1510
////  counter                                                     ////
1511
////                                                              ////
1512
////  To Do:                                                      ////
1513
////   - add LFSR with more taps                                  ////
1514
////                                                              ////
1515
////  Author(s):                                                  ////
1516
////      - Michael Unneback, unneback@opencores.org              ////
1517
////        ORSoC AB                                              ////
1518
////                                                              ////
1519
//////////////////////////////////////////////////////////////////////
1520
////                                                              ////
1521
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1522
////                                                              ////
1523
//// This source file may be used and distributed without         ////
1524
//// restriction provided that this copyright statement is not    ////
1525
//// removed from the file and that any derivative work contains  ////
1526
//// the original copyright notice and the associated disclaimer. ////
1527
////                                                              ////
1528
//// This source file is free software; you can redistribute it   ////
1529
//// and/or modify it under the terms of the GNU Lesser General   ////
1530
//// Public License as published by the Free Software Foundation; ////
1531
//// either version 2.1 of the License, or (at your option) any   ////
1532
//// later version.                                               ////
1533
////                                                              ////
1534
//// This source is distributed in the hope that it will be       ////
1535
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1536
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1537
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1538
//// details.                                                     ////
1539
////                                                              ////
1540
//// You should have received a copy of the GNU Lesser General    ////
1541
//// Public License along with this source; if not, download it   ////
1542
//// from http://www.opencores.org/lgpl.shtml                     ////
1543
////                                                              ////
1544
//////////////////////////////////////////////////////////////////////
1545
 
1546
// binary counter
1547
 
1548 40 unneback
`define MODULE cnt_bin_clear
1549
module `BASE`MODULE (
1550
`undef MODULE
1551
 clear, q, rst, clk);
1552
 
1553 22 unneback
   parameter length = 4;
1554
   input clear;
1555
   output [length:1] q;
1556
   input rst;
1557
   input clk;
1558
 
1559
   parameter clear_value = 0;
1560
   parameter set_value = 1;
1561
   parameter wrap_value = 0;
1562
   parameter level1_value = 15;
1563
 
1564
   reg  [length:1] qi;
1565
   wire [length:1] q_next;
1566
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1567
 
1568
   always @ (posedge clk or posedge rst)
1569
     if (rst)
1570
       qi <= {length{1'b0}};
1571
     else
1572
       qi <= q_next;
1573
 
1574
   assign q = qi;
1575
 
1576
endmodule
1577 40 unneback
`endif
1578
`ifdef CNT_BIN_CE
1579 22 unneback
//////////////////////////////////////////////////////////////////////
1580
////                                                              ////
1581
////  Versatile counter                                           ////
1582
////                                                              ////
1583
////  Description                                                 ////
1584
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1585
////  counter                                                     ////
1586
////                                                              ////
1587
////  To Do:                                                      ////
1588
////   - add LFSR with more taps                                  ////
1589
////                                                              ////
1590
////  Author(s):                                                  ////
1591
////      - Michael Unneback, unneback@opencores.org              ////
1592
////        ORSoC AB                                              ////
1593
////                                                              ////
1594
//////////////////////////////////////////////////////////////////////
1595
////                                                              ////
1596
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1597
////                                                              ////
1598
//// This source file may be used and distributed without         ////
1599
//// restriction provided that this copyright statement is not    ////
1600
//// removed from the file and that any derivative work contains  ////
1601
//// the original copyright notice and the associated disclaimer. ////
1602
////                                                              ////
1603
//// This source file is free software; you can redistribute it   ////
1604
//// and/or modify it under the terms of the GNU Lesser General   ////
1605
//// Public License as published by the Free Software Foundation; ////
1606
//// either version 2.1 of the License, or (at your option) any   ////
1607
//// later version.                                               ////
1608
////                                                              ////
1609
//// This source is distributed in the hope that it will be       ////
1610
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1611
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1612
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1613
//// details.                                                     ////
1614
////                                                              ////
1615
//// You should have received a copy of the GNU Lesser General    ////
1616
//// Public License along with this source; if not, download it   ////
1617
//// from http://www.opencores.org/lgpl.shtml                     ////
1618
////                                                              ////
1619
//////////////////////////////////////////////////////////////////////
1620
 
1621
// binary counter
1622 6 unneback
 
1623 40 unneback
`define MODULE cnt_bin_ce
1624
module `BASE`MODULE (
1625
`undef MODULE
1626
 cke, q, rst, clk);
1627
 
1628 6 unneback
   parameter length = 4;
1629
   input cke;
1630
   output [length:1] q;
1631
   input rst;
1632
   input clk;
1633
 
1634
   parameter clear_value = 0;
1635
   parameter set_value = 1;
1636
   parameter wrap_value = 0;
1637
   parameter level1_value = 15;
1638
 
1639
   reg  [length:1] qi;
1640
   wire [length:1] q_next;
1641
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1642
 
1643
   always @ (posedge clk or posedge rst)
1644
     if (rst)
1645
       qi <= {length{1'b0}};
1646
     else
1647
     if (cke)
1648
       qi <= q_next;
1649
 
1650
   assign q = qi;
1651
 
1652
endmodule
1653 40 unneback
`endif
1654
`ifdef CNT_BIN_CE_CLEAR
1655 6 unneback
//////////////////////////////////////////////////////////////////////
1656
////                                                              ////
1657
////  Versatile counter                                           ////
1658
////                                                              ////
1659
////  Description                                                 ////
1660
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1661
////  counter                                                     ////
1662
////                                                              ////
1663
////  To Do:                                                      ////
1664
////   - add LFSR with more taps                                  ////
1665
////                                                              ////
1666
////  Author(s):                                                  ////
1667
////      - Michael Unneback, unneback@opencores.org              ////
1668
////        ORSoC AB                                              ////
1669
////                                                              ////
1670
//////////////////////////////////////////////////////////////////////
1671
////                                                              ////
1672
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1673
////                                                              ////
1674
//// This source file may be used and distributed without         ////
1675
//// restriction provided that this copyright statement is not    ////
1676
//// removed from the file and that any derivative work contains  ////
1677
//// the original copyright notice and the associated disclaimer. ////
1678
////                                                              ////
1679
//// This source file is free software; you can redistribute it   ////
1680
//// and/or modify it under the terms of the GNU Lesser General   ////
1681
//// Public License as published by the Free Software Foundation; ////
1682
//// either version 2.1 of the License, or (at your option) any   ////
1683
//// later version.                                               ////
1684
////                                                              ////
1685
//// This source is distributed in the hope that it will be       ////
1686
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1687
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1688
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1689
//// details.                                                     ////
1690
////                                                              ////
1691
//// You should have received a copy of the GNU Lesser General    ////
1692
//// Public License along with this source; if not, download it   ////
1693
//// from http://www.opencores.org/lgpl.shtml                     ////
1694
////                                                              ////
1695
//////////////////////////////////////////////////////////////////////
1696
 
1697
// binary counter
1698
 
1699 40 unneback
`define MODULE cnt_bin_ce_clear
1700
module `BASE`MODULE (
1701
`undef MODULE
1702
 clear, cke, q, rst, clk);
1703
 
1704 6 unneback
   parameter length = 4;
1705
   input clear;
1706
   input cke;
1707
   output [length:1] q;
1708
   input rst;
1709
   input clk;
1710
 
1711
   parameter clear_value = 0;
1712
   parameter set_value = 1;
1713
   parameter wrap_value = 0;
1714
   parameter level1_value = 15;
1715
 
1716
   reg  [length:1] qi;
1717
   wire [length:1] q_next;
1718
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1719
 
1720
   always @ (posedge clk or posedge rst)
1721
     if (rst)
1722
       qi <= {length{1'b0}};
1723
     else
1724
     if (cke)
1725
       qi <= q_next;
1726
 
1727
   assign q = qi;
1728
 
1729
endmodule
1730 40 unneback
`endif
1731
`ifdef CNT_BIN_CE_CLEAR_L1_L2
1732 6 unneback
//////////////////////////////////////////////////////////////////////
1733
////                                                              ////
1734
////  Versatile counter                                           ////
1735
////                                                              ////
1736
////  Description                                                 ////
1737
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1738
////  counter                                                     ////
1739
////                                                              ////
1740
////  To Do:                                                      ////
1741
////   - add LFSR with more taps                                  ////
1742
////                                                              ////
1743
////  Author(s):                                                  ////
1744
////      - Michael Unneback, unneback@opencores.org              ////
1745
////        ORSoC AB                                              ////
1746
////                                                              ////
1747
//////////////////////////////////////////////////////////////////////
1748
////                                                              ////
1749
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1750
////                                                              ////
1751
//// This source file may be used and distributed without         ////
1752
//// restriction provided that this copyright statement is not    ////
1753
//// removed from the file and that any derivative work contains  ////
1754
//// the original copyright notice and the associated disclaimer. ////
1755
////                                                              ////
1756
//// This source file is free software; you can redistribute it   ////
1757
//// and/or modify it under the terms of the GNU Lesser General   ////
1758
//// Public License as published by the Free Software Foundation; ////
1759
//// either version 2.1 of the License, or (at your option) any   ////
1760
//// later version.                                               ////
1761
////                                                              ////
1762
//// This source is distributed in the hope that it will be       ////
1763
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1764
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1765
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1766
//// details.                                                     ////
1767
////                                                              ////
1768
//// You should have received a copy of the GNU Lesser General    ////
1769
//// Public License along with this source; if not, download it   ////
1770
//// from http://www.opencores.org/lgpl.shtml                     ////
1771
////                                                              ////
1772
//////////////////////////////////////////////////////////////////////
1773
 
1774
// binary counter
1775 29 unneback
 
1776 40 unneback
`define MODULE cnt_bin_ce_clear_l1_l2
1777
module `BASE`MODULE (
1778
`undef MODULE
1779
 clear, cke, q, level1, level2, rst, clk);
1780
 
1781 29 unneback
   parameter length = 4;
1782
   input clear;
1783
   input cke;
1784
   output [length:1] q;
1785
   output reg level1;
1786
   output reg level2;
1787
   input rst;
1788
   input clk;
1789
 
1790
   parameter clear_value = 0;
1791
   parameter set_value = 1;
1792 30 unneback
   parameter wrap_value = 15;
1793
   parameter level1_value = 8;
1794
   parameter level2_value = 15;
1795 29 unneback
 
1796
   wire rew;
1797 30 unneback
   assign rew = 1'b0;
1798 29 unneback
   reg  [length:1] qi;
1799
   wire [length:1] q_next;
1800
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1801
 
1802
   always @ (posedge clk or posedge rst)
1803
     if (rst)
1804
       qi <= {length{1'b0}};
1805
     else
1806
     if (cke)
1807
       qi <= q_next;
1808
 
1809
   assign q = qi;
1810
 
1811
 
1812
    always @ (posedge clk or posedge rst)
1813
    if (rst)
1814
        level1 <= 1'b0;
1815
    else
1816
    if (cke)
1817
    if (clear)
1818
        level1 <= 1'b0;
1819
    else if (q_next == level1_value)
1820
        level1 <= 1'b1;
1821
    else if (qi == level1_value & rew)
1822
        level1 <= 1'b0;
1823
 
1824
    always @ (posedge clk or posedge rst)
1825
    if (rst)
1826
        level2 <= 1'b0;
1827
    else
1828
    if (cke)
1829
    if (clear)
1830
        level2 <= 1'b0;
1831
    else if (q_next == level2_value)
1832
        level2 <= 1'b1;
1833
    else if (qi == level2_value & rew)
1834
        level2 <= 1'b0;
1835
endmodule
1836 40 unneback
`endif
1837
`ifdef CNT_BIN_CE_CLEAR_SET_REW
1838 29 unneback
//////////////////////////////////////////////////////////////////////
1839
////                                                              ////
1840
////  Versatile counter                                           ////
1841
////                                                              ////
1842
////  Description                                                 ////
1843
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1844
////  counter                                                     ////
1845
////                                                              ////
1846
////  To Do:                                                      ////
1847
////   - add LFSR with more taps                                  ////
1848
////                                                              ////
1849
////  Author(s):                                                  ////
1850
////      - Michael Unneback, unneback@opencores.org              ////
1851
////        ORSoC AB                                              ////
1852
////                                                              ////
1853
//////////////////////////////////////////////////////////////////////
1854
////                                                              ////
1855
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1856
////                                                              ////
1857
//// This source file may be used and distributed without         ////
1858
//// restriction provided that this copyright statement is not    ////
1859
//// removed from the file and that any derivative work contains  ////
1860
//// the original copyright notice and the associated disclaimer. ////
1861
////                                                              ////
1862
//// This source file is free software; you can redistribute it   ////
1863
//// and/or modify it under the terms of the GNU Lesser General   ////
1864
//// Public License as published by the Free Software Foundation; ////
1865
//// either version 2.1 of the License, or (at your option) any   ////
1866
//// later version.                                               ////
1867
////                                                              ////
1868
//// This source is distributed in the hope that it will be       ////
1869
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1870
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1871
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1872
//// details.                                                     ////
1873
////                                                              ////
1874
//// You should have received a copy of the GNU Lesser General    ////
1875
//// Public License along with this source; if not, download it   ////
1876
//// from http://www.opencores.org/lgpl.shtml                     ////
1877
////                                                              ////
1878
//////////////////////////////////////////////////////////////////////
1879
 
1880
// binary counter
1881 6 unneback
 
1882 40 unneback
`define MODULE cnt_bin_ce_clear_set_rew
1883
module `BASE`MODULE (
1884
`undef MODULE
1885
 clear, set, cke, rew, q, rst, clk);
1886
 
1887 6 unneback
   parameter length = 4;
1888
   input clear;
1889
   input set;
1890
   input cke;
1891
   input rew;
1892
   output [length:1] q;
1893
   input rst;
1894
   input clk;
1895
 
1896
   parameter clear_value = 0;
1897
   parameter set_value = 1;
1898
   parameter wrap_value = 0;
1899
   parameter level1_value = 15;
1900
 
1901
   reg  [length:1] qi;
1902
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1903
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
1904
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
1905
   assign q_next = rew ? q_next_rew : q_next_fw;
1906
 
1907
   always @ (posedge clk or posedge rst)
1908
     if (rst)
1909
       qi <= {length{1'b0}};
1910
     else
1911
     if (cke)
1912
       qi <= q_next;
1913
 
1914
   assign q = qi;
1915
 
1916
endmodule
1917 40 unneback
`endif
1918
`ifdef CNT_BIN_CE_REW_L1
1919 6 unneback
//////////////////////////////////////////////////////////////////////
1920
////                                                              ////
1921
////  Versatile counter                                           ////
1922
////                                                              ////
1923
////  Description                                                 ////
1924
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1925
////  counter                                                     ////
1926
////                                                              ////
1927
////  To Do:                                                      ////
1928
////   - add LFSR with more taps                                  ////
1929
////                                                              ////
1930
////  Author(s):                                                  ////
1931
////      - Michael Unneback, unneback@opencores.org              ////
1932
////        ORSoC AB                                              ////
1933
////                                                              ////
1934
//////////////////////////////////////////////////////////////////////
1935
////                                                              ////
1936
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1937
////                                                              ////
1938
//// This source file may be used and distributed without         ////
1939
//// restriction provided that this copyright statement is not    ////
1940
//// removed from the file and that any derivative work contains  ////
1941
//// the original copyright notice and the associated disclaimer. ////
1942
////                                                              ////
1943
//// This source file is free software; you can redistribute it   ////
1944
//// and/or modify it under the terms of the GNU Lesser General   ////
1945
//// Public License as published by the Free Software Foundation; ////
1946
//// either version 2.1 of the License, or (at your option) any   ////
1947
//// later version.                                               ////
1948
////                                                              ////
1949
//// This source is distributed in the hope that it will be       ////
1950
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1951
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1952
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1953
//// details.                                                     ////
1954
////                                                              ////
1955
//// You should have received a copy of the GNU Lesser General    ////
1956
//// Public License along with this source; if not, download it   ////
1957
//// from http://www.opencores.org/lgpl.shtml                     ////
1958
////                                                              ////
1959
//////////////////////////////////////////////////////////////////////
1960
 
1961
// binary counter
1962
 
1963 40 unneback
`define MODULE cnt_bin_ce_rew_l1
1964
module `BASE`MODULE (
1965
`undef MODULE
1966
 cke, rew, level1, rst, clk);
1967
 
1968 6 unneback
   parameter length = 4;
1969
   input cke;
1970
   input rew;
1971
   output reg level1;
1972
   input rst;
1973
   input clk;
1974
 
1975
   parameter clear_value = 0;
1976
   parameter set_value = 1;
1977
   parameter wrap_value = 1;
1978
   parameter level1_value = 15;
1979
 
1980 29 unneback
   wire clear;
1981 30 unneback
   assign clear = 1'b0;
1982 6 unneback
   reg  [length:1] qi;
1983
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1984
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1985
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1986
   assign q_next = rew ? q_next_rew : q_next_fw;
1987
 
1988
   always @ (posedge clk or posedge rst)
1989
     if (rst)
1990
       qi <= {length{1'b0}};
1991
     else
1992
     if (cke)
1993
       qi <= q_next;
1994
 
1995
 
1996
 
1997
    always @ (posedge clk or posedge rst)
1998
    if (rst)
1999
        level1 <= 1'b0;
2000
    else
2001
    if (cke)
2002 29 unneback
    if (clear)
2003
        level1 <= 1'b0;
2004
    else if (q_next == level1_value)
2005 6 unneback
        level1 <= 1'b1;
2006
    else if (qi == level1_value & rew)
2007
        level1 <= 1'b0;
2008
endmodule
2009 40 unneback
`endif
2010
`ifdef CNT_BIN_CE_REW_ZQ_L1
2011 6 unneback
//////////////////////////////////////////////////////////////////////
2012
////                                                              ////
2013
////  Versatile counter                                           ////
2014
////                                                              ////
2015
////  Description                                                 ////
2016
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2017
////  counter                                                     ////
2018
////                                                              ////
2019
////  To Do:                                                      ////
2020
////   - add LFSR with more taps                                  ////
2021
////                                                              ////
2022
////  Author(s):                                                  ////
2023
////      - Michael Unneback, unneback@opencores.org              ////
2024
////        ORSoC AB                                              ////
2025
////                                                              ////
2026
//////////////////////////////////////////////////////////////////////
2027
////                                                              ////
2028
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2029
////                                                              ////
2030
//// This source file may be used and distributed without         ////
2031
//// restriction provided that this copyright statement is not    ////
2032
//// removed from the file and that any derivative work contains  ////
2033
//// the original copyright notice and the associated disclaimer. ////
2034
////                                                              ////
2035
//// This source file is free software; you can redistribute it   ////
2036
//// and/or modify it under the terms of the GNU Lesser General   ////
2037
//// Public License as published by the Free Software Foundation; ////
2038
//// either version 2.1 of the License, or (at your option) any   ////
2039
//// later version.                                               ////
2040
////                                                              ////
2041
//// This source is distributed in the hope that it will be       ////
2042
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2043
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2044
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2045
//// details.                                                     ////
2046
////                                                              ////
2047
//// You should have received a copy of the GNU Lesser General    ////
2048
//// Public License along with this source; if not, download it   ////
2049
//// from http://www.opencores.org/lgpl.shtml                     ////
2050
////                                                              ////
2051
//////////////////////////////////////////////////////////////////////
2052
 
2053 25 unneback
// binary counter
2054
 
2055 40 unneback
`define MODULE cnt_bin_ce_rew_zq_l1
2056
module `BASE`MODULE (
2057
`undef MODULE
2058
 cke, rew, zq, level1, rst, clk);
2059
 
2060 25 unneback
   parameter length = 4;
2061
   input cke;
2062
   input rew;
2063
   output reg zq;
2064
   output reg level1;
2065
   input rst;
2066
   input clk;
2067
 
2068
   parameter clear_value = 0;
2069
   parameter set_value = 1;
2070
   parameter wrap_value = 1;
2071
   parameter level1_value = 15;
2072
 
2073 29 unneback
   wire clear;
2074 30 unneback
   assign clear = 1'b0;
2075 25 unneback
   reg  [length:1] qi;
2076
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2077
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2078
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2079
   assign q_next = rew ? q_next_rew : q_next_fw;
2080
 
2081
   always @ (posedge clk or posedge rst)
2082
     if (rst)
2083
       qi <= {length{1'b0}};
2084
     else
2085
     if (cke)
2086
       qi <= q_next;
2087
 
2088
 
2089
 
2090
   always @ (posedge clk or posedge rst)
2091
     if (rst)
2092
       zq <= 1'b1;
2093
     else
2094
     if (cke)
2095
       zq <= q_next == {length{1'b0}};
2096
 
2097
    always @ (posedge clk or posedge rst)
2098
    if (rst)
2099
        level1 <= 1'b0;
2100
    else
2101
    if (cke)
2102 29 unneback
    if (clear)
2103
        level1 <= 1'b0;
2104
    else if (q_next == level1_value)
2105 25 unneback
        level1 <= 1'b1;
2106
    else if (qi == level1_value & rew)
2107
        level1 <= 1'b0;
2108
endmodule
2109 40 unneback
`endif
2110
`ifdef CNT_BIN_CE_REW_Q_ZQ_L1
2111 25 unneback
//////////////////////////////////////////////////////////////////////
2112
////                                                              ////
2113
////  Versatile counter                                           ////
2114
////                                                              ////
2115
////  Description                                                 ////
2116
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2117
////  counter                                                     ////
2118
////                                                              ////
2119
////  To Do:                                                      ////
2120
////   - add LFSR with more taps                                  ////
2121
////                                                              ////
2122
////  Author(s):                                                  ////
2123
////      - Michael Unneback, unneback@opencores.org              ////
2124
////        ORSoC AB                                              ////
2125
////                                                              ////
2126
//////////////////////////////////////////////////////////////////////
2127
////                                                              ////
2128
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2129
////                                                              ////
2130
//// This source file may be used and distributed without         ////
2131
//// restriction provided that this copyright statement is not    ////
2132
//// removed from the file and that any derivative work contains  ////
2133
//// the original copyright notice and the associated disclaimer. ////
2134
////                                                              ////
2135
//// This source file is free software; you can redistribute it   ////
2136
//// and/or modify it under the terms of the GNU Lesser General   ////
2137
//// Public License as published by the Free Software Foundation; ////
2138
//// either version 2.1 of the License, or (at your option) any   ////
2139
//// later version.                                               ////
2140
////                                                              ////
2141
//// This source is distributed in the hope that it will be       ////
2142
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2143
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2144
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2145
//// details.                                                     ////
2146
////                                                              ////
2147
//// You should have received a copy of the GNU Lesser General    ////
2148
//// Public License along with this source; if not, download it   ////
2149
//// from http://www.opencores.org/lgpl.shtml                     ////
2150
////                                                              ////
2151
//////////////////////////////////////////////////////////////////////
2152
 
2153
// binary counter
2154
 
2155 40 unneback
`define MODULE cnt_bin_ce_rew_q_zq_l1
2156
module `BASE`MODULE (
2157
`undef MODULE
2158
 cke, rew, q, zq, level1, rst, clk);
2159
 
2160 25 unneback
   parameter length = 4;
2161
   input cke;
2162
   input rew;
2163
   output [length:1] q;
2164
   output reg zq;
2165
   output reg level1;
2166
   input rst;
2167
   input clk;
2168
 
2169
   parameter clear_value = 0;
2170
   parameter set_value = 1;
2171
   parameter wrap_value = 1;
2172
   parameter level1_value = 15;
2173
 
2174 29 unneback
   wire clear;
2175 30 unneback
   assign clear = 1'b0;
2176 25 unneback
   reg  [length:1] qi;
2177
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2178
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2179
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2180
   assign q_next = rew ? q_next_rew : q_next_fw;
2181
 
2182
   always @ (posedge clk or posedge rst)
2183
     if (rst)
2184
       qi <= {length{1'b0}};
2185
     else
2186
     if (cke)
2187
       qi <= q_next;
2188
 
2189
   assign q = qi;
2190
 
2191
 
2192
   always @ (posedge clk or posedge rst)
2193
     if (rst)
2194
       zq <= 1'b1;
2195
     else
2196
     if (cke)
2197
       zq <= q_next == {length{1'b0}};
2198
 
2199
    always @ (posedge clk or posedge rst)
2200
    if (rst)
2201
        level1 <= 1'b0;
2202
    else
2203
    if (cke)
2204 29 unneback
    if (clear)
2205
        level1 <= 1'b0;
2206
    else if (q_next == level1_value)
2207 25 unneback
        level1 <= 1'b1;
2208
    else if (qi == level1_value & rew)
2209
        level1 <= 1'b0;
2210
endmodule
2211 40 unneback
`endif
2212
`ifdef CNT_LFSR_ZQ
2213 25 unneback
//////////////////////////////////////////////////////////////////////
2214
////                                                              ////
2215
////  Versatile counter                                           ////
2216
////                                                              ////
2217
////  Description                                                 ////
2218
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2219
////  counter                                                     ////
2220
////                                                              ////
2221
////  To Do:                                                      ////
2222
////   - add LFSR with more taps                                  ////
2223
////                                                              ////
2224
////  Author(s):                                                  ////
2225
////      - Michael Unneback, unneback@opencores.org              ////
2226
////        ORSoC AB                                              ////
2227
////                                                              ////
2228
//////////////////////////////////////////////////////////////////////
2229
////                                                              ////
2230
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2231
////                                                              ////
2232
//// This source file may be used and distributed without         ////
2233
//// restriction provided that this copyright statement is not    ////
2234
//// removed from the file and that any derivative work contains  ////
2235
//// the original copyright notice and the associated disclaimer. ////
2236
////                                                              ////
2237
//// This source file is free software; you can redistribute it   ////
2238
//// and/or modify it under the terms of the GNU Lesser General   ////
2239
//// Public License as published by the Free Software Foundation; ////
2240
//// either version 2.1 of the License, or (at your option) any   ////
2241
//// later version.                                               ////
2242
////                                                              ////
2243
//// This source is distributed in the hope that it will be       ////
2244
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2245
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2246
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2247
//// details.                                                     ////
2248
////                                                              ////
2249
//// You should have received a copy of the GNU Lesser General    ////
2250
//// Public License along with this source; if not, download it   ////
2251
//// from http://www.opencores.org/lgpl.shtml                     ////
2252
////                                                              ////
2253
//////////////////////////////////////////////////////////////////////
2254
 
2255 6 unneback
// LFSR counter
2256
 
2257 40 unneback
`define MODULE cnt_lfsr_zq
2258
module `BASE`MODULE (
2259
`undef MODULE
2260
 zq, rst, clk);
2261
 
2262 6 unneback
   parameter length = 4;
2263
   output reg zq;
2264
   input rst;
2265
   input clk;
2266
 
2267
   parameter clear_value = 0;
2268
   parameter set_value = 1;
2269
   parameter wrap_value = 8;
2270
   parameter level1_value = 15;
2271
 
2272
   reg  [length:1] qi;
2273
   reg lfsr_fb;
2274
   wire [length:1] q_next;
2275
   reg [32:1] polynom;
2276
   integer i;
2277
 
2278
   always @ (qi)
2279
   begin
2280
        case (length)
2281
         2: polynom = 32'b11;                               // 0x3
2282
         3: polynom = 32'b110;                              // 0x6
2283
         4: polynom = 32'b1100;                             // 0xC
2284
         5: polynom = 32'b10100;                            // 0x14
2285
         6: polynom = 32'b110000;                           // 0x30
2286
         7: polynom = 32'b1100000;                          // 0x60
2287
         8: polynom = 32'b10111000;                         // 0xb8
2288
         9: polynom = 32'b100010000;                        // 0x110
2289
        10: polynom = 32'b1001000000;                       // 0x240
2290
        11: polynom = 32'b10100000000;                      // 0x500
2291
        12: polynom = 32'b100000101001;                     // 0x829
2292
        13: polynom = 32'b1000000001100;                    // 0x100C
2293
        14: polynom = 32'b10000000010101;                   // 0x2015
2294
        15: polynom = 32'b110000000000000;                  // 0x6000
2295
        16: polynom = 32'b1101000000001000;                 // 0xD008
2296
        17: polynom = 32'b10010000000000000;                // 0x12000
2297
        18: polynom = 32'b100000010000000000;               // 0x20400
2298
        19: polynom = 32'b1000000000000100011;              // 0x40023
2299 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2300 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2301
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2302
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2303
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2304
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2305
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2306
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2307
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2308
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2309
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2310
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2311
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2312
        default: polynom = 32'b0;
2313
        endcase
2314
        lfsr_fb = qi[length];
2315
        for (i=length-1; i>=1; i=i-1) begin
2316
            if (polynom[i])
2317
                lfsr_fb = lfsr_fb  ~^ qi[i];
2318
        end
2319
    end
2320
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2321
 
2322
   always @ (posedge clk or posedge rst)
2323
     if (rst)
2324
       qi <= {length{1'b0}};
2325
     else
2326
       qi <= q_next;
2327
 
2328
 
2329
 
2330
   always @ (posedge clk or posedge rst)
2331
     if (rst)
2332
       zq <= 1'b1;
2333
     else
2334
       zq <= q_next == {length{1'b0}};
2335
endmodule
2336 40 unneback
`endif
2337
`ifdef CNT_LFSR_CE_ZQ
2338 6 unneback
//////////////////////////////////////////////////////////////////////
2339
////                                                              ////
2340
////  Versatile counter                                           ////
2341
////                                                              ////
2342
////  Description                                                 ////
2343
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2344
////  counter                                                     ////
2345
////                                                              ////
2346
////  To Do:                                                      ////
2347
////   - add LFSR with more taps                                  ////
2348
////                                                              ////
2349
////  Author(s):                                                  ////
2350
////      - Michael Unneback, unneback@opencores.org              ////
2351
////        ORSoC AB                                              ////
2352
////                                                              ////
2353
//////////////////////////////////////////////////////////////////////
2354
////                                                              ////
2355
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2356
////                                                              ////
2357
//// This source file may be used and distributed without         ////
2358
//// restriction provided that this copyright statement is not    ////
2359
//// removed from the file and that any derivative work contains  ////
2360
//// the original copyright notice and the associated disclaimer. ////
2361
////                                                              ////
2362
//// This source file is free software; you can redistribute it   ////
2363
//// and/or modify it under the terms of the GNU Lesser General   ////
2364
//// Public License as published by the Free Software Foundation; ////
2365
//// either version 2.1 of the License, or (at your option) any   ////
2366
//// later version.                                               ////
2367
////                                                              ////
2368
//// This source is distributed in the hope that it will be       ////
2369
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2370
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2371
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2372
//// details.                                                     ////
2373
////                                                              ////
2374
//// You should have received a copy of the GNU Lesser General    ////
2375
//// Public License along with this source; if not, download it   ////
2376
//// from http://www.opencores.org/lgpl.shtml                     ////
2377
////                                                              ////
2378
//////////////////////////////////////////////////////////////////////
2379
 
2380
// LFSR counter
2381
 
2382 40 unneback
`define MODULE cnt_lfsr_ce_zq
2383
module `BASE`MODULE (
2384
`undef MODULE
2385
 cke, zq, rst, clk);
2386
 
2387 6 unneback
   parameter length = 4;
2388
   input cke;
2389
   output reg zq;
2390
   input rst;
2391
   input clk;
2392
 
2393
   parameter clear_value = 0;
2394
   parameter set_value = 1;
2395
   parameter wrap_value = 8;
2396
   parameter level1_value = 15;
2397
 
2398
   reg  [length:1] qi;
2399
   reg lfsr_fb;
2400
   wire [length:1] q_next;
2401
   reg [32:1] polynom;
2402
   integer i;
2403
 
2404
   always @ (qi)
2405
   begin
2406
        case (length)
2407
         2: polynom = 32'b11;                               // 0x3
2408
         3: polynom = 32'b110;                              // 0x6
2409
         4: polynom = 32'b1100;                             // 0xC
2410
         5: polynom = 32'b10100;                            // 0x14
2411
         6: polynom = 32'b110000;                           // 0x30
2412
         7: polynom = 32'b1100000;                          // 0x60
2413
         8: polynom = 32'b10111000;                         // 0xb8
2414
         9: polynom = 32'b100010000;                        // 0x110
2415
        10: polynom = 32'b1001000000;                       // 0x240
2416
        11: polynom = 32'b10100000000;                      // 0x500
2417
        12: polynom = 32'b100000101001;                     // 0x829
2418
        13: polynom = 32'b1000000001100;                    // 0x100C
2419
        14: polynom = 32'b10000000010101;                   // 0x2015
2420
        15: polynom = 32'b110000000000000;                  // 0x6000
2421
        16: polynom = 32'b1101000000001000;                 // 0xD008
2422
        17: polynom = 32'b10010000000000000;                // 0x12000
2423
        18: polynom = 32'b100000010000000000;               // 0x20400
2424
        19: polynom = 32'b1000000000000100011;              // 0x40023
2425 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2426 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2427
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2428
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2429
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2430
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2431
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2432
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2433
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2434
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2435
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2436
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2437
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2438
        default: polynom = 32'b0;
2439
        endcase
2440
        lfsr_fb = qi[length];
2441
        for (i=length-1; i>=1; i=i-1) begin
2442
            if (polynom[i])
2443
                lfsr_fb = lfsr_fb  ~^ qi[i];
2444
        end
2445
    end
2446
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2447
 
2448
   always @ (posedge clk or posedge rst)
2449
     if (rst)
2450
       qi <= {length{1'b0}};
2451
     else
2452
     if (cke)
2453
       qi <= q_next;
2454
 
2455
 
2456
 
2457
   always @ (posedge clk or posedge rst)
2458
     if (rst)
2459
       zq <= 1'b1;
2460
     else
2461
     if (cke)
2462
       zq <= q_next == {length{1'b0}};
2463
endmodule
2464 40 unneback
`endif
2465
`ifdef CNT_LFSR_CE_Q
2466 6 unneback
//////////////////////////////////////////////////////////////////////
2467
////                                                              ////
2468
////  Versatile counter                                           ////
2469
////                                                              ////
2470
////  Description                                                 ////
2471
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2472
////  counter                                                     ////
2473
////                                                              ////
2474
////  To Do:                                                      ////
2475
////   - add LFSR with more taps                                  ////
2476
////                                                              ////
2477
////  Author(s):                                                  ////
2478
////      - Michael Unneback, unneback@opencores.org              ////
2479
////        ORSoC AB                                              ////
2480
////                                                              ////
2481
//////////////////////////////////////////////////////////////////////
2482
////                                                              ////
2483
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2484
////                                                              ////
2485
//// This source file may be used and distributed without         ////
2486
//// restriction provided that this copyright statement is not    ////
2487
//// removed from the file and that any derivative work contains  ////
2488
//// the original copyright notice and the associated disclaimer. ////
2489
////                                                              ////
2490
//// This source file is free software; you can redistribute it   ////
2491
//// and/or modify it under the terms of the GNU Lesser General   ////
2492
//// Public License as published by the Free Software Foundation; ////
2493
//// either version 2.1 of the License, or (at your option) any   ////
2494
//// later version.                                               ////
2495
////                                                              ////
2496
//// This source is distributed in the hope that it will be       ////
2497
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2498
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2499
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2500
//// details.                                                     ////
2501
////                                                              ////
2502
//// You should have received a copy of the GNU Lesser General    ////
2503
//// Public License along with this source; if not, download it   ////
2504
//// from http://www.opencores.org/lgpl.shtml                     ////
2505
////                                                              ////
2506
//////////////////////////////////////////////////////////////////////
2507 22 unneback
 
2508
// LFSR counter
2509 27 unneback
 
2510 40 unneback
`define MODULE cnt_lfsr_ce_q
2511
module `BASE`MODULE (
2512
`undef MODULE
2513
 cke, q, rst, clk);
2514
 
2515 27 unneback
   parameter length = 4;
2516
   input cke;
2517
   output [length:1] q;
2518
   input rst;
2519
   input clk;
2520
 
2521
   parameter clear_value = 0;
2522
   parameter set_value = 1;
2523
   parameter wrap_value = 8;
2524
   parameter level1_value = 15;
2525
 
2526
   reg  [length:1] qi;
2527
   reg lfsr_fb;
2528
   wire [length:1] q_next;
2529
   reg [32:1] polynom;
2530
   integer i;
2531
 
2532
   always @ (qi)
2533
   begin
2534
        case (length)
2535
         2: polynom = 32'b11;                               // 0x3
2536
         3: polynom = 32'b110;                              // 0x6
2537
         4: polynom = 32'b1100;                             // 0xC
2538
         5: polynom = 32'b10100;                            // 0x14
2539
         6: polynom = 32'b110000;                           // 0x30
2540
         7: polynom = 32'b1100000;                          // 0x60
2541
         8: polynom = 32'b10111000;                         // 0xb8
2542
         9: polynom = 32'b100010000;                        // 0x110
2543
        10: polynom = 32'b1001000000;                       // 0x240
2544
        11: polynom = 32'b10100000000;                      // 0x500
2545
        12: polynom = 32'b100000101001;                     // 0x829
2546
        13: polynom = 32'b1000000001100;                    // 0x100C
2547
        14: polynom = 32'b10000000010101;                   // 0x2015
2548
        15: polynom = 32'b110000000000000;                  // 0x6000
2549
        16: polynom = 32'b1101000000001000;                 // 0xD008
2550
        17: polynom = 32'b10010000000000000;                // 0x12000
2551
        18: polynom = 32'b100000010000000000;               // 0x20400
2552
        19: polynom = 32'b1000000000000100011;              // 0x40023
2553 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2554 27 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2555
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2556
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2557
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2558
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2559
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2560
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2561
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2562
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2563
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2564
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2565
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2566
        default: polynom = 32'b0;
2567
        endcase
2568
        lfsr_fb = qi[length];
2569
        for (i=length-1; i>=1; i=i-1) begin
2570
            if (polynom[i])
2571
                lfsr_fb = lfsr_fb  ~^ qi[i];
2572
        end
2573
    end
2574
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2575
 
2576
   always @ (posedge clk or posedge rst)
2577
     if (rst)
2578
       qi <= {length{1'b0}};
2579
     else
2580
     if (cke)
2581
       qi <= q_next;
2582
 
2583
   assign q = qi;
2584
 
2585
endmodule
2586 40 unneback
`endif
2587
`ifdef CNT_LFSR_CE_CLEAR_Q
2588 27 unneback
//////////////////////////////////////////////////////////////////////
2589
////                                                              ////
2590
////  Versatile counter                                           ////
2591
////                                                              ////
2592
////  Description                                                 ////
2593
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2594
////  counter                                                     ////
2595
////                                                              ////
2596
////  To Do:                                                      ////
2597
////   - add LFSR with more taps                                  ////
2598
////                                                              ////
2599
////  Author(s):                                                  ////
2600
////      - Michael Unneback, unneback@opencores.org              ////
2601
////        ORSoC AB                                              ////
2602
////                                                              ////
2603
//////////////////////////////////////////////////////////////////////
2604
////                                                              ////
2605
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2606
////                                                              ////
2607
//// This source file may be used and distributed without         ////
2608
//// restriction provided that this copyright statement is not    ////
2609
//// removed from the file and that any derivative work contains  ////
2610
//// the original copyright notice and the associated disclaimer. ////
2611
////                                                              ////
2612
//// This source file is free software; you can redistribute it   ////
2613
//// and/or modify it under the terms of the GNU Lesser General   ////
2614
//// Public License as published by the Free Software Foundation; ////
2615
//// either version 2.1 of the License, or (at your option) any   ////
2616
//// later version.                                               ////
2617
////                                                              ////
2618
//// This source is distributed in the hope that it will be       ////
2619
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2620
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2621
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2622
//// details.                                                     ////
2623
////                                                              ////
2624
//// You should have received a copy of the GNU Lesser General    ////
2625
//// Public License along with this source; if not, download it   ////
2626
//// from http://www.opencores.org/lgpl.shtml                     ////
2627
////                                                              ////
2628
//////////////////////////////////////////////////////////////////////
2629
 
2630
// LFSR counter
2631
 
2632 40 unneback
`define MODULE cnt_lfsr_ce_clear_q
2633
module `BASE`MODULE (
2634
`undef MODULE
2635
 clear, cke, q, rst, clk);
2636
 
2637 27 unneback
   parameter length = 4;
2638
   input clear;
2639
   input cke;
2640
   output [length:1] q;
2641
   input rst;
2642
   input clk;
2643
 
2644
   parameter clear_value = 0;
2645
   parameter set_value = 1;
2646
   parameter wrap_value = 8;
2647
   parameter level1_value = 15;
2648
 
2649
   reg  [length:1] qi;
2650
   reg lfsr_fb;
2651
   wire [length:1] q_next;
2652
   reg [32:1] polynom;
2653
   integer i;
2654
 
2655
   always @ (qi)
2656
   begin
2657
        case (length)
2658
         2: polynom = 32'b11;                               // 0x3
2659
         3: polynom = 32'b110;                              // 0x6
2660
         4: polynom = 32'b1100;                             // 0xC
2661
         5: polynom = 32'b10100;                            // 0x14
2662
         6: polynom = 32'b110000;                           // 0x30
2663
         7: polynom = 32'b1100000;                          // 0x60
2664
         8: polynom = 32'b10111000;                         // 0xb8
2665
         9: polynom = 32'b100010000;                        // 0x110
2666
        10: polynom = 32'b1001000000;                       // 0x240
2667
        11: polynom = 32'b10100000000;                      // 0x500
2668
        12: polynom = 32'b100000101001;                     // 0x829
2669
        13: polynom = 32'b1000000001100;                    // 0x100C
2670
        14: polynom = 32'b10000000010101;                   // 0x2015
2671
        15: polynom = 32'b110000000000000;                  // 0x6000
2672
        16: polynom = 32'b1101000000001000;                 // 0xD008
2673
        17: polynom = 32'b10010000000000000;                // 0x12000
2674
        18: polynom = 32'b100000010000000000;               // 0x20400
2675
        19: polynom = 32'b1000000000000100011;              // 0x40023
2676 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2677 27 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2678
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2679
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2680
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2681
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2682
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2683
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2684
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2685
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2686
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2687
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2688
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2689
        default: polynom = 32'b0;
2690
        endcase
2691
        lfsr_fb = qi[length];
2692
        for (i=length-1; i>=1; i=i-1) begin
2693
            if (polynom[i])
2694
                lfsr_fb = lfsr_fb  ~^ qi[i];
2695
        end
2696
    end
2697
   assign q_next =  clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2698
 
2699
   always @ (posedge clk or posedge rst)
2700
     if (rst)
2701
       qi <= {length{1'b0}};
2702
     else
2703
     if (cke)
2704
       qi <= q_next;
2705
 
2706
   assign q = qi;
2707
 
2708
endmodule
2709 40 unneback
`endif
2710
`ifdef CNT_LFSR_CE_Q_ZQ
2711 27 unneback
//////////////////////////////////////////////////////////////////////
2712
////                                                              ////
2713
////  Versatile counter                                           ////
2714
////                                                              ////
2715
////  Description                                                 ////
2716
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2717
////  counter                                                     ////
2718
////                                                              ////
2719
////  To Do:                                                      ////
2720
////   - add LFSR with more taps                                  ////
2721
////                                                              ////
2722
////  Author(s):                                                  ////
2723
////      - Michael Unneback, unneback@opencores.org              ////
2724
////        ORSoC AB                                              ////
2725
////                                                              ////
2726
//////////////////////////////////////////////////////////////////////
2727
////                                                              ////
2728
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2729
////                                                              ////
2730
//// This source file may be used and distributed without         ////
2731
//// restriction provided that this copyright statement is not    ////
2732
//// removed from the file and that any derivative work contains  ////
2733
//// the original copyright notice and the associated disclaimer. ////
2734
////                                                              ////
2735
//// This source file is free software; you can redistribute it   ////
2736
//// and/or modify it under the terms of the GNU Lesser General   ////
2737
//// Public License as published by the Free Software Foundation; ////
2738
//// either version 2.1 of the License, or (at your option) any   ////
2739
//// later version.                                               ////
2740
////                                                              ////
2741
//// This source is distributed in the hope that it will be       ////
2742
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2743
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2744
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2745
//// details.                                                     ////
2746
////                                                              ////
2747
//// You should have received a copy of the GNU Lesser General    ////
2748
//// Public License along with this source; if not, download it   ////
2749
//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
2751
//////////////////////////////////////////////////////////////////////
2752
 
2753
// LFSR counter
2754 22 unneback
 
2755 40 unneback
`define MODULE cnt_lfsr_ce_q_zq
2756
module `BASE`MODULE (
2757
`undef MODULE
2758
 cke, q, zq, rst, clk);
2759
 
2760 22 unneback
   parameter length = 4;
2761
   input cke;
2762
   output [length:1] q;
2763
   output reg zq;
2764
   input rst;
2765
   input clk;
2766
 
2767
   parameter clear_value = 0;
2768
   parameter set_value = 1;
2769
   parameter wrap_value = 8;
2770
   parameter level1_value = 15;
2771
 
2772
   reg  [length:1] qi;
2773
   reg lfsr_fb;
2774
   wire [length:1] q_next;
2775
   reg [32:1] polynom;
2776
   integer i;
2777
 
2778
   always @ (qi)
2779
   begin
2780
        case (length)
2781
         2: polynom = 32'b11;                               // 0x3
2782
         3: polynom = 32'b110;                              // 0x6
2783
         4: polynom = 32'b1100;                             // 0xC
2784
         5: polynom = 32'b10100;                            // 0x14
2785
         6: polynom = 32'b110000;                           // 0x30
2786
         7: polynom = 32'b1100000;                          // 0x60
2787
         8: polynom = 32'b10111000;                         // 0xb8
2788
         9: polynom = 32'b100010000;                        // 0x110
2789
        10: polynom = 32'b1001000000;                       // 0x240
2790
        11: polynom = 32'b10100000000;                      // 0x500
2791
        12: polynom = 32'b100000101001;                     // 0x829
2792
        13: polynom = 32'b1000000001100;                    // 0x100C
2793
        14: polynom = 32'b10000000010101;                   // 0x2015
2794
        15: polynom = 32'b110000000000000;                  // 0x6000
2795
        16: polynom = 32'b1101000000001000;                 // 0xD008
2796
        17: polynom = 32'b10010000000000000;                // 0x12000
2797
        18: polynom = 32'b100000010000000000;               // 0x20400
2798
        19: polynom = 32'b1000000000000100011;              // 0x40023
2799 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2800 22 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2801
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2802
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2803
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2804
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2805
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2806
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2807
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2808
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2809
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2810
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2811
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2812
        default: polynom = 32'b0;
2813
        endcase
2814
        lfsr_fb = qi[length];