OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Blame information for rev 45

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 40 unneback
`ifndef BASE
2
`define BASE vl_
3
`endif
4
 
5 44 unneback
`ifdef ACTEL
6
`define SYN_KEEP /*synthesis syn_keep = 1*/
7
`endif
8
 
9 40 unneback
`ifdef ALL
10
 
11
`define GBUF
12
`define SYNC_RST
13
`define PLL
14
 
15
`define MULTS
16
`define MULTS18X18
17
`define MULT
18
`define SHIFT_UNIT_32
19
`define LOGIC_UNIT
20
 
21
`define CNT_SHREG_WRAP
22
`define CNT_SHREG_CE_WRAP
23
`define CNT_SHREG_CE_CLEAR
24
`define CNT_SHREG_CE_CLEAR_WRAP
25
 
26
`define MUX_ANDOR
27
`define MUX2_ANDOR
28
`define MUX3_ANDOR
29
`define MUX4_ANDOR
30
`define MUX5_ANDOR
31
`define MUX6_ANDOR
32 43 unneback
`define PARITY
33 40 unneback
 
34
`define ROM_INIT
35
`define RAM
36
`define RAM_BE
37
`define DPRAM_1R1W
38
`define DPRAM_2R1W
39
`define DPRAM_2R2W
40
`define FIFO_1R1W_FILL_LEVEL_SYNC
41
`define FIFO_2R2W_SYNC_SIMPLEX
42
`define FIFO_CMP_ASYNC
43
`define FIFO_1R1W_ASYNC
44
`define FIFO_2R2W_ASYNC
45
`define FIFO_2R2W_ASYNC_SIMPLEX
46
 
47
`define DFF
48
`define DFF_ARRAY
49
`define DFF_CE
50
`define DFF_CE_CLEAR
51
`define DF_CE_SET
52
`define SPR
53
`define SRP
54
`define DFF_SR
55
`define LATCH
56
`define SHREG
57
`define SHREG_CE
58
`define DELAY
59
`define DELAY_EMPTYFLAG
60
 
61
`define WB3WB3_BRIDGE
62
`define WB3_ARBITER_TYPE1
63
`define WB_BOOT_ROM
64
`define WB_DPRAM
65
 
66 44 unneback
`define IO_DFF_OE
67
`define O_DFF
68
 
69 40 unneback
`endif
70
 
71
`ifdef PLL
72
`ifndef SYNC_RST
73
`define SYNC_RST
74
`endif
75
`endif
76
 
77
`ifdef SYNC_RST
78
`ifndef GBUF
79
`define GBUF
80
`endif
81
`endif
82
 
83
`ifdef WB_DPRAM
84
`ifndef DPRAM_2R2W
85
`define DPRAM_2R2W
86
`endif
87
`ifndef SPR
88
`define SPR
89
`endif
90
`endif
91
 
92
`ifdef WB3_ARBITER_TYPE1
93 42 unneback
`ifndef SPR
94
`define SPR
95
`endif
96 40 unneback
`ifndef MUX_ANDOR
97
`define MUX_ANDOR
98
`endif
99
`endif
100
 
101
`ifdef WB3WB3_BRIDGE
102
`ifndef CNT_SHREG_CE_CLEAR
103
`define CNT_SHREG_CE_CLEAR
104
`endif
105
`ifndef DFF
106
`define DFF
107
`endif
108
`ifndef DFF_CE
109
`define DFF_CE
110
`endif
111
`ifndef CNT_SHREG_CE_CLEAR
112
`define CNT_SHREG_CE_CLEAR
113
`endif
114
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
115
`define FIFO_2R2W_ASYNC_SIMPLEX
116
`endif
117
`endif
118
 
119
`ifdef MULTS18X18
120
`ifndef MULTS
121
`define MULTS
122
`endif
123
`endif
124
 
125
`ifdef SHIFT_UNIT_32
126
`ifndef MULTS
127
`define MULTS
128
`endif
129
`endif
130
 
131
`ifdef MUX2_ANDOR
132
`ifndef MUX_ANDOR
133
`define MUX_ANDOR
134
`endif
135
`endif
136
 
137
`ifdef MUX3_ANDOR
138
`ifndef MUX_ANDOR
139
`define MUX_ANDOR
140
`endif
141
`endif
142
 
143
`ifdef MUX4_ANDOR
144
`ifndef MUX_ANDOR
145
`define MUX_ANDOR
146
`endif
147
`endif
148
 
149
`ifdef MUX5_ANDOR
150
`ifndef MUX_ANDOR
151
`define MUX_ANDOR
152
`endif
153
`endif
154
 
155
`ifdef MUX6_ANDOR
156
`ifndef MUX_ANDOR
157
`define MUX_ANDOR
158
`endif
159
`endif
160
 
161
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
162
`ifndef CNT_BIN_CE
163
`define CNT_BIN_CE
164
`endif
165
`ifndef DPRAM_1R1W
166
`define DPRAM_1R1W
167
`endif
168
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
169
`define CNT_BIN_CE_REW_Q_ZQ_L1
170
`endif
171
`endif
172
 
173
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
174
`ifndef CNT_LFSR_CE
175
`define CNT_LFSR_CE
176
`endif
177
`ifndef DPRAM_2R2W
178
`define DPRAM_2R2W
179
`endif
180
`ifndef CNT_BIN_CE_REW_ZQ_L1
181
`define CNT_BIN_CE_REW_ZQ_L1
182
`endif
183
`endif
184
 
185
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
186
`ifndef CNT_GRAY_CE_BIN
187
`define CNT_GRAY_CE_BIN
188
`endif
189
`ifndef DPRAM_2R2W
190
`define DPRAM_2R2W
191
`endif
192
`ifndef FIFO_CMP_ASYNC
193
`define FIFO_CMP_ASYNC
194
`endif
195
`endif
196
 
197
`ifdef FIFO_2R2W_ASYNC
198
`ifndef FIFO_1R1W_ASYNC
199
`define FIFO_1R1W_ASYNC
200
`endif
201
`endif
202
 
203
`ifdef FIFO_1R1W_ASYNC
204
`ifndef CNT_GRAY_CE_BIN
205
`define CNT_GRAY_CE_BIN
206
`endif
207
`ifndef DPRAM_1R1W
208
`define DPRAM_1R1W
209
`endif
210
`ifndef FIFO_CMP_ASYNC
211
`define FIFO_CMP_ASYNC
212
`endif
213
`endif
214
 
215
`ifdef FIFO_CMP_ASYNC
216
`ifndef DFF_SR
217
`define DFF_SR
218
`endif
219
`ifndef DFF
220
`define DFF
221
`endif
222
`endif
223 6 unneback
//////////////////////////////////////////////////////////////////////
224
////                                                              ////
225
////  Versatile library, clock and reset                          ////
226
////                                                              ////
227
////  Description                                                 ////
228
////  Logic related to clock and reset                            ////
229
////                                                              ////
230
////                                                              ////
231
////  To Do:                                                      ////
232
////   - add more different registers                             ////
233
////                                                              ////
234
////  Author(s):                                                  ////
235
////      - Michael Unneback, unneback@opencores.org              ////
236
////        ORSoC AB                                              ////
237
////                                                              ////
238
//////////////////////////////////////////////////////////////////////
239
////                                                              ////
240
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
241
////                                                              ////
242
//// This source file may be used and distributed without         ////
243
//// restriction provided that this copyright statement is not    ////
244
//// removed from the file and that any derivative work contains  ////
245
//// the original copyright notice and the associated disclaimer. ////
246
////                                                              ////
247
//// This source file is free software; you can redistribute it   ////
248
//// and/or modify it under the terms of the GNU Lesser General   ////
249
//// Public License as published by the Free Software Foundation; ////
250
//// either version 2.1 of the License, or (at your option) any   ////
251
//// later version.                                               ////
252
////                                                              ////
253
//// This source is distributed in the hope that it will be       ////
254
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
255
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
256
//// PURPOSE.  See the GNU Lesser General Public License for more ////
257
//// details.                                                     ////
258
////                                                              ////
259
//// You should have received a copy of the GNU Lesser General    ////
260
//// Public License along with this source; if not, download it   ////
261
//// from http://www.opencores.org/lgpl.shtml                     ////
262
////                                                              ////
263
//////////////////////////////////////////////////////////////////////
264
 
265
// Global buffer
266
// usage:
267
// use to enable global buffers for high fan out signals such as clock and reset
268
 
269
`ifdef ACTEL
270 40 unneback
`ifdef GBUF
271 6 unneback
`timescale 1 ns/100 ps
272
// Version: 8.4 8.4.0.33
273
module gbuf(GL,CLK);
274
output GL;
275
input  CLK;
276
 
277
    wire GND;
278
 
279
    GND GND_1_net(.Y(GND));
280
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
281
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
282
 
283
endmodule
284
`timescale 1 ns/1 ns
285 40 unneback
`define MODULE gbuf
286
module `BASE`MODULE ( i, o);
287
`undef MODULE
288 6 unneback
input i;
289
output o;
290
`ifdef SIM_GBUF
291
assign o=i;
292
`else
293
gbuf gbuf_i0 ( .CLK(i), .GL(o));
294
`endif
295
endmodule
296 40 unneback
`endif
297 33 unneback
 
298 6 unneback
`else
299 33 unneback
 
300 40 unneback
`ifdef ALTERA
301
`ifdef GBUF
302 21 unneback
//altera
303 40 unneback
`define MODULE gbuf
304
module `BASE`MODULE ( i, o);
305
`undef MODULE
306 33 unneback
input i;
307
output o;
308
assign o = i;
309
endmodule
310 40 unneback
`endif
311 33 unneback
 
312 6 unneback
`else
313
 
314 40 unneback
`ifdef GBUF
315 6 unneback
`timescale 1 ns/100 ps
316 40 unneback
`define MODULE
317
module `BASE`MODULE ( i, o);
318
`undef MODULE
319 6 unneback
input i;
320
output o;
321
assign o = i;
322
endmodule
323 40 unneback
`endif
324 6 unneback
`endif // ALTERA
325
`endif //ACTEL
326
 
327 40 unneback
`ifdef SYNC_RST
328 6 unneback
// sync reset
329 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
330 6 unneback
// output active high global reset sync with two DFFs 
331
`timescale 1 ns/100 ps
332 40 unneback
`define MODULE sync_rst
333
module `BASE`MODULE ( rst_n_i, rst_o, clk);
334
`undef MODULE
335 6 unneback
input rst_n_i, clk;
336
output rst_o;
337 18 unneback
reg [1:0] tmp;
338 6 unneback
always @ (posedge clk or negedge rst_n_i)
339
if (!rst_n_i)
340 17 unneback
        tmp <= 2'b11;
341 6 unneback
else
342 33 unneback
        tmp <= {1'b0,tmp[1]};
343 40 unneback
`define MODULE gbuf
344
`BASE`MODULE buf_i0( .i(tmp[0]), .o(rst_o));
345
`undef MODULE
346 6 unneback
endmodule
347 40 unneback
`endif
348 6 unneback
 
349 40 unneback
`ifdef PLL
350 6 unneback
// vl_pll
351
`ifdef ACTEL
352 32 unneback
///////////////////////////////////////////////////////////////////////////////
353 17 unneback
`timescale 1 ps/1 ps
354 40 unneback
`define MODULE pll
355
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
356
`undef MODULE
357 6 unneback
parameter index = 0;
358
parameter number_of_clk = 1;
359 17 unneback
parameter period_time_0 = 20000;
360
parameter period_time_1 = 20000;
361
parameter period_time_2 = 20000;
362
parameter lock_delay = 2000000;
363 6 unneback
input clk_i, rst_n_i;
364
output lock;
365
output reg [0:number_of_clk-1] clk_o;
366
output [0:number_of_clk-1] rst_o;
367
 
368
`ifdef SIM_PLL
369
 
370
always
371
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
372
 
373
generate if (number_of_clk > 1)
374
always
375
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
376
endgenerate
377
 
378
generate if (number_of_clk > 2)
379
always
380
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
381
endgenerate
382
 
383
genvar i;
384
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
385
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
386
end
387
endgenerate
388
 
389
assign #lock_delay lock = rst_n_i;
390
 
391
endmodule
392
`else
393
generate if (number_of_clk==1 & index==0) begin
394
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
395
end
396
endgenerate // index==0
397
generate if (number_of_clk==1 & index==1) begin
398
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
399
end
400
endgenerate // index==1
401
generate if (number_of_clk==1 & index==2) begin
402
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
403
end
404
endgenerate // index==2
405
generate if (number_of_clk==1 & index==3) begin
406
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
407
end
408
endgenerate // index==0
409
 
410
generate if (number_of_clk==2 & index==0) begin
411
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
412
end
413
endgenerate // index==0
414
generate if (number_of_clk==2 & index==1) begin
415
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
416
end
417
endgenerate // index==1
418
generate if (number_of_clk==2 & index==2) begin
419
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
420
end
421
endgenerate // index==2
422
generate if (number_of_clk==2 & index==3) begin
423
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
424
end
425
endgenerate // index==0
426
 
427
generate if (number_of_clk==3 & index==0) begin
428
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
429
end
430
endgenerate // index==0
431
generate if (number_of_clk==3 & index==1) begin
432
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
433
end
434
endgenerate // index==1
435
generate if (number_of_clk==3 & index==2) begin
436
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
437
end
438
endgenerate // index==2
439
generate if (number_of_clk==3 & index==3) begin
440
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
441
end
442
endgenerate // index==0
443
 
444
genvar i;
445
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
446 40 unneback
`define MODULE sync_rst
447
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
448
`undef MODULE
449 6 unneback
end
450
endgenerate
451
endmodule
452
`endif
453 32 unneback
///////////////////////////////////////////////////////////////////////////////
454 6 unneback
 
455
`else
456
 
457 32 unneback
///////////////////////////////////////////////////////////////////////////////
458 6 unneback
`ifdef ALTERA
459
 
460 32 unneback
`timescale 1 ps/1 ps
461 40 unneback
`define MODULE pll
462
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
463
`undef MODULE
464 32 unneback
parameter index = 0;
465
parameter number_of_clk = 1;
466
parameter period_time_0 = 20000;
467
parameter period_time_1 = 20000;
468
parameter period_time_2 = 20000;
469
parameter period_time_3 = 20000;
470
parameter period_time_4 = 20000;
471
parameter lock_delay = 2000000;
472
input clk_i, rst_n_i;
473
output lock;
474
output reg [0:number_of_clk-1] clk_o;
475
output [0:number_of_clk-1] rst_o;
476
 
477
`ifdef SIM_PLL
478
 
479
always
480
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
481
 
482
generate if (number_of_clk > 1)
483
always
484
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
485
endgenerate
486
 
487
generate if (number_of_clk > 2)
488
always
489
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
490
endgenerate
491
 
492 33 unneback
generate if (number_of_clk > 3)
493 32 unneback
always
494
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
495
endgenerate
496
 
497 33 unneback
generate if (number_of_clk > 4)
498 32 unneback
always
499
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
500
endgenerate
501
 
502
genvar i;
503
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
504
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
505
end
506
endgenerate
507
 
508 33 unneback
//assign #lock_delay lock = rst_n_i;
509
assign lock = rst_n_i;
510 32 unneback
 
511
endmodule
512 6 unneback
`else
513
 
514 33 unneback
`ifdef VL_PLL0
515
`ifdef VL_PLL0_CLK1
516
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
517
`endif
518
`ifdef VL_PLL0_CLK2
519
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
520
`endif
521
`ifdef VL_PLL0_CLK3
522
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
523
`endif
524
`ifdef VL_PLL0_CLK4
525
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
526
`endif
527
`ifdef VL_PLL0_CLK5
528
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
529
`endif
530
`endif
531 32 unneback
 
532 33 unneback
`ifdef VL_PLL1
533
`ifdef VL_PLL1_CLK1
534
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
535
`endif
536
`ifdef VL_PLL1_CLK2
537
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
538
`endif
539
`ifdef VL_PLL1_CLK3
540
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
541
`endif
542
`ifdef VL_PLL1_CLK4
543
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
544
`endif
545
`ifdef VL_PLL1_CLK5
546
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
547
`endif
548
`endif
549 32 unneback
 
550 33 unneback
`ifdef VL_PLL2
551
`ifdef VL_PLL2_CLK1
552
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
553
`endif
554
`ifdef VL_PLL2_CLK2
555
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
556
`endif
557
`ifdef VL_PLL2_CLK3
558
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
559
`endif
560
`ifdef VL_PLL2_CLK4
561
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
562
`endif
563
`ifdef VL_PLL2_CLK5
564
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
565
`endif
566
`endif
567 32 unneback
 
568 33 unneback
`ifdef VL_PLL3
569
`ifdef VL_PLL3_CLK1
570
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
571
`endif
572
`ifdef VL_PLL3_CLK2
573
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
574
`endif
575
`ifdef VL_PLL3_CLK3
576
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
577
`endif
578
`ifdef VL_PLL3_CLK4
579
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
580
`endif
581
`ifdef VL_PLL3_CLK5
582
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
583
`endif
584
`endif
585 32 unneback
 
586
genvar i;
587
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
588 40 unneback
`define MODULE sync_rst
589
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
590
`undef MODULE
591 32 unneback
end
592
endgenerate
593
endmodule
594
`endif
595
///////////////////////////////////////////////////////////////////////////////
596
 
597
`else
598
 
599 6 unneback
// generic PLL
600 17 unneback
`timescale 1 ps/1 ps
601 40 unneback
`define MODULE pll
602
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
603
`undef MODULE
604 6 unneback
parameter index = 0;
605
parameter number_of_clk = 1;
606 17 unneback
parameter period_time_0 = 20000;
607
parameter period_time_1 = 20000;
608
parameter period_time_2 = 20000;
609 6 unneback
parameter lock_delay = 2000;
610
input clk_i, rst_n_i;
611
output lock;
612
output reg [0:number_of_clk-1] clk_o;
613
output [0:number_of_clk-1] rst_o;
614
 
615
always
616
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
617
 
618
generate if (number_of_clk > 1)
619
always
620
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
621
endgenerate
622
 
623
generate if (number_of_clk > 2)
624
always
625
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
626
endgenerate
627
 
628
genvar i;
629
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
630 40 unneback
`define MODULE sync_rst
631
     `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
632
`undef MODULE
633 6 unneback
end
634
endgenerate
635
 
636
assign #lock_delay lock = rst_n_i;
637
 
638
endmodule
639
 
640
`endif //altera
641 17 unneback
`endif //actel
642 40 unneback
`undef MODULE
643
`endif//////////////////////////////////////////////////////////////////////
644 6 unneback
////                                                              ////
645
////  Versatile library, registers                                ////
646
////                                                              ////
647
////  Description                                                 ////
648
////  Different type of registers                                 ////
649
////                                                              ////
650
////                                                              ////
651
////  To Do:                                                      ////
652
////   - add more different registers                             ////
653
////                                                              ////
654
////  Author(s):                                                  ////
655
////      - Michael Unneback, unneback@opencores.org              ////
656
////        ORSoC AB                                              ////
657
////                                                              ////
658
//////////////////////////////////////////////////////////////////////
659
////                                                              ////
660
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
661
////                                                              ////
662
//// This source file may be used and distributed without         ////
663
//// restriction provided that this copyright statement is not    ////
664
//// removed from the file and that any derivative work contains  ////
665
//// the original copyright notice and the associated disclaimer. ////
666
////                                                              ////
667
//// This source file is free software; you can redistribute it   ////
668
//// and/or modify it under the terms of the GNU Lesser General   ////
669
//// Public License as published by the Free Software Foundation; ////
670
//// either version 2.1 of the License, or (at your option) any   ////
671
//// later version.                                               ////
672
////                                                              ////
673
//// This source is distributed in the hope that it will be       ////
674
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
675
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
676
//// PURPOSE.  See the GNU Lesser General Public License for more ////
677
//// details.                                                     ////
678
////                                                              ////
679
//// You should have received a copy of the GNU Lesser General    ////
680
//// Public License along with this source; if not, download it   ////
681
//// from http://www.opencores.org/lgpl.shtml                     ////
682
////                                                              ////
683
//////////////////////////////////////////////////////////////////////
684
 
685 40 unneback
`ifdef DFF
686
`define MODULE dff
687
module `BASE`MODULE ( d, q, clk, rst);
688
`undef MODULE
689 6 unneback
        parameter width = 1;
690
        parameter reset_value = 0;
691
 
692
        input [width-1:0] d;
693
        input clk, rst;
694
        output reg [width-1:0] q;
695
 
696
        always @ (posedge clk or posedge rst)
697
        if (rst)
698
                q <= reset_value;
699
        else
700
                q <= d;
701
 
702
endmodule
703 40 unneback
`endif
704 6 unneback
 
705 40 unneback
`ifdef DFF_ARRAY
706
`define MODULE dff_array
707
module `BASE`MODULE ( d, q, clk, rst);
708
`undef MODULE
709 6 unneback
 
710
        parameter width = 1;
711
        parameter depth = 2;
712
        parameter reset_value = 1'b0;
713
 
714
        input [width-1:0] d;
715
        input clk, rst;
716
        output [width-1:0] q;
717
        reg  [0:depth-1] q_tmp [width-1:0];
718
        integer i;
719
        always @ (posedge clk or posedge rst)
720
        if (rst) begin
721
            for (i=0;i<depth;i=i+1)
722
                q_tmp[i] <= {width{reset_value}};
723
        end else begin
724
            q_tmp[0] <= d;
725
            for (i=1;i<depth;i=i+1)
726
                q_tmp[i] <= q_tmp[i-1];
727
        end
728
 
729
    assign q = q_tmp[depth-1];
730
 
731
endmodule
732 40 unneback
`endif
733 6 unneback
 
734 40 unneback
`ifdef DFF_CE
735
`define MODULE dff_ce
736
module `BASE`MODULE ( d, ce, q, clk, rst);
737
`undef MODULE
738 6 unneback
 
739
        parameter width = 1;
740
        parameter reset_value = 0;
741
 
742
        input [width-1:0] d;
743
        input ce, clk, rst;
744
        output reg [width-1:0] q;
745
 
746
        always @ (posedge clk or posedge rst)
747
        if (rst)
748
                q <= reset_value;
749
        else
750
                if (ce)
751
                        q <= d;
752
 
753
endmodule
754 40 unneback
`endif
755 6 unneback
 
756 40 unneback
`ifdef DFF_CE_CLEAR
757
`define MODULE dff_ce_clear
758
module `BASE`MODULE ( d, ce, clear, q, clk, rst);
759
`undef MODULE
760 8 unneback
 
761
        parameter width = 1;
762
        parameter reset_value = 0;
763
 
764
        input [width-1:0] d;
765 10 unneback
        input ce, clear, clk, rst;
766 8 unneback
        output reg [width-1:0] q;
767
 
768
        always @ (posedge clk or posedge rst)
769
        if (rst)
770
            q <= reset_value;
771
        else
772
            if (ce)
773
                if (clear)
774
                    q <= {width{1'b0}};
775
                else
776
                    q <= d;
777
 
778
endmodule
779 40 unneback
`endif
780 8 unneback
 
781 40 unneback
`ifdef DF_CE_SET
782
`define MODULE dff_ce_set
783
module `BASE`MODULE ( d, ce, set, q, clk, rst);
784
`undef MODULE
785 24 unneback
 
786
        parameter width = 1;
787
        parameter reset_value = 0;
788
 
789
        input [width-1:0] d;
790
        input ce, set, clk, rst;
791
        output reg [width-1:0] q;
792
 
793
        always @ (posedge clk or posedge rst)
794
        if (rst)
795
            q <= reset_value;
796
        else
797
            if (ce)
798
                if (set)
799
                    q <= {width{1'b1}};
800
                else
801
                    q <= d;
802
 
803
endmodule
804 40 unneback
`endif
805 24 unneback
 
806 40 unneback
`ifdef SPR
807
`define MODULE spr
808
module `BASE`MODULE ( sp, r, q, clk, rst);
809
`undef MODULE
810
 
811 29 unneback
        parameter width = 1;
812
        parameter reset_value = 0;
813
 
814
        input sp, r;
815
        output reg q;
816
        input clk, rst;
817
 
818
        always @ (posedge clk or posedge rst)
819
        if (rst)
820
            q <= reset_value;
821
        else
822
            if (sp)
823
                q <= 1'b1;
824
            else if (r)
825
                q <= 1'b0;
826
 
827
endmodule
828 40 unneback
`endif
829 29 unneback
 
830 40 unneback
`ifdef SRP
831
`define MODULE srp
832
module `BASE`MODULE ( s, rp, q, clk, rst);
833
`undef MODULE
834
 
835 29 unneback
        parameter width = 1;
836
        parameter reset_value = 0;
837
 
838
        input s, rp;
839
        output reg q;
840
        input clk, rst;
841
 
842
        always @ (posedge clk or posedge rst)
843
        if (rst)
844
            q <= reset_value;
845
        else
846
            if (rp)
847
                q <= 1'b0;
848
            else if (s)
849
                q <= 1'b1;
850
 
851
endmodule
852 40 unneback
`endif
853 29 unneback
 
854 40 unneback
`ifdef ALTERA
855 29 unneback
 
856 40 unneback
`ifdef DFF_SR
857 6 unneback
// megafunction wizard: %LPM_FF%
858
// GENERATION: STANDARD
859
// VERSION: WM1.0
860
// MODULE: lpm_ff 
861
 
862
// ============================================================
863
// File Name: dff_sr.v
864
// Megafunction Name(s):
865
//                      lpm_ff
866
//
867
// Simulation Library Files(s):
868
//                      lpm
869
// ============================================================
870
// ************************************************************
871
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
872
//
873
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
874
// ************************************************************
875
 
876
 
877
//Copyright (C) 1991-2010 Altera Corporation
878
//Your use of Altera Corporation's design tools, logic functions 
879
//and other software and tools, and its AMPP partner logic 
880
//functions, and any output files from any of the foregoing 
881
//(including device programming or simulation files), and any 
882
//associated documentation or information are expressly subject 
883
//to the terms and conditions of the Altera Program License 
884
//Subscription Agreement, Altera MegaCore Function License 
885
//Agreement, or other applicable license agreement, including, 
886
//without limitation, that your use is for the sole purpose of 
887
//programming logic devices manufactured by Altera and sold by 
888
//Altera or its authorized distributors.  Please refer to the 
889
//applicable agreement for further details.
890
 
891
 
892
// synopsys translate_off
893
`timescale 1 ps / 1 ps
894
// synopsys translate_on
895 40 unneback
`define MODULE dff_sr
896
module `BASE`MODULE (
897
`undef MODULE
898
 
899 6 unneback
        aclr,
900
        aset,
901
        clock,
902
        data,
903
        q);
904
 
905
        input     aclr;
906
        input     aset;
907
        input     clock;
908
        input     data;
909
        output    q;
910
 
911
        wire [0:0] sub_wire0;
912
        wire [0:0] sub_wire1 = sub_wire0[0:0];
913
        wire  q = sub_wire1;
914
        wire  sub_wire2 = data;
915
        wire  sub_wire3 = sub_wire2;
916
 
917
        lpm_ff  lpm_ff_component (
918
                                .aclr (aclr),
919
                                .clock (clock),
920
                                .data (sub_wire3),
921
                                .aset (aset),
922
                                .q (sub_wire0)
923
                                // synopsys translate_off
924
                                ,
925
                                .aload (),
926
                                .enable (),
927
                                .sclr (),
928
                                .sload (),
929
                                .sset ()
930
                                // synopsys translate_on
931
                                );
932
        defparam
933
                lpm_ff_component.lpm_fftype = "DFF",
934
                lpm_ff_component.lpm_type = "LPM_FF",
935
                lpm_ff_component.lpm_width = 1;
936
 
937
 
938
endmodule
939
 
940
// ============================================================
941
// CNX file retrieval info
942
// ============================================================
943
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
944
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
945
// Retrieval info: PRIVATE: ASET NUMERIC "1"
946
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
947
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
948
// Retrieval info: PRIVATE: DFF NUMERIC "1"
949
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
950
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
951
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
952
// Retrieval info: PRIVATE: SSET NUMERIC "0"
953
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
954
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
955
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
956
// Retrieval info: PRIVATE: nBit NUMERIC "1"
957
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
958
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
959
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
960
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
961
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
962
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
963
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
964
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
965
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
966
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
967
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
968
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
969
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
970
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
971
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
972
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
973
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
974
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
975
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
976
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
977
// Retrieval info: LIB_FILE: lpm
978 40 unneback
`endif
979 6 unneback
 
980
`else
981
 
982 40 unneback
`ifdef DFF_SR
983
`define MODULE dff_sr
984
module `BASE`MODULE ( aclr, aset, clock, data, q);
985
`undef MODULE
986 6 unneback
 
987
    input         aclr;
988
    input         aset;
989
    input         clock;
990
    input         data;
991
    output reg    q;
992
 
993
   always @ (posedge clock or posedge aclr or posedge aset)
994
     if (aclr)
995
       q <= 1'b0;
996
     else if (aset)
997
       q <= 1'b1;
998
     else
999
       q <= data;
1000
 
1001
endmodule
1002 40 unneback
`endif
1003 6 unneback
 
1004
`endif
1005
 
1006
// LATCH
1007
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
1008
`ifdef ALTERA
1009 40 unneback
 
1010
`ifdef LATCH
1011
`define MODULE latch
1012
module `BASE`MODULE ( d, le, q, clk);
1013
`undef MODULE
1014 6 unneback
input d, le;
1015
output q;
1016
input clk;
1017
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
1018
endmodule
1019 40 unneback
`endif
1020
 
1021 6 unneback
`else
1022 40 unneback
 
1023
`ifdef LATCH
1024
`define MODULE latch
1025
module `BASE`MODULE ( d, le, q, clk);
1026
`undef MODULE
1027 6 unneback
input d, le;
1028
output q;
1029
input clk;/*
1030
   always @ (posedge direction_set or posedge direction_clr)
1031
     if (direction_clr)
1032
       direction <= going_empty;
1033
     else
1034
       direction <= going_full;*/
1035
endmodule
1036 15 unneback
`endif
1037
 
1038 40 unneback
`endif
1039
 
1040
`ifdef SHREG
1041
`define MODULE shreg
1042
module `BASE`MODULE ( d, q, clk, rst);
1043
`undef MODULE
1044
 
1045 17 unneback
parameter depth = 10;
1046
input d;
1047
output q;
1048
input clk, rst;
1049
 
1050
reg [1:depth] dffs;
1051
 
1052
always @ (posedge clk or posedge rst)
1053
if (rst)
1054
    dffs <= {depth{1'b0}};
1055
else
1056
    dffs <= {d,dffs[1:depth-1]};
1057
assign q = dffs[depth];
1058
endmodule
1059 40 unneback
`endif
1060 17 unneback
 
1061 40 unneback
`ifdef SHREG_CE
1062
`define MODULE shreg_ce
1063
module `BASE`MODULE ( d, ce, q, clk, rst);
1064
`undef MODULE
1065 17 unneback
parameter depth = 10;
1066
input d, ce;
1067
output q;
1068
input clk, rst;
1069
 
1070
reg [1:depth] dffs;
1071
 
1072
always @ (posedge clk or posedge rst)
1073
if (rst)
1074
    dffs <= {depth{1'b0}};
1075
else
1076
    if (ce)
1077
        dffs <= {d,dffs[1:depth-1]};
1078
assign q = dffs[depth];
1079
endmodule
1080 40 unneback
`endif
1081 17 unneback
 
1082 40 unneback
`ifdef DELAY
1083
`define MODULE delay
1084
module `BASE`MODULE ( d, q, clk, rst);
1085
`undef MODULE
1086 15 unneback
parameter depth = 10;
1087
input d;
1088
output q;
1089
input clk, rst;
1090
 
1091
reg [1:depth] dffs;
1092
 
1093
always @ (posedge clk or posedge rst)
1094
if (rst)
1095
    dffs <= {depth{1'b0}};
1096
else
1097
    dffs <= {d,dffs[1:depth-1]};
1098
assign q = dffs[depth];
1099 17 unneback
endmodule
1100 40 unneback
`endif
1101 17 unneback
 
1102 40 unneback
`ifdef DELAY_EMPTYFLAG
1103
`define MODULE delay_emptyflag
1104 41 unneback
module `BASE`MODULE ( d, q, emptyflag, clk, rst);
1105 40 unneback
`undef MODULE
1106 17 unneback
parameter depth = 10;
1107
input d;
1108
output q, emptyflag;
1109
input clk, rst;
1110
 
1111
reg [1:depth] dffs;
1112
 
1113
always @ (posedge clk or posedge rst)
1114
if (rst)
1115
    dffs <= {depth{1'b0}};
1116
else
1117
    dffs <= {d,dffs[1:depth-1]};
1118
assign q = dffs[depth];
1119
assign emptyflag = !(|dffs);
1120
endmodule
1121 40 unneback
`endif
1122 17 unneback
//////////////////////////////////////////////////////////////////////
1123 6 unneback
////                                                              ////
1124 18 unneback
////  Logic functions                                             ////
1125
////                                                              ////
1126
////  Description                                                 ////
1127
////  Logic functions such as multiplexers                        ////
1128
////                                                              ////
1129
////                                                              ////
1130
////  To Do:                                                      ////
1131
////   -                                                          ////
1132
////                                                              ////
1133
////  Author(s):                                                  ////
1134
////      - Michael Unneback, unneback@opencores.org              ////
1135
////        ORSoC AB                                              ////
1136
////                                                              ////
1137
//////////////////////////////////////////////////////////////////////
1138
////                                                              ////
1139
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1140
////                                                              ////
1141
//// This source file may be used and distributed without         ////
1142
//// restriction provided that this copyright statement is not    ////
1143
//// removed from the file and that any derivative work contains  ////
1144
//// the original copyright notice and the associated disclaimer. ////
1145
////                                                              ////
1146
//// This source file is free software; you can redistribute it   ////
1147
//// and/or modify it under the terms of the GNU Lesser General   ////
1148
//// Public License as published by the Free Software Foundation; ////
1149
//// either version 2.1 of the License, or (at your option) any   ////
1150
//// later version.                                               ////
1151
////                                                              ////
1152
//// This source is distributed in the hope that it will be       ////
1153
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1154
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1155
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1156
//// details.                                                     ////
1157
////                                                              ////
1158
//// You should have received a copy of the GNU Lesser General    ////
1159
//// Public License along with this source; if not, download it   ////
1160
//// from http://www.opencores.org/lgpl.shtml                     ////
1161
////                                                              ////
1162
//////////////////////////////////////////////////////////////////////
1163 40 unneback
`ifdef MUX_ANDOR
1164
`define MODULE mux_andor
1165
module `BASE`MODULE ( a, sel, dout);
1166
`undef MODULE
1167 36 unneback
 
1168
parameter width = 32;
1169
parameter nr_of_ports = 4;
1170
 
1171
input [nr_of_ports*width-1:0] a;
1172
input [nr_of_ports-1:0] sel;
1173
output reg [width-1:0] dout;
1174
 
1175 38 unneback
integer i,j;
1176
 
1177 36 unneback
always @ (a, sel)
1178
begin
1179
    dout = a[width-1:0] & {width{sel[0]}};
1180 42 unneback
    for (i=1;i<nr_of_ports;i=i+1)
1181
        for (j=0;j<width;j=j+1)
1182
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
1183 36 unneback
end
1184
 
1185
endmodule
1186 40 unneback
`endif
1187 36 unneback
 
1188 40 unneback
`ifdef MUX2_ANDOR
1189
`define MODULE mux2_andor
1190
module `BASE`MODULE ( a1, a0, sel, dout);
1191
`undef MODULE
1192 18 unneback
 
1193 34 unneback
parameter width = 32;
1194 35 unneback
localparam nr_of_ports = 2;
1195 34 unneback
input [width-1:0] a1, a0;
1196
input [nr_of_ports-1:0] sel;
1197
output [width-1:0] dout;
1198
 
1199 40 unneback
`define MODULE mux_andor
1200
`BASE`MODULE
1201 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1202 36 unneback
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
1203 40 unneback
`undef MODULE
1204
 
1205 34 unneback
endmodule
1206 40 unneback
`endif
1207 34 unneback
 
1208 40 unneback
`ifdef MUX3_ANDOR
1209
`define MODULE mux3_andor
1210
module `BASE`MODULE ( a2, a1, a0, sel, dout);
1211
`undef MODULE
1212 34 unneback
 
1213
parameter width = 32;
1214 35 unneback
localparam nr_of_ports = 3;
1215 34 unneback
input [width-1:0] a2, a1, a0;
1216
input [nr_of_ports-1:0] sel;
1217
output [width-1:0] dout;
1218
 
1219 40 unneback
`define MODULE mux_andor
1220
`BASE`MODULE
1221 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1222 36 unneback
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
1223 40 unneback
`undef MODULE
1224 34 unneback
endmodule
1225 40 unneback
`endif
1226 34 unneback
 
1227 40 unneback
`ifdef MUX4_ANDOR
1228
`define MODULE mux4_andor
1229
module `BASE`MODULE ( a3, a2, a1, a0, sel, dout);
1230
`undef MODULE
1231 18 unneback
 
1232
parameter width = 32;
1233 35 unneback
localparam nr_of_ports = 4;
1234 18 unneback
input [width-1:0] a3, a2, a1, a0;
1235
input [nr_of_ports-1:0] sel;
1236 22 unneback
output [width-1:0] dout;
1237 18 unneback
 
1238 40 unneback
`define MODULE mux_andor
1239
`BASE`MODULE
1240 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1241 36 unneback
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
1242 40 unneback
`undef MODULE
1243 18 unneback
 
1244
endmodule
1245 40 unneback
`endif
1246 18 unneback
 
1247 40 unneback
`ifdef MUX5_ANDOR
1248
`define MODULE mux5_andor
1249
module `BASE`MODULE ( a4, a3, a2, a1, a0, sel, dout);
1250
`undef MODULE
1251 18 unneback
 
1252
parameter width = 32;
1253 35 unneback
localparam nr_of_ports = 5;
1254 18 unneback
input [width-1:0] a4, a3, a2, a1, a0;
1255
input [nr_of_ports-1:0] sel;
1256 22 unneback
output [width-1:0] dout;
1257 18 unneback
 
1258 40 unneback
`define MODULE mux_andor
1259
`BASE`MODULE
1260 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1261 36 unneback
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1262 40 unneback
`undef MODULE
1263 18 unneback
 
1264
endmodule
1265 40 unneback
`endif
1266 18 unneback
 
1267 40 unneback
`ifdef MUX6_ANDOR
1268
`define MODULE mux6_andor
1269
module `BASE`MODULE ( a5, a4, a3, a2, a1, a0, sel, dout);
1270
`undef MODULE
1271 18 unneback
 
1272
parameter width = 32;
1273 35 unneback
localparam nr_of_ports = 6;
1274 18 unneback
input [width-1:0] a5, a4, a3, a2, a1, a0;
1275
input [nr_of_ports-1:0] sel;
1276 22 unneback
output [width-1:0] dout;
1277 18 unneback
 
1278 40 unneback
`define MODULE mux_andor
1279
`BASE`MODULE
1280 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1281 36 unneback
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1282 40 unneback
`undef MODULE
1283 18 unneback
 
1284
endmodule
1285 40 unneback
`endif
1286 43 unneback
 
1287
`ifdef PARITY
1288
 
1289
`define MODULE parity_generate
1290
module `BASE`MODULE (data, parity);
1291
`undef MODULE
1292
parameter word_size = 32;
1293
parameter chunk_size = 8;
1294
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1295
input [word_size-1:0] data;
1296
output reg [word_size/chunk_size-1:0] parity;
1297
integer i,j;
1298
always @ (data)
1299
for (i=0;i<word_size/chunk_size;i=i+1) begin
1300
    parity[i] = parity_type;
1301
    for (j=0;j<chunk_size;j=j+1) begin
1302
        parity[i] = data[i+j] ^ parity[i];
1303
    end
1304
end
1305
endmodule
1306
 
1307
`define MODULE parity_check
1308
module `BASE`MODULE( data, parity, parity_error);
1309
`undef MODULE
1310
parameter word_size = 32;
1311
parameter chunk_size = 8;
1312
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1313
input [word_size-1:0] data;
1314
input [word_size/chunk_size-1:0] parity;
1315
output parity_error;
1316 44 unneback
reg [word_size/chunk_size-1:0] error_flag;
1317 43 unneback
integer i,j;
1318
always @ (data or parity)
1319
for (i=0;i<word_size/chunk_size;i=i+1) begin
1320
    error_flag[i] = parity[i] ^ parity_type;
1321
    for (j=0;j<chunk_size;j=j+1) begin
1322
        error_flag[i] = data[i+j] ^ error_flag[i];
1323
    end
1324
end
1325
assign parity_error = |error_flag;
1326
endmodule
1327
 
1328 44 unneback
`endif//////////////////////////////////////////////////////////////////////
1329
////                                                              ////
1330
////  IO functions                                                ////
1331
////                                                              ////
1332
////  Description                                                 ////
1333
////  IO functions such as IOB flip-flops                         ////
1334
////                                                              ////
1335
////                                                              ////
1336
////  To Do:                                                      ////
1337
////   -                                                          ////
1338
////                                                              ////
1339
////  Author(s):                                                  ////
1340
////      - Michael Unneback, unneback@opencores.org              ////
1341
////        ORSoC AB                                              ////
1342
////                                                              ////
1343 18 unneback
//////////////////////////////////////////////////////////////////////
1344
////                                                              ////
1345 44 unneback
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1346
////                                                              ////
1347
//// This source file may be used and distributed without         ////
1348
//// restriction provided that this copyright statement is not    ////
1349
//// removed from the file and that any derivative work contains  ////
1350
//// the original copyright notice and the associated disclaimer. ////
1351
////                                                              ////
1352
//// This source file is free software; you can redistribute it   ////
1353
//// and/or modify it under the terms of the GNU Lesser General   ////
1354
//// Public License as published by the Free Software Foundation; ////
1355
//// either version 2.1 of the License, or (at your option) any   ////
1356
//// later version.                                               ////
1357
////                                                              ////
1358
//// This source is distributed in the hope that it will be       ////
1359
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1360
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1361
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1362
//// details.                                                     ////
1363
////                                                              ////
1364
//// You should have received a copy of the GNU Lesser General    ////
1365
//// Public License along with this source; if not, download it   ////
1366
//// from http://www.opencores.org/lgpl.shtml                     ////
1367
////                                                              ////
1368
//////////////////////////////////////////////////////////////////////
1369 45 unneback
`timescale 1ns/1ns
1370 44 unneback
`ifdef O_DFF
1371
`define MODULE o_dff
1372
module `BASE`MODULE (d_i, o_pad, clk, rst);
1373
`undef MODULE
1374
parameter width = 1;
1375 45 unneback
parameter reset_value = {width{1'b0}};
1376
input  [width-1:0]  d_i;
1377 44 unneback
output [width-1:0] o_pad;
1378
input clk, rst;
1379
wire [width-1:0] d_i_int `SYN_KEEP;
1380 45 unneback
reg  [width-1:0] o_pad_int;
1381 44 unneback
assign d_i_int = d_i;
1382
genvar i;
1383 45 unneback
generate
1384 44 unneback
for (i=0;i<width;i=i+1) begin
1385
    always @ (posedge clk or posedge rst)
1386
    if (rst)
1387 45 unneback
        o_pad_int[i] <= reset_value[i];
1388 44 unneback
    else
1389 45 unneback
        o_pad_int[i] <= d_i_int[i];
1390
    assign #1 o_pad[i] = o_pad_int[i];
1391 44 unneback
end
1392
endgenerate
1393
endmodule
1394
`endif
1395
 
1396 45 unneback
`timescale 1ns/1ns
1397 44 unneback
`ifdef IO_DFF_OE
1398
`define MODULE io_dff_oe
1399
module `BASE`MODULE ( d_i, d_o, oe, io_pad, clk, rst);
1400
`undef MODULE
1401
parameter width = 1;
1402
input  [width-1:0] d_o;
1403
output reg [width-1:0] d_i;
1404
input oe;
1405
inout [width-1:0] io_pad;
1406
input clk, rst;
1407
wire [width-1:0] oe_d `SYN_KEEP;
1408
reg [width-1:0] oe_q;
1409
reg [width-1:0] d_o_q;
1410
assign oe_d = {width{oe}};
1411
genvar i;
1412
generate
1413
for (i=0;i<width;i=i+1) begin
1414
    always @ (posedge clk or posedge rst)
1415
    if (rst)
1416
        oe_q[i] <= 1'b0;
1417
    else
1418
        oe_q[i] <= oe_d[i];
1419
    always @ (posedge clk or posedge rst)
1420
    if (rst)
1421
        d_o_q[i] <= 1'b0;
1422
    else
1423
        d_o_q[i] <= d_o[i];
1424
    always @ (posedge clk or posedge rst)
1425
    if (rst)
1426
        d_i[i] <= 1'b0;
1427
    else
1428
        d_i[i] <= io_pad[i];
1429 45 unneback
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
1430 44 unneback
end
1431
endgenerate
1432
endmodule
1433
`endif
1434
`ifdef CNT_BIN
1435
//////////////////////////////////////////////////////////////////////
1436
////                                                              ////
1437 6 unneback
////  Versatile counter                                           ////
1438
////                                                              ////
1439
////  Description                                                 ////
1440
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1441
////  counter                                                     ////
1442
////                                                              ////
1443
////  To Do:                                                      ////
1444
////   - add LFSR with more taps                                  ////
1445
////                                                              ////
1446
////  Author(s):                                                  ////
1447
////      - Michael Unneback, unneback@opencores.org              ////
1448
////        ORSoC AB                                              ////
1449
////                                                              ////
1450
//////////////////////////////////////////////////////////////////////
1451
////                                                              ////
1452
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1453
////                                                              ////
1454
//// This source file may be used and distributed without         ////
1455
//// restriction provided that this copyright statement is not    ////
1456
//// removed from the file and that any derivative work contains  ////
1457
//// the original copyright notice and the associated disclaimer. ////
1458
////                                                              ////
1459
//// This source file is free software; you can redistribute it   ////
1460
//// and/or modify it under the terms of the GNU Lesser General   ////
1461
//// Public License as published by the Free Software Foundation; ////
1462
//// either version 2.1 of the License, or (at your option) any   ////
1463
//// later version.                                               ////
1464
////                                                              ////
1465
//// This source is distributed in the hope that it will be       ////
1466
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1467
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1468
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1469
//// details.                                                     ////
1470
////                                                              ////
1471
//// You should have received a copy of the GNU Lesser General    ////
1472
//// Public License along with this source; if not, download it   ////
1473
//// from http://www.opencores.org/lgpl.shtml                     ////
1474
////                                                              ////
1475
//////////////////////////////////////////////////////////////////////
1476
 
1477
// binary counter
1478 22 unneback
 
1479 40 unneback
`define MODULE cnt_bin
1480
module `BASE`MODULE (
1481
`undef MODULE
1482
 q, rst, clk);
1483
 
1484 22 unneback
   parameter length = 4;
1485
   output [length:1] q;
1486
   input rst;
1487
   input clk;
1488
 
1489
   parameter clear_value = 0;
1490
   parameter set_value = 1;
1491
   parameter wrap_value = 0;
1492
   parameter level1_value = 15;
1493
 
1494
   reg  [length:1] qi;
1495
   wire [length:1] q_next;
1496
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1497
 
1498
   always @ (posedge clk or posedge rst)
1499
     if (rst)
1500
       qi <= {length{1'b0}};
1501
     else
1502
       qi <= q_next;
1503
 
1504
   assign q = qi;
1505
 
1506
endmodule
1507 40 unneback
`endif
1508
`ifdef CNT_BIN_CLEAR
1509 22 unneback
//////////////////////////////////////////////////////////////////////
1510
////                                                              ////
1511
////  Versatile counter                                           ////
1512
////                                                              ////
1513
////  Description                                                 ////
1514
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1515
////  counter                                                     ////
1516
////                                                              ////
1517
////  To Do:                                                      ////
1518
////   - add LFSR with more taps                                  ////
1519
////                                                              ////
1520
////  Author(s):                                                  ////
1521
////      - Michael Unneback, unneback@opencores.org              ////
1522
////        ORSoC AB                                              ////
1523
////                                                              ////
1524
//////////////////////////////////////////////////////////////////////
1525
////                                                              ////
1526
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1527
////                                                              ////
1528
//// This source file may be used and distributed without         ////
1529
//// restriction provided that this copyright statement is not    ////
1530
//// removed from the file and that any derivative work contains  ////
1531
//// the original copyright notice and the associated disclaimer. ////
1532
////                                                              ////
1533
//// This source file is free software; you can redistribute it   ////
1534
//// and/or modify it under the terms of the GNU Lesser General   ////
1535
//// Public License as published by the Free Software Foundation; ////
1536
//// either version 2.1 of the License, or (at your option) any   ////
1537
//// later version.                                               ////
1538
////                                                              ////
1539
//// This source is distributed in the hope that it will be       ////
1540
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1541
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1542
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1543
//// details.                                                     ////
1544
////                                                              ////
1545
//// You should have received a copy of the GNU Lesser General    ////
1546
//// Public License along with this source; if not, download it   ////
1547
//// from http://www.opencores.org/lgpl.shtml                     ////
1548
////                                                              ////
1549
//////////////////////////////////////////////////////////////////////
1550
 
1551
// binary counter
1552
 
1553 40 unneback
`define MODULE cnt_bin_clear
1554
module `BASE`MODULE (
1555
`undef MODULE
1556
 clear, q, rst, clk);
1557
 
1558 22 unneback
   parameter length = 4;
1559
   input clear;
1560
   output [length:1] q;
1561
   input rst;
1562
   input clk;
1563
 
1564
   parameter clear_value = 0;
1565
   parameter set_value = 1;
1566
   parameter wrap_value = 0;
1567
   parameter level1_value = 15;
1568
 
1569
   reg  [length:1] qi;
1570
   wire [length:1] q_next;
1571
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1572
 
1573
   always @ (posedge clk or posedge rst)
1574
     if (rst)
1575
       qi <= {length{1'b0}};
1576
     else
1577
       qi <= q_next;
1578
 
1579
   assign q = qi;
1580
 
1581
endmodule
1582 40 unneback
`endif
1583
`ifdef CNT_BIN_CE
1584 22 unneback
//////////////////////////////////////////////////////////////////////
1585
////                                                              ////
1586
////  Versatile counter                                           ////
1587
////                                                              ////
1588
////  Description                                                 ////
1589
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1590
////  counter                                                     ////
1591
////                                                              ////
1592
////  To Do:                                                      ////
1593
////   - add LFSR with more taps                                  ////
1594
////                                                              ////
1595
////  Author(s):                                                  ////
1596
////      - Michael Unneback, unneback@opencores.org              ////
1597
////        ORSoC AB                                              ////
1598
////                                                              ////
1599
//////////////////////////////////////////////////////////////////////
1600
////                                                              ////
1601
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1602
////                                                              ////
1603
//// This source file may be used and distributed without         ////
1604
//// restriction provided that this copyright statement is not    ////
1605
//// removed from the file and that any derivative work contains  ////
1606
//// the original copyright notice and the associated disclaimer. ////
1607
////                                                              ////
1608
//// This source file is free software; you can redistribute it   ////
1609
//// and/or modify it under the terms of the GNU Lesser General   ////
1610
//// Public License as published by the Free Software Foundation; ////
1611
//// either version 2.1 of the License, or (at your option) any   ////
1612
//// later version.                                               ////
1613
////                                                              ////
1614
//// This source is distributed in the hope that it will be       ////
1615
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1616
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1617
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1618
//// details.                                                     ////
1619
////                                                              ////
1620
//// You should have received a copy of the GNU Lesser General    ////
1621
//// Public License along with this source; if not, download it   ////
1622
//// from http://www.opencores.org/lgpl.shtml                     ////
1623
////                                                              ////
1624
//////////////////////////////////////////////////////////////////////
1625
 
1626
// binary counter
1627 6 unneback
 
1628 40 unneback
`define MODULE cnt_bin_ce
1629
module `BASE`MODULE (
1630
`undef MODULE
1631
 cke, q, rst, clk);
1632
 
1633 6 unneback
   parameter length = 4;
1634
   input cke;
1635
   output [length:1] q;
1636
   input rst;
1637
   input clk;
1638
 
1639
   parameter clear_value = 0;
1640
   parameter set_value = 1;
1641
   parameter wrap_value = 0;
1642
   parameter level1_value = 15;
1643
 
1644
   reg  [length:1] qi;
1645
   wire [length:1] q_next;
1646
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1647
 
1648
   always @ (posedge clk or posedge rst)
1649
     if (rst)
1650
       qi <= {length{1'b0}};
1651
     else
1652
     if (cke)
1653
       qi <= q_next;
1654
 
1655
   assign q = qi;
1656
 
1657
endmodule
1658 40 unneback
`endif
1659
`ifdef CNT_BIN_CE_CLEAR
1660 6 unneback
//////////////////////////////////////////////////////////////////////
1661
////                                                              ////
1662
////  Versatile counter                                           ////
1663
////                                                              ////
1664
////  Description                                                 ////
1665
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1666
////  counter                                                     ////
1667
////                                                              ////
1668
////  To Do:                                                      ////
1669
////   - add LFSR with more taps                                  ////
1670
////                                                              ////
1671
////  Author(s):                                                  ////
1672
////      - Michael Unneback, unneback@opencores.org              ////
1673
////        ORSoC AB                                              ////
1674
////                                                              ////
1675
//////////////////////////////////////////////////////////////////////
1676
////                                                              ////
1677
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1678
////                                                              ////
1679
//// This source file may be used and distributed without         ////
1680
//// restriction provided that this copyright statement is not    ////
1681
//// removed from the file and that any derivative work contains  ////
1682
//// the original copyright notice and the associated disclaimer. ////
1683
////                                                              ////
1684
//// This source file is free software; you can redistribute it   ////
1685
//// and/or modify it under the terms of the GNU Lesser General   ////
1686
//// Public License as published by the Free Software Foundation; ////
1687
//// either version 2.1 of the License, or (at your option) any   ////
1688
//// later version.                                               ////
1689
////                                                              ////
1690
//// This source is distributed in the hope that it will be       ////
1691
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1692
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1693
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1694
//// details.                                                     ////
1695
////                                                              ////
1696
//// You should have received a copy of the GNU Lesser General    ////
1697
//// Public License along with this source; if not, download it   ////
1698
//// from http://www.opencores.org/lgpl.shtml                     ////
1699
////                                                              ////
1700
//////////////////////////////////////////////////////////////////////
1701
 
1702
// binary counter
1703
 
1704 40 unneback
`define MODULE cnt_bin_ce_clear
1705
module `BASE`MODULE (
1706
`undef MODULE
1707
 clear, cke, q, rst, clk);
1708
 
1709 6 unneback
   parameter length = 4;
1710
   input clear;
1711
   input cke;
1712
   output [length:1] q;
1713
   input rst;
1714
   input clk;
1715
 
1716
   parameter clear_value = 0;
1717
   parameter set_value = 1;
1718
   parameter wrap_value = 0;
1719
   parameter level1_value = 15;
1720
 
1721
   reg  [length:1] qi;
1722
   wire [length:1] q_next;
1723
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1724
 
1725
   always @ (posedge clk or posedge rst)
1726
     if (rst)
1727
       qi <= {length{1'b0}};
1728
     else
1729
     if (cke)
1730
       qi <= q_next;
1731
 
1732
   assign q = qi;
1733
 
1734
endmodule
1735 40 unneback
`endif
1736
`ifdef CNT_BIN_CE_CLEAR_L1_L2
1737 6 unneback
//////////////////////////////////////////////////////////////////////
1738
////                                                              ////
1739
////  Versatile counter                                           ////
1740
////                                                              ////
1741
////  Description                                                 ////
1742
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1743
////  counter                                                     ////
1744
////                                                              ////
1745
////  To Do:                                                      ////
1746
////   - add LFSR with more taps                                  ////
1747
////                                                              ////
1748
////  Author(s):                                                  ////
1749
////      - Michael Unneback, unneback@opencores.org              ////
1750
////        ORSoC AB                                              ////
1751
////                                                              ////
1752
//////////////////////////////////////////////////////////////////////
1753
////                                                              ////
1754
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1755
////                                                              ////
1756
//// This source file may be used and distributed without         ////
1757
//// restriction provided that this copyright statement is not    ////
1758
//// removed from the file and that any derivative work contains  ////
1759
//// the original copyright notice and the associated disclaimer. ////
1760
////                                                              ////
1761
//// This source file is free software; you can redistribute it   ////
1762
//// and/or modify it under the terms of the GNU Lesser General   ////
1763
//// Public License as published by the Free Software Foundation; ////
1764
//// either version 2.1 of the License, or (at your option) any   ////
1765
//// later version.                                               ////
1766
////                                                              ////
1767
//// This source is distributed in the hope that it will be       ////
1768
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1769
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1770
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1771
//// details.                                                     ////
1772
////                                                              ////
1773
//// You should have received a copy of the GNU Lesser General    ////
1774
//// Public License along with this source; if not, download it   ////
1775
//// from http://www.opencores.org/lgpl.shtml                     ////
1776
////                                                              ////
1777
//////////////////////////////////////////////////////////////////////
1778
 
1779
// binary counter
1780 29 unneback
 
1781 40 unneback
`define MODULE cnt_bin_ce_clear_l1_l2
1782
module `BASE`MODULE (
1783
`undef MODULE
1784
 clear, cke, q, level1, level2, rst, clk);
1785
 
1786 29 unneback
   parameter length = 4;
1787
   input clear;
1788
   input cke;
1789
   output [length:1] q;
1790
   output reg level1;
1791
   output reg level2;
1792
   input rst;
1793
   input clk;
1794
 
1795
   parameter clear_value = 0;
1796
   parameter set_value = 1;
1797 30 unneback
   parameter wrap_value = 15;
1798
   parameter level1_value = 8;
1799
   parameter level2_value = 15;
1800 29 unneback
 
1801
   wire rew;
1802 30 unneback
   assign rew = 1'b0;
1803 29 unneback
   reg  [length:1] qi;
1804
   wire [length:1] q_next;
1805
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1806
 
1807
   always @ (posedge clk or posedge rst)
1808
     if (rst)
1809
       qi <= {length{1'b0}};
1810
     else
1811
     if (cke)
1812
       qi <= q_next;
1813
 
1814
   assign q = qi;
1815
 
1816
 
1817
    always @ (posedge clk or posedge rst)
1818
    if (rst)
1819
        level1 <= 1'b0;
1820
    else
1821
    if (cke)
1822
    if (clear)
1823
        level1 <= 1'b0;
1824
    else if (q_next == level1_value)
1825
        level1 <= 1'b1;
1826
    else if (qi == level1_value & rew)
1827
        level1 <= 1'b0;
1828
 
1829
    always @ (posedge clk or posedge rst)
1830
    if (rst)
1831
        level2 <= 1'b0;
1832
    else
1833
    if (cke)
1834
    if (clear)
1835
        level2 <= 1'b0;
1836
    else if (q_next == level2_value)
1837
        level2 <= 1'b1;
1838
    else if (qi == level2_value & rew)
1839
        level2 <= 1'b0;
1840
endmodule
1841 40 unneback
`endif
1842
`ifdef CNT_BIN_CE_CLEAR_SET_REW
1843 29 unneback
//////////////////////////////////////////////////////////////////////
1844
////                                                              ////
1845
////  Versatile counter                                           ////
1846
////                                                              ////
1847
////  Description                                                 ////
1848
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1849
////  counter                                                     ////
1850
////                                                              ////
1851
////  To Do:                                                      ////
1852
////   - add LFSR with more taps                                  ////
1853
////                                                              ////
1854
////  Author(s):                                                  ////
1855
////      - Michael Unneback, unneback@opencores.org              ////
1856
////        ORSoC AB                                              ////
1857
////                                                              ////
1858
//////////////////////////////////////////////////////////////////////
1859
////                                                              ////
1860
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1861
////                                                              ////
1862
//// This source file may be used and distributed without         ////
1863
//// restriction provided that this copyright statement is not    ////
1864
//// removed from the file and that any derivative work contains  ////
1865
//// the original copyright notice and the associated disclaimer. ////
1866
////                                                              ////
1867
//// This source file is free software; you can redistribute it   ////
1868
//// and/or modify it under the terms of the GNU Lesser General   ////
1869
//// Public License as published by the Free Software Foundation; ////
1870
//// either version 2.1 of the License, or (at your option) any   ////
1871
//// later version.                                               ////
1872
////                                                              ////
1873
//// This source is distributed in the hope that it will be       ////
1874
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1875
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1876
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1877
//// details.                                                     ////
1878
////                                                              ////
1879
//// You should have received a copy of the GNU Lesser General    ////
1880
//// Public License along with this source; if not, download it   ////
1881
//// from http://www.opencores.org/lgpl.shtml                     ////
1882
////                                                              ////
1883
//////////////////////////////////////////////////////////////////////
1884
 
1885
// binary counter
1886 6 unneback
 
1887 40 unneback
`define MODULE cnt_bin_ce_clear_set_rew
1888
module `BASE`MODULE (
1889
`undef MODULE
1890
 clear, set, cke, rew, q, rst, clk);
1891
 
1892 6 unneback
   parameter length = 4;
1893
   input clear;
1894
   input set;
1895
   input cke;
1896
   input rew;
1897
   output [length:1] q;
1898
   input rst;
1899
   input clk;
1900
 
1901
   parameter clear_value = 0;
1902
   parameter set_value = 1;
1903
   parameter wrap_value = 0;
1904
   parameter level1_value = 15;
1905
 
1906
   reg  [length:1] qi;
1907
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1908
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
1909
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
1910
   assign q_next = rew ? q_next_rew : q_next_fw;
1911
 
1912
   always @ (posedge clk or posedge rst)
1913
     if (rst)
1914
       qi <= {length{1'b0}};
1915
     else
1916
     if (cke)
1917
       qi <= q_next;
1918
 
1919
   assign q = qi;
1920
 
1921
endmodule
1922 40 unneback
`endif
1923
`ifdef CNT_BIN_CE_REW_L1
1924 6 unneback
//////////////////////////////////////////////////////////////////////
1925
////                                                              ////
1926
////  Versatile counter                                           ////
1927
////                                                              ////
1928
////  Description                                                 ////
1929
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1930
////  counter                                                     ////
1931
////                                                              ////
1932
////  To Do:                                                      ////
1933
////   - add LFSR with more taps                                  ////
1934
////                                                              ////
1935
////  Author(s):                                                  ////
1936
////      - Michael Unneback, unneback@opencores.org              ////
1937
////        ORSoC AB                                              ////
1938
////                                                              ////
1939
//////////////////////////////////////////////////////////////////////
1940
////                                                              ////
1941
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1942
////                                                              ////
1943
//// This source file may be used and distributed without         ////
1944
//// restriction provided that this copyright statement is not    ////
1945
//// removed from the file and that any derivative work contains  ////
1946
//// the original copyright notice and the associated disclaimer. ////
1947
////                                                              ////
1948
//// This source file is free software; you can redistribute it   ////
1949
//// and/or modify it under the terms of the GNU Lesser General   ////
1950
//// Public License as published by the Free Software Foundation; ////
1951
//// either version 2.1 of the License, or (at your option) any   ////
1952
//// later version.                                               ////
1953
////                                                              ////
1954
//// This source is distributed in the hope that it will be       ////
1955
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1956
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1957
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1958
//// details.                                                     ////
1959
////                                                              ////
1960
//// You should have received a copy of the GNU Lesser General    ////
1961
//// Public License along with this source; if not, download it   ////
1962
//// from http://www.opencores.org/lgpl.shtml                     ////
1963
////                                                              ////
1964
//////////////////////////////////////////////////////////////////////
1965
 
1966
// binary counter
1967
 
1968 40 unneback
`define MODULE cnt_bin_ce_rew_l1
1969
module `BASE`MODULE (
1970
`undef MODULE
1971
 cke, rew, level1, rst, clk);
1972
 
1973 6 unneback
   parameter length = 4;
1974
   input cke;
1975
   input rew;
1976
   output reg level1;
1977
   input rst;
1978
   input clk;
1979
 
1980
   parameter clear_value = 0;
1981
   parameter set_value = 1;
1982
   parameter wrap_value = 1;
1983
   parameter level1_value = 15;
1984
 
1985 29 unneback
   wire clear;
1986 30 unneback
   assign clear = 1'b0;
1987 6 unneback
   reg  [length:1] qi;
1988
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1989
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1990
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1991
   assign q_next = rew ? q_next_rew : q_next_fw;
1992
 
1993
   always @ (posedge clk or posedge rst)
1994
     if (rst)
1995
       qi <= {length{1'b0}};
1996
     else
1997
     if (cke)
1998
       qi <= q_next;
1999
 
2000
 
2001
 
2002
    always @ (posedge clk or posedge rst)
2003
    if (rst)
2004
        level1 <= 1'b0;
2005
    else
2006
    if (cke)
2007 29 unneback
    if (clear)
2008
        level1 <= 1'b0;
2009
    else if (q_next == level1_value)
2010 6 unneback
        level1 <= 1'b1;
2011
    else if (qi == level1_value & rew)
2012
        level1 <= 1'b0;
2013
endmodule
2014 40 unneback
`endif
2015
`ifdef CNT_BIN_CE_REW_ZQ_L1
2016 6 unneback
//////////////////////////////////////////////////////////////////////
2017
////                                                              ////
2018
////  Versatile counter                                           ////
2019
////                                                              ////
2020
////  Description                                                 ////
2021
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2022
////  counter                                                     ////
2023
////                                                              ////
2024
////  To Do:                                                      ////
2025
////   - add LFSR with more taps                                  ////
2026
////                                                              ////
2027
////  Author(s):                                                  ////
2028
////      - Michael Unneback, unneback@opencores.org              ////
2029
////        ORSoC AB                                              ////
2030
////                                                              ////
2031
//////////////////////////////////////////////////////////////////////
2032
////                                                              ////
2033
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2034
////                                                              ////
2035
//// This source file may be used and distributed without         ////
2036
//// restriction provided that this copyright statement is not    ////
2037
//// removed from the file and that any derivative work contains  ////
2038
//// the original copyright notice and the associated disclaimer. ////
2039
////                                                              ////
2040
//// This source file is free software; you can redistribute it   ////
2041
//// and/or modify it under the terms of the GNU Lesser General   ////
2042
//// Public License as published by the Free Software Foundation; ////
2043
//// either version 2.1 of the License, or (at your option) any   ////
2044
//// later version.                                               ////
2045
////                                                              ////
2046
//// This source is distributed in the hope that it will be       ////
2047
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2048
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2049
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2050
//// details.                                                     ////
2051
////                                                              ////
2052
//// You should have received a copy of the GNU Lesser General    ////
2053
//// Public License along with this source; if not, download it   ////
2054
//// from http://www.opencores.org/lgpl.shtml                     ////
2055
////                                                              ////
2056
//////////////////////////////////////////////////////////////////////
2057
 
2058 25 unneback
// binary counter
2059
 
2060 40 unneback
`define MODULE cnt_bin_ce_rew_zq_l1
2061
module `BASE`MODULE (
2062
`undef MODULE
2063
 cke, rew, zq, level1, rst, clk);
2064
 
2065 25 unneback
   parameter length = 4;
2066
   input cke;
2067
   input rew;
2068
   output reg zq;
2069
   output reg level1;
2070
   input rst;
2071
   input clk;
2072
 
2073
   parameter clear_value = 0;
2074
   parameter set_value = 1;
2075
   parameter wrap_value = 1;
2076
   parameter level1_value = 15;
2077
 
2078 29 unneback
   wire clear;
2079 30 unneback
   assign clear = 1'b0;
2080 25 unneback
   reg  [length:1] qi;
2081
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2082
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2083
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2084
   assign q_next = rew ? q_next_rew : q_next_fw;
2085
 
2086
   always @ (posedge clk or posedge rst)
2087
     if (rst)
2088
       qi <= {length{1'b0}};
2089
     else
2090
     if (cke)
2091
       qi <= q_next;
2092
 
2093
 
2094
 
2095
   always @ (posedge clk or posedge rst)
2096
     if (rst)
2097
       zq <= 1'b1;
2098
     else
2099
     if (cke)
2100
       zq <= q_next == {length{1'b0}};
2101
 
2102
    always @ (posedge clk or posedge rst)
2103
    if (rst)
2104
        level1 <= 1'b0;
2105
    else
2106
    if (cke)
2107 29 unneback
    if (clear)
2108
        level1 <= 1'b0;
2109
    else if (q_next == level1_value)
2110 25 unneback
        level1 <= 1'b1;
2111
    else if (qi == level1_value & rew)
2112
        level1 <= 1'b0;
2113
endmodule
2114 40 unneback
`endif
2115
`ifdef CNT_BIN_CE_REW_Q_ZQ_L1
2116 25 unneback
//////////////////////////////////////////////////////////////////////
2117
////                                                              ////
2118
////  Versatile counter                                           ////
2119
////                                                              ////
2120
////  Description                                                 ////
2121
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2122
////  counter                                                     ////
2123
////                                                              ////
2124
////  To Do:                                                      ////
2125
////   - add LFSR with more taps                                  ////
2126
////                                                              ////
2127
////  Author(s):                                                  ////
2128
////      - Michael Unneback, unneback@opencores.org              ////
2129
////        ORSoC AB                                              ////
2130
////                                                              ////
2131
//////////////////////////////////////////////////////////////////////
2132
////                                                              ////
2133
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2134
////                                                              ////
2135
//// This source file may be used and distributed without         ////
2136
//// restriction provided that this copyright statement is not    ////
2137
//// removed from the file and that any derivative work contains  ////
2138
//// the original copyright notice and the associated disclaimer. ////
2139
////                                                              ////
2140
//// This source file is free software; you can redistribute it   ////
2141
//// and/or modify it under the terms of the GNU Lesser General   ////
2142
//// Public License as published by the Free Software Foundation; ////
2143
//// either version 2.1 of the License, or (at your option) any   ////
2144
//// later version.                                               ////
2145
////                                                              ////
2146
//// This source is distributed in the hope that it will be       ////
2147
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2148
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2149
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2150
//// details.                                                     ////
2151
////                                                              ////
2152
//// You should have received a copy of the GNU Lesser General    ////
2153
//// Public License along with this source; if not, download it   ////
2154
//// from http://www.opencores.org/lgpl.shtml                     ////
2155
////                                                              ////
2156
//////////////////////////////////////////////////////////////////////
2157
 
2158
// binary counter
2159
 
2160 40 unneback
`define MODULE cnt_bin_ce_rew_q_zq_l1
2161
module `BASE`MODULE (
2162
`undef MODULE
2163
 cke, rew, q, zq, level1, rst, clk);
2164
 
2165 25 unneback
   parameter length = 4;
2166
   input cke;
2167
   input rew;
2168
   output [length:1] q;
2169
   output reg zq;
2170
   output reg level1;
2171
   input rst;
2172
   input clk;
2173
 
2174
   parameter clear_value = 0;
2175
   parameter set_value = 1;
2176
   parameter wrap_value = 1;
2177
   parameter level1_value = 15;
2178
 
2179 29 unneback
   wire clear;
2180 30 unneback
   assign clear = 1'b0;
2181 25 unneback
   reg  [length:1] qi;
2182
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2183
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2184
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2185
   assign q_next = rew ? q_next_rew : q_next_fw;
2186
 
2187
   always @ (posedge clk or posedge rst)
2188
     if (rst)
2189
       qi <= {length{1'b0}};
2190
     else
2191
     if (cke)
2192
       qi <= q_next;
2193
 
2194
   assign q = qi;
2195
 
2196
 
2197
   always @ (posedge clk or posedge rst)
2198
     if (rst)
2199
       zq <= 1'b1;
2200
     else
2201
     if (cke)
2202
       zq <= q_next == {length{1'b0}};
2203
 
2204
    always @ (posedge clk or posedge rst)
2205
    if (rst)
2206
        level1 <= 1'b0;
2207
    else
2208
    if (cke)
2209 29 unneback
    if (clear)
2210
        level1 <= 1'b0;
2211
    else if (q_next == level1_value)
2212 25 unneback
        level1 <= 1'b1;
2213
    else if (qi == level1_value & rew)
2214
        level1 <= 1'b0;
2215
endmodule
2216 40 unneback
`endif
2217
`ifdef CNT_LFSR_ZQ
2218 25 unneback
//////////////////////////////////////////////////////////////////////
2219
////                                                              ////
2220
////  Versatile counter                                           ////
2221
////                                                              ////
2222
////  Description                                                 ////
2223
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2224
////  counter                                                     ////
2225
////                                                              ////
2226
////  To Do:                                                      ////
2227
////   - add LFSR with more taps                                  ////
2228
////                                                              ////
2229
////  Author(s):                                                  ////
2230
////      - Michael Unneback, unneback@opencores.org              ////
2231
////        ORSoC AB                                              ////
2232
////                                                              ////
2233
//////////////////////////////////////////////////////////////////////
2234
////                                                              ////
2235
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2236
////                                                              ////
2237
//// This source file may be used and distributed without         ////
2238
//// restriction provided that this copyright statement is not    ////
2239
//// removed from the file and that any derivative work contains  ////
2240
//// the original copyright notice and the associated disclaimer. ////
2241
////                                                              ////
2242
//// This source file is free software; you can redistribute it   ////
2243
//// and/or modify it under the terms of the GNU Lesser General   ////
2244
//// Public License as published by the Free Software Foundation; ////
2245
//// either version 2.1 of the License, or (at your option) any   ////
2246
//// later version.                                               ////
2247
////                                                              ////
2248
//// This source is distributed in the hope that it will be       ////
2249
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2250
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2251
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2252
//// details.                                                     ////
2253
////                                                              ////
2254
//// You should have received a copy of the GNU Lesser General    ////
2255
//// Public License along with this source; if not, download it   ////
2256
//// from http://www.opencores.org/lgpl.shtml                     ////
2257
////                                                              ////
2258
//////////////////////////////////////////////////////////////////////
2259
 
2260 6 unneback
// LFSR counter
2261
 
2262 40 unneback
`define MODULE cnt_lfsr_zq
2263
module `BASE`MODULE (
2264
`undef MODULE
2265
 zq, rst, clk);
2266
 
2267 6 unneback
   parameter length = 4;
2268
   output reg zq;
2269
   input rst;
2270
   input clk;
2271
 
2272
   parameter clear_value = 0;
2273
   parameter set_value = 1;
2274
   parameter wrap_value = 8;
2275
   parameter level1_value = 15;
2276
 
2277
   reg  [length:1] qi;
2278
   reg lfsr_fb;
2279
   wire [length:1] q_next;
2280
   reg [32:1] polynom;
2281
   integer i;
2282
 
2283
   always @ (qi)
2284
   begin
2285
        case (length)
2286
         2: polynom = 32'b11;                               // 0x3
2287
         3: polynom = 32'b110;                              // 0x6
2288
         4: polynom = 32'b1100;                             // 0xC
2289
         5: polynom = 32'b10100;                            // 0x14
2290
         6: polynom = 32'b110000;                           // 0x30
2291
         7: polynom = 32'b1100000;                          // 0x60
2292
         8: polynom = 32'b10111000;                         // 0xb8
2293
         9: polynom = 32'b100010000;                        // 0x110
2294
        10: polynom = 32'b1001000000;                       // 0x240
2295
        11: polynom = 32'b10100000000;                      // 0x500
2296
        12: polynom = 32'b100000101001;                     // 0x829
2297
        13: polynom = 32'b1000000001100;                    // 0x100C
2298
        14: polynom = 32'b10000000010101;                   // 0x2015
2299
        15: polynom = 32'b110000000000000;                  // 0x6000
2300
        16: polynom = 32'b1101000000001000;                 // 0xD008
2301
        17: polynom = 32'b10010000000000000;                // 0x12000
2302
        18: polynom = 32'b100000010000000000;               // 0x20400
2303
        19: polynom = 32'b1000000000000100011;              // 0x40023
2304 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2305 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2306
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2307
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2308
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2309
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2310
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2311
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2312
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2313
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2314
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2315
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2316
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2317
        default: polynom = 32'b0;
2318
        endcase
2319
        lfsr_fb = qi[length];
2320
        for (i=length-1; i>=1; i=i-1) begin
2321
            if (polynom[i])
2322
                lfsr_fb = lfsr_fb  ~^ qi[i];
2323
        end
2324
    end
2325
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2326
 
2327
   always @ (posedge clk or posedge rst)
2328
     if (rst)
2329
       qi <= {length{1'b0}};
2330
     else
2331
       qi <= q_next;
2332
 
2333
 
2334
 
2335
   always @ (posedge clk or posedge rst)
2336
     if (rst)
2337
       zq <= 1'b1;
2338
     else
2339
       zq <= q_next == {length{1'b0}};
2340
endmodule
2341 40 unneback
`endif
2342
`ifdef CNT_LFSR_CE_ZQ
2343 6 unneback
//////////////////////////////////////////////////////////////////////
2344
////                                                              ////
2345
////  Versatile counter                                           ////
2346
////                                                              ////
2347
////  Description                                                 ////
2348
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2349
////  counter                                                     ////
2350
////                                                              ////
2351
////  To Do:                                                      ////
2352
////   - add LFSR with more taps                                  ////
2353
////                                                              ////
2354
////  Author(s):                                                  ////
2355
////      - Michael Unneback, unneback@opencores.org              ////
2356
////        ORSoC AB                                              ////
2357
////                                                              ////
2358
//////////////////////////////////////////////////////////////////////
2359
////                                                              ////
2360
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2361
////                                                              ////
2362
//// This source file may be used and distributed without         ////
2363
//// restriction provided that this copyright statement is not    ////
2364
//// removed from the file and that any derivative work contains  ////
2365
//// the original copyright notice and the associated disclaimer. ////
2366
////                                                              ////
2367
//// This source file is free software; you can redistribute it   ////
2368
//// and/or modify it under the terms of the GNU Lesser General   ////
2369
//// Public License as published by the Free Software Foundation; ////
2370
//// either version 2.1 of the License, or (at your option) any   ////
2371
//// later version.                                               ////
2372
////                                                              ////
2373
//// This source is distributed in the hope that it will be       ////
2374
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2375
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2376
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2377
//// details.                                                     ////
2378
////                                                              ////
2379
//// You should have received a copy of the GNU Lesser General    ////
2380
//// Public License along with this source; if not, download it   ////
2381
//// from http://www.opencores.org/lgpl.shtml                     ////
2382
////                                                              ////
2383
//////////////////////////////////////////////////////////////////////
2384
 
2385
// LFSR counter
2386
 
2387 40 unneback
`define MODULE cnt_lfsr_ce_zq
2388
module `BASE`MODULE (
2389
`undef MODULE
2390
 cke, zq, rst, clk);
2391
 
2392 6 unneback
   parameter length = 4;
2393
   input cke;
2394
   output reg zq;
2395
   input rst;
2396
   input clk;
2397
 
2398
   parameter clear_value = 0;
2399
   parameter set_value = 1;
2400
   parameter wrap_value = 8;
2401
   parameter level1_value = 15;
2402
 
2403
   reg  [length:1] qi;
2404
   reg lfsr_fb;
2405
   wire [length:1] q_next;
2406
   reg [32:1] polynom;
2407
   integer i;
2408
 
2409
   always @ (qi)
2410
   begin
2411
        case (length)
2412
         2: polynom = 32'b11;                               // 0x3
2413
         3: polynom = 32'b110;                              // 0x6
2414
         4: polynom = 32'b1100;                             // 0xC
2415
         5: polynom = 32'b10100;                            // 0x14
2416
         6: polynom = 32'b110000;                           // 0x30
2417
         7: polynom = 32'b1100000;                          // 0x60
2418
         8: polynom = 32'b10111000;                         // 0xb8
2419
         9: polynom = 32'b100010000;                        // 0x110
2420
        10: polynom = 32'b1001000000;                       // 0x240
2421
        11: polynom = 32'b10100000000;                      // 0x500
2422
        12: polynom = 32'b100000101001;                     // 0x829
2423
        13: polynom = 32'b1000000001100;                    // 0x100C
2424
        14: polynom = 32'b10000000010101;                   // 0x2015
2425
        15: polynom = 32'b110000000000000;                  // 0x6000
2426
        16: polynom = 32'b1101000000001000;                 // 0xD008
2427
        17: polynom = 32'b10010000000000000;                // 0x12000
2428
        18: polynom = 32'b100000010000000000;               // 0x20400
2429
        19: polynom = 32'b1000000000000100011;              // 0x40023
2430 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2431 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2432
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2433
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2434
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2435
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2436
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2437
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2438
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2439
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2440
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2441
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2442
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2443
        default: polynom = 32'b0;
2444
        endcase
2445
        lfsr_fb = qi[length];
2446
        for (i=length-1; i>=1; i=i-1) begin
2447
            if (polynom[i])
2448
                lfsr_fb = lfsr_fb  ~^ qi[i];
2449
        end
2450
    end
2451
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2452
 
2453
   always @ (posedge clk or posedge rst)
2454
     if (rst)
2455
       qi <= {length{1'b0}};
2456
     else
2457
     if (cke)
2458
       qi <= q_next;
2459
 
2460
 
2461
 
2462
   always @ (posedge clk or posedge rst)
2463
     if (rst)
2464
       zq <= 1'b1;
2465
     else
2466
     if (cke)
2467
       zq <= q_next == {length{1'b0}};
2468
endmodule
2469 40 unneback
`endif
2470
`ifdef CNT_LFSR_CE_Q
2471 6 unneback
//////////////////////////////////////////////////////////////////////
2472
////                                                              ////
2473
////  Versatile counter                                           ////
2474
////                                                              ////
2475
////  Description                                                 ////
2476
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2477
////  counter                                                     ////
2478
////                                                              ////
2479
////  To Do:                                                      ////
2480
////   - add LFSR with more taps                                  ////
2481
////                                                              ////
2482
////  Author(s):                                                  ////
2483
////      - Michael Unneback, unneback@opencores.org              ////
2484
////        ORSoC AB                                              ////
2485
////                                                              ////
2486
//////////////////////////////////////////////////////////////////////
2487
////                                                              ////
2488
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2489
////                                                              ////
2490
//// This source file may be used and distributed without         ////
2491
//// restriction provided that this copyright statement is not    ////
2492
//// removed from the file and that any derivative work contains  ////
2493
//// the original copyright notice and the associated disclaimer. ////
2494
////                                                              ////
2495
//// This source file is free software; you can redistribute it   ////
2496
//// and/or modify it under the terms of the GNU Lesser General   ////
2497
//// Public License as published by the Free Software Foundation; ////
2498
//// either version 2.1 of the License, or (at your option) any   ////
2499
//// later version.                                               ////
2500
////                                                              ////
2501
//// This source is distributed in the hope that it will be       ////
2502
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2503
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2504
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2505
//// details.                                                     ////
2506
////                                                              ////
2507
//// You should have received a copy of the GNU Lesser General    ////
2508
//// Public License along with this source; if not, download it   ////
2509
//// from http://www.opencores.org/lgpl.shtml                     ////
2510
////                                                              ////
2511
//////////////////////////////////////////////////////////////////////
2512 22 unneback
 
2513
// LFSR counter
2514 27 unneback
 
2515 40 unneback
`define MODULE cnt_lfsr_ce_q
2516
module `BASE`MODULE (
2517
`undef MODULE
2518
 cke, q, rst, clk);
2519
 
2520 27 unneback
   parameter length = 4;
2521
   input cke;
2522
   output [length:1] q;
2523
   input rst;
2524
   input clk;
2525
 
2526
   parameter clear_value = 0;
2527
   parameter set_value = 1;
2528
   parameter wrap_value = 8;
2529
   parameter level1_value = 15;
2530
 
2531
   reg  [length:1] qi;
2532
   reg lfsr_fb;
2533
   wire [length:1] q_next;
2534
   reg [32:1] polynom;
2535
   integer i;
2536
 
2537
   always @ (qi)
2538
   begin
2539
        case (length)
2540
         2: polynom = 32'b11;                               // 0x3
2541
         3: polynom = 32'b110;                              // 0x6
2542
         4: polynom = 32'b1100;                             // 0xC
2543
         5: polynom = 32'b10100;                            // 0x14
2544
         6: polynom = 32'b110000;                           // 0x30
2545
         7: polynom = 32'b1100000;                          // 0x60
2546
         8: polynom = 32'b10111000;                         // 0xb8
2547
         9: polynom = 32'b100010000;                        // 0x110
2548
        10: polynom = 32'b1001000000;                       // 0x240
2549
        11: polynom = 32'b10100000000;                      // 0x500
2550
        12: polynom = 32'b100000101001;                     // 0x829
2551
        13: polynom = 32'b1000000001100;                    // 0x100C
2552
        14: polynom = 32'b10000000010101;                   // 0x2015
2553
        15: polynom = 32'b110000000000000;                  // 0x6000
2554
        16: polynom = 32'b1101000000001000;                 // 0xD008
2555
        17: polynom = 32'b10010000000000000;                // 0x12000
2556
        18: polynom = 32'b100000010000000000;               // 0x20400
2557
        19: polynom = 32'b1000000000000100011;              // 0x40023
2558 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2559 27 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2560
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2561
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2562
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2563
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2564
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2565
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2566
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2567
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2568
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2569
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2570
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2571
        default: polynom = 32'b0;
2572
        endcase
2573
        lfsr_fb = qi[length];
2574
        for (i=length-1; i>=1; i=i-1) begin
2575
            if (polynom[i])
2576
                lfsr_fb = lfsr_fb  ~^ qi[i];
2577
        end
2578
    end
2579
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2580
 
2581
   always @ (posedge clk or posedge rst)
2582
     if (rst)
2583
       qi <= {length{1'b0}};
2584
     else
2585
     if (cke)
2586
       qi <= q_next;
2587
 
2588
   assign q = qi;
2589
 
2590
endmodule
2591 40 unneback
`endif
2592
`ifdef CNT_LFSR_CE_CLEAR_Q
2593 27 unneback
//////////////////////////////////////////////////////////////////////
2594
////                                                              ////
2595
////  Versatile counter                                           ////
2596
////                                                              ////
2597
////  Description                                                 ////
2598
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2599
////  counter                                                     ////
2600
////                                                              ////
2601
////  To Do:                                                      ////
2602
////   - add LFSR with more taps                                  ////
2603
////                                                              ////
2604
////  Author(s):                                                  ////
2605
////      - Michael Unneback, unneback@opencores.org              ////
2606
////        ORSoC AB                                              ////
2607
////                                                              ////
2608
//////////////////////////////////////////////////////////////////////
2609
////                                                              ////
2610
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2611
////                                                              ////
2612
//// This source file may be used and distributed without         ////
2613
//// restriction provided that this copyright statement is not    ////
2614
//// removed from the file and that any derivative work contains  ////
2615
//// the original copyright notice and the associated disclaimer. ////
2616
////                                                              ////
2617
//// This source file is free software; you can redistribute it   ////
2618
//// and/or modify it under the terms of the GNU Lesser General   ////
2619
//// Public License as published by the Free Software Foundation; ////
2620
//// either version 2.1 of the License, or (at your option) any   ////
2621
//// later version.                                               ////
2622
////                                                              ////
2623
//// This source is distributed in the hope that it will be       ////
2624
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2625
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2626
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2627
//// details.                                                     ////
2628
////                                                              ////
2629
//// You should have received a copy of the GNU Lesser General    ////
2630
//// Public License along with this source; if not, download it   ////
2631
//// from http://www.opencores.org/lgpl.shtml                     ////
2632
////                                                              ////
2633
//////////////////////////////////////////////////////////////////////
2634
 
2635
// LFSR counter
2636
 
2637 40 unneback
`define MODULE cnt_lfsr_ce_clear_q
2638
module `BASE`MODULE (
2639
`undef MODULE
2640
 clear, cke, q, rst, clk);
2641
 
2642 27 unneback
   parameter length = 4;
2643
   input clear;
2644
   input cke;
2645
   output [length:1] q;
2646
   input rst;
2647
   input clk;
2648
 
2649
   parameter clear_value = 0;
2650
   parameter set_value = 1;
2651
   parameter wrap_value = 8;
2652
   parameter level1_value = 15;
2653
 
2654
   reg  [length:1] qi;
2655
   reg lfsr_fb;
2656
   wire [length:1] q_next;
2657
   reg [32:1] polynom;
2658
   integer i;
2659
 
2660
   always @ (qi)
2661
   begin
2662
        case (length)
2663
         2: polynom = 32'b11;                               // 0x3
2664
         3: polynom = 32'b110;                              // 0x6
2665
         4: polynom = 32'b1100;                             // 0xC
2666
         5: polynom = 32'b10100;                            // 0x14
2667
         6: polynom = 32'b110000;                           // 0x30
2668
         7: polynom = 32'b1100000;                          // 0x60
2669
         8: polynom = 32'b10111000;                         // 0xb8
2670
         9: polynom = 32'b100010000;                        // 0x110
2671
        10: polynom = 32'b1001000000;                       // 0x240
2672
        11: polynom = 32'b10100000000;                      // 0x500
2673
        12: polynom = 32'b100000101001;                     // 0x829
2674
        13: polynom = 32'b1000000001100;                    // 0x100C
2675
        14: polynom = 32'b10000000010101;                   // 0x2015
2676
        15: polynom = 32'b110000000000000;                  // 0x6000
2677
        16: polynom = 32'b1101000000001000;                 // 0xD008
2678
        17: polynom = 32'b10010000000000000;                // 0x12000
2679
        18: polynom = 32'b100000010000000000;               // 0x20400
2680
        19: polynom = 32'b1000000000000100011;              // 0x40023
2681 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2682 27 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2683
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2684
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2685
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2686
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2687
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2688
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2689
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2690
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2691
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2692
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2693
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2694
        default: polynom = 32'b0;
2695
        endcase
2696
        lfsr_fb = qi[length];
2697
        for (i=length-1; i>=1; i=i-1) begin
2698
            if (polynom[i])
2699
                lfsr_fb = lfsr_fb  ~^ qi[i];
2700
        end
2701
    end
2702
   assign q_next =  clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2703
 
2704
   always @ (posedge clk or posedge rst)
2705
     if (rst)
2706
       qi <= {length{1'b0}};
2707
     else
2708
     if (cke)
2709
       qi <= q_next;
2710
 
2711
   assign q = qi;
2712
 
2713
endmodule
2714 40 unneback
`endif
2715
`ifdef CNT_LFSR_CE_Q_ZQ
2716 27 unneback
//////////////////////////////////////////////////////////////////////
2717
////                                                              ////
2718
////  Versatile counter                                           ////
2719
////                                                              ////
2720
////  Description                                                 ////
2721
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2722
////  counter                                                     ////
2723
////                                                              ////
2724
////  To Do:                                                      ////
2725
////   - add LFSR with more taps                                  ////
2726
////                                                              ////
2727
////  Author(s):                                                  ////
2728
////      - Michael Unneback, unneback@opencores.org              ////
2729
////        ORSoC AB                                              ////
2730
////                                                              ////
2731
//////////////////////////////////////////////////////////////////////
2732
////                                                              ////
2733
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2734
////                                                              ////
2735
//// This source file may be used and distributed without         ////
2736
//// restriction provided that this copyright statement is not    ////
2737
//// removed from the file and that any derivative work contains  ////
2738
//// the original copyright notice and the associated disclaimer. ////
2739
////                                                              ////
2740
//// This source file is free software; you can redistribute it   ////
2741
//// and/or modify it under the terms of the GNU Lesser General   ////
2742
//// Public License as published by the Free Software Foundation; ////
2743
//// either version 2.1 of the License, or (at your option) any   ////
2744
//// later version.                                               ////
2745
////                                                              ////
2746
//// This source is distributed in the hope that it will be       ////
2747
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2748
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2749
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2750
//// details.                                                     ////
2751
////                                                              ////
2752
//// You should have received a copy of the GNU Lesser General    ////
2753
//// Public License along with this source; if not, download it   ////
2754
//// from http://www.opencores.org/lgpl.shtml                     ////
2755
////                                                              ////
2756
//////////////////////////////////////////////////////////////////////
2757
 
2758
// LFSR counter
2759 22 unneback
 
2760 40 unneback
`define MODULE cnt_lfsr_ce_q_zq
2761
module `BASE`MODULE (
2762
`undef MODULE
2763
 cke, q, zq, rst, clk);
2764
 
2765 22 unneback
   parameter length = 4;
2766
   input cke;
2767
   output [length:1] q;
2768
   output reg zq;
2769
   input rst;
2770
   input clk;
2771
 
2772
   parameter clear_value = 0;
2773
   parameter set_value = 1;
2774
   parameter wrap_value = 8;
2775
   parameter level1_value = 15;
2776
 
2777
   reg  [length:1] qi;
2778
   reg lfsr_fb;
2779
   wire [length:1] q_next;
2780
   reg [32:1] polynom;
2781
   integer i;
2782
 
2783
   always @ (qi)
2784
   begin
2785
        case (length)
2786
         2: polynom = 32'b11;                               // 0x3
2787
         3: polynom = 32'b110;                              // 0x6
2788
         4: polynom = 32'b1100;                             // 0xC
2789
         5: polynom = 32'b10100;                            // 0x14
2790
         6: polynom = 32'b110000;                           // 0x30
2791
         7: polynom = 32'b1100000;                          // 0x60
2792
         8: polynom = 32'b10111000;                         // 0xb8
2793
         9: polynom = 32'b100010000;                        // 0x110
2794
        10: polynom = 32'b1001000000;                       // 0x240
2795
        11: polynom = 32'b10100000000;                      // 0x500
2796
        12: polynom = 32'b100000101001;                     // 0x829
2797
        13: polynom = 32'b1000000001100;                    // 0x100C
2798
        14: polynom = 32'b10000000010101;                   // 0x2015
2799
        15: polynom = 32'b110000000000000;                  // 0x6000
2800
        16: polynom = 32'b1101000000001000;                 // 0xD008
2801
        17: polynom = 32'b10010000000000000;                // 0x12000
2802
        18: polynom = 32'b100000010000000000;               // 0x20400
2803
        19: polynom = 32'b1000000000000100011;              // 0x40023
2804 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2805 22 unneback
        21: polynom = 32'b101000000000000000000