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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Blame information for rev 48

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Line No. Rev Author Line
1 40 unneback
`ifndef BASE
2
`define BASE vl_
3
`endif
4
 
5 44 unneback
`ifdef ACTEL
6
`define SYN_KEEP /*synthesis syn_keep = 1*/
7
`endif
8
 
9 40 unneback
`ifdef ALL
10
 
11
`define GBUF
12
`define SYNC_RST
13
`define PLL
14
 
15
`define MULTS
16
`define MULTS18X18
17
`define MULT
18
`define SHIFT_UNIT_32
19
`define LOGIC_UNIT
20
 
21
`define CNT_SHREG_WRAP
22
`define CNT_SHREG_CE_WRAP
23
`define CNT_SHREG_CE_CLEAR
24
`define CNT_SHREG_CE_CLEAR_WRAP
25
 
26
`define MUX_ANDOR
27
`define MUX2_ANDOR
28
`define MUX3_ANDOR
29
`define MUX4_ANDOR
30
`define MUX5_ANDOR
31
`define MUX6_ANDOR
32 43 unneback
`define PARITY
33 40 unneback
 
34
`define ROM_INIT
35
`define RAM
36
`define RAM_BE
37
`define DPRAM_1R1W
38
`define DPRAM_2R1W
39
`define DPRAM_2R2W
40
`define FIFO_1R1W_FILL_LEVEL_SYNC
41
`define FIFO_2R2W_SYNC_SIMPLEX
42
`define FIFO_CMP_ASYNC
43
`define FIFO_1R1W_ASYNC
44
`define FIFO_2R2W_ASYNC
45
`define FIFO_2R2W_ASYNC_SIMPLEX
46 48 unneback
`define REG_FILE
47 40 unneback
 
48
`define DFF
49
`define DFF_ARRAY
50
`define DFF_CE
51
`define DFF_CE_CLEAR
52
`define DF_CE_SET
53
`define SPR
54
`define SRP
55
`define DFF_SR
56
`define LATCH
57
`define SHREG
58
`define SHREG_CE
59
`define DELAY
60
`define DELAY_EMPTYFLAG
61
 
62
`define WB3WB3_BRIDGE
63
`define WB3_ARBITER_TYPE1
64 48 unneback
`define WB_B4_ROM
65 40 unneback
`define WB_BOOT_ROM
66
`define WB_DPRAM
67
 
68 44 unneback
`define IO_DFF_OE
69
`define O_DFF
70
 
71 40 unneback
`endif
72
 
73
`ifdef PLL
74
`ifndef SYNC_RST
75
`define SYNC_RST
76
`endif
77
`endif
78
 
79
`ifdef SYNC_RST
80
`ifndef GBUF
81
`define GBUF
82
`endif
83
`endif
84
 
85
`ifdef WB_DPRAM
86
`ifndef DPRAM_2R2W
87
`define DPRAM_2R2W
88
`endif
89
`ifndef SPR
90
`define SPR
91
`endif
92
`endif
93
 
94
`ifdef WB3_ARBITER_TYPE1
95 42 unneback
`ifndef SPR
96
`define SPR
97
`endif
98 40 unneback
`ifndef MUX_ANDOR
99
`define MUX_ANDOR
100
`endif
101
`endif
102
 
103
`ifdef WB3WB3_BRIDGE
104
`ifndef CNT_SHREG_CE_CLEAR
105
`define CNT_SHREG_CE_CLEAR
106
`endif
107
`ifndef DFF
108
`define DFF
109
`endif
110
`ifndef DFF_CE
111
`define DFF_CE
112
`endif
113
`ifndef CNT_SHREG_CE_CLEAR
114
`define CNT_SHREG_CE_CLEAR
115
`endif
116
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
117
`define FIFO_2R2W_ASYNC_SIMPLEX
118
`endif
119
`endif
120
 
121
`ifdef MULTS18X18
122
`ifndef MULTS
123
`define MULTS
124
`endif
125
`endif
126
 
127
`ifdef SHIFT_UNIT_32
128
`ifndef MULTS
129
`define MULTS
130
`endif
131
`endif
132
 
133
`ifdef MUX2_ANDOR
134
`ifndef MUX_ANDOR
135
`define MUX_ANDOR
136
`endif
137
`endif
138
 
139
`ifdef MUX3_ANDOR
140
`ifndef MUX_ANDOR
141
`define MUX_ANDOR
142
`endif
143
`endif
144
 
145
`ifdef MUX4_ANDOR
146
`ifndef MUX_ANDOR
147
`define MUX_ANDOR
148
`endif
149
`endif
150
 
151
`ifdef MUX5_ANDOR
152
`ifndef MUX_ANDOR
153
`define MUX_ANDOR
154
`endif
155
`endif
156
 
157
`ifdef MUX6_ANDOR
158
`ifndef MUX_ANDOR
159
`define MUX_ANDOR
160
`endif
161
`endif
162
 
163
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
164
`ifndef CNT_BIN_CE
165
`define CNT_BIN_CE
166
`endif
167
`ifndef DPRAM_1R1W
168
`define DPRAM_1R1W
169
`endif
170
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
171
`define CNT_BIN_CE_REW_Q_ZQ_L1
172
`endif
173
`endif
174
 
175
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
176
`ifndef CNT_LFSR_CE
177
`define CNT_LFSR_CE
178
`endif
179
`ifndef DPRAM_2R2W
180
`define DPRAM_2R2W
181
`endif
182
`ifndef CNT_BIN_CE_REW_ZQ_L1
183
`define CNT_BIN_CE_REW_ZQ_L1
184
`endif
185
`endif
186
 
187
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
188
`ifndef CNT_GRAY_CE_BIN
189
`define CNT_GRAY_CE_BIN
190
`endif
191
`ifndef DPRAM_2R2W
192
`define DPRAM_2R2W
193
`endif
194
`ifndef FIFO_CMP_ASYNC
195
`define FIFO_CMP_ASYNC
196
`endif
197
`endif
198
 
199
`ifdef FIFO_2R2W_ASYNC
200
`ifndef FIFO_1R1W_ASYNC
201
`define FIFO_1R1W_ASYNC
202
`endif
203
`endif
204
 
205
`ifdef FIFO_1R1W_ASYNC
206
`ifndef CNT_GRAY_CE_BIN
207
`define CNT_GRAY_CE_BIN
208
`endif
209
`ifndef DPRAM_1R1W
210
`define DPRAM_1R1W
211
`endif
212
`ifndef FIFO_CMP_ASYNC
213
`define FIFO_CMP_ASYNC
214
`endif
215
`endif
216
 
217
`ifdef FIFO_CMP_ASYNC
218
`ifndef DFF_SR
219
`define DFF_SR
220
`endif
221
`ifndef DFF
222
`define DFF
223
`endif
224
`endif
225 48 unneback
 
226
`ifdef REG_FILE
227
`ifndef DPRAM_1R1W
228
`define DPRAM_1R1W
229
`endif
230
`endif
231 6 unneback
//////////////////////////////////////////////////////////////////////
232
////                                                              ////
233
////  Versatile library, clock and reset                          ////
234
////                                                              ////
235
////  Description                                                 ////
236
////  Logic related to clock and reset                            ////
237
////                                                              ////
238
////                                                              ////
239
////  To Do:                                                      ////
240
////   - add more different registers                             ////
241
////                                                              ////
242
////  Author(s):                                                  ////
243
////      - Michael Unneback, unneback@opencores.org              ////
244
////        ORSoC AB                                              ////
245
////                                                              ////
246
//////////////////////////////////////////////////////////////////////
247
////                                                              ////
248
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
249
////                                                              ////
250
//// This source file may be used and distributed without         ////
251
//// restriction provided that this copyright statement is not    ////
252
//// removed from the file and that any derivative work contains  ////
253
//// the original copyright notice and the associated disclaimer. ////
254
////                                                              ////
255
//// This source file is free software; you can redistribute it   ////
256
//// and/or modify it under the terms of the GNU Lesser General   ////
257
//// Public License as published by the Free Software Foundation; ////
258
//// either version 2.1 of the License, or (at your option) any   ////
259
//// later version.                                               ////
260
////                                                              ////
261
//// This source is distributed in the hope that it will be       ////
262
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
263
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
264
//// PURPOSE.  See the GNU Lesser General Public License for more ////
265
//// details.                                                     ////
266
////                                                              ////
267
//// You should have received a copy of the GNU Lesser General    ////
268
//// Public License along with this source; if not, download it   ////
269
//// from http://www.opencores.org/lgpl.shtml                     ////
270
////                                                              ////
271
//////////////////////////////////////////////////////////////////////
272
 
273 48 unneback
`ifdef ACTEL
274
`ifdef GBUF
275
`timescale 1 ns/100 ps
276 6 unneback
// Global buffer
277
// usage:
278
// use to enable global buffers for high fan out signals such as clock and reset
279
// Version: 8.4 8.4.0.33
280
module gbuf(GL,CLK);
281
output GL;
282
input  CLK;
283
 
284
    wire GND;
285
 
286
    GND GND_1_net(.Y(GND));
287
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
288
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
289
 
290
endmodule
291
`timescale 1 ns/1 ns
292 40 unneback
`define MODULE gbuf
293
module `BASE`MODULE ( i, o);
294
`undef MODULE
295 6 unneback
input i;
296
output o;
297
`ifdef SIM_GBUF
298
assign o=i;
299
`else
300
gbuf gbuf_i0 ( .CLK(i), .GL(o));
301
`endif
302
endmodule
303 40 unneback
`endif
304 33 unneback
 
305 6 unneback
`else
306 33 unneback
 
307 40 unneback
`ifdef ALTERA
308
`ifdef GBUF
309 21 unneback
//altera
310 40 unneback
`define MODULE gbuf
311
module `BASE`MODULE ( i, o);
312
`undef MODULE
313 33 unneback
input i;
314
output o;
315
assign o = i;
316
endmodule
317 40 unneback
`endif
318 33 unneback
 
319 6 unneback
`else
320
 
321 40 unneback
`ifdef GBUF
322 6 unneback
`timescale 1 ns/100 ps
323 40 unneback
`define MODULE
324
module `BASE`MODULE ( i, o);
325
`undef MODULE
326 6 unneback
input i;
327
output o;
328
assign o = i;
329
endmodule
330 40 unneback
`endif
331 6 unneback
`endif // ALTERA
332
`endif //ACTEL
333
 
334 40 unneback
`ifdef SYNC_RST
335 6 unneback
// sync reset
336 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
337 6 unneback
// output active high global reset sync with two DFFs 
338
`timescale 1 ns/100 ps
339 40 unneback
`define MODULE sync_rst
340
module `BASE`MODULE ( rst_n_i, rst_o, clk);
341
`undef MODULE
342 6 unneback
input rst_n_i, clk;
343
output rst_o;
344 18 unneback
reg [1:0] tmp;
345 6 unneback
always @ (posedge clk or negedge rst_n_i)
346
if (!rst_n_i)
347 17 unneback
        tmp <= 2'b11;
348 6 unneback
else
349 33 unneback
        tmp <= {1'b0,tmp[1]};
350 40 unneback
`define MODULE gbuf
351
`BASE`MODULE buf_i0( .i(tmp[0]), .o(rst_o));
352
`undef MODULE
353 6 unneback
endmodule
354 40 unneback
`endif
355 6 unneback
 
356 40 unneback
`ifdef PLL
357 6 unneback
// vl_pll
358
`ifdef ACTEL
359 32 unneback
///////////////////////////////////////////////////////////////////////////////
360 17 unneback
`timescale 1 ps/1 ps
361 40 unneback
`define MODULE pll
362
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
363
`undef MODULE
364 6 unneback
parameter index = 0;
365
parameter number_of_clk = 1;
366 17 unneback
parameter period_time_0 = 20000;
367
parameter period_time_1 = 20000;
368
parameter period_time_2 = 20000;
369
parameter lock_delay = 2000000;
370 6 unneback
input clk_i, rst_n_i;
371
output lock;
372
output reg [0:number_of_clk-1] clk_o;
373
output [0:number_of_clk-1] rst_o;
374
 
375
`ifdef SIM_PLL
376
 
377
always
378
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
379
 
380
generate if (number_of_clk > 1)
381
always
382
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
383
endgenerate
384
 
385
generate if (number_of_clk > 2)
386
always
387
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
388
endgenerate
389
 
390
genvar i;
391
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
392
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
393
end
394
endgenerate
395
 
396
assign #lock_delay lock = rst_n_i;
397
 
398
endmodule
399
`else
400
generate if (number_of_clk==1 & index==0) begin
401
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
402
end
403
endgenerate // index==0
404
generate if (number_of_clk==1 & index==1) begin
405
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
406
end
407
endgenerate // index==1
408
generate if (number_of_clk==1 & index==2) begin
409
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
410
end
411
endgenerate // index==2
412
generate if (number_of_clk==1 & index==3) begin
413
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
414
end
415
endgenerate // index==0
416
 
417
generate if (number_of_clk==2 & index==0) begin
418
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
419
end
420
endgenerate // index==0
421
generate if (number_of_clk==2 & index==1) begin
422
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
423
end
424
endgenerate // index==1
425
generate if (number_of_clk==2 & index==2) begin
426
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
427
end
428
endgenerate // index==2
429
generate if (number_of_clk==2 & index==3) begin
430
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
431
end
432
endgenerate // index==0
433
 
434
generate if (number_of_clk==3 & index==0) begin
435
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
436
end
437
endgenerate // index==0
438
generate if (number_of_clk==3 & index==1) begin
439
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
440
end
441
endgenerate // index==1
442
generate if (number_of_clk==3 & index==2) begin
443
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
444
end
445
endgenerate // index==2
446
generate if (number_of_clk==3 & index==3) begin
447
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
448
end
449
endgenerate // index==0
450
 
451
genvar i;
452
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
453 40 unneback
`define MODULE sync_rst
454
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
455
`undef MODULE
456 6 unneback
end
457
endgenerate
458
endmodule
459
`endif
460 32 unneback
///////////////////////////////////////////////////////////////////////////////
461 6 unneback
 
462
`else
463
 
464 32 unneback
///////////////////////////////////////////////////////////////////////////////
465 6 unneback
`ifdef ALTERA
466
 
467 32 unneback
`timescale 1 ps/1 ps
468 40 unneback
`define MODULE pll
469
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
470
`undef MODULE
471 32 unneback
parameter index = 0;
472
parameter number_of_clk = 1;
473
parameter period_time_0 = 20000;
474
parameter period_time_1 = 20000;
475
parameter period_time_2 = 20000;
476
parameter period_time_3 = 20000;
477
parameter period_time_4 = 20000;
478
parameter lock_delay = 2000000;
479
input clk_i, rst_n_i;
480
output lock;
481
output reg [0:number_of_clk-1] clk_o;
482
output [0:number_of_clk-1] rst_o;
483
 
484
`ifdef SIM_PLL
485
 
486
always
487
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
488
 
489
generate if (number_of_clk > 1)
490
always
491
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
492
endgenerate
493
 
494
generate if (number_of_clk > 2)
495
always
496
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
497
endgenerate
498
 
499 33 unneback
generate if (number_of_clk > 3)
500 32 unneback
always
501
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
502
endgenerate
503
 
504 33 unneback
generate if (number_of_clk > 4)
505 32 unneback
always
506
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
507
endgenerate
508
 
509
genvar i;
510
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
511
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
512
end
513
endgenerate
514
 
515 33 unneback
//assign #lock_delay lock = rst_n_i;
516
assign lock = rst_n_i;
517 32 unneback
 
518
endmodule
519 6 unneback
`else
520
 
521 33 unneback
`ifdef VL_PLL0
522
`ifdef VL_PLL0_CLK1
523
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
524
`endif
525
`ifdef VL_PLL0_CLK2
526
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
527
`endif
528
`ifdef VL_PLL0_CLK3
529
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
530
`endif
531
`ifdef VL_PLL0_CLK4
532
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
533
`endif
534
`ifdef VL_PLL0_CLK5
535
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
536
`endif
537
`endif
538 32 unneback
 
539 33 unneback
`ifdef VL_PLL1
540
`ifdef VL_PLL1_CLK1
541
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
542
`endif
543
`ifdef VL_PLL1_CLK2
544
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
545
`endif
546
`ifdef VL_PLL1_CLK3
547
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
548
`endif
549
`ifdef VL_PLL1_CLK4
550
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
551
`endif
552
`ifdef VL_PLL1_CLK5
553
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
554
`endif
555
`endif
556 32 unneback
 
557 33 unneback
`ifdef VL_PLL2
558
`ifdef VL_PLL2_CLK1
559
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
560
`endif
561
`ifdef VL_PLL2_CLK2
562
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
563
`endif
564
`ifdef VL_PLL2_CLK3
565
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
566
`endif
567
`ifdef VL_PLL2_CLK4
568
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
569
`endif
570
`ifdef VL_PLL2_CLK5
571
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
572
`endif
573
`endif
574 32 unneback
 
575 33 unneback
`ifdef VL_PLL3
576
`ifdef VL_PLL3_CLK1
577
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
578
`endif
579
`ifdef VL_PLL3_CLK2
580
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
581
`endif
582
`ifdef VL_PLL3_CLK3
583
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
584
`endif
585
`ifdef VL_PLL3_CLK4
586
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
587
`endif
588
`ifdef VL_PLL3_CLK5
589
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
590
`endif
591
`endif
592 32 unneback
 
593
genvar i;
594
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
595 40 unneback
`define MODULE sync_rst
596
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
597
`undef MODULE
598 32 unneback
end
599
endgenerate
600
endmodule
601
`endif
602
///////////////////////////////////////////////////////////////////////////////
603
 
604
`else
605
 
606 6 unneback
// generic PLL
607 17 unneback
`timescale 1 ps/1 ps
608 40 unneback
`define MODULE pll
609
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
610
`undef MODULE
611 6 unneback
parameter index = 0;
612
parameter number_of_clk = 1;
613 17 unneback
parameter period_time_0 = 20000;
614
parameter period_time_1 = 20000;
615
parameter period_time_2 = 20000;
616 6 unneback
parameter lock_delay = 2000;
617
input clk_i, rst_n_i;
618
output lock;
619
output reg [0:number_of_clk-1] clk_o;
620
output [0:number_of_clk-1] rst_o;
621
 
622
always
623
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
624
 
625
generate if (number_of_clk > 1)
626
always
627
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
628
endgenerate
629
 
630
generate if (number_of_clk > 2)
631
always
632
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
633
endgenerate
634
 
635
genvar i;
636
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
637 40 unneback
`define MODULE sync_rst
638
     `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
639
`undef MODULE
640 6 unneback
end
641
endgenerate
642
 
643
assign #lock_delay lock = rst_n_i;
644
 
645
endmodule
646
 
647
`endif //altera
648 17 unneback
`endif //actel
649 40 unneback
`undef MODULE
650
`endif//////////////////////////////////////////////////////////////////////
651 6 unneback
////                                                              ////
652
////  Versatile library, registers                                ////
653
////                                                              ////
654
////  Description                                                 ////
655
////  Different type of registers                                 ////
656
////                                                              ////
657
////                                                              ////
658
////  To Do:                                                      ////
659
////   - add more different registers                             ////
660
////                                                              ////
661
////  Author(s):                                                  ////
662
////      - Michael Unneback, unneback@opencores.org              ////
663
////        ORSoC AB                                              ////
664
////                                                              ////
665
//////////////////////////////////////////////////////////////////////
666
////                                                              ////
667
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
668
////                                                              ////
669
//// This source file may be used and distributed without         ////
670
//// restriction provided that this copyright statement is not    ////
671
//// removed from the file and that any derivative work contains  ////
672
//// the original copyright notice and the associated disclaimer. ////
673
////                                                              ////
674
//// This source file is free software; you can redistribute it   ////
675
//// and/or modify it under the terms of the GNU Lesser General   ////
676
//// Public License as published by the Free Software Foundation; ////
677
//// either version 2.1 of the License, or (at your option) any   ////
678
//// later version.                                               ////
679
////                                                              ////
680
//// This source is distributed in the hope that it will be       ////
681
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
682
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
683
//// PURPOSE.  See the GNU Lesser General Public License for more ////
684
//// details.                                                     ////
685
////                                                              ////
686
//// You should have received a copy of the GNU Lesser General    ////
687
//// Public License along with this source; if not, download it   ////
688
//// from http://www.opencores.org/lgpl.shtml                     ////
689
////                                                              ////
690
//////////////////////////////////////////////////////////////////////
691
 
692 40 unneback
`ifdef DFF
693
`define MODULE dff
694
module `BASE`MODULE ( d, q, clk, rst);
695
`undef MODULE
696 6 unneback
        parameter width = 1;
697
        parameter reset_value = 0;
698
 
699
        input [width-1:0] d;
700
        input clk, rst;
701
        output reg [width-1:0] q;
702
 
703
        always @ (posedge clk or posedge rst)
704
        if (rst)
705
                q <= reset_value;
706
        else
707
                q <= d;
708
 
709
endmodule
710 40 unneback
`endif
711 6 unneback
 
712 40 unneback
`ifdef DFF_ARRAY
713
`define MODULE dff_array
714
module `BASE`MODULE ( d, q, clk, rst);
715
`undef MODULE
716 6 unneback
 
717
        parameter width = 1;
718
        parameter depth = 2;
719
        parameter reset_value = 1'b0;
720
 
721
        input [width-1:0] d;
722
        input clk, rst;
723
        output [width-1:0] q;
724
        reg  [0:depth-1] q_tmp [width-1:0];
725
        integer i;
726
        always @ (posedge clk or posedge rst)
727
        if (rst) begin
728
            for (i=0;i<depth;i=i+1)
729
                q_tmp[i] <= {width{reset_value}};
730
        end else begin
731
            q_tmp[0] <= d;
732
            for (i=1;i<depth;i=i+1)
733
                q_tmp[i] <= q_tmp[i-1];
734
        end
735
 
736
    assign q = q_tmp[depth-1];
737
 
738
endmodule
739 40 unneback
`endif
740 6 unneback
 
741 40 unneback
`ifdef DFF_CE
742
`define MODULE dff_ce
743
module `BASE`MODULE ( d, ce, q, clk, rst);
744
`undef MODULE
745 6 unneback
 
746
        parameter width = 1;
747
        parameter reset_value = 0;
748
 
749
        input [width-1:0] d;
750
        input ce, clk, rst;
751
        output reg [width-1:0] q;
752
 
753
        always @ (posedge clk or posedge rst)
754
        if (rst)
755
                q <= reset_value;
756
        else
757
                if (ce)
758
                        q <= d;
759
 
760
endmodule
761 40 unneback
`endif
762 6 unneback
 
763 40 unneback
`ifdef DFF_CE_CLEAR
764
`define MODULE dff_ce_clear
765
module `BASE`MODULE ( d, ce, clear, q, clk, rst);
766
`undef MODULE
767 8 unneback
 
768
        parameter width = 1;
769
        parameter reset_value = 0;
770
 
771
        input [width-1:0] d;
772 10 unneback
        input ce, clear, clk, rst;
773 8 unneback
        output reg [width-1:0] q;
774
 
775
        always @ (posedge clk or posedge rst)
776
        if (rst)
777
            q <= reset_value;
778
        else
779
            if (ce)
780
                if (clear)
781
                    q <= {width{1'b0}};
782
                else
783
                    q <= d;
784
 
785
endmodule
786 40 unneback
`endif
787 8 unneback
 
788 40 unneback
`ifdef DF_CE_SET
789
`define MODULE dff_ce_set
790
module `BASE`MODULE ( d, ce, set, q, clk, rst);
791
`undef MODULE
792 24 unneback
 
793
        parameter width = 1;
794
        parameter reset_value = 0;
795
 
796
        input [width-1:0] d;
797
        input ce, set, clk, rst;
798
        output reg [width-1:0] q;
799
 
800
        always @ (posedge clk or posedge rst)
801
        if (rst)
802
            q <= reset_value;
803
        else
804
            if (ce)
805
                if (set)
806
                    q <= {width{1'b1}};
807
                else
808
                    q <= d;
809
 
810
endmodule
811 40 unneback
`endif
812 24 unneback
 
813 40 unneback
`ifdef SPR
814
`define MODULE spr
815
module `BASE`MODULE ( sp, r, q, clk, rst);
816
`undef MODULE
817
 
818 29 unneback
        parameter width = 1;
819
        parameter reset_value = 0;
820
 
821
        input sp, r;
822
        output reg q;
823
        input clk, rst;
824
 
825
        always @ (posedge clk or posedge rst)
826
        if (rst)
827
            q <= reset_value;
828
        else
829
            if (sp)
830
                q <= 1'b1;
831
            else if (r)
832
                q <= 1'b0;
833
 
834
endmodule
835 40 unneback
`endif
836 29 unneback
 
837 40 unneback
`ifdef SRP
838
`define MODULE srp
839
module `BASE`MODULE ( s, rp, q, clk, rst);
840
`undef MODULE
841
 
842 29 unneback
        parameter width = 1;
843
        parameter reset_value = 0;
844
 
845
        input s, rp;
846
        output reg q;
847
        input clk, rst;
848
 
849
        always @ (posedge clk or posedge rst)
850
        if (rst)
851
            q <= reset_value;
852
        else
853
            if (rp)
854
                q <= 1'b0;
855
            else if (s)
856
                q <= 1'b1;
857
 
858
endmodule
859 40 unneback
`endif
860 29 unneback
 
861 40 unneback
`ifdef ALTERA
862 29 unneback
 
863 40 unneback
`ifdef DFF_SR
864 6 unneback
// megafunction wizard: %LPM_FF%
865
// GENERATION: STANDARD
866
// VERSION: WM1.0
867
// MODULE: lpm_ff 
868
 
869
// ============================================================
870
// File Name: dff_sr.v
871
// Megafunction Name(s):
872
//                      lpm_ff
873
//
874
// Simulation Library Files(s):
875
//                      lpm
876
// ============================================================
877
// ************************************************************
878
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
879
//
880
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
881
// ************************************************************
882
 
883
 
884
//Copyright (C) 1991-2010 Altera Corporation
885
//Your use of Altera Corporation's design tools, logic functions 
886
//and other software and tools, and its AMPP partner logic 
887
//functions, and any output files from any of the foregoing 
888
//(including device programming or simulation files), and any 
889
//associated documentation or information are expressly subject 
890
//to the terms and conditions of the Altera Program License 
891
//Subscription Agreement, Altera MegaCore Function License 
892
//Agreement, or other applicable license agreement, including, 
893
//without limitation, that your use is for the sole purpose of 
894
//programming logic devices manufactured by Altera and sold by 
895
//Altera or its authorized distributors.  Please refer to the 
896
//applicable agreement for further details.
897
 
898
 
899
// synopsys translate_off
900
`timescale 1 ps / 1 ps
901
// synopsys translate_on
902 40 unneback
`define MODULE dff_sr
903
module `BASE`MODULE (
904
`undef MODULE
905
 
906 6 unneback
        aclr,
907
        aset,
908
        clock,
909
        data,
910
        q);
911
 
912
        input     aclr;
913
        input     aset;
914
        input     clock;
915
        input     data;
916
        output    q;
917
 
918
        wire [0:0] sub_wire0;
919
        wire [0:0] sub_wire1 = sub_wire0[0:0];
920
        wire  q = sub_wire1;
921
        wire  sub_wire2 = data;
922
        wire  sub_wire3 = sub_wire2;
923
 
924
        lpm_ff  lpm_ff_component (
925
                                .aclr (aclr),
926
                                .clock (clock),
927
                                .data (sub_wire3),
928
                                .aset (aset),
929
                                .q (sub_wire0)
930
                                // synopsys translate_off
931
                                ,
932
                                .aload (),
933
                                .enable (),
934
                                .sclr (),
935
                                .sload (),
936
                                .sset ()
937
                                // synopsys translate_on
938
                                );
939
        defparam
940
                lpm_ff_component.lpm_fftype = "DFF",
941
                lpm_ff_component.lpm_type = "LPM_FF",
942
                lpm_ff_component.lpm_width = 1;
943
 
944
 
945
endmodule
946
 
947
// ============================================================
948
// CNX file retrieval info
949
// ============================================================
950
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
951
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
952
// Retrieval info: PRIVATE: ASET NUMERIC "1"
953
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
954
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
955
// Retrieval info: PRIVATE: DFF NUMERIC "1"
956
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
957
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
958
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
959
// Retrieval info: PRIVATE: SSET NUMERIC "0"
960
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
961
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
962
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
963
// Retrieval info: PRIVATE: nBit NUMERIC "1"
964
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
965
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
966
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
967
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
968
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
969
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
970
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
971
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
972
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
973
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
974
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
975
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
976
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
977
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
978
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
979
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
980
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
981
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
982
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
983
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
984
// Retrieval info: LIB_FILE: lpm
985 40 unneback
`endif
986 6 unneback
 
987
`else
988
 
989 40 unneback
`ifdef DFF_SR
990
`define MODULE dff_sr
991
module `BASE`MODULE ( aclr, aset, clock, data, q);
992
`undef MODULE
993 6 unneback
 
994
    input         aclr;
995
    input         aset;
996
    input         clock;
997
    input         data;
998
    output reg    q;
999
 
1000
   always @ (posedge clock or posedge aclr or posedge aset)
1001
     if (aclr)
1002
       q <= 1'b0;
1003
     else if (aset)
1004
       q <= 1'b1;
1005
     else
1006
       q <= data;
1007
 
1008
endmodule
1009 40 unneback
`endif
1010 6 unneback
 
1011
`endif
1012
 
1013
// LATCH
1014
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
1015
`ifdef ALTERA
1016 40 unneback
 
1017
`ifdef LATCH
1018
`define MODULE latch
1019
module `BASE`MODULE ( d, le, q, clk);
1020
`undef MODULE
1021 6 unneback
input d, le;
1022
output q;
1023
input clk;
1024
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
1025
endmodule
1026 40 unneback
`endif
1027
 
1028 6 unneback
`else
1029 40 unneback
 
1030
`ifdef LATCH
1031
`define MODULE latch
1032
module `BASE`MODULE ( d, le, q, clk);
1033
`undef MODULE
1034 6 unneback
input d, le;
1035 48 unneback
input clk;
1036
always @ (le or d)
1037
if le
1038
    d <= q;
1039 6 unneback
endmodule
1040 15 unneback
`endif
1041
 
1042 40 unneback
`endif
1043
 
1044
`ifdef SHREG
1045
`define MODULE shreg
1046
module `BASE`MODULE ( d, q, clk, rst);
1047
`undef MODULE
1048
 
1049 17 unneback
parameter depth = 10;
1050
input d;
1051
output q;
1052
input clk, rst;
1053
 
1054
reg [1:depth] dffs;
1055
 
1056
always @ (posedge clk or posedge rst)
1057
if (rst)
1058
    dffs <= {depth{1'b0}};
1059
else
1060
    dffs <= {d,dffs[1:depth-1]};
1061
assign q = dffs[depth];
1062
endmodule
1063 40 unneback
`endif
1064 17 unneback
 
1065 40 unneback
`ifdef SHREG_CE
1066
`define MODULE shreg_ce
1067
module `BASE`MODULE ( d, ce, q, clk, rst);
1068
`undef MODULE
1069 17 unneback
parameter depth = 10;
1070
input d, ce;
1071
output q;
1072
input clk, rst;
1073
 
1074
reg [1:depth] dffs;
1075
 
1076
always @ (posedge clk or posedge rst)
1077
if (rst)
1078
    dffs <= {depth{1'b0}};
1079
else
1080
    if (ce)
1081
        dffs <= {d,dffs[1:depth-1]};
1082
assign q = dffs[depth];
1083
endmodule
1084 40 unneback
`endif
1085 17 unneback
 
1086 40 unneback
`ifdef DELAY
1087
`define MODULE delay
1088
module `BASE`MODULE ( d, q, clk, rst);
1089
`undef MODULE
1090 15 unneback
parameter depth = 10;
1091
input d;
1092
output q;
1093
input clk, rst;
1094
 
1095
reg [1:depth] dffs;
1096
 
1097
always @ (posedge clk or posedge rst)
1098
if (rst)
1099
    dffs <= {depth{1'b0}};
1100
else
1101
    dffs <= {d,dffs[1:depth-1]};
1102
assign q = dffs[depth];
1103 17 unneback
endmodule
1104 40 unneback
`endif
1105 17 unneback
 
1106 40 unneback
`ifdef DELAY_EMPTYFLAG
1107
`define MODULE delay_emptyflag
1108 41 unneback
module `BASE`MODULE ( d, q, emptyflag, clk, rst);
1109 40 unneback
`undef MODULE
1110 17 unneback
parameter depth = 10;
1111
input d;
1112
output q, emptyflag;
1113
input clk, rst;
1114
 
1115
reg [1:depth] dffs;
1116
 
1117
always @ (posedge clk or posedge rst)
1118
if (rst)
1119
    dffs <= {depth{1'b0}};
1120
else
1121
    dffs <= {d,dffs[1:depth-1]};
1122
assign q = dffs[depth];
1123
assign emptyflag = !(|dffs);
1124
endmodule
1125 40 unneback
`endif
1126 17 unneback
//////////////////////////////////////////////////////////////////////
1127 6 unneback
////                                                              ////
1128 18 unneback
////  Logic functions                                             ////
1129
////                                                              ////
1130
////  Description                                                 ////
1131
////  Logic functions such as multiplexers                        ////
1132
////                                                              ////
1133
////                                                              ////
1134
////  To Do:                                                      ////
1135
////   -                                                          ////
1136
////                                                              ////
1137
////  Author(s):                                                  ////
1138
////      - Michael Unneback, unneback@opencores.org              ////
1139
////        ORSoC AB                                              ////
1140
////                                                              ////
1141
//////////////////////////////////////////////////////////////////////
1142
////                                                              ////
1143
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1144
////                                                              ////
1145
//// This source file may be used and distributed without         ////
1146
//// restriction provided that this copyright statement is not    ////
1147
//// removed from the file and that any derivative work contains  ////
1148
//// the original copyright notice and the associated disclaimer. ////
1149
////                                                              ////
1150
//// This source file is free software; you can redistribute it   ////
1151
//// and/or modify it under the terms of the GNU Lesser General   ////
1152
//// Public License as published by the Free Software Foundation; ////
1153
//// either version 2.1 of the License, or (at your option) any   ////
1154
//// later version.                                               ////
1155
////                                                              ////
1156
//// This source is distributed in the hope that it will be       ////
1157
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1158
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1159
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1160
//// details.                                                     ////
1161
////                                                              ////
1162
//// You should have received a copy of the GNU Lesser General    ////
1163
//// Public License along with this source; if not, download it   ////
1164
//// from http://www.opencores.org/lgpl.shtml                     ////
1165
////                                                              ////
1166
//////////////////////////////////////////////////////////////////////
1167 40 unneback
`ifdef MUX_ANDOR
1168
`define MODULE mux_andor
1169
module `BASE`MODULE ( a, sel, dout);
1170
`undef MODULE
1171 36 unneback
 
1172
parameter width = 32;
1173
parameter nr_of_ports = 4;
1174
 
1175
input [nr_of_ports*width-1:0] a;
1176
input [nr_of_ports-1:0] sel;
1177
output reg [width-1:0] dout;
1178
 
1179 38 unneback
integer i,j;
1180
 
1181 36 unneback
always @ (a, sel)
1182
begin
1183
    dout = a[width-1:0] & {width{sel[0]}};
1184 42 unneback
    for (i=1;i<nr_of_ports;i=i+1)
1185
        for (j=0;j<width;j=j+1)
1186
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
1187 36 unneback
end
1188
 
1189
endmodule
1190 40 unneback
`endif
1191 36 unneback
 
1192 40 unneback
`ifdef MUX2_ANDOR
1193
`define MODULE mux2_andor
1194
module `BASE`MODULE ( a1, a0, sel, dout);
1195
`undef MODULE
1196 18 unneback
 
1197 34 unneback
parameter width = 32;
1198 35 unneback
localparam nr_of_ports = 2;
1199 34 unneback
input [width-1:0] a1, a0;
1200
input [nr_of_ports-1:0] sel;
1201
output [width-1:0] dout;
1202
 
1203 40 unneback
`define MODULE mux_andor
1204
`BASE`MODULE
1205 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1206 36 unneback
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
1207 40 unneback
`undef MODULE
1208
 
1209 34 unneback
endmodule
1210 40 unneback
`endif
1211 34 unneback
 
1212 40 unneback
`ifdef MUX3_ANDOR
1213
`define MODULE mux3_andor
1214
module `BASE`MODULE ( a2, a1, a0, sel, dout);
1215
`undef MODULE
1216 34 unneback
 
1217
parameter width = 32;
1218 35 unneback
localparam nr_of_ports = 3;
1219 34 unneback
input [width-1:0] a2, a1, a0;
1220
input [nr_of_ports-1:0] sel;
1221
output [width-1:0] dout;
1222
 
1223 40 unneback
`define MODULE mux_andor
1224
`BASE`MODULE
1225 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1226 36 unneback
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
1227 40 unneback
`undef MODULE
1228 34 unneback
endmodule
1229 40 unneback
`endif
1230 34 unneback
 
1231 40 unneback
`ifdef MUX4_ANDOR
1232
`define MODULE mux4_andor
1233
module `BASE`MODULE ( a3, a2, a1, a0, sel, dout);
1234
`undef MODULE
1235 18 unneback
 
1236
parameter width = 32;
1237 35 unneback
localparam nr_of_ports = 4;
1238 18 unneback
input [width-1:0] a3, a2, a1, a0;
1239
input [nr_of_ports-1:0] sel;
1240 22 unneback
output [width-1:0] dout;
1241 18 unneback
 
1242 40 unneback
`define MODULE mux_andor
1243
`BASE`MODULE
1244 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1245 36 unneback
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
1246 40 unneback
`undef MODULE
1247 18 unneback
 
1248
endmodule
1249 40 unneback
`endif
1250 18 unneback
 
1251 40 unneback
`ifdef MUX5_ANDOR
1252
`define MODULE mux5_andor
1253
module `BASE`MODULE ( a4, a3, a2, a1, a0, sel, dout);
1254
`undef MODULE
1255 18 unneback
 
1256
parameter width = 32;
1257 35 unneback
localparam nr_of_ports = 5;
1258 18 unneback
input [width-1:0] a4, a3, a2, a1, a0;
1259
input [nr_of_ports-1:0] sel;
1260 22 unneback
output [width-1:0] dout;
1261 18 unneback
 
1262 40 unneback
`define MODULE mux_andor
1263
`BASE`MODULE
1264 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1265 36 unneback
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1266 40 unneback
`undef MODULE
1267 18 unneback
 
1268
endmodule
1269 40 unneback
`endif
1270 18 unneback
 
1271 40 unneback
`ifdef MUX6_ANDOR
1272
`define MODULE mux6_andor
1273
module `BASE`MODULE ( a5, a4, a3, a2, a1, a0, sel, dout);
1274
`undef MODULE
1275 18 unneback
 
1276
parameter width = 32;
1277 35 unneback
localparam nr_of_ports = 6;
1278 18 unneback
input [width-1:0] a5, a4, a3, a2, a1, a0;
1279
input [nr_of_ports-1:0] sel;
1280 22 unneback
output [width-1:0] dout;
1281 18 unneback
 
1282 40 unneback
`define MODULE mux_andor
1283
`BASE`MODULE
1284 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1285 36 unneback
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1286 40 unneback
`undef MODULE
1287 18 unneback
 
1288
endmodule
1289 40 unneback
`endif
1290 43 unneback
 
1291
`ifdef PARITY
1292
 
1293
`define MODULE parity_generate
1294
module `BASE`MODULE (data, parity);
1295
`undef MODULE
1296
parameter word_size = 32;
1297
parameter chunk_size = 8;
1298
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1299
input [word_size-1:0] data;
1300
output reg [word_size/chunk_size-1:0] parity;
1301
integer i,j;
1302
always @ (data)
1303
for (i=0;i<word_size/chunk_size;i=i+1) begin
1304
    parity[i] = parity_type;
1305
    for (j=0;j<chunk_size;j=j+1) begin
1306 46 unneback
        parity[i] = data[i*chunk_size+j] ^ parity[i];
1307 43 unneback
    end
1308
end
1309
endmodule
1310
 
1311
`define MODULE parity_check
1312
module `BASE`MODULE( data, parity, parity_error);
1313
`undef MODULE
1314
parameter word_size = 32;
1315
parameter chunk_size = 8;
1316
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1317
input [word_size-1:0] data;
1318
input [word_size/chunk_size-1:0] parity;
1319
output parity_error;
1320 44 unneback
reg [word_size/chunk_size-1:0] error_flag;
1321 43 unneback
integer i,j;
1322
always @ (data or parity)
1323
for (i=0;i<word_size/chunk_size;i=i+1) begin
1324
    error_flag[i] = parity[i] ^ parity_type;
1325
    for (j=0;j<chunk_size;j=j+1) begin
1326 46 unneback
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
1327 43 unneback
    end
1328
end
1329
assign parity_error = |error_flag;
1330
endmodule
1331
 
1332 44 unneback
`endif//////////////////////////////////////////////////////////////////////
1333
////                                                              ////
1334
////  IO functions                                                ////
1335
////                                                              ////
1336
////  Description                                                 ////
1337
////  IO functions such as IOB flip-flops                         ////
1338
////                                                              ////
1339
////                                                              ////
1340
////  To Do:                                                      ////
1341
////   -                                                          ////
1342
////                                                              ////
1343
////  Author(s):                                                  ////
1344
////      - Michael Unneback, unneback@opencores.org              ////
1345
////        ORSoC AB                                              ////
1346
////                                                              ////
1347 18 unneback
//////////////////////////////////////////////////////////////////////
1348
////                                                              ////
1349 44 unneback
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1350
////                                                              ////
1351
//// This source file may be used and distributed without         ////
1352
//// restriction provided that this copyright statement is not    ////
1353
//// removed from the file and that any derivative work contains  ////
1354
//// the original copyright notice and the associated disclaimer. ////
1355
////                                                              ////
1356
//// This source file is free software; you can redistribute it   ////
1357
//// and/or modify it under the terms of the GNU Lesser General   ////
1358
//// Public License as published by the Free Software Foundation; ////
1359
//// either version 2.1 of the License, or (at your option) any   ////
1360
//// later version.                                               ////
1361
////                                                              ////
1362
//// This source is distributed in the hope that it will be       ////
1363
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1364
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1365
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1366
//// details.                                                     ////
1367
////                                                              ////
1368
//// You should have received a copy of the GNU Lesser General    ////
1369
//// Public License along with this source; if not, download it   ////
1370
//// from http://www.opencores.org/lgpl.shtml                     ////
1371
////                                                              ////
1372
//////////////////////////////////////////////////////////////////////
1373 45 unneback
`timescale 1ns/1ns
1374 44 unneback
`ifdef O_DFF
1375
`define MODULE o_dff
1376
module `BASE`MODULE (d_i, o_pad, clk, rst);
1377
`undef MODULE
1378
parameter width = 1;
1379 45 unneback
parameter reset_value = {width{1'b0}};
1380
input  [width-1:0]  d_i;
1381 44 unneback
output [width-1:0] o_pad;
1382
input clk, rst;
1383
wire [width-1:0] d_i_int `SYN_KEEP;
1384 45 unneback
reg  [width-1:0] o_pad_int;
1385 44 unneback
assign d_i_int = d_i;
1386
genvar i;
1387 45 unneback
generate
1388 44 unneback
for (i=0;i<width;i=i+1) begin
1389
    always @ (posedge clk or posedge rst)
1390
    if (rst)
1391 45 unneback
        o_pad_int[i] <= reset_value[i];
1392 44 unneback
    else
1393 45 unneback
        o_pad_int[i] <= d_i_int[i];
1394
    assign #1 o_pad[i] = o_pad_int[i];
1395 44 unneback
end
1396
endgenerate
1397
endmodule
1398
`endif
1399
 
1400 45 unneback
`timescale 1ns/1ns
1401 44 unneback
`ifdef IO_DFF_OE
1402
`define MODULE io_dff_oe
1403
module `BASE`MODULE ( d_i, d_o, oe, io_pad, clk, rst);
1404
`undef MODULE
1405
parameter width = 1;
1406
input  [width-1:0] d_o;
1407
output reg [width-1:0] d_i;
1408
input oe;
1409
inout [width-1:0] io_pad;
1410
input clk, rst;
1411
wire [width-1:0] oe_d `SYN_KEEP;
1412
reg [width-1:0] oe_q;
1413
reg [width-1:0] d_o_q;
1414
assign oe_d = {width{oe}};
1415
genvar i;
1416
generate
1417
for (i=0;i<width;i=i+1) begin
1418
    always @ (posedge clk or posedge rst)
1419
    if (rst)
1420
        oe_q[i] <= 1'b0;
1421
    else
1422
        oe_q[i] <= oe_d[i];
1423
    always @ (posedge clk or posedge rst)
1424
    if (rst)
1425
        d_o_q[i] <= 1'b0;
1426
    else
1427
        d_o_q[i] <= d_o[i];
1428
    always @ (posedge clk or posedge rst)
1429
    if (rst)
1430
        d_i[i] <= 1'b0;
1431
    else
1432
        d_i[i] <= io_pad[i];
1433 45 unneback
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
1434 44 unneback
end
1435
endgenerate
1436
endmodule
1437
`endif
1438
`ifdef CNT_BIN
1439
//////////////////////////////////////////////////////////////////////
1440
////                                                              ////
1441 6 unneback
////  Versatile counter                                           ////
1442
////                                                              ////
1443
////  Description                                                 ////
1444
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1445
////  counter                                                     ////
1446
////                                                              ////
1447
////  To Do:                                                      ////
1448
////   - add LFSR with more taps                                  ////
1449
////                                                              ////
1450
////  Author(s):                                                  ////
1451
////      - Michael Unneback, unneback@opencores.org              ////
1452
////        ORSoC AB                                              ////
1453
////                                                              ////
1454
//////////////////////////////////////////////////////////////////////
1455
////                                                              ////
1456
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1457
////                                                              ////
1458
//// This source file may be used and distributed without         ////
1459
//// restriction provided that this copyright statement is not    ////
1460
//// removed from the file and that any derivative work contains  ////
1461
//// the original copyright notice and the associated disclaimer. ////
1462
////                                                              ////
1463
//// This source file is free software; you can redistribute it   ////
1464
//// and/or modify it under the terms of the GNU Lesser General   ////
1465
//// Public License as published by the Free Software Foundation; ////
1466
//// either version 2.1 of the License, or (at your option) any   ////
1467
//// later version.                                               ////
1468
////                                                              ////
1469
//// This source is distributed in the hope that it will be       ////
1470
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1471
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1472
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1473
//// details.                                                     ////
1474
////                                                              ////
1475
//// You should have received a copy of the GNU Lesser General    ////
1476
//// Public License along with this source; if not, download it   ////
1477
//// from http://www.opencores.org/lgpl.shtml                     ////
1478
////                                                              ////
1479
//////////////////////////////////////////////////////////////////////
1480
 
1481
// binary counter
1482 22 unneback
 
1483 40 unneback
`define MODULE cnt_bin
1484
module `BASE`MODULE (
1485
`undef MODULE
1486
 q, rst, clk);
1487
 
1488 22 unneback
   parameter length = 4;
1489
   output [length:1] q;
1490
   input rst;
1491
   input clk;
1492
 
1493
   parameter clear_value = 0;
1494
   parameter set_value = 1;
1495
   parameter wrap_value = 0;
1496
   parameter level1_value = 15;
1497
 
1498
   reg  [length:1] qi;
1499
   wire [length:1] q_next;
1500
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1501
 
1502
   always @ (posedge clk or posedge rst)
1503
     if (rst)
1504
       qi <= {length{1'b0}};
1505
     else
1506
       qi <= q_next;
1507
 
1508
   assign q = qi;
1509
 
1510
endmodule
1511 40 unneback
`endif
1512
`ifdef CNT_BIN_CLEAR
1513 22 unneback
//////////////////////////////////////////////////////////////////////
1514
////                                                              ////
1515
////  Versatile counter                                           ////
1516
////                                                              ////
1517
////  Description                                                 ////
1518
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1519
////  counter                                                     ////
1520
////                                                              ////
1521
////  To Do:                                                      ////
1522
////   - add LFSR with more taps                                  ////
1523
////                                                              ////
1524
////  Author(s):                                                  ////
1525
////      - Michael Unneback, unneback@opencores.org              ////
1526
////        ORSoC AB                                              ////
1527
////                                                              ////
1528
//////////////////////////////////////////////////////////////////////
1529
////                                                              ////
1530
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1531
////                                                              ////
1532
//// This source file may be used and distributed without         ////
1533
//// restriction provided that this copyright statement is not    ////
1534
//// removed from the file and that any derivative work contains  ////
1535
//// the original copyright notice and the associated disclaimer. ////
1536
////                                                              ////
1537
//// This source file is free software; you can redistribute it   ////
1538
//// and/or modify it under the terms of the GNU Lesser General   ////
1539
//// Public License as published by the Free Software Foundation; ////
1540
//// either version 2.1 of the License, or (at your option) any   ////
1541
//// later version.                                               ////
1542
////                                                              ////
1543
//// This source is distributed in the hope that it will be       ////
1544
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1545
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1546
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1547
//// details.                                                     ////
1548
////                                                              ////
1549
//// You should have received a copy of the GNU Lesser General    ////
1550
//// Public License along with this source; if not, download it   ////
1551
//// from http://www.opencores.org/lgpl.shtml                     ////
1552
////                                                              ////
1553
//////////////////////////////////////////////////////////////////////
1554
 
1555
// binary counter
1556
 
1557 40 unneback
`define MODULE cnt_bin_clear
1558
module `BASE`MODULE (
1559
`undef MODULE
1560
 clear, q, rst, clk);
1561
 
1562 22 unneback
   parameter length = 4;
1563
   input clear;
1564
   output [length:1] q;
1565
   input rst;
1566
   input clk;
1567
 
1568
   parameter clear_value = 0;
1569
   parameter set_value = 1;
1570
   parameter wrap_value = 0;
1571
   parameter level1_value = 15;
1572
 
1573
   reg  [length:1] qi;
1574
   wire [length:1] q_next;
1575
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1576
 
1577
   always @ (posedge clk or posedge rst)
1578
     if (rst)
1579
       qi <= {length{1'b0}};
1580
     else
1581
       qi <= q_next;
1582
 
1583
   assign q = qi;
1584
 
1585
endmodule
1586 40 unneback
`endif
1587
`ifdef CNT_BIN_CE
1588 22 unneback
//////////////////////////////////////////////////////////////////////
1589
////                                                              ////
1590
////  Versatile counter                                           ////
1591
////                                                              ////
1592
////  Description                                                 ////
1593
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1594
////  counter                                                     ////
1595
////                                                              ////
1596
////  To Do:                                                      ////
1597
////   - add LFSR with more taps                                  ////
1598
////                                                              ////
1599
////  Author(s):                                                  ////
1600
////      - Michael Unneback, unneback@opencores.org              ////
1601
////        ORSoC AB                                              ////
1602
////                                                              ////
1603
//////////////////////////////////////////////////////////////////////
1604
////                                                              ////
1605
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1606
////                                                              ////
1607
//// This source file may be used and distributed without         ////
1608
//// restriction provided that this copyright statement is not    ////
1609
//// removed from the file and that any derivative work contains  ////
1610
//// the original copyright notice and the associated disclaimer. ////
1611
////                                                              ////
1612
//// This source file is free software; you can redistribute it   ////
1613
//// and/or modify it under the terms of the GNU Lesser General   ////
1614
//// Public License as published by the Free Software Foundation; ////
1615
//// either version 2.1 of the License, or (at your option) any   ////
1616
//// later version.                                               ////
1617
////                                                              ////
1618
//// This source is distributed in the hope that it will be       ////
1619
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1620
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1621
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1622
//// details.                                                     ////
1623
////                                                              ////
1624
//// You should have received a copy of the GNU Lesser General    ////
1625
//// Public License along with this source; if not, download it   ////
1626
//// from http://www.opencores.org/lgpl.shtml                     ////
1627
////                                                              ////
1628
//////////////////////////////////////////////////////////////////////
1629
 
1630
// binary counter
1631 6 unneback
 
1632 40 unneback
`define MODULE cnt_bin_ce
1633
module `BASE`MODULE (
1634
`undef MODULE
1635
 cke, q, rst, clk);
1636
 
1637 6 unneback
   parameter length = 4;
1638
   input cke;
1639
   output [length:1] q;
1640
   input rst;
1641
   input clk;
1642
 
1643
   parameter clear_value = 0;
1644
   parameter set_value = 1;
1645
   parameter wrap_value = 0;
1646
   parameter level1_value = 15;
1647
 
1648
   reg  [length:1] qi;
1649
   wire [length:1] q_next;
1650
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1651
 
1652
   always @ (posedge clk or posedge rst)
1653
     if (rst)
1654
       qi <= {length{1'b0}};
1655
     else
1656
     if (cke)
1657
       qi <= q_next;
1658
 
1659
   assign q = qi;
1660
 
1661
endmodule
1662 40 unneback
`endif
1663
`ifdef CNT_BIN_CE_CLEAR
1664 6 unneback
//////////////////////////////////////////////////////////////////////
1665
////                                                              ////
1666
////  Versatile counter                                           ////
1667
////                                                              ////
1668
////  Description                                                 ////
1669
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1670
////  counter                                                     ////
1671
////                                                              ////
1672
////  To Do:                                                      ////
1673
////   - add LFSR with more taps                                  ////
1674
////                                                              ////
1675
////  Author(s):                                                  ////
1676
////      - Michael Unneback, unneback@opencores.org              ////
1677
////        ORSoC AB                                              ////
1678
////                                                              ////
1679
//////////////////////////////////////////////////////////////////////
1680
////                                                              ////
1681
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1682
////                                                              ////
1683
//// This source file may be used and distributed without         ////
1684
//// restriction provided that this copyright statement is not    ////
1685
//// removed from the file and that any derivative work contains  ////
1686
//// the original copyright notice and the associated disclaimer. ////
1687
////                                                              ////
1688
//// This source file is free software; you can redistribute it   ////
1689
//// and/or modify it under the terms of the GNU Lesser General   ////
1690
//// Public License as published by the Free Software Foundation; ////
1691
//// either version 2.1 of the License, or (at your option) any   ////
1692
//// later version.                                               ////
1693
////                                                              ////
1694
//// This source is distributed in the hope that it will be       ////
1695
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1696
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1697
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1698
//// details.                                                     ////
1699
////                                                              ////
1700
//// You should have received a copy of the GNU Lesser General    ////
1701
//// Public License along with this source; if not, download it   ////
1702
//// from http://www.opencores.org/lgpl.shtml                     ////
1703
////                                                              ////
1704
//////////////////////////////////////////////////////////////////////
1705
 
1706
// binary counter
1707
 
1708 40 unneback
`define MODULE cnt_bin_ce_clear
1709
module `BASE`MODULE (
1710
`undef MODULE
1711
 clear, cke, q, rst, clk);
1712
 
1713 6 unneback
   parameter length = 4;
1714
   input clear;
1715
   input cke;
1716
   output [length:1] q;
1717
   input rst;
1718
   input clk;
1719
 
1720
   parameter clear_value = 0;
1721
   parameter set_value = 1;
1722
   parameter wrap_value = 0;
1723
   parameter level1_value = 15;
1724
 
1725
   reg  [length:1] qi;
1726
   wire [length:1] q_next;
1727
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1728
 
1729
   always @ (posedge clk or posedge rst)
1730
     if (rst)
1731
       qi <= {length{1'b0}};
1732
     else
1733
     if (cke)
1734
       qi <= q_next;
1735
 
1736
   assign q = qi;
1737
 
1738
endmodule
1739 40 unneback
`endif
1740
`ifdef CNT_BIN_CE_CLEAR_L1_L2
1741 6 unneback
//////////////////////////////////////////////////////////////////////
1742
////                                                              ////
1743
////  Versatile counter                                           ////
1744
////                                                              ////
1745
////  Description                                                 ////
1746
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1747
////  counter                                                     ////
1748
////                                                              ////
1749
////  To Do:                                                      ////
1750
////   - add LFSR with more taps                                  ////
1751
////                                                              ////
1752
////  Author(s):                                                  ////
1753
////      - Michael Unneback, unneback@opencores.org              ////
1754
////        ORSoC AB                                              ////
1755
////                                                              ////
1756
//////////////////////////////////////////////////////////////////////
1757
////                                                              ////
1758
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1759
////                                                              ////
1760
//// This source file may be used and distributed without         ////
1761
//// restriction provided that this copyright statement is not    ////
1762
//// removed from the file and that any derivative work contains  ////
1763
//// the original copyright notice and the associated disclaimer. ////
1764
////                                                              ////
1765
//// This source file is free software; you can redistribute it   ////
1766
//// and/or modify it under the terms of the GNU Lesser General   ////
1767
//// Public License as published by the Free Software Foundation; ////
1768
//// either version 2.1 of the License, or (at your option) any   ////
1769
//// later version.                                               ////
1770
////                                                              ////
1771
//// This source is distributed in the hope that it will be       ////
1772
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1773
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1774
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1775
//// details.                                                     ////
1776
////                                                              ////
1777
//// You should have received a copy of the GNU Lesser General    ////
1778
//// Public License along with this source; if not, download it   ////
1779
//// from http://www.opencores.org/lgpl.shtml                     ////
1780
////                                                              ////
1781
//////////////////////////////////////////////////////////////////////
1782
 
1783
// binary counter
1784 29 unneback
 
1785 40 unneback
`define MODULE cnt_bin_ce_clear_l1_l2
1786
module `BASE`MODULE (
1787
`undef MODULE
1788
 clear, cke, q, level1, level2, rst, clk);
1789
 
1790 29 unneback
   parameter length = 4;
1791
   input clear;
1792
   input cke;
1793
   output [length:1] q;
1794
   output reg level1;
1795
   output reg level2;
1796
   input rst;
1797
   input clk;
1798
 
1799
   parameter clear_value = 0;
1800
   parameter set_value = 1;
1801 30 unneback
   parameter wrap_value = 15;
1802
   parameter level1_value = 8;
1803
   parameter level2_value = 15;
1804 29 unneback
 
1805
   wire rew;
1806 30 unneback
   assign rew = 1'b0;
1807 29 unneback
   reg  [length:1] qi;
1808
   wire [length:1] q_next;
1809
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1810
 
1811
   always @ (posedge clk or posedge rst)
1812
     if (rst)
1813
       qi <= {length{1'b0}};
1814
     else
1815
     if (cke)
1816
       qi <= q_next;
1817
 
1818
   assign q = qi;
1819
 
1820
 
1821
    always @ (posedge clk or posedge rst)
1822
    if (rst)
1823
        level1 <= 1'b0;
1824
    else
1825
    if (cke)
1826
    if (clear)
1827
        level1 <= 1'b0;
1828
    else if (q_next == level1_value)
1829
        level1 <= 1'b1;
1830
    else if (qi == level1_value & rew)
1831
        level1 <= 1'b0;
1832
 
1833
    always @ (posedge clk or posedge rst)
1834
    if (rst)
1835
        level2 <= 1'b0;
1836
    else
1837
    if (cke)
1838
    if (clear)
1839
        level2 <= 1'b0;
1840
    else if (q_next == level2_value)
1841
        level2 <= 1'b1;
1842
    else if (qi == level2_value & rew)
1843
        level2 <= 1'b0;
1844
endmodule
1845 40 unneback
`endif
1846
`ifdef CNT_BIN_CE_CLEAR_SET_REW
1847 29 unneback
//////////////////////////////////////////////////////////////////////
1848
////                                                              ////
1849
////  Versatile counter                                           ////
1850
////                                                              ////
1851
////  Description                                                 ////
1852
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1853
////  counter                                                     ////
1854
////                                                              ////
1855
////  To Do:                                                      ////
1856
////   - add LFSR with more taps                                  ////
1857
////                                                              ////
1858
////  Author(s):                                                  ////
1859
////      - Michael Unneback, unneback@opencores.org              ////
1860
////        ORSoC AB                                              ////
1861
////                                                              ////
1862
//////////////////////////////////////////////////////////////////////
1863
////                                                              ////
1864
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1865
////                                                              ////
1866
//// This source file may be used and distributed without         ////
1867
//// restriction provided that this copyright statement is not    ////
1868
//// removed from the file and that any derivative work contains  ////
1869
//// the original copyright notice and the associated disclaimer. ////
1870
////                                                              ////
1871
//// This source file is free software; you can redistribute it   ////
1872
//// and/or modify it under the terms of the GNU Lesser General   ////
1873
//// Public License as published by the Free Software Foundation; ////
1874
//// either version 2.1 of the License, or (at your option) any   ////
1875
//// later version.                                               ////
1876
////                                                              ////
1877
//// This source is distributed in the hope that it will be       ////
1878
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1879
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1880
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1881
//// details.                                                     ////
1882
////                                                              ////
1883
//// You should have received a copy of the GNU Lesser General    ////
1884
//// Public License along with this source; if not, download it   ////
1885
//// from http://www.opencores.org/lgpl.shtml                     ////
1886
////                                                              ////
1887
//////////////////////////////////////////////////////////////////////
1888
 
1889
// binary counter
1890 6 unneback
 
1891 40 unneback
`define MODULE cnt_bin_ce_clear_set_rew
1892
module `BASE`MODULE (
1893
`undef MODULE
1894
 clear, set, cke, rew, q, rst, clk);
1895
 
1896 6 unneback
   parameter length = 4;
1897
   input clear;
1898
   input set;
1899
   input cke;
1900
   input rew;
1901
   output [length:1] q;
1902
   input rst;
1903
   input clk;
1904
 
1905
   parameter clear_value = 0;
1906
   parameter set_value = 1;
1907
   parameter wrap_value = 0;
1908
   parameter level1_value = 15;
1909
 
1910
   reg  [length:1] qi;
1911
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1912
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
1913
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
1914
   assign q_next = rew ? q_next_rew : q_next_fw;
1915
 
1916
   always @ (posedge clk or posedge rst)
1917
     if (rst)
1918
       qi <= {length{1'b0}};
1919
     else
1920
     if (cke)
1921
       qi <= q_next;
1922
 
1923
   assign q = qi;
1924
 
1925
endmodule
1926 40 unneback
`endif
1927
`ifdef CNT_BIN_CE_REW_L1
1928 6 unneback
//////////////////////////////////////////////////////////////////////
1929
////                                                              ////
1930
////  Versatile counter                                           ////
1931
////                                                              ////
1932
////  Description                                                 ////
1933
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1934
////  counter                                                     ////
1935
////                                                              ////
1936
////  To Do:                                                      ////
1937
////   - add LFSR with more taps                                  ////
1938
////                                                              ////
1939
////  Author(s):                                                  ////
1940
////      - Michael Unneback, unneback@opencores.org              ////
1941
////        ORSoC AB                                              ////
1942
////                                                              ////
1943
//////////////////////////////////////////////////////////////////////
1944
////                                                              ////
1945
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1946
////                                                              ////
1947
//// This source file may be used and distributed without         ////
1948
//// restriction provided that this copyright statement is not    ////
1949
//// removed from the file and that any derivative work contains  ////
1950
//// the original copyright notice and the associated disclaimer. ////
1951
////                                                              ////
1952
//// This source file is free software; you can redistribute it   ////
1953
//// and/or modify it under the terms of the GNU Lesser General   ////
1954
//// Public License as published by the Free Software Foundation; ////
1955
//// either version 2.1 of the License, or (at your option) any   ////
1956
//// later version.                                               ////
1957
////                                                              ////
1958
//// This source is distributed in the hope that it will be       ////
1959
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1960
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1961
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1962
//// details.                                                     ////
1963
////                                                              ////
1964
//// You should have received a copy of the GNU Lesser General    ////
1965
//// Public License along with this source; if not, download it   ////
1966
//// from http://www.opencores.org/lgpl.shtml                     ////
1967
////                                                              ////
1968
//////////////////////////////////////////////////////////////////////
1969
 
1970
// binary counter
1971
 
1972 40 unneback
`define MODULE cnt_bin_ce_rew_l1
1973
module `BASE`MODULE (
1974
`undef MODULE
1975
 cke, rew, level1, rst, clk);
1976
 
1977 6 unneback
   parameter length = 4;
1978
   input cke;
1979
   input rew;
1980
   output reg level1;
1981
   input rst;
1982
   input clk;
1983
 
1984
   parameter clear_value = 0;
1985
   parameter set_value = 1;
1986
   parameter wrap_value = 1;
1987
   parameter level1_value = 15;
1988
 
1989 29 unneback
   wire clear;
1990 30 unneback
   assign clear = 1'b0;
1991 6 unneback
   reg  [length:1] qi;
1992
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1993
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1994
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1995
   assign q_next = rew ? q_next_rew : q_next_fw;
1996
 
1997
   always @ (posedge clk or posedge rst)
1998
     if (rst)
1999
       qi <= {length{1'b0}};
2000
     else
2001
     if (cke)
2002
       qi <= q_next;
2003
 
2004
 
2005
 
2006
    always @ (posedge clk or posedge rst)
2007
    if (rst)
2008
        level1 <= 1'b0;
2009
    else
2010
    if (cke)
2011 29 unneback
    if (clear)
2012
        level1 <= 1'b0;
2013
    else if (q_next == level1_value)
2014 6 unneback
        level1 <= 1'b1;
2015
    else if (qi == level1_value & rew)
2016
        level1 <= 1'b0;
2017
endmodule
2018 40 unneback
`endif
2019
`ifdef CNT_BIN_CE_REW_ZQ_L1
2020 6 unneback
//////////////////////////////////////////////////////////////////////
2021
////                                                              ////
2022
////  Versatile counter                                           ////
2023
////                                                              ////
2024
////  Description                                                 ////
2025
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2026
////  counter                                                     ////
2027
////                                                              ////
2028
////  To Do:                                                      ////
2029
////   - add LFSR with more taps                                  ////
2030
////                                                              ////
2031
////  Author(s):                                                  ////
2032
////      - Michael Unneback, unneback@opencores.org              ////
2033
////        ORSoC AB                                              ////
2034
////                                                              ////
2035
//////////////////////////////////////////////////////////////////////
2036
////                                                              ////
2037
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2038
////                                                              ////
2039
//// This source file may be used and distributed without         ////
2040
//// restriction provided that this copyright statement is not    ////
2041
//// removed from the file and that any derivative work contains  ////
2042
//// the original copyright notice and the associated disclaimer. ////
2043
////                                                              ////
2044
//// This source file is free software; you can redistribute it   ////
2045
//// and/or modify it under the terms of the GNU Lesser General   ////
2046
//// Public License as published by the Free Software Foundation; ////
2047
//// either version 2.1 of the License, or (at your option) any   ////
2048
//// later version.                                               ////
2049
////                                                              ////
2050
//// This source is distributed in the hope that it will be       ////
2051
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2052
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2053
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2054
//// details.                                                     ////
2055
////                                                              ////
2056
//// You should have received a copy of the GNU Lesser General    ////
2057
//// Public License along with this source; if not, download it   ////
2058
//// from http://www.opencores.org/lgpl.shtml                     ////
2059
////                                                              ////
2060
//////////////////////////////////////////////////////////////////////
2061
 
2062 25 unneback
// binary counter
2063
 
2064 40 unneback
`define MODULE cnt_bin_ce_rew_zq_l1
2065
module `BASE`MODULE (
2066
`undef MODULE
2067
 cke, rew, zq, level1, rst, clk);
2068
 
2069 25 unneback
   parameter length = 4;
2070
   input cke;
2071
   input rew;
2072
   output reg zq;
2073
   output reg level1;
2074
   input rst;
2075
   input clk;
2076
 
2077
   parameter clear_value = 0;
2078
   parameter set_value = 1;
2079
   parameter wrap_value = 1;
2080
   parameter level1_value = 15;
2081
 
2082 29 unneback
   wire clear;
2083 30 unneback
   assign clear = 1'b0;
2084 25 unneback
   reg  [length:1] qi;
2085
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2086
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2087
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2088
   assign q_next = rew ? q_next_rew : q_next_fw;
2089
 
2090
   always @ (posedge clk or posedge rst)
2091
     if (rst)
2092
       qi <= {length{1'b0}};
2093
     else
2094
     if (cke)
2095
       qi <= q_next;
2096
 
2097
 
2098
 
2099
   always @ (posedge clk or posedge rst)
2100
     if (rst)
2101
       zq <= 1'b1;
2102
     else
2103
     if (cke)
2104
       zq <= q_next == {length{1'b0}};
2105
 
2106
    always @ (posedge clk or posedge rst)
2107
    if (rst)
2108
        level1 <= 1'b0;
2109
    else
2110
    if (cke)
2111 29 unneback
    if (clear)
2112
        level1 <= 1'b0;
2113
    else if (q_next == level1_value)
2114 25 unneback
        level1 <= 1'b1;
2115
    else if (qi == level1_value & rew)
2116
        level1 <= 1'b0;
2117
endmodule
2118 40 unneback
`endif
2119
`ifdef CNT_BIN_CE_REW_Q_ZQ_L1
2120 25 unneback
//////////////////////////////////////////////////////////////////////
2121
////                                                              ////
2122
////  Versatile counter                                           ////
2123
////                                                              ////
2124
////  Description                                                 ////
2125
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2126
////  counter                                                     ////
2127
////                                                              ////
2128
////  To Do:                                                      ////
2129
////   - add LFSR with more taps                                  ////
2130
////                                                              ////
2131
////  Author(s):                                                  ////
2132
////      - Michael Unneback, unneback@opencores.org              ////
2133
////        ORSoC AB                                              ////
2134
////                                                              ////
2135
//////////////////////////////////////////////////////////////////////
2136
////                                                              ////
2137
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2138
////                                                              ////
2139
//// This source file may be used and distributed without         ////
2140
//// restriction provided that this copyright statement is not    ////
2141
//// removed from the file and that any derivative work contains  ////
2142
//// the original copyright notice and the associated disclaimer. ////
2143
////                                                              ////
2144
//// This source file is free software; you can redistribute it   ////
2145
//// and/or modify it under the terms of the GNU Lesser General   ////
2146
//// Public License as published by the Free Software Foundation; ////
2147
//// either version 2.1 of the License, or (at your option) any   ////
2148
//// later version.                                               ////
2149
////                                                              ////
2150
//// This source is distributed in the hope that it will be       ////
2151
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2152
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2153
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2154
//// details.                                                     ////
2155
////                                                              ////
2156
//// You should have received a copy of the GNU Lesser General    ////
2157
//// Public License along with this source; if not, download it   ////
2158
//// from http://www.opencores.org/lgpl.shtml                     ////
2159
////                                                              ////
2160
//////////////////////////////////////////////////////////////////////
2161
 
2162
// binary counter
2163
 
2164 40 unneback
`define MODULE cnt_bin_ce_rew_q_zq_l1
2165
module `BASE`MODULE (
2166
`undef MODULE
2167
 cke, rew, q, zq, level1, rst, clk);
2168
 
2169 25 unneback
   parameter length = 4;
2170
   input cke;
2171
   input rew;
2172
   output [length:1] q;
2173
   output reg zq;
2174
   output reg level1;
2175
   input rst;
2176
   input clk;
2177
 
2178
   parameter clear_value = 0;
2179
   parameter set_value = 1;
2180
   parameter wrap_value = 1;
2181
   parameter level1_value = 15;
2182
 
2183 29 unneback
   wire clear;
2184 30 unneback
   assign clear = 1'b0;
2185 25 unneback
   reg  [length:1] qi;
2186
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2187
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2188
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2189
   assign q_next = rew ? q_next_rew : q_next_fw;
2190
 
2191
   always @ (posedge clk or posedge rst)
2192
     if (rst)
2193
       qi <= {length{1'b0}};
2194
     else
2195
     if (cke)
2196
       qi <= q_next;
2197
 
2198
   assign q = qi;
2199
 
2200
 
2201
   always @ (posedge clk or posedge rst)
2202
     if (rst)
2203
       zq <= 1'b1;
2204
     else
2205
     if (cke)
2206
       zq <= q_next == {length{1'b0}};
2207
 
2208
    always @ (posedge clk or posedge rst)
2209
    if (rst)
2210
        level1 <= 1'b0;
2211
    else
2212
    if (cke)
2213 29 unneback
    if (clear)
2214
        level1 <= 1'b0;
2215
    else if (q_next == level1_value)
2216 25 unneback
        level1 <= 1'b1;
2217
    else if (qi == level1_value & rew)
2218
        level1 <= 1'b0;
2219
endmodule
2220 40 unneback
`endif
2221
`ifdef CNT_LFSR_ZQ
2222 25 unneback
//////////////////////////////////////////////////////////////////////
2223
////                                                              ////
2224
////  Versatile counter                                           ////
2225
////                                                              ////
2226
////  Description                                                 ////
2227
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2228
////  counter                                                     ////
2229
////                                                              ////
2230
////  To Do:                                                      ////
2231
////   - add LFSR with more taps                                  ////
2232
////                                                              ////
2233
////  Author(s):                                                  ////
2234
////      - Michael Unneback, unneback@opencores.org              ////
2235
////        ORSoC AB                                              ////
2236
////                                                              ////
2237
//////////////////////////////////////////////////////////////////////
2238
////                                                              ////
2239
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2240
////                                                              ////
2241
//// This source file may be used and distributed without         ////
2242
//// restriction provided that this copyright statement is not    ////
2243
//// removed from the file and that any derivative work contains  ////
2244
//// the original copyright notice and the associated disclaimer. ////
2245
////                                                              ////
2246
//// This source file is free software; you can redistribute it   ////
2247
//// and/or modify it under the terms of the GNU Lesser General   ////
2248
//// Public License as published by the Free Software Foundation; ////
2249
//// either version 2.1 of the License, or (at your option) any   ////
2250
//// later version.                                               ////
2251
////                                                              ////
2252
//// This source is distributed in the hope that it will be       ////
2253
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2254
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2255
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2256
//// details.                                                     ////
2257
////                                                              ////
2258
//// You should have received a copy of the GNU Lesser General    ////
2259
//// Public License along with this source; if not, download it   ////
2260
//// from http://www.opencores.org/lgpl.shtml                     ////
2261
////                                                              ////
2262
//////////////////////////////////////////////////////////////////////
2263
 
2264 6 unneback
// LFSR counter
2265
 
2266 40 unneback
`define MODULE cnt_lfsr_zq
2267
module `BASE`MODULE (
2268
`undef MODULE
2269
 zq, rst, clk);
2270
 
2271 6 unneback
   parameter length = 4;
2272
   output reg zq;
2273
   input rst;
2274
   input clk;
2275
 
2276
   parameter clear_value = 0;
2277
   parameter set_value = 1;
2278
   parameter wrap_value = 8;
2279
   parameter level1_value = 15;
2280
 
2281
   reg  [length:1] qi;
2282
   reg lfsr_fb;
2283
   wire [length:1] q_next;
2284
   reg [32:1] polynom;
2285
   integer i;
2286
 
2287
   always @ (qi)
2288
   begin
2289
        case (length)
2290
         2: polynom = 32'b11;                               // 0x3
2291
         3: polynom = 32'b110;                              // 0x6
2292
         4: polynom = 32'b1100;                             // 0xC
2293
         5: polynom = 32'b10100;                            // 0x14
2294
         6: polynom = 32'b110000;                           // 0x30
2295
         7: polynom = 32'b1100000;                          // 0x60
2296
         8: polynom = 32'b10111000;                         // 0xb8
2297
         9: polynom = 32'b100010000;                        // 0x110
2298
        10: polynom = 32'b1001000000;                       // 0x240
2299
        11: polynom = 32'b10100000000;                      // 0x500
2300
        12: polynom = 32'b100000101001;                     // 0x829
2301
        13: polynom = 32'b1000000001100;                    // 0x100C
2302
        14: polynom = 32'b10000000010101;                   // 0x2015
2303
        15: polynom = 32'b110000000000000;                  // 0x6000
2304
        16: polynom = 32'b1101000000001000;                 // 0xD008
2305
        17: polynom = 32'b10010000000000000;                // 0x12000
2306
        18: polynom = 32'b100000010000000000;               // 0x20400
2307
        19: polynom = 32'b1000000000000100011;              // 0x40023
2308 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2309 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2310
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2311
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2312
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2313
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2314
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2315
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2316
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2317
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2318
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2319
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2320
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2321
        default: polynom = 32'b0;
2322
        endcase
2323
        lfsr_fb = qi[length];
2324
        for (i=length-1; i>=1; i=i-1) begin
2325
            if (polynom[i])
2326
                lfsr_fb = lfsr_fb  ~^ qi[i];
2327
        end
2328
    end
2329
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2330
 
2331
   always @ (posedge clk or posedge rst)
2332
     if (rst)
2333
       qi <= {length{1'b0}};
2334
     else
2335
       qi <= q_next;
2336
 
2337
 
2338
 
2339
   always @ (posedge clk or posedge rst)
2340
     if (rst)
2341
       zq <= 1'b1;
2342
     else
2343
       zq <= q_next == {length{1'b0}};
2344
endmodule
2345 40 unneback
`endif
2346
`ifdef CNT_LFSR_CE_ZQ
2347 6 unneback
//////////////////////////////////////////////////////////////////////
2348
////                                                              ////
2349
////  Versatile counter                                           ////
2350
////                                                              ////
2351
////  Description                                                 ////
2352
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2353
////  counter                                                     ////
2354
////                                                              ////
2355
////  To Do:                                                      ////
2356
////   - add LFSR with more taps                                  ////
2357
////                                                              ////
2358
////  Author(s):                                                  ////
2359
////      - Michael Unneback, unneback@opencores.org              ////
2360
////        ORSoC AB                                              ////
2361
////                                                              ////
2362
//////////////////////////////////////////////////////////////////////
2363
////                                                              ////
2364
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2365
////                                                              ////
2366
//// This source file may be used and distributed without         ////
2367
//// restriction provided that this copyright statement is not    ////
2368
//// removed from the file and that any derivative work contains  ////
2369
//// the original copyright notice and the associated disclaimer. ////
2370
////                                                              ////
2371
//// This source file is free software; you can redistribute it   ////
2372
//// and/or modify it under the terms of the GNU Lesser General   ////
2373
//// Public License as published by the Free Software Foundation; ////
2374
//// either version 2.1 of the License, or (at your option) any   ////
2375
//// later version.                                               ////
2376
////                                                              ////
2377
//// This source is distributed in the hope that it will be       ////
2378
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2379
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2380
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2381
//// details.                                                     ////
2382
////                                                              ////
2383
//// You should have received a copy of the GNU Lesser General    ////
2384
//// Public License along with this source; if not, download it   ////
2385
//// from http://www.opencores.org/lgpl.shtml                     ////
2386
////                                                              ////
2387
//////////////////////////////////////////////////////////////////////
2388
 
2389
// LFSR counter
2390
 
2391 40 unneback
`define MODULE cnt_lfsr_ce_zq
2392
module `BASE`MODULE (
2393
`undef MODULE
2394
 cke, zq, rst, clk);
2395
 
2396 6 unneback
   parameter length = 4;
2397
   input cke;
2398
   output reg zq;
2399
   input rst;
2400
   input clk;
2401
 
2402
   parameter clear_value = 0;
2403
   parameter set_value = 1;
2404
   parameter wrap_value = 8;
2405
   parameter level1_value = 15;
2406
 
2407
   reg  [length:1] qi;
2408
   reg lfsr_fb;
2409
   wire [length:1] q_next;
2410
   reg [32:1] polynom;
2411
   integer i;
2412
 
2413
   always @ (qi)
2414
   begin
2415
        case (length)
2416
         2: polynom = 32'b11;                               // 0x3
2417
         3: polynom = 32'b110;                              // 0x6
2418
         4: polynom = 32'b1100;                             // 0xC
2419
         5: polynom = 32'b10100;                            // 0x14
2420
         6: polynom = 32'b110000;                           // 0x30
2421
         7: polynom = 32'b1100000;                          // 0x60
2422
         8: polynom = 32'b10111000;                         // 0xb8
2423
         9: polynom = 32'b100010000;                        // 0x110
2424
        10: polynom = 32'b1001000000;                       // 0x240
2425
        11: polynom = 32'b10100000000;                      // 0x500
2426
        12: polynom = 32'b100000101001;                     // 0x829
2427
        13: polynom = 32'b1000000001100;                    // 0x100C
2428
        14: polynom = 32'b10000000010101;                   // 0x2015
2429
        15: polynom = 32'b110000000000000;                  // 0x6000
2430
        16: polynom = 32'b1101000000001000;                 // 0xD008
2431
        17: polynom = 32'b10010000000000000;                // 0x12000
2432
        18: polynom = 32'b100000010000000000;               // 0x20400
2433
        19: polynom = 32'b1000000000000100011;              // 0x40023
2434 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2435 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2436
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2437
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2438
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2439
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2440
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2441
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2442
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2443
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2444
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2445
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2446
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2447
        default: polynom = 32'b0;
2448
        endcase
2449
        lfsr_fb = qi[length];
2450
        for (i=length-1; i>=1; i=i-1) begin
2451
            if (polynom[i])
2452
                lfsr_fb = lfsr_fb  ~^ qi[i];
2453
        end
2454
    end
2455
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2456
 
2457
   always @ (posedge clk or posedge rst)
2458
     if (rst)
2459
       qi <= {length{1'b0}};
2460
     else
2461
     if (cke)
2462
       qi <= q_next;
2463
 
2464
 
2465
 
2466
   always @ (posedge clk or posedge rst)
2467
     if (rst)
2468
       zq <= 1'b1;
2469
     else
2470
     if (cke)
2471
       zq <= q_next == {length{1'b0}};
2472
endmodule
2473 40 unneback
`endif
2474
`ifdef CNT_LFSR_CE_Q
2475 6 unneback
//////////////////////////////////////////////////////////////////////
2476
////                                                              ////
2477
////  Versatile counter                                           ////
2478
////                                                              ////
2479
////  Description                                                 ////
2480
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2481
////  counter                                                     ////
2482
////                                                              ////
2483
////  To Do:                                                      ////
2484
////   - add LFSR with more taps                                  ////
2485
////                                                              ////
2486
////  Author(s):                                                  ////
2487
////      - Michael Unneback, unneback@opencores.org              ////
2488
////        ORSoC AB                                              ////
2489
////                                                              ////
2490
//////////////////////////////////////////////////////////////////////
2491
////                                                              ////
2492
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2493
////                                                              ////
2494
//// This source file may be used and distributed without         ////
2495
//// restriction provided that this copyright statement is not    ////
2496
//// removed from the file and that any derivative work contains  ////
2497
//// the original copyright notice and the associated disclaimer. ////
2498
////                                                              ////
2499
//// This source file is free software; you can redistribute it   ////
2500
//// and/or modify it under the terms of the GNU Lesser General   ////
2501
//// Public License as published by the Free Software Foundation; ////
2502
//// either version 2.1 of the License, or (at your option) any   ////
2503
//// later version.                                               ////
2504
////                                                              ////
2505
//// This source is distributed in the hope that it will be       ////
2506
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2507
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2508
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2509
//// details.                                                     ////
2510
////                                                              ////
2511
//// You should have received a copy of the GNU Lesser General    ////
2512
//// Public License along with this source; if not, download it   ////
2513
//// from http://www.opencores.org/lgpl.shtml                     ////
2514
////                                                              ////
2515
//////////////////////////////////////////////////////////////////////
2516 22 unneback
 
2517
// LFSR counter
2518 27 unneback
 
2519 40 unneback
`define MODULE cnt_lfsr_ce_q
2520
module `BASE`MODULE (
2521
`undef MODULE
2522
 cke, q, rst, clk);
2523
 
2524 27 unneback
   parameter length = 4;
2525
   input cke;
2526
   output [length:1] q;
2527
   input rst;
2528
   input clk;
2529
 
2530
   parameter clear_value = 0;
2531
   parameter set_value = 1;
2532
   parameter wrap_value = 8;
2533
   parameter level1_value = 15;
2534
 
2535
   reg  [length:1] qi;
2536
   reg lfsr_fb;
2537
   wire [length:1] q_next;
2538
   reg [32:1] polynom;
2539
   integer i;
2540
 
2541
   always @ (qi)
2542
   begin
2543
        case (length)
2544
         2: polynom = 32'b11;                               // 0x3
2545
         3: polynom = 32'b110;                              // 0x6
2546
         4: polynom = 32'b1100;                             // 0xC
2547
         5: polynom = 32'b10100;                            // 0x14
2548
         6: polynom = 32'b110000;                           // 0x30
2549
         7: polynom = 32'b1100000;                          // 0x60
2550
         8: polynom = 32'b10111000;                         // 0xb8
2551
         9: polynom = 32'b100010000;                        // 0x110
2552
        10: polynom = 32'b1001000000;                       // 0x240
2553
        11: polynom = 32'b10100000000;                      // 0x500
2554
        12: polynom = 32'b100000101001;                     // 0x829
2555
        13: polynom = 32'b1000000001100;                    // 0x100C
2556
        14: polynom = 32'b10000000010101;                   // 0x2015
2557
        15: polynom = 32'b110000000000000;                  // 0x6000
2558
        16: polynom = 32'b1101000000001000;                 // 0xD008
2559
        17: polynom = 32'b10010000000000000;                // 0x12000
2560
        18: polynom = 32'b100000010000000000;               // 0x20400
2561
        19: polynom = 32'b1000000000000100011;              // 0x40023
2562 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2563 27 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2564
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2565
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2566
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2567
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2568
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2569
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2570
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2571
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2572
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2573
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2574
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2575
        default: polynom = 32'b0;
2576
        endcase
2577
        lfsr_fb = qi[length];
2578
        for (i=length-1; i>=1; i=i-1) begin
2579
            if (polynom[i])
2580
                lfsr_fb = lfsr_fb  ~^ qi[i];
2581
        end
2582
    end
2583
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2584
 
2585
   always @ (posedge clk or posedge rst)
2586
     if (rst)
2587
       qi <= {length{1'b0}};
2588
     else
2589
     if (cke)
2590
       qi <= q_next;
2591
 
2592
   assign q = qi;
2593
 
2594
endmodule
2595 40 unneback
`endif
2596
`ifdef CNT_LFSR_CE_CLEAR_Q
2597 27 unneback
//////////////////////////////////////////////////////////////////////
2598
////                                                              ////
2599
////  Versatile counter                                           ////
2600
////                                                              ////
2601
////  Description                                                 ////
2602
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2603
////  counter                                                     ////
2604
////                                                              ////
2605
////  To Do:                                                      ////
2606
////   - add LFSR with more taps                                  ////
2607
////                                                              ////
2608
////  Author(s):                                                  ////
2609
////      - Michael Unneback, unneback@opencores.org              ////
2610
////        ORSoC AB                                              ////
2611
////                                                              ////
2612
//////////////////////////////////////////////////////////////////////
2613
////                                                              ////
2614
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2615
////                                                              ////
2616
//// This source file may be used and distributed without         ////
2617
//// restriction provided that this copyright statement is not    ////
2618
//// removed from the file and that any derivative work contains  ////
2619
//// the original copyright notice and the associated disclaimer. ////
2620
////                                                              ////
2621
//// This source file is free software; you can redistribute it   ////
2622
//// and/or modify it under the terms of the GNU Lesser General   ////
2623
//// Public License as published by the Free Software Foundation; ////
2624
//// either version 2.1 of the License, or (at your option) any   ////
2625
//// later version.                                               ////
2626
////                                                              ////
2627
//// This source is distributed in the hope that it will be       ////
2628
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2629
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2630
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2631
//// details.                                                     ////
2632
////                                                              ////
2633
//// You should have received a copy of the GNU Lesser General    ////
2634
//// Public License along with this source; if not, download it   ////
2635
//// from http://www.opencores.org/lgpl.shtml                     ////
2636
////                                                              ////
2637
//////////////////////////////////////////////////////////////////////
2638
 
2639
// LFSR counter
2640
 
2641 40 unneback
`define MODULE cnt_lfsr_ce_clear_q
2642
module `BASE`MODULE (
2643
`undef MODULE
2644
 clear, cke, q, rst, clk);
2645
 
2646 27 unneback
   parameter length = 4;
2647
   input clear;
2648
   input cke;
2649
   output [length:1] q;
2650
   input rst;
2651
   input clk;
2652
 
2653
   parameter clear_value = 0;
2654
   parameter set_value = 1;
2655
   parameter wrap_value = 8;
2656
   parameter level1_value = 15;
2657
 
2658
   reg  [length:1] qi;
2659
   reg lfsr_fb;
2660
   wire [length:1] q_next;
2661
   reg [32:1] polynom;
2662
   integer i;
2663
 
2664
   always @ (qi)
2665
   begin
2666
        case (length)
2667
         2: polynom = 32'b11;                               // 0x3
2668
         3: polynom = 32'b110;                              // 0x6
2669
         4: polynom = 32'b1100;                             // 0xC
2670
         5: polynom = 32'b10100;                            // 0x14
2671
         6: polynom = 32'b110000;                           // 0x30
2672
         7: polynom = 32'b1100000;                          // 0x60
2673
         8: polynom = 32'b10111000;                         // 0xb8
2674
         9: polynom = 32'b100010000;                        // 0x110
2675
        10: polynom = 32'b1001000000;                       // 0x240
2676
        11: polynom = 32'b10100000000;                      // 0x500
2677
        12: polynom = 32'b100000101001;                     // 0x829
2678
        13: polynom = 32'b1000000001100;                    // 0x100C
2679
        14: polynom = 32'b10000000010101;                   // 0x2015
2680
        15: polynom = 32'b110000000000000;                  // 0x6000
2681
        16: polynom = 32'b1101000000001000;                 // 0xD008
2682
        17: polynom = 32'b10010000000000000;                // 0x12000
2683
        18: polynom = 32'b100000010000000000;               // 0x20400
2684
        19: polynom = 32'b1000000000000100011;              // 0x40023
2685 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2686 27 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2687
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2688
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2689
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2690
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2691
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2692
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2693
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2694
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2695
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2696
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2697
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2698
        default: polynom = 32'b0;
2699
        endcase
2700
        lfsr_fb = qi[length];
2701
        for (i=length-1; i>=1; i=i-1) begin
2702
            if (polynom[i])
2703
                lfsr_fb = lfsr_fb  ~^ qi[i];
2704
        end
2705
    end
2706
   assign q_next =  clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2707
 
2708
   always @ (posedge clk or posedge rst)
2709
     if (rst)
2710
       qi <= {length{1'b0}};
2711
     else
2712
     if (cke)
2713
       qi <= q_next;
2714
 
2715
   assign q = qi;
2716
 
2717
endmodule
2718 40 unneback
`endif
2719
`ifdef CNT_LFSR_CE_Q_ZQ
2720 27 unneback
//////////////////////////////////////////////////////////////////////
2721
////                                                              ////
2722
////  Versatile counter                                           ////
2723
////                                                              ////
2724
////  Description                                                 ////
2725
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2726
////  counter                                                     ////
2727
////                                                              ////
2728
////  To Do:                                                      ////
2729
////   - add LFSR with more taps                                  ////
2730
////                                                              ////
2731
////  Author(s):                                                  ////
2732
////      - Michael Unneback, unneback@opencores.org              ////
2733
////        ORSoC AB                                              ////
2734
////                                                              ////
2735
//////////////////////////////////////////////////////////////////////
2736
////                                                              ////
2737
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2738
////                                                              ////
2739
//// This source file may be used and distributed without         ////
2740
//// restriction provided that this copyright statement is not    ////
2741
//// removed from the file and that any derivative work contains  ////
2742
//// the original copyright notice and the associated disclaimer. ////
2743
////                                                              ////
2744
//// This source file is free software; you can redistribute it   ////
2745
//// and/or modify it under the terms of the GNU Lesser General   ////
2746
//// Public License as published by the Free Software Foundation; ////
2747
//// either version 2.1 of the License, or (at your option) any   ////
2748
//// later version.                                               ////
2749
////                                                              ////
2750
//// This source is distributed in the hope that it will be       ////
2751
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2752
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2753
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2754
//// details.                                                     ////
2755
////                                                              ////
2756
//// You should have received a copy of the GNU Lesser General    ////
2757
//// Public License along with this source; if not, download it   ////
2758
//// from http://www.opencores.org/lgpl.shtml                     ////
2759
////                                                              ////
2760
//////////////////////////////////////////////////////////////////////
2761
 
2762
// LFSR counter
2763 22 unneback
 
2764 40 unneback
`define MODULE cnt_lfsr_ce_q_zq
2765
module `BASE`MODULE (
2766
`undef MODULE
2767
 cke, q, zq, rst, clk);
2768
 
2769 22 unneback
   parameter length = 4;
2770
   input cke;
2771
   output [length:1] q;
2772
   output reg zq;
2773
   input rst;
2774
   input clk;
2775
 
2776
   parameter clear_value = 0;
2777
   parameter set_value = 1;
2778
   parameter wrap_value = 8;
2779
   parameter level1_value = 15;
2780
 
2781
   reg  [length:1] qi;
2782
   reg lfsr_fb;
2783
   wire [length:1] q_next;
2784
   reg [32:1] polynom;
2785
   integer i;
2786
 
2787
   always @ (qi)
2788
   begin
2789
        case (length)
2790
         2: polynom = 32'b11;                               // 0x3
2791
         3: polynom = 32'b110;                              // 0x6
2792
         4: polynom = 32'b1100;                             // 0xC
2793
         5: polynom = 32'b10100;                            // 0x14
2794
         6: polynom = 32'b110000;                           // 0x30
2795
         7: polynom = 32'b1100000;                          // 0x60
2796
         8: polynom = 32'b10111000;                         // 0xb8
2797
         9: polynom = 32'b100010000;                        // 0x110
2798
        10: polynom = 32'b1001000000;                       // 0x240
2799
        11: polynom = 32'b10100000000;                      // 0x500
2800
        12: polynom = 32'b100000101001;                     // 0x829
2801
        13: polynom = 32'b1000000001100;                    // 0x100C
2802
        14: polynom = 32'b10000000010101;                   // 0x2015
2803
        15: polynom = 32'b110000000000000;                  // 0x6000
2804
        16: polynom = 32'b1101000000001000;                 // 0xD008
2805
        17: polynom = 32'b10010000000000000;                // 0x12000
2806
        18: polynom = 32'b100000010000000000;               // 0x20400
2807
        19: polynom = 32'b1000000000000100011;              // 0x40023
2808 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2809