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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Blame information for rev 48

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Line No. Rev Author Line
1 40 unneback 
`ifndef BASE
2 
`define BASE vl_
3 
`endif
4 
 
5 44 unneback 
`ifdef ACTEL
6 
`define SYN_KEEP /*synthesis syn_keep = 1*/
7 
`endif
8 
 
9 40 unneback 
`ifdef ALL
10 
 
11 
`define GBUF
12 
`define SYNC_RST
13 
`define PLL
14 
 
15 
`define MULTS
16 
`define MULTS18X18
17 
`define MULT
18 
`define SHIFT_UNIT_32
19 
`define LOGIC_UNIT
20 
 
21 
`define CNT_SHREG_WRAP
22 
`define CNT_SHREG_CE_WRAP
23 
`define CNT_SHREG_CE_CLEAR
24 
`define CNT_SHREG_CE_CLEAR_WRAP
25 
 
26 
`define MUX_ANDOR
27 
`define MUX2_ANDOR
28 
`define MUX3_ANDOR
29 
`define MUX4_ANDOR
30 
`define MUX5_ANDOR
31 
`define MUX6_ANDOR
32 43 unneback 
`define PARITY
33 40 unneback 
 
34 
`define ROM_INIT
35 
`define RAM
36 
`define RAM_BE
37 
`define DPRAM_1R1W
38 
`define DPRAM_2R1W
39 
`define DPRAM_2R2W
40 
`define FIFO_1R1W_FILL_LEVEL_SYNC
41 
`define FIFO_2R2W_SYNC_SIMPLEX
42 
`define FIFO_CMP_ASYNC
43 
`define FIFO_1R1W_ASYNC
44 
`define FIFO_2R2W_ASYNC
45 
`define FIFO_2R2W_ASYNC_SIMPLEX
46 48 unneback 
`define REG_FILE
47 40 unneback 
 
48 
`define DFF
49 
`define DFF_ARRAY
50 
`define DFF_CE
51 
`define DFF_CE_CLEAR
52 
`define DF_CE_SET
53 
`define SPR
54 
`define SRP
55 
`define DFF_SR
56 
`define LATCH
57 
`define SHREG
58 
`define SHREG_CE
59 
`define DELAY
60 
`define DELAY_EMPTYFLAG
61 
 
62 
`define WB3WB3_BRIDGE
63 
`define WB3_ARBITER_TYPE1
64 48 unneback 
`define WB_B4_ROM
65 40 unneback 
`define WB_BOOT_ROM
66 
`define WB_DPRAM
67 
 
68 44 unneback 
`define IO_DFF_OE
69 
`define O_DFF
70 
 
71 40 unneback 
`endif
72 
 
73 
`ifdef PLL
74 
`ifndef SYNC_RST
75 
`define SYNC_RST
76 
`endif
77 
`endif
78 
 
79 
`ifdef SYNC_RST
80 
`ifndef GBUF
81 
`define GBUF
82 
`endif
83 
`endif
84 
 
85 
`ifdef WB_DPRAM
86 
`ifndef DPRAM_2R2W
87 
`define DPRAM_2R2W
88 
`endif
89 
`ifndef SPR
90 
`define SPR
91 
`endif
92 
`endif
93 
 
94 
`ifdef WB3_ARBITER_TYPE1
95 42 unneback 
`ifndef SPR
96 
`define SPR
97 
`endif
98 40 unneback 
`ifndef MUX_ANDOR
99 
`define MUX_ANDOR
100 
`endif
101 
`endif
102 
 
103 
`ifdef WB3WB3_BRIDGE
104 
`ifndef CNT_SHREG_CE_CLEAR
105 
`define CNT_SHREG_CE_CLEAR
106 
`endif
107 
`ifndef DFF
108 
`define DFF
109 
`endif
110 
`ifndef DFF_CE
111 
`define DFF_CE
112 
`endif
113 
`ifndef CNT_SHREG_CE_CLEAR
114 
`define CNT_SHREG_CE_CLEAR
115 
`endif
116 
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
117 
`define FIFO_2R2W_ASYNC_SIMPLEX
118 
`endif
119 
`endif
120 
 
121 
`ifdef MULTS18X18
122 
`ifndef MULTS
123 
`define MULTS
124 
`endif
125 
`endif
126 
 
127 
`ifdef SHIFT_UNIT_32
128 
`ifndef MULTS
129 
`define MULTS
130 
`endif
131 
`endif
132 
 
133 
`ifdef MUX2_ANDOR
134 
`ifndef MUX_ANDOR
135 
`define MUX_ANDOR
136 
`endif
137 
`endif
138 
 
139 
`ifdef MUX3_ANDOR
140 
`ifndef MUX_ANDOR
141 
`define MUX_ANDOR
142 
`endif
143 
`endif
144 
 
145 
`ifdef MUX4_ANDOR
146 
`ifndef MUX_ANDOR
147 
`define MUX_ANDOR
148 
`endif
149 
`endif
150 
 
151 
`ifdef MUX5_ANDOR
152 
`ifndef MUX_ANDOR
153 
`define MUX_ANDOR
154 
`endif
155 
`endif
156 
 
157 
`ifdef MUX6_ANDOR
158 
`ifndef MUX_ANDOR
159 
`define MUX_ANDOR
160 
`endif
161 
`endif
162 
 
163 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
164 
`ifndef CNT_BIN_CE
165 
`define CNT_BIN_CE
166 
`endif
167 
`ifndef DPRAM_1R1W
168 
`define DPRAM_1R1W
169 
`endif
170 
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
171 
`define CNT_BIN_CE_REW_Q_ZQ_L1
172 
`endif
173 
`endif
174 
 
175 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
176 
`ifndef CNT_LFSR_CE
177 
`define CNT_LFSR_CE
178 
`endif
179 
`ifndef DPRAM_2R2W
180 
`define DPRAM_2R2W
181 
`endif
182 
`ifndef CNT_BIN_CE_REW_ZQ_L1
183 
`define CNT_BIN_CE_REW_ZQ_L1
184 
`endif
185 
`endif
186 
 
187 
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
188 
`ifndef CNT_GRAY_CE_BIN
189 
`define CNT_GRAY_CE_BIN
190 
`endif
191 
`ifndef DPRAM_2R2W
192 
`define DPRAM_2R2W
193 
`endif
194 
`ifndef FIFO_CMP_ASYNC
195 
`define FIFO_CMP_ASYNC
196 
`endif
197 
`endif
198 
 
199 
`ifdef FIFO_2R2W_ASYNC
200 
`ifndef FIFO_1R1W_ASYNC
201 
`define FIFO_1R1W_ASYNC
202 
`endif
203 
`endif
204 
 
205 
`ifdef FIFO_1R1W_ASYNC
206 
`ifndef CNT_GRAY_CE_BIN
207 
`define CNT_GRAY_CE_BIN
208 
`endif
209 
`ifndef DPRAM_1R1W
210 
`define DPRAM_1R1W
211 
`endif
212 
`ifndef FIFO_CMP_ASYNC
213 
`define FIFO_CMP_ASYNC
214 
`endif
215 
`endif
216 
 
217 
`ifdef FIFO_CMP_ASYNC
218 
`ifndef DFF_SR
219 
`define DFF_SR
220 
`endif
221 
`ifndef DFF
222 
`define DFF
223 
`endif
224 
`endif
225 48 unneback 
 
226 
`ifdef REG_FILE
227 
`ifndef DPRAM_1R1W
228 
`define DPRAM_1R1W
229 
`endif
230 
`endif
231 6 unneback 
//////////////////////////////////////////////////////////////////////
232 
////                                                              ////
233 
////  Versatile library, clock and reset                          ////
234 
////                                                              ////
235 
////  Description                                                 ////
236 
////  Logic related to clock and reset                            ////
237 
////                                                              ////
238 
////                                                              ////
239 
////  To Do:                                                      ////
240 
////   - add more different registers                             ////
241 
////                                                              ////
242 
////  Author(s):                                                  ////
243 
////      - Michael Unneback, unneback@opencores.org              ////
244 
////        ORSoC AB                                              ////
245 
////                                                              ////
246 
//////////////////////////////////////////////////////////////////////
247 
////                                                              ////
248 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
249 
////                                                              ////
250 
//// This source file may be used and distributed without         ////
251 
//// restriction provided that this copyright statement is not    ////
252 
//// removed from the file and that any derivative work contains  ////
253 
//// the original copyright notice and the associated disclaimer. ////
254 
////                                                              ////
255 
//// This source file is free software; you can redistribute it   ////
256 
//// and/or modify it under the terms of the GNU Lesser General   ////
257 
//// Public License as published by the Free Software Foundation; ////
258 
//// either version 2.1 of the License, or (at your option) any   ////
259 
//// later version.                                               ////
260 
////                                                              ////
261 
//// This source is distributed in the hope that it will be       ////
262 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
263 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
264 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
265 
//// details.                                                     ////
266 
////                                                              ////
267 
//// You should have received a copy of the GNU Lesser General    ////
268 
//// Public License along with this source; if not, download it   ////
269 
//// from http://www.opencores.org/lgpl.shtml                     ////
270 
////                                                              ////
271 
//////////////////////////////////////////////////////////////////////
272 
 
273 48 unneback 
`ifdef ACTEL
274 
`ifdef GBUF
275 
`timescale 1 ns/100 ps
276 6 unneback 
// Global buffer
277 
// usage:
278 
// use to enable global buffers for high fan out signals such as clock and reset
279 
// Version: 8.4 8.4.0.33
280 
module gbuf(GL,CLK);
281 
output GL;
282 
input  CLK;
283 
 
284 
    wire GND;
285 
 
286 
    GND GND_1_net(.Y(GND));
287 
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
288 
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
289 
 
290 
endmodule
291 
`timescale 1 ns/1 ns
292 40 unneback 
`define MODULE gbuf
293 
module `BASE`MODULE ( i, o);
294 
`undef MODULE
295 6 unneback 
input i;
296 
output o;
297 
`ifdef SIM_GBUF
298 
assign o=i;
299 
`else
300 
gbuf gbuf_i0 ( .CLK(i), .GL(o));
301 
`endif
302 
endmodule
303 40 unneback 
`endif
304 33 unneback 
 
305 6 unneback 
`else
306 33 unneback 
 
307 40 unneback 
`ifdef ALTERA
308 
`ifdef GBUF
309 21 unneback 
//altera
310 40 unneback 
`define MODULE gbuf
311 
module `BASE`MODULE ( i, o);
312 
`undef MODULE
313 33 unneback 
input i;
314 
output o;
315 
assign o = i;
316 
endmodule
317 40 unneback 
`endif
318 33 unneback 
 
319 6 unneback 
`else
320 
 
321 40 unneback 
`ifdef GBUF
322 6 unneback 
`timescale 1 ns/100 ps
323 40 unneback 
`define MODULE
324 
module `BASE`MODULE ( i, o);
325 
`undef MODULE
326 6 unneback 
input i;
327 
output o;
328 
assign o = i;
329 
endmodule
330 40 unneback 
`endif
331 6 unneback 
`endif // ALTERA
332 
`endif //ACTEL
333 
 
334 40 unneback 
`ifdef SYNC_RST
335 6 unneback 
// sync reset
336 17 unneback 
// input active lo async reset, normally from external reset generator and/or switch
337 6 unneback 
// output active high global reset sync with two DFFs
338 
`timescale 1 ns/100 ps
339 40 unneback 
`define MODULE sync_rst
340 
module `BASE`MODULE ( rst_n_i, rst_o, clk);
341 
`undef MODULE
342 6 unneback 
input rst_n_i, clk;
343 
output rst_o;
344 18 unneback 
reg [1:0] tmp;
345 6 unneback 
always @ (posedge clk or negedge rst_n_i)
346 
if (!rst_n_i)
347 17 unneback 
        tmp <= 2'b11;
348 6 unneback 
else
349 33 unneback 
        tmp <= {1'b0,tmp[1]};
350 40 unneback 
`define MODULE gbuf
351 
`BASE`MODULE buf_i0( .i(tmp[0]), .o(rst_o));
352 
`undef MODULE
353 6 unneback 
endmodule
354 40 unneback 
`endif
355 6 unneback 
 
356 40 unneback 
`ifdef PLL
357 6 unneback 
// vl_pll
358 
`ifdef ACTEL
359 32 unneback 
///////////////////////////////////////////////////////////////////////////////
360 17 unneback 
`timescale 1 ps/1 ps
361 40 unneback 
`define MODULE pll
362 
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
363 
`undef MODULE
364 6 unneback 
parameter index = 0;
365 
parameter number_of_clk = 1;
366 17 unneback 
parameter period_time_0 = 20000;
367 
parameter period_time_1 = 20000;
368 
parameter period_time_2 = 20000;
369 
parameter lock_delay = 2000000;
370 6 unneback 
input clk_i, rst_n_i;
371 
output lock;
372 
output reg [0:number_of_clk-1] clk_o;
373 
output [0:number_of_clk-1] rst_o;
374 
 
375 
`ifdef SIM_PLL
376 
 
377 
always
378 
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
379 
 
380 
generate if (number_of_clk > 1)
381 
always
382 
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
383 
endgenerate
384 
 
385 
generate if (number_of_clk > 2)
386 
always
387 
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
388 
endgenerate
389 
 
390 
genvar i;
391 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
392 
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
393 
end
394 
endgenerate
395 
 
396 
assign #lock_delay lock = rst_n_i;
397 
 
398 
endmodule
399 
`else
400 
generate if (number_of_clk==1 & index==0) begin
401 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
402 
end
403 
endgenerate // index==0
404 
generate if (number_of_clk==1 & index==1) begin
405 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
406 
end
407 
endgenerate // index==1
408 
generate if (number_of_clk==1 & index==2) begin
409 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
410 
end
411 
endgenerate // index==2
412 
generate if (number_of_clk==1 & index==3) begin
413 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
414 
end
415 
endgenerate // index==0
416 
 
417 
generate if (number_of_clk==2 & index==0) begin
418 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
419 
end
420 
endgenerate // index==0
421 
generate if (number_of_clk==2 & index==1) begin
422 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
423 
end
424 
endgenerate // index==1
425 
generate if (number_of_clk==2 & index==2) begin
426 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
427 
end
428 
endgenerate // index==2
429 
generate if (number_of_clk==2 & index==3) begin
430 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
431 
end
432 
endgenerate // index==0
433 
 
434 
generate if (number_of_clk==3 & index==0) begin
435 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
436 
end
437 
endgenerate // index==0
438 
generate if (number_of_clk==3 & index==1) begin
439 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
440 
end
441 
endgenerate // index==1
442 
generate if (number_of_clk==3 & index==2) begin
443 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
444 
end
445 
endgenerate // index==2
446 
generate if (number_of_clk==3 & index==3) begin
447 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
448 
end
449 
endgenerate // index==0
450 
 
451 
genvar i;
452 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
453 40 unneback 
`define MODULE sync_rst
454 
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
455 
`undef MODULE
456 6 unneback 
end
457 
endgenerate
458 
endmodule
459 
`endif
460 32 unneback 
///////////////////////////////////////////////////////////////////////////////
461 6 unneback 
 
462 
`else
463 
 
464 32 unneback 
///////////////////////////////////////////////////////////////////////////////
465 6 unneback 
`ifdef ALTERA
466 
 
467 32 unneback 
`timescale 1 ps/1 ps
468 40 unneback 
`define MODULE pll
469 
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
470 
`undef MODULE
471 32 unneback 
parameter index = 0;
472 
parameter number_of_clk = 1;
473 
parameter period_time_0 = 20000;
474 
parameter period_time_1 = 20000;
475 
parameter period_time_2 = 20000;
476 
parameter period_time_3 = 20000;
477 
parameter period_time_4 = 20000;
478 
parameter lock_delay = 2000000;
479 
input clk_i, rst_n_i;
480 
output lock;
481 
output reg [0:number_of_clk-1] clk_o;
482 
output [0:number_of_clk-1] rst_o;
483 
 
484 
`ifdef SIM_PLL
485 
 
486 
always
487 
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
488 
 
489 
generate if (number_of_clk > 1)
490 
always
491 
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
492 
endgenerate
493 
 
494 
generate if (number_of_clk > 2)
495 
always
496 
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
497 
endgenerate
498 
 
499 33 unneback 
generate if (number_of_clk > 3)
500 32 unneback 
always
501 
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
502 
endgenerate
503 
 
504 33 unneback 
generate if (number_of_clk > 4)
505 32 unneback 
always
506 
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
507 
endgenerate
508 
 
509 
genvar i;
510 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
511 
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
512 
end
513 
endgenerate
514 
 
515 33 unneback 
//assign #lock_delay lock = rst_n_i;
516 
assign lock = rst_n_i;
517 32 unneback 
 
518 
endmodule
519 6 unneback 
`else
520 
 
521 33 unneback 
`ifdef VL_PLL0
522 
`ifdef VL_PLL0_CLK1
523 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
524 
`endif
525 
`ifdef VL_PLL0_CLK2
526 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
527 
`endif
528 
`ifdef VL_PLL0_CLK3
529 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
530 
`endif
531 
`ifdef VL_PLL0_CLK4
532 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
533 
`endif
534 
`ifdef VL_PLL0_CLK5
535 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
536 
`endif
537 
`endif
538 32 unneback 
 
539 33 unneback 
`ifdef VL_PLL1
540 
`ifdef VL_PLL1_CLK1
541 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
542 
`endif
543 
`ifdef VL_PLL1_CLK2
544 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
545 
`endif
546 
`ifdef VL_PLL1_CLK3
547 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
548 
`endif
549 
`ifdef VL_PLL1_CLK4
550 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
551 
`endif
552 
`ifdef VL_PLL1_CLK5
553 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
554 
`endif
555 
`endif
556 32 unneback 
 
557 33 unneback 
`ifdef VL_PLL2
558 
`ifdef VL_PLL2_CLK1
559 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
560 
`endif
561 
`ifdef VL_PLL2_CLK2
562 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
563 
`endif
564 
`ifdef VL_PLL2_CLK3
565 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
566 
`endif
567 
`ifdef VL_PLL2_CLK4
568 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
569 
`endif
570 
`ifdef VL_PLL2_CLK5
571 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
572 
`endif
573 
`endif
574 32 unneback 
 
575 33 unneback 
`ifdef VL_PLL3
576 
`ifdef VL_PLL3_CLK1
577 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
578 
`endif
579 
`ifdef VL_PLL3_CLK2
580 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
581 
`endif
582 
`ifdef VL_PLL3_CLK3
583 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
584 
`endif
585 
`ifdef VL_PLL3_CLK4
586 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
587 
`endif
588 
`ifdef VL_PLL3_CLK5
589 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
590 
`endif
591 
`endif
592 32 unneback 
 
593 
genvar i;
594 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
595 40 unneback 
`define MODULE sync_rst
596 
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
597 
`undef MODULE
598 32 unneback 
end
599 
endgenerate
600 
endmodule
601 
`endif
602 
///////////////////////////////////////////////////////////////////////////////
603 
 
604 
`else
605 
 
606 6 unneback 
// generic PLL
607 17 unneback 
`timescale 1 ps/1 ps
608 40 unneback 
`define MODULE pll
609 
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
610 
`undef MODULE
611 6 unneback 
parameter index = 0;
612 
parameter number_of_clk = 1;
613 17 unneback 
parameter period_time_0 = 20000;
614 
parameter period_time_1 = 20000;
615 
parameter period_time_2 = 20000;
616 6 unneback 
parameter lock_delay = 2000;
617 
input clk_i, rst_n_i;
618 
output lock;
619 
output reg [0:number_of_clk-1] clk_o;
620 
output [0:number_of_clk-1] rst_o;
621 
 
622 
always
623 
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
624 
 
625 
generate if (number_of_clk > 1)
626 
always
627 
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
628 
endgenerate
629 
 
630 
generate if (number_of_clk > 2)
631 
always
632 
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
633 
endgenerate
634 
 
635 
genvar i;
636 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
637 40 unneback 
`define MODULE sync_rst
638 
     `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
639 
`undef MODULE
640 6 unneback 
end
641 
endgenerate
642 
 
643 
assign #lock_delay lock = rst_n_i;
644 
 
645 
endmodule
646 
 
647 
`endif //altera
648 17 unneback 
`endif //actel
649 40 unneback 
`undef MODULE
650 
`endif//////////////////////////////////////////////////////////////////////
651 6 unneback 
////                                                              ////
652 
////  Versatile library, registers                                ////
653 
////                                                              ////
654 
////  Description                                                 ////
655 
////  Different type of registers                                 ////
656 
////                                                              ////
657 
////                                                              ////
658 
////  To Do:                                                      ////
659 
////   - add more different registers                             ////
660 
////                                                              ////
661 
////  Author(s):                                                  ////
662 
////      - Michael Unneback, unneback@opencores.org              ////
663 
////        ORSoC AB                                              ////
664 
////                                                              ////
665 
//////////////////////////////////////////////////////////////////////
666 
////                                                              ////
667 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
668 
////                                                              ////
669 
//// This source file may be used and distributed without         ////
670 
//// restriction provided that this copyright statement is not    ////
671 
//// removed from the file and that any derivative work contains  ////
672 
//// the original copyright notice and the associated disclaimer. ////
673 
////                                                              ////
674 
//// This source file is free software; you can redistribute it   ////
675 
//// and/or modify it under the terms of the GNU Lesser General   ////
676 
//// Public License as published by the Free Software Foundation; ////
677 
//// either version 2.1 of the License, or (at your option) any   ////
678 
//// later version.                                               ////
679 
////                                                              ////
680 
//// This source is distributed in the hope that it will be       ////
681 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
682 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
683 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
684 
//// details.                                                     ////
685 
////                                                              ////
686 
//// You should have received a copy of the GNU Lesser General    ////
687 
//// Public License along with this source; if not, download it   ////
688 
//// from http://www.opencores.org/lgpl.shtml                     ////
689 
////                                                              ////
690 
//////////////////////////////////////////////////////////////////////
691 
 
692 40 unneback 
`ifdef DFF
693 
`define MODULE dff
694 
module `BASE`MODULE ( d, q, clk, rst);
695 
`undef MODULE
696 6 unneback 
        parameter width = 1;
697 
        parameter reset_value = 0;
698 
 
699 
        input [width-1:0] d;
700 
        input clk, rst;
701 
        output reg [width-1:0] q;
702 
 
703 
        always @ (posedge clk or posedge rst)
704 
        if (rst)
705 
                q <= reset_value;
706 
        else
707 
                q <= d;
708 
 
709 
endmodule
710 40 unneback 
`endif
711 6 unneback 
 
712 40 unneback 
`ifdef DFF_ARRAY
713 
`define MODULE dff_array
714 
module `BASE`MODULE ( d, q, clk, rst);
715 
`undef MODULE
716 6 unneback 
 
717 
        parameter width = 1;
718 
        parameter depth = 2;
719 
        parameter reset_value = 1'b0;
720 
 
721 
        input [width-1:0] d;
722 
        input clk, rst;
723 
        output [width-1:0] q;
724 
        reg  [0:depth-1] q_tmp [width-1:0];
725 
        integer i;
726 
        always @ (posedge clk or posedge rst)
727 
        if (rst) begin
728 
            for (i=0;i<depth;i=i+1)
729 
                q_tmp[i] <= {width{reset_value}};
730 
        end else begin
731 
            q_tmp[0] <= d;
732 
            for (i=1;i<depth;i=i+1)
733 
                q_tmp[i] <= q_tmp[i-1];
734 
        end
735 
 
736 
    assign q = q_tmp[depth-1];
737 
 
738 
endmodule
739 40 unneback 
`endif
740 6 unneback 
 
741 40 unneback 
`ifdef DFF_CE
742 
`define MODULE dff_ce
743 
module `BASE`MODULE ( d, ce, q, clk, rst);
744 
`undef MODULE
745 6 unneback 
 
746 
        parameter width = 1;
747 
        parameter reset_value = 0;
748 
 
749 
        input [width-1:0] d;
750 
        input ce, clk, rst;
751 
        output reg [width-1:0] q;
752 
 
753 
        always @ (posedge clk or posedge rst)
754 
        if (rst)
755 
                q <= reset_value;
756 
        else
757 
                if (ce)
758 
                        q <= d;
759 
 
760 
endmodule
761 40 unneback 
`endif
762 6 unneback 
 
763 40 unneback 
`ifdef DFF_CE_CLEAR
764 
`define MODULE dff_ce_clear
765 
module `BASE`MODULE ( d, ce, clear, q, clk, rst);
766 
`undef MODULE
767 8 unneback 
 
768 
        parameter width = 1;
769 
        parameter reset_value = 0;
770 
 
771 
        input [width-1:0] d;
772 10 unneback 
        input ce, clear, clk, rst;
773 8 unneback 
        output reg [width-1:0] q;
774 
 
775 
        always @ (posedge clk or posedge rst)
776 
        if (rst)
777 
            q <= reset_value;
778 
        else
779 
            if (ce)
780 
                if (clear)
781 
                    q <= {width{1'b0}};
782 
                else
783 
                    q <= d;
784 
 
785 
endmodule
786 40 unneback 
`endif
787 8 unneback 
 
788 40 unneback 
`ifdef DF_CE_SET
789 
`define MODULE dff_ce_set
790 
module `BASE`MODULE ( d, ce, set, q, clk, rst);
791 
`undef MODULE
792 24 unneback 
 
793 
        parameter width = 1;
794 
        parameter reset_value = 0;
795 
 
796 
        input [width-1:0] d;
797 
        input ce, set, clk, rst;
798 
        output reg [width-1:0] q;
799 
 
800 
        always @ (posedge clk or posedge rst)
801 
        if (rst)
802 
            q <= reset_value;
803 
        else
804 
            if (ce)
805 
                if (set)
806 
                    q <= {width{1'b1}};
807 
                else
808 
                    q <= d;
809 
 
810 
endmodule
811 40 unneback 
`endif
812 24 unneback 
 
813 40 unneback 
`ifdef SPR
814 
`define MODULE spr
815 
module `BASE`MODULE ( sp, r, q, clk, rst);
816 
`undef MODULE
817 
 
818 29 unneback 
        parameter width = 1;
819 
        parameter reset_value = 0;
820 
 
821 
        input sp, r;
822 
        output reg q;
823 
        input clk, rst;
824 
 
825 
        always @ (posedge clk or posedge rst)
826 
        if (rst)
827 
            q <= reset_value;
828 
        else
829 
            if (sp)
830 
                q <= 1'b1;
831 
            else if (r)
832 
                q <= 1'b0;
833 
 
834 
endmodule
835 40 unneback 
`endif
836 29 unneback 
 
837 40 unneback 
`ifdef SRP
838 
`define MODULE srp
839 
module `BASE`MODULE ( s, rp, q, clk, rst);
840 
`undef MODULE
841 
 
842 29 unneback 
        parameter width = 1;
843 
        parameter reset_value = 0;
844 
 
845 
        input s, rp;
846 
        output reg q;
847 
        input clk, rst;
848 
 
849 
        always @ (posedge clk or posedge rst)
850 
        if (rst)
851 
            q <= reset_value;
852 
        else
853 
            if (rp)
854 
                q <= 1'b0;
855 
            else if (s)
856 
                q <= 1'b1;
857 
 
858 
endmodule
859 40 unneback 
`endif
860 29 unneback 
 
861 40 unneback 
`ifdef ALTERA
862 29 unneback 
 
863 40 unneback 
`ifdef DFF_SR
864 6 unneback 
// megafunction wizard: %LPM_FF%
865 
// GENERATION: STANDARD
866 
// VERSION: WM1.0
867 
// MODULE: lpm_ff
868 
 
869 
// ============================================================
870 
// File Name: dff_sr.v
871 
// Megafunction Name(s):
872 
//                      lpm_ff
873 
//
874 
// Simulation Library Files(s):
875 
//                      lpm
876 
// ============================================================
877 
// ************************************************************
878 
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
879 
//
880 
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
881 
// ************************************************************
882 
 
883 
 
884 
//Copyright (C) 1991-2010 Altera Corporation
885 
//Your use of Altera Corporation's design tools, logic functions
886 
//and other software and tools, and its AMPP partner logic
887 
//functions, and any output files from any of the foregoing
888 
//(including device programming or simulation files), and any
889 
//associated documentation or information are expressly subject
890 
//to the terms and conditions of the Altera Program License
891 
//Subscription Agreement, Altera MegaCore Function License
892 
//Agreement, or other applicable license agreement, including,
893 
//without limitation, that your use is for the sole purpose of
894 
//programming logic devices manufactured by Altera and sold by
895 
//Altera or its authorized distributors.  Please refer to the
896 
//applicable agreement for further details.
897 
 
898 
 
899 
// synopsys translate_off
900 
`timescale 1 ps / 1 ps
901 
// synopsys translate_on
902 40 unneback 
`define MODULE dff_sr
903 
module `BASE`MODULE (
904 
`undef MODULE
905 
 
906 6 unneback 
        aclr,
907 
        aset,
908 
        clock,
909 
        data,
910 
        q);
911 
 
912 
        input     aclr;
913 
        input     aset;
914 
        input     clock;
915 
        input     data;
916 
        output    q;
917 
 
918 
        wire [0:0] sub_wire0;
919 
        wire [0:0] sub_wire1 = sub_wire0[0:0];
920 
        wire  q = sub_wire1;
921 
        wire  sub_wire2 = data;
922 
        wire  sub_wire3 = sub_wire2;
923 
 
924 
        lpm_ff  lpm_ff_component (
925 
                                .aclr (aclr),
926 
                                .clock (clock),
927 
                                .data (sub_wire3),
928 
                                .aset (aset),
929 
                                .q (sub_wire0)
930 
                                // synopsys translate_off
931 
                                ,
932 
                                .aload (),
933 
                                .enable (),
934 
                                .sclr (),
935 
                                .sload (),
936 
                                .sset ()
937 
                                // synopsys translate_on
938 
                                );
939 
        defparam
940 
                lpm_ff_component.lpm_fftype = "DFF",
941 
                lpm_ff_component.lpm_type = "LPM_FF",
942 
                lpm_ff_component.lpm_width = 1;
943 
 
944 
 
945 
endmodule
946 
 
947 
// ============================================================
948 
// CNX file retrieval info
949 
// ============================================================
950 
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
951 
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
952 
// Retrieval info: PRIVATE: ASET NUMERIC "1"
953 
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
954 
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
955 
// Retrieval info: PRIVATE: DFF NUMERIC "1"
956 
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
957 
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
958 
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
959 
// Retrieval info: PRIVATE: SSET NUMERIC "0"
960 
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
961 
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
962 
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
963 
// Retrieval info: PRIVATE: nBit NUMERIC "1"
964 
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
965 
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
966 
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
967 
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
968 
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
969 
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
970 
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
971 
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
972 
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
973 
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
974 
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
975 
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
976 
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
977 
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
978 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
979 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
980 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
981 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
982 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
983 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
984 
// Retrieval info: LIB_FILE: lpm
985 40 unneback 
`endif
986 6 unneback 
 
987 
`else
988 
 
989 40 unneback 
`ifdef DFF_SR
990 
`define MODULE dff_sr
991 
module `BASE`MODULE ( aclr, aset, clock, data, q);
992 
`undef MODULE
993 6 unneback 
 
994 
    input         aclr;
995 
    input         aset;
996 
    input         clock;
997 
    input         data;
998 
    output reg    q;
999 
 
1000 
   always @ (posedge clock or posedge aclr or posedge aset)
1001 
     if (aclr)
1002 
       q <= 1'b0;
1003 
     else if (aset)
1004 
       q <= 1'b1;
1005 
     else
1006 
       q <= data;
1007 
 
1008 
endmodule
1009 40 unneback 
`endif
1010 6 unneback 
 
1011 
`endif
1012 
 
1013 
// LATCH
1014 
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
1015 
`ifdef ALTERA
1016 40 unneback 
 
1017 
`ifdef LATCH
1018 
`define MODULE latch
1019 
module `BASE`MODULE ( d, le, q, clk);
1020 
`undef MODULE
1021 6 unneback 
input d, le;
1022 
output q;
1023 
input clk;
1024 
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
1025 
endmodule
1026 40 unneback 
`endif
1027 
 
1028 6 unneback 
`else
1029 40 unneback 
 
1030 
`ifdef LATCH
1031 
`define MODULE latch
1032 
module `BASE`MODULE ( d, le, q, clk);
1033 
`undef MODULE
1034 6 unneback 
input d, le;
1035 48 unneback 
input clk;
1036 
always @ (le or d)
1037 
if le
1038 
    d <= q;
1039 6 unneback 
endmodule
1040 15 unneback 
`endif
1041 
 
1042 40 unneback 
`endif
1043 
 
1044 
`ifdef SHREG
1045 
`define MODULE shreg
1046 
module `BASE`MODULE ( d, q, clk, rst);
1047 
`undef MODULE
1048 
 
1049 17 unneback 
parameter depth = 10;
1050 
input d;
1051 
output q;
1052 
input clk, rst;
1053 
 
1054 
reg [1:depth] dffs;
1055 
 
1056 
always @ (posedge clk or posedge rst)
1057 
if (rst)
1058 
    dffs <= {depth{1'b0}};
1059 
else
1060 
    dffs <= {d,dffs[1:depth-1]};
1061 
assign q = dffs[depth];
1062 
endmodule
1063 40 unneback 
`endif
1064 17 unneback 
 
1065 40 unneback 
`ifdef SHREG_CE
1066 
`define MODULE shreg_ce
1067 
module `BASE`MODULE ( d, ce, q, clk, rst);
1068 
`undef MODULE
1069 17 unneback 
parameter depth = 10;
1070 
input d, ce;
1071 
output q;
1072 
input clk, rst;
1073 
 
1074 
reg [1:depth] dffs;
1075 
 
1076 
always @ (posedge clk or posedge rst)
1077 
if (rst)
1078 
    dffs <= {depth{1'b0}};
1079 
else
1080 
    if (ce)
1081 
        dffs <= {d,dffs[1:depth-1]};
1082 
assign q = dffs[depth];
1083 
endmodule
1084 40 unneback 
`endif
1085 17 unneback 
 
1086 40 unneback 
`ifdef DELAY
1087 
`define MODULE delay
1088 
module `BASE`MODULE ( d, q, clk, rst);
1089 
`undef MODULE
1090 15 unneback 
parameter depth = 10;
1091 
input d;
1092 
output q;
1093 
input clk, rst;
1094 
 
1095 
reg [1:depth] dffs;
1096 
 
1097 
always @ (posedge clk or posedge rst)
1098 
if (rst)
1099 
    dffs <= {depth{1'b0}};
1100 
else
1101 
    dffs <= {d,dffs[1:depth-1]};
1102 
assign q = dffs[depth];
1103 17 unneback 
endmodule
1104 40 unneback 
`endif
1105 17 unneback 
 
1106 40 unneback 
`ifdef DELAY_EMPTYFLAG
1107 
`define MODULE delay_emptyflag
1108 41 unneback 
module `BASE`MODULE ( d, q, emptyflag, clk, rst);
1109 40 unneback 
`undef MODULE
1110 17 unneback 
parameter depth = 10;
1111 
input d;
1112 
output q, emptyflag;
1113 
input clk, rst;
1114 
 
1115 
reg [1:depth] dffs;
1116 
 
1117 
always @ (posedge clk or posedge rst)
1118 
if (rst)
1119 
    dffs <= {depth{1'b0}};
1120 
else
1121 
    dffs <= {d,dffs[1:depth-1]};
1122 
assign q = dffs[depth];
1123 
assign emptyflag = !(|dffs);
1124 
endmodule
1125 40 unneback 
`endif
1126 17 unneback 
//////////////////////////////////////////////////////////////////////
1127 6 unneback 
////                                                              ////
1128 18 unneback 
////  Logic functions                                             ////
1129 
////                                                              ////
1130 
////  Description                                                 ////
1131 
////  Logic functions such as multiplexers                        ////
1132 
////                                                              ////
1133 
////                                                              ////
1134 
////  To Do:                                                      ////
1135 
////   -                                                          ////
1136 
////                                                              ////
1137 
////  Author(s):                                                  ////
1138 
////      - Michael Unneback, unneback@opencores.org              ////
1139 
////        ORSoC AB                                              ////
1140 
////                                                              ////
1141 
//////////////////////////////////////////////////////////////////////
1142 
////                                                              ////
1143 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1144 
////                                                              ////
1145 
//// This source file may be used and distributed without         ////
1146 
//// restriction provided that this copyright statement is not    ////
1147 
//// removed from the file and that any derivative work contains  ////
1148 
//// the original copyright notice and the associated disclaimer. ////
1149 
////                                                              ////
1150 
//// This source file is free software; you can redistribute it   ////
1151 
//// and/or modify it under the terms of the GNU Lesser General   ////
1152 
//// Public License as published by the Free Software Foundation; ////
1153 
//// either version 2.1 of the License, or (at your option) any   ////
1154 
//// later version.                                               ////
1155 
////                                                              ////
1156 
//// This source is distributed in the hope that it will be       ////
1157 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1158 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1159 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1160 
//// details.                                                     ////
1161 
////                                                              ////
1162 
//// You should have received a copy of the GNU Lesser General    ////
1163 
//// Public License along with this source; if not, download it   ////
1164 
//// from http://www.opencores.org/lgpl.shtml                     ////
1165 
////                                                              ////
1166 
//////////////////////////////////////////////////////////////////////
1167 40 unneback 
`ifdef MUX_ANDOR
1168 
`define MODULE mux_andor
1169 
module `BASE`MODULE ( a, sel, dout);
1170 
`undef MODULE
1171 36 unneback 
 
1172 
parameter width = 32;
1173 
parameter nr_of_ports = 4;
1174 
 
1175 
input [nr_of_ports*width-1:0] a;
1176 
input [nr_of_ports-1:0] sel;
1177 
output reg [width-1:0] dout;
1178 
 
1179 38 unneback 
integer i,j;
1180 
 
1181 36 unneback 
always @ (a, sel)
1182 
begin
1183 
    dout = a[width-1:0] & {width{sel[0]}};
1184 42 unneback 
    for (i=1;i<nr_of_ports;i=i+1)
1185 
        for (j=0;j<width;j=j+1)
1186 
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
1187 36 unneback 
end
1188 
 
1189 
endmodule
1190 40 unneback 
`endif
1191 36 unneback 
 
1192 40 unneback 
`ifdef MUX2_ANDOR
1193 
`define MODULE mux2_andor
1194 
module `BASE`MODULE ( a1, a0, sel, dout);
1195 
`undef MODULE
1196 18 unneback 
 
1197 34 unneback 
parameter width = 32;
1198 35 unneback 
localparam nr_of_ports = 2;
1199 34 unneback 
input [width-1:0] a1, a0;
1200 
input [nr_of_ports-1:0] sel;
1201 
output [width-1:0] dout;
1202 
 
1203 40 unneback 
`define MODULE mux_andor
1204 
`BASE`MODULE
1205 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1206 36 unneback 
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
1207 40 unneback 
`undef MODULE
1208 
 
1209 34 unneback 
endmodule
1210 40 unneback 
`endif
1211 34 unneback 
 
1212 40 unneback 
`ifdef MUX3_ANDOR
1213 
`define MODULE mux3_andor
1214 
module `BASE`MODULE ( a2, a1, a0, sel, dout);
1215 
`undef MODULE
1216 34 unneback 
 
1217 
parameter width = 32;
1218 35 unneback 
localparam nr_of_ports = 3;
1219 34 unneback 
input [width-1:0] a2, a1, a0;
1220 
input [nr_of_ports-1:0] sel;
1221 
output [width-1:0] dout;
1222 
 
1223 40 unneback 
`define MODULE mux_andor
1224 
`BASE`MODULE
1225 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1226 36 unneback 
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
1227 40 unneback 
`undef MODULE
1228 34 unneback 
endmodule
1229 40 unneback 
`endif
1230 34 unneback 
 
1231 40 unneback 
`ifdef MUX4_ANDOR
1232 
`define MODULE mux4_andor
1233 
module `BASE`MODULE ( a3, a2, a1, a0, sel, dout);
1234 
`undef MODULE
1235 18 unneback 
 
1236 
parameter width = 32;
1237 35 unneback 
localparam nr_of_ports = 4;
1238 18 unneback 
input [width-1:0] a3, a2, a1, a0;
1239 
input [nr_of_ports-1:0] sel;
1240 22 unneback 
output [width-1:0] dout;
1241 18 unneback 
 
1242 40 unneback 
`define MODULE mux_andor
1243 
`BASE`MODULE
1244 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1245 36 unneback 
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
1246 40 unneback 
`undef MODULE
1247 18 unneback 
 
1248 
endmodule
1249 40 unneback 
`endif
1250 18 unneback 
 
1251 40 unneback 
`ifdef MUX5_ANDOR
1252 
`define MODULE mux5_andor
1253 
module `BASE`MODULE ( a4, a3, a2, a1, a0, sel, dout);
1254 
`undef MODULE
1255 18 unneback 
 
1256 
parameter width = 32;
1257 35 unneback 
localparam nr_of_ports = 5;
1258 18 unneback 
input [width-1:0] a4, a3, a2, a1, a0;
1259 
input [nr_of_ports-1:0] sel;
1260 22 unneback 
output [width-1:0] dout;
1261 18 unneback 
 
1262 40 unneback 
`define MODULE mux_andor
1263 
`BASE`MODULE
1264 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1265 36 unneback 
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1266 40 unneback 
`undef MODULE
1267 18 unneback 
 
1268 
endmodule
1269 40 unneback 
`endif
1270 18 unneback 
 
1271 40 unneback 
`ifdef MUX6_ANDOR
1272 
`define MODULE mux6_andor
1273 
module `BASE`MODULE ( a5, a4, a3, a2, a1, a0, sel, dout);
1274 
`undef MODULE
1275 18 unneback 
 
1276 
parameter width = 32;
1277 35 unneback 
localparam nr_of_ports = 6;
1278 18 unneback 
input [width-1:0] a5, a4, a3, a2, a1, a0;
1279 
input [nr_of_ports-1:0] sel;
1280 22 unneback 
output [width-1:0] dout;
1281 18 unneback 
 
1282 40 unneback 
`define MODULE mux_andor
1283 
`BASE`MODULE
1284 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1285 36 unneback 
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1286 40 unneback 
`undef MODULE
1287 18 unneback 
 
1288 
endmodule
1289 40 unneback 
`endif
1290 43 unneback 
 
1291 
`ifdef PARITY
1292 
 
1293 
`define MODULE parity_generate
1294 
module `BASE`MODULE (data, parity);
1295 
`undef MODULE
1296 
parameter word_size = 32;
1297 
parameter chunk_size = 8;
1298 
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1299 
input [word_size-1:0] data;
1300 
output reg [word_size/chunk_size-1:0] parity;
1301 
integer i,j;
1302 
always @ (data)
1303 
for (i=0;i<word_size/chunk_size;i=i+1) begin
1304 
    parity[i] = parity_type;
1305 
    for (j=0;j<chunk_size;j=j+1) begin
1306 46 unneback 
        parity[i] = data[i*chunk_size+j] ^ parity[i];
1307 43 unneback 
    end
1308 
end
1309 
endmodule
1310 
 
1311 
`define MODULE parity_check
1312 
module `BASE`MODULE( data, parity, parity_error);
1313 
`undef MODULE
1314 
parameter word_size = 32;
1315 
parameter chunk_size = 8;
1316 
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1317 
input [word_size-1:0] data;
1318 
input [word_size/chunk_size-1:0] parity;
1319 
output parity_error;
1320 44 unneback 
reg [word_size/chunk_size-1:0] error_flag;
1321 43 unneback 
integer i,j;
1322 
always @ (data or parity)
1323 
for (i=0;i<word_size/chunk_size;i=i+1) begin
1324 
    error_flag[i] = parity[i] ^ parity_type;
1325 
    for (j=0;j<chunk_size;j=j+1) begin
1326 46 unneback 
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
1327 43 unneback 
    end
1328 
end
1329 
assign parity_error = |error_flag;
1330 
endmodule
1331 
 
1332 44 unneback 
`endif//////////////////////////////////////////////////////////////////////
1333 
////                                                              ////
1334 
////  IO functions                                                ////
1335 
////                                                              ////
1336 
////  Description                                                 ////
1337 
////  IO functions such as IOB flip-flops                         ////
1338 
////                                                              ////
1339 
////                                                              ////
1340 
////  To Do:                                                      ////
1341 
////   -                                                          ////
1342 
////                                                              ////
1343 
////  Author(s):                                                  ////
1344 
////      - Michael Unneback, unneback@opencores.org              ////
1345 
////        ORSoC AB                                              ////
1346 
////                                                              ////
1347 18 unneback 
//////////////////////////////////////////////////////////////////////
1348 
////                                                              ////
1349 44 unneback 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1350 
////                                                              ////
1351 
//// This source file may be used and distributed without         ////
1352 
//// restriction provided that this copyright statement is not    ////
1353 
//// removed from the file and that any derivative work contains  ////
1354 
//// the original copyright notice and the associated disclaimer. ////
1355 
////                                                              ////
1356 
//// This source file is free software; you can redistribute it   ////
1357 
//// and/or modify it under the terms of the GNU Lesser General   ////
1358 
//// Public License as published by the Free Software Foundation; ////
1359 
//// either version 2.1 of the License, or (at your option) any   ////
1360 
//// later version.                                               ////
1361 
////                                                              ////
1362 
//// This source is distributed in the hope that it will be       ////
1363 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1364 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1365 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1366 
//// details.                                                     ////
1367 
////                                                              ////
1368 
//// You should have received a copy of the GNU Lesser General    ////
1369 
//// Public License along with this source; if not, download it   ////
1370 
//// from http://www.opencores.org/lgpl.shtml                     ////
1371 
////                                                              ////
1372 
//////////////////////////////////////////////////////////////////////
1373 45 unneback 
`timescale 1ns/1ns
1374 44 unneback 
`ifdef O_DFF
1375 
`define MODULE o_dff
1376 
module `BASE`MODULE (d_i, o_pad, clk, rst);
1377 
`undef MODULE
1378 
parameter width = 1;
1379 45 unneback 
parameter reset_value = {width{1'b0}};
1380 
input  [width-1:0]  d_i;
1381 44 unneback 
output [width-1:0] o_pad;
1382 
input clk, rst;
1383 
wire [width-1:0] d_i_int `SYN_KEEP;
1384 45 unneback 
reg  [width-1:0] o_pad_int;
1385 44 unneback 
assign d_i_int = d_i;
1386 
genvar i;
1387 45 unneback 
generate
1388 44 unneback 
for (i=0;i<width;i=i+1) begin
1389 
    always @ (posedge clk or posedge rst)
1390 
    if (rst)
1391 45 unneback 
        o_pad_int[i] <= reset_value[i];
1392 44 unneback 
    else
1393 45 unneback 
        o_pad_int[i] <= d_i_int[i];
1394 
    assign #1 o_pad[i] = o_pad_int[i];
1395 44 unneback 
end
1396 
endgenerate
1397 
endmodule
1398 
`endif
1399 
 
1400 45 unneback 
`timescale 1ns/1ns
1401 44 unneback 
`ifdef IO_DFF_OE
1402 
`define MODULE io_dff_oe
1403 
module `BASE`MODULE ( d_i, d_o, oe, io_pad, clk, rst);
1404 
`undef MODULE
1405 
parameter width = 1;
1406 
input  [width-1:0] d_o;
1407 
output reg [width-1:0] d_i;
1408 
input oe;
1409 
inout [width-1:0] io_pad;
1410 
input clk, rst;
1411 
wire [width-1:0] oe_d `SYN_KEEP;
1412 
reg [width-1:0] oe_q;
1413 
reg [width-1:0] d_o_q;
1414 
assign oe_d = {width{oe}};
1415 
genvar i;
1416 
generate
1417 
for (i=0;i<width;i=i+1) begin
1418 
    always @ (posedge clk or posedge rst)
1419 
    if (rst)
1420 
        oe_q[i] <= 1'b0;
1421 
    else
1422 
        oe_q[i] <= oe_d[i];
1423 
    always @ (posedge clk or posedge rst)
1424 
    if (rst)
1425 
        d_o_q[i] <= 1'b0;
1426 
    else
1427 
        d_o_q[i] <= d_o[i];
1428 
    always @ (posedge clk or posedge rst)
1429 
    if (rst)
1430 
        d_i[i] <= 1'b0;
1431 
    else
1432 
        d_i[i] <= io_pad[i];
1433 45 unneback 
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
1434 44 unneback 
end
1435 
endgenerate
1436 
endmodule
1437 
`endif
1438 
`ifdef CNT_BIN
1439 
//////////////////////////////////////////////////////////////////////
1440 
////                                                              ////
1441 6 unneback 
////  Versatile counter                                           ////
1442 
////                                                              ////
1443 
////  Description                                                 ////
1444 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1445 
////  counter                                                     ////
1446 
////                                                              ////
1447 
////  To Do:                                                      ////
1448 
////   - add LFSR with more taps                                  ////
1449 
////                                                              ////
1450 
////  Author(s):                                                  ////
1451 
////      - Michael Unneback, unneback@opencores.org              ////
1452 
////        ORSoC AB                                              ////
1453 
////                                                              ////
1454 
//////////////////////////////////////////////////////////////////////
1455 
////                                                              ////
1456 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1457 
////                                                              ////
1458 
//// This source file may be used and distributed without         ////
1459 
//// restriction provided that this copyright statement is not    ////
1460 
//// removed from the file and that any derivative work contains  ////
1461 
//// the original copyright notice and the associated disclaimer. ////
1462 
////                                                              ////
1463 
//// This source file is free software; you can redistribute it   ////
1464 
//// and/or modify it under the terms of the GNU Lesser General   ////
1465 
//// Public License as published by the Free Software Foundation; ////
1466 
//// either version 2.1 of the License, or (at your option) any   ////
1467 
//// later version.                                               ////
1468 
////                                                              ////
1469 
//// This source is distributed in the hope that it will be       ////
1470 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1471 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1472 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1473 
//// details.                                                     ////
1474 
////                                                              ////
1475 
//// You should have received a copy of the GNU Lesser General    ////
1476 
//// Public License along with this source; if not, download it   ////
1477 
//// from http://www.opencores.org/lgpl.shtml                     ////
1478 
////                                                              ////
1479 
//////////////////////////////////////////////////////////////////////
1480 
 
1481 
// binary counter
1482 22 unneback 
 
1483 40 unneback 
`define MODULE cnt_bin
1484 
module `BASE`MODULE (
1485 
`undef MODULE
1486 
 q, rst, clk);
1487 
 
1488 22 unneback 
   parameter length = 4;
1489 
   output [length:1] q;
1490 
   input rst;
1491 
   input clk;
1492 
 
1493 
   parameter clear_value = 0;
1494 
   parameter set_value = 1;
1495 
   parameter wrap_value = 0;
1496 
   parameter level1_value = 15;
1497 
 
1498 
   reg  [length:1] qi;
1499 
   wire [length:1] q_next;
1500 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1501 
 
1502 
   always @ (posedge clk or posedge rst)
1503 
     if (rst)
1504 
       qi <= {length{1'b0}};
1505 
     else
1506 
       qi <= q_next;
1507 
 
1508 
   assign q = qi;
1509 
 
1510 
endmodule
1511 40 unneback 
`endif
1512 
`ifdef CNT_BIN_CLEAR
1513 22 unneback 
//////////////////////////////////////////////////////////////////////
1514 
////                                                              ////
1515 
////  Versatile counter                                           ////
1516 
////                                                              ////
1517 
////  Description                                                 ////
1518 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1519 
////  counter                                                     ////
1520 
////                                                              ////
1521 
////  To Do:                                                      ////
1522 
////   - add LFSR with more taps                                  ////
1523 
////                                                              ////
1524 
////  Author(s):                                                  ////
1525 
////      - Michael Unneback, unneback@opencores.org              ////
1526 
////        ORSoC AB                                              ////
1527 
////                                                              ////
1528 
//////////////////////////////////////////////////////////////////////
1529 
////                                                              ////
1530 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1531 
////                                                              ////
1532 
//// This source file may be used and distributed without         ////
1533 
//// restriction provided that this copyright statement is not    ////
1534 
//// removed from the file and that any derivative work contains  ////
1535 
//// the original copyright notice and the associated disclaimer. ////
1536 
////                                                              ////
1537 
//// This source file is free software; you can redistribute it   ////
1538 
//// and/or modify it under the terms of the GNU Lesser General   ////
1539 
//// Public License as published by the Free Software Foundation; ////
1540 
//// either version 2.1 of the License, or (at your option) any   ////
1541 
//// later version.                                               ////
1542 
////                                                              ////
1543 
//// This source is distributed in the hope that it will be       ////
1544 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1545 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1546 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1547 
//// details.                                                     ////
1548 
////                                                              ////
1549 
//// You should have received a copy of the GNU Lesser General    ////
1550 
//// Public License along with this source; if not, download it   ////
1551 
//// from http://www.opencores.org/lgpl.shtml                     ////
1552 
////                                                              ////
1553 
//////////////////////////////////////////////////////////////////////
1554 
 
1555 
// binary counter
1556 
 
1557 40 unneback 
`define MODULE cnt_bin_clear
1558 
module `BASE`MODULE (
1559 
`undef MODULE
1560 
 clear, q, rst, clk);
1561 
 
1562 22 unneback 
   parameter length = 4;
1563 
   input clear;
1564 
   output [length:1] q;
1565 
   input rst;
1566 
   input clk;
1567 
 
1568 
   parameter clear_value = 0;
1569 
   parameter set_value = 1;
1570 
   parameter wrap_value = 0;
1571 
   parameter level1_value = 15;
1572 
 
1573 
   reg  [length:1] qi;
1574 
   wire [length:1] q_next;
1575 
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1576 
 
1577 
   always @ (posedge clk or posedge rst)
1578 
     if (rst)
1579 
       qi <= {length{1'b0}};
1580 
     else
1581 
       qi <= q_next;
1582 
 
1583 
   assign q = qi;
1584 
 
1585 
endmodule
1586 40 unneback 
`endif
1587 
`ifdef CNT_BIN_CE
1588 22 unneback 
//////////////////////////////////////////////////////////////////////
1589 
////                                                              ////
1590 
////  Versatile counter                                           ////
1591 
////                                                              ////
1592 
////  Description                                                 ////
1593 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1594 
////  counter                                                     ////
1595 
////                                                              ////
1596 
////  To Do:                                                      ////
1597 
////   - add LFSR with more taps                                  ////
1598 
////                                                              ////
1599 
////  Author(s):                                                  ////
1600 
////      - Michael Unneback, unneback@opencores.org              ////
1601 
////        ORSoC AB                                              ////
1602 
////                                                              ////
1603 
//////////////////////////////////////////////////////////////////////
1604 
////                                                              ////
1605 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1606 
////                                                              ////
1607 
//// This source file may be used and distributed without         ////
1608 
//// restriction provided that this copyright statement is not    ////
1609 
//// removed from the file and that any derivative work contains  ////
1610 
//// the original copyright notice and the associated disclaimer. ////
1611 
////                                                              ////
1612 
//// This source file is free software; you can redistribute it   ////
1613 
//// and/or modify it under the terms of the GNU Lesser General   ////
1614 
//// Public License as published by the Free Software Foundation; ////
1615 
//// either version 2.1 of the License, or (at your option) any   ////
1616 
//// later version.                                               ////
1617 
////                                                              ////
1618 
//// This source is distributed in the hope that it will be       ////
1619 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1620 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1621 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1622 
//// details.                                                     ////
1623 
////                                                              ////
1624 
//// You should have received a copy of the GNU Lesser General    ////
1625 
//// Public License along with this source; if not, download it   ////
1626 
//// from http://www.opencores.org/lgpl.shtml                     ////
1627 
////                                                              ////
1628 
//////////////////////////////////////////////////////////////////////
1629 
 
1630 
// binary counter
1631 6 unneback 
 
1632 40 unneback 
`define MODULE cnt_bin_ce
1633 
module `BASE`MODULE (
1634 
`undef MODULE
1635 
 cke, q, rst, clk);
1636 
 
1637 6 unneback 
   parameter length = 4;
1638 
   input cke;
1639 
   output [length:1] q;
1640 
   input rst;
1641 
   input clk;
1642 
 
1643 
   parameter clear_value = 0;
1644 
   parameter set_value = 1;
1645 
   parameter wrap_value = 0;
1646 
   parameter level1_value = 15;
1647 
 
1648 
   reg  [length:1] qi;
1649 
   wire [length:1] q_next;
1650 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1651 
 
1652 
   always @ (posedge clk or posedge rst)
1653 
     if (rst)
1654 
       qi <= {length{1'b0}};
1655 
     else
1656 
     if (cke)
1657 
       qi <= q_next;
1658 
 
1659 
   assign q = qi;
1660 
 
1661 
endmodule
1662 40 unneback 
`endif
1663 
`ifdef CNT_BIN_CE_CLEAR
1664 6 unneback 
//////////////////////////////////////////////////////////////////////
1665 
////                                                              ////
1666 
////  Versatile counter                                           ////
1667 
////                                                              ////
1668 
////  Description                                                 ////
1669 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1670 
////  counter                                                     ////
1671 
////                                                              ////
1672 
////  To Do:                                                      ////
1673 
////   - add LFSR with more taps                                  ////
1674 
////                                                              ////
1675 
////  Author(s):                                                  ////
1676 
////      - Michael Unneback, unneback@opencores.org              ////
1677 
////        ORSoC AB                                              ////
1678 
////                                                              ////
1679 
//////////////////////////////////////////////////////////////////////
1680 
////                                                              ////
1681 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1682 
////                                                              ////
1683 
//// This source file may be used and distributed without         ////
1684 
//// restriction provided that this copyright statement is not    ////
1685 
//// removed from the file and that any derivative work contains  ////
1686 
//// the original copyright notice and the associated disclaimer. ////
1687 
////                                                              ////
1688 
//// This source file is free software; you can redistribute it   ////
1689 
//// and/or modify it under the terms of the GNU Lesser General   ////
1690 
//// Public License as published by the Free Software Foundation; ////
1691 
//// either version 2.1 of the License, or (at your option) any   ////
1692 
//// later version.                                               ////
1693 
////                                                              ////
1694 
//// This source is distributed in the hope that it will be       ////
1695 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1696 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1697 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1698 
//// details.                                                     ////
1699 
////                                                              ////
1700 
//// You should have received a copy of the GNU Lesser General    ////
1701 
//// Public License along with this source; if not, download it   ////
1702 
//// from http://www.opencores.org/lgpl.shtml                     ////
1703 
////                                                              ////
1704 
//////////////////////////////////////////////////////////////////////
1705 
 
1706 
// binary counter
1707 
 
1708 40 unneback 
`define MODULE cnt_bin_ce_clear
1709 
module `BASE`MODULE (
1710 
`undef MODULE
1711 
 clear, cke, q, rst, clk);
1712 
 
1713 6 unneback 
   parameter length = 4;
1714 
   input clear;
1715 
   input cke;
1716 
   output [length:1] q;
1717 
   input rst;
1718 
   input clk;
1719 
 
1720 
   parameter clear_value = 0;
1721 
   parameter set_value = 1;
1722 
   parameter wrap_value = 0;
1723 
   parameter level1_value = 15;
1724 
 
1725 
   reg  [length:1] qi;
1726 
   wire [length:1] q_next;
1727 
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1728 
 
1729 
   always @ (posedge clk or posedge rst)
1730 
     if (rst)
1731 
       qi <= {length{1'b0}};
1732 
     else
1733 
     if (cke)
1734 
       qi <= q_next;
1735 
 
1736 
   assign q = qi;
1737 
 
1738 
endmodule
1739 40 unneback 
`endif
1740 
`ifdef CNT_BIN_CE_CLEAR_L1_L2
1741 6 unneback 
//////////////////////////////////////////////////////////////////////
1742 
////                                                              ////
1743 
////  Versatile counter                                           ////
1744 
////                                                              ////
1745 
////  Description                                                 ////
1746 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1747 
////  counter                                                     ////
1748 
////                                                              ////
1749 
////  To Do:                                                      ////
1750 
////   - add LFSR with more taps                                  ////
1751 
////                                                              ////
1752 
////  Author(s):                                                  ////
1753 
////      - Michael Unneback, unneback@opencores.org              ////
1754 
////        ORSoC AB                                              ////
1755 
////                                                              ////
1756 
//////////////////////////////////////////////////////////////////////
1757 
////                                                              ////
1758 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1759 
////                                                              ////
1760 
//// This source file may be used and distributed without         ////
1761 
//// restriction provided that this copyright statement is not    ////
1762 
//// removed from the file and that any derivative work contains  ////
1763 
//// the original copyright notice and the associated disclaimer. ////
1764 
////                                                              ////
1765 
//// This source file is free software; you can redistribute it   ////
1766 
//// and/or modify it under the terms of the GNU Lesser General   ////
1767 
//// Public License as published by the Free Software Foundation; ////
1768 
//// either version 2.1 of the License, or (at your option) any   ////
1769 
//// later version.                                               ////
1770 
////                                                              ////
1771 
//// This source is distributed in the hope that it will be       ////
1772 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1773 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1774 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1775 
//// details.                                                     ////
1776 
////                                                              ////
1777 
//// You should have received a copy of the GNU Lesser General    ////
1778 
//// Public License along with this source; if not, download it   ////
1779 
//// from http://www.opencores.org/lgpl.shtml                     ////
1780 
////                                                              ////
1781 
//////////////////////////////////////////////////////////////////////
1782 
 
1783 
// binary counter
1784 29 unneback 
 
1785 40 unneback 
`define MODULE cnt_bin_ce_clear_l1_l2
1786 
module `BASE`MODULE (
1787 
`undef MODULE
1788 
 clear, cke, q, level1, level2, rst, clk);
1789 
 
1790 29 unneback 
   parameter length = 4;
1791 
   input clear;
1792 
   input cke;
1793 
   output [length:1] q;
1794 
   output reg level1;
1795 
   output reg level2;
1796 
   input rst;
1797 
   input clk;
1798 
 
1799 
   parameter clear_value = 0;
1800 
   parameter set_value = 1;
1801 30 unneback 
   parameter wrap_value = 15;
1802 
   parameter level1_value = 8;
1803 
   parameter level2_value = 15;
1804 29 unneback 
 
1805 
   wire rew;
1806 30 unneback 
   assign rew = 1'b0;
1807 29 unneback 
   reg  [length:1] qi;
1808 
   wire [length:1] q_next;
1809 
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1810 
 
1811 
   always @ (posedge clk or posedge rst)
1812 
     if (rst)
1813 
       qi <= {length{1'b0}};
1814 
     else
1815 
     if (cke)
1816 
       qi <= q_next;
1817 
 
1818 
   assign q = qi;
1819 
 
1820 
 
1821 
    always @ (posedge clk or posedge rst)
1822 
    if (rst)
1823 
        level1 <= 1'b0;
1824 
    else
1825 
    if (cke)
1826 
    if (clear)
1827 
        level1 <= 1'b0;
1828 
    else if (q_next == level1_value)
1829 
        level1 <= 1'b1;
1830 
    else if (qi == level1_value & rew)
1831 
        level1 <= 1'b0;
1832 
 
1833 
    always @ (posedge clk or posedge rst)
1834 
    if (rst)
1835 
        level2 <= 1'b0;
1836 
    else
1837 
    if (cke)
1838 
    if (clear)
1839 
        level2 <= 1'b0;
1840 
    else if (q_next == level2_value)
1841 
        level2 <= 1'b1;
1842 
    else if (qi == level2_value & rew)
1843 
        level2 <= 1'b0;
1844 
endmodule
1845 40 unneback 
`endif
1846 
`ifdef CNT_BIN_CE_CLEAR_SET_REW
1847 29 unneback 
//////////////////////////////////////////////////////////////////////
1848 
////                                                              ////
1849 
////  Versatile counter                                           ////
1850 
////                                                              ////
1851 
////  Description                                                 ////
1852 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1853 
////  counter                                                     ////
1854 
////                                                              ////
1855 
////  To Do:                                                      ////
1856 
////   - add LFSR with more taps                                  ////
1857 
////                                                              ////
1858 
////  Author(s):                                                  ////
1859 
////      - Michael Unneback, unneback@opencores.org              ////
1860 
////        ORSoC AB                                              ////
1861 
////                                                              ////
1862 
//////////////////////////////////////////////////////////////////////
1863 
////                                                              ////
1864 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1865 
////                                                              ////
1866 
//// This source file may be used and distributed without         ////
1867 
//// restriction provided that this copyright statement is not    ////
1868 
//// removed from the file and that any derivative work contains  ////
1869 
//// the original copyright notice and the associated disclaimer. ////
1870 
////                                                              ////
1871 
//// This source file is free software; you can redistribute it   ////
1872 
//// and/or modify it under the terms of the GNU Lesser General   ////
1873 
//// Public License as published by the Free Software Foundation; ////
1874 
//// either version 2.1 of the License, or (at your option) any   ////
1875 
//// later version.                                               ////
1876 
////                                                              ////
1877 
//// This source is distributed in the hope that it will be       ////
1878 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1879 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1880 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1881 
//// details.                                                     ////
1882 
////                                                              ////
1883 
//// You should have received a copy of the GNU Lesser General    ////
1884 
//// Public License along with this source; if not, download it   ////
1885 
//// from http://www.opencores.org/lgpl.shtml                     ////
1886 
////                                                              ////
1887 
//////////////////////////////////////////////////////////////////////
1888 
 
1889 
// binary counter
1890 6 unneback 
 
1891 40 unneback 
`define MODULE cnt_bin_ce_clear_set_rew
1892 
module `BASE`MODULE (
1893 
`undef MODULE
1894 
 clear, set, cke, rew, q, rst, clk);
1895 
 
1896 6 unneback 
   parameter length = 4;
1897 
   input clear;
1898 
   input set;
1899 
   input cke;
1900 
   input rew;
1901 
   output [length:1] q;
1902 
   input rst;
1903 
   input clk;
1904 
 
1905 
   parameter clear_value = 0;
1906 
   parameter set_value = 1;
1907 
   parameter wrap_value = 0;
1908 
   parameter level1_value = 15;
1909 
 
1910 
   reg  [length:1] qi;
1911 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1912 
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
1913 
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
1914 
   assign q_next = rew ? q_next_rew : q_next_fw;
1915 
 
1916 
   always @ (posedge clk or posedge rst)
1917 
     if (rst)
1918 
       qi <= {length{1'b0}};
1919 
     else
1920 
     if (cke)
1921 
       qi <= q_next;
1922 
 
1923 
   assign q = qi;
1924 
 
1925 
endmodule
1926 40 unneback 
`endif
1927 
`ifdef CNT_BIN_CE_REW_L1
1928 6 unneback 
//////////////////////////////////////////////////////////////////////
1929 
////                                                              ////
1930 
////  Versatile counter                                           ////
1931 
////                                                              ////
1932 
////  Description                                                 ////
1933 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1934 
////  counter                                                     ////
1935 
////                                                              ////
1936 
////  To Do:                                                      ////
1937 
////   - add LFSR with more taps                                  ////
1938 
////                                                              ////
1939 
////  Author(s):                                                  ////
1940 
////      - Michael Unneback, unneback@opencores.org              ////
1941 
////        ORSoC AB                                              ////
1942 
////                                                              ////
1943 
//////////////////////////////////////////////////////////////////////
1944 
////                                                              ////
1945 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1946 
////                                                              ////
1947 
//// This source file may be used and distributed without         ////
1948 
//// restriction provided that this copyright statement is not    ////
1949 
//// removed from the file and that any derivative work contains  ////
1950 
//// the original copyright notice and the associated disclaimer. ////
1951 
////                                                              ////
1952 
//// This source file is free software; you can redistribute it   ////
1953 
//// and/or modify it under the terms of the GNU Lesser General   ////
1954 
//// Public License as published by the Free Software Foundation; ////
1955 
//// either version 2.1 of the License, or (at your option) any   ////
1956 
//// later version.                                               ////
1957 
////                                                              ////
1958 
//// This source is distributed in the hope that it will be       ////
1959 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1960 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1961 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1962 
//// details.                                                     ////
1963 
////                                                              ////
1964 
//// You should have received a copy of the GNU Lesser General    ////
1965 
//// Public License along with this source; if not, download it   ////
1966 
//// from http://www.opencores.org/lgpl.shtml                     ////
1967 
////                                                              ////
1968 
//////////////////////////////////////////////////////////////////////
1969 
 
1970 
// binary counter
1971 
 
1972 40 unneback 
`define MODULE cnt_bin_ce_rew_l1
1973 
module `BASE`MODULE (
1974 
`undef MODULE
1975 
 cke, rew, level1, rst, clk);
1976 
 
1977 6 unneback 
   parameter length = 4;
1978 
   input cke;
1979 
   input rew;
1980 
   output reg level1;
1981 
   input rst;
1982 
   input clk;
1983 
 
1984 
   parameter clear_value = 0;
1985 
   parameter set_value = 1;
1986 
   parameter wrap_value = 1;
1987 
   parameter level1_value = 15;
1988 
 
1989 29 unneback 
   wire clear;
1990 30 unneback 
   assign clear = 1'b0;
1991 6 unneback 
   reg  [length:1] qi;
1992 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1993 
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1994 
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1995 
   assign q_next = rew ? q_next_rew : q_next_fw;
1996 
 
1997 
   always @ (posedge clk or posedge rst)
1998 
     if (rst)
1999 
       qi <= {length{1'b0}};
2000 
     else
2001 
     if (cke)
2002 
       qi <= q_next;
2003 
 
2004 
 
2005 
 
2006 
    always @ (posedge clk or posedge rst)
2007 
    if (rst)
2008 
        level1 <= 1'b0;
2009 
    else
2010 
    if (cke)
2011 29 unneback 
    if (clear)
2012 
        level1 <= 1'b0;
2013 
    else if (q_next == level1_value)
2014 6 unneback 
        level1 <= 1'b1;
2015 
    else if (qi == level1_value & rew)
2016 
        level1 <= 1'b0;
2017 
endmodule
2018 40 unneback 
`endif
2019 
`ifdef CNT_BIN_CE_REW_ZQ_L1
2020 6 unneback 
//////////////////////////////////////////////////////////////////////
2021 
////                                                              ////
2022 
////  Versatile counter                                           ////
2023 
////                                                              ////
2024 
////  Description                                                 ////
2025 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2026 
////  counter                                                     ////
2027 
////                                                              ////
2028 
////  To Do:                                                      ////
2029 
////   - add LFSR with more taps                                  ////
2030 
////                                                              ////
2031 
////  Author(s):                                                  ////
2032 
////      - Michael Unneback, unneback@opencores.org              ////
2033 
////        ORSoC AB                                              ////
2034 
////                                                              ////
2035 
//////////////////////////////////////////////////////////////////////
2036 
////                                                              ////
2037 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2038 
////                                                              ////
2039 
//// This source file may be used and distributed without         ////
2040 
//// restriction provided that this copyright statement is not    ////
2041 
//// removed from the file and that any derivative work contains  ////
2042 
//// the original copyright notice and the associated disclaimer. ////
2043 
////                                                              ////
2044 
//// This source file is free software; you can redistribute it   ////
2045 
//// and/or modify it under the terms of the GNU Lesser General   ////
2046 
//// Public License as published by the Free Software Foundation; ////
2047 
//// either version 2.1 of the License, or (at your option) any   ////
2048 
//// later version.                                               ////
2049 
////                                                              ////
2050 
//// This source is distributed in the hope that it will be       ////
2051 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2052 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2053 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2054 
//// details.                                                     ////
2055 
////                                                              ////
2056 
//// You should have received a copy of the GNU Lesser General    ////
2057 
//// Public License along with this source; if not, download it   ////
2058 
//// from http://www.opencores.org/lgpl.shtml                     ////
2059 
////                                                              ////
2060 
//////////////////////////////////////////////////////////////////////
2061 
 
2062 25 unneback 
// binary counter
2063 
 
2064 40 unneback 
`define MODULE cnt_bin_ce_rew_zq_l1
2065 
module `BASE`MODULE (
2066 
`undef MODULE
2067 
 cke, rew, zq, level1, rst, clk);
2068 
 
2069 25 unneback 
   parameter length = 4;
2070 
   input cke;
2071 
   input rew;
2072 
   output reg zq;
2073 
   output reg level1;
2074 
   input rst;
2075 
   input clk;
2076 
 
2077 
   parameter clear_value = 0;
2078 
   parameter set_value = 1;
2079 
   parameter wrap_value = 1;
2080 
   parameter level1_value = 15;
2081 
 
2082 29 unneback 
   wire clear;
2083 30 unneback 
   assign clear = 1'b0;
2084 25 unneback 
   reg  [length:1] qi;
2085 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2086 
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2087 
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2088 
   assign q_next = rew ? q_next_rew : q_next_fw;
2089 
 
2090 
   always @ (posedge clk or posedge rst)
2091 
     if (rst)
2092 
       qi <= {length{1'b0}};
2093 
     else
2094 
     if (cke)
2095 
       qi <= q_next;
2096 
 
2097 
 
2098 
 
2099 
   always @ (posedge clk or posedge rst)
2100 
     if (rst)
2101 
       zq <= 1'b1;
2102 
     else
2103 
     if (cke)
2104 
       zq <= q_next == {length{1'b0}};
2105 
 
2106 
    always @ (posedge clk or posedge rst)
2107 
    if (rst)
2108 
        level1 <= 1'b0;
2109 
    else
2110 
    if (cke)
2111 29 unneback 
    if (clear)
2112 
        level1 <= 1'b0;
2113 
    else if (q_next == level1_value)
2114 25 unneback 
        level1 <= 1'b1;
2115 
    else if (qi == level1_value & rew)
2116 
        level1 <= 1'b0;
2117 
endmodule
2118 40 unneback 
`endif
2119 
`ifdef CNT_BIN_CE_REW_Q_ZQ_L1
2120 25 unneback 
//////////////////////////////////////////////////////////////////////
2121 
////                                                              ////
2122 
////  Versatile counter                                           ////
2123 
////                                                              ////
2124 
////  Description                                                 ////
2125 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2126 
////  counter                                                     ////
2127 
////                                                              ////
2128 
////  To Do:                                                      ////
2129 
////   - add LFSR with more taps                                  ////
2130 
////                                                              ////
2131 
////  Author(s):                                                  ////
2132 
////      - Michael Unneback, unneback@opencores.org              ////
2133 
////        ORSoC AB                                              ////
2134 
////                                                              ////
2135 
//////////////////////////////////////////////////////////////////////
2136 
////                                                              ////
2137 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2138 
////                                                              ////
2139 
//// This source file may be used and distributed without         ////
2140 
//// restriction provided that this copyright statement is not    ////
2141 
//// removed from the file and that any derivative work contains  ////
2142 
//// the original copyright notice and the associated disclaimer. ////
2143 
////                                                              ////
2144 
//// This source file is free software; you can redistribute it   ////
2145 
//// and/or modify it under the terms of the GNU Lesser General   ////
2146 
//// Public License as published by the Free Software Foundation; ////
2147 
//// either version 2.1 of the License, or (at your option) any   ////
2148 
//// later version.                                               ////
2149 
////                                                              ////
2150 
//// This source is distributed in the hope that it will be       ////
2151 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2152 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2153 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2154 
//// details.                                                     ////
2155 
////                                                              ////
2156 
//// You should have received a copy of the GNU Lesser General    ////
2157 
//// Public License along with this source; if not, download it   ////
2158 
//// from http://www.opencores.org/lgpl.shtml                     ////
2159 
////                                                              ////
2160 
//////////////////////////////////////////////////////////////////////
2161 
 
2162 
// binary counter
2163 
 
2164 40 unneback 
`define MODULE cnt_bin_ce_rew_q_zq_l1
2165 
module `BASE`MODULE (
2166 
`undef MODULE
2167 
 cke, rew, q, zq, level1, rst, clk);
2168 
 
2169 25 unneback 
   parameter length = 4;
2170 
   input cke;
2171 
   input rew;
2172 
   output [length:1] q;
2173 
   output reg zq;
2174 
   output reg level1;
2175 
   input rst;
2176 
   input clk;
2177 
 
2178 
   parameter clear_value = 0;
2179 
   parameter set_value = 1;
2180 
   parameter wrap_value = 1;
2181 
   parameter level1_value = 15;
2182 
 
2183 29 unneback 
   wire clear;
2184 30 unneback 
   assign clear = 1'b0;
2185 25 unneback 
   reg  [length:1] qi;
2186 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2187 
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2188 
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2189 
   assign q_next = rew ? q_next_rew : q_next_fw;
2190 
 
2191 
   always @ (posedge clk or posedge rst)
2192 
     if (rst)
2193 
       qi <= {length{1'b0}};
2194 
     else
2195 
     if (cke)
2196 
       qi <= q_next;
2197 
 
2198 
   assign q = qi;
2199 
 
2200 
 
2201 
   always @ (posedge clk or posedge rst)
2202 
     if (rst)
2203 
       zq <= 1'b1;
2204 
     else
2205 
     if (cke)
2206 
       zq <= q_next == {length{1'b0}};
2207 
 
2208 
    always @ (posedge clk or posedge rst)
2209 
    if (rst)
2210 
        level1 <= 1'b0;
2211 
    else
2212 
    if (cke)
2213 29 unneback 
    if (clear)
2214 
        level1 <= 1'b0;
2215 
    else if (q_next == level1_value)
2216 25 unneback 
        level1 <= 1'b1;
2217 
    else if (qi == level1_value & rew)
2218 
        level1 <= 1'b0;
2219 
endmodule
2220 40 unneback 
`endif
2221 
`ifdef CNT_LFSR_ZQ
2222 25 unneback 
//////////////////////////////////////////////////////////////////////
2223 
////                                                              ////
2224 
////  Versatile counter                                           ////
2225 
////                                                              ////
2226 
////  Description                                                 ////
2227 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2228 
////  counter                                                     ////
2229 
////                                                              ////
2230 
////  To Do:                                                      ////
2231 
////   - add LFSR with more taps                                  ////
2232 
////                                                              ////
2233 
////  Author(s):                                                  ////
2234 
////      - Michael Unneback, unneback@opencores.org              ////
2235 
////        ORSoC AB                                              ////
2236 
////                                                              ////
2237 
//////////////////////////////////////////////////////////////////////
2238 
////                                                              ////
2239 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2240 
////                                                              ////
2241 
//// This source file may be used and distributed without         ////
2242 
//// restriction provided that this copyright statement is not    ////
2243 
//// removed from the file and that any derivative work contains  ////
2244 
//// the original copyright notice and the associated disclaimer. ////
2245 
////                                                              ////
2246 
//// This source file is free software; you can redistribute it   ////
2247 
//// and/or modify it under the terms of the GNU Lesser General   ////
2248 
//// Public License as published by the Free Software Foundation; ////
2249 
//// either version 2.1 of the License, or (at your option) any   ////
2250 
//// later version.                                               ////
2251 
////                                                              ////
2252 
//// This source is distributed in the hope that it will be       ////
2253 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2254 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2255 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2256 
//// details.                                                     ////
2257 
////                                                              ////
2258 
//// You should have received a copy of the GNU Lesser General    ////
2259 
//// Public License along with this source; if not, download it   ////
2260 
//// from http://www.opencores.org/lgpl.shtml                     ////
2261 
////                                                              ////
2262 
//////////////////////////////////////////////////////////////////////
2263 
 
2264 6 unneback 
// LFSR counter
2265 
 
2266 40 unneback 
`define MODULE cnt_lfsr_zq
2267 
module `BASE`MODULE (
2268 
`undef MODULE
2269 
 zq, rst, clk);
2270 
 
2271 6 unneback 
   parameter length = 4;
2272 
   output reg zq;
2273 
   input rst;
2274 
   input clk;
2275 
 
2276 
   parameter clear_value = 0;
2277 
   parameter set_value = 1;
2278 
   parameter wrap_value = 8;
2279 
   parameter level1_value = 15;
2280 
 
2281 
   reg  [length:1] qi;
2282 
   reg lfsr_fb;
2283 
   wire [length:1] q_next;
2284 
   reg [32:1] polynom;
2285 
   integer i;
2286 
 
2287 
   always @ (qi)
2288 
   begin
2289 
        case (length)
2290 
         2: polynom = 32'b11;                               // 0x3
2291 
         3: polynom = 32'b110;                              // 0x6
2292 
         4: polynom = 32'b1100;                             // 0xC
2293 
         5: polynom = 32'b10100;                            // 0x14
2294 
         6: polynom = 32'b110000;                           // 0x30
2295 
         7: polynom = 32'b1100000;                          // 0x60
2296 
         8: polynom = 32'b10111000;                         // 0xb8
2297 
         9: polynom = 32'b100010000;                        // 0x110
2298 
        10: polynom = 32'b1001000000;                       // 0x240
2299 
        11: polynom = 32'b10100000000;                      // 0x500
2300 
        12: polynom = 32'b100000101001;                     // 0x829
2301 
        13: polynom = 32'b1000000001100;                    // 0x100C
2302 
        14: polynom = 32'b10000000010101;                   // 0x2015
2303 
        15: polynom = 32'b110000000000000;                  // 0x6000
2304 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2305 
        17: polynom = 32'b10010000000000000;                // 0x12000
2306 
        18: polynom = 32'b100000010000000000;               // 0x20400
2307 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2308 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2309 6 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2310 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2311 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2312 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2313 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2314 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2315 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2316 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2317 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2318 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2319 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2320 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2321 
        default: polynom = 32'b0;
2322 
        endcase
2323 
        lfsr_fb = qi[length];
2324 
        for (i=length-1; i>=1; i=i-1) begin
2325 
            if (polynom[i])
2326 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2327 
        end
2328 
    end
2329 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2330 
 
2331 
   always @ (posedge clk or posedge rst)
2332 
     if (rst)
2333 
       qi <= {length{1'b0}};
2334 
     else
2335 
       qi <= q_next;
2336 
 
2337 
 
2338 
 
2339 
   always @ (posedge clk or posedge rst)
2340 
     if (rst)
2341 
       zq <= 1'b1;
2342 
     else
2343 
       zq <= q_next == {length{1'b0}};
2344 
endmodule
2345 40 unneback 
`endif
2346 
`ifdef CNT_LFSR_CE_ZQ
2347 6 unneback 
//////////////////////////////////////////////////////////////////////
2348 
////                                                              ////
2349 
////  Versatile counter                                           ////
2350 
////                                                              ////
2351 
////  Description                                                 ////
2352 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2353 
////  counter                                                     ////
2354 
////                                                              ////
2355 
////  To Do:                                                      ////
2356 
////   - add LFSR with more taps                                  ////
2357 
////                                                              ////
2358 
////  Author(s):                                                  ////
2359 
////      - Michael Unneback, unneback@opencores.org              ////
2360 
////        ORSoC AB                                              ////
2361 
////                                                              ////
2362 
//////////////////////////////////////////////////////////////////////
2363 
////                                                              ////
2364 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2365 
////                                                              ////
2366 
//// This source file may be used and distributed without         ////
2367 
//// restriction provided that this copyright statement is not    ////
2368 
//// removed from the file and that any derivative work contains  ////
2369 
//// the original copyright notice and the associated disclaimer. ////
2370 
////                                                              ////
2371 
//// This source file is free software; you can redistribute it   ////
2372 
//// and/or modify it under the terms of the GNU Lesser General   ////
2373 
//// Public License as published by the Free Software Foundation; ////
2374 
//// either version 2.1 of the License, or (at your option) any   ////
2375 
//// later version.                                               ////
2376 
////                                                              ////
2377 
//// This source is distributed in the hope that it will be       ////
2378 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2379 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2380 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2381 
//// details.                                                     ////
2382 
////                                                              ////
2383 
//// You should have received a copy of the GNU Lesser General    ////
2384 
//// Public License along with this source; if not, download it   ////
2385 
//// from http://www.opencores.org/lgpl.shtml                     ////
2386 
////                                                              ////
2387 
//////////////////////////////////////////////////////////////////////
2388 
 
2389 
// LFSR counter
2390 
 
2391 40 unneback 
`define MODULE cnt_lfsr_ce_zq
2392 
module `BASE`MODULE (
2393 
`undef MODULE
2394 
 cke, zq, rst, clk);
2395 
 
2396 6 unneback 
   parameter length = 4;
2397 
   input cke;
2398 
   output reg zq;
2399 
   input rst;
2400 
   input clk;
2401 
 
2402 
   parameter clear_value = 0;
2403 
   parameter set_value = 1;
2404 
   parameter wrap_value = 8;
2405 
   parameter level1_value = 15;
2406 
 
2407 
   reg  [length:1] qi;
2408 
   reg lfsr_fb;
2409 
   wire [length:1] q_next;
2410 
   reg [32:1] polynom;
2411 
   integer i;
2412 
 
2413 
   always @ (qi)
2414 
   begin
2415 
        case (length)
2416 
         2: polynom = 32'b11;                               // 0x3
2417 
         3: polynom = 32'b110;                              // 0x6
2418 
         4: polynom = 32'b1100;                             // 0xC
2419 
         5: polynom = 32'b10100;                            // 0x14
2420 
         6: polynom = 32'b110000;                           // 0x30
2421 
         7: polynom = 32'b1100000;                          // 0x60
2422 
         8: polynom = 32'b10111000;                         // 0xb8
2423 
         9: polynom = 32'b100010000;                        // 0x110
2424 
        10: polynom = 32'b1001000000;                       // 0x240
2425 
        11: polynom = 32'b10100000000;                      // 0x500
2426 
        12: polynom = 32'b100000101001;                     // 0x829
2427 
        13: polynom = 32'b1000000001100;                    // 0x100C
2428 
        14: polynom = 32'b10000000010101;                   // 0x2015
2429 
        15: polynom = 32'b110000000000000;                  // 0x6000
2430 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2431 
        17: polynom = 32'b10010000000000000;                // 0x12000
2432 
        18: polynom = 32'b100000010000000000;               // 0x20400
2433 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2434 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2435 6 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2436 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2437 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2438 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2439 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2440 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2441 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2442 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2443 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2444 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2445 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2446 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2447 
        default: polynom = 32'b0;
2448 
        endcase
2449 
        lfsr_fb = qi[length];
2450 
        for (i=length-1; i>=1; i=i-1) begin
2451 
            if (polynom[i])
2452 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2453 
        end
2454 
    end
2455 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2456 
 
2457 
   always @ (posedge clk or posedge rst)
2458 
     if (rst)
2459 
       qi <= {length{1'b0}};
2460 
     else
2461 
     if (cke)
2462 
       qi <= q_next;
2463 
 
2464 
 
2465 
 
2466 
   always @ (posedge clk or posedge rst)
2467 
     if (rst)
2468 
       zq <= 1'b1;
2469 
     else
2470 
     if (cke)
2471 
       zq <= q_next == {length{1'b0}};
2472 
endmodule
2473 40 unneback 
`endif
2474 
`ifdef CNT_LFSR_CE_Q
2475 6 unneback 
//////////////////////////////////////////////////////////////////////
2476 
////                                                              ////
2477 
////  Versatile counter                                           ////
2478 
////                                                              ////
2479 
////  Description                                                 ////
2480 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2481 
////  counter                                                     ////
2482 
////                                                              ////
2483 
////  To Do:                                                      ////
2484 
////   - add LFSR with more taps                                  ////
2485 
////                                                              ////
2486 
////  Author(s):                                                  ////
2487 
////      - Michael Unneback, unneback@opencores.org              ////
2488 
////        ORSoC AB                                              ////
2489 
////                                                              ////
2490 
//////////////////////////////////////////////////////////////////////
2491 
////                                                              ////
2492 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2493 
////                                                              ////
2494 
//// This source file may be used and distributed without         ////
2495 
//// restriction provided that this copyright statement is not    ////
2496 
//// removed from the file and that any derivative work contains  ////
2497 
//// the original copyright notice and the associated disclaimer. ////
2498 
////                                                              ////
2499 
//// This source file is free software; you can redistribute it   ////
2500 
//// and/or modify it under the terms of the GNU Lesser General   ////
2501 
//// Public License as published by the Free Software Foundation; ////
2502 
//// either version 2.1 of the License, or (at your option) any   ////
2503 
//// later version.                                               ////
2504 
////                                                              ////
2505 
//// This source is distributed in the hope that it will be       ////
2506 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2507 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2508 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2509 
//// details.                                                     ////
2510 
////                                                              ////
2511 
//// You should have received a copy of the GNU Lesser General    ////
2512 
//// Public License along with this source; if not, download it   ////
2513 
//// from http://www.opencores.org/lgpl.shtml                     ////
2514 
////                                                              ////
2515 
//////////////////////////////////////////////////////////////////////
2516 22 unneback 
 
2517 
// LFSR counter
2518 27 unneback 
 
2519 40 unneback 
`define MODULE cnt_lfsr_ce_q
2520 
module `BASE`MODULE (
2521 
`undef MODULE
2522 
 cke, q, rst, clk);
2523 
 
2524 27 unneback 
   parameter length = 4;
2525 
   input cke;
2526 
   output [length:1] q;
2527 
   input rst;
2528 
   input clk;
2529 
 
2530 
   parameter clear_value = 0;
2531 
   parameter set_value = 1;
2532 
   parameter wrap_value = 8;
2533 
   parameter level1_value = 15;
2534 
 
2535 
   reg  [length:1] qi;
2536 
   reg lfsr_fb;
2537 
   wire [length:1] q_next;
2538 
   reg [32:1] polynom;
2539 
   integer i;
2540 
 
2541 
   always @ (qi)
2542 
   begin
2543 
        case (length)
2544 
         2: polynom = 32'b11;                               // 0x3
2545 
         3: polynom = 32'b110;                              // 0x6
2546 
         4: polynom = 32'b1100;                             // 0xC
2547 
         5: polynom = 32'b10100;                            // 0x14
2548 
         6: polynom = 32'b110000;                           // 0x30
2549 
         7: polynom = 32'b1100000;                          // 0x60
2550 
         8: polynom = 32'b10111000;                         // 0xb8
2551 
         9: polynom = 32'b100010000;                        // 0x110
2552 
        10: polynom = 32'b1001000000;                       // 0x240
2553 
        11: polynom = 32'b10100000000;                      // 0x500
2554 
        12: polynom = 32'b100000101001;                     // 0x829
2555 
        13: polynom = 32'b1000000001100;                    // 0x100C
2556 
        14: polynom = 32'b10000000010101;                   // 0x2015
2557 
        15: polynom = 32'b110000000000000;                  // 0x6000
2558 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2559 
        17: polynom = 32'b10010000000000000;                // 0x12000
2560 
        18: polynom = 32'b100000010000000000;               // 0x20400
2561 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2562 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2563 27 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2564 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2565 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2566 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2567 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2568 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2569 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2570 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2571 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2572 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2573 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2574 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2575 
        default: polynom = 32'b0;
2576 
        endcase
2577 
        lfsr_fb = qi[length];
2578 
        for (i=length-1; i>=1; i=i-1) begin
2579 
            if (polynom[i])
2580 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2581 
        end
2582 
    end
2583 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2584 
 
2585 
   always @ (posedge clk or posedge rst)
2586 
     if (rst)
2587 
       qi <= {length{1'b0}};
2588 
     else
2589 
     if (cke)
2590 
       qi <= q_next;
2591 
 
2592 
   assign q = qi;
2593 
 
2594 
endmodule
2595 40 unneback 
`endif
2596 
`ifdef CNT_LFSR_CE_CLEAR_Q
2597 27 unneback 
//////////////////////////////////////////////////////////////////////
2598 
////                                                              ////
2599 
////  Versatile counter                                           ////
2600 
////                                                              ////
2601 
////  Description                                                 ////
2602 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2603 
////  counter                                                     ////
2604 
////                                                              ////
2605 
////  To Do:                                                      ////
2606 
////   - add LFSR with more taps                                  ////
2607 
////                                                              ////
2608 
////  Author(s):                                                  ////
2609 
////      - Michael Unneback, unneback@opencores.org              ////
2610 
////        ORSoC AB                                              ////
2611 
////                                                              ////
2612 
//////////////////////////////////////////////////////////////////////
2613 
////                                                              ////
2614 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2615 
////                                                              ////
2616 
//// This source file may be used and distributed without         ////
2617 
//// restriction provided that this copyright statement is not    ////
2618 
//// removed from the file and that any derivative work contains  ////
2619 
//// the original copyright notice and the associated disclaimer. ////
2620 
////                                                              ////
2621 
//// This source file is free software; you can redistribute it   ////
2622 
//// and/or modify it under the terms of the GNU Lesser General   ////
2623 
//// Public License as published by the Free Software Foundation; ////
2624 
//// either version 2.1 of the License, or (at your option) any   ////
2625 
//// later version.                                               ////
2626 
////                                                              ////
2627 
//// This source is distributed in the hope that it will be       ////
2628 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2629 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2630 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2631 
//// details.                                                     ////
2632 
////                                                              ////
2633 
//// You should have received a copy of the GNU Lesser General    ////
2634 
//// Public License along with this source; if not, download it   ////
2635 
//// from http://www.opencores.org/lgpl.shtml                     ////
2636 
////                                                              ////
2637 
//////////////////////////////////////////////////////////////////////
2638 
 
2639 
// LFSR counter
2640 
 
2641 40 unneback 
`define MODULE cnt_lfsr_ce_clear_q
2642 
module `BASE`MODULE (
2643 
`undef MODULE
2644 
 clear, cke, q, rst, clk);
2645 
 
2646 27 unneback 
   parameter length = 4;
2647 
   input clear;
2648 
   input cke;
2649 
   output [length:1] q;
2650 
   input rst;
2651 
   input clk;
2652 
 
2653 
   parameter clear_value = 0;
2654 
   parameter set_value = 1;
2655 
   parameter wrap_value = 8;
2656 
   parameter level1_value = 15;
2657 
 
2658 
   reg  [length:1] qi;
2659 
   reg lfsr_fb;
2660 
   wire [length:1] q_next;
2661 
   reg [32:1] polynom;
2662 
   integer i;
2663 
 
2664 
   always @ (qi)
2665 
   begin
2666 
        case (length)
2667 
         2: polynom = 32'b11;                               // 0x3
2668 
         3: polynom = 32'b110;                              // 0x6
2669 
         4: polynom = 32'b1100;                             // 0xC
2670 
         5: polynom = 32'b10100;                            // 0x14
2671 
         6: polynom = 32'b110000;                           // 0x30
2672 
         7: polynom = 32'b1100000;                          // 0x60
2673 
         8: polynom = 32'b10111000;                         // 0xb8
2674 
         9: polynom = 32'b100010000;                        // 0x110
2675 
        10: polynom = 32'b1001000000;                       // 0x240
2676 
        11: polynom = 32'b10100000000;                      // 0x500
2677 
        12: polynom = 32'b100000101001;                     // 0x829
2678 
        13: polynom = 32'b1000000001100;                    // 0x100C
2679 
        14: polynom = 32'b10000000010101;                   // 0x2015
2680 
        15: polynom = 32'b110000000000000;                  // 0x6000
2681 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2682 
        17: polynom = 32'b10010000000000000;                // 0x12000
2683 
        18: polynom = 32'b100000010000000000;               // 0x20400
2684 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2685 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2686 27 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2687 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2688 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2689 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2690 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2691 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2692 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2693 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2694 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2695 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2696 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2697 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2698 
        default: polynom = 32'b0;
2699 
        endcase
2700 
        lfsr_fb = qi[length];
2701 
        for (i=length-1; i>=1; i=i-1) begin
2702 
            if (polynom[i])
2703 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2704 
        end
2705 
    end
2706 
   assign q_next =  clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2707 
 
2708 
   always @ (posedge clk or posedge rst)
2709 
     if (rst)
2710 
       qi <= {length{1'b0}};
2711 
     else
2712 
     if (cke)
2713 
       qi <= q_next;
2714 
 
2715 
   assign q = qi;
2716 
 
2717 
endmodule
2718 40 unneback 
`endif
2719 
`ifdef CNT_LFSR_CE_Q_ZQ
2720 27 unneback 
//////////////////////////////////////////////////////////////////////
2721 
////                                                              ////
2722 
////  Versatile counter                                           ////
2723 
////                                                              ////
2724 
////  Description                                                 ////
2725 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2726 
////  counter                                                     ////
2727 
////                                                              ////
2728 
////  To Do:                                                      ////
2729 
////   - add LFSR with more taps                                  ////
2730 
////                                                              ////
2731 
////  Author(s):                                                  ////
2732 
////      - Michael Unneback, unneback@opencores.org              ////
2733 
////        ORSoC AB                                              ////
2734 
////                                                              ////
2735 
//////////////////////////////////////////////////////////////////////
2736 
////                                                              ////
2737 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2738 
////                                                              ////
2739 
//// This source file may be used and distributed without         ////
2740 
//// restriction provided that this copyright statement is not    ////
2741 
//// removed from the file and that any derivative work contains  ////
2742 
//// the original copyright notice and the associated disclaimer. ////
2743 
////                                                              ////
2744 
//// This source file is free software; you can redistribute it   ////
2745 
//// and/or modify it under the terms of the GNU Lesser General   ////
2746 
//// Public License as published by the Free Software Foundation; ////
2747 
//// either version 2.1 of the License, or (at your option) any   ////
2748 
//// later version.                                               ////
2749 
////                                                              ////
2750 
//// This source is distributed in the hope that it will be       ////
2751 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2752 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2753 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2754 
//// details.                                                     ////
2755 
////                                                              ////
2756 
//// You should have received a copy of the GNU Lesser General    ////
2757 
//// Public License along with this source; if not, download it   ////
2758 
//// from http://www.opencores.org/lgpl.shtml                     ////
2759 
////                                                              ////
2760 
//////////////////////////////////////////////////////////////////////
2761 
 
2762 
// LFSR counter
2763 22 unneback 
 
2764 40 unneback 
`define MODULE cnt_lfsr_ce_q_zq
2765 
module `BASE`MODULE (
2766 
`undef MODULE
2767 
 cke, q, zq, rst, clk);
2768 
 
2769 22 unneback 
   parameter length = 4;
2770 
   input cke;
2771 
   output [length:1] q;
2772 
   output reg zq;
2773 
   input rst;
2774 
   input clk;
2775 
 
2776 
   parameter clear_value = 0;
2777 
   parameter set_value = 1;
2778 
   parameter wrap_value = 8;
2779 
   parameter level1_value = 15;
2780 
 
2781 
   reg  [length:1] qi;
2782 
   reg lfsr_fb;
2783 
   wire [length:1] q_next;
2784 
   reg [32:1] polynom;
2785 
   integer i;
2786 
 
2787 
   always @ (qi)
2788 
   begin
2789 
        case (length)
2790 
         2: polynom = 32'b11;                               // 0x3
2791 
         3: polynom = 32'b110;                              // 0x6
2792 
         4: polynom = 32'b1100;                             // 0xC
2793 
         5: polynom = 32'b10100;                            // 0x14
2794 
         6: polynom = 32'b110000;                           // 0x30
2795 
         7: polynom = 32'b1100000;                          // 0x60
2796 
         8: polynom = 32'b10111000;                         // 0xb8
2797 
         9: polynom = 32'b100010000;                        // 0x110
2798 
        10: polynom = 32'b1001000000;                       // 0x240
2799 
        11: polynom = 32'b10100000000;                      // 0x500
2800 
        12: polynom = 32'b100000101001;                     // 0x829
2801 
        13: polynom = 32'b1000000001100;                    // 0x100C
2802 
        14: polynom = 32'b10000000010101;                   // 0x2015
2803 
        15: polynom = 32'b110000000000000;                  // 0x6000
2804 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2805 
        17: polynom = 32'b10010000000000000;                // 0x12000
2806 
        18: polynom = 32'b100000010000000000;               // 0x20400
2807 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2808 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2809 22 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2810 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2811 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2812 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2813 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2814 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2815 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2816 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2817 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2818 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2819 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2820 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2821 
        default: polynom = 32'b0;
2822 
        endcase
2823 
        lfsr_fb = qi[length];
2824 
        for (i=length-1; i>=1; i=i-1) begin
2825 
            if (polynom[i])
2826 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2827 
        end
2828 
    end
2829 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2830 
 
2831 
   always @ (posedge clk or posedge rst)
2832 
     if (rst)
2833 
       qi <= {length{1'b0}};
2834 
     else
2835 
     if (cke)
2836 
       qi <= q_next;
2837 
 
2838 
   assign q = qi;
2839 
 
2840 
 
2841 
   always @ (posedge clk or posedge rst)
2842 
     if (rst)
2843 
       zq <= 1'b1;
2844 
     else
2845 
     if (cke)
2846 
       zq <= q_next == {length{1'b0}};
2847 
endmodule
2848 40 unneback 
`endif
2849 
`ifdef CNT_LFSR_CE_REW_L1
2850 22 unneback 
//////////////////////////////////////////////////////////////////////
2851 
////                                                              ////
2852 
////  Versatile counter                                           ////
2853 
////                                                              ////
2854 
////  Description                                                 ////
2855 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2856 
////  counter                                                     ////
2857 
////                                                              ////
2858 
////  To Do:                                                      ////
2859 
////   - add LFSR with more taps                                  ////
2860 
////                                                              ////
2861 
////  Author(s):                                                  ////
2862 
////      - Michael Unneback, unneback@opencores.org              ////
2863 
////        ORSoC AB                                              ////
2864 
////                                                              ////
2865 
//////////////////////////////////////////////////////////////////////
2866 
////                                                              ////
2867 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2868 
////                                                              ////
2869 
//// This source file may be used and distributed without         ////
2870 
//// restriction provided that this copyright statement is not    ////
2871 
//// removed from the file and that any derivative work contains  ////
2872 
//// the original copyright notice and the associated disclaimer. ////
2873 
////                                                              ////
2874 
//// This source file is free software; you can redistribute it   ////
2875 
//// and/or modify it under the terms of the GNU Lesser General   ////
2876 
//// Public License as published by the Free Software Foundation; ////
2877 
//// either version 2.1 of the License, or (at your option) any   ////
2878 
//// later version.                                               ////
2879 
////                                                              ////
2880 
//// This source is distributed in the hope that it will be       ////
2881 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2882 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2883 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2884 
//// details.                                                     ////
2885 
////                                                              ////
2886 
//// You should have received a copy of the GNU Lesser General    ////
2887 
//// Public License along with this source; if not, download it   ////
2888 
//// from http://www.opencores.org/lgpl.shtml                     ////
2889 
////                                                              ////
2890 
//////////////////////////////////////////////////////////////////////
2891 6 unneback 
 
2892 
// LFSR counter
2893 
 
2894 40 unneback 
`define MODULE cnt_lfsr_ce_rew_l1
2895 
module `BASE`MODULE (
2896 
`undef MODULE
2897 
 cke, rew, level1, rst, clk);
2898 
 
2899 6 unneback 
   parameter length = 4;
2900 
   input cke;
2901 
   input rew;
2902 
   output reg level1;
2903 
   input rst;
2904 
   input clk;
2905 
 
2906 
   parameter clear_value = 0;
2907 
   parameter set_value = 1;
2908 
   parameter wrap_value = 8;
2909 
   parameter level1_value = 15;
2910 
 
2911 29 unneback 
   wire clear;
2912 30 unneback 
   assign clear = 1'b0;
2913 6 unneback 
   reg  [length:1] qi;
2914 
   reg lfsr_fb, lfsr_fb_rew;
2915 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2916 
   reg [32:1] polynom_rew;
2917 
   integer j;
2918 
   reg [32:1] polynom;
2919 
   integer i;
2920 
 
2921 
   always @ (qi)
2922 
   begin
2923 
        case (length)
2924 
         2: polynom = 32'b11;                               // 0x3
2925 
         3: polynom = 32'b110;                              // 0x6
2926 
         4: polynom = 32'b1100;                             // 0xC
2927 
         5: polynom = 32'b10100;                            // 0x14
2928 
         6: polynom = 32'b110000;                           // 0x30
2929 
         7: polynom = 32'b1100000;                          // 0x60
2930 
         8: polynom = 32'b10111000;                         // 0xb8
2931 
         9: polynom = 32'b100010000;                        // 0x110
2932 
        10: polynom = 32'b1001000000;                       // 0x240
2933 
        11: polynom = 32'b10100000000;                      // 0x500
2934 
        12: polynom = 32'b100000101001;                     // 0x829
2935 
        13: polynom = 32'b1000000001100;                    // 0x100C
2936 
        14: polynom = 32'b10000000010101;                   // 0x2015
2937 
        15: polynom = 32'b110000000000000;                  // 0x6000
2938 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2939 
        17: polynom = 32'b10010000000000000;                // 0x12000
2940 
        18: polynom = 32'b100000010000000000;               // 0x20400
2941 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2942 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2943 6 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2944 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2945 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2946 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2947 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2948 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2949 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2950 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2951 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2952 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2953 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2954 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2955 
        default: polynom = 32'b0;
2956 
        endcase
2957 
        lfsr_fb = qi[length];
2958 
        for (i=length-1; i>=1; i=i-1) begin
2959 
            if (polynom[i])
2960 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2961 
        end
2962 
    end
2963 
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2964 
   always @ (qi)
2965 
   begin
2966 
        case (length)
2967 
         2: polynom_rew = 32'b11;
2968 
         3: polynom_rew = 32'b110;
2969 
         4: polynom_rew = 32'b1100;
2970 
         5: polynom_rew = 32'b10100;
2971 
         6: polynom_rew = 32'b110000;
2972 
         7: polynom_rew = 32'b1100000;
2973 
         8: polynom_rew = 32'b10111000;
2974 
         9: polynom_rew = 32'b100010000;
2975 
        10: polynom_rew = 32'b1001000000;
2976 
        11: polynom_rew = 32'b10100000000;
2977 
        12: polynom_rew = 32'b100000101001;
2978 
        13: polynom_rew = 32'b1000000001100;
2979 
        14: polynom_rew = 32'b10000000010101;
2980 
        15: polynom_rew = 32'b110000000000000;
2981 
        16: polynom_rew = 32'b1101000000001000;
2982 
        17: polynom_rew = 32'b10010000000000000;
2983 
        18: polynom_rew = 32'b100000010000000000;
2984 
        19: polynom_rew = 32'b1000000000000100011;
2985 
        20: polynom_rew = 32'b10000010000000000000;
2986 
        21: polynom_rew = 32'b101000000000000000000;
2987 
        22: polynom_rew = 32'b1100000000000000000000;
2988 
        23: polynom_rew = 32'b10000100000000000000000;
2989 
        24: polynom_rew = 32'b111000010000000000000000;
2990 
        25: polynom_rew = 32'b1001000000000000000000000;
2991 
        26: polynom_rew = 32'b10000000000000000000100011;
2992 
        27: polynom_rew = 32'b100000000000000000000010011;
2993 
        28: polynom_rew = 32'b1100100000000000000000000000;
2994 
        29: polynom_rew = 32'b10100000000000000000000000000;
2995 
        30: polynom_rew = 32'b100000000000000000000000101001;
2996 
        31: polynom_rew = 32'b1001000000000000000000000000000;
2997 
        32: polynom_rew = 32'b10000000001000000000000000000011;
2998 
        default: polynom_rew = 32'b0;
2999 
        endcase
3000 
        // rotate left
3001 
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
3002 
        lfsr_fb_rew = qi[length];
3003 
        for (i=length-1; i>=1; i=i-1) begin
3004 
            if (polynom_rew[i])
3005 
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
3006 
        end
3007 
    end
3008 
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
3009 
   assign q_next = rew ? q_next_rew : q_next_fw;
3010 
 
3011 
   always @ (posedge clk or posedge rst)
3012 
     if (rst)
3013 
       qi <= {length{1'b0}};
3014 
     else
3015 
     if (cke)
3016 
       qi <= q_next;
3017 
 
3018 
 
3019 
 
3020 
    always @ (posedge clk or posedge rst)
3021 
    if (rst)
3022 
        level1 <= 1'b0;
3023 
    else
3024 
    if (cke)
3025 29 unneback 
    if (clear)
3026 
        level1 <= 1'b0;
3027 
    else if (q_next == level1_value)
3028 6 unneback 
        level1 <= 1'b1;
3029 
    else if (qi == level1_value & rew)
3030 
        level1 <= 1'b0;
3031 
endmodule
3032 40 unneback 
`endif
3033 
`ifdef CNT_GRAY
3034 6 unneback 
//////////////////////////////////////////////////////////////////////
3035 
////                                                              ////
3036 
////  Versatile counter                                           ////
3037 
////                                                              ////
3038 
////  Description                                                 ////
3039 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3040 
////  counter                                                     ////
3041 
////                                                              ////
3042 
////  To Do:                                                      ////
3043 
////   - add LFSR with more taps                                  ////
3044 
////                                                              ////
3045 
////  Author(s):                                                  ////
3046 
////      - Michael Unneback, unneback@opencores.org              ////
3047 
////        ORSoC AB                                              ////
3048 
////                                                              ////
3049 
//////////////////////////////////////////////////////////////////////
3050 
////                                                              ////
3051 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3052 
////                                                              ////
3053 
//// This source file may be used and distributed without         ////
3054 
//// restriction provided that this copyright statement is not    ////
3055 
//// removed from the file and that any derivative work contains  ////
3056 
//// the original copyright notice and the associated disclaimer. ////
3057 
////                                                              ////
3058 
//// This source file is free software; you can redistribute it   ////
3059 
//// and/or modify it under the terms of the GNU Lesser General   ////
3060 
//// Public License as published by the Free Software Foundation; ////
3061 
//// either version 2.1 of the License, or (at your option) any   ////
3062 
//// later version.                                               ////
3063 
////                                                              ////
3064 
//// This source is distributed in the hope that it will be       ////
3065 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3066 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3067 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3068 
//// details.                                                     ////
3069 
////                                                              ////
3070 
//// You should have received a copy of the GNU Lesser General    ////
3071 
//// Public License along with this source; if not, download it   ////
3072 
//// from http://www.opencores.org/lgpl.shtml                     ////
3073 
////                                                              ////
3074 
//////////////////////////////////////////////////////////////////////
3075 
 
3076 
// GRAY counter
3077 
 
3078 40 unneback 
`define MODULE cnt_gray
3079 
module `BASE`MODULE (
3080 
`undef MODULE
3081 
 q, rst, clk);
3082 
 
3083 6 unneback 
   parameter length = 4;
3084 
   output reg [length:1] q;
3085 
   input rst;
3086 
   input clk;
3087 
 
3088 
   parameter clear_value = 0;
3089 
   parameter set_value = 1;
3090 
   parameter wrap_value = 8;
3091 
   parameter level1_value = 15;
3092 
 
3093 
   reg  [length:1] qi;
3094 
   wire [length:1] q_next;
3095 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3096 
 
3097 
   always @ (posedge clk or posedge rst)
3098 
     if (rst)
3099 
       qi <= {length{1'b0}};
3100 
     else
3101 
       qi <= q_next;
3102 
 
3103 
   always @ (posedge clk or posedge rst)
3104 
     if (rst)
3105 
       q <= {length{1'b0}};
3106 
     else
3107 
         q <= (q_next>>1) ^ q_next;
3108 
 
3109 
endmodule
3110 40 unneback 
`endif
3111 
`ifdef CNT_GRAY_CE
3112 6 unneback 
//////////////////////////////////////////////////////////////////////
3113 
////                                                              ////
3114 
////  Versatile counter                                           ////
3115 
////                                                              ////
3116 
////  Description                                                 ////
3117 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3118 
////  counter                                                     ////
3119 
////                                                              ////
3120 
////  To Do:                                                      ////
3121 
////   - add LFSR with more taps                                  ////
3122 
////                                                              ////
3123 
////  Author(s):                                                  ////
3124 
////      - Michael Unneback, unneback@opencores.org              ////
3125 
////        ORSoC AB                                              ////
3126 
////                                                              ////
3127 
//////////////////////////////////////////////////////////////////////
3128 
////                                                              ////
3129 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3130 
////                                                              ////
3131 
//// This source file may be used and distributed without         ////
3132 
//// restriction provided that this copyright statement is not    ////
3133 
//// removed from the file and that any derivative work contains  ////
3134 
//// the original copyright notice and the associated disclaimer. ////
3135 
////                                                              ////
3136 
//// This source file is free software; you can redistribute it   ////
3137 
//// and/or modify it under the terms of the GNU Lesser General   ////
3138 
//// Public License as published by the Free Software Foundation; ////
3139 
//// either version 2.1 of the License, or (at your option) any   ////
3140 
//// later version.                                               ////
3141 
////                                                              ////
3142 
//// This source is distributed in the hope that it will be       ////
3143 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3144 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3145 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3146 
//// details.                                                     ////
3147 
////                                                              ////
3148 
//// You should have received a copy of the GNU Lesser General    ////
3149 
//// Public License along with this source; if not, download it   ////
3150 
//// from http://www.opencores.org/lgpl.shtml                     ////
3151 
////                                                              ////
3152 
//////////////////////////////////////////////////////////////////////
3153 
 
3154 
// GRAY counter
3155 
 
3156 40 unneback 
`define MODULE cnt_gray_ce
3157 
module `BASE`MODULE (
3158 
`undef MODULE
3159 
 cke, q, rst, clk);
3160 
 
3161 6 unneback 
   parameter length = 4;
3162 
   input cke;
3163 
   output reg [length:1] q;
3164 
   input rst;
3165 
   input clk;
3166 
 
3167 
   parameter clear_value = 0;
3168 
   parameter set_value = 1;
3169 
   parameter wrap_value = 8;
3170 
   parameter level1_value = 15;
3171 
 
3172 
   reg  [length:1] qi;
3173 
   wire [length:1] q_next;
3174 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3175 
 
3176 
   always @ (posedge clk or posedge rst)
3177 
     if (rst)
3178 
       qi <= {length{1'b0}};
3179 
     else
3180 
     if (cke)
3181 
       qi <= q_next;
3182 
 
3183 
   always @ (posedge clk or posedge rst)
3184 
     if (rst)
3185 
       q <= {length{1'b0}};
3186 
     else
3187 
       if (cke)
3188 
         q <= (q_next>>1) ^ q_next;
3189 
 
3190 
endmodule
3191 40 unneback 
`endif
3192 
`ifdef CNT_GRAY_CE_BIN
3193 6 unneback 
//////////////////////////////////////////////////////////////////////
3194 
////                                                              ////
3195 
////  Versatile counter                                           ////
3196 
////                                                              ////
3197 
////  Description                                                 ////
3198 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3199 
////  counter                                                     ////
3200 
////                                                              ////
3201 
////  To Do:                                                      ////
3202 
////   - add LFSR with more taps                                  ////
3203 
////                                                              ////
3204 
////  Author(s):                                                  ////
3205 
////      - Michael Unneback, unneback@opencores.org              ////
3206 
////        ORSoC AB                                              ////
3207 
////                                                              ////
3208 
//////////////////////////////////////////////////////////////////////
3209 
////                                                              ////
3210 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3211 
////                                                              ////
3212 
//// This source file may be used and distributed without         ////
3213 
//// restriction provided that this copyright statement is not    ////
3214 
//// removed from the file and that any derivative work contains  ////
3215 
//// the original copyright notice and the associated disclaimer. ////
3216 
////                                                              ////
3217 
//// This source file is free software; you can redistribute it   ////
3218 
//// and/or modify it under the terms of the GNU Lesser General   ////
3219 
//// Public License as published by the Free Software Foundation; ////
3220 
//// either version 2.1 of the License, or (at your option) any   ////
3221 
//// later version.                                               ////
3222 
////                                                              ////
3223 
//// This source is distributed in the hope that it will be       ////
3224 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3225 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3226 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3227 
//// details.                                                     ////
3228 
////                                                              ////
3229 
//// You should have received a copy of the GNU Lesser General    ////
3230 
//// Public License along with this source; if not, download it   ////
3231 
//// from http://www.opencores.org/lgpl.shtml                     ////
3232 
////                                                              ////
3233 
//////////////////////////////////////////////////////////////////////
3234 
 
3235 
// GRAY counter
3236 
 
3237 40 unneback 
`define MODULE cnt_gray_ce_bin
3238 
module `BASE`MODULE (
3239 
`undef MODULE
3240 
 cke, q, q_bin, rst, clk);
3241 
 
3242 6 unneback 
   parameter length = 4;
3243 
   input cke;
3244 
   output reg [length:1] q;
3245 
   output [length:1] q_bin;
3246 
   input rst;
3247 
   input clk;
3248 
 
3249 
   parameter clear_value = 0;
3250 
   parameter set_value = 1;
3251 
   parameter wrap_value = 8;
3252 
   parameter level1_value = 15;
3253 
 
3254 
   reg  [length:1] qi;
3255 
   wire [length:1] q_next;
3256 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3257 
 
3258 
   always @ (posedge clk or posedge rst)
3259 
     if (rst)
3260 
       qi <= {length{1'b0}};
3261 
     else
3262 
     if (cke)
3263 
       qi <= q_next;
3264 
 
3265 
   always @ (posedge clk or posedge rst)
3266 
     if (rst)
3267 
       q <= {length{1'b0}};
3268 
     else
3269 
       if (cke)
3270 
         q <= (q_next>>1) ^ q_next;
3271 
 
3272 
   assign q_bin = qi;
3273 
 
3274 
endmodule
3275 40 unneback 
`endif
3276 6 unneback 
//////////////////////////////////////////////////////////////////////
3277 
////                                                              ////
3278 
////  Versatile library, counters                                 ////
3279 
////                                                              ////
3280 
////  Description                                                 ////
3281 
////  counters                                                    ////
3282 
////                                                              ////
3283 
////                                                              ////
3284 
////  To Do:                                                      ////
3285 
////   - add more counters                                        ////
3286 
////                                                              ////
3287 
////  Author(s):                                                  ////
3288 
////      - Michael Unneback, unneback@opencores.org              ////
3289 
////        ORSoC AB                                              ////
3290 
////                                                              ////
3291 
//////////////////////////////////////////////////////////////////////
3292 
////                                                              ////
3293 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
3294 
////                                                              ////
3295 
//// This source file may be used and distributed without         ////
3296 
//// restriction provided that this copyright statement is not    ////
3297 
//// removed from the file and that any derivative work contains  ////
3298 
//// the original copyright notice and the associated disclaimer. ////
3299 
////                                                              ////
3300 
//// This source file is free software; you can redistribute it   ////
3301 
//// and/or modify it under the terms of the GNU Lesser General   ////
3302 
//// Public License as published by the Free Software Foundation; ////
3303 
//// either version 2.1 of the License, or (at your option) any   ////
3304 
//// later version.                                               ////
3305 
////                                                              ////
3306 
//// This source is distributed in the hope that it will be       ////
3307 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3308 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3309 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3310 
//// details.                                                     ////
3311 
////                                                              ////
3312 
//// You should have received a copy of the GNU Lesser General    ////
3313 
//// Public License along with this source; if not, download it   ////
3314 
//// from http://www.opencores.org/lgpl.shtml                     ////
3315 
////                                                              ////
3316 
//////////////////////////////////////////////////////////////////////
3317 
 
3318 40 unneback 
`ifdef CNT_SHREG_WRAP
3319 
`define MODULE cnt_shreg_wrap
3320 
module `BASE`MODULE ( q, rst, clk);
3321 
`undef MODULE
3322 6 unneback 
 
3323 
   parameter length = 4;
3324 
   output reg [0:length-1] q;
3325 
   input rst;
3326 
   input clk;
3327 
 
3328 
    always @ (posedge clk or posedge rst)
3329 
    if (rst)
3330 
        q <= {1'b1,{length-1{1'b0}}};
3331 
    else
3332 
        q <= {q[length-1],q[0:length-2]};
3333 
 
3334 
endmodule
3335 40 unneback 
`endif
3336 6 unneback 
 
3337 40 unneback 
`ifdef CNT_SHREG_CE_WRAP
3338 
`define MODULE cnt_shreg_ce_wrap
3339 
module `BASE`MODULE ( cke, q, rst, clk);
3340 
`undef MODULE
3341 6 unneback 
 
3342 
   parameter length = 4;
3343 
   input cke;
3344 
   output reg [0:length-1] q;
3345 
   input rst;
3346 
   input clk;
3347 
 
3348 
    always @ (posedge clk or posedge rst)
3349 
    if (rst)
3350 
        q <= {1'b1,{length-1{1'b0}}};
3351 
    else
3352 
        if (cke)
3353 
            q <= {q[length-1],q[0:length-2]};
3354 
 
3355 
endmodule
3356 40 unneback 
`endif
3357 6 unneback 
 
3358 40 unneback 
`ifdef CNT_SHREG_CE_CLEAR
3359 
`define MODULE cnt_shreg_ce_clear
3360 
module `BASE`MODULE ( cke, clear, q, rst, clk);
3361 
`undef MODULE
3362 6 unneback 
 
3363 
   parameter length = 4;
3364 
   input cke, clear;
3365 
   output reg [0:length-1] q;
3366 
   input rst;
3367 
   input clk;
3368 
 
3369 
    always @ (posedge clk or posedge rst)
3370 
    if (rst)
3371 
        q <= {1'b1,{length-1{1'b0}}};
3372 
    else
3373 
        if (cke)
3374 
            if (clear)
3375 
                q <= {1'b1,{length-1{1'b0}}};
3376 
            else
3377 
                q <= q >> 1;
3378 
 
3379 
endmodule
3380 40 unneback 
`endif
3381 6 unneback 
 
3382 40 unneback 
`ifdef CNT_SHREG_CE_CLEAR_WRAP
3383 
`define MODULE cnt_shreg_ce_clear_wrap
3384 
module `BASE`MODULE ( cke, clear, q, rst, clk);
3385 
`undef MODULE
3386 6 unneback 
 
3387 
   parameter length = 4;
3388 
   input cke, clear;
3389 
   output reg [0:length-1] q;
3390 
   input rst;
3391 
   input clk;
3392 
 
3393 
    always @ (posedge clk or posedge rst)
3394 
    if (rst)
3395 
        q <= {1'b1,{length-1{1'b0}}};
3396 
    else
3397 
        if (cke)
3398 
            if (clear)
3399 
                q <= {1'b1,{length-1{1'b0}}};
3400 
            else
3401 
            q <= {q[length-1],q[0:length-2]};
3402 
 
3403 
endmodule
3404 40 unneback 
`endif
3405 6 unneback 
//////////////////////////////////////////////////////////////////////
3406 
////                                                              ////
3407 
////  Versatile library, memories                                 ////
3408 
////                                                              ////
3409 
////  Description                                                 ////
3410 
////  memories                                                    ////
3411 
////                                                              ////
3412 
////                                                              ////
3413 
////  To Do:                                                      ////
3414 
////   - add more memory types                                    ////
3415 
////                                                              ////
3416 
////  Author(s):                                                  ////
3417 
////      - Michael Unneback, unneback@opencores.org              ////
3418 
////        ORSoC AB                                              ////
3419 
////                                                              ////
3420 
//////////////////////////////////////////////////////////////////////
3421 
////                                                              ////
3422 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
3423 
////                                                              ////
3424 
//// This source file may be used and distributed without         ////
3425 
//// restriction provided that this copyright statement is not    ////
3426 
//// removed from the file and that any derivative work contains  ////
3427 
//// the original copyright notice and the associated disclaimer. ////
3428 
////                                                              ////
3429 
//// This source file is free software; you can redistribute it   ////
3430 
//// and/or modify it under the terms of the GNU Lesser General   ////
3431 
//// Public License as published by the Free Software Foundation; ////
3432 
//// either version 2.1 of the License, or (at your option) any   ////
3433 
//// later version.                                               ////
3434 
////                                                              ////
3435 
//// This source is distributed in the hope that it will be       ////
3436 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3437 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3438 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3439 
//// details.                                                     ////
3440 
////                                                              ////
3441 
//// You should have received a copy of the GNU Lesser General    ////
3442 
//// Public License along with this source; if not, download it   ////
3443 
//// from http://www.opencores.org/lgpl.shtml                     ////
3444 
////                                                              ////
3445 
//////////////////////////////////////////////////////////////////////
3446 
 
3447 40 unneback 
`ifdef ROM_INIT
3448 6 unneback 
/// ROM
3449 40 unneback 
`define MODULE rom_init
3450 
module `BASE`MODULE ( adr, q, clk);
3451 
`undef MODULE
3452 6 unneback 
 
3453 7 unneback 
   parameter data_width = 32;
3454 
   parameter addr_width = 8;
3455 
   input [(addr_width-1):0]       adr;
3456 
   output reg [(data_width-1):0] q;
3457 
   input                         clk;
3458 
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
3459 
   parameter memory_file = "vl_rom.vmem";
3460 
   initial
3461 
     begin
3462 
        $readmemh(memory_file, rom);
3463 
     end
3464 
 
3465 
   always @ (posedge clk)
3466 
     q <= rom[adr];
3467 6 unneback 
 
3468 7 unneback 
endmodule
3469 40 unneback 
`endif
3470 7 unneback 
 
3471 40 unneback 
`ifdef RAM
3472 
`define MODULE ram
3473 6 unneback 
// Single port RAM
3474 40 unneback 
module `BASE`MODULE ( d, adr, we, q, clk);
3475 
`undef MODULE
3476 6 unneback 
 
3477 
   parameter data_width = 32;
3478 
   parameter addr_width = 8;
3479 
   input [(data_width-1):0]      d;
3480 
   input [(addr_width-1):0]       adr;
3481 
   input                         we;
3482 7 unneback 
   output reg [(data_width-1):0] q;
3483 6 unneback 
   input                         clk;
3484 
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
3485 7 unneback 
   parameter init = 0;
3486 
   parameter memory_file = "vl_ram.vmem";
3487 
   generate if (init) begin : init_mem
3488 
   initial
3489 
     begin
3490 
        $readmemh(memory_file, ram);
3491 
     end
3492 
   end
3493 
   endgenerate
3494 
 
3495 6 unneback 
   always @ (posedge clk)
3496 
   begin
3497 
   if (we)
3498 
     ram[adr] <= d;
3499 
   q <= ram[adr];
3500 
   end
3501 
 
3502 
endmodule
3503 40 unneback 
`endif
3504 6 unneback 
 
3505 40 unneback 
`ifdef RAM_BE
3506 
`define MODULE ram_be
3507 
module `BASE`MODULE ( d, adr, be, we, q, clk);
3508 
`undef MODULE
3509 
 
3510 7 unneback 
   parameter data_width = 32;
3511 
   parameter addr_width = 8;
3512 
   input [(data_width-1):0]      d;
3513 
   input [(addr_width-1):0]       adr;
3514 
   input [(addr_width/4)-1:0]    be;
3515 
   input                         we;
3516 
   output reg [(data_width-1):0] q;
3517 
   input                         clk;
3518 
 
3519 
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
3520 
 
3521 
   parameter init = 0;
3522 
   parameter memory_file = "vl_ram.vmem";
3523 
   generate if (init) begin : init_mem
3524 
   initial
3525 
     begin
3526 
        $readmemh(memory_file, ram);
3527 
     end
3528 
   end
3529 
   endgenerate
3530 
 
3531 
   genvar i;
3532 
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
3533 
      always @ (posedge clk)
3534 
      if (we & be[i])
3535 
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
3536 
   end
3537 
   endgenerate
3538 
 
3539 
   always @ (posedge clk)
3540 
      q <= ram[adr];
3541 
 
3542 
endmodule
3543 40 unneback 
`endif
3544 7 unneback 
 
3545 6 unneback 
`ifdef ACTEL
3546 48 unneback 
        // ACTEL FPGA should not use logic to handle rw collision
3547 6 unneback 
        `define SYN /*synthesis syn_ramstyle = "no_rw_check"*/
3548 
`else
3549 
        `define SYN
3550 
`endif
3551 
 
3552 40 unneback 
`ifdef DPRAM_1R1W
3553 
`define MODULE dpram_1r1w
3554 
module `BASE`MODULE ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
3555 
`undef MODULE
3556 6 unneback 
   parameter data_width = 32;
3557 
   parameter addr_width = 8;
3558 
   input [(data_width-1):0]      d_a;
3559 
   input [(addr_width-1):0]       adr_a;
3560 
   input [(addr_width-1):0]       adr_b;
3561 
   input                         we_a;
3562 
   output [(data_width-1):0]      q_b;
3563 
   input                         clk_a, clk_b;
3564 
   reg [(addr_width-1):0]         adr_b_reg;
3565 
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
3566 7 unneback 
 
3567 
   parameter init = 0;
3568 
   parameter memory_file = "vl_ram.vmem";
3569 
   generate if (init) begin : init_mem
3570 
   initial
3571 
     begin
3572 
        $readmemh(memory_file, ram);
3573 
     end
3574 
   end
3575 
   endgenerate
3576 
 
3577 6 unneback 
   always @ (posedge clk_a)
3578 
   if (we_a)
3579 
     ram[adr_a] <= d_a;
3580 
   always @ (posedge clk_b)
3581 
   adr_b_reg <= adr_b;
3582 
   assign q_b = ram[adr_b_reg];
3583 40 unneback 
 
3584 6 unneback 
endmodule
3585 40 unneback 
`endif
3586 6 unneback 
 
3587 40 unneback 
`ifdef DPRAM_2R1W
3588 
`define MODULE dpram_2r1w
3589 
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
3590 
`undef MODULE
3591 
 
3592 6 unneback 
   parameter data_width = 32;
3593 
   parameter addr_width = 8;
3594 
   input [(data_width-1):0]      d_a;
3595 
   input [(addr_width-1):0]       adr_a;
3596 
   input [(addr_width-1):0]       adr_b;
3597 
   input                         we_a;
3598 
   output [(data_width-1):0]      q_b;
3599 
   output reg [(data_width-1):0] q_a;
3600 
   input                         clk_a, clk_b;
3601 
   reg [(data_width-1):0]         q_b;
3602 
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
3603 7 unneback 
 
3604 
   parameter init = 0;
3605 
   parameter memory_file = "vl_ram.vmem";
3606 
   generate if (init) begin : init_mem
3607 
   initial
3608 
     begin
3609 
        $readmemh(memory_file, ram);
3610 
     end
3611 
   end
3612 
   endgenerate
3613 
 
3614 6 unneback 
   always @ (posedge clk_a)
3615 
     begin
3616 
        q_a <= ram[adr_a];
3617 
        if (we_a)
3618 
             ram[adr_a] <= d_a;
3619 
     end
3620 
   always @ (posedge clk_b)
3621 
          q_b <= ram[adr_b];
3622 
endmodule
3623 40 unneback 
`endif
3624 6 unneback 
 
3625 40 unneback 
`ifdef DPRAM_2R2W
3626 
`define MODULE dpram_2r2w
3627 
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
3628 
`undef MODULE
3629 
 
3630 6 unneback 
   parameter data_width = 32;
3631 
   parameter addr_width = 8;
3632 
   input [(data_width-1):0]      d_a;
3633 
   input [(addr_width-1):0]       adr_a;
3634 
   input [(addr_width-1):0]       adr_b;
3635 
   input                         we_a;
3636 
   output [(data_width-1):0]      q_b;
3637 
   input [(data_width-1):0]       d_b;
3638 
   output reg [(data_width-1):0] q_a;
3639 
   input                         we_b;
3640 
   input                         clk_a, clk_b;
3641 
   reg [(data_width-1):0]         q_b;
3642 
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
3643 7 unneback 
 
3644 
   parameter init = 0;
3645 
   parameter memory_file = "vl_ram.vmem";
3646 
   generate if (init) begin : init_mem
3647 
   initial
3648 
     begin
3649 
        $readmemh(memory_file, ram);
3650 
     end
3651 
   end
3652 
   endgenerate
3653 
 
3654 6 unneback 
   always @ (posedge clk_a)
3655 
     begin
3656 
        q_a <= ram[adr_a];
3657 
        if (we_a)
3658 
             ram[adr_a] <= d_a;
3659 
     end
3660 
   always @ (posedge clk_b)
3661 
     begin
3662 
        q_b <= ram[adr_b];
3663 
        if (we_b)
3664 
          ram[adr_b] <= d_b;
3665 
     end
3666 
endmodule
3667 40 unneback 
`endif
3668 6 unneback 
 
3669 
// Content addresable memory, CAM
3670 
 
3671 40 unneback 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
3672 6 unneback 
// FIFO
3673 40 unneback 
`define MODULE fifo_1r1w_fill_level_sync
3674 
module `BASE`MODULE (
3675 
`undef MODULE
3676 25 unneback 
    d, wr, fifo_full,
3677 
    q, rd, fifo_empty,
3678 
    fill_level,
3679 
    clk, rst
3680 
    );
3681 
 
3682 
parameter data_width = 18;
3683 
parameter addr_width = 4;
3684 6 unneback 
 
3685 25 unneback 
// write side
3686 
input  [data_width-1:0] d;
3687 
input                   wr;
3688 
output                  fifo_full;
3689 
// read side
3690 
output [data_width-1:0] q;
3691 
input                   rd;
3692 
output                  fifo_empty;
3693 
// common
3694 
output [addr_width:0]   fill_level;
3695 
input rst, clk;
3696 
 
3697 
wire [addr_width:1] wadr, radr;
3698 
 
3699 40 unneback 
`define MODULE cnt_bin_ce
3700 
`BASE`MODULE
3701 25 unneback 
    # ( .length(addr_width))
3702 
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
3703 40 unneback 
`BASE`MODULE
3704 25 unneback 
    # (.length(addr_width))
3705 
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
3706 40 unneback 
`undef MODULE
3707 25 unneback 
 
3708 40 unneback 
`define MODULE dpram_1r1w
3709 
`BASE`MODULE
3710 25 unneback 
    # (.data_width(data_width), .addr_width(addr_width))
3711 
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
3712 40 unneback 
`undef MODULE
3713 25 unneback 
 
3714 40 unneback 
`define MODULE cnt_bin_ce_rew_q_zq_l1
3715 
`BASE`MODULE
3716 27 unneback 
    # (.length(addr_width+1), .level1_value(1<<addr_width))
3717 25 unneback 
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
3718 40 unneback 
`undef MODULE
3719 25 unneback 
endmodule
3720 40 unneback 
`endif
3721 25 unneback 
 
3722 40 unneback 
`ifdef FIFO_2R2W_SYNC_SIMPLEX
3723 27 unneback 
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
3724 
// RAM is supposed to be larger than the two FIFOs
3725 
// LFSR counters used adr pointers
3726 40 unneback 
`define MODULE fifo_2r2w_sync_simplex
3727 
module `BASE`MODULE (
3728 
`undef MODULE
3729 27 unneback 
    // a side
3730 
    a_d, a_wr, a_fifo_full,
3731 
    a_q, a_rd, a_fifo_empty,
3732 
    a_fill_level,
3733 
    // b side
3734 
    b_d, b_wr, b_fifo_full,
3735 
    b_q, b_rd, b_fifo_empty,
3736 
    b_fill_level,
3737 
    // common
3738 
    clk, rst
3739 
    );
3740 
parameter data_width = 8;
3741 
parameter addr_width = 5;
3742 
parameter fifo_full_level = (1<<addr_width)-1;
3743 
 
3744 
// a side
3745 
input  [data_width-1:0] a_d;
3746 
input                   a_wr;
3747 
output                  a_fifo_full;
3748 
output [data_width-1:0] a_q;
3749 
input                   a_rd;
3750 
output                  a_fifo_empty;
3751 
output [addr_width-1:0] a_fill_level;
3752 
 
3753 
// b side
3754 
input  [data_width-1:0] b_d;
3755 
input                   b_wr;
3756 
output                  b_fifo_full;
3757 
output [data_width-1:0] b_q;
3758 
input                   b_rd;
3759 
output                  b_fifo_empty;
3760 
output [addr_width-1:0] b_fill_level;
3761 
 
3762 
input                   clk;
3763 
input                   rst;
3764 
 
3765 
// adr_gen
3766 
wire [addr_width:1] a_wadr, a_radr;
3767 
wire [addr_width:1] b_wadr, b_radr;
3768 
// dpram
3769 
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
3770 
 
3771 40 unneback 
`define MODULE cnt_lfsr_ce
3772 
`BASE`MODULE
3773 27 unneback 
    # ( .length(addr_width))
3774 
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
3775 
 
3776 40 unneback 
`BASE`MODULE
3777 27 unneback 
    # (.length(addr_width))
3778 
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
3779 
 
3780 40 unneback 
`BASE`MODULE
3781 27 unneback 
    # ( .length(addr_width))
3782 
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
3783 
 
3784 40 unneback 
`BASE`MODULE
3785 27 unneback 
    # (.length(addr_width))
3786 
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
3787 40 unneback 
`undef MODULE
3788 27 unneback 
 
3789 
// mux read or write adr to DPRAM
3790 
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
3791 
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
3792 
 
3793 40 unneback 
`define MODULE dpram_2r2w
3794 
`BASE`MODULE
3795 27 unneback 
    # (.data_width(data_width), .addr_width(addr_width+1))
3796 
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
3797 
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
3798 40 unneback 
`undef MODULE
3799 
 
3800 
`define MODULE cnt_bin_ce_rew_zq_l1
3801 
`BASE`MODULE
3802 28 unneback 
    # (.length(addr_width), .level1_value(fifo_full_level))
3803 27 unneback 
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
3804 
 
3805 40 unneback 
`BASE`MODULE
3806 28 unneback 
    # (.length(addr_width), .level1_value(fifo_full_level))
3807 27 unneback 
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
3808 40 unneback 
`undef MODULE
3809 27 unneback 
 
3810 
endmodule
3811 40 unneback 
`endif
3812 27 unneback 
 
3813 40 unneback 
`ifdef FIFO_CMP_ASYNC
3814 
`define MODULE fifo_cmp_async
3815 
module `BASE`MODULE ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
3816 
`undef MODULE
3817 6 unneback 
 
3818 11 unneback 
   parameter addr_width = 4;
3819 
   parameter N = addr_width-1;
3820 6 unneback 
 
3821 
   parameter Q1 = 2'b00;
3822 
   parameter Q2 = 2'b01;
3823 
   parameter Q3 = 2'b11;
3824 
   parameter Q4 = 2'b10;
3825 
 
3826 
   parameter going_empty = 1'b0;
3827 
   parameter going_full  = 1'b1;
3828 
 
3829 
   input [N:0]  wptr, rptr;
3830 14 unneback 
   output       fifo_empty;
3831 6 unneback 
   output       fifo_full;
3832 
   input        wclk, rclk, rst;
3833 
 
3834 
`ifndef GENERATE_DIRECTION_AS_LATCH
3835 
   wire direction;
3836 
`endif
3837 
`ifdef GENERATE_DIRECTION_AS_LATCH
3838 
   reg direction;
3839 
`endif
3840 
   reg  direction_set, direction_clr;
3841 
 
3842 
   wire async_empty, async_full;
3843 
   wire fifo_full2;
3844 14 unneback 
   wire fifo_empty2;
3845 6 unneback 
 
3846 
   // direction_set
3847 
   always @ (wptr[N:N-1] or rptr[N:N-1])
3848 
     case ({wptr[N:N-1],rptr[N:N-1]})
3849 
       {Q1,Q2} : direction_set <= 1'b1;
3850 
       {Q2,Q3} : direction_set <= 1'b1;
3851 
       {Q3,Q4} : direction_set <= 1'b1;
3852 
       {Q4,Q1} : direction_set <= 1'b1;
3853 
       default : direction_set <= 1'b0;
3854 
     endcase
3855 
 
3856 
   // direction_clear
3857 
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
3858 
     if (rst)
3859 
       direction_clr <= 1'b1;
3860 
     else
3861 
       case ({wptr[N:N-1],rptr[N:N-1]})
3862 
         {Q2,Q1} : direction_clr <= 1'b1;
3863 
         {Q3,Q2} : direction_clr <= 1'b1;
3864 
         {Q4,Q3} : direction_clr <= 1'b1;
3865 
         {Q1,Q4} : direction_clr <= 1'b1;
3866 
         default : direction_clr <= 1'b0;
3867 
       endcase
3868 
 
3869 40 unneback 
`define MODULE dff_sr
3870 6 unneback 
`ifndef GENERATE_DIRECTION_AS_LATCH
3871 40 unneback 
    `BASE`MODULE dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
3872 6 unneback 
`endif
3873 
 
3874 
`ifdef GENERATE_DIRECTION_AS_LATCH
3875 
   always @ (posedge direction_set or posedge direction_clr)
3876 
     if (direction_clr)
3877 
       direction <= going_empty;
3878 
     else
3879 
       direction <= going_full;
3880 
`endif
3881 
 
3882 
   assign async_empty = (wptr == rptr) && (direction==going_empty);
3883 
   assign async_full  = (wptr == rptr) && (direction==going_full);
3884 
 
3885 40 unneback 
    `BASE`MODULE dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
3886 
    `BASE`MODULE dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
3887 
`undef MODULE
3888 6 unneback 
 
3889 
/*
3890 
   always @ (posedge wclk or posedge rst or posedge async_full)
3891 
     if (rst)
3892 
       {fifo_full, fifo_full2} <= 2'b00;
3893 
     else if (async_full)
3894 
       {fifo_full, fifo_full2} <= 2'b11;
3895 
     else
3896 
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
3897 
*/
3898 14 unneback 
/*   always @ (posedge rclk or posedge async_empty)
3899 6 unneback 
     if (async_empty)
3900 
       {fifo_empty, fifo_empty2} <= 2'b11;
3901 
     else
3902 14 unneback 
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
3903 40 unneback 
`define MODULE dff
3904 
    `BASE`MODULE # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
3905 
    `BASE`MODULE # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
3906 
`undef MODULE
3907 27 unneback 
endmodule // async_compb
3908 40 unneback 
`endif
3909 6 unneback 
 
3910 40 unneback 
`ifdef FIFO_1R1W_ASYNC
3911 
`define MODULE fifo_1r1w_async
3912 
module `BASE`MODULE (
3913 
`undef MODULE
3914 6 unneback 
    d, wr, fifo_full, wr_clk, wr_rst,
3915 
    q, rd, fifo_empty, rd_clk, rd_rst
3916 
    );
3917 
 
3918 
parameter data_width = 18;
3919 
parameter addr_width = 4;
3920 
 
3921 
// write side
3922 
input  [data_width-1:0] d;
3923 
input                   wr;
3924 
output                  fifo_full;
3925 
input                   wr_clk;
3926 
input                   wr_rst;
3927 
// read side
3928 
output [data_width-1:0] q;
3929 
input                   rd;
3930 
output                  fifo_empty;
3931 
input                   rd_clk;
3932 
input                   rd_rst;
3933 
 
3934 
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
3935 23 unneback 
 
3936 40 unneback 
`define MODULE cnt_gray_ce_bin
3937 
`BASE`MODULE
3938 6 unneback 
    # ( .length(addr_width))
3939 
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
3940 
 
3941 40 unneback 
`BASE`MODULE
3942 6 unneback 
    # (.length(addr_width))
3943 23 unneback 
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
3944 40 unneback 
`undef MODULE
3945 6 unneback 
 
3946 40 unneback 
`define MODULE dpram_1r1w
3947 
`BASE`MODULE
3948 6 unneback 
    # (.data_width(data_width), .addr_width(addr_width))
3949 
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
3950 40 unneback 
`undef MODULE
3951 6 unneback 
 
3952 40 unneback 
`define MODULE fifo_cmp_async
3953 
`BASE`MODULE
3954 6 unneback 
    # (.addr_width(addr_width))
3955 
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
3956 40 unneback 
`undef MODULE
3957 6 unneback 
 
3958 
endmodule
3959 40 unneback 
`endif
3960 6 unneback 
 
3961 40 unneback 
`ifdef FIFO_2R2W_ASYNC
3962 
`define MODULE fifo_2r2w_async
3963 
module `BASE`MODULE (
3964 
`undef MODULE
3965 6 unneback 
    // a side
3966 
    a_d, a_wr, a_fifo_full,
3967 
    a_q, a_rd, a_fifo_empty,
3968 
    a_clk, a_rst,
3969 
    // b side
3970 
    b_d, b_wr, b_fifo_full,
3971 
    b_q, b_rd, b_fifo_empty,
3972 
    b_clk, b_rst
3973 
    );
3974 
 
3975 
parameter data_width = 18;
3976 
parameter addr_width = 4;
3977 
 
3978 
// a side
3979 
input  [data_width-1:0] a_d;
3980 
input                   a_wr;
3981 
output                  a_fifo_full;
3982 
output [data_width-1:0] a_q;
3983 
input                   a_rd;
3984 
output                  a_fifo_empty;
3985 
input                   a_clk;
3986 
input                   a_rst;
3987 
 
3988 
// b side
3989 
input  [data_width-1:0] b_d;
3990 
input                   b_wr;
3991 
output                  b_fifo_full;
3992 
output [data_width-1:0] b_q;
3993 
input                   b_rd;
3994 
output                  b_fifo_empty;
3995 
input                   b_clk;
3996 
input                   b_rst;
3997 
 
3998 40 unneback 
`define MODULE fifo_1r1w_async
3999 
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
4000 6 unneback 
vl_fifo_1r1w_async_a (
4001 
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
4002 
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
4003 
    );
4004 
 
4005 40 unneback 
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
4006 6 unneback 
vl_fifo_1r1w_async_b (
4007 
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
4008 
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
4009 
    );
4010 40 unneback 
`undef MODULE
4011 
 
4012 6 unneback 
endmodule
4013 40 unneback 
`endif
4014 6 unneback 
 
4015 40 unneback 
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
4016 
`define MODULE fifo_2r2w_async_simplex
4017 
module `BASE`MODULE (
4018 
`undef MODULE
4019 6 unneback 
    // a side
4020 
    a_d, a_wr, a_fifo_full,
4021 
    a_q, a_rd, a_fifo_empty,
4022 
    a_clk, a_rst,
4023 
    // b side
4024 
    b_d, b_wr, b_fifo_full,
4025 
    b_q, b_rd, b_fifo_empty,
4026 
    b_clk, b_rst
4027 
    );
4028 
 
4029 
parameter data_width = 18;
4030 
parameter addr_width = 4;
4031 
 
4032 
// a side
4033 
input  [data_width-1:0] a_d;
4034 
input                   a_wr;
4035 
output                  a_fifo_full;
4036 
output [data_width-1:0] a_q;
4037 
input                   a_rd;
4038 
output                  a_fifo_empty;
4039 
input                   a_clk;
4040 
input                   a_rst;
4041 
 
4042 
// b side
4043 
input  [data_width-1:0] b_d;
4044 
input                   b_wr;
4045 
output                  b_fifo_full;
4046 
output [data_width-1:0] b_q;
4047 
input                   b_rd;
4048 
output                  b_fifo_empty;
4049 
input                   b_clk;
4050 
input                   b_rst;
4051 
 
4052 
// adr_gen
4053 
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
4054 
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
4055 
// dpram
4056 
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
4057 
 
4058 40 unneback 
`define MODULE cnt_gray_ce_bin
4059 
`BASE`MODULE
4060 6 unneback 
    # ( .length(addr_width))
4061 
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
4062 
 
4063 40 unneback 
`BASE`MODULE
4064 6 unneback 
    # (.length(addr_width))
4065 
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
4066 
 
4067 40 unneback 
`BASE`MODULE
4068 6 unneback 
    # ( .length(addr_width))
4069 
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
4070 
 
4071 40 unneback 
`BASE`MODULE
4072 6 unneback 
    # (.length(addr_width))
4073 
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
4074 40 unneback 
`undef MODULE
4075 6 unneback 
 
4076 
// mux read or write adr to DPRAM
4077 
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
4078 
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
4079 
 
4080 40 unneback 
`define MODULE dpram_2r2w
4081 
`BASE`MODULE
4082 6 unneback 
    # (.data_width(data_width), .addr_width(addr_width+1))
4083 
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
4084 
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
4085 40 unneback 
`undef MODULE
4086 6 unneback 
 
4087 40 unneback 
`define MODULE fifo_cmp_async
4088 
`BASE`MODULE
4089 6 unneback 
    # (.addr_width(addr_width))
4090 
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
4091 
 
4092 40 unneback 
`BASE`MODULE
4093 6 unneback 
    # (.addr_width(addr_width))
4094 
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
4095 40 unneback 
`undef MODULE
4096 6 unneback 
 
4097 
endmodule
4098 40 unneback 
`endif
4099 48 unneback 
 
4100 
`ifdef REG_FILE
4101 
`define MODULE reg_file
4102 
module `BASE`MODULE (
4103 
`undef MODULE
4104 
    a1, a2, a3, wd3, we3, rd1, rd2, clk
4105 
);
4106 
parameter data_width = 32;
4107 
parameter addr_width = 5;
4108 
input [addr_width-1:0] a1, a2, a3;
4109 
input [data_width-1:0] wd3;
4110 
input we3;
4111 
output [data_width-1:0] rd1, rd2;
4112 
input clk;
4113 
 
4114 
`ifdef ACTEL
4115 
reg [data_width-1:0] wd3_reg;
4116 
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
4117 
reg we3_reg;
4118 
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] `SYN;
4119 
reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] `SYN;
4120 
always @ (posedge clk or posedge rst)
4121 
if (rst)
4122 
    {wd3_reg, a3_reg, we3_reg} <= {(data_width+addr_width+1){1'b0}};
4123 
else
4124 
    {wd3_reg, a3_reg, we3_reg} <= {wd3,a3,wd3};
4125 
 
4126 
    always @ (negedge clk)
4127 
    if (we3_reg)
4128 
        ram1[a3_reg] <= wd3;
4129 
    always @ (posedge clk)
4130 
        a1_reg <= a1;
4131 
    assign rd1 = ram1[a1_reg];
4132 
 
4133 
    always @ (negedge clk)
4134 
    if (we3_reg)
4135 
        ram2[a3_reg] <= wd3;
4136 
    always @ (posedge clk)
4137 
        a2_reg <= a2;
4138 
    assign rd2 = ram2[a2_reg];
4139 
 
4140 
`else
4141 
 
4142 
`define MODULE dpram_1r1w
4143 
`BASE`MODULE
4144 
    # ( .data_width(data_width), .addr_width(addr_width))
4145 
    ram1 (
4146 
        .d_a(wd3),
4147 
        .adr_a(a3),
4148 
        .we_a(we3),
4149 
        .clk_a(clk),
4150 
        .q_b(rd1),
4151 
        .adr_b(a1),
4152 
        .clk_b(clk) );
4153 
 
4154 
`BASE`MODULE
4155 
    # ( .data_width(data_width), .addr_width(addr_width))
4156 
    ram2 (
4157 
        .d_a(wd3),
4158 
        .adr_a(a3),
4159 
        .we_a(we3),
4160 
        .clk_a(clk),
4161 
        .q_b(rd2),
4162 
        .adr_b(a2),
4163 
        .clk_b(clk) );
4164 
`undef MODULE
4165 
 
4166 
`endif
4167 
 
4168 
endmodule
4169 
`endif
4170 12 unneback 
//////////////////////////////////////////////////////////////////////
4171 
////                                                              ////
4172 
////  Versatile library, wishbone stuff                           ////
4173 
////                                                              ////
4174 
////  Description                                                 ////
4175 
////  Wishbone compliant modules                                  ////
4176 
////                                                              ////
4177 
////                                                              ////
4178 
////  To Do:                                                      ////
4179 
////   -                                                          ////
4180 
////                                                              ////
4181 
////  Author(s):                                                  ////
4182 
////      - Michael Unneback, unneback@opencores.org              ////
4183 
////        ORSoC AB                                              ////
4184 
////                                                              ////
4185 
//////////////////////////////////////////////////////////////////////
4186 
////                                                              ////
4187 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
4188 
////                                                              ////
4189 
//// This source file may be used and distributed without         ////
4190 
//// restriction provided that this copyright statement is not    ////
4191 
//// removed from the file and that any derivative work contains  ////
4192 
//// the original copyright notice and the associated disclaimer. ////
4193 
////                                                              ////
4194 
//// This source file is free software; you can redistribute it   ////
4195 
//// and/or modify it under the terms of the GNU Lesser General   ////
4196 
//// Public License as published by the Free Software Foundation; ////
4197 
//// either version 2.1 of the License, or (at your option) any   ////
4198 
//// later version.                                               ////
4199 
////                                                              ////
4200 
//// This source is distributed in the hope that it will be       ////
4201 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
4202 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
4203 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
4204 
//// details.                                                     ////
4205 
////                                                              ////
4206 
//// You should have received a copy of the GNU Lesser General    ////
4207 
//// Public License along with this source; if not, download it   ////
4208 
//// from http://www.opencores.org/lgpl.shtml                     ////
4209 
////                                                              ////
4210 
//////////////////////////////////////////////////////////////////////
4211 
 
4212 40 unneback 
`ifdef WB3WB3_BRIDGE
4213 12 unneback 
// async wb3 - wb3 bridge
4214 
`timescale 1ns/1ns
4215 40 unneback 
`define MODULE wb3wb3_bridge
4216 
module `BASE`MODULE (
4217 
`undef MODULE
4218 12 unneback 
        // wishbone slave side
4219 
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
4220 
        // wishbone master side
4221 
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
4222 
 
4223 
input [31:0] wbs_dat_i;
4224 
input [31:2] wbs_adr_i;
4225 
input [3:0]  wbs_sel_i;
4226 
input [1:0]  wbs_bte_i;
4227 
input [2:0]  wbs_cti_i;
4228 
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
4229 
output [31:0] wbs_dat_o;
4230 14 unneback 
output wbs_ack_o;
4231 12 unneback 
input wbs_clk, wbs_rst;
4232 
 
4233 
output [31:0] wbm_dat_o;
4234 
output reg [31:2] wbm_adr_o;
4235 
output [3:0]  wbm_sel_o;
4236 
output reg [1:0]  wbm_bte_o;
4237 
output reg [2:0]  wbm_cti_o;
4238 14 unneback 
output reg wbm_we_o;
4239 
output wbm_cyc_o;
4240 12 unneback 
output wbm_stb_o;
4241 
input [31:0]  wbm_dat_i;
4242 
input wbm_ack_i;
4243 
input wbm_clk, wbm_rst;
4244 
 
4245 
parameter addr_width = 4;
4246 
 
4247 
// bte
4248 
parameter linear       = 2'b00;
4249 
parameter wrap4        = 2'b01;
4250 
parameter wrap8        = 2'b10;
4251 
parameter wrap16       = 2'b11;
4252 
// cti
4253 
parameter classic      = 3'b000;
4254 
parameter incburst     = 3'b010;
4255 
parameter endofburst   = 3'b111;
4256 
 
4257 
parameter wbs_adr  = 1'b0;
4258 
parameter wbs_data = 1'b1;
4259 
 
4260 33 unneback 
parameter wbm_adr0      = 2'b00;
4261 
parameter wbm_adr1      = 2'b01;
4262 
parameter wbm_data      = 2'b10;
4263 
parameter wbm_data_wait = 2'b11;
4264 12 unneback 
 
4265 
reg [1:0] wbs_bte_reg;
4266 
reg wbs;
4267 
wire wbs_eoc_alert, wbm_eoc_alert;
4268 
reg wbs_eoc, wbm_eoc;
4269 
reg [1:0] wbm;
4270 
 
4271 14 unneback 
wire [1:16] wbs_count, wbm_count;
4272 12 unneback 
 
4273 
wire [35:0] a_d, a_q, b_d, b_q;
4274 
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
4275 
reg a_rd_reg;
4276 
wire b_rd_adr, b_rd_data;
4277 14 unneback 
wire b_rd_data_reg;
4278 
wire [35:0] temp;
4279 12 unneback 
 
4280 
`define WE 5
4281 
`define BTE 4:3
4282 
`define CTI 2:0
4283 
 
4284 
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
4285 
always @ (posedge wbs_clk or posedge wbs_rst)
4286 
if (wbs_rst)
4287 
        wbs_eoc <= 1'b0;
4288 
else
4289 
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
4290 
                wbs_eoc <= wbs_bte_i==linear;
4291 
        else if (wbs_eoc_alert & (a_rd | a_wr))
4292 
                wbs_eoc <= 1'b1;
4293 
 
4294 40 unneback 
`define MODULE cnt_shreg_ce_clear
4295 
`BASE`MODULE # ( .length(16))
4296 
`undef MODULE
4297 12 unneback 
    cnt0 (
4298 
        .cke(wbs_ack_o),
4299 
        .clear(wbs_eoc),
4300 
        .q(wbs_count),
4301 
        .rst(wbs_rst),
4302 
        .clk(wbs_clk));
4303 
 
4304 
always @ (posedge wbs_clk or posedge wbs_rst)
4305 
if (wbs_rst)
4306 
        wbs <= wbs_adr;
4307 
else
4308 
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & !a_fifo_full)
4309 
                wbs <= wbs_data;
4310 
        else if (wbs_eoc & wbs_ack_o)
4311 
                wbs <= wbs_adr;
4312 
 
4313 
// wbs FIFO
4314 
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,wbs_bte_i,wbs_cti_i} : {wbs_dat_i,wbs_sel_i};
4315 
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & !a_fifo_full :
4316 
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
4317 
              1'b0;
4318 
assign a_rd = !a_fifo_empty;
4319 
always @ (posedge wbs_clk or posedge wbs_rst)
4320 
if (wbs_rst)
4321 
        a_rd_reg <= 1'b0;
4322 
else
4323 
        a_rd_reg <= a_rd;
4324 
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
4325 
 
4326 
assign wbs_dat_o = a_q[35:4];
4327 
 
4328 
always @ (posedge wbs_clk or posedge wbs_rst)
4329 
if (wbs_rst)
4330 13 unneback 
        wbs_bte_reg <= 2'b00;
4331 12 unneback 
else
4332 13 unneback 
        wbs_bte_reg <= wbs_bte_i;
4333 12 unneback 
 
4334 
// wbm FIFO
4335 
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
4336 
always @ (posedge wbm_clk or posedge wbm_rst)
4337 
if (wbm_rst)
4338 
        wbm_eoc <= 1'b0;
4339 
else
4340 
        if (wbm==wbm_adr0 & !b_fifo_empty)
4341 
                wbm_eoc <= b_q[`BTE] == linear;
4342 
        else if (wbm_eoc_alert & wbm_ack_i)
4343 
                wbm_eoc <= 1'b1;
4344 
 
4345 
always @ (posedge wbm_clk or posedge wbm_rst)
4346 
if (wbm_rst)
4347 
        wbm <= wbm_adr0;
4348 
else
4349 33 unneback 
/*
4350 12 unneback 
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
4351 
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
4352 
        (wbm==wbm_adr1 & !wbm_we_o) |
4353 
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
4354 
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
4355 33 unneback 
*/
4356 
    case (wbm)
4357 
    wbm_adr0:
4358 
        if (!b_fifo_empty)
4359 
            wbm <= wbm_adr1;
4360 
    wbm_adr1:
4361 
        if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
4362 
            wbm <= wbm_data;
4363 
    wbm_data:
4364 
        if (wbm_ack_i & wbm_eoc)
4365 
            wbm <= wbm_adr0;
4366 
        else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
4367 
            wbm <= wbm_data_wait;
4368 
    wbm_data_wait:
4369 
        if (!b_fifo_empty)
4370 
            wbm <= wbm_data;
4371 
    endcase
4372 12 unneback 
 
4373 
assign b_d = {wbm_dat_i,4'b1111};
4374 
assign b_wr = !wbm_we_o & wbm_ack_i;
4375 
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
4376 
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
4377 
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
4378 33 unneback 
                   (wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
4379 12 unneback 
                   1'b0;
4380 
assign b_rd = b_rd_adr | b_rd_data;
4381 
 
4382 40 unneback 
`define MODULE dff
4383 
`BASE`MODULE dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
4384 
`undef MODULE
4385 
`define MODULE dff_ce
4386 
`BASE`MODULE # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
4387 
`undef MODULE
4388 12 unneback 
 
4389 
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
4390 
 
4391 40 unneback 
`define MODULE cnt_shreg_ce_clear
4392 42 unneback 
`BASE`MODULE # ( .length(16))
4393 40 unneback 
`undef MODULE
4394 12 unneback 
    cnt1 (
4395 
        .cke(wbm_ack_i),
4396 
        .clear(wbm_eoc),
4397 
        .q(wbm_count),
4398 
        .rst(wbm_rst),
4399 
        .clk(wbm_clk));
4400 
 
4401 33 unneback 
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
4402 
assign wbm_stb_o = (wbm==wbm_data);
4403 12 unneback 
 
4404 
always @ (posedge wbm_clk or posedge wbm_rst)
4405 
if (wbm_rst)
4406 
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
4407 
else begin
4408 
        if (wbm==wbm_adr0 & !b_fifo_empty)
4409 
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
4410 
        else if (wbm_eoc_alert & wbm_ack_i)
4411 
                wbm_cti_o <= endofburst;
4412 
end
4413 
 
4414 
//async_fifo_dw_simplex_top
4415 40 unneback 
`define MODULE fifo_2r2w_async_simplex
4416 
`BASE`MODULE
4417 
`undef MODULE
4418 12 unneback 
# ( .data_width(36), .addr_width(addr_width))
4419 
fifo (
4420 
    // a side
4421 
    .a_d(a_d),
4422 
    .a_wr(a_wr),
4423 
    .a_fifo_full(a_fifo_full),
4424 
    .a_q(a_q),
4425 
    .a_rd(a_rd),
4426 
    .a_fifo_empty(a_fifo_empty),
4427 
    .a_clk(wbs_clk),
4428 
    .a_rst(wbs_rst),
4429 
    // b side
4430 
    .b_d(b_d),
4431 
    .b_wr(b_wr),
4432 
    .b_fifo_full(b_fifo_full),
4433 
    .b_q(b_q),
4434 
    .b_rd(b_rd),
4435 
    .b_fifo_empty(b_fifo_empty),
4436 
    .b_clk(wbm_clk),
4437 
    .b_rst(wbm_rst)
4438 
    );
4439 
 
4440 
endmodule
4441 40 unneback 
`undef WE
4442 
`undef BTE
4443 
`undef CTI
4444 
`endif
4445 17 unneback 
 
4446 40 unneback 
`ifdef WB3_ARBITER_TYPE1
4447 
`define MODULE wb3_arbiter_type1
4448 42 unneback 
module `BASE`MODULE (
4449 40 unneback 
`undef MODULE
4450 39 unneback 
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
4451 
    wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
4452 
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
4453 
    wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
4454 
    wb_clk, wb_rst
4455 
);
4456 
 
4457 
parameter nr_of_ports = 3;
4458 
parameter adr_size = 26;
4459 
parameter adr_lo   = 2;
4460 
parameter dat_size = 32;
4461 
parameter sel_size = dat_size/8;
4462 
 
4463 
localparam aw = (adr_size - adr_lo) * nr_of_ports;
4464 
localparam dw = dat_size * nr_of_ports;
4465 
localparam sw = sel_size * nr_of_ports;
4466 
localparam cw = 3 * nr_of_ports;
4467 
localparam bw = 2 * nr_of_ports;
4468 
 
4469 
input  [dw-1:0] wbm_dat_o;
4470 
input  [aw-1:0] wbm_adr_o;
4471 
input  [sw-1:0] wbm_sel_o;
4472 
input  [cw-1:0] wbm_cti_o;
4473 
input  [bw-1:0] wbm_bte_o;
4474 
input  [nr_of_ports-1:0] wbm_we_o, wbm_stb_o, wbm_cyc_o;
4475 
output [dw-1:0] wbm_dat_i;
4476 
output [nr_of_ports-1:0] wbm_ack_i, wbm_err_i, wbm_rty_i;
4477 
 
4478 
output [dat_size-1:0] wbs_dat_i;
4479 
output [adr_size-1:adr_lo] wbs_adr_i;
4480 
output [sel_size-1:0] wbs_sel_i;
4481 
output [2:0] wbs_cti_i;
4482 
output [1:0] wbs_bte_i;
4483 
output wbs_we_i, wbs_stb_i, wbs_cyc_i;
4484 
input  [dat_size-1:0] wbs_dat_o;
4485 
input  wbs_ack_o, wbs_err_o, wbs_rty_o;
4486 
 
4487 
input wb_clk, wb_rst;
4488 
 
4489 44 unneback 
reg  [nr_of_ports-1:0] select;
4490 39 unneback 
wire [nr_of_ports-1:0] state;
4491 
wire [nr_of_ports-1:0] eoc; // end-of-cycle
4492 
wire [nr_of_ports-1:0] sel;
4493 
wire idle;
4494 
 
4495 
genvar i;
4496 
 
4497 
assign idle = !(|state);
4498 
 
4499 
generate
4500 
if (nr_of_ports == 2) begin
4501 
 
4502 
    wire [2:0] wbm1_cti_o, wbm0_cti_o;
4503 
 
4504 
    assign {wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
4505 
 
4506 44 unneback 
    //assign select = (idle) ? {wbm_cyc_o[1],!wbm_cyc_o[1] & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
4507 
 
4508 
    always @ (idle or wbm_cyc_o)
4509 
    if (idle)
4510 
        casex (wbm_cyc_o)
4511 
        2'b1x : select = 2'b10;
4512 
        2'b01 : select = 2'b01;
4513 
        default : select = {nr_of_ports{1'b0}};
4514 
        endcase
4515 
    else
4516 
        select = {nr_of_ports{1'b0}};
4517 
 
4518 39 unneback 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
4519 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
4520 
 
4521 
end
4522 
endgenerate
4523 
 
4524 
generate
4525 
if (nr_of_ports == 3) begin
4526 
 
4527 
    wire [2:0] wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
4528 
 
4529 
    assign {wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
4530 
 
4531 44 unneback 
    always @ (idle or wbm_cyc_o)
4532 
    if (idle)
4533 
        casex (wbm_cyc_o)
4534 
        3'b1xx : select = 3'b100;
4535 
        3'b01x : select = 3'b010;
4536 
        3'b001 : select = 3'b001;
4537 
        default : select = {nr_of_ports{1'b0}};
4538 
        endcase
4539 
    else
4540 
        select = {nr_of_ports{1'b0}};
4541 
 
4542 
//    assign select = (idle) ? {wbm_cyc_o[2],!wbm_cyc_o[2] & wbm_cyc_o[1],wbm_cyc_o[2:1]==2'b00 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
4543 39 unneback 
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
4544 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
4545 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
4546 
 
4547 
end
4548 
endgenerate
4549 
 
4550 
generate
4551 44 unneback 
if (nr_of_ports == 4) begin
4552 
 
4553 
    wire [2:0] wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
4554 
 
4555 
    assign {wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
4556 
 
4557 
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
4558 
 
4559 
    always @ (idle or wbm_cyc_o)
4560 
    if (idle)
4561 
        casex (wbm_cyc_o)
4562 
        4'b1xxx : select = 4'b1000;
4563 
        4'b01xx : select = 4'b0100;
4564 
        4'b001x : select = 4'b0010;
4565 
        4'b0001 : select = 4'b0001;
4566 
        default : select = {nr_of_ports{1'b0}};
4567 
        endcase
4568 
    else
4569 
        select = {nr_of_ports{1'b0}};
4570 
 
4571 
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
4572 
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
4573 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
4574 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
4575 
 
4576 
end
4577 
endgenerate
4578 
 
4579 
generate
4580 
if (nr_of_ports == 5) begin
4581 
 
4582 
    wire [2:0] wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
4583 
 
4584 
    assign {wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
4585 
 
4586 
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
4587 
 
4588 
    always @ (idle or wbm_cyc_o)
4589 
    if (idle)
4590 
        casex (wbm_cyc_o)
4591 
        5'b1xxxx : select = 5'b10000;
4592 
        5'b01xxx : select = 5'b01000;
4593 
        5'b001xx : select = 5'b00100;
4594 
        5'b0001x : select = 5'b00010;
4595 
        5'b00001 : select = 5'b00001;
4596 
        default : select = {nr_of_ports{1'b0}};
4597 
        endcase
4598 
    else
4599 
        select = {nr_of_ports{1'b0}};
4600 
 
4601 
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
4602 
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
4603 
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
4604 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
4605 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
4606 
 
4607 
end
4608 
endgenerate
4609 
 
4610 
generate
4611 39 unneback 
for (i=0;i<nr_of_ports;i=i+1) begin
4612 42 unneback 
`define MODULE spr
4613 
    `BASE`MODULE sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));
4614 
`undef MODULE
4615 39 unneback 
end
4616 
endgenerate
4617 
 
4618 
    assign sel = select | state;
4619 
 
4620 40 unneback 
`define MODULE mux_andor
4621 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i));
4622 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(adr_size-adr_lo)) mux1 ( .a(wbm_adr_o), .sel(sel), .dout(wbs_adr_i));
4623 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(sel_size)) mux2 ( .a(wbm_sel_o), .sel(sel), .dout(wbs_sel_i));
4624 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(3)) mux3 ( .a(wbm_cti_o), .sel(sel), .dout(wbs_cti_i));
4625 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(2)) mux4 ( .a(wbm_bte_o), .sel(sel), .dout(wbs_bte_i));
4626 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux5 ( .a(wbm_we_o), .sel(sel), .dout(wbs_we_i));
4627 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux6 ( .a(wbm_stb_o), .sel(sel), .dout(wbs_stb_i));
4628 
`undef MODULE
4629 39 unneback 
    assign wbs_cyc_i = |sel;
4630 
 
4631 
    assign wbm_dat_i = {nr_of_ports{wbs_dat_o}};
4632 
    assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
4633 
    assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
4634 
    assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
4635 
 
4636 
endmodule
4637 40 unneback 
`endif
4638 39 unneback 
 
4639 48 unneback 
`ifdef WB_B4_ROM
4640 
// WB ROM
4641 
`define MODULE wb_b4_rom
4642 
module `BASE`MODULE (
4643 
`undef MODULE
4644 
    wb_adr_i, wb_stb_i, wb_cyc_i,
4645 
    wb_dat_o, stall_o, wb_ack_o, wb_clk, wb_rst);
4646 
 
4647 
    parameter dat_width = 32;
4648 
    parameter dat_default = 32'h15000000;
4649 
    parameter adr_width = 32;
4650 
 
4651 
/*
4652 
`ifndef ROM
4653 
`define ROM "rom.v"
4654 
`endif
4655 
*/
4656 
    input [adr_width-1:2]   wb_adr_i;
4657 
    input                   wb_stb_i;
4658 
    input                   wb_cyc_i;
4659 
    output [dat_width-1:0]  wb_dat_o;
4660 
    reg [dat_width-1:0]     wb_dat_o;
4661 
    output                  wb_ack_o;
4662 
    reg                     wb_ack_o;
4663 
    output                  stall_o;
4664 
    input                   wb_clk;
4665 
    input                   wb_rst;
4666 
 
4667 
always @ (posedge wb_clk or posedge wb_rst)
4668 
    if (wb_rst)
4669 
        wb_dat_o <= {dat_width{1'b0}};
4670 
    else
4671 
         case (wb_adr_i[adr_width-1:2])
4672 
`ifdef ROM
4673 
`include `ROM
4674 
`endif
4675 
           default:
4676 
             wb_dat_o <= dat_default;
4677 
 
4678 
         endcase // case (wb_adr_i)
4679 
 
4680 
 
4681 
always @ (posedge wb_clk or posedge wb_rst)
4682 
    if (wb_rst)
4683 
        wb_ack_o <= 1'b0;
4684 
    else
4685 
        wb_ack_o <= wb_stb_i & wb_cyc_i;
4686 
 
4687 
assign stall_o = 1'b0;
4688 
 
4689 
endmodule
4690 
`endif
4691 
 
4692 
 
4693 40 unneback 
`ifdef WB_BOOT_ROM
4694 17 unneback 
// WB ROM
4695 40 unneback 
`define MODULE wb_boot_rom
4696 
module `BASE`MODULE (
4697 
`undef MODULE
4698 17 unneback 
    wb_adr_i, wb_stb_i, wb_cyc_i,
4699 18 unneback 
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
4700 17 unneback 
 
4701 18 unneback 
    parameter adr_hi = 31;
4702 
    parameter adr_lo = 28;
4703 
    parameter adr_sel = 4'hf;
4704 
    parameter addr_width = 5;
4705 33 unneback 
/*
4706 17 unneback 
`ifndef BOOT_ROM
4707 
`define BOOT_ROM "boot_rom.v"
4708 
`endif
4709 33 unneback 
*/
4710 18 unneback 
    input [adr_hi:2]    wb_adr_i;
4711 
    input               wb_stb_i;
4712 
    input               wb_cyc_i;
4713 
    output [31:0]        wb_dat_o;
4714 
    output              wb_ack_o;
4715 
    output              hit_o;
4716 
    input               wb_clk;
4717 
    input               wb_rst;
4718 
 
4719 
    wire hit;
4720 
    reg [31:0] wb_dat;
4721 
    reg wb_ack;
4722 
 
4723 
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
4724 17 unneback 
 
4725 
always @ (posedge wb_clk or posedge wb_rst)
4726 
    if (wb_rst)
4727 18 unneback 
        wb_dat <= 32'h15000000;
4728 17 unneback 
    else
4729 18 unneback 
         case (wb_adr_i[addr_width-1:2])
4730 33 unneback 
`ifdef BOOT_ROM
4731 17 unneback 
`include `BOOT_ROM
4732 33 unneback 
`endif
4733 17 unneback 
           /*
4734 
            // Zero r0 and jump to 0x00000100
4735 18 unneback 
 
4736 
            1 : wb_dat <= 32'hA8200000;
4737 
            2 : wb_dat <= 32'hA8C00100;
4738 
            3 : wb_dat <= 32'h44003000;
4739 
            4 : wb_dat <= 32'h15000000;
4740 17 unneback 
            */
4741 
           default:
4742 18 unneback 
             wb_dat <= 32'h00000000;
4743 17 unneback 
 
4744 
         endcase // case (wb_adr_i)
4745 
 
4746 
 
4747 
always @ (posedge wb_clk or posedge wb_rst)
4748 
    if (wb_rst)
4749 18 unneback 
        wb_ack <= 1'b0;
4750 17 unneback 
    else
4751 18 unneback 
        wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
4752 17 unneback 
 
4753 18 unneback 
assign hit_o = hit;
4754 
assign wb_dat_o = wb_dat & {32{wb_ack}};
4755 
assign wb_ack_o = wb_ack;
4756 
 
4757 17 unneback 
endmodule
4758 40 unneback 
`endif
4759 32 unneback 
 
4760 40 unneback 
`ifdef WB_DPRAM
4761 
`define MODULE wb_dpram
4762 
module `BASE`MODULE (
4763 
`undef MODULE
4764 32 unneback 
        // wishbone slave side a
4765 
        wbsa_dat_i, wbsa_adr_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o,
4766 
        wbsa_clk, wbsa_rst,
4767 
        // wishbone slave side a
4768 
        wbsb_dat_i, wbsb_adr_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o,
4769 
        wbsb_clk, wbsb_rst);
4770 
 
4771 
parameter data_width = 32;
4772 
parameter addr_width = 8;
4773 
 
4774 
parameter dat_o_mask_a = 1;
4775 
parameter dat_o_mask_b = 1;
4776 
 
4777 
input [31:0] wbsa_dat_i;
4778 
input [addr_width-1:2] wbsa_adr_i;
4779 
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
4780 
output [31:0] wbsa_dat_o;
4781 
output wbsa_ack_o;
4782 
input wbsa_clk, wbsa_rst;
4783 
 
4784 
input [31:0] wbsb_dat_i;
4785 
input [addr_width-1:2] wbsb_adr_i;
4786 
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
4787 
output [31:0] wbsb_dat_o;
4788 
output wbsb_ack_o;
4789 
input wbsb_clk, wbsb_rst;
4790 
 
4791 
wire wbsa_dat_tmp, wbsb_dat_tmp;
4792 
 
4793 40 unneback 
`define MODULE dpram_2r2w
4794 
`BASE`MODULE # (
4795 
`undef MODULE
4796 33 unneback 
    .data_width(data_width), .addr_width(addr_width) )
4797 32 unneback 
dpram0(
4798 
    .d_a(wbsa_dat_i),
4799 
    .q_a(wbsa_dat_tmp),
4800 
    .adr_a(wbsa_adr_i),
4801 
    .we_a(wbsa_we_i),
4802 
    .clk_a(wbsa_clk),
4803 
    .d_b(wbsb_dat_i),
4804 
    .q_b(wbsb_dat_tmp),
4805 
    .adr_b(wbsb_adr_i),
4806 
    .we_b(wbsb_we_i),
4807 
    .clk_b(wbsb_clk) );
4808 
 
4809 33 unneback 
generate if (dat_o_mask_a==1)
4810 32 unneback 
    assign wbsa_dat_o = wbsa_dat_tmp & {data_width{wbsa_ack_o}};
4811 
endgenerate
4812 33 unneback 
generate if (dat_o_mask_a==0)
4813 32 unneback 
    assign wbsa_dat_o = wbsa_dat_tmp;
4814 
endgenerate
4815 
 
4816 33 unneback 
generate if (dat_o_mask_b==1)
4817 32 unneback 
    assign wbsb_dat_o = wbsb_dat_tmp & {data_width{wbsb_ack_o}};
4818 
endgenerate
4819 33 unneback 
generate if (dat_o_mask_b==0)
4820 32 unneback 
    assign wbsb_dat_o = wbsb_dat_tmp;
4821 
endgenerate
4822 
 
4823 40 unneback 
`define MODULE spr
4824 
`BASE`MODULE ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
4825 
`BASE`MODULE ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
4826 
`undef MODULE
4827 32 unneback 
 
4828 
endmodule
4829 40 unneback 
`endif
4830 18 unneback 
//////////////////////////////////////////////////////////////////////
4831 
////                                                              ////
4832 
////  Arithmetic functions                                        ////
4833 
////                                                              ////
4834 
////  Description                                                 ////
4835 
////  Arithmetic functions for ALU and DSP                        ////
4836 
////                                                              ////
4837 
////                                                              ////
4838 
////  To Do:                                                      ////
4839 
////   -                                                          ////
4840 
////                                                              ////
4841 
////  Author(s):                                                  ////
4842 
////      - Michael Unneback, unneback@opencores.org              ////
4843 
////        ORSoC AB                                              ////
4844 
////                                                              ////
4845 
//////////////////////////////////////////////////////////////////////
4846 
////                                                              ////
4847 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
4848 
////                                                              ////
4849 
//// This source file may be used and distributed without         ////
4850 
//// restriction provided that this copyright statement is not    ////
4851 
//// removed from the file and that any derivative work contains  ////
4852 
//// the original copyright notice and the associated disclaimer. ////
4853 
////                                                              ////
4854 
//// This source file is free software; you can redistribute it   ////
4855 
//// and/or modify it under the terms of the GNU Lesser General   ////
4856 
//// Public License as published by the Free Software Foundation; ////
4857 
//// either version 2.1 of the License, or (at your option) any   ////
4858 
//// later version.                                               ////
4859 
////                                                              ////
4860 
//// This source is distributed in the hope that it will be       ////
4861 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
4862 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
4863 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
4864 
//// details.                                                     ////
4865 
////                                                              ////
4866 
//// You should have received a copy of the GNU Lesser General    ////
4867 
//// Public License along with this source; if not, download it   ////
4868 
//// from http://www.opencores.org/lgpl.shtml                     ////
4869 
////                                                              ////
4870 
//////////////////////////////////////////////////////////////////////
4871 
 
4872 40 unneback 
`ifdef MULTS
4873 18 unneback 
// signed multiplication
4874 40 unneback 
`define MODULE mults
4875 
module `BASE`MODULE (a,b,p);
4876 
`undef MODULE
4877 18 unneback 
parameter operand_a_width = 18;
4878 
parameter operand_b_width = 18;
4879 
parameter result_hi = 35;
4880 
parameter result_lo = 0;
4881 
input [operand_a_width-1:0] a;
4882 
input [operand_b_width-1:0] b;
4883 
output [result_hi:result_lo] p;
4884 
wire signed [operand_a_width-1:0] ai;
4885 
wire signed [operand_b_width-1:0] bi;
4886 
wire signed [operand_a_width+operand_b_width-1:0] result;
4887 
 
4888 
    assign ai = a;
4889 
    assign bi = b;
4890 
    assign result = ai * bi;
4891 
    assign p = result[result_hi:result_lo];
4892 
 
4893 
endmodule
4894 40 unneback 
`endif
4895 
`ifdef MULTS18X18
4896 
`define MODULE mults18x18
4897 
module `BASE`MODULE (a,b,p);
4898 
`undef MODULE
4899 18 unneback 
input [17:0] a,b;
4900 
output [35:0] p;
4901 
vl_mult
4902 
    # (.operand_a_width(18), .operand_b_width(18))
4903 
    mult0 (.a(a), .b(b), .p(p));
4904 
endmodule
4905 40 unneback 
`endif
4906 18 unneback 
 
4907 40 unneback 
`ifdef MULT
4908 
`define MODULE mult
4909 18 unneback 
// unsigned multiplication
4910 40 unneback 
module `BASE`MODULE (a,b,p);
4911 
`undef MODULE
4912 18 unneback 
parameter operand_a_width = 18;
4913 
parameter operand_b_width = 18;
4914 
parameter result_hi = 35;
4915 
parameter result_lo = 0;
4916 
input [operand_a_width-1:0] a;
4917 
input [operand_b_width-1:0] b;
4918 
output [result_hi:result_hi] p;
4919 
 
4920 
wire [operand_a_width+operand_b_width-1:0] result;
4921 
 
4922 
    assign result = a * b;
4923 
    assign p = result[result_hi:result_lo];
4924 
 
4925 
endmodule
4926 40 unneback 
`endif
4927 18 unneback 
 
4928 40 unneback 
`ifdef SHIFT_UNIT_32
4929 
`define MODULE shift_unit_32
4930 18 unneback 
// shift unit
4931 
// supporting the following shift functions
4932 
//   SLL
4933 
//   SRL
4934 
//   SRA
4935 
`define SHIFT_UNIT_MULT # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7))
4936 40 unneback 
module `BASE`MODULE( din, s, dout, opcode);
4937 
`undef MODULE
4938 18 unneback 
input [31:0] din; // data in operand
4939 
input [4:0] s; // shift operand
4940 
input [1:0] opcode;
4941 
output [31:0] dout;
4942 
 
4943 
parameter opcode_sll = 2'b00;
4944 
//parameter opcode_srl = 2'b01;
4945 
parameter opcode_sra = 2'b10;
4946 
//parameter opcode_ror = 2'b11;
4947 
 
4948 
wire sll, sra;
4949 
assign sll = opcode == opcode_sll;
4950 
assign sra = opcode == opcode_sra;
4951 
 
4952 
wire [15:1] s1;
4953 
wire [3:0] sign;
4954 
wire [7:0] tmp [0:3];
4955 
 
4956 
// first stage is multiplier based
4957 
// shift operand as fractional 8.7
4958 
assign s1[15] = sll & s[2:0]==3'd7;
4959 
assign s1[14] = sll & s[2:0]==3'd6;
4960 
assign s1[13] = sll & s[2:0]==3'd5;
4961 
assign s1[12] = sll & s[2:0]==3'd4;
4962 
assign s1[11] = sll & s[2:0]==3'd3;
4963 
assign s1[10] = sll & s[2:0]==3'd2;
4964 
assign s1[ 9] = sll & s[2:0]==3'd1;
4965 
assign s1[ 8] = s[2:0]==3'd0;
4966 
assign s1[ 7] = !sll & s[2:0]==3'd1;
4967 
assign s1[ 6] = !sll & s[2:0]==3'd2;
4968 
assign s1[ 5] = !sll & s[2:0]==3'd3;
4969 
assign s1[ 4] = !sll & s[2:0]==3'd4;
4970 
assign s1[ 3] = !sll & s[2:0]==3'd5;
4971 
assign s1[ 2] = !sll & s[2:0]==3'd6;
4972 
assign s1[ 1] = !sll & s[2:0]==3'd7;
4973 
 
4974 
assign sign[3] = din[31] & sra;
4975 
assign sign[2] = sign[3] & (&din[31:24]);
4976 
assign sign[1] = sign[2] & (&din[23:16]);
4977 
assign sign[0] = sign[1] & (&din[15:8]);
4978 40 unneback 
`define MODULE mults
4979 
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte3 ( .a({sign[3], {8{sign[3]}},din[31:24], din[23:16]}), .b({1'b0,s1}), .p(tmp[3]));
4980 
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte2 ( .a({sign[2], din[31:24]  ,din[23:16],  din[15:8]}), .b({1'b0,s1}), .p(tmp[2]));
4981 
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte1 ( .a({sign[1], din[23:16]  ,din[15:8],   din[7:0]}), .b({1'b0,s1}), .p(tmp[1]));
4982 
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte0 ( .a({sign[0], din[15:8]   ,din[7:0],    8'h00}),      .b({1'b0,s1}), .p(tmp[0]));
4983 
`undef MODULE
4984 18 unneback 
// second stage is multiplexer based
4985 
// shift on byte level
4986 
 
4987 
// mux byte 3
4988 
assign dout[31:24] = (s[4:3]==2'b00) ? tmp[3] :
4989 
                     (sll & s[4:3]==2'b01) ? tmp[2] :
4990 
                     (sll & s[4:3]==2'b10) ? tmp[1] :
4991 
                     (sll & s[4:3]==2'b11) ? tmp[0] :
4992 
                     {8{sign[3]}};
4993 
 
4994 
// mux byte 2
4995 
assign dout[23:16] = (s[4:3]==2'b00) ? tmp[2] :
4996 
                     (sll & s[4:3]==2'b01) ? tmp[1] :
4997 
                     (sll & s[4:3]==2'b10) ? tmp[0] :
4998 
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
4999 
                     (s[4:3]==2'b01) ? tmp[3] :
5000 
                     {8{sign[3]}};
5001 
 
5002 
// mux byte 1
5003 
assign dout[15:8]  = (s[4:3]==2'b00) ? tmp[1] :
5004 
                     (sll & s[4:3]==2'b01) ? tmp[0] :
5005 
                     (sll & s[4:3]==2'b10) ? {8{1'b0}} :
5006 
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
5007 
                     (s[4:3]==2'b01) ? tmp[2] :
5008 
                     (s[4:3]==2'b10) ? tmp[3] :
5009 
                     {8{sign[3]}};
5010 
 
5011 
// mux byte 0
5012 
assign dout[7:0]   = (s[4:3]==2'b00) ? tmp[0] :
5013 
                     (sll) ?  {8{1'b0}}:
5014 
                     (s[4:3]==2'b01) ? tmp[1] :
5015 
                     (s[4:3]==2'b10) ? tmp[2] :
5016 
                     tmp[3];
5017 
 
5018 
endmodule
5019 40 unneback 
`endif
5020 18 unneback 
 
5021 40 unneback 
`ifdef LOGIC_UNIT
5022 18 unneback 
// logic unit
5023 
// supporting the following logic functions
5024 
//    a and b
5025 
//    a or  b
5026 
//    a xor b
5027 
//    not b
5028 40 unneback 
`define MODULE logic_unit
5029 
module `BASE`MODULE( a, b, result, opcode);
5030 
`undef MODULE
5031 18 unneback 
parameter width = 32;
5032 
parameter opcode_and = 2'b00;
5033 
parameter opcode_or  = 2'b01;
5034 
parameter opcode_xor = 2'b10;
5035 
input [width-1:0] a,b;
5036 
output [width-1:0] result;
5037 
input [1:0] opcode;
5038 
 
5039 
assign result = (opcode==opcode_and) ? a & b :
5040 
                (opcode==opcode_or)  ? a | b :
5041 
                (opcode==opcode_xor) ? a ^ b :
5042 
                b;
5043 
 
5044 
endmodule
5045 48 unneback 
`endif
5046 18 unneback 
 
5047 48 unneback 
`ifdef ARITH_UNIT
5048 
`define MODULE arith_unit
5049 
module `BASE`MODULE ( a, b, c_in, add_sub, sign, result, c_out, z, ovfl);
5050 
`undef MODULE
5051 18 unneback 
parameter width = 32;
5052 
parameter opcode_add = 1'b0;
5053 
parameter opcode_sub = 1'b1;
5054 
input [width-1:0] a,b;
5055 
input c_in, add_sub, sign;
5056 
output [width-1:0] result;
5057 
output c_out, z, ovfl;
5058 
 
5059 
assign {c_out,result} = {(a[width-1] & sign),a} + ({a[width-1] & sign,b} ^ {(width+1){(add_sub==opcode_sub)}}) + {{(width-1){1'b0}},(c_in | (add_sub==opcode_sub))};
5060 
assign z = (result=={width{1'b0}});
5061 
assign ovfl = ( a[width-1] &  b[width-1] & ~result[width-1]) |
5062 
               (~a[width-1] & ~b[width-1] &  result[width-1]);
5063 
endmodule
5064 40 unneback 
`endif
5065 48 unneback 
 
5066 
`ifdef COUNT_UNIT
5067 
`define MODULE count_unit
5068 
module `BASE`MODULE (din, dout, opcode);
5069 
`undef MODULE
5070 
parameter width = 32;
5071 
input [width-1:0] din;
5072 
output [width-1:0] dout;
5073 
input opcode;
5074 
 
5075 
integer i;
5076 
reg [width/32+3:0] ff1, fl1;
5077 
 
5078 
always @(din) begin
5079 
    ff1 = 0; i = 0;
5080 
    while (din[i] == 0 && i < width) begin // complex condition
5081 
        ff1 = ff1 + 1;
5082 
        i = i + 1;
5083 
    end
5084 
end
5085 
 
5086 
always @(din) begin
5087 
    fl1 = width; i = width-1;
5088 
    while (din[i] == 0 && i >= width) begin // complex condition
5089 
        fl1 = fl1 - 1;
5090 
        i = i - 1;
5091 
    end
5092 
end
5093 
 
5094 
generate
5095 
if (width==32) begin
5096 
    assign dout = (!opcode) ? {{58{1'b0}}, ff1} : {{58{1'b0}}, fl1};
5097 
end
5098 
endgenerate
5099 
generate
5100 
if (width==64) begin
5101 
    assign dout = (!opcode) ? {{27{1'b0}}, ff1} : {{27{1'b0}}, fl1};
5102 
end
5103 
endgenerate
5104 
 
5105 
endmodule
5106 
`endif
5107 
 
5108 
`ifdef EXT_UNIT
5109 
`define MODULE ext_unit
5110 
module `BASE`MODULE ( a, b, F, result, opcode);
5111 
`undef MODULE
5112 
parameter width = 32;
5113 
input [width-1:0] a, b;
5114 
input F;
5115 
output reg [width-1:0] result;
5116 
input [2:0] opcode;
5117 
 
5118 
generate
5119 
if (width==32) begin
5120 
always @ (a or b or F or opcode)
5121 
begin
5122 
    case (opcode)
5123 
    3'b000: result = {{24{1'b0}},a[7:0]};
5124 
    3'b001: result = {{24{a[7]}},a[7:0]};
5125 
    3'b010: result = {{16{1'b0}},a[7:0]};
5126 
    3'b011: result = {{16{a[15]}},a[15:0]};
5127 
    3'b110: result = (F) ? a : b;
5128 
    default: result = {b[15:0],16'h0000};
5129 
    endcase
5130 
end
5131 
end
5132 
endgenerate
5133 
 
5134 
generate
5135 
if (width==64) begin
5136 
always @ (a or b or F or opcode)
5137 
begin
5138 
    case (opcode)
5139 
    3'b000: result = {{56{1'b0}},a[7:0]};
5140 
    3'b001: result = {{56{a[7]}},a[7:0]};
5141 
    3'b010: result = {{48{1'b0}},a[7:0]};
5142 
    3'b011: result = {{48{a[15]}},a[15:0]};
5143 
    3'b110: result = (SR.F) ? a : b;
5144 
    default: result = {32'h00000000,b[15:0],16'h0000};
5145 
    endcase
5146 
end
5147 
end
5148 
endgenerate
5149 
endmodule
5150 
`endif

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