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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Blame information for rev 51

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Line No. Rev Author Line
1 40 unneback
`ifndef BASE
2
`define BASE vl_
3
`endif
4
 
5 44 unneback
`ifdef ACTEL
6
`define SYN_KEEP /*synthesis syn_keep = 1*/
7
`endif
8
 
9 40 unneback
`ifdef ALL
10
 
11
`define GBUF
12
`define SYNC_RST
13
`define PLL
14
 
15
`define MULTS
16
`define MULTS18X18
17
`define MULT
18
`define SHIFT_UNIT_32
19
`define LOGIC_UNIT
20
 
21
`define CNT_SHREG_WRAP
22
`define CNT_SHREG_CE_WRAP
23
`define CNT_SHREG_CE_CLEAR
24
`define CNT_SHREG_CE_CLEAR_WRAP
25
 
26
`define MUX_ANDOR
27
`define MUX2_ANDOR
28
`define MUX3_ANDOR
29
`define MUX4_ANDOR
30
`define MUX5_ANDOR
31
`define MUX6_ANDOR
32 43 unneback
`define PARITY
33 40 unneback
 
34
`define ROM_INIT
35
`define RAM
36
`define RAM_BE
37
`define DPRAM_1R1W
38
`define DPRAM_2R1W
39
`define DPRAM_2R2W
40
`define FIFO_1R1W_FILL_LEVEL_SYNC
41
`define FIFO_2R2W_SYNC_SIMPLEX
42
`define FIFO_CMP_ASYNC
43
`define FIFO_1R1W_ASYNC
44
`define FIFO_2R2W_ASYNC
45
`define FIFO_2R2W_ASYNC_SIMPLEX
46 48 unneback
`define REG_FILE
47 40 unneback
 
48
`define DFF
49
`define DFF_ARRAY
50
`define DFF_CE
51
`define DFF_CE_CLEAR
52
`define DF_CE_SET
53
`define SPR
54
`define SRP
55
`define DFF_SR
56
`define LATCH
57
`define SHREG
58
`define SHREG_CE
59
`define DELAY
60
`define DELAY_EMPTYFLAG
61
 
62
`define WB3WB3_BRIDGE
63
`define WB3_ARBITER_TYPE1
64 49 unneback
`define WB_B4_RAM_BE
65 48 unneback
`define WB_B4_ROM
66 40 unneback
`define WB_BOOT_ROM
67
`define WB_DPRAM
68
 
69 44 unneback
`define IO_DFF_OE
70
`define O_DFF
71
 
72 40 unneback
`endif
73
 
74
`ifdef PLL
75
`ifndef SYNC_RST
76
`define SYNC_RST
77
`endif
78
`endif
79
 
80
`ifdef SYNC_RST
81
`ifndef GBUF
82
`define GBUF
83
`endif
84
`endif
85
 
86
`ifdef WB_DPRAM
87
`ifndef DPRAM_2R2W
88
`define DPRAM_2R2W
89
`endif
90
`ifndef SPR
91
`define SPR
92
`endif
93
`endif
94
 
95
`ifdef WB3_ARBITER_TYPE1
96 42 unneback
`ifndef SPR
97
`define SPR
98
`endif
99 40 unneback
`ifndef MUX_ANDOR
100
`define MUX_ANDOR
101
`endif
102
`endif
103
 
104
`ifdef WB3WB3_BRIDGE
105
`ifndef CNT_SHREG_CE_CLEAR
106
`define CNT_SHREG_CE_CLEAR
107
`endif
108
`ifndef DFF
109
`define DFF
110
`endif
111
`ifndef DFF_CE
112
`define DFF_CE
113
`endif
114
`ifndef CNT_SHREG_CE_CLEAR
115
`define CNT_SHREG_CE_CLEAR
116
`endif
117
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
118
`define FIFO_2R2W_ASYNC_SIMPLEX
119
`endif
120
`endif
121
 
122
`ifdef MULTS18X18
123
`ifndef MULTS
124
`define MULTS
125
`endif
126
`endif
127
 
128
`ifdef SHIFT_UNIT_32
129
`ifndef MULTS
130
`define MULTS
131
`endif
132
`endif
133
 
134
`ifdef MUX2_ANDOR
135
`ifndef MUX_ANDOR
136
`define MUX_ANDOR
137
`endif
138
`endif
139
 
140
`ifdef MUX3_ANDOR
141
`ifndef MUX_ANDOR
142
`define MUX_ANDOR
143
`endif
144
`endif
145
 
146
`ifdef MUX4_ANDOR
147
`ifndef MUX_ANDOR
148
`define MUX_ANDOR
149
`endif
150
`endif
151
 
152
`ifdef MUX5_ANDOR
153
`ifndef MUX_ANDOR
154
`define MUX_ANDOR
155
`endif
156
`endif
157
 
158
`ifdef MUX6_ANDOR
159
`ifndef MUX_ANDOR
160
`define MUX_ANDOR
161
`endif
162
`endif
163
 
164
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
165
`ifndef CNT_BIN_CE
166
`define CNT_BIN_CE
167
`endif
168
`ifndef DPRAM_1R1W
169
`define DPRAM_1R1W
170
`endif
171
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
172
`define CNT_BIN_CE_REW_Q_ZQ_L1
173
`endif
174
`endif
175
 
176
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
177
`ifndef CNT_LFSR_CE
178
`define CNT_LFSR_CE
179
`endif
180
`ifndef DPRAM_2R2W
181
`define DPRAM_2R2W
182
`endif
183
`ifndef CNT_BIN_CE_REW_ZQ_L1
184
`define CNT_BIN_CE_REW_ZQ_L1
185
`endif
186
`endif
187
 
188
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
189
`ifndef CNT_GRAY_CE_BIN
190
`define CNT_GRAY_CE_BIN
191
`endif
192
`ifndef DPRAM_2R2W
193
`define DPRAM_2R2W
194
`endif
195
`ifndef FIFO_CMP_ASYNC
196
`define FIFO_CMP_ASYNC
197
`endif
198
`endif
199
 
200
`ifdef FIFO_2R2W_ASYNC
201
`ifndef FIFO_1R1W_ASYNC
202
`define FIFO_1R1W_ASYNC
203
`endif
204
`endif
205
 
206
`ifdef FIFO_1R1W_ASYNC
207
`ifndef CNT_GRAY_CE_BIN
208
`define CNT_GRAY_CE_BIN
209
`endif
210
`ifndef DPRAM_1R1W
211
`define DPRAM_1R1W
212
`endif
213
`ifndef FIFO_CMP_ASYNC
214
`define FIFO_CMP_ASYNC
215
`endif
216
`endif
217
 
218
`ifdef FIFO_CMP_ASYNC
219
`ifndef DFF_SR
220
`define DFF_SR
221
`endif
222
`ifndef DFF
223
`define DFF
224
`endif
225
`endif
226 48 unneback
 
227
`ifdef REG_FILE
228
`ifndef DPRAM_1R1W
229
`define DPRAM_1R1W
230
`endif
231
`endif
232 6 unneback
//////////////////////////////////////////////////////////////////////
233
////                                                              ////
234
////  Versatile library, clock and reset                          ////
235
////                                                              ////
236
////  Description                                                 ////
237
////  Logic related to clock and reset                            ////
238
////                                                              ////
239
////                                                              ////
240
////  To Do:                                                      ////
241
////   - add more different registers                             ////
242
////                                                              ////
243
////  Author(s):                                                  ////
244
////      - Michael Unneback, unneback@opencores.org              ////
245
////        ORSoC AB                                              ////
246
////                                                              ////
247
//////////////////////////////////////////////////////////////////////
248
////                                                              ////
249
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
250
////                                                              ////
251
//// This source file may be used and distributed without         ////
252
//// restriction provided that this copyright statement is not    ////
253
//// removed from the file and that any derivative work contains  ////
254
//// the original copyright notice and the associated disclaimer. ////
255
////                                                              ////
256
//// This source file is free software; you can redistribute it   ////
257
//// and/or modify it under the terms of the GNU Lesser General   ////
258
//// Public License as published by the Free Software Foundation; ////
259
//// either version 2.1 of the License, or (at your option) any   ////
260
//// later version.                                               ////
261
////                                                              ////
262
//// This source is distributed in the hope that it will be       ////
263
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
264
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
265
//// PURPOSE.  See the GNU Lesser General Public License for more ////
266
//// details.                                                     ////
267
////                                                              ////
268
//// You should have received a copy of the GNU Lesser General    ////
269
//// Public License along with this source; if not, download it   ////
270
//// from http://www.opencores.org/lgpl.shtml                     ////
271
////                                                              ////
272
//////////////////////////////////////////////////////////////////////
273
 
274 48 unneback
`ifdef ACTEL
275
`ifdef GBUF
276
`timescale 1 ns/100 ps
277 6 unneback
// Global buffer
278
// usage:
279
// use to enable global buffers for high fan out signals such as clock and reset
280
// Version: 8.4 8.4.0.33
281
module gbuf(GL,CLK);
282
output GL;
283
input  CLK;
284
 
285
    wire GND;
286
 
287
    GND GND_1_net(.Y(GND));
288
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
289
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
290
 
291
endmodule
292
`timescale 1 ns/1 ns
293 40 unneback
`define MODULE gbuf
294
module `BASE`MODULE ( i, o);
295
`undef MODULE
296 6 unneback
input i;
297
output o;
298
`ifdef SIM_GBUF
299
assign o=i;
300
`else
301
gbuf gbuf_i0 ( .CLK(i), .GL(o));
302
`endif
303
endmodule
304 40 unneback
`endif
305 33 unneback
 
306 6 unneback
`else
307 33 unneback
 
308 40 unneback
`ifdef ALTERA
309
`ifdef GBUF
310 21 unneback
//altera
311 40 unneback
`define MODULE gbuf
312
module `BASE`MODULE ( i, o);
313
`undef MODULE
314 33 unneback
input i;
315
output o;
316
assign o = i;
317
endmodule
318 40 unneback
`endif
319 33 unneback
 
320 6 unneback
`else
321
 
322 40 unneback
`ifdef GBUF
323 6 unneback
`timescale 1 ns/100 ps
324 40 unneback
`define MODULE
325
module `BASE`MODULE ( i, o);
326
`undef MODULE
327 6 unneback
input i;
328
output o;
329
assign o = i;
330
endmodule
331 40 unneback
`endif
332 6 unneback
`endif // ALTERA
333
`endif //ACTEL
334
 
335 40 unneback
`ifdef SYNC_RST
336 6 unneback
// sync reset
337 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
338 6 unneback
// output active high global reset sync with two DFFs 
339
`timescale 1 ns/100 ps
340 40 unneback
`define MODULE sync_rst
341
module `BASE`MODULE ( rst_n_i, rst_o, clk);
342
`undef MODULE
343 6 unneback
input rst_n_i, clk;
344
output rst_o;
345 18 unneback
reg [1:0] tmp;
346 6 unneback
always @ (posedge clk or negedge rst_n_i)
347
if (!rst_n_i)
348 17 unneback
        tmp <= 2'b11;
349 6 unneback
else
350 33 unneback
        tmp <= {1'b0,tmp[1]};
351 40 unneback
`define MODULE gbuf
352
`BASE`MODULE buf_i0( .i(tmp[0]), .o(rst_o));
353
`undef MODULE
354 6 unneback
endmodule
355 40 unneback
`endif
356 6 unneback
 
357 40 unneback
`ifdef PLL
358 6 unneback
// vl_pll
359
`ifdef ACTEL
360 32 unneback
///////////////////////////////////////////////////////////////////////////////
361 17 unneback
`timescale 1 ps/1 ps
362 40 unneback
`define MODULE pll
363
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
364
`undef MODULE
365 6 unneback
parameter index = 0;
366
parameter number_of_clk = 1;
367 17 unneback
parameter period_time_0 = 20000;
368
parameter period_time_1 = 20000;
369
parameter period_time_2 = 20000;
370
parameter lock_delay = 2000000;
371 6 unneback
input clk_i, rst_n_i;
372
output lock;
373
output reg [0:number_of_clk-1] clk_o;
374
output [0:number_of_clk-1] rst_o;
375
 
376
`ifdef SIM_PLL
377
 
378
always
379
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
380
 
381
generate if (number_of_clk > 1)
382
always
383
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
384
endgenerate
385
 
386
generate if (number_of_clk > 2)
387
always
388
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
389
endgenerate
390
 
391
genvar i;
392
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
393
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
394
end
395
endgenerate
396
 
397
assign #lock_delay lock = rst_n_i;
398
 
399
endmodule
400
`else
401
generate if (number_of_clk==1 & index==0) begin
402
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
403
end
404
endgenerate // index==0
405
generate if (number_of_clk==1 & index==1) begin
406
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
407
end
408
endgenerate // index==1
409
generate if (number_of_clk==1 & index==2) begin
410
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
411
end
412
endgenerate // index==2
413
generate if (number_of_clk==1 & index==3) begin
414
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
415
end
416
endgenerate // index==0
417
 
418
generate if (number_of_clk==2 & index==0) begin
419
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
420
end
421
endgenerate // index==0
422
generate if (number_of_clk==2 & index==1) begin
423
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
424
end
425
endgenerate // index==1
426
generate if (number_of_clk==2 & index==2) begin
427
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
428
end
429
endgenerate // index==2
430
generate if (number_of_clk==2 & index==3) begin
431
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
432
end
433
endgenerate // index==0
434
 
435
generate if (number_of_clk==3 & index==0) begin
436
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
437
end
438
endgenerate // index==0
439
generate if (number_of_clk==3 & index==1) begin
440
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
441
end
442
endgenerate // index==1
443
generate if (number_of_clk==3 & index==2) begin
444
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
445
end
446
endgenerate // index==2
447
generate if (number_of_clk==3 & index==3) begin
448
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
449
end
450
endgenerate // index==0
451
 
452
genvar i;
453
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
454 40 unneback
`define MODULE sync_rst
455
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
456
`undef MODULE
457 6 unneback
end
458
endgenerate
459
endmodule
460
`endif
461 32 unneback
///////////////////////////////////////////////////////////////////////////////
462 6 unneback
 
463
`else
464
 
465 32 unneback
///////////////////////////////////////////////////////////////////////////////
466 6 unneback
`ifdef ALTERA
467
 
468 32 unneback
`timescale 1 ps/1 ps
469 40 unneback
`define MODULE pll
470
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
471
`undef MODULE
472 32 unneback
parameter index = 0;
473
parameter number_of_clk = 1;
474
parameter period_time_0 = 20000;
475
parameter period_time_1 = 20000;
476
parameter period_time_2 = 20000;
477
parameter period_time_3 = 20000;
478
parameter period_time_4 = 20000;
479
parameter lock_delay = 2000000;
480
input clk_i, rst_n_i;
481
output lock;
482
output reg [0:number_of_clk-1] clk_o;
483
output [0:number_of_clk-1] rst_o;
484
 
485
`ifdef SIM_PLL
486
 
487
always
488
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
489
 
490
generate if (number_of_clk > 1)
491
always
492
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
493
endgenerate
494
 
495
generate if (number_of_clk > 2)
496
always
497
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
498
endgenerate
499
 
500 33 unneback
generate if (number_of_clk > 3)
501 32 unneback
always
502
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
503
endgenerate
504
 
505 33 unneback
generate if (number_of_clk > 4)
506 32 unneback
always
507
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
508
endgenerate
509
 
510
genvar i;
511
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
512
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
513
end
514
endgenerate
515
 
516 33 unneback
//assign #lock_delay lock = rst_n_i;
517
assign lock = rst_n_i;
518 32 unneback
 
519
endmodule
520 6 unneback
`else
521
 
522 33 unneback
`ifdef VL_PLL0
523
`ifdef VL_PLL0_CLK1
524
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
525
`endif
526
`ifdef VL_PLL0_CLK2
527
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
528
`endif
529
`ifdef VL_PLL0_CLK3
530
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
531
`endif
532
`ifdef VL_PLL0_CLK4
533
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
534
`endif
535
`ifdef VL_PLL0_CLK5
536
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
537
`endif
538
`endif
539 32 unneback
 
540 33 unneback
`ifdef VL_PLL1
541
`ifdef VL_PLL1_CLK1
542
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
543
`endif
544
`ifdef VL_PLL1_CLK2
545
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
546
`endif
547
`ifdef VL_PLL1_CLK3
548
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
549
`endif
550
`ifdef VL_PLL1_CLK4
551
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
552
`endif
553
`ifdef VL_PLL1_CLK5
554
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
555
`endif
556
`endif
557 32 unneback
 
558 33 unneback
`ifdef VL_PLL2
559
`ifdef VL_PLL2_CLK1
560
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
561
`endif
562
`ifdef VL_PLL2_CLK2
563
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
564
`endif
565
`ifdef VL_PLL2_CLK3
566
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
567
`endif
568
`ifdef VL_PLL2_CLK4
569
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
570
`endif
571
`ifdef VL_PLL2_CLK5
572
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
573
`endif
574
`endif
575 32 unneback
 
576 33 unneback
`ifdef VL_PLL3
577
`ifdef VL_PLL3_CLK1
578
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
579
`endif
580
`ifdef VL_PLL3_CLK2
581
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
582
`endif
583
`ifdef VL_PLL3_CLK3
584
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
585
`endif
586
`ifdef VL_PLL3_CLK4
587
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
588
`endif
589
`ifdef VL_PLL3_CLK5
590
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
591
`endif
592
`endif
593 32 unneback
 
594
genvar i;
595
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
596 40 unneback
`define MODULE sync_rst
597
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
598
`undef MODULE
599 32 unneback
end
600
endgenerate
601
endmodule
602
`endif
603
///////////////////////////////////////////////////////////////////////////////
604
 
605
`else
606
 
607 6 unneback
// generic PLL
608 17 unneback
`timescale 1 ps/1 ps
609 40 unneback
`define MODULE pll
610
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
611
`undef MODULE
612 6 unneback
parameter index = 0;
613
parameter number_of_clk = 1;
614 17 unneback
parameter period_time_0 = 20000;
615
parameter period_time_1 = 20000;
616
parameter period_time_2 = 20000;
617 6 unneback
parameter lock_delay = 2000;
618
input clk_i, rst_n_i;
619
output lock;
620
output reg [0:number_of_clk-1] clk_o;
621
output [0:number_of_clk-1] rst_o;
622
 
623
always
624
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
625
 
626
generate if (number_of_clk > 1)
627
always
628
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
629
endgenerate
630
 
631
generate if (number_of_clk > 2)
632
always
633
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
634
endgenerate
635
 
636
genvar i;
637
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
638 40 unneback
`define MODULE sync_rst
639
     `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
640
`undef MODULE
641 6 unneback
end
642
endgenerate
643
 
644
assign #lock_delay lock = rst_n_i;
645
 
646
endmodule
647
 
648
`endif //altera
649 17 unneback
`endif //actel
650 40 unneback
`undef MODULE
651
`endif//////////////////////////////////////////////////////////////////////
652 6 unneback
////                                                              ////
653
////  Versatile library, registers                                ////
654
////                                                              ////
655
////  Description                                                 ////
656
////  Different type of registers                                 ////
657
////                                                              ////
658
////                                                              ////
659
////  To Do:                                                      ////
660
////   - add more different registers                             ////
661
////                                                              ////
662
////  Author(s):                                                  ////
663
////      - Michael Unneback, unneback@opencores.org              ////
664
////        ORSoC AB                                              ////
665
////                                                              ////
666
//////////////////////////////////////////////////////////////////////
667
////                                                              ////
668
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
669
////                                                              ////
670
//// This source file may be used and distributed without         ////
671
//// restriction provided that this copyright statement is not    ////
672
//// removed from the file and that any derivative work contains  ////
673
//// the original copyright notice and the associated disclaimer. ////
674
////                                                              ////
675
//// This source file is free software; you can redistribute it   ////
676
//// and/or modify it under the terms of the GNU Lesser General   ////
677
//// Public License as published by the Free Software Foundation; ////
678
//// either version 2.1 of the License, or (at your option) any   ////
679
//// later version.                                               ////
680
////                                                              ////
681
//// This source is distributed in the hope that it will be       ////
682
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
683
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
684
//// PURPOSE.  See the GNU Lesser General Public License for more ////
685
//// details.                                                     ////
686
////                                                              ////
687
//// You should have received a copy of the GNU Lesser General    ////
688
//// Public License along with this source; if not, download it   ////
689
//// from http://www.opencores.org/lgpl.shtml                     ////
690
////                                                              ////
691
//////////////////////////////////////////////////////////////////////
692
 
693 40 unneback
`ifdef DFF
694
`define MODULE dff
695
module `BASE`MODULE ( d, q, clk, rst);
696
`undef MODULE
697 6 unneback
        parameter width = 1;
698
        parameter reset_value = 0;
699
 
700
        input [width-1:0] d;
701
        input clk, rst;
702
        output reg [width-1:0] q;
703
 
704
        always @ (posedge clk or posedge rst)
705
        if (rst)
706
                q <= reset_value;
707
        else
708
                q <= d;
709
 
710
endmodule
711 40 unneback
`endif
712 6 unneback
 
713 40 unneback
`ifdef DFF_ARRAY
714
`define MODULE dff_array
715
module `BASE`MODULE ( d, q, clk, rst);
716
`undef MODULE
717 6 unneback
 
718
        parameter width = 1;
719
        parameter depth = 2;
720
        parameter reset_value = 1'b0;
721
 
722
        input [width-1:0] d;
723
        input clk, rst;
724
        output [width-1:0] q;
725
        reg  [0:depth-1] q_tmp [width-1:0];
726
        integer i;
727
        always @ (posedge clk or posedge rst)
728
        if (rst) begin
729
            for (i=0;i<depth;i=i+1)
730
                q_tmp[i] <= {width{reset_value}};
731
        end else begin
732
            q_tmp[0] <= d;
733
            for (i=1;i<depth;i=i+1)
734
                q_tmp[i] <= q_tmp[i-1];
735
        end
736
 
737
    assign q = q_tmp[depth-1];
738
 
739
endmodule
740 40 unneback
`endif
741 6 unneback
 
742 40 unneback
`ifdef DFF_CE
743
`define MODULE dff_ce
744
module `BASE`MODULE ( d, ce, q, clk, rst);
745
`undef MODULE
746 6 unneback
 
747
        parameter width = 1;
748
        parameter reset_value = 0;
749
 
750
        input [width-1:0] d;
751
        input ce, clk, rst;
752
        output reg [width-1:0] q;
753
 
754
        always @ (posedge clk or posedge rst)
755
        if (rst)
756
                q <= reset_value;
757
        else
758
                if (ce)
759
                        q <= d;
760
 
761
endmodule
762 40 unneback
`endif
763 6 unneback
 
764 40 unneback
`ifdef DFF_CE_CLEAR
765
`define MODULE dff_ce_clear
766
module `BASE`MODULE ( d, ce, clear, q, clk, rst);
767
`undef MODULE
768 8 unneback
 
769
        parameter width = 1;
770
        parameter reset_value = 0;
771
 
772
        input [width-1:0] d;
773 10 unneback
        input ce, clear, clk, rst;
774 8 unneback
        output reg [width-1:0] q;
775
 
776
        always @ (posedge clk or posedge rst)
777
        if (rst)
778
            q <= reset_value;
779
        else
780
            if (ce)
781
                if (clear)
782
                    q <= {width{1'b0}};
783
                else
784
                    q <= d;
785
 
786
endmodule
787 40 unneback
`endif
788 8 unneback
 
789 40 unneback
`ifdef DF_CE_SET
790
`define MODULE dff_ce_set
791
module `BASE`MODULE ( d, ce, set, q, clk, rst);
792
`undef MODULE
793 24 unneback
 
794
        parameter width = 1;
795
        parameter reset_value = 0;
796
 
797
        input [width-1:0] d;
798
        input ce, set, clk, rst;
799
        output reg [width-1:0] q;
800
 
801
        always @ (posedge clk or posedge rst)
802
        if (rst)
803
            q <= reset_value;
804
        else
805
            if (ce)
806
                if (set)
807
                    q <= {width{1'b1}};
808
                else
809
                    q <= d;
810
 
811
endmodule
812 40 unneback
`endif
813 24 unneback
 
814 40 unneback
`ifdef SPR
815
`define MODULE spr
816
module `BASE`MODULE ( sp, r, q, clk, rst);
817
`undef MODULE
818
 
819 29 unneback
        parameter width = 1;
820
        parameter reset_value = 0;
821
 
822
        input sp, r;
823
        output reg q;
824
        input clk, rst;
825
 
826
        always @ (posedge clk or posedge rst)
827
        if (rst)
828
            q <= reset_value;
829
        else
830
            if (sp)
831
                q <= 1'b1;
832
            else if (r)
833
                q <= 1'b0;
834
 
835
endmodule
836 40 unneback
`endif
837 29 unneback
 
838 40 unneback
`ifdef SRP
839
`define MODULE srp
840
module `BASE`MODULE ( s, rp, q, clk, rst);
841
`undef MODULE
842
 
843 29 unneback
        parameter width = 1;
844
        parameter reset_value = 0;
845
 
846
        input s, rp;
847
        output reg q;
848
        input clk, rst;
849
 
850
        always @ (posedge clk or posedge rst)
851
        if (rst)
852
            q <= reset_value;
853
        else
854
            if (rp)
855
                q <= 1'b0;
856
            else if (s)
857
                q <= 1'b1;
858
 
859
endmodule
860 40 unneback
`endif
861 29 unneback
 
862 40 unneback
`ifdef ALTERA
863 29 unneback
 
864 40 unneback
`ifdef DFF_SR
865 6 unneback
// megafunction wizard: %LPM_FF%
866
// GENERATION: STANDARD
867
// VERSION: WM1.0
868
// MODULE: lpm_ff 
869
 
870
// ============================================================
871
// File Name: dff_sr.v
872
// Megafunction Name(s):
873
//                      lpm_ff
874
//
875
// Simulation Library Files(s):
876
//                      lpm
877
// ============================================================
878
// ************************************************************
879
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
880
//
881
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
882
// ************************************************************
883
 
884
 
885
//Copyright (C) 1991-2010 Altera Corporation
886
//Your use of Altera Corporation's design tools, logic functions 
887
//and other software and tools, and its AMPP partner logic 
888
//functions, and any output files from any of the foregoing 
889
//(including device programming or simulation files), and any 
890
//associated documentation or information are expressly subject 
891
//to the terms and conditions of the Altera Program License 
892
//Subscription Agreement, Altera MegaCore Function License 
893
//Agreement, or other applicable license agreement, including, 
894
//without limitation, that your use is for the sole purpose of 
895
//programming logic devices manufactured by Altera and sold by 
896
//Altera or its authorized distributors.  Please refer to the 
897
//applicable agreement for further details.
898
 
899
 
900
// synopsys translate_off
901
`timescale 1 ps / 1 ps
902
// synopsys translate_on
903 40 unneback
`define MODULE dff_sr
904
module `BASE`MODULE (
905
`undef MODULE
906
 
907 6 unneback
        aclr,
908
        aset,
909
        clock,
910
        data,
911
        q);
912
 
913
        input     aclr;
914
        input     aset;
915
        input     clock;
916
        input     data;
917
        output    q;
918
 
919
        wire [0:0] sub_wire0;
920
        wire [0:0] sub_wire1 = sub_wire0[0:0];
921
        wire  q = sub_wire1;
922
        wire  sub_wire2 = data;
923
        wire  sub_wire3 = sub_wire2;
924
 
925
        lpm_ff  lpm_ff_component (
926
                                .aclr (aclr),
927
                                .clock (clock),
928
                                .data (sub_wire3),
929
                                .aset (aset),
930
                                .q (sub_wire0)
931
                                // synopsys translate_off
932
                                ,
933
                                .aload (),
934
                                .enable (),
935
                                .sclr (),
936
                                .sload (),
937
                                .sset ()
938
                                // synopsys translate_on
939
                                );
940
        defparam
941
                lpm_ff_component.lpm_fftype = "DFF",
942
                lpm_ff_component.lpm_type = "LPM_FF",
943
                lpm_ff_component.lpm_width = 1;
944
 
945
 
946
endmodule
947
 
948
// ============================================================
949
// CNX file retrieval info
950
// ============================================================
951
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
952
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
953
// Retrieval info: PRIVATE: ASET NUMERIC "1"
954
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
955
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
956
// Retrieval info: PRIVATE: DFF NUMERIC "1"
957
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
958
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
959
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
960
// Retrieval info: PRIVATE: SSET NUMERIC "0"
961
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
962
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
963
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
964
// Retrieval info: PRIVATE: nBit NUMERIC "1"
965
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
966
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
967
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
968
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
969
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
970
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
971
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
972
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
973
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
974
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
975
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
976
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
977
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
978
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
979
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
980
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
981
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
982
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
983
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
984
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
985
// Retrieval info: LIB_FILE: lpm
986 40 unneback
`endif
987 6 unneback
 
988
`else
989
 
990 40 unneback
`ifdef DFF_SR
991
`define MODULE dff_sr
992
module `BASE`MODULE ( aclr, aset, clock, data, q);
993
`undef MODULE
994 6 unneback
 
995
    input         aclr;
996
    input         aset;
997
    input         clock;
998
    input         data;
999
    output reg    q;
1000
 
1001
   always @ (posedge clock or posedge aclr or posedge aset)
1002
     if (aclr)
1003
       q <= 1'b0;
1004
     else if (aset)
1005
       q <= 1'b1;
1006
     else
1007
       q <= data;
1008
 
1009
endmodule
1010 40 unneback
`endif
1011 6 unneback
 
1012
`endif
1013
 
1014
// LATCH
1015
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
1016
`ifdef ALTERA
1017 40 unneback
 
1018
`ifdef LATCH
1019
`define MODULE latch
1020
module `BASE`MODULE ( d, le, q, clk);
1021
`undef MODULE
1022 6 unneback
input d, le;
1023
output q;
1024
input clk;
1025
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
1026
endmodule
1027 40 unneback
`endif
1028
 
1029 6 unneback
`else
1030 40 unneback
 
1031
`ifdef LATCH
1032
`define MODULE latch
1033
module `BASE`MODULE ( d, le, q, clk);
1034
`undef MODULE
1035 6 unneback
input d, le;
1036 48 unneback
input clk;
1037
always @ (le or d)
1038
if le
1039
    d <= q;
1040 6 unneback
endmodule
1041 15 unneback
`endif
1042
 
1043 40 unneback
`endif
1044
 
1045
`ifdef SHREG
1046
`define MODULE shreg
1047
module `BASE`MODULE ( d, q, clk, rst);
1048
`undef MODULE
1049
 
1050 17 unneback
parameter depth = 10;
1051
input d;
1052
output q;
1053
input clk, rst;
1054
 
1055
reg [1:depth] dffs;
1056
 
1057
always @ (posedge clk or posedge rst)
1058
if (rst)
1059
    dffs <= {depth{1'b0}};
1060
else
1061
    dffs <= {d,dffs[1:depth-1]};
1062
assign q = dffs[depth];
1063
endmodule
1064 40 unneback
`endif
1065 17 unneback
 
1066 40 unneback
`ifdef SHREG_CE
1067
`define MODULE shreg_ce
1068
module `BASE`MODULE ( d, ce, q, clk, rst);
1069
`undef MODULE
1070 17 unneback
parameter depth = 10;
1071
input d, ce;
1072
output q;
1073
input clk, rst;
1074
 
1075
reg [1:depth] dffs;
1076
 
1077
always @ (posedge clk or posedge rst)
1078
if (rst)
1079
    dffs <= {depth{1'b0}};
1080
else
1081
    if (ce)
1082
        dffs <= {d,dffs[1:depth-1]};
1083
assign q = dffs[depth];
1084
endmodule
1085 40 unneback
`endif
1086 17 unneback
 
1087 40 unneback
`ifdef DELAY
1088
`define MODULE delay
1089
module `BASE`MODULE ( d, q, clk, rst);
1090
`undef MODULE
1091 15 unneback
parameter depth = 10;
1092
input d;
1093
output q;
1094
input clk, rst;
1095
 
1096
reg [1:depth] dffs;
1097
 
1098
always @ (posedge clk or posedge rst)
1099
if (rst)
1100
    dffs <= {depth{1'b0}};
1101
else
1102
    dffs <= {d,dffs[1:depth-1]};
1103
assign q = dffs[depth];
1104 17 unneback
endmodule
1105 40 unneback
`endif
1106 17 unneback
 
1107 40 unneback
`ifdef DELAY_EMPTYFLAG
1108
`define MODULE delay_emptyflag
1109 41 unneback
module `BASE`MODULE ( d, q, emptyflag, clk, rst);
1110 40 unneback
`undef MODULE
1111 17 unneback
parameter depth = 10;
1112
input d;
1113
output q, emptyflag;
1114
input clk, rst;
1115
 
1116
reg [1:depth] dffs;
1117
 
1118
always @ (posedge clk or posedge rst)
1119
if (rst)
1120
    dffs <= {depth{1'b0}};
1121
else
1122
    dffs <= {d,dffs[1:depth-1]};
1123
assign q = dffs[depth];
1124
assign emptyflag = !(|dffs);
1125
endmodule
1126 40 unneback
`endif
1127 17 unneback
//////////////////////////////////////////////////////////////////////
1128 6 unneback
////                                                              ////
1129 18 unneback
////  Logic functions                                             ////
1130
////                                                              ////
1131
////  Description                                                 ////
1132
////  Logic functions such as multiplexers                        ////
1133
////                                                              ////
1134
////                                                              ////
1135
////  To Do:                                                      ////
1136
////   -                                                          ////
1137
////                                                              ////
1138
////  Author(s):                                                  ////
1139
////      - Michael Unneback, unneback@opencores.org              ////
1140
////        ORSoC AB                                              ////
1141
////                                                              ////
1142
//////////////////////////////////////////////////////////////////////
1143
////                                                              ////
1144
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1145
////                                                              ////
1146
//// This source file may be used and distributed without         ////
1147
//// restriction provided that this copyright statement is not    ////
1148
//// removed from the file and that any derivative work contains  ////
1149
//// the original copyright notice and the associated disclaimer. ////
1150
////                                                              ////
1151
//// This source file is free software; you can redistribute it   ////
1152
//// and/or modify it under the terms of the GNU Lesser General   ////
1153
//// Public License as published by the Free Software Foundation; ////
1154
//// either version 2.1 of the License, or (at your option) any   ////
1155
//// later version.                                               ////
1156
////                                                              ////
1157
//// This source is distributed in the hope that it will be       ////
1158
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1159
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1160
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1161
//// details.                                                     ////
1162
////                                                              ////
1163
//// You should have received a copy of the GNU Lesser General    ////
1164
//// Public License along with this source; if not, download it   ////
1165
//// from http://www.opencores.org/lgpl.shtml                     ////
1166
////                                                              ////
1167
//////////////////////////////////////////////////////////////////////
1168 40 unneback
`ifdef MUX_ANDOR
1169
`define MODULE mux_andor
1170
module `BASE`MODULE ( a, sel, dout);
1171
`undef MODULE
1172 36 unneback
 
1173
parameter width = 32;
1174
parameter nr_of_ports = 4;
1175
 
1176
input [nr_of_ports*width-1:0] a;
1177
input [nr_of_ports-1:0] sel;
1178
output reg [width-1:0] dout;
1179
 
1180 38 unneback
integer i,j;
1181
 
1182 36 unneback
always @ (a, sel)
1183
begin
1184
    dout = a[width-1:0] & {width{sel[0]}};
1185 42 unneback
    for (i=1;i<nr_of_ports;i=i+1)
1186
        for (j=0;j<width;j=j+1)
1187
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
1188 36 unneback
end
1189
 
1190
endmodule
1191 40 unneback
`endif
1192 36 unneback
 
1193 40 unneback
`ifdef MUX2_ANDOR
1194
`define MODULE mux2_andor
1195
module `BASE`MODULE ( a1, a0, sel, dout);
1196
`undef MODULE
1197 18 unneback
 
1198 34 unneback
parameter width = 32;
1199 35 unneback
localparam nr_of_ports = 2;
1200 34 unneback
input [width-1:0] a1, a0;
1201
input [nr_of_ports-1:0] sel;
1202
output [width-1:0] dout;
1203
 
1204 40 unneback
`define MODULE mux_andor
1205
`BASE`MODULE
1206 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1207 36 unneback
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
1208 40 unneback
`undef MODULE
1209
 
1210 34 unneback
endmodule
1211 40 unneback
`endif
1212 34 unneback
 
1213 40 unneback
`ifdef MUX3_ANDOR
1214
`define MODULE mux3_andor
1215
module `BASE`MODULE ( a2, a1, a0, sel, dout);
1216
`undef MODULE
1217 34 unneback
 
1218
parameter width = 32;
1219 35 unneback
localparam nr_of_ports = 3;
1220 34 unneback
input [width-1:0] a2, a1, a0;
1221
input [nr_of_ports-1:0] sel;
1222
output [width-1:0] dout;
1223
 
1224 40 unneback
`define MODULE mux_andor
1225
`BASE`MODULE
1226 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1227 36 unneback
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
1228 40 unneback
`undef MODULE
1229 34 unneback
endmodule
1230 40 unneback
`endif
1231 34 unneback
 
1232 40 unneback
`ifdef MUX4_ANDOR
1233
`define MODULE mux4_andor
1234
module `BASE`MODULE ( a3, a2, a1, a0, sel, dout);
1235
`undef MODULE
1236 18 unneback
 
1237
parameter width = 32;
1238 35 unneback
localparam nr_of_ports = 4;
1239 18 unneback
input [width-1:0] a3, a2, a1, a0;
1240
input [nr_of_ports-1:0] sel;
1241 22 unneback
output [width-1:0] dout;
1242 18 unneback
 
1243 40 unneback
`define MODULE mux_andor
1244
`BASE`MODULE
1245 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1246 36 unneback
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
1247 40 unneback
`undef MODULE
1248 18 unneback
 
1249
endmodule
1250 40 unneback
`endif
1251 18 unneback
 
1252 40 unneback
`ifdef MUX5_ANDOR
1253
`define MODULE mux5_andor
1254
module `BASE`MODULE ( a4, a3, a2, a1, a0, sel, dout);
1255
`undef MODULE
1256 18 unneback
 
1257
parameter width = 32;
1258 35 unneback
localparam nr_of_ports = 5;
1259 18 unneback
input [width-1:0] a4, a3, a2, a1, a0;
1260
input [nr_of_ports-1:0] sel;
1261 22 unneback
output [width-1:0] dout;
1262 18 unneback
 
1263 40 unneback
`define MODULE mux_andor
1264
`BASE`MODULE
1265 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1266 36 unneback
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1267 40 unneback
`undef MODULE
1268 18 unneback
 
1269
endmodule
1270 40 unneback
`endif
1271 18 unneback
 
1272 40 unneback
`ifdef MUX6_ANDOR
1273
`define MODULE mux6_andor
1274
module `BASE`MODULE ( a5, a4, a3, a2, a1, a0, sel, dout);
1275
`undef MODULE
1276 18 unneback
 
1277
parameter width = 32;
1278 35 unneback
localparam nr_of_ports = 6;
1279 18 unneback
input [width-1:0] a5, a4, a3, a2, a1, a0;
1280
input [nr_of_ports-1:0] sel;
1281 22 unneback
output [width-1:0] dout;
1282 18 unneback
 
1283 40 unneback
`define MODULE mux_andor
1284
`BASE`MODULE
1285 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1286 36 unneback
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1287 40 unneback
`undef MODULE
1288 18 unneback
 
1289
endmodule
1290 40 unneback
`endif
1291 43 unneback
 
1292
`ifdef PARITY
1293
 
1294
`define MODULE parity_generate
1295
module `BASE`MODULE (data, parity);
1296
`undef MODULE
1297
parameter word_size = 32;
1298
parameter chunk_size = 8;
1299
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1300
input [word_size-1:0] data;
1301
output reg [word_size/chunk_size-1:0] parity;
1302
integer i,j;
1303
always @ (data)
1304
for (i=0;i<word_size/chunk_size;i=i+1) begin
1305
    parity[i] = parity_type;
1306
    for (j=0;j<chunk_size;j=j+1) begin
1307 46 unneback
        parity[i] = data[i*chunk_size+j] ^ parity[i];
1308 43 unneback
    end
1309
end
1310
endmodule
1311
 
1312
`define MODULE parity_check
1313
module `BASE`MODULE( data, parity, parity_error);
1314
`undef MODULE
1315
parameter word_size = 32;
1316
parameter chunk_size = 8;
1317
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1318
input [word_size-1:0] data;
1319
input [word_size/chunk_size-1:0] parity;
1320
output parity_error;
1321 44 unneback
reg [word_size/chunk_size-1:0] error_flag;
1322 43 unneback
integer i,j;
1323
always @ (data or parity)
1324
for (i=0;i<word_size/chunk_size;i=i+1) begin
1325
    error_flag[i] = parity[i] ^ parity_type;
1326
    for (j=0;j<chunk_size;j=j+1) begin
1327 46 unneback
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
1328 43 unneback
    end
1329
end
1330
assign parity_error = |error_flag;
1331
endmodule
1332
 
1333 44 unneback
`endif//////////////////////////////////////////////////////////////////////
1334
////                                                              ////
1335
////  IO functions                                                ////
1336
////                                                              ////
1337
////  Description                                                 ////
1338
////  IO functions such as IOB flip-flops                         ////
1339
////                                                              ////
1340
////                                                              ////
1341
////  To Do:                                                      ////
1342
////   -                                                          ////
1343
////                                                              ////
1344
////  Author(s):                                                  ////
1345
////      - Michael Unneback, unneback@opencores.org              ////
1346
////        ORSoC AB                                              ////
1347
////                                                              ////
1348 18 unneback
//////////////////////////////////////////////////////////////////////
1349
////                                                              ////
1350 44 unneback
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1351
////                                                              ////
1352
//// This source file may be used and distributed without         ////
1353
//// restriction provided that this copyright statement is not    ////
1354
//// removed from the file and that any derivative work contains  ////
1355
//// the original copyright notice and the associated disclaimer. ////
1356
////                                                              ////
1357
//// This source file is free software; you can redistribute it   ////
1358
//// and/or modify it under the terms of the GNU Lesser General   ////
1359
//// Public License as published by the Free Software Foundation; ////
1360
//// either version 2.1 of the License, or (at your option) any   ////
1361
//// later version.                                               ////
1362
////                                                              ////
1363
//// This source is distributed in the hope that it will be       ////
1364
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1365
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1366
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1367
//// details.                                                     ////
1368
////                                                              ////
1369
//// You should have received a copy of the GNU Lesser General    ////
1370
//// Public License along with this source; if not, download it   ////
1371
//// from http://www.opencores.org/lgpl.shtml                     ////
1372
////                                                              ////
1373
//////////////////////////////////////////////////////////////////////
1374 45 unneback
`timescale 1ns/1ns
1375 44 unneback
`ifdef O_DFF
1376
`define MODULE o_dff
1377
module `BASE`MODULE (d_i, o_pad, clk, rst);
1378
`undef MODULE
1379
parameter width = 1;
1380 45 unneback
parameter reset_value = {width{1'b0}};
1381
input  [width-1:0]  d_i;
1382 44 unneback
output [width-1:0] o_pad;
1383
input clk, rst;
1384
wire [width-1:0] d_i_int `SYN_KEEP;
1385 45 unneback
reg  [width-1:0] o_pad_int;
1386 44 unneback
assign d_i_int = d_i;
1387
genvar i;
1388 45 unneback
generate
1389 44 unneback
for (i=0;i<width;i=i+1) begin
1390
    always @ (posedge clk or posedge rst)
1391
    if (rst)
1392 45 unneback
        o_pad_int[i] <= reset_value[i];
1393 44 unneback
    else
1394 45 unneback
        o_pad_int[i] <= d_i_int[i];
1395
    assign #1 o_pad[i] = o_pad_int[i];
1396 44 unneback
end
1397
endgenerate
1398
endmodule
1399
`endif
1400
 
1401 45 unneback
`timescale 1ns/1ns
1402 44 unneback
`ifdef IO_DFF_OE
1403
`define MODULE io_dff_oe
1404
module `BASE`MODULE ( d_i, d_o, oe, io_pad, clk, rst);
1405
`undef MODULE
1406
parameter width = 1;
1407
input  [width-1:0] d_o;
1408
output reg [width-1:0] d_i;
1409
input oe;
1410
inout [width-1:0] io_pad;
1411
input clk, rst;
1412
wire [width-1:0] oe_d `SYN_KEEP;
1413
reg [width-1:0] oe_q;
1414
reg [width-1:0] d_o_q;
1415
assign oe_d = {width{oe}};
1416
genvar i;
1417
generate
1418
for (i=0;i<width;i=i+1) begin
1419
    always @ (posedge clk or posedge rst)
1420
    if (rst)
1421
        oe_q[i] <= 1'b0;
1422
    else
1423
        oe_q[i] <= oe_d[i];
1424
    always @ (posedge clk or posedge rst)
1425
    if (rst)
1426
        d_o_q[i] <= 1'b0;
1427
    else
1428
        d_o_q[i] <= d_o[i];
1429
    always @ (posedge clk or posedge rst)
1430
    if (rst)
1431
        d_i[i] <= 1'b0;
1432
    else
1433
        d_i[i] <= io_pad[i];
1434 45 unneback
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
1435 44 unneback
end
1436
endgenerate
1437
endmodule
1438
`endif
1439
`ifdef CNT_BIN
1440
//////////////////////////////////////////////////////////////////////
1441
////                                                              ////
1442 6 unneback
////  Versatile counter                                           ////
1443
////                                                              ////
1444
////  Description                                                 ////
1445
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1446
////  counter                                                     ////
1447
////                                                              ////
1448
////  To Do:                                                      ////
1449
////   - add LFSR with more taps                                  ////
1450
////                                                              ////
1451
////  Author(s):                                                  ////
1452
////      - Michael Unneback, unneback@opencores.org              ////
1453
////        ORSoC AB                                              ////
1454
////                                                              ////
1455
//////////////////////////////////////////////////////////////////////
1456
////                                                              ////
1457
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1458
////                                                              ////
1459
//// This source file may be used and distributed without         ////
1460
//// restriction provided that this copyright statement is not    ////
1461
//// removed from the file and that any derivative work contains  ////
1462
//// the original copyright notice and the associated disclaimer. ////
1463
////                                                              ////
1464
//// This source file is free software; you can redistribute it   ////
1465
//// and/or modify it under the terms of the GNU Lesser General   ////
1466
//// Public License as published by the Free Software Foundation; ////
1467
//// either version 2.1 of the License, or (at your option) any   ////
1468
//// later version.                                               ////
1469
////                                                              ////
1470
//// This source is distributed in the hope that it will be       ////
1471
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1472
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1473
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1474
//// details.                                                     ////
1475
////                                                              ////
1476
//// You should have received a copy of the GNU Lesser General    ////
1477
//// Public License along with this source; if not, download it   ////
1478
//// from http://www.opencores.org/lgpl.shtml                     ////
1479
////                                                              ////
1480
//////////////////////////////////////////////////////////////////////
1481
 
1482
// binary counter
1483 22 unneback
 
1484 40 unneback
`define MODULE cnt_bin
1485
module `BASE`MODULE (
1486
`undef MODULE
1487
 q, rst, clk);
1488
 
1489 22 unneback
   parameter length = 4;
1490
   output [length:1] q;
1491
   input rst;
1492
   input clk;
1493
 
1494
   parameter clear_value = 0;
1495
   parameter set_value = 1;
1496
   parameter wrap_value = 0;
1497
   parameter level1_value = 15;
1498
 
1499
   reg  [length:1] qi;
1500
   wire [length:1] q_next;
1501
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1502
 
1503
   always @ (posedge clk or posedge rst)
1504
     if (rst)
1505
       qi <= {length{1'b0}};
1506
     else
1507
       qi <= q_next;
1508
 
1509
   assign q = qi;
1510
 
1511
endmodule
1512 40 unneback
`endif
1513
`ifdef CNT_BIN_CLEAR
1514 22 unneback
//////////////////////////////////////////////////////////////////////
1515
////                                                              ////
1516
////  Versatile counter                                           ////
1517
////                                                              ////
1518
////  Description                                                 ////
1519
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1520
////  counter                                                     ////
1521
////                                                              ////
1522
////  To Do:                                                      ////
1523
////   - add LFSR with more taps                                  ////
1524
////                                                              ////
1525
////  Author(s):                                                  ////
1526
////      - Michael Unneback, unneback@opencores.org              ////
1527
////        ORSoC AB                                              ////
1528
////                                                              ////
1529
//////////////////////////////////////////////////////////////////////
1530
////                                                              ////
1531
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1532
////                                                              ////
1533
//// This source file may be used and distributed without         ////
1534
//// restriction provided that this copyright statement is not    ////
1535
//// removed from the file and that any derivative work contains  ////
1536
//// the original copyright notice and the associated disclaimer. ////
1537
////                                                              ////
1538
//// This source file is free software; you can redistribute it   ////
1539
//// and/or modify it under the terms of the GNU Lesser General   ////
1540
//// Public License as published by the Free Software Foundation; ////
1541
//// either version 2.1 of the License, or (at your option) any   ////
1542
//// later version.                                               ////
1543
////                                                              ////
1544
//// This source is distributed in the hope that it will be       ////
1545
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1546
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1547
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1548
//// details.                                                     ////
1549
////                                                              ////
1550
//// You should have received a copy of the GNU Lesser General    ////
1551
//// Public License along with this source; if not, download it   ////
1552
//// from http://www.opencores.org/lgpl.shtml                     ////
1553
////                                                              ////
1554
//////////////////////////////////////////////////////////////////////
1555
 
1556
// binary counter
1557
 
1558 40 unneback
`define MODULE cnt_bin_clear
1559
module `BASE`MODULE (
1560
`undef MODULE
1561
 clear, q, rst, clk);
1562
 
1563 22 unneback
   parameter length = 4;
1564
   input clear;
1565
   output [length:1] q;
1566
   input rst;
1567
   input clk;
1568
 
1569
   parameter clear_value = 0;
1570
   parameter set_value = 1;
1571
   parameter wrap_value = 0;
1572
   parameter level1_value = 15;
1573
 
1574
   reg  [length:1] qi;
1575
   wire [length:1] q_next;
1576
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1577
 
1578
   always @ (posedge clk or posedge rst)
1579
     if (rst)
1580
       qi <= {length{1'b0}};
1581
     else
1582
       qi <= q_next;
1583
 
1584
   assign q = qi;
1585
 
1586
endmodule
1587 40 unneback
`endif
1588
`ifdef CNT_BIN_CE
1589 22 unneback
//////////////////////////////////////////////////////////////////////
1590
////                                                              ////
1591
////  Versatile counter                                           ////
1592
////                                                              ////
1593
////  Description                                                 ////
1594
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1595
////  counter                                                     ////
1596
////                                                              ////
1597
////  To Do:                                                      ////
1598
////   - add LFSR with more taps                                  ////
1599
////                                                              ////
1600
////  Author(s):                                                  ////
1601
////      - Michael Unneback, unneback@opencores.org              ////
1602
////        ORSoC AB                                              ////
1603
////                                                              ////
1604
//////////////////////////////////////////////////////////////////////
1605
////                                                              ////
1606
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1607
////                                                              ////
1608
//// This source file may be used and distributed without         ////
1609
//// restriction provided that this copyright statement is not    ////
1610
//// removed from the file and that any derivative work contains  ////
1611
//// the original copyright notice and the associated disclaimer. ////
1612
////                                                              ////
1613
//// This source file is free software; you can redistribute it   ////
1614
//// and/or modify it under the terms of the GNU Lesser General   ////
1615
//// Public License as published by the Free Software Foundation; ////
1616
//// either version 2.1 of the License, or (at your option) any   ////
1617
//// later version.                                               ////
1618
////                                                              ////
1619
//// This source is distributed in the hope that it will be       ////
1620
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1621
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1622
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1623
//// details.                                                     ////
1624
////                                                              ////
1625
//// You should have received a copy of the GNU Lesser General    ////
1626
//// Public License along with this source; if not, download it   ////
1627
//// from http://www.opencores.org/lgpl.shtml                     ////
1628
////                                                              ////
1629
//////////////////////////////////////////////////////////////////////
1630
 
1631
// binary counter
1632 6 unneback
 
1633 40 unneback
`define MODULE cnt_bin_ce
1634
module `BASE`MODULE (
1635
`undef MODULE
1636
 cke, q, rst, clk);
1637
 
1638 6 unneback
   parameter length = 4;
1639
   input cke;
1640
   output [length:1] q;
1641
   input rst;
1642
   input clk;
1643
 
1644
   parameter clear_value = 0;
1645
   parameter set_value = 1;
1646
   parameter wrap_value = 0;
1647
   parameter level1_value = 15;
1648
 
1649
   reg  [length:1] qi;
1650
   wire [length:1] q_next;
1651
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1652
 
1653
   always @ (posedge clk or posedge rst)
1654
     if (rst)
1655
       qi <= {length{1'b0}};
1656
     else
1657
     if (cke)
1658
       qi <= q_next;
1659
 
1660
   assign q = qi;
1661
 
1662
endmodule
1663 40 unneback
`endif
1664
`ifdef CNT_BIN_CE_CLEAR
1665 6 unneback
//////////////////////////////////////////////////////////////////////
1666
////                                                              ////
1667
////  Versatile counter                                           ////
1668
////                                                              ////
1669
////  Description                                                 ////
1670
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1671
////  counter                                                     ////
1672
////                                                              ////
1673
////  To Do:                                                      ////
1674
////   - add LFSR with more taps                                  ////
1675
////                                                              ////
1676
////  Author(s):                                                  ////
1677
////      - Michael Unneback, unneback@opencores.org              ////
1678
////        ORSoC AB                                              ////
1679
////                                                              ////
1680
//////////////////////////////////////////////////////////////////////
1681
////                                                              ////
1682
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1683
////                                                              ////
1684
//// This source file may be used and distributed without         ////
1685
//// restriction provided that this copyright statement is not    ////
1686
//// removed from the file and that any derivative work contains  ////
1687
//// the original copyright notice and the associated disclaimer. ////
1688
////                                                              ////
1689
//// This source file is free software; you can redistribute it   ////
1690
//// and/or modify it under the terms of the GNU Lesser General   ////
1691
//// Public License as published by the Free Software Foundation; ////
1692
//// either version 2.1 of the License, or (at your option) any   ////
1693
//// later version.                                               ////
1694
////                                                              ////
1695
//// This source is distributed in the hope that it will be       ////
1696
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1697
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1698
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1699
//// details.                                                     ////
1700
////                                                              ////
1701
//// You should have received a copy of the GNU Lesser General    ////
1702
//// Public License along with this source; if not, download it   ////
1703
//// from http://www.opencores.org/lgpl.shtml                     ////
1704
////                                                              ////
1705
//////////////////////////////////////////////////////////////////////
1706
 
1707
// binary counter
1708
 
1709 40 unneback
`define MODULE cnt_bin_ce_clear
1710
module `BASE`MODULE (
1711
`undef MODULE
1712
 clear, cke, q, rst, clk);
1713
 
1714 6 unneback
   parameter length = 4;
1715
   input clear;
1716
   input cke;
1717
   output [length:1] q;
1718
   input rst;
1719
   input clk;
1720
 
1721
   parameter clear_value = 0;
1722
   parameter set_value = 1;
1723
   parameter wrap_value = 0;
1724
   parameter level1_value = 15;
1725
 
1726
   reg  [length:1] qi;
1727
   wire [length:1] q_next;
1728
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1729
 
1730
   always @ (posedge clk or posedge rst)
1731
     if (rst)
1732
       qi <= {length{1'b0}};
1733
     else
1734
     if (cke)
1735
       qi <= q_next;
1736
 
1737
   assign q = qi;
1738
 
1739
endmodule
1740 40 unneback
`endif
1741
`ifdef CNT_BIN_CE_CLEAR_L1_L2
1742 6 unneback
//////////////////////////////////////////////////////////////////////
1743
////                                                              ////
1744
////  Versatile counter                                           ////
1745
////                                                              ////
1746
////  Description                                                 ////
1747
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1748
////  counter                                                     ////
1749
////                                                              ////
1750
////  To Do:                                                      ////
1751
////   - add LFSR with more taps                                  ////
1752
////                                                              ////
1753
////  Author(s):                                                  ////
1754
////      - Michael Unneback, unneback@opencores.org              ////
1755
////        ORSoC AB                                              ////
1756
////                                                              ////
1757
//////////////////////////////////////////////////////////////////////
1758
////                                                              ////
1759
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1760
////                                                              ////
1761
//// This source file may be used and distributed without         ////
1762
//// restriction provided that this copyright statement is not    ////
1763
//// removed from the file and that any derivative work contains  ////
1764
//// the original copyright notice and the associated disclaimer. ////
1765
////                                                              ////
1766
//// This source file is free software; you can redistribute it   ////
1767
//// and/or modify it under the terms of the GNU Lesser General   ////
1768
//// Public License as published by the Free Software Foundation; ////
1769
//// either version 2.1 of the License, or (at your option) any   ////
1770
//// later version.                                               ////
1771
////                                                              ////
1772
//// This source is distributed in the hope that it will be       ////
1773
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1774
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1775
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1776
//// details.                                                     ////
1777
////                                                              ////
1778
//// You should have received a copy of the GNU Lesser General    ////
1779
//// Public License along with this source; if not, download it   ////
1780
//// from http://www.opencores.org/lgpl.shtml                     ////
1781
////                                                              ////
1782
//////////////////////////////////////////////////////////////////////
1783
 
1784
// binary counter
1785 29 unneback
 
1786 40 unneback
`define MODULE cnt_bin_ce_clear_l1_l2
1787
module `BASE`MODULE (
1788
`undef MODULE
1789
 clear, cke, q, level1, level2, rst, clk);
1790
 
1791 29 unneback
   parameter length = 4;
1792
   input clear;
1793
   input cke;
1794
   output [length:1] q;
1795
   output reg level1;
1796
   output reg level2;
1797
   input rst;
1798
   input clk;
1799
 
1800
   parameter clear_value = 0;
1801
   parameter set_value = 1;
1802 30 unneback
   parameter wrap_value = 15;
1803
   parameter level1_value = 8;
1804
   parameter level2_value = 15;
1805 29 unneback
 
1806
   wire rew;
1807 30 unneback
   assign rew = 1'b0;
1808 29 unneback
   reg  [length:1] qi;
1809
   wire [length:1] q_next;
1810
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1811
 
1812
   always @ (posedge clk or posedge rst)
1813
     if (rst)
1814
       qi <= {length{1'b0}};
1815
     else
1816
     if (cke)
1817
       qi <= q_next;
1818
 
1819
   assign q = qi;
1820
 
1821
 
1822
    always @ (posedge clk or posedge rst)
1823
    if (rst)
1824
        level1 <= 1'b0;
1825
    else
1826
    if (cke)
1827
    if (clear)
1828
        level1 <= 1'b0;
1829
    else if (q_next == level1_value)
1830
        level1 <= 1'b1;
1831
    else if (qi == level1_value & rew)
1832
        level1 <= 1'b0;
1833
 
1834
    always @ (posedge clk or posedge rst)
1835
    if (rst)
1836
        level2 <= 1'b0;
1837
    else
1838
    if (cke)
1839
    if (clear)
1840
        level2 <= 1'b0;
1841
    else if (q_next == level2_value)
1842
        level2 <= 1'b1;
1843
    else if (qi == level2_value & rew)
1844
        level2 <= 1'b0;
1845
endmodule
1846 40 unneback
`endif
1847
`ifdef CNT_BIN_CE_CLEAR_SET_REW
1848 29 unneback
//////////////////////////////////////////////////////////////////////
1849
////                                                              ////
1850
////  Versatile counter                                           ////
1851
////                                                              ////
1852
////  Description                                                 ////
1853
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1854
////  counter                                                     ////
1855
////                                                              ////
1856
////  To Do:                                                      ////
1857
////   - add LFSR with more taps                                  ////
1858
////                                                              ////
1859
////  Author(s):                                                  ////
1860
////      - Michael Unneback, unneback@opencores.org              ////
1861
////        ORSoC AB                                              ////
1862
////                                                              ////
1863
//////////////////////////////////////////////////////////////////////
1864
////                                                              ////
1865
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1866
////                                                              ////
1867
//// This source file may be used and distributed without         ////
1868
//// restriction provided that this copyright statement is not    ////
1869
//// removed from the file and that any derivative work contains  ////
1870
//// the original copyright notice and the associated disclaimer. ////
1871
////                                                              ////
1872
//// This source file is free software; you can redistribute it   ////
1873
//// and/or modify it under the terms of the GNU Lesser General   ////
1874
//// Public License as published by the Free Software Foundation; ////
1875
//// either version 2.1 of the License, or (at your option) any   ////
1876
//// later version.                                               ////
1877
////                                                              ////
1878
//// This source is distributed in the hope that it will be       ////
1879
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1880
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1881
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1882
//// details.                                                     ////
1883
////                                                              ////
1884
//// You should have received a copy of the GNU Lesser General    ////
1885
//// Public License along with this source; if not, download it   ////
1886
//// from http://www.opencores.org/lgpl.shtml                     ////
1887
////                                                              ////
1888
//////////////////////////////////////////////////////////////////////
1889
 
1890
// binary counter
1891 6 unneback
 
1892 40 unneback
`define MODULE cnt_bin_ce_clear_set_rew
1893
module `BASE`MODULE (
1894
`undef MODULE
1895
 clear, set, cke, rew, q, rst, clk);
1896
 
1897 6 unneback
   parameter length = 4;
1898
   input clear;
1899
   input set;
1900
   input cke;
1901
   input rew;
1902
   output [length:1] q;
1903
   input rst;
1904
   input clk;
1905
 
1906
   parameter clear_value = 0;
1907
   parameter set_value = 1;
1908
   parameter wrap_value = 0;
1909
   parameter level1_value = 15;
1910
 
1911
   reg  [length:1] qi;
1912
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1913
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
1914
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
1915
   assign q_next = rew ? q_next_rew : q_next_fw;
1916
 
1917
   always @ (posedge clk or posedge rst)
1918
     if (rst)
1919
       qi <= {length{1'b0}};
1920
     else
1921
     if (cke)
1922
       qi <= q_next;
1923
 
1924
   assign q = qi;
1925
 
1926
endmodule
1927 40 unneback
`endif
1928
`ifdef CNT_BIN_CE_REW_L1
1929 6 unneback
//////////////////////////////////////////////////////////////////////
1930
////                                                              ////
1931
////  Versatile counter                                           ////
1932
////                                                              ////
1933
////  Description                                                 ////
1934
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1935
////  counter                                                     ////
1936
////                                                              ////
1937
////  To Do:                                                      ////
1938
////   - add LFSR with more taps                                  ////
1939
////                                                              ////
1940
////  Author(s):                                                  ////
1941
////      - Michael Unneback, unneback@opencores.org              ////
1942
////        ORSoC AB                                              ////
1943
////                                                              ////
1944
//////////////////////////////////////////////////////////////////////
1945
////                                                              ////
1946
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1947
////                                                              ////
1948
//// This source file may be used and distributed without         ////
1949
//// restriction provided that this copyright statement is not    ////
1950
//// removed from the file and that any derivative work contains  ////
1951
//// the original copyright notice and the associated disclaimer. ////
1952
////                                                              ////
1953
//// This source file is free software; you can redistribute it   ////
1954
//// and/or modify it under the terms of the GNU Lesser General   ////
1955
//// Public License as published by the Free Software Foundation; ////
1956
//// either version 2.1 of the License, or (at your option) any   ////
1957
//// later version.                                               ////
1958
////                                                              ////
1959
//// This source is distributed in the hope that it will be       ////
1960
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1961
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1962
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1963
//// details.                                                     ////
1964
////                                                              ////
1965
//// You should have received a copy of the GNU Lesser General    ////
1966
//// Public License along with this source; if not, download it   ////
1967
//// from http://www.opencores.org/lgpl.shtml                     ////
1968
////                                                              ////
1969
//////////////////////////////////////////////////////////////////////
1970
 
1971
// binary counter
1972
 
1973 40 unneback
`define MODULE cnt_bin_ce_rew_l1
1974
module `BASE`MODULE (
1975
`undef MODULE
1976
 cke, rew, level1, rst, clk);
1977
 
1978 6 unneback
   parameter length = 4;
1979
   input cke;
1980
   input rew;
1981
   output reg level1;
1982
   input rst;
1983
   input clk;
1984
 
1985
   parameter clear_value = 0;
1986
   parameter set_value = 1;
1987
   parameter wrap_value = 1;
1988
   parameter level1_value = 15;
1989
 
1990 29 unneback
   wire clear;
1991 30 unneback
   assign clear = 1'b0;
1992 6 unneback
   reg  [length:1] qi;
1993
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1994
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1995
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1996
   assign q_next = rew ? q_next_rew : q_next_fw;
1997
 
1998
   always @ (posedge clk or posedge rst)
1999
     if (rst)
2000
       qi <= {length{1'b0}};
2001
     else
2002
     if (cke)
2003
       qi <= q_next;
2004
 
2005
 
2006
 
2007
    always @ (posedge clk or posedge rst)
2008
    if (rst)
2009
        level1 <= 1'b0;
2010
    else
2011
    if (cke)
2012 29 unneback
    if (clear)
2013
        level1 <= 1'b0;
2014
    else if (q_next == level1_value)
2015 6 unneback
        level1 <= 1'b1;
2016
    else if (qi == level1_value & rew)
2017
        level1 <= 1'b0;
2018
endmodule
2019 40 unneback
`endif
2020
`ifdef CNT_BIN_CE_REW_ZQ_L1
2021 6 unneback
//////////////////////////////////////////////////////////////////////
2022
////                                                              ////
2023
////  Versatile counter                                           ////
2024
////                                                              ////
2025
////  Description                                                 ////
2026
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2027
////  counter                                                     ////
2028
////                                                              ////
2029
////  To Do:                                                      ////
2030
////   - add LFSR with more taps                                  ////
2031
////                                                              ////
2032
////  Author(s):                                                  ////
2033
////      - Michael Unneback, unneback@opencores.org              ////
2034
////        ORSoC AB                                              ////
2035
////                                                              ////
2036
//////////////////////////////////////////////////////////////////////
2037
////                                                              ////
2038
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2039
////                                                              ////
2040
//// This source file may be used and distributed without         ////
2041
//// restriction provided that this copyright statement is not    ////
2042
//// removed from the file and that any derivative work contains  ////
2043
//// the original copyright notice and the associated disclaimer. ////
2044
////                                                              ////
2045
//// This source file is free software; you can redistribute it   ////
2046
//// and/or modify it under the terms of the GNU Lesser General   ////
2047
//// Public License as published by the Free Software Foundation; ////
2048
//// either version 2.1 of the License, or (at your option) any   ////
2049
//// later version.                                               ////
2050
////                                                              ////
2051
//// This source is distributed in the hope that it will be       ////
2052
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2053
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2054
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2055
//// details.                                                     ////
2056
////                                                              ////
2057
//// You should have received a copy of the GNU Lesser General    ////
2058
//// Public License along with this source; if not, download it   ////
2059
//// from http://www.opencores.org/lgpl.shtml                     ////
2060
////                                                              ////
2061
//////////////////////////////////////////////////////////////////////
2062
 
2063 25 unneback
// binary counter
2064
 
2065 40 unneback
`define MODULE cnt_bin_ce_rew_zq_l1
2066
module `BASE`MODULE (
2067
`undef MODULE
2068
 cke, rew, zq, level1, rst, clk);
2069
 
2070 25 unneback
   parameter length = 4;
2071
   input cke;
2072
   input rew;
2073
   output reg zq;
2074
   output reg level1;
2075
   input rst;
2076
   input clk;
2077
 
2078
   parameter clear_value = 0;
2079
   parameter set_value = 1;
2080
   parameter wrap_value = 1;
2081
   parameter level1_value = 15;
2082
 
2083 29 unneback
   wire clear;
2084 30 unneback
   assign clear = 1'b0;
2085 25 unneback
   reg  [length:1] qi;
2086
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2087
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2088
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2089
   assign q_next = rew ? q_next_rew : q_next_fw;
2090
 
2091
   always @ (posedge clk or posedge rst)
2092
     if (rst)
2093
       qi <= {length{1'b0}};
2094
     else
2095
     if (cke)
2096
       qi <= q_next;
2097
 
2098
 
2099
 
2100
   always @ (posedge clk or posedge rst)
2101
     if (rst)
2102
       zq <= 1'b1;
2103
     else
2104
     if (cke)
2105
       zq <= q_next == {length{1'b0}};
2106
 
2107
    always @ (posedge clk or posedge rst)
2108
    if (rst)
2109
        level1 <= 1'b0;
2110
    else
2111
    if (cke)
2112 29 unneback
    if (clear)
2113
        level1 <= 1'b0;
2114
    else if (q_next == level1_value)
2115 25 unneback
        level1 <= 1'b1;
2116
    else if (qi == level1_value & rew)
2117
        level1 <= 1'b0;
2118
endmodule
2119 40 unneback
`endif
2120
`ifdef CNT_BIN_CE_REW_Q_ZQ_L1
2121 25 unneback
//////////////////////////////////////////////////////////////////////
2122
////                                                              ////
2123
////  Versatile counter                                           ////
2124
////                                                              ////
2125
////  Description                                                 ////
2126
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2127
////  counter                                                     ////
2128
////                                                              ////
2129
////  To Do:                                                      ////
2130
////   - add LFSR with more taps                                  ////
2131
////                                                              ////
2132
////  Author(s):                                                  ////
2133
////      - Michael Unneback, unneback@opencores.org              ////
2134
////        ORSoC AB                                              ////
2135
////                                                              ////
2136
//////////////////////////////////////////////////////////////////////
2137
////                                                              ////
2138
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2139
////                                                              ////
2140
//// This source file may be used and distributed without         ////
2141
//// restriction provided that this copyright statement is not    ////
2142
//// removed from the file and that any derivative work contains  ////
2143
//// the original copyright notice and the associated disclaimer. ////
2144
////                                                              ////
2145
//// This source file is free software; you can redistribute it   ////
2146
//// and/or modify it under the terms of the GNU Lesser General   ////
2147
//// Public License as published by the Free Software Foundation; ////
2148
//// either version 2.1 of the License, or (at your option) any   ////
2149
//// later version.                                               ////
2150
////                                                              ////
2151
//// This source is distributed in the hope that it will be       ////
2152
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2153
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2154
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2155
//// details.                                                     ////
2156
////                                                              ////
2157
//// You should have received a copy of the GNU Lesser General    ////
2158
//// Public License along with this source; if not, download it   ////
2159
//// from http://www.opencores.org/lgpl.shtml                     ////
2160
////                                                              ////
2161
//////////////////////////////////////////////////////////////////////
2162
 
2163
// binary counter
2164
 
2165 40 unneback
`define MODULE cnt_bin_ce_rew_q_zq_l1
2166
module `BASE`MODULE (
2167
`undef MODULE
2168
 cke, rew, q, zq, level1, rst, clk);
2169
 
2170 25 unneback
   parameter length = 4;
2171
   input cke;
2172
   input rew;
2173
   output [length:1] q;
2174
   output reg zq;
2175
   output reg level1;
2176
   input rst;
2177
   input clk;
2178
 
2179
   parameter clear_value = 0;
2180
   parameter set_value = 1;
2181
   parameter wrap_value = 1;
2182
   parameter level1_value = 15;
2183
 
2184 29 unneback
   wire clear;
2185 30 unneback
   assign clear = 1'b0;
2186 25 unneback
   reg  [length:1] qi;
2187
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2188
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2189
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2190
   assign q_next = rew ? q_next_rew : q_next_fw;
2191
 
2192
   always @ (posedge clk or posedge rst)
2193
     if (rst)
2194
       qi <= {length{1'b0}};
2195
     else
2196
     if (cke)
2197
       qi <= q_next;
2198
 
2199
   assign q = qi;
2200
 
2201
 
2202
   always @ (posedge clk or posedge rst)
2203
     if (rst)
2204
       zq <= 1'b1;
2205
     else
2206
     if (cke)
2207
       zq <= q_next == {length{1'b0}};
2208
 
2209
    always @ (posedge clk or posedge rst)
2210
    if (rst)
2211
        level1 <= 1'b0;
2212
    else
2213
    if (cke)
2214 29 unneback
    if (clear)
2215
        level1 <= 1'b0;
2216
    else if (q_next == level1_value)
2217 25 unneback
        level1 <= 1'b1;
2218
    else if (qi == level1_value & rew)
2219
        level1 <= 1'b0;
2220
endmodule
2221 40 unneback
`endif
2222
`ifdef CNT_LFSR_ZQ
2223 25 unneback
//////////////////////////////////////////////////////////////////////
2224
////                                                              ////
2225
////  Versatile counter                                           ////
2226
////                                                              ////
2227
////  Description                                                 ////
2228
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2229
////  counter                                                     ////
2230
////                                                              ////
2231
////  To Do:                                                      ////
2232
////   - add LFSR with more taps                                  ////
2233
////                                                              ////
2234
////  Author(s):                                                  ////
2235
////      - Michael Unneback, unneback@opencores.org              ////
2236
////        ORSoC AB                                              ////
2237
////                                                              ////
2238
//////////////////////////////////////////////////////////////////////
2239
////                                                              ////
2240
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2241
////                                                              ////
2242
//// This source file may be used and distributed without         ////
2243
//// restriction provided that this copyright statement is not    ////
2244
//// removed from the file and that any derivative work contains  ////
2245
//// the original copyright notice and the associated disclaimer. ////
2246
////                                                              ////
2247
//// This source file is free software; you can redistribute it   ////
2248
//// and/or modify it under the terms of the GNU Lesser General   ////
2249
//// Public License as published by the Free Software Foundation; ////
2250
//// either version 2.1 of the License, or (at your option) any   ////
2251
//// later version.                                               ////
2252
////                                                              ////
2253
//// This source is distributed in the hope that it will be       ////
2254
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2255
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2256
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2257
//// details.                                                     ////
2258
////                                                              ////
2259
//// You should have received a copy of the GNU Lesser General    ////
2260
//// Public License along with this source; if not, download it   ////
2261
//// from http://www.opencores.org/lgpl.shtml                     ////
2262
////                                                              ////
2263
//////////////////////////////////////////////////////////////////////
2264
 
2265 6 unneback
// LFSR counter
2266
 
2267 40 unneback
`define MODULE cnt_lfsr_zq
2268
module `BASE`MODULE (
2269
`undef MODULE
2270
 zq, rst, clk);
2271
 
2272 6 unneback
   parameter length = 4;
2273
   output reg zq;
2274
   input rst;
2275
   input clk;
2276
 
2277
   parameter clear_value = 0;
2278
   parameter set_value = 1;
2279
   parameter wrap_value = 8;
2280
   parameter level1_value = 15;
2281
 
2282
   reg  [length:1] qi;
2283
   reg lfsr_fb;
2284
   wire [length:1] q_next;
2285
   reg [32:1] polynom;
2286
   integer i;
2287
 
2288
   always @ (qi)
2289
   begin
2290
        case (length)
2291
         2: polynom = 32'b11;                               // 0x3
2292
         3: polynom = 32'b110;                              // 0x6
2293
         4: polynom = 32'b1100;                             // 0xC
2294
         5: polynom = 32'b10100;                            // 0x14
2295
         6: polynom = 32'b110000;                           // 0x30
2296
         7: polynom = 32'b1100000;                          // 0x60
2297
         8: polynom = 32'b10111000;                         // 0xb8
2298
         9: polynom = 32'b100010000;                        // 0x110
2299
        10: polynom = 32'b1001000000;                       // 0x240
2300
        11: polynom = 32'b10100000000;                      // 0x500
2301
        12: polynom = 32'b100000101001;                     // 0x829
2302
        13: polynom = 32'b1000000001100;                    // 0x100C
2303
        14: polynom = 32'b10000000010101;                   // 0x2015
2304
        15: polynom = 32'b110000000000000;                  // 0x6000
2305
        16: polynom = 32'b1101000000001000;                 // 0xD008
2306
        17: polynom = 32'b10010000000000000;                // 0x12000
2307
        18: polynom = 32'b100000010000000000;               // 0x20400
2308
        19: polynom = 32'b1000000000000100011;              // 0x40023
2309 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2310 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2311
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2312
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2313
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2314
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2315
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2316
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2317
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2318
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2319
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2320
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2321
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2322
        default: polynom = 32'b0;
2323
        endcase
2324
        lfsr_fb = qi[length];
2325
        for (i=length-1; i>=1; i=i-1) begin
2326
            if (polynom[i])
2327
                lfsr_fb = lfsr_fb  ~^ qi[i];
2328
        end
2329
    end
2330
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2331
 
2332
   always @ (posedge clk or posedge rst)
2333
     if (rst)
2334
       qi <= {length{1'b0}};
2335
     else
2336
       qi <= q_next;
2337
 
2338
 
2339
 
2340
   always @ (posedge clk or posedge rst)
2341
     if (rst)
2342
       zq <= 1'b1;
2343
     else
2344
       zq <= q_next == {length{1'b0}};
2345
endmodule
2346 40 unneback
`endif
2347
`ifdef CNT_LFSR_CE_ZQ
2348 6 unneback
//////////////////////////////////////////////////////////////////////
2349
////                                                              ////
2350
////  Versatile counter                                           ////
2351
////                                                              ////
2352
////  Description                                                 ////
2353
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2354
////  counter                                                     ////
2355
////                                                              ////
2356
////  To Do:                                                      ////
2357
////   - add LFSR with more taps                                  ////
2358
////                                                              ////
2359
////  Author(s):                                                  ////
2360
////      - Michael Unneback, unneback@opencores.org              ////
2361
////        ORSoC AB                                              ////
2362
////                                                              ////
2363
//////////////////////////////////////////////////////////////////////
2364
////                                                              ////
2365
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2366
////                                                              ////
2367
//// This source file may be used and distributed without         ////
2368
//// restriction provided that this copyright statement is not    ////
2369
//// removed from the file and that any derivative work contains  ////
2370
//// the original copyright notice and the associated disclaimer. ////
2371
////                                                              ////
2372
//// This source file is free software; you can redistribute it   ////
2373
//// and/or modify it under the terms of the GNU Lesser General   ////
2374
//// Public License as published by the Free Software Foundation; ////
2375
//// either version 2.1 of the License, or (at your option) any   ////
2376
//// later version.                                               ////
2377
////                                                              ////
2378
//// This source is distributed in the hope that it will be       ////
2379
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2380
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2381
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2382
//// details.                                                     ////
2383
////                                                              ////
2384
//// You should have received a copy of the GNU Lesser General    ////
2385
//// Public License along with this source; if not, download it   ////
2386
//// from http://www.opencores.org/lgpl.shtml                     ////
2387
////                                                              ////
2388
//////////////////////////////////////////////////////////////////////
2389
 
2390
// LFSR counter
2391
 
2392 40 unneback
`define MODULE cnt_lfsr_ce_zq
2393
module `BASE`MODULE (
2394
`undef MODULE
2395
 cke, zq, rst, clk);
2396
 
2397 6 unneback
   parameter length = 4;
2398
   input cke;
2399
   output reg zq;
2400
   input rst;
2401
   input clk;
2402
 
2403
   parameter clear_value = 0;
2404
   parameter set_value = 1;
2405
   parameter wrap_value = 8;
2406
   parameter level1_value = 15;
2407
 
2408
   reg  [length:1] qi;
2409
   reg lfsr_fb;
2410
   wire [length:1] q_next;
2411
   reg [32:1] polynom;
2412
   integer i;
2413
 
2414
   always @ (qi)
2415
   begin
2416
        case (length)
2417
         2: polynom = 32'b11;                               // 0x3
2418
         3: polynom = 32'b110;                              // 0x6
2419
         4: polynom = 32'b1100;                             // 0xC
2420
         5: polynom = 32'b10100;                            // 0x14
2421
         6: polynom = 32'b110000;                           // 0x30
2422
         7: polynom = 32'b1100000;                          // 0x60
2423
         8: polynom = 32'b10111000;                         // 0xb8
2424
         9: polynom = 32'b100010000;                        // 0x110
2425
        10: polynom = 32'b1001000000;                       // 0x240
2426
        11: polynom = 32'b10100000000;                      // 0x500
2427
        12: polynom = 32'b100000101001;                     // 0x829
2428
        13: polynom = 32'b1000000001100;                    // 0x100C
2429
        14: polynom = 32'b10000000010101;                   // 0x2015
2430
        15: polynom = 32'b110000000000000;                  // 0x6000
2431
        16: polynom = 32'b1101000000001000;                 // 0xD008
2432
        17: polynom = 32'b10010000000000000;                // 0x12000
2433
        18: polynom = 32'b100000010000000000;               // 0x20400
2434
        19: polynom = 32'b1000000000000100011;              // 0x40023
2435 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2436 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2437
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2438
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2439
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2440
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2441
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2442
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2443
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2444
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2445
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2446
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2447
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2448
        default: polynom = 32'b0;
2449
        endcase
2450
        lfsr_fb = qi[length];
2451
        for (i=length-1; i>=1; i=i-1) begin
2452
            if (polynom[i])
2453
                lfsr_fb = lfsr_fb  ~^ qi[i];
2454
        end
2455
    end
2456
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2457
 
2458
   always @ (posedge clk or posedge rst)
2459
     if (rst)
2460
       qi <= {length{1'b0}};
2461
     else
2462
     if (cke)
2463
       qi <= q_next;
2464
 
2465
 
2466
 
2467
   always @ (posedge clk or posedge rst)
2468
     if (rst)
2469
       zq <= 1'b1;
2470
     else
2471
     if (cke)
2472
       zq <= q_next == {length{1'b0}};
2473
endmodule
2474 40 unneback
`endif
2475
`ifdef CNT_LFSR_CE_Q
2476 6 unneback
//////////////////////////////////////////////////////////////////////
2477
////                                                              ////
2478
////  Versatile counter                                           ////
2479
////                                                              ////
2480
////  Description                                                 ////
2481
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2482
////  counter                                                     ////
2483
////                                                              ////
2484
////  To Do:                                                      ////
2485
////   - add LFSR with more taps                                  ////
2486
////                                                              ////
2487
////  Author(s):                                                  ////
2488
////      - Michael Unneback, unneback@opencores.org              ////
2489
////        ORSoC AB                                              ////
2490
////                                                              ////
2491
//////////////////////////////////////////////////////////////////////
2492
////                                                              ////
2493
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2494
////                                                              ////
2495
//// This source file may be used and distributed without         ////
2496
//// restriction provided that this copyright statement is not    ////
2497
//// removed from the file and that any derivative work contains  ////
2498
//// the original copyright notice and the associated disclaimer. ////
2499
////                                                              ////
2500
//// This source file is free software; you can redistribute it   ////
2501
//// and/or modify it under the terms of the GNU Lesser General   ////
2502
//// Public License as published by the Free Software Foundation; ////
2503
//// either version 2.1 of the License, or (at your option) any   ////
2504
//// later version.                                               ////
2505
////                                                              ////
2506
//// This source is distributed in the hope that it will be       ////
2507
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2508
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2509
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2510
//// details.                                                     ////
2511
////                                                              ////
2512
//// You should have received a copy of the GNU Lesser General    ////
2513
//// Public License along with this source; if not, download it   ////
2514
//// from http://www.opencores.org/lgpl.shtml                     ////
2515
////                                                              ////
2516
//////////////////////////////////////////////////////////////////////
2517 22 unneback
 
2518
// LFSR counter
2519 27 unneback
 
2520 40 unneback
`define MODULE cnt_lfsr_ce_q
2521
module `BASE`MODULE (
2522
`undef MODULE
2523
 cke, q, rst, clk);
2524
 
2525 27 unneback
   parameter length = 4;
2526
   input cke;
2527
   output [length:1] q;
2528
   input rst;
2529
   input clk;
2530
 
2531
   parameter clear_value = 0;
2532
   parameter set_value = 1;
2533
   parameter wrap_value = 8;
2534
   parameter level1_value = 15;
2535
 
2536
   reg  [length:1] qi;
2537
   reg lfsr_fb;
2538
   wire [length:1] q_next;
2539
   reg [32:1] polynom;
2540
   integer i;
2541
 
2542
   always @ (qi)
2543
   begin
2544
        case (length)
2545
         2: polynom = 32'b11;                               // 0x3
2546
         3: polynom = 32'b110;                              // 0x6
2547
         4: polynom = 32'b1100;                             // 0xC
2548
         5: polynom = 32'b10100;                            // 0x14
2549
         6: polynom = 32'b110000;                           // 0x30
2550
         7: polynom = 32'b1100000;                          // 0x60
2551
         8: polynom = 32'b10111000;                         // 0xb8
2552
         9: polynom = 32'b100010000;                        // 0x110
2553
        10: polynom = 32'b1001000000;                       // 0x240
2554
        11: polynom = 32'b10100000000;                      // 0x500
2555
        12: polynom = 32'b100000101001;                     // 0x829
2556
        13: polynom = 32'b1000000001100;                    // 0x100C
2557
        14: polynom = 32'b10000000010101;                   // 0x2015
2558
        15: polynom = 32'b110000000000000;                  // 0x6000
2559
        16: polynom = 32'b1101000000001000;                 // 0xD008
2560
        17: polynom = 32'b10010000000000000;                // 0x12000
2561
        18: polynom = 32'b100000010000000000;               // 0x20400
2562
        19: polynom = 32'b1000000000000100011;              // 0x40023
2563 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2564 27 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2565
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2566
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2567
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2568
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2569
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2570
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2571
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2572
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2573
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2574
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2575
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2576
        default: polynom = 32'b0;
2577
        endcase
2578
        lfsr_fb = qi[length];
2579
        for (i=length-1; i>=1; i=i-1) begin
2580
            if (polynom[i])
2581
                lfsr_fb = lfsr_fb  ~^ qi[i];
2582
        end
2583
    end
2584
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2585
 
2586
   always @ (posedge clk or posedge rst)
2587
     if (rst)
2588
       qi <= {length{1'b0}};
2589
     else
2590
     if (cke)
2591
       qi <= q_next;
2592
 
2593
   assign q = qi;
2594
 
2595
endmodule
2596 40 unneback
`endif
2597
`ifdef CNT_LFSR_CE_CLEAR_Q
2598 27 unneback
//////////////////////////////////////////////////////////////////////
2599
////                                                              ////
2600
////  Versatile counter                                           ////
2601
////                                                              ////
2602
////  Description                                                 ////
2603
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2604
////  counter                                                     ////
2605
////                                                              ////
2606
////  To Do:                                                      ////
2607
////   - add LFSR with more taps                                  ////
2608
////                                                              ////
2609
////  Author(s):                                                  ////
2610
////      - Michael Unneback, unneback@opencores.org              ////
2611
////        ORSoC AB                                              ////
2612
////                                                              ////
2613
//////////////////////////////////////////////////////////////////////
2614
////                                                              ////
2615
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2616
////                                                              ////
2617
//// This source file may be used and distributed without         ////
2618
//// restriction provided that this copyright statement is not    ////
2619
//// removed from the file and that any derivative work contains  ////
2620
//// the original copyright notice and the associated disclaimer. ////
2621
////                                                              ////
2622
//// This source file is free software; you can redistribute it   ////
2623
//// and/or modify it under the terms of the GNU Lesser General   ////
2624
//// Public License as published by the Free Software Foundation; ////
2625
//// either version 2.1 of the License, or (at your option) any   ////
2626
//// later version.                                               ////
2627
////                                                              ////
2628
//// This source is distributed in the hope that it will be       ////
2629
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2630
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2631
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2632
//// details.                                                     ////
2633
////                                                              ////
2634
//// You should have received a copy of the GNU Lesser General    ////
2635
//// Public License along with this source; if not, download it   ////
2636
//// from http://www.opencores.org/lgpl.shtml                     ////
2637
////                                                              ////
2638
//////////////////////////////////////////////////////////////////////
2639
 
2640
// LFSR counter
2641
 
2642 40 unneback
`define MODULE cnt_lfsr_ce_clear_q
2643
module `BASE`MODULE (
2644
`undef MODULE
2645
 clear, cke, q, rst, clk);
2646
 
2647 27 unneback
   parameter length = 4;
2648
   input clear;
2649
   input cke;
2650
   output [length:1] q;
2651
   input rst;
2652
   input clk;
2653
 
2654
   parameter clear_value = 0;
2655
   parameter set_value = 1;
2656
   parameter wrap_value = 8;
2657
   parameter level1_value = 15;
2658
 
2659
   reg  [length:1] qi;
2660
   reg lfsr_fb;
2661
   wire [length:1] q_next;
2662
   reg [32:1] polynom;
2663
   integer i;
2664
 
2665
   always @ (qi)
2666
   begin
2667
        case (length)
2668
         2: polynom = 32'b11;                               // 0x3
2669
         3: polynom = 32'b110;                              // 0x6
2670
         4: polynom = 32'b1100;                             // 0xC
2671
         5: polynom = 32'b10100;                            // 0x14
2672
         6: polynom = 32'b110000;                           // 0x30
2673
         7: polynom = 32'b1100000;                          // 0x60
2674
         8: polynom = 32'b10111000;                         // 0xb8
2675
         9: polynom = 32'b100010000;                        // 0x110
2676
        10: polynom = 32'b1001000000;                       // 0x240
2677
        11: polynom = 32'b10100000000;                      // 0x500
2678
        12: polynom = 32'b100000101001;                     // 0x829
2679
        13: polynom = 32'b1000000001100;                    // 0x100C
2680
        14: polynom = 32'b10000000010101;                   // 0x2015
2681
        15: polynom = 32'b110000000000000;                  // 0x6000
2682
        16: polynom = 32'b1101000000001000;                 // 0xD008
2683
        17: polynom = 32'b10010000000000000;                // 0x12000
2684
        18: polynom = 32'b100000010000000000;               // 0x20400
2685
        19: polynom = 32'b1000000000000100011;              // 0x40023
2686 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2687 27 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2688
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2689
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2690
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2691
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2692
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2693
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2694
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2695
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2696
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2697
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2698
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2699
        default: polynom = 32'b0;
2700
        endcase
2701
        lfsr_fb = qi[length];
2702
        for (i=length-1; i>=1; i=i-1) begin
2703
            if (polynom[i])
2704
                lfsr_fb = lfsr_fb  ~^ qi[i];
2705
        end
2706
    end
2707
   assign q_next =  clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2708
 
2709
   always @ (posedge clk or posedge rst)
2710
     if (rst)
2711
       qi <= {length{1'b0}};
2712
     else
2713
     if (cke)
2714
       qi <= q_next;
2715
 
2716
   assign q = qi;
2717
 
2718
endmodule
2719 40 unneback
`endif
2720
`ifdef CNT_LFSR_CE_Q_ZQ
2721 27 unneback
//////////////////////////////////////////////////////////////////////
2722
////                                                              ////
2723
////  Versatile counter                                           ////
2724
////                                                              ////
2725
////  Description                                                 ////
2726
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2727
////  counter                                                     ////
2728
////                                                              ////
2729
////  To Do:                                                      ////
2730
////   - add LFSR with more taps                                  ////
2731
////                                                              ////
2732
////  Author(s):                                                  ////
2733
////      - Michael Unneback, unneback@opencores.org              ////
2734
////        ORSoC AB                                              ////
2735
////                                                              ////
2736
//////////////////////////////////////////////////////////////////////
2737
////                                                              ////
2738
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2739
////                                                              ////
2740
//// This source file may be used and distributed without         ////
2741
//// restriction provided that this copyright statement is not    ////
2742
//// removed from the file and that any derivative work contains  ////
2743
//// the original copyright notice and the associated disclaimer. ////
2744
////                                                              ////
2745
//// This source file is free software; you can redistribute it   ////
2746
//// and/or modify it under the terms of the GNU Lesser General   ////
2747
//// Public License as published by the Free Software Foundation; ////
2748
//// either version 2.1 of the License, or (at your option) any   ////
2749
//// later version.                                               ////
2750
////                                                              ////
2751
//// This source is distributed in the hope that it will be       ////
2752
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2753
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2754
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2755
//// details.                                                     ////
2756
////                                                              ////
2757
//// You should have received a copy of the GNU Lesser General    ////
2758
//// Public License along with this source; if not, download it   ////
2759
//// from http://www.opencores.org/lgpl.shtml                     ////
2760
////                                                              ////
2761
//////////////////////////////////////////////////////////////////////
2762
 
2763
// LFSR counter
2764 22 unneback
 
2765 40 unneback
`define MODULE cnt_lfsr_ce_q_zq
2766
module `BASE`MODULE (
2767
`undef MODULE
2768
 cke, q, zq, rst, clk);
2769
 
2770 22 unneback
   parameter length = 4;
2771
   input cke;
2772
   output [length:1] q;
2773
   output reg zq;
2774
   input rst;
2775
   input clk;
2776
 
2777
   parameter clear_value = 0;
2778
   parameter set_value = 1;
2779
   parameter wrap_value = 8;
2780
   parameter level1_value = 15;
2781
 
2782
   reg  [length:1] qi;
2783
   reg lfsr_fb;
2784
   wire [length:1] q_next;
2785
   reg [32:1] polynom;
2786
   integer i;
2787
 
2788
   always @ (qi)
2789
   begin
2790
        case (length)
2791
         2: polynom = 32'b11;                               // 0x3
2792
         3: polynom = 32'b110;                              // 0x6
2793
         4: polynom = 32'b1100;                             // 0xC
2794
         5: polynom = 32'b10100;                            // 0x14
2795
         6: polynom = 32'b110000;                           // 0x30
2796
         7: polynom = 32'b1100000;                          // 0x60
2797
         8: polynom = 32'b10111000;                         // 0xb8
2798
         9: polynom = 32'b100010000;                        // 0x110
2799
        10: polynom = 32'b1001000000;                       // 0x240
2800
        11: polynom = 32'b10100000000;                      // 0x500
2801
        12: polynom = 32'b100000101001;                     // 0x829
2802
        13: polynom = 32'b1000000001100;                    // 0x100C
2803
        14: polynom = 32'b10000000010101;                   // 0x2015
2804
        15: polynom = 32'b110000000000000;                  // 0x6000
2805
        16: polynom = 32'b1101000000001000;                 // 0xD008
2806
        17: polynom = 32'b10010000000000000;                // 0x12000
2807
        18: polynom = 32'b100000010000000000;               // 0x20400
2808
        19: polynom = 32'b1000000000000100011;              // 0x40023
2809 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2810 22 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2811
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2812
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2813
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2814
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2815
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2816
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2817
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2818
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2819
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2820
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2821
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2822
        default: polynom = 32'b0;
2823
        endcase
2824
        lfsr_fb = qi[length];
2825
        for (i=length-1; i>=1; i=i-1) begin
2826
            if (polynom[i])
2827
                lfsr_fb = lfsr_fb  ~^ qi[i];
2828
        end
2829
    end
2830
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2831
 
2832
   always @ (posedge clk or posedge rst)
2833
     if (rst)
2834
       qi <= {length{1'b0}};
2835
     else
2836
     if (cke)
2837
       qi <= q_next;
2838
 
2839
   assign q = qi;
2840
 
2841
 
2842
   always @ (posedge clk or posedge rst)
2843
     if (rst)
2844
       zq <= 1'b1;
2845
     else
2846
     if (cke)
2847
       zq <= q_next == {length{1'b0}};
2848
endmodule
2849 40 unneback
`endif
2850
`ifdef CNT_LFSR_CE_REW_L1
2851 22 unneback
//////////////////////////////////////////////////////////////////////
2852
////                                                              ////
2853
////  Versatile counter                                           ////
2854
////                                                              ////
2855
////  Description                                                 ////
2856
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2857
////  counter                                                     ////
2858
////                                                              ////
2859
////  To Do:                                                      ////
2860
////   - add LFSR with more taps                                  ////
2861
////                                                              ////
2862
////  Author(s):                                                  ////
2863
////      - Michael Unneback, unneback@opencores.org              ////
2864
////        ORSoC AB                                              ////
2865
////                                                              ////
2866
//////////////////////////////////////////////////////////////////////
2867
////                                                              ////
2868
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2869
////                                                              ////
2870
//// This source file may be used and distributed without         ////
2871
//// restriction provided that this copyright statement is not    ////
2872
//// removed from the file and that any derivative work contains  ////
2873
//// the original copyright notice and the associated disclaimer. ////
2874
////                                                              ////
2875
//// This source file is free software; you can redistribute it   ////
2876
//// and/or modify it under the terms of the GNU Lesser General   ////
2877
//// Public License as published by the Free Software Foundation; ////
2878
//// either version 2.1 of the License, or (at your option) any   ////
2879
//// later version.                                               ////
2880
////                                                              ////
2881
//// This source is distributed in the hope that it will be       ////
2882
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2883
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2884
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2885
//// details.                                                     ////
2886
////                                                              ////
2887
//// You should have received a copy of the GNU Lesser General    ////
2888
//// Public License along with this source; if not, download it   ////
2889
//// from http://www.opencores.org/lgpl.shtml                     ////
2890
////                                                              ////
2891
//////////////////////////////////////////////////////////////////////
2892 6 unneback
 
2893
// LFSR counter
2894
 
2895 40 unneback
`define MODULE cnt_lfsr_ce_rew_l1
2896
module `BASE`MODULE (
2897
`undef MODULE
2898
 cke, rew, level1, rst, clk);
2899
 
2900 6 unneback
   parameter length = 4;
2901
   input cke;
2902
   input rew;
2903
   output reg level1;
2904
   input rst;
2905
   input clk;
2906
 
2907
   parameter clear_value = 0;
2908
   parameter set_value = 1;
2909
   parameter wrap_value = 8;
2910
   parameter level1_value = 15;
2911
 
2912 29 unneback
   wire clear;
2913 30 unneback
   assign clear = 1'b0;
2914 6 unneback
   reg  [length:1] qi;
2915
   reg lfsr_fb, lfsr_fb_rew;
2916
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2917
   reg [32:1] polynom_rew;
2918
   integer j;
2919
   reg [32:1] polynom;
2920
   integer i;
2921
 
2922
   always @ (qi)
2923
   begin
2924
        case (length)
2925
         2: polynom = 32'b11;                               // 0x3
2926
         3: polynom = 32'b110;                              // 0x6
2927
         4: polynom = 32'b1100;                             // 0xC
2928
         5: polynom = 32'b10100;                            // 0x14
2929
         6: polynom = 32'b110000;                           // 0x30
2930
         7: polynom = 32'b1100000;                          // 0x60
2931
         8: polynom = 32'b10111000;                         // 0xb8
2932
         9: polynom = 32'b100010000;                        // 0x110
2933
        10: polynom = 32'b1001000000;                       // 0x240
2934
        11: polynom = 32'b10100000000;                      // 0x500
2935
        12: polynom = 32'b100000101001;                     // 0x829
2936
        13: polynom = 32'b1000000001100;                    // 0x100C
2937
        14: polynom = 32'b10000000010101;                   // 0x2015
2938
        15: polynom = 32'b110000000000000;                  // 0x6000
2939
        16: polynom = 32'b1101000000001000;                 // 0xD008
2940
        17: polynom = 32'b10010000000000000;                // 0x12000
2941
        18: polynom = 32'b100000010000000000;               // 0x20400
2942
        19: polynom = 32'b1000000000000100011;              // 0x40023
2943 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2944 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2945
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2946
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2947
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2948
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2949
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2950
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2951
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2952
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2953
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2954
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2955
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2956
        default: polynom = 32'b0;
2957
        endcase
2958
        lfsr_fb = qi[length];
2959
        for (i=length-1; i>=1; i=i-1) begin
2960
            if (polynom[i])
2961
                lfsr_fb = lfsr_fb  ~^ qi[i];
2962
        end
2963
    end
2964
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2965
   always @ (qi)
2966
   begin
2967
        case (length)
2968
         2: polynom_rew = 32'b11;
2969
         3: polynom_rew = 32'b110;
2970
         4: polynom_rew = 32'b1100;
2971
         5: polynom_rew = 32'b10100;
2972
         6: polynom_rew = 32'b110000;
2973
         7: polynom_rew = 32'b1100000;
2974
         8: polynom_rew = 32'b10111000;
2975
         9: polynom_rew = 32'b100010000;
2976
        10: polynom_rew = 32'b1001000000;
2977
        11: polynom_rew = 32'b10100000000;
2978
        12: polynom_rew = 32'b100000101001;
2979
        13: polynom_rew = 32'b1000000001100;
2980
        14: polynom_rew = 32'b10000000010101;
2981
        15: polynom_rew = 32'b110000000000000;
2982
        16: polynom_rew = 32'b1101000000001000;
2983
        17: polynom_rew = 32'b10010000000000000;
2984
        18: polynom_rew = 32'b100000010000000000;
2985
        19: polynom_rew = 32'b1000000000000100011;
2986
        20: polynom_rew = 32'b10000010000000000000;
2987
        21: polynom_rew = 32'b101000000000000000000;
2988
        22: polynom_rew = 32'b1100000000000000000000;
2989
        23: polynom_rew = 32'b10000100000000000000000;
2990
        24: polynom_rew = 32'b111000010000000000000000;
2991
        25: polynom_rew = 32'b1001000000000000000000000;
2992
        26: polynom_rew = 32'b10000000000000000000100011;
2993
        27: polynom_rew = 32'b100000000000000000000010011;
2994
        28: polynom_rew = 32'b1100100000000000000000000000;
2995
        29: polynom_rew = 32'b10100000000000000000000000000;
2996
        30: polynom_rew = 32'b100000000000000000000000101001;
2997
        31: polynom_rew = 32'b1001000000000000000000000000000;
2998
        32: polynom_rew = 32'b10000000001000000000000000000011;
2999
        default: polynom_rew = 32'b0;
3000
        endcase
3001
        // rotate left
3002
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
3003
        lfsr_fb_rew = qi[length];
3004
        for (i=length-1; i>=1; i=i-1) begin
3005
            if (polynom_rew[i])
3006
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
3007
        end
3008
    end
3009
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
3010
   assign q_next = rew ? q_next_rew : q_next_fw;
3011
 
3012
   always @ (posedge clk or posedge rst)
3013
     if (rst)
3014
       qi <= {length{1'b0}};
3015
     else
3016
     if (cke)
3017
       qi <= q_next;
3018
 
3019
 
3020
 
3021
    always @ (posedge clk or posedge rst)
3022
    if (rst)
3023
        level1 <= 1'b0;
3024
    else
3025
    if (cke)
3026 29 unneback
    if (clear)
3027
        level1 <= 1'b0;
3028
    else if (q_next == level1_value)
3029 6 unneback
        level1 <= 1'b1;
3030
    else if (qi == level1_value & rew)
3031
        level1 <= 1'b0;
3032
endmodule
3033 40 unneback
`endif
3034
`ifdef CNT_GRAY
3035 6 unneback
//////////////////////////////////////////////////////////////////////
3036
////                                                              ////
3037
////  Versatile counter                                           ////
3038
////                                                              ////
3039
////  Description                                                 ////
3040
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3041
////  counter                                                     ////
3042
////                                                              ////
3043
////  To Do:                                                      ////
3044
////   - add LFSR with more taps                                  ////
3045
////                                                              ////
3046
////  Author(s):                                                  ////
3047
////      - Michael Unneback, unneback@opencores.org              ////
3048
////        ORSoC AB                                              ////
3049
////                                                              ////
3050
//////////////////////////////////////////////////////////////////////
3051
////                                                              ////
3052
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3053
////                                                              ////
3054
//// This source file may be used and distributed without         ////
3055
//// restriction provided that this copyright statement is not    ////
3056
//// removed from the file and that any derivative work contains  ////
3057
//// the original copyright notice and the associated disclaimer. ////
3058
////                                                              ////
3059
//// This source file is free software; you can redistribute it   ////
3060
//// and/or modify it under the terms of the GNU Lesser General   ////
3061
//// Public License as published by the Free Software Foundation; ////
3062
//// either version 2.1 of the License, or (at your option) any   ////
3063
//// later version.                                               ////
3064
////                                                              ////
3065
//// This source is distributed in the hope that it will be       ////
3066
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3067
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3068
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3069
//// details.                                                     ////
3070
////                                                              ////
3071
//// You should have received a copy of the GNU Lesser General    ////
3072
//// Public License along with this source; if not, download it   ////
3073
//// from http://www.opencores.org/lgpl.shtml                     ////
3074
////                                                              ////
3075
//////////////////////////////////////////////////////////////////////
3076
 
3077
// GRAY counter
3078
 
3079 40 unneback
`define MODULE cnt_gray
3080
module `BASE`MODULE (
3081
`undef MODULE
3082
 q, rst, clk);
3083
 
3084 6 unneback
   parameter length = 4;
3085
   output reg [length:1] q;
3086
   input rst;
3087
   input clk;
3088
 
3089
   parameter clear_value = 0;
3090
   parameter set_value = 1;
3091
   parameter wrap_value = 8;
3092
   parameter level1_value = 15;
3093
 
3094
   reg  [length:1] qi;
3095
   wire [length:1] q_next;
3096
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3097
 
3098
   always @ (posedge clk or posedge rst)
3099
     if (rst)
3100
       qi <= {length{1'b0}};
3101
     else
3102
       qi <= q_next;
3103
 
3104
   always @ (posedge clk or posedge rst)
3105
     if (rst)
3106
       q <= {length{1'b0}};
3107
     else
3108
         q <= (q_next>>1) ^ q_next;
3109
 
3110
endmodule
3111 40 unneback
`endif
3112
`ifdef CNT_GRAY_CE
3113 6 unneback
//////////////////////////////////////////////////////////////////////
3114
////                                                              ////
3115
////  Versatile counter                                           ////
3116
////                                                              ////
3117
////  Description                                                 ////
3118
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3119
////  counter                                                     ////
3120
////                                                              ////
3121
////  To Do:                                                      ////
3122
////   - add LFSR with more taps                                  ////
3123
////                                                              ////
3124
////  Author(s):                                                  ////
3125
////      - Michael Unneback, unneback@opencores.org              ////
3126
////        ORSoC AB                                              ////
3127
////                                                              ////
3128
//////////////////////////////////////////////////////////////////////
3129
////                                                              ////
3130
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3131
////                                                              ////
3132
//// This source file may be used and distributed without         ////
3133
//// restriction provided that this copyright statement is not    ////
3134
//// removed from the file and that any derivative work contains  ////
3135
//// the original copyright notice and the associated disclaimer. ////
3136
////                                                              ////
3137
//// This source file is free software; you can redistribute it   ////
3138
//// and/or modify it under the terms of the GNU Lesser General   ////
3139
//// Public License as published by the Free Software Foundation; ////
3140
//// either version 2.1 of the License, or (at your option) any   ////
3141
//// later version.                                               ////
3142
////                                                              ////
3143
//// This source is distributed in the hope that it will be       ////
3144
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3145
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3146
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3147
//// details.                                                     ////
3148
////                                                              ////
3149
//// You should have received a copy of the GNU Lesser General    ////
3150
//// Public License along with this source; if not, download it   ////
3151
//// from http://www.opencores.org/lgpl.shtml                     ////
3152
////                                                              ////
3153
//////////////////////////////////////////////////////////////////////
3154
 
3155
// GRAY counter
3156
 
3157 40 unneback
`define MODULE cnt_gray_ce
3158
module `BASE`MODULE (
3159
`undef MODULE
3160
 cke, q, rst, clk);
3161
 
3162 6 unneback
   parameter length = 4;
3163
   input cke;
3164
   output reg [length:1] q;
3165
   input rst;
3166
   input clk;
3167
 
3168
   parameter clear_value = 0;
3169
   parameter set_value = 1;
3170
   parameter wrap_value = 8;
3171
   parameter level1_value = 15;
3172
 
3173
   reg  [length:1] qi;
3174
   wire [length:1] q_next;
3175
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3176
 
3177
   always @ (posedge clk or posedge rst)
3178
     if (rst)
3179
       qi <= {length{1'b0}};
3180
     else
3181
     if (cke)
3182
       qi <= q_next;
3183
 
3184
   always @ (posedge clk or posedge rst)
3185
     if (rst)
3186
       q <= {length{1'b0}};
3187
     else
3188
       if (cke)
3189
         q <= (q_next>>1) ^ q_next;
3190
 
3191
endmodule
3192 40 unneback
`endif
3193
`ifdef CNT_GRAY_CE_BIN
3194 6 unneback
//////////////////////////////////////////////////////////////////////
3195
////                                                              ////
3196
////  Versatile counter                                           ////
3197
////                                                              ////
3198
////  Description                                                 ////
3199
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3200
////  counter                                                     ////
3201
////                                                              ////
3202
////  To Do:                                                      ////
3203
////   - add LFSR with more taps                                  ////
3204
////                                                              ////
3205
////  Author(s):                                                  ////
3206
////      - Michael Unneback, unneback@opencores.org              ////
3207
////        ORSoC AB                                              ////
3208
////                                                              ////
3209
//////////////////////////////////////////////////////////////////////
3210
////                                                              ////
3211
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3212
////                                                              ////
3213
//// This source file may be used and distributed without         ////
3214
//// restriction provided that this copyright statement is not    ////
3215
//// removed from the file and that any derivative work contains  ////
3216
//// the original copyright notice and the associated disclaimer. ////
3217
////                                                              ////
3218
//// This source file is free software; you can redistribute it   ////
3219
//// and/or modify it under the terms of the GNU Lesser General   ////
3220
//// Public License as published by the Free Software Foundation; ////
3221
//// either version 2.1 of the License, or (at your option) any   ////
3222
//// later version.                                               ////
3223
////                                                              ////
3224
//// This source is distributed in the hope that it will be       ////
3225
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3226
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3227
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3228
//// details.                                                     ////
3229
////                                                              ////
3230
//// You should have received a copy of the GNU Lesser General    ////
3231
//// Public License along with this source; if not, download it   ////
3232
//// from http://www.opencores.org/lgpl.shtml                     ////
3233
////                                                              ////
3234
//////////////////////////////////////////////////////////////////////
3235
 
3236
// GRAY counter
3237
 
3238 40 unneback
`define MODULE cnt_gray_ce_bin
3239
module `BASE`MODULE (
3240
`undef MODULE
3241
 cke, q, q_bin, rst, clk);
3242
 
3243 6 unneback
   parameter length = 4;
3244
   input cke;
3245
   output reg [length:1] q;
3246
   output [length:1] q_bin;
3247
   input rst;
3248
   input clk;
3249
 
3250
   parameter clear_value = 0;
3251
   parameter set_value = 1;
3252
   parameter wrap_value = 8;
3253
   parameter level1_value = 15;
3254
 
3255
   reg  [length:1] qi;
3256
   wire [length:1] q_next;
3257
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3258
 
3259
   always @ (posedge clk or posedge rst)
3260
     if (rst)
3261
       qi <= {length{1'b0}};
3262
     else
3263
     if (cke)
3264
       qi <= q_next;
3265
 
3266
   always @ (posedge clk or posedge rst)
3267
     if (rst)
3268
       q <= {length{1'b0}};
3269
     else
3270
       if (cke)
3271
         q <= (q_next>>1) ^ q_next;
3272
 
3273
   assign q_bin = qi;
3274
 
3275
endmodule
3276 40 unneback
`endif
3277 6 unneback
//////////////////////////////////////////////////////////////////////
3278
////                                                              ////
3279
////  Versatile library, counters                                 ////
3280
////                                                              ////
3281
////  Description                                                 ////
3282
////  counters                                                    ////
3283
////                                                              ////
3284
////                                                              ////
3285
////  To Do:                                                      ////
3286
////   - add more counters                                        ////
3287
////                                                              ////
3288
////  Author(s):                                                  ////
3289
////      - Michael Unneback, unneback@opencores.org              ////
3290
////        ORSoC AB                                              ////
3291
////                                                              ////
3292
//////////////////////////////////////////////////////////////////////
3293
////                                                              ////
3294
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
3295
////                                                              ////
3296
//// This source file may be used and distributed without         ////
3297
//// restriction provided that this copyright statement is not    ////
3298
//// removed from the file and that any derivative work contains  ////
3299
//// the original copyright notice and the associated disclaimer. ////
3300
////                                                              ////
3301
//// This source file is free software; you can redistribute it   ////
3302
//// and/or modify it under the terms of the GNU Lesser General   ////
3303
//// Public License as published by the Free Software Foundation; ////
3304
//// either version 2.1 of the License, or (at your option) any   ////
3305
//// later version.                                               ////
3306
////                                                              ////
3307
//// This source is distributed in the hope that it will be       ////
3308
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3309
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3310
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3311
//// details.                                                     ////
3312
////                                                              ////
3313
//// You should have received a copy of the GNU Lesser General    ////
3314
//// Public License along with this source; if not, download it   ////
3315
//// from http://www.opencores.org/lgpl.shtml                     ////
3316
////                                                              ////
3317
//////////////////////////////////////////////////////////////////////
3318
 
3319 40 unneback
`ifdef CNT_SHREG_WRAP
3320
`define MODULE cnt_shreg_wrap
3321
module `BASE`MODULE ( q, rst, clk);
3322
`undef MODULE
3323 6 unneback
 
3324
   parameter length = 4;
3325
   output reg [0:length-1] q;
3326
   input rst;
3327
   input clk;
3328
 
3329
    always @ (posedge clk or posedge rst)
3330
    if (rst)
3331
        q <= {1'b1,{length-1{1'b0}}};
3332
    else
3333
        q <= {q[length-1],q[0:length-2]};
3334
 
3335
endmodule
3336 40 unneback
`endif
3337 6 unneback
 
3338 40 unneback
`ifdef CNT_SHREG_CE_WRAP
3339
`define MODULE cnt_shreg_ce_wrap
3340
module `BASE`MODULE ( cke, q, rst, clk);
3341
`undef MODULE
3342 6 unneback
 
3343
   parameter length = 4;
3344
   input cke;
3345
   output reg [0:length-1] q;
3346
   input rst;
3347
   input clk;
3348
 
3349
    always @ (posedge clk or posedge rst)
3350
    if (rst)
3351
        q <= {1'b1,{length-1{1'b0}}};
3352
    else
3353
        if (cke)
3354
            q <= {q[length-1],q[0:length-2]};
3355
 
3356
endmodule
3357 40 unneback
`endif
3358 6 unneback
 
3359 40 unneback
`ifdef CNT_SHREG_CE_CLEAR
3360
`define MODULE cnt_shreg_ce_clear
3361
module `BASE`MODULE ( cke, clear, q, rst, clk);
3362
`undef MODULE
3363 6 unneback
 
3364
   parameter length = 4;
3365
   input cke, clear;
3366
   output reg [0:length-1] q;
3367
   input rst;
3368
   input clk;
3369
 
3370
    always @ (posedge clk or posedge rst)
3371
    if (rst)
3372
        q <= {1'b1,{length-1{1'b0}}};
3373
    else
3374
        if (cke)
3375
            if (clear)
3376
                q <= {1'b1,{length-1{1'b0}}};
3377
            else
3378
                q <= q >> 1;
3379
 
3380
endmodule
3381 40 unneback
`endif
3382 6 unneback
 
3383 40 unneback
`ifdef CNT_SHREG_CE_CLEAR_WRAP
3384
`define MODULE cnt_shreg_ce_clear_wrap
3385
module `BASE`MODULE ( cke, clear, q, rst, clk);
3386
`undef MODULE
3387 6 unneback
 
3388
   parameter length = 4;
3389
   input cke, clear;
3390
   output reg [0:length-1] q;
3391
   input rst;
3392
   input clk;
3393
 
3394
    always @ (posedge clk or posedge rst)
3395
    if (rst)
3396
        q <= {1'b1,{length-1{1'b0}}};
3397
    else
3398
        if (cke)
3399
            if (clear)
3400
                q <= {1'b1,{length-1{1'b0}}};
3401
            else
3402
            q <= {q[length-1],q[0:length-2]};
3403
 
3404
endmodule
3405 40 unneback
`endif
3406 6 unneback
//////////////////////////////////////////////////////////////////////
3407
////                                                              ////
3408
////  Versatile library, memories                                 ////
3409
////                                                              ////
3410
////  Description                                                 ////
3411
////  memories                                                    ////
3412
////                                                              ////
3413
////                                                              ////
3414
////  To Do:                                                      ////
3415
////   - add more memory types                                    ////
3416
////                                                              ////
3417
////  Author(s):                                                  ////
3418
////      - Michael Unneback, unneback@opencores.org              ////
3419
////        ORSoC AB                                              ////
3420
////                                                              ////
3421
//////////////////////////////////////////////////////////////////////
3422
////                                                              ////
3423
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
3424
////                                                              ////
3425
//// This source file may be used and distributed without         ////
3426
//// restriction provided that this copyright statement is not    ////
3427
//// removed from the file and that any derivative work contains  ////
3428
//// the original copyright notice and the associated disclaimer. ////
3429
////                                                              ////
3430
//// This source file is free software; you can redistribute it   ////
3431
//// and/or modify it under the terms of the GNU Lesser General   ////
3432
//// Public License as published by the Free Software Foundation; ////
3433
//// either version 2.1 of the License, or (at your option) any   ////
3434
//// later version.                                               ////
3435
////                                                              ////
3436
//// This source is distributed in the hope that it will be       ////
3437
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3438
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3439
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3440
//// details.                                                     ////
3441
////                                                              ////
3442
//// You should have received a copy of the GNU Lesser General    ////
3443
//// Public License along with this source; if not, download it   ////
3444
//// from http://www.opencores.org/lgpl.shtml                     ////
3445
////                                                              ////
3446
//////////////////////////////////////////////////////////////////////
3447
 
3448 40 unneback
`ifdef ROM_INIT
3449 6 unneback
/// ROM
3450 40 unneback
`define MODULE rom_init
3451
module `BASE`MODULE ( adr, q, clk);
3452
`undef MODULE
3453 6 unneback
 
3454 7 unneback
   parameter data_width = 32;
3455
   parameter addr_width = 8;
3456
   input [(addr_width-1):0]       adr;
3457
   output reg [(data_width-1):0] q;
3458
   input                         clk;
3459
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
3460
   parameter memory_file = "vl_rom.vmem";
3461
   initial
3462
     begin
3463
        $readmemh(memory_file, rom);
3464
     end
3465
 
3466
   always @ (posedge clk)
3467
     q <= rom[adr];
3468 6 unneback
 
3469 7 unneback
endmodule
3470 40 unneback
`endif
3471 7 unneback
 
3472 40 unneback
`ifdef RAM
3473
`define MODULE ram
3474 6 unneback
// Single port RAM
3475 40 unneback
module `BASE`MODULE ( d, adr, we, q, clk);
3476
`undef MODULE
3477 6 unneback
 
3478
   parameter data_width = 32;
3479
   parameter addr_width = 8;
3480
   input [(data_width-1):0]      d;
3481
   input [(addr_width-1):0]       adr;
3482
   input                         we;
3483 7 unneback
   output reg [(data_width-1):0] q;
3484 6 unneback
   input                         clk;
3485
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
3486 7 unneback
   parameter init = 0;
3487
   parameter memory_file = "vl_ram.vmem";
3488
   generate if (init) begin : init_mem
3489
   initial
3490
     begin
3491
        $readmemh(memory_file, ram);
3492
     end
3493
   end
3494
   endgenerate
3495
 
3496 6 unneback
   always @ (posedge clk)
3497
   begin
3498
   if (we)
3499
     ram[adr] <= d;
3500
   q <= ram[adr];
3501
   end
3502
 
3503
endmodule
3504 40 unneback
`endif
3505 6 unneback
 
3506 40 unneback
`ifdef RAM_BE
3507
`define MODULE ram_be
3508
module `BASE`MODULE ( d, adr, be, we, q, clk);
3509
`undef MODULE
3510
 
3511 7 unneback
   parameter data_width = 32;
3512
   parameter addr_width = 8;
3513
   input [(data_width-1):0]      d;
3514
   input [(addr_width-1):0]       adr;
3515
   input [(addr_width/4)-1:0]    be;
3516
   input                         we;
3517
   output reg [(data_width-1):0] q;
3518
   input                         clk;
3519
 
3520
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
3521
 
3522
   parameter init = 0;
3523
   parameter memory_file = "vl_ram.vmem";
3524
   generate if (init) begin : init_mem
3525
   initial
3526
     begin
3527
        $readmemh(memory_file, ram);
3528
     end
3529
   end
3530
   endgenerate
3531
 
3532
   genvar i;
3533
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
3534
      always @ (posedge clk)
3535
      if (we & be[i])
3536
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
3537
   end
3538
   endgenerate
3539
 
3540
   always @ (posedge clk)
3541
      q <= ram[adr];
3542
 
3543
endmodule
3544 40 unneback
`endif
3545 7 unneback
 
3546 6 unneback
`ifdef ACTEL
3547 48 unneback
        // ACTEL FPGA should not use logic to handle rw collision
3548 6 unneback
        `define SYN /*synthesis syn_ramstyle = "no_rw_check"*/
3549
`else
3550
        `define SYN
3551
`endif
3552
 
3553 40 unneback
`ifdef DPRAM_1R1W
3554
`define MODULE dpram_1r1w
3555
module `BASE`MODULE ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
3556
`undef MODULE
3557 6 unneback
   parameter data_width = 32;
3558
   parameter addr_width = 8;
3559
   input [(data_width-1):0]      d_a;
3560
   input [(addr_width-1):0]       adr_a;
3561
   input [(addr_width-1):0]       adr_b;
3562
   input                         we_a;
3563
   output [(data_width-1):0]      q_b;
3564
   input                         clk_a, clk_b;
3565
   reg [(addr_width-1):0]         adr_b_reg;
3566
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
3567 7 unneback
 
3568
   parameter init = 0;
3569
   parameter memory_file = "vl_ram.vmem";
3570
   generate if (init) begin : init_mem
3571
   initial
3572
     begin
3573
        $readmemh(memory_file, ram);
3574
     end
3575
   end
3576
   endgenerate
3577
 
3578 6 unneback
   always @ (posedge clk_a)
3579
   if (we_a)
3580
     ram[adr_a] <= d_a;
3581
   always @ (posedge clk_b)
3582
   adr_b_reg <= adr_b;
3583
   assign q_b = ram[adr_b_reg];
3584 40 unneback
 
3585 6 unneback
endmodule
3586 40 unneback
`endif
3587 6 unneback
 
3588 40 unneback
`ifdef DPRAM_2R1W
3589
`define MODULE dpram_2r1w
3590
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
3591
`undef MODULE
3592
 
3593 6 unneback
   parameter data_width = 32;
3594
   parameter addr_width = 8;
3595
   input [(data_width-1):0]      d_a;
3596
   input [(addr_width-1):0]       adr_a;
3597
   input [(addr_width-1):0]       adr_b;
3598
   input                         we_a;
3599
   output [(data_width-1):0]      q_b;
3600
   output reg [(data_width-1):0] q_a;
3601
   input                         clk_a, clk_b;
3602
   reg [(data_width-1):0]         q_b;
3603
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
3604 7 unneback
 
3605
   parameter init = 0;
3606
   parameter memory_file = "vl_ram.vmem";
3607
   generate if (init) begin : init_mem
3608
   initial
3609
     begin
3610
        $readmemh(memory_file, ram);
3611
     end
3612
   end
3613
   endgenerate
3614
 
3615 6 unneback
   always @ (posedge clk_a)
3616
     begin
3617
        q_a <= ram[adr_a];
3618
        if (we_a)
3619
             ram[adr_a] <= d_a;
3620
     end
3621
   always @ (posedge clk_b)
3622
          q_b <= ram[adr_b];
3623
endmodule
3624 40 unneback
`endif
3625 6 unneback
 
3626 40 unneback
`ifdef DPRAM_2R2W
3627
`define MODULE dpram_2r2w
3628
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
3629
`undef MODULE
3630
 
3631 6 unneback
   parameter data_width = 32;
3632
   parameter addr_width = 8;
3633
   input [(data_width-1):0]      d_a;
3634
   input [(addr_width-1):0]       adr_a;
3635
   input [(addr_width-1):0]       adr_b;
3636
   input                         we_a;
3637
   output [(data_width-1):0]      q_b;
3638
   input [(data_width-1):0]       d_b;
3639
   output reg [(data_width-1):0] q_a;
3640
   input                         we_b;
3641
   input                         clk_a, clk_b;
3642
   reg [(data_width-1):0]         q_b;
3643
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] `SYN;
3644 7 unneback
 
3645
   parameter init = 0;
3646
   parameter memory_file = "vl_ram.vmem";
3647
   generate if (init) begin : init_mem
3648
   initial
3649
     begin
3650
        $readmemh(memory_file, ram);
3651
     end
3652
   end
3653
   endgenerate
3654
 
3655 6 unneback
   always @ (posedge clk_a)
3656
     begin
3657
        q_a <= ram[adr_a];
3658
        if (we_a)
3659
             ram[adr_a] <= d_a;
3660
     end
3661
   always @ (posedge clk_b)
3662
     begin
3663
        q_b <= ram[adr_b];
3664
        if (we_b)
3665
          ram[adr_b] <= d_b;
3666
     end
3667
endmodule
3668 40 unneback
`endif
3669 6 unneback
 
3670
// Content addresable memory, CAM
3671
 
3672 40 unneback
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
3673 6 unneback
// FIFO
3674 40 unneback
`define MODULE fifo_1r1w_fill_level_sync
3675
module `BASE`MODULE (
3676
`undef MODULE
3677 25 unneback
    d, wr, fifo_full,
3678
    q, rd, fifo_empty,
3679
    fill_level,
3680
    clk, rst
3681
    );
3682
 
3683
parameter data_width = 18;
3684
parameter addr_width = 4;
3685 6 unneback
 
3686 25 unneback
// write side
3687
input  [data_width-1:0] d;
3688
input                   wr;
3689
output                  fifo_full;
3690
// read side
3691
output [data_width-1:0] q;
3692
input                   rd;
3693
output                  fifo_empty;
3694
// common
3695
output [addr_width:0]   fill_level;
3696
input rst, clk;
3697
 
3698
wire [addr_width:1] wadr, radr;
3699
 
3700 40 unneback
`define MODULE cnt_bin_ce
3701
`BASE`MODULE
3702 25 unneback
    # ( .length(addr_width))
3703
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
3704 40 unneback
`BASE`MODULE
3705 25 unneback
    # (.length(addr_width))
3706
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
3707 40 unneback
`undef MODULE
3708 25 unneback
 
3709 40 unneback
`define MODULE dpram_1r1w
3710
`BASE`MODULE
3711 25 unneback
    # (.data_width(data_width), .addr_width(addr_width))
3712
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
3713 40 unneback
`undef MODULE
3714 25 unneback
 
3715 40 unneback
`define MODULE cnt_bin_ce_rew_q_zq_l1
3716
`BASE`MODULE
3717 27 unneback
    # (.length(addr_width+1), .level1_value(1<<addr_width))
3718 25 unneback
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
3719 40 unneback
`undef MODULE
3720 25 unneback
endmodule
3721 40 unneback
`endif
3722 25 unneback
 
3723 40 unneback
`ifdef FIFO_2R2W_SYNC_SIMPLEX
3724 27 unneback
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
3725
// RAM is supposed to be larger than the two FIFOs
3726
// LFSR counters used adr pointers
3727 40 unneback
`define MODULE fifo_2r2w_sync_simplex
3728
module `BASE`MODULE (
3729
`undef MODULE
3730 27 unneback
    // a side
3731
    a_d, a_wr, a_fifo_full,
3732
    a_q, a_rd, a_fifo_empty,
3733
    a_fill_level,
3734
    // b side
3735
    b_d, b_wr, b_fifo_full,
3736
    b_q, b_rd, b_fifo_empty,
3737
    b_fill_level,
3738
    // common
3739
    clk, rst
3740
    );
3741
parameter data_width = 8;
3742
parameter addr_width = 5;
3743
parameter fifo_full_level = (1<<addr_width)-1;
3744
 
3745
// a side
3746
input  [data_width-1:0] a_d;
3747
input                   a_wr;
3748
output                  a_fifo_full;
3749
output [data_width-1:0] a_q;
3750
input                   a_rd;
3751
output                  a_fifo_empty;
3752
output [addr_width-1:0] a_fill_level;
3753
 
3754
// b side
3755
input  [data_width-1:0] b_d;
3756
input                   b_wr;
3757
output                  b_fifo_full;
3758
output [data_width-1:0] b_q;
3759
input                   b_rd;
3760
output                  b_fifo_empty;
3761
output [addr_width-1:0] b_fill_level;
3762
 
3763
input                   clk;
3764
input                   rst;
3765
 
3766
// adr_gen
3767
wire [addr_width:1] a_wadr, a_radr;
3768
wire [addr_width:1] b_wadr, b_radr;
3769
// dpram
3770
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
3771
 
3772 40 unneback
`define MODULE cnt_lfsr_ce
3773
`BASE`MODULE
3774 27 unneback
    # ( .length(addr_width))
3775
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
3776
 
3777 40 unneback
`BASE`MODULE
3778 27 unneback
    # (.length(addr_width))
3779
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
3780
 
3781 40 unneback
`BASE`MODULE
3782 27 unneback
    # ( .length(addr_width))
3783
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
3784
 
3785 40 unneback
`BASE`MODULE
3786 27 unneback
    # (.length(addr_width))
3787
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
3788 40 unneback
`undef MODULE
3789 27 unneback
 
3790
// mux read or write adr to DPRAM
3791
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
3792
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
3793
 
3794 40 unneback
`define MODULE dpram_2r2w
3795
`BASE`MODULE
3796 27 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
3797
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
3798
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
3799 40 unneback
`undef MODULE
3800
 
3801
`define MODULE cnt_bin_ce_rew_zq_l1
3802
`BASE`MODULE
3803 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
3804 27 unneback
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
3805
 
3806 40 unneback
`BASE`MODULE
3807 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
3808 27 unneback
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
3809 40 unneback
`undef MODULE
3810 27 unneback
 
3811
endmodule
3812 40 unneback
`endif
3813 27 unneback
 
3814 40 unneback
`ifdef FIFO_CMP_ASYNC
3815
`define MODULE fifo_cmp_async
3816
module `BASE`MODULE ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
3817
`undef MODULE
3818 6 unneback
 
3819 11 unneback
   parameter addr_width = 4;
3820
   parameter N = addr_width-1;
3821 6 unneback
 
3822
   parameter Q1 = 2'b00;
3823
   parameter Q2 = 2'b01;
3824
   parameter Q3 = 2'b11;
3825
   parameter Q4 = 2'b10;
3826
 
3827
   parameter going_empty = 1'b0;
3828
   parameter going_full  = 1'b1;
3829
 
3830
   input [N:0]  wptr, rptr;
3831 14 unneback
   output       fifo_empty;
3832 6 unneback
   output       fifo_full;
3833
   input        wclk, rclk, rst;
3834
 
3835
`ifndef GENERATE_DIRECTION_AS_LATCH
3836
   wire direction;
3837
`endif
3838
`ifdef GENERATE_DIRECTION_AS_LATCH
3839
   reg direction;
3840
`endif
3841
   reg  direction_set, direction_clr;
3842
 
3843
   wire async_empty, async_full;
3844
   wire fifo_full2;
3845 14 unneback
   wire fifo_empty2;
3846 6 unneback
 
3847
   // direction_set
3848
   always @ (wptr[N:N-1] or rptr[N:N-1])
3849
     case ({wptr[N:N-1],rptr[N:N-1]})
3850
       {Q1,Q2} : direction_set <= 1'b1;
3851
       {Q2,Q3} : direction_set <= 1'b1;
3852
       {Q3,Q4} : direction_set <= 1'b1;
3853
       {Q4,Q1} : direction_set <= 1'b1;
3854
       default : direction_set <= 1'b0;
3855
     endcase
3856
 
3857
   // direction_clear
3858
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
3859
     if (rst)
3860
       direction_clr <= 1'b1;
3861
     else
3862
       case ({wptr[N:N-1],rptr[N:N-1]})
3863
         {Q2,Q1} : direction_clr <= 1'b1;
3864
         {Q3,Q2} : direction_clr <= 1'b1;
3865
         {Q4,Q3} : direction_clr <= 1'b1;
3866
         {Q1,Q4} : direction_clr <= 1'b1;
3867
         default : direction_clr <= 1'b0;
3868
       endcase
3869
 
3870 40 unneback
`define MODULE dff_sr
3871 6 unneback
`ifndef GENERATE_DIRECTION_AS_LATCH
3872 40 unneback
    `BASE`MODULE dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
3873 6 unneback
`endif
3874
 
3875
`ifdef GENERATE_DIRECTION_AS_LATCH
3876
   always @ (posedge direction_set or posedge direction_clr)
3877
     if (direction_clr)
3878
       direction <= going_empty;
3879
     else
3880
       direction <= going_full;
3881
`endif
3882
 
3883
   assign async_empty = (wptr == rptr) && (direction==going_empty);
3884
   assign async_full  = (wptr == rptr) && (direction==going_full);
3885
 
3886 40 unneback
    `BASE`MODULE dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
3887
    `BASE`MODULE dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
3888
`undef MODULE
3889 6 unneback
 
3890
/*
3891
   always @ (posedge wclk or posedge rst or posedge async_full)
3892
     if (rst)
3893
       {fifo_full, fifo_full2} <= 2'b00;
3894
     else if (async_full)
3895
       {fifo_full, fifo_full2} <= 2'b11;
3896
     else
3897
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
3898
*/
3899 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
3900 6 unneback
     if (async_empty)
3901
       {fifo_empty, fifo_empty2} <= 2'b11;
3902
     else
3903 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
3904 40 unneback
`define MODULE dff
3905
    `BASE`MODULE # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
3906
    `BASE`MODULE # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
3907
`undef MODULE
3908 27 unneback
endmodule // async_compb
3909 40 unneback
`endif
3910 6 unneback
 
3911 40 unneback
`ifdef FIFO_1R1W_ASYNC
3912
`define MODULE fifo_1r1w_async
3913
module `BASE`MODULE (
3914
`undef MODULE
3915 6 unneback
    d, wr, fifo_full, wr_clk, wr_rst,
3916
    q, rd, fifo_empty, rd_clk, rd_rst
3917
    );
3918
 
3919
parameter data_width = 18;
3920
parameter addr_width = 4;
3921
 
3922
// write side
3923
input  [data_width-1:0] d;
3924
input                   wr;
3925
output                  fifo_full;
3926
input                   wr_clk;
3927
input                   wr_rst;
3928
// read side
3929
output [data_width-1:0] q;
3930
input                   rd;
3931
output                  fifo_empty;
3932
input                   rd_clk;
3933
input                   rd_rst;
3934
 
3935
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
3936 23 unneback
 
3937 40 unneback
`define MODULE cnt_gray_ce_bin
3938
`BASE`MODULE
3939 6 unneback
    # ( .length(addr_width))
3940
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
3941
 
3942 40 unneback
`BASE`MODULE
3943 6 unneback
    # (.length(addr_width))
3944 23 unneback
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
3945 40 unneback
`undef MODULE
3946 6 unneback
 
3947 40 unneback
`define MODULE dpram_1r1w
3948
`BASE`MODULE
3949 6 unneback
    # (.data_width(data_width), .addr_width(addr_width))
3950
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
3951 40 unneback
`undef MODULE
3952 6 unneback
 
3953 40 unneback
`define MODULE fifo_cmp_async
3954
`BASE`MODULE
3955 6 unneback
    # (.addr_width(addr_width))
3956
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
3957 40 unneback
`undef MODULE
3958 6 unneback
 
3959
endmodule
3960 40 unneback
`endif
3961 6 unneback
 
3962 40 unneback
`ifdef FIFO_2R2W_ASYNC
3963
`define MODULE fifo_2r2w_async
3964
module `BASE`MODULE (
3965
`undef MODULE
3966 6 unneback
    // a side
3967
    a_d, a_wr, a_fifo_full,
3968
    a_q, a_rd, a_fifo_empty,
3969
    a_clk, a_rst,
3970
    // b side
3971
    b_d, b_wr, b_fifo_full,
3972
    b_q, b_rd, b_fifo_empty,
3973
    b_clk, b_rst
3974
    );
3975
 
3976
parameter data_width = 18;
3977
parameter addr_width = 4;
3978
 
3979
// a side
3980
input  [data_width-1:0] a_d;
3981
input                   a_wr;
3982
output                  a_fifo_full;
3983
output [data_width-1:0] a_q;
3984
input                   a_rd;
3985
output                  a_fifo_empty;
3986
input                   a_clk;
3987
input                   a_rst;
3988
 
3989
// b side
3990
input  [data_width-1:0] b_d;
3991
input                   b_wr;
3992
output                  b_fifo_full;
3993
output [data_width-1:0] b_q;
3994
input                   b_rd;
3995
output                  b_fifo_empty;
3996
input                   b_clk;
3997
input                   b_rst;
3998
 
3999 40 unneback
`define MODULE fifo_1r1w_async
4000
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
4001 6 unneback
vl_fifo_1r1w_async_a (
4002
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
4003
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
4004
    );
4005
 
4006 40 unneback
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
4007 6 unneback
vl_fifo_1r1w_async_b (
4008
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
4009
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
4010
    );
4011 40 unneback
`undef MODULE
4012
 
4013 6 unneback
endmodule
4014 40 unneback
`endif
4015 6 unneback
 
4016 40 unneback
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
4017
`define MODULE fifo_2r2w_async_simplex
4018
module `BASE`MODULE (
4019
`undef MODULE
4020 6 unneback
    // a side
4021
    a_d, a_wr, a_fifo_full,
4022
    a_q, a_rd, a_fifo_empty,
4023
    a_clk, a_rst,
4024
    // b side
4025
    b_d, b_wr, b_fifo_full,
4026
    b_q, b_rd, b_fifo_empty,
4027
    b_clk, b_rst
4028
    );
4029
 
4030
parameter data_width = 18;
4031
parameter addr_width = 4;
4032
 
4033
// a side
4034
input  [data_width-1:0] a_d;
4035
input                   a_wr;
4036
output                  a_fifo_full;
4037
output [data_width-1:0] a_q;
4038
input                   a_rd;
4039
output                  a_fifo_empty;
4040
input                   a_clk;
4041
input                   a_rst;
4042
 
4043
// b side
4044
input  [data_width-1:0] b_d;
4045
input                   b_wr;
4046
output                  b_fifo_full;
4047
output [data_width-1:0] b_q;
4048
input                   b_rd;
4049
output                  b_fifo_empty;
4050
input                   b_clk;
4051
input                   b_rst;
4052
 
4053
// adr_gen
4054
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
4055
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
4056
// dpram
4057
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
4058
 
4059 40 unneback
`define MODULE cnt_gray_ce_bin
4060
`BASE`MODULE
4061 6 unneback
    # ( .length(addr_width))
4062
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
4063
 
4064 40 unneback
`BASE`MODULE
4065 6 unneback
    # (.length(addr_width))
4066
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
4067
 
4068 40 unneback
`BASE`MODULE
4069 6 unneback
    # ( .length(addr_width))
4070
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
4071
 
4072 40 unneback
`BASE`MODULE
4073 6 unneback
    # (.length(addr_width))
4074
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
4075 40 unneback
`undef MODULE
4076 6 unneback
 
4077
// mux read or write adr to DPRAM
4078
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
4079
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
4080
 
4081 40 unneback
`define MODULE dpram_2r2w
4082
`BASE`MODULE
4083 6 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
4084
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
4085
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
4086 40 unneback
`undef MODULE
4087 6 unneback
 
4088 40 unneback
`define MODULE fifo_cmp_async
4089
`BASE`MODULE
4090 6 unneback
    # (.addr_width(addr_width))
4091
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
4092
 
4093 40 unneback
`BASE`MODULE
4094 6 unneback
    # (.addr_width(addr_width))
4095
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
4096 40 unneback
`undef MODULE
4097 6 unneback
 
4098
endmodule
4099 40 unneback
`endif
4100 48 unneback
 
4101
`ifdef REG_FILE
4102
`define MODULE reg_file
4103
module `BASE`MODULE (
4104
`undef MODULE
4105
    a1, a2, a3, wd3, we3, rd1, rd2, clk
4106
);
4107
parameter data_width = 32;
4108
parameter addr_width = 5;
4109
input [addr_width-1:0] a1, a2, a3;
4110
input [data_width-1:0] wd3;
4111
input we3;
4112
output [data_width-1:0] rd1, rd2;
4113
input clk;
4114
 
4115
`ifdef ACTEL
4116
reg [data_width-1:0] wd3_reg;
4117
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
4118
reg we3_reg;
4119
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] `SYN;
4120
reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] `SYN;
4121
always @ (posedge clk or posedge rst)
4122
if (rst)
4123
    {wd3_reg, a3_reg, we3_reg} <= {(data_width+addr_width+1){1'b0}};
4124
else
4125
    {wd3_reg, a3_reg, we3_reg} <= {wd3,a3,wd3};
4126
 
4127
    always @ (negedge clk)
4128
    if (we3_reg)
4129
        ram1[a3_reg] <= wd3;
4130
    always @ (posedge clk)
4131
        a1_reg <= a1;
4132
    assign rd1 = ram1[a1_reg];
4133
 
4134
    always @ (negedge clk)
4135
    if (we3_reg)
4136
        ram2[a3_reg] <= wd3;
4137
    always @ (posedge clk)
4138
        a2_reg <= a2;
4139
    assign rd2 = ram2[a2_reg];
4140
 
4141
`else
4142
 
4143
`define MODULE dpram_1r1w
4144
`BASE`MODULE
4145
    # ( .data_width(data_width), .addr_width(addr_width))
4146
    ram1 (
4147
        .d_a(wd3),
4148
        .adr_a(a3),
4149
        .we_a(we3),
4150
        .clk_a(clk),
4151
        .q_b(rd1),
4152
        .adr_b(a1),
4153
        .clk_b(clk) );
4154
 
4155
`BASE`MODULE
4156
    # ( .data_width(data_width), .addr_width(addr_width))
4157
    ram2 (
4158
        .d_a(wd3),
4159
        .adr_a(a3),
4160
        .we_a(we3),
4161
        .clk_a(clk),
4162
        .q_b(rd2),
4163
        .adr_b(a2),
4164
        .clk_b(clk) );
4165
`undef MODULE
4166
 
4167
`endif
4168
 
4169
endmodule
4170
`endif
4171 12 unneback
//////////////////////////////////////////////////////////////////////
4172
////                                                              ////
4173
////  Versatile library, wishbone stuff                           ////
4174
////                                                              ////
4175
////  Description                                                 ////
4176
////  Wishbone compliant modules                                  ////
4177
////                                                              ////
4178
////                                                              ////
4179
////  To Do:                                                      ////
4180
////   -                                                          ////
4181
////                                                              ////
4182
////  Author(s):                                                  ////
4183
////      - Michael Unneback, unneback@opencores.org              ////
4184
////        ORSoC AB                                              ////
4185
////                                                              ////
4186
//////////////////////////////////////////////////////////////////////
4187
////                                                              ////
4188
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
4189
////                                                              ////
4190
//// This source file may be used and distributed without         ////
4191
//// restriction provided that this copyright statement is not    ////
4192
//// removed from the file and that any derivative work contains  ////
4193
//// the original copyright notice and the associated disclaimer. ////
4194
////                                                              ////
4195
//// This source file is free software; you can redistribute it   ////
4196
//// and/or modify it under the terms of the GNU Lesser General   ////
4197
//// Public License as published by the Free Software Foundation; ////
4198
//// either version 2.1 of the License, or (at your option) any   ////
4199
//// later version.                                               ////
4200
////                                                              ////
4201
//// This source is distributed in the hope that it will be       ////
4202
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
4203
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
4204
//// PURPOSE.  See the GNU Lesser General Public License for more ////
4205
//// details.                                                     ////
4206
////                                                              ////
4207
//// You should have received a copy of the GNU Lesser General    ////
4208
//// Public License along with this source; if not, download it   ////
4209
//// from http://www.opencores.org/lgpl.shtml                     ////
4210
////                                                              ////
4211
//////////////////////////////////////////////////////////////////////
4212
 
4213 40 unneback
`ifdef WB3WB3_BRIDGE
4214 12 unneback
// async wb3 - wb3 bridge
4215
`timescale 1ns/1ns
4216 40 unneback
`define MODULE wb3wb3_bridge
4217
module `BASE`MODULE (
4218
`undef MODULE
4219 12 unneback
        // wishbone slave side
4220
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
4221
        // wishbone master side
4222
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
4223
 
4224
input [31:0] wbs_dat_i;
4225
input [31:2] wbs_adr_i;
4226
input [3:0]  wbs_sel_i;
4227
input [1:0]  wbs_bte_i;
4228
input [2:0]  wbs_cti_i;
4229
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
4230
output [31:0] wbs_dat_o;
4231 14 unneback
output wbs_ack_o;
4232 12 unneback
input wbs_clk, wbs_rst;
4233
 
4234
output [31:0] wbm_dat_o;
4235
output reg [31:2] wbm_adr_o;
4236
output [3:0]  wbm_sel_o;
4237
output reg [1:0]  wbm_bte_o;
4238
output reg [2:0]  wbm_cti_o;
4239 14 unneback
output reg wbm_we_o;
4240
output wbm_cyc_o;
4241 12 unneback
output wbm_stb_o;
4242
input [31:0]  wbm_dat_i;
4243
input wbm_ack_i;
4244
input wbm_clk, wbm_rst;
4245
 
4246
parameter addr_width = 4;
4247
 
4248
// bte
4249
parameter linear       = 2'b00;
4250
parameter wrap4        = 2'b01;
4251
parameter wrap8        = 2'b10;
4252
parameter wrap16       = 2'b11;
4253
// cti
4254
parameter classic      = 3'b000;
4255
parameter incburst     = 3'b010;
4256
parameter endofburst   = 3'b111;
4257
 
4258
parameter wbs_adr  = 1'b0;
4259
parameter wbs_data = 1'b1;
4260
 
4261 33 unneback
parameter wbm_adr0      = 2'b00;
4262
parameter wbm_adr1      = 2'b01;
4263
parameter wbm_data      = 2'b10;
4264
parameter wbm_data_wait = 2'b11;
4265 12 unneback
 
4266
reg [1:0] wbs_bte_reg;
4267
reg wbs;
4268
wire wbs_eoc_alert, wbm_eoc_alert;
4269
reg wbs_eoc, wbm_eoc;
4270
reg [1:0] wbm;
4271
 
4272 14 unneback
wire [1:16] wbs_count, wbm_count;
4273 12 unneback
 
4274
wire [35:0] a_d, a_q, b_d, b_q;
4275
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
4276
reg a_rd_reg;
4277
wire b_rd_adr, b_rd_data;
4278 14 unneback
wire b_rd_data_reg;
4279
wire [35:0] temp;
4280 12 unneback
 
4281
`define WE 5
4282
`define BTE 4:3
4283
`define CTI 2:0
4284
 
4285
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
4286
always @ (posedge wbs_clk or posedge wbs_rst)
4287
if (wbs_rst)
4288
        wbs_eoc <= 1'b0;
4289
else
4290
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
4291
                wbs_eoc <= wbs_bte_i==linear;
4292
        else if (wbs_eoc_alert & (a_rd | a_wr))
4293
                wbs_eoc <= 1'b1;
4294
 
4295 40 unneback
`define MODULE cnt_shreg_ce_clear
4296
`BASE`MODULE # ( .length(16))
4297
`undef MODULE
4298 12 unneback
    cnt0 (
4299
        .cke(wbs_ack_o),
4300
        .clear(wbs_eoc),
4301
        .q(wbs_count),
4302
        .rst(wbs_rst),
4303
        .clk(wbs_clk));
4304
 
4305
always @ (posedge wbs_clk or posedge wbs_rst)
4306
if (wbs_rst)
4307
        wbs <= wbs_adr;
4308
else
4309
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & !a_fifo_full)
4310
                wbs <= wbs_data;
4311
        else if (wbs_eoc & wbs_ack_o)
4312
                wbs <= wbs_adr;
4313
 
4314
// wbs FIFO
4315
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,wbs_bte_i,wbs_cti_i} : {wbs_dat_i,wbs_sel_i};
4316
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & !a_fifo_full :
4317
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
4318
              1'b0;
4319
assign a_rd = !a_fifo_empty;
4320
always @ (posedge wbs_clk or posedge wbs_rst)
4321
if (wbs_rst)
4322
        a_rd_reg <= 1'b0;
4323
else
4324
        a_rd_reg <= a_rd;
4325
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
4326
 
4327
assign wbs_dat_o = a_q[35:4];
4328
 
4329
always @ (posedge wbs_clk or posedge wbs_rst)
4330
if (wbs_rst)
4331 13 unneback
        wbs_bte_reg <= 2'b00;
4332 12 unneback
else
4333 13 unneback
        wbs_bte_reg <= wbs_bte_i;
4334 12 unneback
 
4335
// wbm FIFO
4336
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
4337
always @ (posedge wbm_clk or posedge wbm_rst)
4338
if (wbm_rst)
4339
        wbm_eoc <= 1'b0;
4340
else
4341
        if (wbm==wbm_adr0 & !b_fifo_empty)
4342
                wbm_eoc <= b_q[`BTE] == linear;
4343
        else if (wbm_eoc_alert & wbm_ack_i)
4344
                wbm_eoc <= 1'b1;
4345
 
4346
always @ (posedge wbm_clk or posedge wbm_rst)
4347
if (wbm_rst)
4348
        wbm <= wbm_adr0;
4349
else
4350 33 unneback
/*
4351 12 unneback
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
4352
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
4353
        (wbm==wbm_adr1 & !wbm_we_o) |
4354
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
4355
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
4356 33 unneback
*/
4357
    case (wbm)
4358
    wbm_adr0:
4359
        if (!b_fifo_empty)
4360
            wbm <= wbm_adr1;
4361
    wbm_adr1:
4362
        if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
4363
            wbm <= wbm_data;
4364
    wbm_data:
4365
        if (wbm_ack_i & wbm_eoc)
4366
            wbm <= wbm_adr0;
4367
        else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
4368
            wbm <= wbm_data_wait;
4369
    wbm_data_wait:
4370
        if (!b_fifo_empty)
4371
            wbm <= wbm_data;
4372
    endcase
4373 12 unneback
 
4374
assign b_d = {wbm_dat_i,4'b1111};
4375
assign b_wr = !wbm_we_o & wbm_ack_i;
4376
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
4377
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
4378
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
4379 33 unneback
                   (wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
4380 12 unneback
                   1'b0;
4381
assign b_rd = b_rd_adr | b_rd_data;
4382
 
4383 40 unneback
`define MODULE dff
4384
`BASE`MODULE dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
4385
`undef MODULE
4386
`define MODULE dff_ce
4387
`BASE`MODULE # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
4388
`undef MODULE
4389 12 unneback
 
4390
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
4391
 
4392 40 unneback
`define MODULE cnt_shreg_ce_clear
4393 42 unneback
`BASE`MODULE # ( .length(16))
4394 40 unneback
`undef MODULE
4395 12 unneback
    cnt1 (
4396
        .cke(wbm_ack_i),
4397
        .clear(wbm_eoc),
4398
        .q(wbm_count),
4399
        .rst(wbm_rst),
4400
        .clk(wbm_clk));
4401
 
4402 33 unneback
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
4403
assign wbm_stb_o = (wbm==wbm_data);
4404 12 unneback
 
4405
always @ (posedge wbm_clk or posedge wbm_rst)
4406
if (wbm_rst)
4407
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
4408
else begin
4409
        if (wbm==wbm_adr0 & !b_fifo_empty)
4410
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
4411
        else if (wbm_eoc_alert & wbm_ack_i)
4412
                wbm_cti_o <= endofburst;
4413
end
4414
 
4415
//async_fifo_dw_simplex_top
4416 40 unneback
`define MODULE fifo_2r2w_async_simplex
4417
`BASE`MODULE
4418
`undef MODULE
4419 12 unneback
# ( .data_width(36), .addr_width(addr_width))
4420
fifo (
4421
    // a side
4422
    .a_d(a_d),
4423
    .a_wr(a_wr),
4424
    .a_fifo_full(a_fifo_full),
4425
    .a_q(a_q),
4426
    .a_rd(a_rd),
4427
    .a_fifo_empty(a_fifo_empty),
4428
    .a_clk(wbs_clk),
4429
    .a_rst(wbs_rst),
4430
    // b side
4431
    .b_d(b_d),
4432
    .b_wr(b_wr),
4433
    .b_fifo_full(b_fifo_full),
4434
    .b_q(b_q),
4435
    .b_rd(b_rd),
4436
    .b_fifo_empty(b_fifo_empty),
4437
    .b_clk(wbm_clk),
4438
    .b_rst(wbm_rst)
4439
    );
4440
 
4441
endmodule
4442 40 unneback
`undef WE
4443
`undef BTE
4444
`undef CTI
4445
`endif
4446 17 unneback
 
4447 40 unneback
`ifdef WB3_ARBITER_TYPE1
4448
`define MODULE wb3_arbiter_type1
4449 42 unneback
module `BASE`MODULE (
4450 40 unneback
`undef MODULE
4451 39 unneback
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
4452
    wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
4453
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
4454
    wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
4455
    wb_clk, wb_rst
4456
);
4457
 
4458
parameter nr_of_ports = 3;
4459
parameter adr_size = 26;
4460
parameter adr_lo   = 2;
4461
parameter dat_size = 32;
4462
parameter sel_size = dat_size/8;
4463
 
4464
localparam aw = (adr_size - adr_lo) * nr_of_ports;
4465
localparam dw = dat_size * nr_of_ports;
4466
localparam sw = sel_size * nr_of_ports;
4467
localparam cw = 3 * nr_of_ports;
4468
localparam bw = 2 * nr_of_ports;
4469
 
4470
input  [dw-1:0] wbm_dat_o;
4471
input  [aw-1:0] wbm_adr_o;
4472
input  [sw-1:0] wbm_sel_o;
4473
input  [cw-1:0] wbm_cti_o;
4474
input  [bw-1:0] wbm_bte_o;
4475
input  [nr_of_ports-1:0] wbm_we_o, wbm_stb_o, wbm_cyc_o;
4476
output [dw-1:0] wbm_dat_i;
4477
output [nr_of_ports-1:0] wbm_ack_i, wbm_err_i, wbm_rty_i;
4478
 
4479
output [dat_size-1:0] wbs_dat_i;
4480
output [adr_size-1:adr_lo] wbs_adr_i;
4481
output [sel_size-1:0] wbs_sel_i;
4482
output [2:0] wbs_cti_i;
4483
output [1:0] wbs_bte_i;
4484
output wbs_we_i, wbs_stb_i, wbs_cyc_i;
4485
input  [dat_size-1:0] wbs_dat_o;
4486
input  wbs_ack_o, wbs_err_o, wbs_rty_o;
4487
 
4488
input wb_clk, wb_rst;
4489
 
4490 44 unneback
reg  [nr_of_ports-1:0] select;
4491 39 unneback
wire [nr_of_ports-1:0] state;
4492
wire [nr_of_ports-1:0] eoc; // end-of-cycle
4493
wire [nr_of_ports-1:0] sel;
4494
wire idle;
4495
 
4496
genvar i;
4497
 
4498
assign idle = !(|state);
4499
 
4500
generate
4501
if (nr_of_ports == 2) begin
4502
 
4503
    wire [2:0] wbm1_cti_o, wbm0_cti_o;
4504
 
4505
    assign {wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
4506
 
4507 44 unneback
    //assign select = (idle) ? {wbm_cyc_o[1],!wbm_cyc_o[1] & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
4508
 
4509
    always @ (idle or wbm_cyc_o)
4510
    if (idle)
4511
        casex (wbm_cyc_o)
4512
        2'b1x : select = 2'b10;
4513
        2'b01 : select = 2'b01;
4514
        default : select = {nr_of_ports{1'b0}};
4515
        endcase
4516
    else
4517
        select = {nr_of_ports{1'b0}};
4518
 
4519 39 unneback
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
4520
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
4521
 
4522
end
4523
endgenerate
4524
 
4525
generate
4526
if (nr_of_ports == 3) begin
4527
 
4528
    wire [2:0] wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
4529
 
4530
    assign {wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
4531
 
4532 44 unneback
    always @ (idle or wbm_cyc_o)
4533
    if (idle)
4534
        casex (wbm_cyc_o)
4535
        3'b1xx : select = 3'b100;
4536
        3'b01x : select = 3'b010;
4537
        3'b001 : select = 3'b001;
4538
        default : select = {nr_of_ports{1'b0}};
4539
        endcase
4540
    else
4541
        select = {nr_of_ports{1'b0}};
4542
 
4543
//    assign select = (idle) ? {wbm_cyc_o[2],!wbm_cyc_o[2] & wbm_cyc_o[1],wbm_cyc_o[2:1]==2'b00 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
4544 39 unneback
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
4545
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
4546
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
4547
 
4548
end
4549
endgenerate
4550
 
4551
generate
4552 44 unneback
if (nr_of_ports == 4) begin
4553
 
4554
    wire [2:0] wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
4555
 
4556
    assign {wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
4557
 
4558
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
4559
 
4560
    always @ (idle or wbm_cyc_o)
4561
    if (idle)
4562
        casex (wbm_cyc_o)
4563
        4'b1xxx : select = 4'b1000;
4564
        4'b01xx : select = 4'b0100;
4565
        4'b001x : select = 4'b0010;
4566
        4'b0001 : select = 4'b0001;
4567
        default : select = {nr_of_ports{1'b0}};
4568
        endcase
4569
    else
4570
        select = {nr_of_ports{1'b0}};
4571
 
4572
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
4573
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
4574
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
4575
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
4576
 
4577
end
4578
endgenerate
4579
 
4580
generate
4581
if (nr_of_ports == 5) begin
4582
 
4583
    wire [2:0] wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
4584
 
4585
    assign {wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
4586
 
4587
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
4588
 
4589
    always @ (idle or wbm_cyc_o)
4590
    if (idle)
4591
        casex (wbm_cyc_o)
4592
        5'b1xxxx : select = 5'b10000;
4593
        5'b01xxx : select = 5'b01000;
4594
        5'b001xx : select = 5'b00100;
4595
        5'b0001x : select = 5'b00010;
4596
        5'b00001 : select = 5'b00001;
4597
        default : select = {nr_of_ports{1'b0}};
4598
        endcase
4599
    else
4600
        select = {nr_of_ports{1'b0}};
4601
 
4602
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
4603
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
4604
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
4605
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
4606
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
4607
 
4608
end
4609
endgenerate
4610
 
4611
generate
4612 39 unneback
for (i=0;i<nr_of_ports;i=i+1) begin
4613 42 unneback
`define MODULE spr
4614
    `BASE`MODULE sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));
4615
`undef MODULE
4616 39 unneback
end
4617
endgenerate
4618
 
4619
    assign sel = select | state;
4620
 
4621 40 unneback
`define MODULE mux_andor
4622
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i));
4623
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(adr_size-adr_lo)) mux1 ( .a(wbm_adr_o), .sel(sel), .dout(wbs_adr_i));
4624
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(sel_size)) mux2 ( .a(wbm_sel_o), .sel(sel), .dout(wbs_sel_i));
4625
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(3)) mux3 ( .a(wbm_cti_o), .sel(sel), .dout(wbs_cti_i));
4626
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(2)) mux4 ( .a(wbm_bte_o), .sel(sel), .dout(wbs_bte_i));
4627
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux5 ( .a(wbm_we_o), .sel(sel), .dout(wbs_we_i));
4628
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux6 ( .a(wbm_stb_o), .sel(sel), .dout(wbs_stb_i));
4629
`undef MODULE
4630 39 unneback
    assign wbs_cyc_i = |sel;
4631
 
4632
    assign wbm_dat_i = {nr_of_ports{wbs_dat_o}};
4633
    assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
4634
    assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
4635
    assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
4636
 
4637
endmodule
4638 40 unneback
`endif
4639 39 unneback
 
4640 49 unneback
`ifdef WB_B4_RAM_BE
4641
// WB RAM with byte enable
4642
`define MODULE wb_b4_ram_be
4643
module `BASE`MODULE (
4644
`undef MODULE
4645
    wb_dat_i, wb_adr_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
4646
    wb_dat_o, stall_o, wb_ack_o, wb_clk, wb_rst);
4647
 
4648
    parameter dat_width = 32;
4649
    parameter adr_width = 8;
4650
 
4651
input [dat_width-1:0] wb_dat_i;
4652
input [adr_width-1:0] wb_adr_i;
4653
input [dat_width/8-1:0] wb_sel_i;
4654
input wb_we_i, wb_stb_i, wb_cyc_i;
4655
output [dat_width-1:0] wb_dat_o;
4656 51 unneback
reg [dat_width-1:0] wb_dat_o;
4657 49 unneback
output stall_o;
4658
output wb_ack_o;
4659
reg wb_ack_o;
4660
input wb_clk, wb_rst;
4661
 
4662
generate
4663
if (dat_width==32) begin
4664 51 unneback
reg [7:0] ram3 [1<<(adr_width-2)-1:0];
4665
reg [7:0] ram2 [1<<(adr_width-2)-1:0];
4666
reg [7:0] ram1 [1<<(adr_width-2)-1:0];
4667
reg [7:0] ram0 [1<<(adr_width-2)-1:0];
4668 49 unneback
    always @ (posedge wb_clk)
4669
    begin
4670 50 unneback
        if (wb_sel_i[3]) ram3[wb_adr_i[adr_width-1:2]] <= wb_dat_i[31:24];
4671
        if (wb_sel_i[2]) ram2[wb_adr_i[adr_width-1:2]] <= wb_dat_i[23:16];
4672
        if (wb_sel_i[1]) ram1[wb_adr_i[adr_width-1:2]] <= wb_dat_i[15:8];
4673
        if (wb_sel_i[0]) ram0[wb_adr_i[adr_width-1:2]] <= wb_dat_i[7:0];
4674 51 unneback
        wb_dat_o <= {ram3[wb_adr_i[adr_width-1:2]],ram2[wb_adr_i[adr_width-1:2]],ram1[wb_adr_i[adr_width-1:2]],ram0[wb_adr_i[adr_width-1:2]]};
4675 49 unneback
    end
4676
end
4677
endgenerate
4678
 
4679
endmodule
4680
`endif
4681
 
4682 48 unneback
`ifdef WB_B4_ROM
4683
// WB ROM
4684
`define MODULE wb_b4_rom
4685
module `BASE`MODULE (
4686
`undef MODULE
4687
    wb_adr_i, wb_stb_i, wb_cyc_i,
4688
    wb_dat_o, stall_o, wb_ack_o, wb_clk, wb_rst);
4689
 
4690
    parameter dat_width = 32;
4691
    parameter dat_default = 32'h15000000;
4692
    parameter adr_width = 32;
4693
 
4694
/*
4695
`ifndef ROM
4696
`define ROM "rom.v"
4697
`endif
4698
*/
4699
    input [adr_width-1:2]   wb_adr_i;
4700
    input                   wb_stb_i;
4701
    input                   wb_cyc_i;
4702
    output [dat_width-1:0]  wb_dat_o;
4703
    reg [dat_width-1:0]     wb_dat_o;
4704
    output                  wb_ack_o;
4705
    reg                     wb_ack_o;
4706
    output                  stall_o;
4707
    input                   wb_clk;
4708
    input                   wb_rst;
4709
 
4710
always @ (posedge wb_clk or posedge wb_rst)
4711
    if (wb_rst)
4712
        wb_dat_o <= {dat_width{1'b0}};
4713
    else
4714
         case (wb_adr_i[adr_width-1:2])
4715
`ifdef ROM
4716
`include `ROM
4717
`endif
4718
           default:
4719
             wb_dat_o <= dat_default;
4720
 
4721
         endcase // case (wb_adr_i)
4722
 
4723
 
4724
always @ (posedge wb_clk or posedge wb_rst)
4725
    if (wb_rst)
4726
        wb_ack_o <= 1'b0;
4727
    else
4728
        wb_ack_o <= wb_stb_i & wb_cyc_i;
4729
 
4730
assign stall_o = 1'b0;
4731
 
4732
endmodule
4733
`endif
4734
 
4735
 
4736 40 unneback
`ifdef WB_BOOT_ROM
4737 17 unneback
// WB ROM
4738 40 unneback
`define MODULE wb_boot_rom
4739
module `BASE`MODULE (
4740
`undef MODULE
4741 17 unneback
    wb_adr_i, wb_stb_i, wb_cyc_i,
4742 18 unneback
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
4743 17 unneback
 
4744 18 unneback
    parameter adr_hi = 31;
4745
    parameter adr_lo = 28;
4746
    parameter adr_sel = 4'hf;
4747
    parameter addr_width = 5;
4748 33 unneback
/*
4749 17 unneback
`ifndef BOOT_ROM
4750
`define BOOT_ROM "boot_rom.v"
4751
`endif
4752 33 unneback
*/
4753 18 unneback
    input [adr_hi:2]    wb_adr_i;
4754
    input               wb_stb_i;
4755
    input               wb_cyc_i;
4756
    output [31:0]        wb_dat_o;
4757
    output              wb_ack_o;
4758
    output              hit_o;
4759
    input               wb_clk;
4760
    input               wb_rst;
4761
 
4762
    wire hit;
4763
    reg [31:0] wb_dat;
4764
    reg wb_ack;
4765
 
4766
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
4767 17 unneback
 
4768
always @ (posedge wb_clk or posedge wb_rst)
4769
    if (wb_rst)
4770 18 unneback
        wb_dat <= 32'h15000000;
4771 17 unneback
    else
4772 18 unneback
         case (wb_adr_i[addr_width-1:2])
4773 33 unneback
`ifdef BOOT_ROM
4774 17 unneback
`include `BOOT_ROM
4775 33 unneback
`endif
4776 17 unneback
           /*
4777
            // Zero r0 and jump to 0x00000100
4778 18 unneback
 
4779
            1 : wb_dat <= 32'hA8200000;
4780
            2 : wb_dat <= 32'hA8C00100;
4781
            3 : wb_dat <= 32'h44003000;
4782
            4 : wb_dat <= 32'h15000000;
4783 17 unneback
            */
4784
           default:
4785 18 unneback
             wb_dat <= 32'h00000000;
4786 17 unneback
 
4787
         endcase // case (wb_adr_i)
4788
 
4789
 
4790
always @ (posedge wb_clk or posedge wb_rst)
4791
    if (wb_rst)
4792 18 unneback
        wb_ack <= 1'b0;
4793 17 unneback
    else
4794 18 unneback
        wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
4795 17 unneback
 
4796 18 unneback
assign hit_o = hit;
4797
assign wb_dat_o = wb_dat & {32{wb_ack}};
4798
assign wb_ack_o = wb_ack;
4799
 
4800 17 unneback
endmodule
4801 40 unneback
`endif
4802 32 unneback
 
4803 40 unneback
`ifdef WB_DPRAM
4804
`define MODULE wb_dpram
4805
module `BASE`MODULE (
4806
`undef MODULE
4807 32 unneback
        // wishbone slave side a
4808
        wbsa_dat_i, wbsa_adr_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o,
4809
        wbsa_clk, wbsa_rst,
4810
        // wishbone slave side a
4811
        wbsb_dat_i, wbsb_adr_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o,
4812
        wbsb_clk, wbsb_rst);
4813
 
4814
parameter data_width = 32;
4815
parameter addr_width = 8;
4816
 
4817
parameter dat_o_mask_a = 1;
4818
parameter dat_o_mask_b = 1;
4819
 
4820
input [31:0] wbsa_dat_i;
4821
input [addr_width-1:2] wbsa_adr_i;
4822
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
4823
output [31:0] wbsa_dat_o;
4824
output wbsa_ack_o;
4825
input wbsa_clk, wbsa_rst;
4826
 
4827
input [31:0] wbsb_dat_i;
4828
input [addr_width-1:2] wbsb_adr_i;
4829
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
4830
output [31:0] wbsb_dat_o;
4831
output wbsb_ack_o;
4832
input wbsb_clk, wbsb_rst;
4833
 
4834
wire wbsa_dat_tmp, wbsb_dat_tmp;
4835
 
4836 40 unneback
`define MODULE dpram_2r2w
4837
`BASE`MODULE # (
4838
`undef MODULE
4839 33 unneback
    .data_width(data_width), .addr_width(addr_width) )
4840 32 unneback
dpram0(
4841
    .d_a(wbsa_dat_i),
4842
    .q_a(wbsa_dat_tmp),
4843
    .adr_a(wbsa_adr_i),
4844
    .we_a(wbsa_we_i),
4845
    .clk_a(wbsa_clk),
4846
    .d_b(wbsb_dat_i),
4847
    .q_b(wbsb_dat_tmp),
4848
    .adr_b(wbsb_adr_i),
4849
    .we_b(wbsb_we_i),
4850
    .clk_b(wbsb_clk) );
4851
 
4852 33 unneback
generate if (dat_o_mask_a==1)
4853 32 unneback
    assign wbsa_dat_o = wbsa_dat_tmp & {data_width{wbsa_ack_o}};
4854
endgenerate
4855 33 unneback
generate if (dat_o_mask_a==0)
4856 32 unneback
    assign wbsa_dat_o = wbsa_dat_tmp;
4857
endgenerate
4858
 
4859 33 unneback
generate if (dat_o_mask_b==1)
4860 32 unneback
    assign wbsb_dat_o = wbsb_dat_tmp & {data_width{wbsb_ack_o}};
4861
endgenerate
4862 33 unneback
generate if (dat_o_mask_b==0)
4863 32 unneback
    assign wbsb_dat_o = wbsb_dat_tmp;
4864
endgenerate
4865
 
4866 40 unneback
`define MODULE spr
4867
`BASE`MODULE ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
4868
`BASE`MODULE ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
4869
`undef MODULE
4870 32 unneback
 
4871
endmodule
4872 40 unneback
`endif
4873 18 unneback
//////////////////////////////////////////////////////////////////////
4874
////                                                              ////
4875
////  Arithmetic functions                                        ////
4876
////                                                              ////
4877
////  Description                                                 ////
4878
////  Arithmetic functions for ALU and DSP                        ////
4879
////                                                              ////
4880
////                                                              ////
4881
////  To Do:                                                      ////
4882
////   -                                                          ////
4883
////                                                              ////
4884
////  Author(s):                                                  ////
4885
////      - Michael Unneback, unneback@opencores.org              ////
4886
////        ORSoC AB                                              ////
4887
////                                                              ////
4888
//////////////////////////////////////////////////////////////////////
4889
////                                                              ////
4890
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
4891
////                                                              ////
4892
//// This source file may be used and distributed without         ////
4893
//// restriction provided that this copyright statement is not    ////
4894
//// removed from the file and that any derivative work contains  ////
4895
//// the original copyright notice and the associated disclaimer. ////
4896
////                                                              ////
4897
//// This source file is free software; you can redistribute it   ////
4898
//// and/or modify it under the terms of the GNU Lesser General   ////
4899
//// Public License as published by the Free Software Foundation; ////
4900
//// either version 2.1 of the License, or (at your option) any   ////
4901
//// later version.                                               ////
4902
////                                                              ////
4903
//// This source is distributed in the hope that it will be       ////
4904
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
4905
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
4906
//// PURPOSE.  See the GNU Lesser General Public License for more ////
4907
//// details.                                                     ////
4908
////                                                              ////
4909
//// You should have received a copy of the GNU Lesser General    ////
4910
//// Public License along with this source; if not, download it   ////
4911
//// from http://www.opencores.org/lgpl.shtml                     ////
4912
////                                                              ////
4913
//////////////////////////////////////////////////////////////////////
4914
 
4915 40 unneback
`ifdef MULTS
4916 18 unneback
// signed multiplication
4917 40 unneback
`define MODULE mults
4918
module `BASE`MODULE (a,b,p);
4919
`undef MODULE
4920 18 unneback
parameter operand_a_width = 18;
4921
parameter operand_b_width = 18;
4922
parameter result_hi = 35;
4923
parameter result_lo = 0;
4924
input [operand_a_width-1:0] a;
4925
input [operand_b_width-1:0] b;
4926
output [result_hi:result_lo] p;
4927
wire signed [operand_a_width-1:0] ai;
4928
wire signed [operand_b_width-1:0] bi;
4929
wire signed [operand_a_width+operand_b_width-1:0] result;
4930
 
4931
    assign ai = a;
4932
    assign bi = b;
4933
    assign result = ai * bi;
4934
    assign p = result[result_hi:result_lo];
4935
 
4936
endmodule
4937 40 unneback
`endif
4938
`ifdef MULTS18X18
4939
`define MODULE mults18x18
4940
module `BASE`MODULE (a,b,p);
4941
`undef MODULE
4942 18 unneback
input [17:0] a,b;
4943
output [35:0] p;
4944
vl_mult
4945
    # (.operand_a_width(18), .operand_b_width(18))
4946
    mult0 (.a(a), .b(b), .p(p));
4947
endmodule
4948 40 unneback
`endif
4949 18 unneback
 
4950 40 unneback
`ifdef MULT
4951
`define MODULE mult
4952 18 unneback
// unsigned multiplication
4953 40 unneback
module `BASE`MODULE (a,b,p);
4954
`undef MODULE
4955 18 unneback
parameter operand_a_width = 18;
4956
parameter operand_b_width = 18;
4957
parameter result_hi = 35;
4958
parameter result_lo = 0;
4959
input [operand_a_width-1:0] a;
4960
input [operand_b_width-1:0] b;
4961
output [result_hi:result_hi] p;
4962
 
4963
wire [operand_a_width+operand_b_width-1:0] result;
4964
 
4965
    assign result = a * b;
4966
    assign p = result[result_hi:result_lo];
4967
 
4968
endmodule
4969 40 unneback
`endif
4970 18 unneback
 
4971 40 unneback
`ifdef SHIFT_UNIT_32
4972
`define MODULE shift_unit_32
4973 18 unneback
// shift unit
4974
// supporting the following shift functions
4975
//   SLL
4976
//   SRL
4977
//   SRA
4978
`define SHIFT_UNIT_MULT # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7))
4979 40 unneback
module `BASE`MODULE( din, s, dout, opcode);
4980
`undef MODULE
4981 18 unneback
input [31:0] din; // data in operand
4982
input [4:0] s; // shift operand
4983
input [1:0] opcode;
4984
output [31:0] dout;
4985
 
4986
parameter opcode_sll = 2'b00;
4987
//parameter opcode_srl = 2'b01;
4988
parameter opcode_sra = 2'b10;
4989
//parameter opcode_ror = 2'b11;
4990
 
4991
wire sll, sra;
4992
assign sll = opcode == opcode_sll;
4993
assign sra = opcode == opcode_sra;
4994
 
4995
wire [15:1] s1;
4996
wire [3:0] sign;
4997
wire [7:0] tmp [0:3];
4998
 
4999
// first stage is multiplier based
5000
// shift operand as fractional 8.7
5001
assign s1[15] = sll & s[2:0]==3'd7;
5002
assign s1[14] = sll & s[2:0]==3'd6;
5003
assign s1[13] = sll & s[2:0]==3'd5;
5004
assign s1[12] = sll & s[2:0]==3'd4;
5005
assign s1[11] = sll & s[2:0]==3'd3;
5006
assign s1[10] = sll & s[2:0]==3'd2;
5007
assign s1[ 9] = sll & s[2:0]==3'd1;
5008
assign s1[ 8] = s[2:0]==3'd0;
5009
assign s1[ 7] = !sll & s[2:0]==3'd1;
5010
assign s1[ 6] = !sll & s[2:0]==3'd2;
5011
assign s1[ 5] = !sll & s[2:0]==3'd3;
5012
assign s1[ 4] = !sll & s[2:0]==3'd4;
5013
assign s1[ 3] = !sll & s[2:0]==3'd5;
5014
assign s1[ 2] = !sll & s[2:0]==3'd6;
5015
assign s1[ 1] = !sll & s[2:0]==3'd7;
5016
 
5017
assign sign[3] = din[31] & sra;
5018
assign sign[2] = sign[3] & (&din[31:24]);
5019
assign sign[1] = sign[2] & (&din[23:16]);
5020
assign sign[0] = sign[1] & (&din[15:8]);
5021 40 unneback
`define MODULE mults
5022
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte3 ( .a({sign[3], {8{sign[3]}},din[31:24], din[23:16]}), .b({1'b0,s1}), .p(tmp[3]));
5023
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte2 ( .a({sign[2], din[31:24]  ,din[23:16],  din[15:8]}), .b({1'b0,s1}), .p(tmp[2]));
5024
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte1 ( .a({sign[1], din[23:16]  ,din[15:8],   din[7:0]}), .b({1'b0,s1}), .p(tmp[1]));
5025
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte0 ( .a({sign[0], din[15:8]   ,din[7:0],    8'h00}),      .b({1'b0,s1}), .p(tmp[0]));
5026
`undef MODULE
5027 18 unneback
// second stage is multiplexer based
5028
// shift on byte level
5029
 
5030
// mux byte 3
5031
assign dout[31:24] = (s[4:3]==2'b00) ? tmp[3] :
5032
                     (sll & s[4:3]==2'b01) ? tmp[2] :
5033
                     (sll & s[4:3]==2'b10) ? tmp[1] :
5034
                     (sll & s[4:3]==2'b11) ? tmp[0] :
5035
                     {8{sign[3]}};
5036
 
5037
// mux byte 2
5038
assign dout[23:16] = (s[4:3]==2'b00) ? tmp[2] :
5039
                     (sll & s[4:3]==2'b01) ? tmp[1] :
5040
                     (sll & s[4:3]==2'b10) ? tmp[0] :
5041
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
5042
                     (s[4:3]==2'b01) ? tmp[3] :
5043
                     {8{sign[3]}};
5044
 
5045
// mux byte 1
5046
assign dout[15:8]  = (s[4:3]==2'b00) ? tmp[1] :
5047
                     (sll & s[4:3]==2'b01) ? tmp[0] :
5048
                     (sll & s[4:3]==2'b10) ? {8{1'b0}} :
5049
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
5050
                     (s[4:3]==2'b01) ? tmp[2] :
5051
                     (s[4:3]==2'b10) ? tmp[3] :
5052
                     {8{sign[3]}};
5053
 
5054
// mux byte 0
5055
assign dout[7:0]   = (s[4:3]==2'b00) ? tmp[0] :
5056
                     (sll) ?  {8{1'b0}}:
5057
                     (s[4:3]==2'b01) ? tmp[1] :
5058
                     (s[4:3]==2'b10) ? tmp[2] :
5059
                     tmp[3];
5060
 
5061
endmodule
5062 40 unneback
`endif
5063 18 unneback
 
5064 40 unneback
`ifdef LOGIC_UNIT
5065 18 unneback
// logic unit
5066
// supporting the following logic functions
5067
//    a and b
5068
//    a or  b
5069
//    a xor b
5070
//    not b
5071 40 unneback
`define MODULE logic_unit
5072
module `BASE`MODULE( a, b, result, opcode);
5073
`undef MODULE
5074 18 unneback
parameter width = 32;
5075
parameter opcode_and = 2'b00;
5076
parameter opcode_or  = 2'b01;
5077
parameter opcode_xor = 2'b10;
5078
input [width-1:0] a,b;
5079
output [width-1:0] result;
5080
input [1:0] opcode;
5081
 
5082
assign result = (opcode==opcode_and) ? a & b :
5083
                (opcode==opcode_or)  ? a | b :
5084
                (opcode==opcode_xor) ? a ^ b :
5085
                b;
5086
 
5087
endmodule
5088 48 unneback
`endif
5089 18 unneback
 
5090 48 unneback
`ifdef ARITH_UNIT
5091
`define MODULE arith_unit
5092
module `BASE`MODULE ( a, b, c_in, add_sub, sign, result, c_out, z, ovfl);
5093
`undef MODULE
5094 18 unneback
parameter width = 32;
5095
parameter opcode_add = 1'b0;
5096
parameter opcode_sub = 1'b1;
5097
input [width-1:0] a,b;
5098
input c_in, add_sub, sign;
5099
output [width-1:0] result;
5100
output c_out, z, ovfl;
5101
 
5102
assign {c_out,result} = {(a[width-1] & sign),a} + ({a[width-1] & sign,b} ^ {(width+1){(add_sub==opcode_sub)}}) + {{(width-1){1'b0}},(c_in | (add_sub==opcode_sub))};
5103
assign z = (result=={width{1'b0}});
5104
assign ovfl = ( a[width-1] &  b[width-1] & ~result[width-1]) |
5105
               (~a[width-1] & ~b[width-1] &  result[width-1]);
5106
endmodule
5107 40 unneback
`endif
5108 48 unneback
 
5109
`ifdef COUNT_UNIT
5110
`define MODULE count_unit
5111
module `BASE`MODULE (din, dout, opcode);
5112
`undef MODULE
5113
parameter width = 32;
5114
input [width-1:0] din;
5115
output [width-1:0] dout;
5116
input opcode;
5117
 
5118
integer i;
5119
reg [width/32+3:0] ff1, fl1;
5120
 
5121
always @(din) begin
5122
    ff1 = 0; i = 0;
5123
    while (din[i] == 0 && i < width) begin // complex condition
5124
        ff1 = ff1 + 1;
5125
        i = i + 1;
5126
    end
5127
end
5128
 
5129
always @(din) begin
5130
    fl1 = width; i = width-1;
5131
    while (din[i] == 0 && i >= width) begin // complex condition
5132
        fl1 = fl1 - 1;
5133
        i = i - 1;
5134
    end
5135
end
5136
 
5137
generate
5138
if (width==32) begin
5139
    assign dout = (!opcode) ? {{58{1'b0}}, ff1} : {{58{1'b0}}, fl1};
5140
end
5141
endgenerate
5142
generate
5143
if (width==64) begin
5144
    assign dout = (!opcode) ? {{27{1'b0}}, ff1} : {{27{1'b0}}, fl1};
5145
end
5146
endgenerate
5147
 
5148
endmodule
5149
`endif
5150
 
5151
`ifdef EXT_UNIT
5152
`define MODULE ext_unit
5153
module `BASE`MODULE ( a, b, F, result, opcode);
5154
`undef MODULE
5155
parameter width = 32;
5156
input [width-1:0] a, b;
5157
input F;
5158
output reg [width-1:0] result;
5159
input [2:0] opcode;
5160
 
5161
generate
5162
if (width==32) begin
5163
always @ (a or b or F or opcode)
5164
begin
5165
    case (opcode)
5166
    3'b000: result = {{24{1'b0}},a[7:0]};
5167
    3'b001: result = {{24{a[7]}},a[7:0]};
5168
    3'b010: result = {{16{1'b0}},a[7:0]};
5169
    3'b011: result = {{16{a[15]}},a[15:0]};
5170
    3'b110: result = (F) ? a : b;
5171
    default: result = {b[15:0],16'h0000};
5172
    endcase
5173
end
5174
end
5175
endgenerate
5176
 
5177
generate
5178
if (width==64) begin
5179
always @ (a or b or F or opcode)
5180
begin
5181
    case (opcode)
5182
    3'b000: result = {{56{1'b0}},a[7:0]};
5183
    3'b001: result = {{56{a[7]}},a[7:0]};
5184
    3'b010: result = {{48{1'b0}},a[7:0]};
5185
    3'b011: result = {{48{a[15]}},a[15:0]};
5186
    3'b110: result = (SR.F) ? a : b;
5187
    default: result = {32'h00000000,b[15:0],16'h0000};
5188
    endcase
5189
end
5190
end
5191
endgenerate
5192
endmodule
5193
`endif

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