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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Blame information for rev 60

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Line No. Rev Author Line
1 40 unneback
`ifndef BASE
2
`define BASE vl_
3
`endif
4
 
5 60 unneback
// default SYN_KEEP definition
6
`define SYN_KEEP /*synthesis syn_keep = 1*/
7
 
8 44 unneback
`ifdef ACTEL
9 60 unneback
`undef SYN_KEEP
10 44 unneback
`define SYN_KEEP /*synthesis syn_keep = 1*/
11
`endif
12
 
13 40 unneback
`ifdef ALL
14
 
15
`define GBUF
16
`define SYNC_RST
17
`define PLL
18
 
19
`define MULTS
20
`define MULTS18X18
21
`define MULT
22
`define SHIFT_UNIT_32
23
`define LOGIC_UNIT
24
 
25
`define CNT_SHREG_WRAP
26
`define CNT_SHREG_CE_WRAP
27
`define CNT_SHREG_CE_CLEAR
28
`define CNT_SHREG_CE_CLEAR_WRAP
29
 
30
`define MUX_ANDOR
31
`define MUX2_ANDOR
32
`define MUX3_ANDOR
33
`define MUX4_ANDOR
34
`define MUX5_ANDOR
35
`define MUX6_ANDOR
36 43 unneback
`define PARITY
37 40 unneback
 
38
`define ROM_INIT
39
`define RAM
40
`define RAM_BE
41
`define DPRAM_1R1W
42
`define DPRAM_2R1W
43
`define DPRAM_2R2W
44
`define FIFO_1R1W_FILL_LEVEL_SYNC
45
`define FIFO_2R2W_SYNC_SIMPLEX
46
`define FIFO_CMP_ASYNC
47
`define FIFO_1R1W_ASYNC
48
`define FIFO_2R2W_ASYNC
49
`define FIFO_2R2W_ASYNC_SIMPLEX
50 48 unneback
`define REG_FILE
51 40 unneback
 
52
`define DFF
53
`define DFF_ARRAY
54
`define DFF_CE
55
`define DFF_CE_CLEAR
56
`define DF_CE_SET
57
`define SPR
58
`define SRP
59
`define DFF_SR
60
`define LATCH
61
`define SHREG
62
`define SHREG_CE
63
`define DELAY
64
`define DELAY_EMPTYFLAG
65
 
66
`define WB3WB3_BRIDGE
67
`define WB3_ARBITER_TYPE1
68 59 unneback
`define WB_B3_RAM_BE
69 49 unneback
`define WB_B4_RAM_BE
70 48 unneback
`define WB_B4_ROM
71 40 unneback
`define WB_BOOT_ROM
72
`define WB_DPRAM
73
 
74 44 unneback
`define IO_DFF_OE
75
`define O_DFF
76
 
77 40 unneback
`endif
78
 
79
`ifdef PLL
80
`ifndef SYNC_RST
81
`define SYNC_RST
82
`endif
83
`endif
84
 
85
`ifdef SYNC_RST
86
`ifndef GBUF
87
`define GBUF
88
`endif
89
`endif
90
 
91
`ifdef WB_DPRAM
92
`ifndef DPRAM_2R2W
93
`define DPRAM_2R2W
94
`endif
95
`ifndef SPR
96
`define SPR
97
`endif
98
`endif
99
 
100
`ifdef WB3_ARBITER_TYPE1
101 42 unneback
`ifndef SPR
102
`define SPR
103
`endif
104 40 unneback
`ifndef MUX_ANDOR
105
`define MUX_ANDOR
106
`endif
107
`endif
108
 
109
`ifdef WB3WB3_BRIDGE
110
`ifndef CNT_SHREG_CE_CLEAR
111
`define CNT_SHREG_CE_CLEAR
112
`endif
113
`ifndef DFF
114
`define DFF
115
`endif
116
`ifndef DFF_CE
117
`define DFF_CE
118
`endif
119
`ifndef CNT_SHREG_CE_CLEAR
120
`define CNT_SHREG_CE_CLEAR
121
`endif
122
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
123
`define FIFO_2R2W_ASYNC_SIMPLEX
124
`endif
125
`endif
126
 
127
`ifdef MULTS18X18
128
`ifndef MULTS
129
`define MULTS
130
`endif
131
`endif
132
 
133
`ifdef SHIFT_UNIT_32
134
`ifndef MULTS
135
`define MULTS
136
`endif
137
`endif
138
 
139
`ifdef MUX2_ANDOR
140
`ifndef MUX_ANDOR
141
`define MUX_ANDOR
142
`endif
143
`endif
144
 
145
`ifdef MUX3_ANDOR
146
`ifndef MUX_ANDOR
147
`define MUX_ANDOR
148
`endif
149
`endif
150
 
151
`ifdef MUX4_ANDOR
152
`ifndef MUX_ANDOR
153
`define MUX_ANDOR
154
`endif
155
`endif
156
 
157
`ifdef MUX5_ANDOR
158
`ifndef MUX_ANDOR
159
`define MUX_ANDOR
160
`endif
161
`endif
162
 
163
`ifdef MUX6_ANDOR
164
`ifndef MUX_ANDOR
165
`define MUX_ANDOR
166
`endif
167
`endif
168
 
169
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
170
`ifndef CNT_BIN_CE
171
`define CNT_BIN_CE
172
`endif
173
`ifndef DPRAM_1R1W
174
`define DPRAM_1R1W
175
`endif
176
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
177
`define CNT_BIN_CE_REW_Q_ZQ_L1
178
`endif
179
`endif
180
 
181
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
182
`ifndef CNT_LFSR_CE
183
`define CNT_LFSR_CE
184
`endif
185
`ifndef DPRAM_2R2W
186
`define DPRAM_2R2W
187
`endif
188
`ifndef CNT_BIN_CE_REW_ZQ_L1
189
`define CNT_BIN_CE_REW_ZQ_L1
190
`endif
191
`endif
192
 
193
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
194
`ifndef CNT_GRAY_CE_BIN
195
`define CNT_GRAY_CE_BIN
196
`endif
197
`ifndef DPRAM_2R2W
198
`define DPRAM_2R2W
199
`endif
200
`ifndef FIFO_CMP_ASYNC
201
`define FIFO_CMP_ASYNC
202
`endif
203
`endif
204
 
205
`ifdef FIFO_2R2W_ASYNC
206
`ifndef FIFO_1R1W_ASYNC
207
`define FIFO_1R1W_ASYNC
208
`endif
209
`endif
210
 
211
`ifdef FIFO_1R1W_ASYNC
212
`ifndef CNT_GRAY_CE_BIN
213
`define CNT_GRAY_CE_BIN
214
`endif
215
`ifndef DPRAM_1R1W
216
`define DPRAM_1R1W
217
`endif
218
`ifndef FIFO_CMP_ASYNC
219
`define FIFO_CMP_ASYNC
220
`endif
221
`endif
222
 
223
`ifdef FIFO_CMP_ASYNC
224
`ifndef DFF_SR
225
`define DFF_SR
226
`endif
227
`ifndef DFF
228
`define DFF
229
`endif
230
`endif
231 48 unneback
 
232
`ifdef REG_FILE
233
`ifndef DPRAM_1R1W
234
`define DPRAM_1R1W
235
`endif
236
`endif
237 6 unneback
//////////////////////////////////////////////////////////////////////
238
////                                                              ////
239
////  Versatile library, clock and reset                          ////
240
////                                                              ////
241
////  Description                                                 ////
242
////  Logic related to clock and reset                            ////
243
////                                                              ////
244
////                                                              ////
245
////  To Do:                                                      ////
246
////   - add more different registers                             ////
247
////                                                              ////
248
////  Author(s):                                                  ////
249
////      - Michael Unneback, unneback@opencores.org              ////
250
////        ORSoC AB                                              ////
251
////                                                              ////
252
//////////////////////////////////////////////////////////////////////
253
////                                                              ////
254
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
255
////                                                              ////
256
//// This source file may be used and distributed without         ////
257
//// restriction provided that this copyright statement is not    ////
258
//// removed from the file and that any derivative work contains  ////
259
//// the original copyright notice and the associated disclaimer. ////
260
////                                                              ////
261
//// This source file is free software; you can redistribute it   ////
262
//// and/or modify it under the terms of the GNU Lesser General   ////
263
//// Public License as published by the Free Software Foundation; ////
264
//// either version 2.1 of the License, or (at your option) any   ////
265
//// later version.                                               ////
266
////                                                              ////
267
//// This source is distributed in the hope that it will be       ////
268
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
269
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
270
//// PURPOSE.  See the GNU Lesser General Public License for more ////
271
//// details.                                                     ////
272
////                                                              ////
273
//// You should have received a copy of the GNU Lesser General    ////
274
//// Public License along with this source; if not, download it   ////
275
//// from http://www.opencores.org/lgpl.shtml                     ////
276
////                                                              ////
277
//////////////////////////////////////////////////////////////////////
278
 
279 48 unneback
`ifdef ACTEL
280
`ifdef GBUF
281
`timescale 1 ns/100 ps
282 6 unneback
// Global buffer
283
// usage:
284
// use to enable global buffers for high fan out signals such as clock and reset
285
// Version: 8.4 8.4.0.33
286
module gbuf(GL,CLK);
287
output GL;
288
input  CLK;
289
 
290
    wire GND;
291
 
292
    GND GND_1_net(.Y(GND));
293
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
294
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
295
 
296
endmodule
297
`timescale 1 ns/1 ns
298 40 unneback
`define MODULE gbuf
299
module `BASE`MODULE ( i, o);
300
`undef MODULE
301 6 unneback
input i;
302
output o;
303
`ifdef SIM_GBUF
304
assign o=i;
305
`else
306
gbuf gbuf_i0 ( .CLK(i), .GL(o));
307
`endif
308
endmodule
309 40 unneback
`endif
310 33 unneback
 
311 6 unneback
`else
312 33 unneback
 
313 40 unneback
`ifdef ALTERA
314
`ifdef GBUF
315 21 unneback
//altera
316 40 unneback
`define MODULE gbuf
317
module `BASE`MODULE ( i, o);
318
`undef MODULE
319 33 unneback
input i;
320
output o;
321
assign o = i;
322
endmodule
323 40 unneback
`endif
324 33 unneback
 
325 6 unneback
`else
326
 
327 40 unneback
`ifdef GBUF
328 6 unneback
`timescale 1 ns/100 ps
329 40 unneback
`define MODULE
330
module `BASE`MODULE ( i, o);
331
`undef MODULE
332 6 unneback
input i;
333
output o;
334
assign o = i;
335
endmodule
336 40 unneback
`endif
337 6 unneback
`endif // ALTERA
338
`endif //ACTEL
339
 
340 40 unneback
`ifdef SYNC_RST
341 6 unneback
// sync reset
342 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
343 6 unneback
// output active high global reset sync with two DFFs 
344
`timescale 1 ns/100 ps
345 40 unneback
`define MODULE sync_rst
346
module `BASE`MODULE ( rst_n_i, rst_o, clk);
347
`undef MODULE
348 6 unneback
input rst_n_i, clk;
349
output rst_o;
350 18 unneback
reg [1:0] tmp;
351 6 unneback
always @ (posedge clk or negedge rst_n_i)
352
if (!rst_n_i)
353 17 unneback
        tmp <= 2'b11;
354 6 unneback
else
355 33 unneback
        tmp <= {1'b0,tmp[1]};
356 40 unneback
`define MODULE gbuf
357
`BASE`MODULE buf_i0( .i(tmp[0]), .o(rst_o));
358
`undef MODULE
359 6 unneback
endmodule
360 40 unneback
`endif
361 6 unneback
 
362 40 unneback
`ifdef PLL
363 6 unneback
// vl_pll
364
`ifdef ACTEL
365 32 unneback
///////////////////////////////////////////////////////////////////////////////
366 17 unneback
`timescale 1 ps/1 ps
367 40 unneback
`define MODULE pll
368
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
369
`undef MODULE
370 6 unneback
parameter index = 0;
371
parameter number_of_clk = 1;
372 17 unneback
parameter period_time_0 = 20000;
373
parameter period_time_1 = 20000;
374
parameter period_time_2 = 20000;
375
parameter lock_delay = 2000000;
376 6 unneback
input clk_i, rst_n_i;
377
output lock;
378
output reg [0:number_of_clk-1] clk_o;
379
output [0:number_of_clk-1] rst_o;
380
 
381
`ifdef SIM_PLL
382
 
383
always
384
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
385
 
386
generate if (number_of_clk > 1)
387
always
388
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
389
endgenerate
390
 
391
generate if (number_of_clk > 2)
392
always
393
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
394
endgenerate
395
 
396
genvar i;
397
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
398
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
399
end
400
endgenerate
401
 
402
assign #lock_delay lock = rst_n_i;
403
 
404
endmodule
405
`else
406
generate if (number_of_clk==1 & index==0) begin
407
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
408
end
409
endgenerate // index==0
410
generate if (number_of_clk==1 & index==1) begin
411
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
412
end
413
endgenerate // index==1
414
generate if (number_of_clk==1 & index==2) begin
415
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
416
end
417
endgenerate // index==2
418
generate if (number_of_clk==1 & index==3) begin
419
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
420
end
421
endgenerate // index==0
422
 
423
generate if (number_of_clk==2 & index==0) begin
424
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
425
end
426
endgenerate // index==0
427
generate if (number_of_clk==2 & index==1) begin
428
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
429
end
430
endgenerate // index==1
431
generate if (number_of_clk==2 & index==2) begin
432
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
433
end
434
endgenerate // index==2
435
generate if (number_of_clk==2 & index==3) begin
436
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
437
end
438
endgenerate // index==0
439
 
440
generate if (number_of_clk==3 & index==0) begin
441
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
442
end
443
endgenerate // index==0
444
generate if (number_of_clk==3 & index==1) begin
445
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
446
end
447
endgenerate // index==1
448
generate if (number_of_clk==3 & index==2) begin
449
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
450
end
451
endgenerate // index==2
452
generate if (number_of_clk==3 & index==3) begin
453
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
454
end
455
endgenerate // index==0
456
 
457
genvar i;
458
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
459 40 unneback
`define MODULE sync_rst
460
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
461
`undef MODULE
462 6 unneback
end
463
endgenerate
464
endmodule
465
`endif
466 32 unneback
///////////////////////////////////////////////////////////////////////////////
467 6 unneback
 
468
`else
469
 
470 32 unneback
///////////////////////////////////////////////////////////////////////////////
471 6 unneback
`ifdef ALTERA
472
 
473 32 unneback
`timescale 1 ps/1 ps
474 40 unneback
`define MODULE pll
475
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
476
`undef MODULE
477 32 unneback
parameter index = 0;
478
parameter number_of_clk = 1;
479
parameter period_time_0 = 20000;
480
parameter period_time_1 = 20000;
481
parameter period_time_2 = 20000;
482
parameter period_time_3 = 20000;
483
parameter period_time_4 = 20000;
484
parameter lock_delay = 2000000;
485
input clk_i, rst_n_i;
486
output lock;
487
output reg [0:number_of_clk-1] clk_o;
488
output [0:number_of_clk-1] rst_o;
489
 
490
`ifdef SIM_PLL
491
 
492
always
493
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
494
 
495
generate if (number_of_clk > 1)
496
always
497
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
498
endgenerate
499
 
500
generate if (number_of_clk > 2)
501
always
502
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
503
endgenerate
504
 
505 33 unneback
generate if (number_of_clk > 3)
506 32 unneback
always
507
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
508
endgenerate
509
 
510 33 unneback
generate if (number_of_clk > 4)
511 32 unneback
always
512
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
513
endgenerate
514
 
515
genvar i;
516
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
517
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
518
end
519
endgenerate
520
 
521 33 unneback
//assign #lock_delay lock = rst_n_i;
522
assign lock = rst_n_i;
523 32 unneback
 
524
endmodule
525 6 unneback
`else
526
 
527 33 unneback
`ifdef VL_PLL0
528
`ifdef VL_PLL0_CLK1
529
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
530
`endif
531
`ifdef VL_PLL0_CLK2
532
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
533
`endif
534
`ifdef VL_PLL0_CLK3
535
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
536
`endif
537
`ifdef VL_PLL0_CLK4
538
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
539
`endif
540
`ifdef VL_PLL0_CLK5
541
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
542
`endif
543
`endif
544 32 unneback
 
545 33 unneback
`ifdef VL_PLL1
546
`ifdef VL_PLL1_CLK1
547
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
548
`endif
549
`ifdef VL_PLL1_CLK2
550
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
551
`endif
552
`ifdef VL_PLL1_CLK3
553
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
554
`endif
555
`ifdef VL_PLL1_CLK4
556
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
557
`endif
558
`ifdef VL_PLL1_CLK5
559
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
560
`endif
561
`endif
562 32 unneback
 
563 33 unneback
`ifdef VL_PLL2
564
`ifdef VL_PLL2_CLK1
565
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
566
`endif
567
`ifdef VL_PLL2_CLK2
568
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
569
`endif
570
`ifdef VL_PLL2_CLK3
571
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
572
`endif
573
`ifdef VL_PLL2_CLK4
574
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
575
`endif
576
`ifdef VL_PLL2_CLK5
577
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
578
`endif
579
`endif
580 32 unneback
 
581 33 unneback
`ifdef VL_PLL3
582
`ifdef VL_PLL3_CLK1
583
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
584
`endif
585
`ifdef VL_PLL3_CLK2
586
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
587
`endif
588
`ifdef VL_PLL3_CLK3
589
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
590
`endif
591
`ifdef VL_PLL3_CLK4
592
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
593
`endif
594
`ifdef VL_PLL3_CLK5
595
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
596
`endif
597
`endif
598 32 unneback
 
599
genvar i;
600
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
601 40 unneback
`define MODULE sync_rst
602
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
603
`undef MODULE
604 32 unneback
end
605
endgenerate
606
endmodule
607
`endif
608
///////////////////////////////////////////////////////////////////////////////
609
 
610
`else
611
 
612 6 unneback
// generic PLL
613 17 unneback
`timescale 1 ps/1 ps
614 40 unneback
`define MODULE pll
615
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
616
`undef MODULE
617 6 unneback
parameter index = 0;
618
parameter number_of_clk = 1;
619 17 unneback
parameter period_time_0 = 20000;
620
parameter period_time_1 = 20000;
621
parameter period_time_2 = 20000;
622 6 unneback
parameter lock_delay = 2000;
623
input clk_i, rst_n_i;
624
output lock;
625
output reg [0:number_of_clk-1] clk_o;
626
output [0:number_of_clk-1] rst_o;
627
 
628
always
629
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
630
 
631
generate if (number_of_clk > 1)
632
always
633
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
634
endgenerate
635
 
636
generate if (number_of_clk > 2)
637
always
638
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
639
endgenerate
640
 
641
genvar i;
642
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
643 40 unneback
`define MODULE sync_rst
644
     `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
645
`undef MODULE
646 6 unneback
end
647
endgenerate
648
 
649
assign #lock_delay lock = rst_n_i;
650
 
651
endmodule
652
 
653
`endif //altera
654 17 unneback
`endif //actel
655 40 unneback
`undef MODULE
656
`endif//////////////////////////////////////////////////////////////////////
657 6 unneback
////                                                              ////
658
////  Versatile library, registers                                ////
659
////                                                              ////
660
////  Description                                                 ////
661
////  Different type of registers                                 ////
662
////                                                              ////
663
////                                                              ////
664
////  To Do:                                                      ////
665
////   - add more different registers                             ////
666
////                                                              ////
667
////  Author(s):                                                  ////
668
////      - Michael Unneback, unneback@opencores.org              ////
669
////        ORSoC AB                                              ////
670
////                                                              ////
671
//////////////////////////////////////////////////////////////////////
672
////                                                              ////
673
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
674
////                                                              ////
675
//// This source file may be used and distributed without         ////
676
//// restriction provided that this copyright statement is not    ////
677
//// removed from the file and that any derivative work contains  ////
678
//// the original copyright notice and the associated disclaimer. ////
679
////                                                              ////
680
//// This source file is free software; you can redistribute it   ////
681
//// and/or modify it under the terms of the GNU Lesser General   ////
682
//// Public License as published by the Free Software Foundation; ////
683
//// either version 2.1 of the License, or (at your option) any   ////
684
//// later version.                                               ////
685
////                                                              ////
686
//// This source is distributed in the hope that it will be       ////
687
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
688
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
689
//// PURPOSE.  See the GNU Lesser General Public License for more ////
690
//// details.                                                     ////
691
////                                                              ////
692
//// You should have received a copy of the GNU Lesser General    ////
693
//// Public License along with this source; if not, download it   ////
694
//// from http://www.opencores.org/lgpl.shtml                     ////
695
////                                                              ////
696
//////////////////////////////////////////////////////////////////////
697
 
698 40 unneback
`ifdef DFF
699
`define MODULE dff
700
module `BASE`MODULE ( d, q, clk, rst);
701
`undef MODULE
702 6 unneback
        parameter width = 1;
703
        parameter reset_value = 0;
704
 
705
        input [width-1:0] d;
706
        input clk, rst;
707
        output reg [width-1:0] q;
708
 
709
        always @ (posedge clk or posedge rst)
710
        if (rst)
711
                q <= reset_value;
712
        else
713
                q <= d;
714
 
715
endmodule
716 40 unneback
`endif
717 6 unneback
 
718 40 unneback
`ifdef DFF_ARRAY
719
`define MODULE dff_array
720
module `BASE`MODULE ( d, q, clk, rst);
721
`undef MODULE
722 6 unneback
 
723
        parameter width = 1;
724
        parameter depth = 2;
725
        parameter reset_value = 1'b0;
726
 
727
        input [width-1:0] d;
728
        input clk, rst;
729
        output [width-1:0] q;
730
        reg  [0:depth-1] q_tmp [width-1:0];
731
        integer i;
732
        always @ (posedge clk or posedge rst)
733
        if (rst) begin
734
            for (i=0;i<depth;i=i+1)
735
                q_tmp[i] <= {width{reset_value}};
736
        end else begin
737
            q_tmp[0] <= d;
738
            for (i=1;i<depth;i=i+1)
739
                q_tmp[i] <= q_tmp[i-1];
740
        end
741
 
742
    assign q = q_tmp[depth-1];
743
 
744
endmodule
745 40 unneback
`endif
746 6 unneback
 
747 40 unneback
`ifdef DFF_CE
748
`define MODULE dff_ce
749
module `BASE`MODULE ( d, ce, q, clk, rst);
750
`undef MODULE
751 6 unneback
 
752
        parameter width = 1;
753
        parameter reset_value = 0;
754
 
755
        input [width-1:0] d;
756
        input ce, clk, rst;
757
        output reg [width-1:0] q;
758
 
759
        always @ (posedge clk or posedge rst)
760
        if (rst)
761
                q <= reset_value;
762
        else
763
                if (ce)
764
                        q <= d;
765
 
766
endmodule
767 40 unneback
`endif
768 6 unneback
 
769 40 unneback
`ifdef DFF_CE_CLEAR
770
`define MODULE dff_ce_clear
771
module `BASE`MODULE ( d, ce, clear, q, clk, rst);
772
`undef MODULE
773 8 unneback
 
774
        parameter width = 1;
775
        parameter reset_value = 0;
776
 
777
        input [width-1:0] d;
778 10 unneback
        input ce, clear, clk, rst;
779 8 unneback
        output reg [width-1:0] q;
780
 
781
        always @ (posedge clk or posedge rst)
782
        if (rst)
783
            q <= reset_value;
784
        else
785
            if (ce)
786
                if (clear)
787
                    q <= {width{1'b0}};
788
                else
789
                    q <= d;
790
 
791
endmodule
792 40 unneback
`endif
793 8 unneback
 
794 40 unneback
`ifdef DF_CE_SET
795
`define MODULE dff_ce_set
796
module `BASE`MODULE ( d, ce, set, q, clk, rst);
797
`undef MODULE
798 24 unneback
 
799
        parameter width = 1;
800
        parameter reset_value = 0;
801
 
802
        input [width-1:0] d;
803
        input ce, set, clk, rst;
804
        output reg [width-1:0] q;
805
 
806
        always @ (posedge clk or posedge rst)
807
        if (rst)
808
            q <= reset_value;
809
        else
810
            if (ce)
811
                if (set)
812
                    q <= {width{1'b1}};
813
                else
814
                    q <= d;
815
 
816
endmodule
817 40 unneback
`endif
818 24 unneback
 
819 40 unneback
`ifdef SPR
820
`define MODULE spr
821
module `BASE`MODULE ( sp, r, q, clk, rst);
822
`undef MODULE
823
 
824 29 unneback
        parameter width = 1;
825
        parameter reset_value = 0;
826
 
827
        input sp, r;
828
        output reg q;
829
        input clk, rst;
830
 
831
        always @ (posedge clk or posedge rst)
832
        if (rst)
833
            q <= reset_value;
834
        else
835
            if (sp)
836
                q <= 1'b1;
837
            else if (r)
838
                q <= 1'b0;
839
 
840
endmodule
841 40 unneback
`endif
842 29 unneback
 
843 40 unneback
`ifdef SRP
844
`define MODULE srp
845
module `BASE`MODULE ( s, rp, q, clk, rst);
846
`undef MODULE
847
 
848 29 unneback
        parameter width = 1;
849
        parameter reset_value = 0;
850
 
851
        input s, rp;
852
        output reg q;
853
        input clk, rst;
854
 
855
        always @ (posedge clk or posedge rst)
856
        if (rst)
857
            q <= reset_value;
858
        else
859
            if (rp)
860
                q <= 1'b0;
861
            else if (s)
862
                q <= 1'b1;
863
 
864
endmodule
865 40 unneback
`endif
866 29 unneback
 
867 40 unneback
`ifdef ALTERA
868 29 unneback
 
869 40 unneback
`ifdef DFF_SR
870 6 unneback
// megafunction wizard: %LPM_FF%
871
// GENERATION: STANDARD
872
// VERSION: WM1.0
873
// MODULE: lpm_ff 
874
 
875
// ============================================================
876
// File Name: dff_sr.v
877
// Megafunction Name(s):
878
//                      lpm_ff
879
//
880
// Simulation Library Files(s):
881
//                      lpm
882
// ============================================================
883
// ************************************************************
884
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
885
//
886
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
887
// ************************************************************
888
 
889
 
890
//Copyright (C) 1991-2010 Altera Corporation
891
//Your use of Altera Corporation's design tools, logic functions 
892
//and other software and tools, and its AMPP partner logic 
893
//functions, and any output files from any of the foregoing 
894
//(including device programming or simulation files), and any 
895
//associated documentation or information are expressly subject 
896
//to the terms and conditions of the Altera Program License 
897
//Subscription Agreement, Altera MegaCore Function License 
898
//Agreement, or other applicable license agreement, including, 
899
//without limitation, that your use is for the sole purpose of 
900
//programming logic devices manufactured by Altera and sold by 
901
//Altera or its authorized distributors.  Please refer to the 
902
//applicable agreement for further details.
903
 
904
 
905
// synopsys translate_off
906
`timescale 1 ps / 1 ps
907
// synopsys translate_on
908 40 unneback
`define MODULE dff_sr
909
module `BASE`MODULE (
910
`undef MODULE
911
 
912 6 unneback
        aclr,
913
        aset,
914
        clock,
915
        data,
916
        q);
917
 
918
        input     aclr;
919
        input     aset;
920
        input     clock;
921
        input     data;
922
        output    q;
923
 
924
        wire [0:0] sub_wire0;
925
        wire [0:0] sub_wire1 = sub_wire0[0:0];
926
        wire  q = sub_wire1;
927
        wire  sub_wire2 = data;
928
        wire  sub_wire3 = sub_wire2;
929
 
930
        lpm_ff  lpm_ff_component (
931
                                .aclr (aclr),
932
                                .clock (clock),
933
                                .data (sub_wire3),
934
                                .aset (aset),
935
                                .q (sub_wire0)
936
                                // synopsys translate_off
937
                                ,
938
                                .aload (),
939
                                .enable (),
940
                                .sclr (),
941
                                .sload (),
942
                                .sset ()
943
                                // synopsys translate_on
944
                                );
945
        defparam
946
                lpm_ff_component.lpm_fftype = "DFF",
947
                lpm_ff_component.lpm_type = "LPM_FF",
948
                lpm_ff_component.lpm_width = 1;
949
 
950
 
951
endmodule
952
 
953
// ============================================================
954
// CNX file retrieval info
955
// ============================================================
956
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
957
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
958
// Retrieval info: PRIVATE: ASET NUMERIC "1"
959
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
960
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
961
// Retrieval info: PRIVATE: DFF NUMERIC "1"
962
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
963
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
964
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
965
// Retrieval info: PRIVATE: SSET NUMERIC "0"
966
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
967
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
968
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
969
// Retrieval info: PRIVATE: nBit NUMERIC "1"
970
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
971
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
972
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
973
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
974
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
975
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
976
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
977
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
978
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
979
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
980
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
981
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
982
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
983
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
984
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
985
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
986
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
987
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
988
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
989
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
990
// Retrieval info: LIB_FILE: lpm
991 40 unneback
`endif
992 6 unneback
 
993
`else
994
 
995 40 unneback
`ifdef DFF_SR
996
`define MODULE dff_sr
997
module `BASE`MODULE ( aclr, aset, clock, data, q);
998
`undef MODULE
999 6 unneback
 
1000
    input         aclr;
1001
    input         aset;
1002
    input         clock;
1003
    input         data;
1004
    output reg    q;
1005
 
1006
   always @ (posedge clock or posedge aclr or posedge aset)
1007
     if (aclr)
1008
       q <= 1'b0;
1009
     else if (aset)
1010
       q <= 1'b1;
1011
     else
1012
       q <= data;
1013
 
1014
endmodule
1015 40 unneback
`endif
1016 6 unneback
 
1017
`endif
1018
 
1019
// LATCH
1020
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
1021
`ifdef ALTERA
1022 40 unneback
 
1023
`ifdef LATCH
1024
`define MODULE latch
1025
module `BASE`MODULE ( d, le, q, clk);
1026
`undef MODULE
1027 6 unneback
input d, le;
1028
output q;
1029
input clk;
1030
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
1031
endmodule
1032 40 unneback
`endif
1033
 
1034 6 unneback
`else
1035 40 unneback
 
1036
`ifdef LATCH
1037
`define MODULE latch
1038
module `BASE`MODULE ( d, le, q, clk);
1039
`undef MODULE
1040 6 unneback
input d, le;
1041 48 unneback
input clk;
1042
always @ (le or d)
1043 60 unneback
if (le)
1044 48 unneback
    d <= q;
1045 6 unneback
endmodule
1046 15 unneback
`endif
1047
 
1048 40 unneback
`endif
1049
 
1050
`ifdef SHREG
1051
`define MODULE shreg
1052
module `BASE`MODULE ( d, q, clk, rst);
1053
`undef MODULE
1054
 
1055 17 unneback
parameter depth = 10;
1056
input d;
1057
output q;
1058
input clk, rst;
1059
 
1060
reg [1:depth] dffs;
1061
 
1062
always @ (posedge clk or posedge rst)
1063
if (rst)
1064
    dffs <= {depth{1'b0}};
1065
else
1066
    dffs <= {d,dffs[1:depth-1]};
1067
assign q = dffs[depth];
1068
endmodule
1069 40 unneback
`endif
1070 17 unneback
 
1071 40 unneback
`ifdef SHREG_CE
1072
`define MODULE shreg_ce
1073
module `BASE`MODULE ( d, ce, q, clk, rst);
1074
`undef MODULE
1075 17 unneback
parameter depth = 10;
1076
input d, ce;
1077
output q;
1078
input clk, rst;
1079
 
1080
reg [1:depth] dffs;
1081
 
1082
always @ (posedge clk or posedge rst)
1083
if (rst)
1084
    dffs <= {depth{1'b0}};
1085
else
1086
    if (ce)
1087
        dffs <= {d,dffs[1:depth-1]};
1088
assign q = dffs[depth];
1089
endmodule
1090 40 unneback
`endif
1091 17 unneback
 
1092 40 unneback
`ifdef DELAY
1093
`define MODULE delay
1094
module `BASE`MODULE ( d, q, clk, rst);
1095
`undef MODULE
1096 15 unneback
parameter depth = 10;
1097
input d;
1098
output q;
1099
input clk, rst;
1100
 
1101
reg [1:depth] dffs;
1102
 
1103
always @ (posedge clk or posedge rst)
1104
if (rst)
1105
    dffs <= {depth{1'b0}};
1106
else
1107
    dffs <= {d,dffs[1:depth-1]};
1108
assign q = dffs[depth];
1109 17 unneback
endmodule
1110 40 unneback
`endif
1111 17 unneback
 
1112 40 unneback
`ifdef DELAY_EMPTYFLAG
1113
`define MODULE delay_emptyflag
1114 41 unneback
module `BASE`MODULE ( d, q, emptyflag, clk, rst);
1115 40 unneback
`undef MODULE
1116 17 unneback
parameter depth = 10;
1117
input d;
1118
output q, emptyflag;
1119
input clk, rst;
1120
 
1121
reg [1:depth] dffs;
1122
 
1123
always @ (posedge clk or posedge rst)
1124
if (rst)
1125
    dffs <= {depth{1'b0}};
1126
else
1127
    dffs <= {d,dffs[1:depth-1]};
1128
assign q = dffs[depth];
1129
assign emptyflag = !(|dffs);
1130
endmodule
1131 40 unneback
`endif
1132 17 unneback
//////////////////////////////////////////////////////////////////////
1133 6 unneback
////                                                              ////
1134 18 unneback
////  Logic functions                                             ////
1135
////                                                              ////
1136
////  Description                                                 ////
1137
////  Logic functions such as multiplexers                        ////
1138
////                                                              ////
1139
////                                                              ////
1140
////  To Do:                                                      ////
1141
////   -                                                          ////
1142
////                                                              ////
1143
////  Author(s):                                                  ////
1144
////      - Michael Unneback, unneback@opencores.org              ////
1145
////        ORSoC AB                                              ////
1146
////                                                              ////
1147
//////////////////////////////////////////////////////////////////////
1148
////                                                              ////
1149
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1150
////                                                              ////
1151
//// This source file may be used and distributed without         ////
1152
//// restriction provided that this copyright statement is not    ////
1153
//// removed from the file and that any derivative work contains  ////
1154
//// the original copyright notice and the associated disclaimer. ////
1155
////                                                              ////
1156
//// This source file is free software; you can redistribute it   ////
1157
//// and/or modify it under the terms of the GNU Lesser General   ////
1158
//// Public License as published by the Free Software Foundation; ////
1159
//// either version 2.1 of the License, or (at your option) any   ////
1160
//// later version.                                               ////
1161
////                                                              ////
1162
//// This source is distributed in the hope that it will be       ////
1163
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1164
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1165
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1166
//// details.                                                     ////
1167
////                                                              ////
1168
//// You should have received a copy of the GNU Lesser General    ////
1169
//// Public License along with this source; if not, download it   ////
1170
//// from http://www.opencores.org/lgpl.shtml                     ////
1171
////                                                              ////
1172
//////////////////////////////////////////////////////////////////////
1173 40 unneback
`ifdef MUX_ANDOR
1174
`define MODULE mux_andor
1175
module `BASE`MODULE ( a, sel, dout);
1176
`undef MODULE
1177 36 unneback
 
1178
parameter width = 32;
1179
parameter nr_of_ports = 4;
1180
 
1181
input [nr_of_ports*width-1:0] a;
1182
input [nr_of_ports-1:0] sel;
1183
output reg [width-1:0] dout;
1184
 
1185 38 unneback
integer i,j;
1186
 
1187 36 unneback
always @ (a, sel)
1188
begin
1189
    dout = a[width-1:0] & {width{sel[0]}};
1190 42 unneback
    for (i=1;i<nr_of_ports;i=i+1)
1191
        for (j=0;j<width;j=j+1)
1192
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
1193 36 unneback
end
1194
 
1195
endmodule
1196 40 unneback
`endif
1197 36 unneback
 
1198 40 unneback
`ifdef MUX2_ANDOR
1199
`define MODULE mux2_andor
1200
module `BASE`MODULE ( a1, a0, sel, dout);
1201
`undef MODULE
1202 18 unneback
 
1203 34 unneback
parameter width = 32;
1204 35 unneback
localparam nr_of_ports = 2;
1205 34 unneback
input [width-1:0] a1, a0;
1206
input [nr_of_ports-1:0] sel;
1207
output [width-1:0] dout;
1208
 
1209 40 unneback
`define MODULE mux_andor
1210
`BASE`MODULE
1211 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1212 36 unneback
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
1213 40 unneback
`undef MODULE
1214
 
1215 34 unneback
endmodule
1216 40 unneback
`endif
1217 34 unneback
 
1218 40 unneback
`ifdef MUX3_ANDOR
1219
`define MODULE mux3_andor
1220
module `BASE`MODULE ( a2, a1, a0, sel, dout);
1221
`undef MODULE
1222 34 unneback
 
1223
parameter width = 32;
1224 35 unneback
localparam nr_of_ports = 3;
1225 34 unneback
input [width-1:0] a2, a1, a0;
1226
input [nr_of_ports-1:0] sel;
1227
output [width-1:0] dout;
1228
 
1229 40 unneback
`define MODULE mux_andor
1230
`BASE`MODULE
1231 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1232 36 unneback
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
1233 40 unneback
`undef MODULE
1234 34 unneback
endmodule
1235 40 unneback
`endif
1236 34 unneback
 
1237 40 unneback
`ifdef MUX4_ANDOR
1238
`define MODULE mux4_andor
1239
module `BASE`MODULE ( a3, a2, a1, a0, sel, dout);
1240
`undef MODULE
1241 18 unneback
 
1242
parameter width = 32;
1243 35 unneback
localparam nr_of_ports = 4;
1244 18 unneback
input [width-1:0] a3, a2, a1, a0;
1245
input [nr_of_ports-1:0] sel;
1246 22 unneback
output [width-1:0] dout;
1247 18 unneback
 
1248 40 unneback
`define MODULE mux_andor
1249
`BASE`MODULE
1250 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1251 36 unneback
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
1252 40 unneback
`undef MODULE
1253 18 unneback
 
1254
endmodule
1255 40 unneback
`endif
1256 18 unneback
 
1257 40 unneback
`ifdef MUX5_ANDOR
1258
`define MODULE mux5_andor
1259
module `BASE`MODULE ( a4, a3, a2, a1, a0, sel, dout);
1260
`undef MODULE
1261 18 unneback
 
1262
parameter width = 32;
1263 35 unneback
localparam nr_of_ports = 5;
1264 18 unneback
input [width-1:0] a4, a3, a2, a1, a0;
1265
input [nr_of_ports-1:0] sel;
1266 22 unneback
output [width-1:0] dout;
1267 18 unneback
 
1268 40 unneback
`define MODULE mux_andor
1269
`BASE`MODULE
1270 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1271 36 unneback
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1272 40 unneback
`undef MODULE
1273 18 unneback
 
1274
endmodule
1275 40 unneback
`endif
1276 18 unneback
 
1277 40 unneback
`ifdef MUX6_ANDOR
1278
`define MODULE mux6_andor
1279
module `BASE`MODULE ( a5, a4, a3, a2, a1, a0, sel, dout);
1280
`undef MODULE
1281 18 unneback
 
1282
parameter width = 32;
1283 35 unneback
localparam nr_of_ports = 6;
1284 18 unneback
input [width-1:0] a5, a4, a3, a2, a1, a0;
1285
input [nr_of_ports-1:0] sel;
1286 22 unneback
output [width-1:0] dout;
1287 18 unneback
 
1288 40 unneback
`define MODULE mux_andor
1289
`BASE`MODULE
1290 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
1291 36 unneback
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1292 40 unneback
`undef MODULE
1293 18 unneback
 
1294
endmodule
1295 40 unneback
`endif
1296 43 unneback
 
1297
`ifdef PARITY
1298
 
1299
`define MODULE parity_generate
1300
module `BASE`MODULE (data, parity);
1301
`undef MODULE
1302
parameter word_size = 32;
1303
parameter chunk_size = 8;
1304
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1305
input [word_size-1:0] data;
1306
output reg [word_size/chunk_size-1:0] parity;
1307
integer i,j;
1308
always @ (data)
1309
for (i=0;i<word_size/chunk_size;i=i+1) begin
1310
    parity[i] = parity_type;
1311
    for (j=0;j<chunk_size;j=j+1) begin
1312 46 unneback
        parity[i] = data[i*chunk_size+j] ^ parity[i];
1313 43 unneback
    end
1314
end
1315
endmodule
1316
 
1317
`define MODULE parity_check
1318
module `BASE`MODULE( data, parity, parity_error);
1319
`undef MODULE
1320
parameter word_size = 32;
1321
parameter chunk_size = 8;
1322
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1323
input [word_size-1:0] data;
1324
input [word_size/chunk_size-1:0] parity;
1325
output parity_error;
1326 44 unneback
reg [word_size/chunk_size-1:0] error_flag;
1327 43 unneback
integer i,j;
1328
always @ (data or parity)
1329
for (i=0;i<word_size/chunk_size;i=i+1) begin
1330
    error_flag[i] = parity[i] ^ parity_type;
1331
    for (j=0;j<chunk_size;j=j+1) begin
1332 46 unneback
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
1333 43 unneback
    end
1334
end
1335
assign parity_error = |error_flag;
1336
endmodule
1337
 
1338 44 unneback
`endif//////////////////////////////////////////////////////////////////////
1339
////                                                              ////
1340
////  IO functions                                                ////
1341
////                                                              ////
1342
////  Description                                                 ////
1343
////  IO functions such as IOB flip-flops                         ////
1344
////                                                              ////
1345
////                                                              ////
1346
////  To Do:                                                      ////
1347
////   -                                                          ////
1348
////                                                              ////
1349
////  Author(s):                                                  ////
1350
////      - Michael Unneback, unneback@opencores.org              ////
1351
////        ORSoC AB                                              ////
1352
////                                                              ////
1353 18 unneback
//////////////////////////////////////////////////////////////////////
1354
////                                                              ////
1355 44 unneback
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1356
////                                                              ////
1357
//// This source file may be used and distributed without         ////
1358
//// restriction provided that this copyright statement is not    ////
1359
//// removed from the file and that any derivative work contains  ////
1360
//// the original copyright notice and the associated disclaimer. ////
1361
////                                                              ////
1362
//// This source file is free software; you can redistribute it   ////
1363
//// and/or modify it under the terms of the GNU Lesser General   ////
1364
//// Public License as published by the Free Software Foundation; ////
1365
//// either version 2.1 of the License, or (at your option) any   ////
1366
//// later version.                                               ////
1367
////                                                              ////
1368
//// This source is distributed in the hope that it will be       ////
1369
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1370
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1371
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1372
//// details.                                                     ////
1373
////                                                              ////
1374
//// You should have received a copy of the GNU Lesser General    ////
1375
//// Public License along with this source; if not, download it   ////
1376
//// from http://www.opencores.org/lgpl.shtml                     ////
1377
////                                                              ////
1378
//////////////////////////////////////////////////////////////////////
1379 45 unneback
`timescale 1ns/1ns
1380 44 unneback
`ifdef O_DFF
1381
`define MODULE o_dff
1382
module `BASE`MODULE (d_i, o_pad, clk, rst);
1383
`undef MODULE
1384
parameter width = 1;
1385 45 unneback
parameter reset_value = {width{1'b0}};
1386
input  [width-1:0]  d_i;
1387 44 unneback
output [width-1:0] o_pad;
1388
input clk, rst;
1389
wire [width-1:0] d_i_int `SYN_KEEP;
1390 45 unneback
reg  [width-1:0] o_pad_int;
1391 44 unneback
assign d_i_int = d_i;
1392
genvar i;
1393 45 unneback
generate
1394 44 unneback
for (i=0;i<width;i=i+1) begin
1395
    always @ (posedge clk or posedge rst)
1396
    if (rst)
1397 45 unneback
        o_pad_int[i] <= reset_value[i];
1398 44 unneback
    else
1399 45 unneback
        o_pad_int[i] <= d_i_int[i];
1400
    assign #1 o_pad[i] = o_pad_int[i];
1401 44 unneback
end
1402
endgenerate
1403
endmodule
1404
`endif
1405
 
1406 45 unneback
`timescale 1ns/1ns
1407 44 unneback
`ifdef IO_DFF_OE
1408
`define MODULE io_dff_oe
1409
module `BASE`MODULE ( d_i, d_o, oe, io_pad, clk, rst);
1410
`undef MODULE
1411
parameter width = 1;
1412
input  [width-1:0] d_o;
1413
output reg [width-1:0] d_i;
1414
input oe;
1415
inout [width-1:0] io_pad;
1416
input clk, rst;
1417
wire [width-1:0] oe_d `SYN_KEEP;
1418
reg [width-1:0] oe_q;
1419
reg [width-1:0] d_o_q;
1420
assign oe_d = {width{oe}};
1421
genvar i;
1422
generate
1423
for (i=0;i<width;i=i+1) begin
1424
    always @ (posedge clk or posedge rst)
1425
    if (rst)
1426
        oe_q[i] <= 1'b0;
1427
    else
1428
        oe_q[i] <= oe_d[i];
1429
    always @ (posedge clk or posedge rst)
1430
    if (rst)
1431
        d_o_q[i] <= 1'b0;
1432
    else
1433
        d_o_q[i] <= d_o[i];
1434
    always @ (posedge clk or posedge rst)
1435
    if (rst)
1436
        d_i[i] <= 1'b0;
1437
    else
1438
        d_i[i] <= io_pad[i];
1439 45 unneback
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
1440 44 unneback
end
1441
endgenerate
1442
endmodule
1443
`endif
1444
`ifdef CNT_BIN
1445
//////////////////////////////////////////////////////////////////////
1446
////                                                              ////
1447 6 unneback
////  Versatile counter                                           ////
1448
////                                                              ////
1449
////  Description                                                 ////
1450
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1451
////  counter                                                     ////
1452
////                                                              ////
1453
////  To Do:                                                      ////
1454
////   - add LFSR with more taps                                  ////
1455
////                                                              ////
1456
////  Author(s):                                                  ////
1457
////      - Michael Unneback, unneback@opencores.org              ////
1458
////        ORSoC AB                                              ////
1459
////                                                              ////
1460
//////////////////////////////////////////////////////////////////////
1461
////                                                              ////
1462
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1463
////                                                              ////
1464
//// This source file may be used and distributed without         ////
1465
//// restriction provided that this copyright statement is not    ////
1466
//// removed from the file and that any derivative work contains  ////
1467
//// the original copyright notice and the associated disclaimer. ////
1468
////                                                              ////
1469
//// This source file is free software; you can redistribute it   ////
1470
//// and/or modify it under the terms of the GNU Lesser General   ////
1471
//// Public License as published by the Free Software Foundation; ////
1472
//// either version 2.1 of the License, or (at your option) any   ////
1473
//// later version.                                               ////
1474
////                                                              ////
1475
//// This source is distributed in the hope that it will be       ////
1476
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1477
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1478
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1479
//// details.                                                     ////
1480
////                                                              ////
1481
//// You should have received a copy of the GNU Lesser General    ////
1482
//// Public License along with this source; if not, download it   ////
1483
//// from http://www.opencores.org/lgpl.shtml                     ////
1484
////                                                              ////
1485
//////////////////////////////////////////////////////////////////////
1486
 
1487
// binary counter
1488 22 unneback
 
1489 40 unneback
`define MODULE cnt_bin
1490
module `BASE`MODULE (
1491
`undef MODULE
1492
 q, rst, clk);
1493
 
1494 22 unneback
   parameter length = 4;
1495
   output [length:1] q;
1496
   input rst;
1497
   input clk;
1498
 
1499
   parameter clear_value = 0;
1500
   parameter set_value = 1;
1501
   parameter wrap_value = 0;
1502
   parameter level1_value = 15;
1503
 
1504
   reg  [length:1] qi;
1505
   wire [length:1] q_next;
1506
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1507
 
1508
   always @ (posedge clk or posedge rst)
1509
     if (rst)
1510
       qi <= {length{1'b0}};
1511
     else
1512
       qi <= q_next;
1513
 
1514
   assign q = qi;
1515
 
1516
endmodule
1517 40 unneback
`endif
1518
`ifdef CNT_BIN_CLEAR
1519 22 unneback
//////////////////////////////////////////////////////////////////////
1520
////                                                              ////
1521
////  Versatile counter                                           ////
1522
////                                                              ////
1523
////  Description                                                 ////
1524
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1525
////  counter                                                     ////
1526
////                                                              ////
1527
////  To Do:                                                      ////
1528
////   - add LFSR with more taps                                  ////
1529
////                                                              ////
1530
////  Author(s):                                                  ////
1531
////      - Michael Unneback, unneback@opencores.org              ////
1532
////        ORSoC AB                                              ////
1533
////                                                              ////
1534
//////////////////////////////////////////////////////////////////////
1535
////                                                              ////
1536
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1537
////                                                              ////
1538
//// This source file may be used and distributed without         ////
1539
//// restriction provided that this copyright statement is not    ////
1540
//// removed from the file and that any derivative work contains  ////
1541
//// the original copyright notice and the associated disclaimer. ////
1542
////                                                              ////
1543
//// This source file is free software; you can redistribute it   ////
1544
//// and/or modify it under the terms of the GNU Lesser General   ////
1545
//// Public License as published by the Free Software Foundation; ////
1546
//// either version 2.1 of the License, or (at your option) any   ////
1547
//// later version.                                               ////
1548
////                                                              ////
1549
//// This source is distributed in the hope that it will be       ////
1550
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1551
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1552
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1553
//// details.                                                     ////
1554
////                                                              ////
1555
//// You should have received a copy of the GNU Lesser General    ////
1556
//// Public License along with this source; if not, download it   ////
1557
//// from http://www.opencores.org/lgpl.shtml                     ////
1558
////                                                              ////
1559
//////////////////////////////////////////////////////////////////////
1560
 
1561
// binary counter
1562
 
1563 40 unneback
`define MODULE cnt_bin_clear
1564
module `BASE`MODULE (
1565
`undef MODULE
1566
 clear, q, rst, clk);
1567
 
1568 22 unneback
   parameter length = 4;
1569
   input clear;
1570
   output [length:1] q;
1571
   input rst;
1572
   input clk;
1573
 
1574
   parameter clear_value = 0;
1575
   parameter set_value = 1;
1576
   parameter wrap_value = 0;
1577
   parameter level1_value = 15;
1578
 
1579
   reg  [length:1] qi;
1580
   wire [length:1] q_next;
1581
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1582
 
1583
   always @ (posedge clk or posedge rst)
1584
     if (rst)
1585
       qi <= {length{1'b0}};
1586
     else
1587
       qi <= q_next;
1588
 
1589
   assign q = qi;
1590
 
1591
endmodule
1592 40 unneback
`endif
1593
`ifdef CNT_BIN_CE
1594 22 unneback
//////////////////////////////////////////////////////////////////////
1595
////                                                              ////
1596
////  Versatile counter                                           ////
1597
////                                                              ////
1598
////  Description                                                 ////
1599
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1600
////  counter                                                     ////
1601
////                                                              ////
1602
////  To Do:                                                      ////
1603
////   - add LFSR with more taps                                  ////
1604
////                                                              ////
1605
////  Author(s):                                                  ////
1606
////      - Michael Unneback, unneback@opencores.org              ////
1607
////        ORSoC AB                                              ////
1608
////                                                              ////
1609
//////////////////////////////////////////////////////////////////////
1610
////                                                              ////
1611
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1612
////                                                              ////
1613
//// This source file may be used and distributed without         ////
1614
//// restriction provided that this copyright statement is not    ////
1615
//// removed from the file and that any derivative work contains  ////
1616
//// the original copyright notice and the associated disclaimer. ////
1617
////                                                              ////
1618
//// This source file is free software; you can redistribute it   ////
1619
//// and/or modify it under the terms of the GNU Lesser General   ////
1620
//// Public License as published by the Free Software Foundation; ////
1621
//// either version 2.1 of the License, or (at your option) any   ////
1622
//// later version.                                               ////
1623
////                                                              ////
1624
//// This source is distributed in the hope that it will be       ////
1625
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1626
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1627
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1628
//// details.                                                     ////
1629
////                                                              ////
1630
//// You should have received a copy of the GNU Lesser General    ////
1631
//// Public License along with this source; if not, download it   ////
1632
//// from http://www.opencores.org/lgpl.shtml                     ////
1633
////                                                              ////
1634
//////////////////////////////////////////////////////////////////////
1635
 
1636
// binary counter
1637 6 unneback
 
1638 40 unneback
`define MODULE cnt_bin_ce
1639
module `BASE`MODULE (
1640
`undef MODULE
1641
 cke, q, rst, clk);
1642
 
1643 6 unneback
   parameter length = 4;
1644
   input cke;
1645
   output [length:1] q;
1646
   input rst;
1647
   input clk;
1648
 
1649
   parameter clear_value = 0;
1650
   parameter set_value = 1;
1651
   parameter wrap_value = 0;
1652
   parameter level1_value = 15;
1653
 
1654
   reg  [length:1] qi;
1655
   wire [length:1] q_next;
1656
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1657
 
1658
   always @ (posedge clk or posedge rst)
1659
     if (rst)
1660
       qi <= {length{1'b0}};
1661
     else
1662
     if (cke)
1663
       qi <= q_next;
1664
 
1665
   assign q = qi;
1666
 
1667
endmodule
1668 40 unneback
`endif
1669
`ifdef CNT_BIN_CE_CLEAR
1670 6 unneback
//////////////////////////////////////////////////////////////////////
1671
////                                                              ////
1672
////  Versatile counter                                           ////
1673
////                                                              ////
1674
////  Description                                                 ////
1675
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1676
////  counter                                                     ////
1677
////                                                              ////
1678
////  To Do:                                                      ////
1679
////   - add LFSR with more taps                                  ////
1680
////                                                              ////
1681
////  Author(s):                                                  ////
1682
////      - Michael Unneback, unneback@opencores.org              ////
1683
////        ORSoC AB                                              ////
1684
////                                                              ////
1685
//////////////////////////////////////////////////////////////////////
1686
////                                                              ////
1687
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1688
////                                                              ////
1689
//// This source file may be used and distributed without         ////
1690
//// restriction provided that this copyright statement is not    ////
1691
//// removed from the file and that any derivative work contains  ////
1692
//// the original copyright notice and the associated disclaimer. ////
1693
////                                                              ////
1694
//// This source file is free software; you can redistribute it   ////
1695
//// and/or modify it under the terms of the GNU Lesser General   ////
1696
//// Public License as published by the Free Software Foundation; ////
1697
//// either version 2.1 of the License, or (at your option) any   ////
1698
//// later version.                                               ////
1699
////                                                              ////
1700
//// This source is distributed in the hope that it will be       ////
1701
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1702
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1703
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1704
//// details.                                                     ////
1705
////                                                              ////
1706
//// You should have received a copy of the GNU Lesser General    ////
1707
//// Public License along with this source; if not, download it   ////
1708
//// from http://www.opencores.org/lgpl.shtml                     ////
1709
////                                                              ////
1710
//////////////////////////////////////////////////////////////////////
1711
 
1712
// binary counter
1713
 
1714 40 unneback
`define MODULE cnt_bin_ce_clear
1715
module `BASE`MODULE (
1716
`undef MODULE
1717
 clear, cke, q, rst, clk);
1718
 
1719 6 unneback
   parameter length = 4;
1720
   input clear;
1721
   input cke;
1722
   output [length:1] q;
1723
   input rst;
1724
   input clk;
1725
 
1726
   parameter clear_value = 0;
1727
   parameter set_value = 1;
1728
   parameter wrap_value = 0;
1729
   parameter level1_value = 15;
1730
 
1731
   reg  [length:1] qi;
1732
   wire [length:1] q_next;
1733
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1734
 
1735
   always @ (posedge clk or posedge rst)
1736
     if (rst)
1737
       qi <= {length{1'b0}};
1738
     else
1739
     if (cke)
1740
       qi <= q_next;
1741
 
1742
   assign q = qi;
1743
 
1744
endmodule
1745 40 unneback
`endif
1746
`ifdef CNT_BIN_CE_CLEAR_L1_L2
1747 6 unneback
//////////////////////////////////////////////////////////////////////
1748
////                                                              ////
1749
////  Versatile counter                                           ////
1750
////                                                              ////
1751
////  Description                                                 ////
1752
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1753
////  counter                                                     ////
1754
////                                                              ////
1755
////  To Do:                                                      ////
1756
////   - add LFSR with more taps                                  ////
1757
////                                                              ////
1758
////  Author(s):                                                  ////
1759
////      - Michael Unneback, unneback@opencores.org              ////
1760
////        ORSoC AB                                              ////
1761
////                                                              ////
1762
//////////////////////////////////////////////////////////////////////
1763
////                                                              ////
1764
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1765
////                                                              ////
1766
//// This source file may be used and distributed without         ////
1767
//// restriction provided that this copyright statement is not    ////
1768
//// removed from the file and that any derivative work contains  ////
1769
//// the original copyright notice and the associated disclaimer. ////
1770
////                                                              ////
1771
//// This source file is free software; you can redistribute it   ////
1772
//// and/or modify it under the terms of the GNU Lesser General   ////
1773
//// Public License as published by the Free Software Foundation; ////
1774
//// either version 2.1 of the License, or (at your option) any   ////
1775
//// later version.                                               ////
1776
////                                                              ////
1777
//// This source is distributed in the hope that it will be       ////
1778
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1779
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1780
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1781
//// details.                                                     ////
1782
////                                                              ////
1783
//// You should have received a copy of the GNU Lesser General    ////
1784
//// Public License along with this source; if not, download it   ////
1785
//// from http://www.opencores.org/lgpl.shtml                     ////
1786
////                                                              ////
1787
//////////////////////////////////////////////////////////////////////
1788
 
1789
// binary counter
1790 29 unneback
 
1791 40 unneback
`define MODULE cnt_bin_ce_clear_l1_l2
1792
module `BASE`MODULE (
1793
`undef MODULE
1794
 clear, cke, q, level1, level2, rst, clk);
1795
 
1796 29 unneback
   parameter length = 4;
1797
   input clear;
1798
   input cke;
1799
   output [length:1] q;
1800
   output reg level1;
1801
   output reg level2;
1802
   input rst;
1803
   input clk;
1804
 
1805
   parameter clear_value = 0;
1806
   parameter set_value = 1;
1807 30 unneback
   parameter wrap_value = 15;
1808
   parameter level1_value = 8;
1809
   parameter level2_value = 15;
1810 29 unneback
 
1811
   wire rew;
1812 30 unneback
   assign rew = 1'b0;
1813 29 unneback
   reg  [length:1] qi;
1814
   wire [length:1] q_next;
1815
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1816
 
1817
   always @ (posedge clk or posedge rst)
1818
     if (rst)
1819
       qi <= {length{1'b0}};
1820
     else
1821
     if (cke)
1822
       qi <= q_next;
1823
 
1824
   assign q = qi;
1825
 
1826
 
1827
    always @ (posedge clk or posedge rst)
1828
    if (rst)
1829
        level1 <= 1'b0;
1830
    else
1831
    if (cke)
1832
    if (clear)
1833
        level1 <= 1'b0;
1834
    else if (q_next == level1_value)
1835
        level1 <= 1'b1;
1836
    else if (qi == level1_value & rew)
1837
        level1 <= 1'b0;
1838
 
1839
    always @ (posedge clk or posedge rst)
1840
    if (rst)
1841
        level2 <= 1'b0;
1842
    else
1843
    if (cke)
1844
    if (clear)
1845
        level2 <= 1'b0;
1846
    else if (q_next == level2_value)
1847
        level2 <= 1'b1;
1848
    else if (qi == level2_value & rew)
1849
        level2 <= 1'b0;
1850
endmodule
1851 40 unneback
`endif
1852
`ifdef CNT_BIN_CE_CLEAR_SET_REW
1853 29 unneback
//////////////////////////////////////////////////////////////////////
1854
////                                                              ////
1855
////  Versatile counter                                           ////
1856
////                                                              ////
1857
////  Description                                                 ////
1858
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1859
////  counter                                                     ////
1860
////                                                              ////
1861
////  To Do:                                                      ////
1862
////   - add LFSR with more taps                                  ////
1863
////                                                              ////
1864
////  Author(s):                                                  ////
1865
////      - Michael Unneback, unneback@opencores.org              ////
1866
////        ORSoC AB                                              ////
1867
////                                                              ////
1868
//////////////////////////////////////////////////////////////////////
1869
////                                                              ////
1870
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1871
////                                                              ////
1872
//// This source file may be used and distributed without         ////
1873
//// restriction provided that this copyright statement is not    ////
1874
//// removed from the file and that any derivative work contains  ////
1875
//// the original copyright notice and the associated disclaimer. ////
1876
////                                                              ////
1877
//// This source file is free software; you can redistribute it   ////
1878
//// and/or modify it under the terms of the GNU Lesser General   ////
1879
//// Public License as published by the Free Software Foundation; ////
1880
//// either version 2.1 of the License, or (at your option) any   ////
1881
//// later version.                                               ////
1882
////                                                              ////
1883
//// This source is distributed in the hope that it will be       ////
1884
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1885
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1886
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1887
//// details.                                                     ////
1888
////                                                              ////
1889
//// You should have received a copy of the GNU Lesser General    ////
1890
//// Public License along with this source; if not, download it   ////
1891
//// from http://www.opencores.org/lgpl.shtml                     ////
1892
////                                                              ////
1893
//////////////////////////////////////////////////////////////////////
1894
 
1895
// binary counter
1896 6 unneback
 
1897 40 unneback
`define MODULE cnt_bin_ce_clear_set_rew
1898
module `BASE`MODULE (
1899
`undef MODULE
1900
 clear, set, cke, rew, q, rst, clk);
1901
 
1902 6 unneback
   parameter length = 4;
1903
   input clear;
1904
   input set;
1905
   input cke;
1906
   input rew;
1907
   output [length:1] q;
1908
   input rst;
1909
   input clk;
1910
 
1911
   parameter clear_value = 0;
1912
   parameter set_value = 1;
1913
   parameter wrap_value = 0;
1914
   parameter level1_value = 15;
1915
 
1916
   reg  [length:1] qi;
1917
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1918
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
1919
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
1920
   assign q_next = rew ? q_next_rew : q_next_fw;
1921
 
1922
   always @ (posedge clk or posedge rst)
1923
     if (rst)
1924
       qi <= {length{1'b0}};
1925
     else
1926
     if (cke)
1927
       qi <= q_next;
1928
 
1929
   assign q = qi;
1930
 
1931
endmodule
1932 40 unneback
`endif
1933
`ifdef CNT_BIN_CE_REW_L1
1934 6 unneback
//////////////////////////////////////////////////////////////////////
1935
////                                                              ////
1936
////  Versatile counter                                           ////
1937
////                                                              ////
1938
////  Description                                                 ////
1939
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1940
////  counter                                                     ////
1941
////                                                              ////
1942
////  To Do:                                                      ////
1943
////   - add LFSR with more taps                                  ////
1944
////                                                              ////
1945
////  Author(s):                                                  ////
1946
////      - Michael Unneback, unneback@opencores.org              ////
1947
////        ORSoC AB                                              ////
1948
////                                                              ////
1949
//////////////////////////////////////////////////////////////////////
1950
////                                                              ////
1951
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1952
////                                                              ////
1953
//// This source file may be used and distributed without         ////
1954
//// restriction provided that this copyright statement is not    ////
1955
//// removed from the file and that any derivative work contains  ////
1956
//// the original copyright notice and the associated disclaimer. ////
1957
////                                                              ////
1958
//// This source file is free software; you can redistribute it   ////
1959
//// and/or modify it under the terms of the GNU Lesser General   ////
1960
//// Public License as published by the Free Software Foundation; ////
1961
//// either version 2.1 of the License, or (at your option) any   ////
1962
//// later version.                                               ////
1963
////                                                              ////
1964
//// This source is distributed in the hope that it will be       ////
1965
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1966
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1967
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1968
//// details.                                                     ////
1969
////                                                              ////
1970
//// You should have received a copy of the GNU Lesser General    ////
1971
//// Public License along with this source; if not, download it   ////
1972
//// from http://www.opencores.org/lgpl.shtml                     ////
1973
////                                                              ////
1974
//////////////////////////////////////////////////////////////////////
1975
 
1976
// binary counter
1977
 
1978 40 unneback
`define MODULE cnt_bin_ce_rew_l1
1979
module `BASE`MODULE (
1980
`undef MODULE
1981
 cke, rew, level1, rst, clk);
1982
 
1983 6 unneback
   parameter length = 4;
1984
   input cke;
1985
   input rew;
1986
   output reg level1;
1987
   input rst;
1988
   input clk;
1989
 
1990
   parameter clear_value = 0;
1991
   parameter set_value = 1;
1992
   parameter wrap_value = 1;
1993
   parameter level1_value = 15;
1994
 
1995 29 unneback
   wire clear;
1996 30 unneback
   assign clear = 1'b0;
1997 6 unneback
   reg  [length:1] qi;
1998
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1999
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2000
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2001
   assign q_next = rew ? q_next_rew : q_next_fw;
2002
 
2003
   always @ (posedge clk or posedge rst)
2004
     if (rst)
2005
       qi <= {length{1'b0}};
2006
     else
2007
     if (cke)
2008
       qi <= q_next;
2009
 
2010
 
2011
 
2012
    always @ (posedge clk or posedge rst)
2013
    if (rst)
2014
        level1 <= 1'b0;
2015
    else
2016
    if (cke)
2017 29 unneback
    if (clear)
2018
        level1 <= 1'b0;
2019
    else if (q_next == level1_value)
2020 6 unneback
        level1 <= 1'b1;
2021
    else if (qi == level1_value & rew)
2022
        level1 <= 1'b0;
2023
endmodule
2024 40 unneback
`endif
2025
`ifdef CNT_BIN_CE_REW_ZQ_L1
2026 6 unneback
//////////////////////////////////////////////////////////////////////
2027
////                                                              ////
2028
////  Versatile counter                                           ////
2029
////                                                              ////
2030
////  Description                                                 ////
2031
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2032
////  counter                                                     ////
2033
////                                                              ////
2034
////  To Do:                                                      ////
2035
////   - add LFSR with more taps                                  ////
2036
////                                                              ////
2037
////  Author(s):                                                  ////
2038
////      - Michael Unneback, unneback@opencores.org              ////
2039
////        ORSoC AB                                              ////
2040
////                                                              ////
2041
//////////////////////////////////////////////////////////////////////
2042
////                                                              ////
2043
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2044
////                                                              ////
2045
//// This source file may be used and distributed without         ////
2046
//// restriction provided that this copyright statement is not    ////
2047
//// removed from the file and that any derivative work contains  ////
2048
//// the original copyright notice and the associated disclaimer. ////
2049
////                                                              ////
2050
//// This source file is free software; you can redistribute it   ////
2051
//// and/or modify it under the terms of the GNU Lesser General   ////
2052
//// Public License as published by the Free Software Foundation; ////
2053
//// either version 2.1 of the License, or (at your option) any   ////
2054
//// later version.                                               ////
2055
////                                                              ////
2056
//// This source is distributed in the hope that it will be       ////
2057
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2058
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2059
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2060
//// details.                                                     ////
2061
////                                                              ////
2062
//// You should have received a copy of the GNU Lesser General    ////
2063
//// Public License along with this source; if not, download it   ////
2064
//// from http://www.opencores.org/lgpl.shtml                     ////
2065
////                                                              ////
2066
//////////////////////////////////////////////////////////////////////
2067
 
2068 25 unneback
// binary counter
2069
 
2070 40 unneback
`define MODULE cnt_bin_ce_rew_zq_l1
2071
module `BASE`MODULE (
2072
`undef MODULE
2073
 cke, rew, zq, level1, rst, clk);
2074
 
2075 25 unneback
   parameter length = 4;
2076
   input cke;
2077
   input rew;
2078
   output reg zq;
2079
   output reg level1;
2080
   input rst;
2081
   input clk;
2082
 
2083
   parameter clear_value = 0;
2084
   parameter set_value = 1;
2085
   parameter wrap_value = 1;
2086
   parameter level1_value = 15;
2087
 
2088 29 unneback
   wire clear;
2089 30 unneback
   assign clear = 1'b0;
2090 25 unneback
   reg  [length:1] qi;
2091
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2092
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2093
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2094
   assign q_next = rew ? q_next_rew : q_next_fw;
2095
 
2096
   always @ (posedge clk or posedge rst)
2097
     if (rst)
2098
       qi <= {length{1'b0}};
2099
     else
2100
     if (cke)
2101
       qi <= q_next;
2102
 
2103
 
2104
 
2105
   always @ (posedge clk or posedge rst)
2106
     if (rst)
2107
       zq <= 1'b1;
2108
     else
2109
     if (cke)
2110
       zq <= q_next == {length{1'b0}};
2111
 
2112
    always @ (posedge clk or posedge rst)
2113
    if (rst)
2114
        level1 <= 1'b0;
2115
    else
2116
    if (cke)
2117 29 unneback
    if (clear)
2118
        level1 <= 1'b0;
2119
    else if (q_next == level1_value)
2120 25 unneback
        level1 <= 1'b1;
2121
    else if (qi == level1_value & rew)
2122
        level1 <= 1'b0;
2123
endmodule
2124 40 unneback
`endif
2125
`ifdef CNT_BIN_CE_REW_Q_ZQ_L1
2126 25 unneback
//////////////////////////////////////////////////////////////////////
2127
////                                                              ////
2128
////  Versatile counter                                           ////
2129
////                                                              ////
2130
////  Description                                                 ////
2131
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2132
////  counter                                                     ////
2133
////                                                              ////
2134
////  To Do:                                                      ////
2135
////   - add LFSR with more taps                                  ////
2136
////                                                              ////
2137
////  Author(s):                                                  ////
2138
////      - Michael Unneback, unneback@opencores.org              ////
2139
////        ORSoC AB                                              ////
2140
////                                                              ////
2141
//////////////////////////////////////////////////////////////////////
2142
////                                                              ////
2143
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2144
////                                                              ////
2145
//// This source file may be used and distributed without         ////
2146
//// restriction provided that this copyright statement is not    ////
2147
//// removed from the file and that any derivative work contains  ////
2148
//// the original copyright notice and the associated disclaimer. ////
2149
////                                                              ////
2150
//// This source file is free software; you can redistribute it   ////
2151
//// and/or modify it under the terms of the GNU Lesser General   ////
2152
//// Public License as published by the Free Software Foundation; ////
2153
//// either version 2.1 of the License, or (at your option) any   ////
2154
//// later version.                                               ////
2155
////                                                              ////
2156
//// This source is distributed in the hope that it will be       ////
2157
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2158
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2159
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2160
//// details.                                                     ////
2161
////                                                              ////
2162
//// You should have received a copy of the GNU Lesser General    ////
2163
//// Public License along with this source; if not, download it   ////
2164
//// from http://www.opencores.org/lgpl.shtml                     ////
2165
////                                                              ////
2166
//////////////////////////////////////////////////////////////////////
2167
 
2168
// binary counter
2169
 
2170 40 unneback
`define MODULE cnt_bin_ce_rew_q_zq_l1
2171
module `BASE`MODULE (
2172
`undef MODULE
2173
 cke, rew, q, zq, level1, rst, clk);
2174
 
2175 25 unneback
   parameter length = 4;
2176
   input cke;
2177
   input rew;
2178
   output [length:1] q;
2179
   output reg zq;
2180
   output reg level1;
2181
   input rst;
2182
   input clk;
2183
 
2184
   parameter clear_value = 0;
2185
   parameter set_value = 1;
2186
   parameter wrap_value = 1;
2187
   parameter level1_value = 15;
2188
 
2189 29 unneback
   wire clear;
2190 30 unneback
   assign clear = 1'b0;
2191 25 unneback
   reg  [length:1] qi;
2192
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2193
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2194
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2195
   assign q_next = rew ? q_next_rew : q_next_fw;
2196
 
2197
   always @ (posedge clk or posedge rst)
2198
     if (rst)
2199
       qi <= {length{1'b0}};
2200
     else
2201
     if (cke)
2202
       qi <= q_next;
2203
 
2204
   assign q = qi;
2205
 
2206
 
2207
   always @ (posedge clk or posedge rst)
2208
     if (rst)
2209
       zq <= 1'b1;
2210
     else
2211
     if (cke)
2212
       zq <= q_next == {length{1'b0}};
2213
 
2214
    always @ (posedge clk or posedge rst)
2215
    if (rst)
2216
        level1 <= 1'b0;
2217
    else
2218
    if (cke)
2219 29 unneback
    if (clear)
2220
        level1 <= 1'b0;
2221
    else if (q_next == level1_value)
2222 25 unneback
        level1 <= 1'b1;
2223
    else if (qi == level1_value & rew)
2224
        level1 <= 1'b0;
2225
endmodule
2226 40 unneback
`endif
2227
`ifdef CNT_LFSR_ZQ
2228 25 unneback
//////////////////////////////////////////////////////////////////////
2229
////                                                              ////
2230
////  Versatile counter                                           ////
2231
////                                                              ////
2232
////  Description                                                 ////
2233
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2234
////  counter                                                     ////
2235
////                                                              ////
2236
////  To Do:                                                      ////
2237
////   - add LFSR with more taps                                  ////
2238
////                                                              ////
2239
////  Author(s):                                                  ////
2240
////      - Michael Unneback, unneback@opencores.org              ////
2241
////        ORSoC AB                                              ////
2242
////                                                              ////
2243
//////////////////////////////////////////////////////////////////////
2244
////                                                              ////
2245
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2246
////                                                              ////
2247
//// This source file may be used and distributed without         ////
2248
//// restriction provided that this copyright statement is not    ////
2249
//// removed from the file and that any derivative work contains  ////
2250
//// the original copyright notice and the associated disclaimer. ////
2251
////                                                              ////
2252
//// This source file is free software; you can redistribute it   ////
2253
//// and/or modify it under the terms of the GNU Lesser General   ////
2254
//// Public License as published by the Free Software Foundation; ////
2255
//// either version 2.1 of the License, or (at your option) any   ////
2256
//// later version.                                               ////
2257
////                                                              ////
2258
//// This source is distributed in the hope that it will be       ////
2259
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2260
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2261
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2262
//// details.                                                     ////
2263
////                                                              ////
2264
//// You should have received a copy of the GNU Lesser General    ////
2265
//// Public License along with this source; if not, download it   ////
2266
//// from http://www.opencores.org/lgpl.shtml                     ////
2267
////                                                              ////
2268
//////////////////////////////////////////////////////////////////////
2269
 
2270 6 unneback
// LFSR counter
2271
 
2272 40 unneback
`define MODULE cnt_lfsr_zq
2273
module `BASE`MODULE (
2274
`undef MODULE
2275
 zq, rst, clk);
2276
 
2277 6 unneback
   parameter length = 4;
2278
   output reg zq;
2279
   input rst;
2280
   input clk;
2281
 
2282
   parameter clear_value = 0;
2283
   parameter set_value = 1;
2284
   parameter wrap_value = 8;
2285
   parameter level1_value = 15;
2286
 
2287
   reg  [length:1] qi;
2288
   reg lfsr_fb;
2289
   wire [length:1] q_next;
2290
   reg [32:1] polynom;
2291
   integer i;
2292
 
2293
   always @ (qi)
2294
   begin
2295
        case (length)
2296
         2: polynom = 32'b11;                               // 0x3
2297
         3: polynom = 32'b110;                              // 0x6
2298
         4: polynom = 32'b1100;                             // 0xC
2299
         5: polynom = 32'b10100;                            // 0x14
2300
         6: polynom = 32'b110000;                           // 0x30
2301
         7: polynom = 32'b1100000;                          // 0x60
2302
         8: polynom = 32'b10111000;                         // 0xb8
2303
         9: polynom = 32'b100010000;                        // 0x110
2304
        10: polynom = 32'b1001000000;                       // 0x240
2305
        11: polynom = 32'b10100000000;                      // 0x500
2306
        12: polynom = 32'b100000101001;                     // 0x829
2307
        13: polynom = 32'b1000000001100;                    // 0x100C
2308
        14: polynom = 32'b10000000010101;                   // 0x2015
2309
        15: polynom = 32'b110000000000000;                  // 0x6000
2310
        16: polynom = 32'b1101000000001000;                 // 0xD008
2311
        17: polynom = 32'b10010000000000000;                // 0x12000
2312
        18: polynom = 32'b100000010000000000;               // 0x20400
2313
        19: polynom = 32'b1000000000000100011;              // 0x40023
2314 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2315 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2316
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2317
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2318
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2319
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2320
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2321
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2322
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2323
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2324
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2325
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2326
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2327
        default: polynom = 32'b0;
2328
        endcase
2329
        lfsr_fb = qi[length];
2330
        for (i=length-1; i>=1; i=i-1) begin
2331
            if (polynom[i])
2332
                lfsr_fb = lfsr_fb  ~^ qi[i];
2333
        end
2334
    end
2335
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2336
 
2337
   always @ (posedge clk or posedge rst)
2338
     if (rst)
2339
       qi <= {length{1'b0}};
2340
     else
2341
       qi <= q_next;
2342
 
2343
 
2344
 
2345
   always @ (posedge clk or posedge rst)
2346
     if (rst)
2347
       zq <= 1'b1;
2348
     else
2349
       zq <= q_next == {length{1'b0}};
2350
endmodule
2351 40 unneback
`endif
2352
`ifdef CNT_LFSR_CE_ZQ
2353 6 unneback
//////////////////////////////////////////////////////////////////////
2354
////                                                              ////
2355
////  Versatile counter                                           ////
2356
////                                                              ////
2357
////  Description                                                 ////
2358
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2359
////  counter                                                     ////
2360
////                                                              ////
2361
////  To Do:                                                      ////
2362
////   - add LFSR with more taps                                  ////
2363
////                                                              ////
2364
////  Author(s):                                                  ////
2365
////      - Michael Unneback, unneback@opencores.org              ////
2366
////        ORSoC AB                                              ////
2367
////                                                              ////
2368
//////////////////////////////////////////////////////////////////////
2369
////                                                              ////
2370
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2371
////                                                              ////
2372
//// This source file may be used and distributed without         ////
2373
//// restriction provided that this copyright statement is not    ////
2374
//// removed from the file and that any derivative work contains  ////
2375
//// the original copyright notice and the associated disclaimer. ////
2376
////                                                              ////
2377
//// This source file is free software; you can redistribute it   ////
2378
//// and/or modify it under the terms of the GNU Lesser General   ////
2379
//// Public License as published by the Free Software Foundation; ////
2380
//// either version 2.1 of the License, or (at your option) any   ////
2381
//// later version.                                               ////
2382
////                                                              ////
2383
//// This source is distributed in the hope that it will be       ////
2384
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2385
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2386
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2387
//// details.                                                     ////
2388
////                                                              ////
2389
//// You should have received a copy of the GNU Lesser General    ////
2390
//// Public License along with this source; if not, download it   ////
2391
//// from http://www.opencores.org/lgpl.shtml                     ////
2392
////                                                              ////
2393
//////////////////////////////////////////////////////////////////////
2394
 
2395
// LFSR counter
2396
 
2397 40 unneback
`define MODULE cnt_lfsr_ce_zq
2398
module `BASE`MODULE (
2399
`undef MODULE
2400
 cke, zq, rst, clk);
2401
 
2402 6 unneback
   parameter length = 4;
2403
   input cke;
2404
   output reg zq;
2405
   input rst;
2406
   input clk;
2407
 
2408
   parameter clear_value = 0;
2409
   parameter set_value = 1;
2410
   parameter wrap_value = 8;
2411
   parameter level1_value = 15;
2412
 
2413
   reg  [length:1] qi;
2414
   reg lfsr_fb;
2415
   wire [length:1] q_next;
2416
   reg [32:1] polynom;
2417
   integer i;
2418
 
2419
   always @ (qi)
2420
   begin
2421
        case (length)
2422
         2: polynom = 32'b11;                               // 0x3
2423
         3: polynom = 32'b110;                              // 0x6
2424
         4: polynom = 32'b1100;                             // 0xC
2425
         5: polynom = 32'b10100;                            // 0x14
2426
         6: polynom = 32'b110000;                           // 0x30
2427
         7: polynom = 32'b1100000;                          // 0x60
2428
         8: polynom = 32'b10111000;                         // 0xb8
2429
         9: polynom = 32'b100010000;                        // 0x110
2430
        10: polynom = 32'b1001000000;                       // 0x240
2431
        11: polynom = 32'b10100000000;                      // 0x500
2432
        12: polynom = 32'b100000101001;                     // 0x829
2433
        13: polynom = 32'b1000000001100;                    // 0x100C
2434
        14: polynom = 32'b10000000010101;                   // 0x2015
2435
        15: polynom = 32'b110000000000000;                  // 0x6000
2436
        16: polynom = 32'b1101000000001000;                 // 0xD008
2437
        17: polynom = 32'b10010000000000000;                // 0x12000
2438
        18: polynom = 32'b100000010000000000;               // 0x20400
2439
        19: polynom = 32'b1000000000000100011;              // 0x40023
2440 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2441 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2442
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2443
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2444
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2445
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2446
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2447
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2448
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2449
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2450
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2451
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2452
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2453
        default: polynom = 32'b0;
2454
        endcase
2455
        lfsr_fb = qi[length];
2456
        for (i=length-1; i>=1; i=i-1) begin
2457
            if (polynom[i])
2458
                lfsr_fb = lfsr_fb  ~^ qi[i];
2459
        end
2460
    end
2461
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2462
 
2463
   always @ (posedge clk or posedge rst)
2464
     if (rst)
2465
       qi <= {length{1'b0}};
2466
     else
2467
     if (cke)
2468
       qi <= q_next;
2469
 
2470
 
2471
 
2472
   always @ (posedge clk or posedge rst)
2473
     if (rst)
2474
       zq <= 1'b1;
2475
     else
2476
     if (cke)
2477
       zq <= q_next == {length{1'b0}};
2478
endmodule
2479 40 unneback
`endif
2480
`ifdef CNT_LFSR_CE_Q
2481 6 unneback
//////////////////////////////////////////////////////////////////////
2482
////                                                              ////
2483
////  Versatile counter                                           ////
2484
////                                                              ////
2485
////  Description                                                 ////
2486
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2487
////  counter                                                     ////
2488
////                                                              ////
2489
////  To Do:                                                      ////
2490
////   - add LFSR with more taps                                  ////
2491
////                                                              ////
2492
////  Author(s):                                                  ////
2493
////      - Michael Unneback, unneback@opencores.org              ////
2494
////        ORSoC AB                                              ////
2495
////                                                              ////
2496
//////////////////////////////////////////////////////////////////////
2497
////                                                              ////
2498
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2499
////                                                              ////
2500
//// This source file may be used and distributed without         ////
2501
//// restriction provided that this copyright statement is not    ////
2502
//// removed from the file and that any derivative work contains  ////
2503
//// the original copyright notice and the associated disclaimer. ////
2504
////                                                              ////
2505
//// This source file is free software; you can redistribute it   ////
2506
//// and/or modify it under the terms of the GNU Lesser General   ////
2507
//// Public License as published by the Free Software Foundation; ////
2508
//// either version 2.1 of the License, or (at your option) any   ////
2509
//// later version.                                               ////
2510
////                                                              ////
2511
//// This source is distributed in the hope that it will be       ////
2512
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2513
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2514
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2515
//// details.                                                     ////
2516
////                                                              ////
2517
//// You should have received a copy of the GNU Lesser General    ////
2518
//// Public License along with this source; if not, download it   ////
2519
//// from http://www.opencores.org/lgpl.shtml                     ////
2520
////                                                              ////
2521
//////////////////////////////////////////////////////////////////////
2522 22 unneback
 
2523
// LFSR counter
2524 27 unneback
 
2525 40 unneback
`define MODULE cnt_lfsr_ce_q
2526
module `BASE`MODULE (
2527
`undef MODULE
2528
 cke, q, rst, clk);
2529
 
2530 27 unneback
   parameter length = 4;
2531
   input cke;
2532
   output [length:1] q;
2533
   input rst;
2534
   input clk;
2535
 
2536
   parameter clear_value = 0;
2537
   parameter set_value = 1;
2538
   parameter wrap_value = 8;
2539
   parameter level1_value = 15;
2540
 
2541
   reg  [length:1] qi;
2542
   reg lfsr_fb;
2543
   wire [length:1] q_next;
2544
   reg [32:1] polynom;
2545
   integer i;
2546
 
2547
   always @ (qi)
2548
   begin
2549
        case (length)
2550
         2: polynom = 32'b11;                               // 0x3
2551
         3: polynom = 32'b110;                              // 0x6
2552
         4: polynom = 32'b1100;                             // 0xC
2553
         5: polynom = 32'b10100;                            // 0x14
2554
         6: polynom = 32'b110000;                           // 0x30
2555
         7: polynom = 32'b1100000;                          // 0x60
2556
         8: polynom = 32'b10111000;                         // 0xb8
2557
         9: polynom = 32'b100010000;                        // 0x110
2558
        10: polynom = 32'b1001000000;                       // 0x240
2559
        11: polynom = 32'b10100000000;                      // 0x500
2560
        12: polynom = 32'b100000101001;                     // 0x829
2561
        13: polynom = 32'b1000000001100;                    // 0x100C
2562
        14: polynom = 32'b10000000010101;                   // 0x2015
2563
        15: polynom = 32'b110000000000000;                  // 0x6000
2564
        16: polynom = 32'b1101000000001000;                 // 0xD008
2565
        17: polynom = 32'b10010000000000000;                // 0x12000
2566
        18: polynom = 32'b100000010000000000;               // 0x20400
2567
        19: polynom = 32'b1000000000000100011;              // 0x40023
2568 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2569 27 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2570
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2571
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2572
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2573
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2574
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2575
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2576
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2577
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2578
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2579
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2580
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2581
        default: polynom = 32'b0;
2582
        endcase
2583
        lfsr_fb = qi[length];
2584
        for (i=length-1; i>=1; i=i-1) begin
2585
            if (polynom[i])
2586
                lfsr_fb = lfsr_fb  ~^ qi[i];
2587
        end
2588
    end
2589
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2590
 
2591
   always @ (posedge clk or posedge rst)
2592
     if (rst)
2593
       qi <= {length{1'b0}};
2594
     else
2595
     if (cke)
2596
       qi <= q_next;
2597
 
2598
   assign q = qi;
2599
 
2600
endmodule
2601 40 unneback
`endif
2602
`ifdef CNT_LFSR_CE_CLEAR_Q
2603 27 unneback
//////////////////////////////////////////////////////////////////////
2604
////                                                              ////
2605
////  Versatile counter                                           ////
2606
////                                                              ////
2607
////  Description                                                 ////
2608
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2609
////  counter                                                     ////
2610
////                                                              ////
2611
////  To Do:                                                      ////
2612
////   - add LFSR with more taps                                  ////
2613
////                                                              ////
2614
////  Author(s):                                                  ////
2615
////      - Michael Unneback, unneback@opencores.org              ////
2616
////        ORSoC AB                                              ////
2617
////                                                              ////
2618
//////////////////////////////////////////////////////////////////////
2619
////                                                              ////
2620
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2621
////                                                              ////
2622
//// This source file may be used and distributed without         ////
2623
//// restriction provided that this copyright statement is not    ////
2624
//// removed from the file and that any derivative work contains  ////
2625
//// the original copyright notice and the associated disclaimer. ////
2626
////                                                              ////
2627
//// This source file is free software; you can redistribute it   ////
2628
//// and/or modify it under the terms of the GNU Lesser General   ////
2629
//// Public License as published by the Free Software Foundation; ////
2630
//// either version 2.1 of the License, or (at your option) any   ////
2631
//// later version.                                               ////
2632
////                                                              ////
2633
//// This source is distributed in the hope that it will be       ////
2634
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2635
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2636
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2637
//// details.                                                     ////
2638
////                                                              ////
2639
//// You should have received a copy of the GNU Lesser General    ////
2640
//// Public License along with this source; if not, download it   ////
2641
//// from http://www.opencores.org/lgpl.shtml                     ////
2642
////                                                              ////
2643
//////////////////////////////////////////////////////////////////////
2644
 
2645
// LFSR counter
2646
 
2647 40 unneback
`define MODULE cnt_lfsr_ce_clear_q
2648
module `BASE`MODULE (
2649
`undef MODULE
2650
 clear, cke, q, rst, clk);
2651
 
2652 27 unneback
   parameter length = 4;
2653
   input clear;
2654
   input cke;
2655
   output [length:1] q;
2656
   input rst;
2657
   input clk;
2658
 
2659
   parameter clear_value = 0;
2660
   parameter set_value = 1;
2661
   parameter wrap_value = 8;
2662
   parameter level1_value = 15;
2663
 
2664
   reg  [length:1] qi;
2665
   reg lfsr_fb;
2666
   wire [length:1] q_next;
2667
   reg [32:1] polynom;
2668
   integer i;
2669
 
2670
   always @ (qi)
2671
   begin
2672
        case (length)
2673
         2: polynom = 32'b11;                               // 0x3
2674
         3: polynom = 32'b110;                              // 0x6
2675
         4: polynom = 32'b1100;                             // 0xC
2676
         5: polynom = 32'b10100;                            // 0x14
2677
         6: polynom = 32'b110000;                           // 0x30
2678
         7: polynom = 32'b1100000;                          // 0x60
2679
         8: polynom = 32'b10111000;                         // 0xb8
2680
         9: polynom = 32'b100010000;                        // 0x110
2681
        10: polynom = 32'b1001000000;                       // 0x240
2682
        11: polynom = 32'b10100000000;                      // 0x500
2683
        12: polynom = 32'b100000101001;                     // 0x829
2684
        13: polynom = 32'b1000000001100;                    // 0x100C
2685
        14: polynom = 32'b10000000010101;                   // 0x2015
2686
        15: polynom = 32'b110000000000000;                  // 0x6000
2687
        16: polynom = 32'b1101000000001000;                 // 0xD008
2688
        17: polynom = 32'b10010000000000000;                // 0x12000
2689
        18: polynom = 32'b100000010000000000;               // 0x20400
2690
        19: polynom = 32'b1000000000000100011;              // 0x40023
2691 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
2692 27 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
2693
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2694
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2695
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2696
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2697
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2698
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2699
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2700
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2701
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2702
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2703
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2704
        default: polynom = 32'b0;
2705
        endcase
2706
        lfsr_fb = qi[length];
2707
        for (i=length-1; i>=1; i=i-1) begin
2708
            if (polynom[i])
2709
                lfsr_fb = lfsr_fb  ~^ qi[i];
2710
        end
2711
    end
2712
   assign q_next =  clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2713
 
2714
   always @ (posedge clk or posedge rst)
2715
     if (rst)
2716
       qi <= {length{1'b0}};
2717
     else
2718
     if (cke)
2719
       qi <= q_next;
2720
 
2721
   assign q = qi;
2722
 
2723
endmodule
2724 40 unneback
`endif
2725
`ifdef CNT_LFSR_CE_Q_ZQ
2726 27 unneback
//////////////////////////////////////////////////////////////////////
2727
////                                                              ////
2728
////  Versatile counter                                           ////
2729
////                                                              ////
2730
////  Description                                                 ////
2731
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2732
////  counter                                                     ////
2733
////                                                              ////
2734
////  To Do:                                                      ////
2735
////   - add LFSR with more taps                                  ////
2736
////                                                              ////
2737
////  Author(s):                                                  ////
2738
////      - Michael Unneback, unneback@opencores.org              ////
2739
////        ORSoC AB                                              ////
2740
////                                                              ////
2741
//////////////////////////////////////////////////////////////////////
2742
////                                                              ////
2743
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2744
////                                                              ////
2745
//// This source file may be used and distributed without         ////
2746
//// restriction provided that this copyright statement is not    ////
2747
//// removed from the file and that any derivative work contains  ////
2748
//// the original copyright notice and the associated disclaimer. ////
2749
////                                                              ////
2750
//// This source file is free software; you can redistribute it   ////
2751
//// and/or modify it under the terms of the GNU Lesser General   ////
2752
//// Public License as published by the Free Software Foundation; ////
2753
//// either version 2.1 of the License, or (at your option) any   ////
2754
//// later version.                                               ////
2755
////                                                              ////
2756
//// This source is distributed in the hope that it will be       ////
2757
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2758
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2759
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2760
//// details.                                                     ////
2761
////                                                              ////
2762
//// You should have received a copy of the GNU Lesser General    ////
2763
//// Public License along with this source; if not, download it   ////
2764
//// from http://www.opencores.org/lgpl.shtml                     ////
2765
////                                                              ////
2766
//////////////////////////////////////////////////////////////////////
2767
 
2768
// LFSR counter
2769 22 unneback
 
2770 40 unneback
`define MODULE cnt_lfsr_ce_q_zq
2771
module `BASE`MODULE (
2772
`undef MODULE
2773
 cke, q, zq, rst, clk);
2774
 
2775 22 unneback
   parameter length = 4;
2776
   input cke;
2777
   output [length:1] q;
2778
   output reg zq;
2779
   input rst;
2780
   input clk;
2781
 
2782
   parameter clear_value = 0;
2783
   parameter set_value = 1;
2784
   parameter wrap_value = 8;
2785
   parameter level1_value = 15;
2786
 
2787
   reg  [length:1] qi;
2788
   reg lfsr_fb;
2789
   wire [length:1] q_next;
2790
   reg [32:1] polynom;
2791
   integer i;
2792
 
2793
   always @ (qi)
2794
   begin
2795
        case (length)
2796
         2: polynom = 32'b11;                               // 0x3
2797
         3: polynom = 32'b110;                              // 0x6
2798
         4: polynom = 32'b1100;                             // 0xC
2799
         5: polynom = 32'b10100;                            // 0x14
2800
         6: polynom = 32'b110000;                           // 0x30
2801
         7: polynom = 32'b1100000;                          // 0x60
2802
         8: polynom = 32'b10111000;                         // 0xb8
2803
         9: polynom = 32'b100010000;                        // 0x110
2804
        10: polynom = 32'b1001000000;                       // 0x240
2805
        11: polynom = 32'b10100000000;                      // 0x500
2806
        12: polynom = 32'b100000101001;                     // 0x829
2807
        13: polynom = 32'b1000000001100