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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Blame information for rev 81

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Line No. Rev Author Line
1 40 unneback 
`ifndef BASE
2 
`define BASE vl_
3 
`endif
4 
 
5 60 unneback 
// default SYN_KEEP definition
6 
`define SYN_KEEP /*synthesis syn_keep = 1*/
7 
 
8 44 unneback 
`ifdef ACTEL
9 60 unneback 
`undef SYN_KEEP
10 44 unneback 
`define SYN_KEEP /*synthesis syn_keep = 1*/
11 
`endif
12 
 
13 40 unneback 
`ifdef ALL
14 
 
15 
`define GBUF
16 
`define SYNC_RST
17 
`define PLL
18 
 
19 
`define MULTS
20 
`define MULTS18X18
21 
`define MULT
22 
`define SHIFT_UNIT_32
23 
`define LOGIC_UNIT
24 
 
25 
`define CNT_SHREG_WRAP
26 
`define CNT_SHREG_CE_WRAP
27 
`define CNT_SHREG_CE_CLEAR
28 
`define CNT_SHREG_CE_CLEAR_WRAP
29 
 
30 
`define MUX_ANDOR
31 
`define MUX2_ANDOR
32 
`define MUX3_ANDOR
33 
`define MUX4_ANDOR
34 
`define MUX5_ANDOR
35 
`define MUX6_ANDOR
36 43 unneback 
`define PARITY
37 40 unneback 
 
38 
`define ROM_INIT
39 
`define RAM
40 
`define RAM_BE
41 
`define DPRAM_1R1W
42 
`define DPRAM_2R1W
43 
`define DPRAM_2R2W
44 75 unneback 
`define DPRAM_BE_2R2W
45 40 unneback 
`define FIFO_1R1W_FILL_LEVEL_SYNC
46 
`define FIFO_2R2W_SYNC_SIMPLEX
47 
`define FIFO_CMP_ASYNC
48 
`define FIFO_1R1W_ASYNC
49 
`define FIFO_2R2W_ASYNC
50 
`define FIFO_2R2W_ASYNC_SIMPLEX
51 48 unneback 
`define REG_FILE
52 40 unneback 
 
53 
`define DFF
54 
`define DFF_ARRAY
55 
`define DFF_CE
56 
`define DFF_CE_CLEAR
57 
`define DF_CE_SET
58 
`define SPR
59 
`define SRP
60 
`define DFF_SR
61 
`define LATCH
62 
`define SHREG
63 
`define SHREG_CE
64 
`define DELAY
65 
`define DELAY_EMPTYFLAG
66 
 
67 75 unneback 
`define WB3AVALON_BRIDGE
68 40 unneback 
`define WB3WB3_BRIDGE
69 
`define WB3_ARBITER_TYPE1
70 59 unneback 
`define WB_B3_RAM_BE
71 49 unneback 
`define WB_B4_RAM_BE
72 48 unneback 
`define WB_B4_ROM
73 40 unneback 
`define WB_BOOT_ROM
74 
`define WB_DPRAM
75 
 
76 44 unneback 
`define IO_DFF_OE
77 
`define O_DFF
78 
 
79 40 unneback 
`endif
80 
 
81 
`ifdef PLL
82 
`ifndef SYNC_RST
83 
`define SYNC_RST
84 
`endif
85 
`endif
86 
 
87 
`ifdef SYNC_RST
88 
`ifndef GBUF
89 
`define GBUF
90 
`endif
91 
`endif
92 
 
93 
`ifdef WB_DPRAM
94 
`ifndef DPRAM_2R2W
95 
`define DPRAM_2R2W
96 
`endif
97 
`ifndef SPR
98 
`define SPR
99 
`endif
100 
`endif
101 
 
102 62 unneback 
`ifdef WB_B3_RAM_BE
103 
`ifndef WB3_ARBITER_TYPE1
104 
`define WB3_ARBITER_TYPE1
105 
`endif
106 
`ifndef RAM_BE
107 
`define RAM_BE
108 
`endif
109 
`endif
110 
 
111 40 unneback 
`ifdef WB3_ARBITER_TYPE1
112 42 unneback 
`ifndef SPR
113 
`define SPR
114 
`endif
115 40 unneback 
`ifndef MUX_ANDOR
116 
`define MUX_ANDOR
117 
`endif
118 
`endif
119 
 
120 76 unneback 
`ifdef WB3AVALON_BRIDGE
121 
`ifndef WB3WB3_BRIDGE
122 
`define WB3WB3_BRIDGE
123 
`endif
124 
`endif
125 
 
126 40 unneback 
`ifdef WB3WB3_BRIDGE
127 
`ifndef CNT_SHREG_CE_CLEAR
128 
`define CNT_SHREG_CE_CLEAR
129 
`endif
130 
`ifndef DFF
131 
`define DFF
132 
`endif
133 
`ifndef DFF_CE
134 
`define DFF_CE
135 
`endif
136 
`ifndef CNT_SHREG_CE_CLEAR
137 
`define CNT_SHREG_CE_CLEAR
138 
`endif
139 
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
140 
`define FIFO_2R2W_ASYNC_SIMPLEX
141 
`endif
142 
`endif
143 
 
144 
`ifdef MULTS18X18
145 
`ifndef MULTS
146 
`define MULTS
147 
`endif
148 
`endif
149 
 
150 
`ifdef SHIFT_UNIT_32
151 
`ifndef MULTS
152 
`define MULTS
153 
`endif
154 
`endif
155 
 
156 
`ifdef MUX2_ANDOR
157 
`ifndef MUX_ANDOR
158 
`define MUX_ANDOR
159 
`endif
160 
`endif
161 
 
162 
`ifdef MUX3_ANDOR
163 
`ifndef MUX_ANDOR
164 
`define MUX_ANDOR
165 
`endif
166 
`endif
167 
 
168 
`ifdef MUX4_ANDOR
169 
`ifndef MUX_ANDOR
170 
`define MUX_ANDOR
171 
`endif
172 
`endif
173 
 
174 
`ifdef MUX5_ANDOR
175 
`ifndef MUX_ANDOR
176 
`define MUX_ANDOR
177 
`endif
178 
`endif
179 
 
180 
`ifdef MUX6_ANDOR
181 
`ifndef MUX_ANDOR
182 
`define MUX_ANDOR
183 
`endif
184 
`endif
185 
 
186 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
187 
`ifndef CNT_BIN_CE
188 
`define CNT_BIN_CE
189 
`endif
190 
`ifndef DPRAM_1R1W
191 
`define DPRAM_1R1W
192 
`endif
193 
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
194 
`define CNT_BIN_CE_REW_Q_ZQ_L1
195 
`endif
196 
`endif
197 
 
198 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
199 
`ifndef CNT_LFSR_CE
200 
`define CNT_LFSR_CE
201 
`endif
202 
`ifndef DPRAM_2R2W
203 
`define DPRAM_2R2W
204 
`endif
205 
`ifndef CNT_BIN_CE_REW_ZQ_L1
206 
`define CNT_BIN_CE_REW_ZQ_L1
207 
`endif
208 
`endif
209 
 
210 
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
211 
`ifndef CNT_GRAY_CE_BIN
212 
`define CNT_GRAY_CE_BIN
213 
`endif
214 
`ifndef DPRAM_2R2W
215 
`define DPRAM_2R2W
216 
`endif
217 
`ifndef FIFO_CMP_ASYNC
218 
`define FIFO_CMP_ASYNC
219 
`endif
220 
`endif
221 
 
222 
`ifdef FIFO_2R2W_ASYNC
223 
`ifndef FIFO_1R1W_ASYNC
224 
`define FIFO_1R1W_ASYNC
225 
`endif
226 
`endif
227 
 
228 
`ifdef FIFO_1R1W_ASYNC
229 
`ifndef CNT_GRAY_CE_BIN
230 
`define CNT_GRAY_CE_BIN
231 
`endif
232 
`ifndef DPRAM_1R1W
233 
`define DPRAM_1R1W
234 
`endif
235 
`ifndef FIFO_CMP_ASYNC
236 
`define FIFO_CMP_ASYNC
237 
`endif
238 
`endif
239 
 
240 
`ifdef FIFO_CMP_ASYNC
241 
`ifndef DFF_SR
242 
`define DFF_SR
243 
`endif
244 
`ifndef DFF
245 
`define DFF
246 
`endif
247 
`endif
248 48 unneback 
 
249 
`ifdef REG_FILE
250 
`ifndef DPRAM_1R1W
251 
`define DPRAM_1R1W
252 
`endif
253 
`endif
254 62 unneback 
//////////////////////////////////////////////////////////////////////
255 6 unneback 
////                                                              ////
256 
////  Versatile library, clock and reset                          ////
257 
////                                                              ////
258 
////  Description                                                 ////
259 
////  Logic related to clock and reset                            ////
260 
////                                                              ////
261 
////                                                              ////
262 
////  To Do:                                                      ////
263 
////   - add more different registers                             ////
264 
////                                                              ////
265 
////  Author(s):                                                  ////
266 
////      - Michael Unneback, unneback@opencores.org              ////
267 
////        ORSoC AB                                              ////
268 
////                                                              ////
269 
//////////////////////////////////////////////////////////////////////
270 
////                                                              ////
271 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
272 
////                                                              ////
273 
//// This source file may be used and distributed without         ////
274 
//// restriction provided that this copyright statement is not    ////
275 
//// removed from the file and that any derivative work contains  ////
276 
//// the original copyright notice and the associated disclaimer. ////
277 
////                                                              ////
278 
//// This source file is free software; you can redistribute it   ////
279 
//// and/or modify it under the terms of the GNU Lesser General   ////
280 
//// Public License as published by the Free Software Foundation; ////
281 
//// either version 2.1 of the License, or (at your option) any   ////
282 
//// later version.                                               ////
283 
////                                                              ////
284 
//// This source is distributed in the hope that it will be       ////
285 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
286 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
287 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
288 
//// details.                                                     ////
289 
////                                                              ////
290 
//// You should have received a copy of the GNU Lesser General    ////
291 
//// Public License along with this source; if not, download it   ////
292 
//// from http://www.opencores.org/lgpl.shtml                     ////
293 
////                                                              ////
294 
//////////////////////////////////////////////////////////////////////
295 
 
296 48 unneback 
`ifdef ACTEL
297 
`ifdef GBUF
298 
`timescale 1 ns/100 ps
299 6 unneback 
// Global buffer
300 
// usage:
301 
// use to enable global buffers for high fan out signals such as clock and reset
302 
// Version: 8.4 8.4.0.33
303 
module gbuf(GL,CLK);
304 
output GL;
305 
input  CLK;
306 
 
307 
    wire GND;
308 
 
309 
    GND GND_1_net(.Y(GND));
310 
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
311 
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
312 
 
313 
endmodule
314 
`timescale 1 ns/1 ns
315 40 unneback 
`define MODULE gbuf
316 
module `BASE`MODULE ( i, o);
317 
`undef MODULE
318 6 unneback 
input i;
319 
output o;
320 
`ifdef SIM_GBUF
321 
assign o=i;
322 
`else
323 
gbuf gbuf_i0 ( .CLK(i), .GL(o));
324 
`endif
325 
endmodule
326 40 unneback 
`endif
327 33 unneback 
 
328 6 unneback 
`else
329 33 unneback 
 
330 40 unneback 
`ifdef ALTERA
331 
`ifdef GBUF
332 21 unneback 
//altera
333 40 unneback 
`define MODULE gbuf
334 
module `BASE`MODULE ( i, o);
335 
`undef MODULE
336 33 unneback 
input i;
337 
output o;
338 
assign o = i;
339 
endmodule
340 40 unneback 
`endif
341 33 unneback 
 
342 6 unneback 
`else
343 
 
344 40 unneback 
`ifdef GBUF
345 6 unneback 
`timescale 1 ns/100 ps
346 40 unneback 
`define MODULE
347 
module `BASE`MODULE ( i, o);
348 
`undef MODULE
349 6 unneback 
input i;
350 
output o;
351 
assign o = i;
352 
endmodule
353 40 unneback 
`endif
354 6 unneback 
`endif // ALTERA
355 
`endif //ACTEL
356 
 
357 40 unneback 
`ifdef SYNC_RST
358 6 unneback 
// sync reset
359 17 unneback 
// input active lo async reset, normally from external reset generator and/or switch
360 6 unneback 
// output active high global reset sync with two DFFs
361 
`timescale 1 ns/100 ps
362 40 unneback 
`define MODULE sync_rst
363 
module `BASE`MODULE ( rst_n_i, rst_o, clk);
364 
`undef MODULE
365 6 unneback 
input rst_n_i, clk;
366 
output rst_o;
367 18 unneback 
reg [1:0] tmp;
368 6 unneback 
always @ (posedge clk or negedge rst_n_i)
369 
if (!rst_n_i)
370 17 unneback 
        tmp <= 2'b11;
371 6 unneback 
else
372 33 unneback 
        tmp <= {1'b0,tmp[1]};
373 40 unneback 
`define MODULE gbuf
374 
`BASE`MODULE buf_i0( .i(tmp[0]), .o(rst_o));
375 
`undef MODULE
376 6 unneback 
endmodule
377 40 unneback 
`endif
378 6 unneback 
 
379 40 unneback 
`ifdef PLL
380 6 unneback 
// vl_pll
381 
`ifdef ACTEL
382 32 unneback 
///////////////////////////////////////////////////////////////////////////////
383 17 unneback 
`timescale 1 ps/1 ps
384 40 unneback 
`define MODULE pll
385 
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
386 
`undef MODULE
387 6 unneback 
parameter index = 0;
388 
parameter number_of_clk = 1;
389 17 unneback 
parameter period_time_0 = 20000;
390 
parameter period_time_1 = 20000;
391 
parameter period_time_2 = 20000;
392 
parameter lock_delay = 2000000;
393 6 unneback 
input clk_i, rst_n_i;
394 
output lock;
395 
output reg [0:number_of_clk-1] clk_o;
396 
output [0:number_of_clk-1] rst_o;
397 
 
398 
`ifdef SIM_PLL
399 
 
400 
always
401 
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
402 
 
403 
generate if (number_of_clk > 1)
404 
always
405 
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
406 
endgenerate
407 
 
408 
generate if (number_of_clk > 2)
409 
always
410 
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
411 
endgenerate
412 
 
413 
genvar i;
414 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
415 
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
416 
end
417 
endgenerate
418 
 
419 
assign #lock_delay lock = rst_n_i;
420 
 
421 
endmodule
422 
`else
423 
generate if (number_of_clk==1 & index==0) begin
424 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
425 
end
426 
endgenerate // index==0
427 
generate if (number_of_clk==1 & index==1) begin
428 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
429 
end
430 
endgenerate // index==1
431 
generate if (number_of_clk==1 & index==2) begin
432 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
433 
end
434 
endgenerate // index==2
435 
generate if (number_of_clk==1 & index==3) begin
436 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
437 
end
438 
endgenerate // index==0
439 
 
440 
generate if (number_of_clk==2 & index==0) begin
441 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
442 
end
443 
endgenerate // index==0
444 
generate if (number_of_clk==2 & index==1) begin
445 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
446 
end
447 
endgenerate // index==1
448 
generate if (number_of_clk==2 & index==2) begin
449 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
450 
end
451 
endgenerate // index==2
452 
generate if (number_of_clk==2 & index==3) begin
453 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
454 
end
455 
endgenerate // index==0
456 
 
457 
generate if (number_of_clk==3 & index==0) begin
458 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
459 
end
460 
endgenerate // index==0
461 
generate if (number_of_clk==3 & index==1) begin
462 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
463 
end
464 
endgenerate // index==1
465 
generate if (number_of_clk==3 & index==2) begin
466 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
467 
end
468 
endgenerate // index==2
469 
generate if (number_of_clk==3 & index==3) begin
470 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
471 
end
472 
endgenerate // index==0
473 
 
474 
genvar i;
475 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
476 40 unneback 
`define MODULE sync_rst
477 
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
478 
`undef MODULE
479 6 unneback 
end
480 
endgenerate
481 
endmodule
482 
`endif
483 32 unneback 
///////////////////////////////////////////////////////////////////////////////
484 6 unneback 
 
485 
`else
486 
 
487 32 unneback 
///////////////////////////////////////////////////////////////////////////////
488 6 unneback 
`ifdef ALTERA
489 
 
490 32 unneback 
`timescale 1 ps/1 ps
491 40 unneback 
`define MODULE pll
492 
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
493 
`undef MODULE
494 32 unneback 
parameter index = 0;
495 
parameter number_of_clk = 1;
496 
parameter period_time_0 = 20000;
497 
parameter period_time_1 = 20000;
498 
parameter period_time_2 = 20000;
499 
parameter period_time_3 = 20000;
500 
parameter period_time_4 = 20000;
501 
parameter lock_delay = 2000000;
502 
input clk_i, rst_n_i;
503 
output lock;
504 
output reg [0:number_of_clk-1] clk_o;
505 
output [0:number_of_clk-1] rst_o;
506 
 
507 
`ifdef SIM_PLL
508 
 
509 
always
510 
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
511 
 
512 
generate if (number_of_clk > 1)
513 
always
514 
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
515 
endgenerate
516 
 
517 
generate if (number_of_clk > 2)
518 
always
519 
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
520 
endgenerate
521 
 
522 33 unneback 
generate if (number_of_clk > 3)
523 32 unneback 
always
524 
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
525 
endgenerate
526 
 
527 33 unneback 
generate if (number_of_clk > 4)
528 32 unneback 
always
529 
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
530 
endgenerate
531 
 
532 
genvar i;
533 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
534 
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
535 
end
536 
endgenerate
537 
 
538 33 unneback 
//assign #lock_delay lock = rst_n_i;
539 
assign lock = rst_n_i;
540 32 unneback 
 
541 
endmodule
542 6 unneback 
`else
543 
 
544 33 unneback 
`ifdef VL_PLL0
545 
`ifdef VL_PLL0_CLK1
546 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
547 
`endif
548 
`ifdef VL_PLL0_CLK2
549 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
550 
`endif
551 
`ifdef VL_PLL0_CLK3
552 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
553 
`endif
554 
`ifdef VL_PLL0_CLK4
555 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
556 
`endif
557 
`ifdef VL_PLL0_CLK5
558 
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
559 
`endif
560 
`endif
561 32 unneback 
 
562 33 unneback 
`ifdef VL_PLL1
563 
`ifdef VL_PLL1_CLK1
564 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
565 
`endif
566 
`ifdef VL_PLL1_CLK2
567 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
568 
`endif
569 
`ifdef VL_PLL1_CLK3
570 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
571 
`endif
572 
`ifdef VL_PLL1_CLK4
573 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
574 
`endif
575 
`ifdef VL_PLL1_CLK5
576 
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
577 
`endif
578 
`endif
579 32 unneback 
 
580 33 unneback 
`ifdef VL_PLL2
581 
`ifdef VL_PLL2_CLK1
582 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
583 
`endif
584 
`ifdef VL_PLL2_CLK2
585 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
586 
`endif
587 
`ifdef VL_PLL2_CLK3
588 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
589 
`endif
590 
`ifdef VL_PLL2_CLK4
591 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
592 
`endif
593 
`ifdef VL_PLL2_CLK5
594 
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
595 
`endif
596 
`endif
597 32 unneback 
 
598 33 unneback 
`ifdef VL_PLL3
599 
`ifdef VL_PLL3_CLK1
600 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
601 
`endif
602 
`ifdef VL_PLL3_CLK2
603 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
604 
`endif
605 
`ifdef VL_PLL3_CLK3
606 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
607 
`endif
608 
`ifdef VL_PLL3_CLK4
609 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
610 
`endif
611 
`ifdef VL_PLL3_CLK5
612 
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
613 
`endif
614 
`endif
615 32 unneback 
 
616 
genvar i;
617 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
618 40 unneback 
`define MODULE sync_rst
619 
        `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
620 
`undef MODULE
621 32 unneback 
end
622 
endgenerate
623 
endmodule
624 
`endif
625 
///////////////////////////////////////////////////////////////////////////////
626 
 
627 
`else
628 
 
629 6 unneback 
// generic PLL
630 17 unneback 
`timescale 1 ps/1 ps
631 40 unneback 
`define MODULE pll
632 
module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o);
633 
`undef MODULE
634 6 unneback 
parameter index = 0;
635 
parameter number_of_clk = 1;
636 17 unneback 
parameter period_time_0 = 20000;
637 
parameter period_time_1 = 20000;
638 
parameter period_time_2 = 20000;
639 6 unneback 
parameter lock_delay = 2000;
640 
input clk_i, rst_n_i;
641 
output lock;
642 
output reg [0:number_of_clk-1] clk_o;
643 
output [0:number_of_clk-1] rst_o;
644 
 
645 
always
646 
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
647 
 
648 
generate if (number_of_clk > 1)
649 
always
650 
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
651 
endgenerate
652 
 
653 
generate if (number_of_clk > 2)
654 
always
655 
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
656 
endgenerate
657 
 
658 
genvar i;
659 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
660 40 unneback 
`define MODULE sync_rst
661 
     `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
662 
`undef MODULE
663 6 unneback 
end
664 
endgenerate
665 
 
666 
assign #lock_delay lock = rst_n_i;
667 
 
668 
endmodule
669 
 
670 
`endif //altera
671 17 unneback 
`endif //actel
672 40 unneback 
`undef MODULE
673 
`endif//////////////////////////////////////////////////////////////////////
674 6 unneback 
////                                                              ////
675 
////  Versatile library, registers                                ////
676 
////                                                              ////
677 
////  Description                                                 ////
678 
////  Different type of registers                                 ////
679 
////                                                              ////
680 
////                                                              ////
681 
////  To Do:                                                      ////
682 
////   - add more different registers                             ////
683 
////                                                              ////
684 
////  Author(s):                                                  ////
685 
////      - Michael Unneback, unneback@opencores.org              ////
686 
////        ORSoC AB                                              ////
687 
////                                                              ////
688 
//////////////////////////////////////////////////////////////////////
689 
////                                                              ////
690 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
691 
////                                                              ////
692 
//// This source file may be used and distributed without         ////
693 
//// restriction provided that this copyright statement is not    ////
694 
//// removed from the file and that any derivative work contains  ////
695 
//// the original copyright notice and the associated disclaimer. ////
696 
////                                                              ////
697 
//// This source file is free software; you can redistribute it   ////
698 
//// and/or modify it under the terms of the GNU Lesser General   ////
699 
//// Public License as published by the Free Software Foundation; ////
700 
//// either version 2.1 of the License, or (at your option) any   ////
701 
//// later version.                                               ////
702 
////                                                              ////
703 
//// This source is distributed in the hope that it will be       ////
704 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
705 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
706 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
707 
//// details.                                                     ////
708 
////                                                              ////
709 
//// You should have received a copy of the GNU Lesser General    ////
710 
//// Public License along with this source; if not, download it   ////
711 
//// from http://www.opencores.org/lgpl.shtml                     ////
712 
////                                                              ////
713 
//////////////////////////////////////////////////////////////////////
714 
 
715 40 unneback 
`ifdef DFF
716 
`define MODULE dff
717 
module `BASE`MODULE ( d, q, clk, rst);
718 
`undef MODULE
719 6 unneback 
        parameter width = 1;
720 
        parameter reset_value = 0;
721 
 
722 
        input [width-1:0] d;
723 
        input clk, rst;
724 
        output reg [width-1:0] q;
725 
 
726 
        always @ (posedge clk or posedge rst)
727 
        if (rst)
728 
                q <= reset_value;
729 
        else
730 
                q <= d;
731 
 
732 
endmodule
733 40 unneback 
`endif
734 6 unneback 
 
735 40 unneback 
`ifdef DFF_ARRAY
736 
`define MODULE dff_array
737 
module `BASE`MODULE ( d, q, clk, rst);
738 
`undef MODULE
739 6 unneback 
 
740 
        parameter width = 1;
741 
        parameter depth = 2;
742 
        parameter reset_value = 1'b0;
743 
 
744 
        input [width-1:0] d;
745 
        input clk, rst;
746 
        output [width-1:0] q;
747 
        reg  [0:depth-1] q_tmp [width-1:0];
748 
        integer i;
749 
        always @ (posedge clk or posedge rst)
750 
        if (rst) begin
751 
            for (i=0;i<depth;i=i+1)
752 
                q_tmp[i] <= {width{reset_value}};
753 
        end else begin
754 
            q_tmp[0] <= d;
755 
            for (i=1;i<depth;i=i+1)
756 
                q_tmp[i] <= q_tmp[i-1];
757 
        end
758 
 
759 
    assign q = q_tmp[depth-1];
760 
 
761 
endmodule
762 40 unneback 
`endif
763 6 unneback 
 
764 40 unneback 
`ifdef DFF_CE
765 
`define MODULE dff_ce
766 
module `BASE`MODULE ( d, ce, q, clk, rst);
767 
`undef MODULE
768 6 unneback 
 
769 
        parameter width = 1;
770 
        parameter reset_value = 0;
771 
 
772 
        input [width-1:0] d;
773 
        input ce, clk, rst;
774 
        output reg [width-1:0] q;
775 
 
776 
        always @ (posedge clk or posedge rst)
777 
        if (rst)
778 
                q <= reset_value;
779 
        else
780 
                if (ce)
781 
                        q <= d;
782 
 
783 
endmodule
784 40 unneback 
`endif
785 6 unneback 
 
786 40 unneback 
`ifdef DFF_CE_CLEAR
787 
`define MODULE dff_ce_clear
788 
module `BASE`MODULE ( d, ce, clear, q, clk, rst);
789 
`undef MODULE
790 8 unneback 
 
791 
        parameter width = 1;
792 
        parameter reset_value = 0;
793 
 
794 
        input [width-1:0] d;
795 10 unneback 
        input ce, clear, clk, rst;
796 8 unneback 
        output reg [width-1:0] q;
797 
 
798 
        always @ (posedge clk or posedge rst)
799 
        if (rst)
800 
            q <= reset_value;
801 
        else
802 
            if (ce)
803 
                if (clear)
804 
                    q <= {width{1'b0}};
805 
                else
806 
                    q <= d;
807 
 
808 
endmodule
809 40 unneback 
`endif
810 8 unneback 
 
811 40 unneback 
`ifdef DF_CE_SET
812 
`define MODULE dff_ce_set
813 
module `BASE`MODULE ( d, ce, set, q, clk, rst);
814 
`undef MODULE
815 24 unneback 
 
816 
        parameter width = 1;
817 
        parameter reset_value = 0;
818 
 
819 
        input [width-1:0] d;
820 
        input ce, set, clk, rst;
821 
        output reg [width-1:0] q;
822 
 
823 
        always @ (posedge clk or posedge rst)
824 
        if (rst)
825 
            q <= reset_value;
826 
        else
827 
            if (ce)
828 
                if (set)
829 
                    q <= {width{1'b1}};
830 
                else
831 
                    q <= d;
832 
 
833 
endmodule
834 40 unneback 
`endif
835 24 unneback 
 
836 40 unneback 
`ifdef SPR
837 
`define MODULE spr
838 
module `BASE`MODULE ( sp, r, q, clk, rst);
839 
`undef MODULE
840 
 
841 64 unneback 
        //parameter width = 1;
842 
        parameter reset_value = 1'b0;
843 29 unneback 
 
844 
        input sp, r;
845 
        output reg q;
846 
        input clk, rst;
847 
 
848 
        always @ (posedge clk or posedge rst)
849 
        if (rst)
850 
            q <= reset_value;
851 
        else
852 
            if (sp)
853 
                q <= 1'b1;
854 
            else if (r)
855 
                q <= 1'b0;
856 
 
857 
endmodule
858 40 unneback 
`endif
859 29 unneback 
 
860 40 unneback 
`ifdef SRP
861 
`define MODULE srp
862 
module `BASE`MODULE ( s, rp, q, clk, rst);
863 
`undef MODULE
864 
 
865 29 unneback 
        parameter width = 1;
866 
        parameter reset_value = 0;
867 
 
868 
        input s, rp;
869 
        output reg q;
870 
        input clk, rst;
871 
 
872 
        always @ (posedge clk or posedge rst)
873 
        if (rst)
874 
            q <= reset_value;
875 
        else
876 
            if (rp)
877 
                q <= 1'b0;
878 
            else if (s)
879 
                q <= 1'b1;
880 
 
881 
endmodule
882 40 unneback 
`endif
883 29 unneback 
 
884 40 unneback 
`ifdef ALTERA
885 29 unneback 
 
886 40 unneback 
`ifdef DFF_SR
887 6 unneback 
// megafunction wizard: %LPM_FF%
888 
// GENERATION: STANDARD
889 
// VERSION: WM1.0
890 
// MODULE: lpm_ff
891 
 
892 
// ============================================================
893 
// File Name: dff_sr.v
894 
// Megafunction Name(s):
895 
//                      lpm_ff
896 
//
897 
// Simulation Library Files(s):
898 
//                      lpm
899 
// ============================================================
900 
// ************************************************************
901 
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
902 
//
903 
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
904 
// ************************************************************
905 
 
906 
 
907 
//Copyright (C) 1991-2010 Altera Corporation
908 
//Your use of Altera Corporation's design tools, logic functions
909 
//and other software and tools, and its AMPP partner logic
910 
//functions, and any output files from any of the foregoing
911 
//(including device programming or simulation files), and any
912 
//associated documentation or information are expressly subject
913 
//to the terms and conditions of the Altera Program License
914 
//Subscription Agreement, Altera MegaCore Function License
915 
//Agreement, or other applicable license agreement, including,
916 
//without limitation, that your use is for the sole purpose of
917 
//programming logic devices manufactured by Altera and sold by
918 
//Altera or its authorized distributors.  Please refer to the
919 
//applicable agreement for further details.
920 
 
921 
 
922 
// synopsys translate_off
923 
`timescale 1 ps / 1 ps
924 
// synopsys translate_on
925 40 unneback 
`define MODULE dff_sr
926 
module `BASE`MODULE (
927 
`undef MODULE
928 
 
929 6 unneback 
        aclr,
930 
        aset,
931 
        clock,
932 
        data,
933 
        q);
934 
 
935 
        input     aclr;
936 
        input     aset;
937 
        input     clock;
938 
        input     data;
939 
        output    q;
940 
 
941 
        wire [0:0] sub_wire0;
942 
        wire [0:0] sub_wire1 = sub_wire0[0:0];
943 
        wire  q = sub_wire1;
944 
        wire  sub_wire2 = data;
945 
        wire  sub_wire3 = sub_wire2;
946 
 
947 
        lpm_ff  lpm_ff_component (
948 
                                .aclr (aclr),
949 
                                .clock (clock),
950 
                                .data (sub_wire3),
951 
                                .aset (aset),
952 
                                .q (sub_wire0)
953 
                                // synopsys translate_off
954 
                                ,
955 
                                .aload (),
956 
                                .enable (),
957 
                                .sclr (),
958 
                                .sload (),
959 
                                .sset ()
960 
                                // synopsys translate_on
961 
                                );
962 
        defparam
963 
                lpm_ff_component.lpm_fftype = "DFF",
964 
                lpm_ff_component.lpm_type = "LPM_FF",
965 
                lpm_ff_component.lpm_width = 1;
966 
 
967 
 
968 
endmodule
969 
 
970 
// ============================================================
971 
// CNX file retrieval info
972 
// ============================================================
973 
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
974 
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
975 
// Retrieval info: PRIVATE: ASET NUMERIC "1"
976 
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
977 
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
978 
// Retrieval info: PRIVATE: DFF NUMERIC "1"
979 
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
980 
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
981 
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
982 
// Retrieval info: PRIVATE: SSET NUMERIC "0"
983 
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
984 
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
985 
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
986 
// Retrieval info: PRIVATE: nBit NUMERIC "1"
987 
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
988 
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
989 
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
990 
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
991 
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
992 
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
993 
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
994 
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
995 
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
996 
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
997 
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
998 
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
999 
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
1000 
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
1001 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
1002 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
1003 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
1004 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
1005 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
1006 
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
1007 
// Retrieval info: LIB_FILE: lpm
1008 40 unneback 
`endif
1009 6 unneback 
 
1010 
`else
1011 
 
1012 40 unneback 
`ifdef DFF_SR
1013 
`define MODULE dff_sr
1014 
module `BASE`MODULE ( aclr, aset, clock, data, q);
1015 
`undef MODULE
1016 6 unneback 
 
1017 
    input         aclr;
1018 
    input         aset;
1019 
    input         clock;
1020 
    input         data;
1021 
    output reg    q;
1022 
 
1023 
   always @ (posedge clock or posedge aclr or posedge aset)
1024 
     if (aclr)
1025 
       q <= 1'b0;
1026 
     else if (aset)
1027 
       q <= 1'b1;
1028 
     else
1029 
       q <= data;
1030 
 
1031 
endmodule
1032 40 unneback 
`endif
1033 6 unneback 
 
1034 
`endif
1035 
 
1036 
// LATCH
1037 
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
1038 
`ifdef ALTERA
1039 40 unneback 
 
1040 
`ifdef LATCH
1041 
`define MODULE latch
1042 
module `BASE`MODULE ( d, le, q, clk);
1043 
`undef MODULE
1044 6 unneback 
input d, le;
1045 
output q;
1046 
input clk;
1047 
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
1048 
endmodule
1049 40 unneback 
`endif
1050 
 
1051 6 unneback 
`else
1052 40 unneback 
 
1053 
`ifdef LATCH
1054 
`define MODULE latch
1055 
module `BASE`MODULE ( d, le, q, clk);
1056 
`undef MODULE
1057 6 unneback 
input d, le;
1058 48 unneback 
input clk;
1059 
always @ (le or d)
1060 60 unneback 
if (le)
1061 48 unneback 
    d <= q;
1062 6 unneback 
endmodule
1063 15 unneback 
`endif
1064 
 
1065 40 unneback 
`endif
1066 
 
1067 
`ifdef SHREG
1068 
`define MODULE shreg
1069 
module `BASE`MODULE ( d, q, clk, rst);
1070 
`undef MODULE
1071 
 
1072 17 unneback 
parameter depth = 10;
1073 
input d;
1074 
output q;
1075 
input clk, rst;
1076 
 
1077 
reg [1:depth] dffs;
1078 
 
1079 
always @ (posedge clk or posedge rst)
1080 
if (rst)
1081 
    dffs <= {depth{1'b0}};
1082 
else
1083 
    dffs <= {d,dffs[1:depth-1]};
1084 
assign q = dffs[depth];
1085 
endmodule
1086 40 unneback 
`endif
1087 17 unneback 
 
1088 40 unneback 
`ifdef SHREG_CE
1089 
`define MODULE shreg_ce
1090 
module `BASE`MODULE ( d, ce, q, clk, rst);
1091 
`undef MODULE
1092 17 unneback 
parameter depth = 10;
1093 
input d, ce;
1094 
output q;
1095 
input clk, rst;
1096 
 
1097 
reg [1:depth] dffs;
1098 
 
1099 
always @ (posedge clk or posedge rst)
1100 
if (rst)
1101 
    dffs <= {depth{1'b0}};
1102 
else
1103 
    if (ce)
1104 
        dffs <= {d,dffs[1:depth-1]};
1105 
assign q = dffs[depth];
1106 
endmodule
1107 40 unneback 
`endif
1108 17 unneback 
 
1109 40 unneback 
`ifdef DELAY
1110 
`define MODULE delay
1111 
module `BASE`MODULE ( d, q, clk, rst);
1112 
`undef MODULE
1113 15 unneback 
parameter depth = 10;
1114 
input d;
1115 
output q;
1116 
input clk, rst;
1117 
 
1118 
reg [1:depth] dffs;
1119 
 
1120 
always @ (posedge clk or posedge rst)
1121 
if (rst)
1122 
    dffs <= {depth{1'b0}};
1123 
else
1124 
    dffs <= {d,dffs[1:depth-1]};
1125 
assign q = dffs[depth];
1126 17 unneback 
endmodule
1127 40 unneback 
`endif
1128 17 unneback 
 
1129 40 unneback 
`ifdef DELAY_EMPTYFLAG
1130 
`define MODULE delay_emptyflag
1131 41 unneback 
module `BASE`MODULE ( d, q, emptyflag, clk, rst);
1132 40 unneback 
`undef MODULE
1133 17 unneback 
parameter depth = 10;
1134 
input d;
1135 
output q, emptyflag;
1136 
input clk, rst;
1137 
 
1138 
reg [1:depth] dffs;
1139 
 
1140 
always @ (posedge clk or posedge rst)
1141 
if (rst)
1142 
    dffs <= {depth{1'b0}};
1143 
else
1144 
    dffs <= {d,dffs[1:depth-1]};
1145 
assign q = dffs[depth];
1146 
assign emptyflag = !(|dffs);
1147 
endmodule
1148 40 unneback 
`endif
1149 75 unneback 
 
1150 
`ifdef ASYNC_REG_REQ_ACK
1151 
`define MODULE async_reg_req_ack
1152 
module `BASE`MODULE ( d, q, req_i, req_o, ack_i, ack_o, clk_a, rst_a, clk_b, rst_b);
1153 
`undef MODULE
1154 
parameter data_width = 8;
1155 
input [data_width-1:0] d;
1156 
output [data_width-1:0] q;
1157 
input req_i;
1158 
output req_o;
1159 
input ack_i;
1160 
output ack_o;
1161 
input clk_a, rst_a, clk_b, rst_b;
1162 
 
1163 
reg [3:0] reqi; // 3: last req in clk_a, 2: input dff, 1-0: sync
1164 
wire rst;
1165 
 
1166 
always @ (posedge clk_a or rst_a)
1167 
if (rst_a)
1168 
    q <= {data_width{1'b0}};
1169 
else
1170 
    if (req_i)
1171 
        q <= d;
1172 
 
1173 
assign rst = ack_i | rst_a;
1174 
always @ (posedge clk_a or posedge rst)
1175 
if (rst)
1176 
    req[2] <= 1'b0;
1177 
else
1178 
    req[2] <= req_i & !ack_o;
1179 
 
1180 
always @ (posedge clk_a or posedge rst_a)
1181 
if (rst_a)
1182 
    req[3] <= 1'b0;
1183 
else
1184 
    req[3] <= req[2];
1185 
 
1186 
always @ (posedge clk_b or posedge rst_b)
1187 
if (rst_b)
1188 
    req[1:0] <= 2'b00;
1189 
else
1190 
    if (ack_i)
1191 
        req[1:0] <= 2'b00;
1192 
    else
1193 
        req[1:0] <= req[2:1];
1194 
assign req_o = req[0];
1195 
 
1196 
always @ (posedge clk_a or posedge rst_a)
1197 
if (rst_a)
1198 
    ack_o <= 1'b0;
1199 
else
1200 
    ack_o <= req[3] & req[2];
1201 
 
1202 
endmodule
1203 
`endif
1204 17 unneback 
//////////////////////////////////////////////////////////////////////
1205 6 unneback 
////                                                              ////
1206 18 unneback 
////  Logic functions                                             ////
1207 
////                                                              ////
1208 
////  Description                                                 ////
1209 
////  Logic functions such as multiplexers                        ////
1210 
////                                                              ////
1211 
////                                                              ////
1212 
////  To Do:                                                      ////
1213 
////   -                                                          ////
1214 
////                                                              ////
1215 
////  Author(s):                                                  ////
1216 
////      - Michael Unneback, unneback@opencores.org              ////
1217 
////        ORSoC AB                                              ////
1218 
////                                                              ////
1219 
//////////////////////////////////////////////////////////////////////
1220 
////                                                              ////
1221 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1222 
////                                                              ////
1223 
//// This source file may be used and distributed without         ////
1224 
//// restriction provided that this copyright statement is not    ////
1225 
//// removed from the file and that any derivative work contains  ////
1226 
//// the original copyright notice and the associated disclaimer. ////
1227 
////                                                              ////
1228 
//// This source file is free software; you can redistribute it   ////
1229 
//// and/or modify it under the terms of the GNU Lesser General   ////
1230 
//// Public License as published by the Free Software Foundation; ////
1231 
//// either version 2.1 of the License, or (at your option) any   ////
1232 
//// later version.                                               ////
1233 
////                                                              ////
1234 
//// This source is distributed in the hope that it will be       ////
1235 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1236 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1237 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1238 
//// details.                                                     ////
1239 
////                                                              ////
1240 
//// You should have received a copy of the GNU Lesser General    ////
1241 
//// Public License along with this source; if not, download it   ////
1242 
//// from http://www.opencores.org/lgpl.shtml                     ////
1243 
////                                                              ////
1244 
//////////////////////////////////////////////////////////////////////
1245 40 unneback 
`ifdef MUX_ANDOR
1246 
`define MODULE mux_andor
1247 
module `BASE`MODULE ( a, sel, dout);
1248 
`undef MODULE
1249 36 unneback 
 
1250 
parameter width = 32;
1251 
parameter nr_of_ports = 4;
1252 
 
1253 
input [nr_of_ports*width-1:0] a;
1254 
input [nr_of_ports-1:0] sel;
1255 
output reg [width-1:0] dout;
1256 
 
1257 38 unneback 
integer i,j;
1258 
 
1259 36 unneback 
always @ (a, sel)
1260 
begin
1261 
    dout = a[width-1:0] & {width{sel[0]}};
1262 42 unneback 
    for (i=1;i<nr_of_ports;i=i+1)
1263 
        for (j=0;j<width;j=j+1)
1264 
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
1265 36 unneback 
end
1266 
 
1267 
endmodule
1268 40 unneback 
`endif
1269 36 unneback 
 
1270 40 unneback 
`ifdef MUX2_ANDOR
1271 
`define MODULE mux2_andor
1272 
module `BASE`MODULE ( a1, a0, sel, dout);
1273 
`undef MODULE
1274 18 unneback 
 
1275 34 unneback 
parameter width = 32;
1276 35 unneback 
localparam nr_of_ports = 2;
1277 34 unneback 
input [width-1:0] a1, a0;
1278 
input [nr_of_ports-1:0] sel;
1279 
output [width-1:0] dout;
1280 
 
1281 40 unneback 
`define MODULE mux_andor
1282 
`BASE`MODULE
1283 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1284 36 unneback 
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
1285 40 unneback 
`undef MODULE
1286 
 
1287 34 unneback 
endmodule
1288 40 unneback 
`endif
1289 34 unneback 
 
1290 40 unneback 
`ifdef MUX3_ANDOR
1291 
`define MODULE mux3_andor
1292 
module `BASE`MODULE ( a2, a1, a0, sel, dout);
1293 
`undef MODULE
1294 34 unneback 
 
1295 
parameter width = 32;
1296 35 unneback 
localparam nr_of_ports = 3;
1297 34 unneback 
input [width-1:0] a2, a1, a0;
1298 
input [nr_of_ports-1:0] sel;
1299 
output [width-1:0] dout;
1300 
 
1301 40 unneback 
`define MODULE mux_andor
1302 
`BASE`MODULE
1303 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1304 36 unneback 
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
1305 40 unneback 
`undef MODULE
1306 34 unneback 
endmodule
1307 40 unneback 
`endif
1308 34 unneback 
 
1309 40 unneback 
`ifdef MUX4_ANDOR
1310 
`define MODULE mux4_andor
1311 
module `BASE`MODULE ( a3, a2, a1, a0, sel, dout);
1312 
`undef MODULE
1313 18 unneback 
 
1314 
parameter width = 32;
1315 35 unneback 
localparam nr_of_ports = 4;
1316 18 unneback 
input [width-1:0] a3, a2, a1, a0;
1317 
input [nr_of_ports-1:0] sel;
1318 22 unneback 
output [width-1:0] dout;
1319 18 unneback 
 
1320 40 unneback 
`define MODULE mux_andor
1321 
`BASE`MODULE
1322 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1323 36 unneback 
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
1324 40 unneback 
`undef MODULE
1325 18 unneback 
 
1326 
endmodule
1327 40 unneback 
`endif
1328 18 unneback 
 
1329 40 unneback 
`ifdef MUX5_ANDOR
1330 
`define MODULE mux5_andor
1331 
module `BASE`MODULE ( a4, a3, a2, a1, a0, sel, dout);
1332 
`undef MODULE
1333 18 unneback 
 
1334 
parameter width = 32;
1335 35 unneback 
localparam nr_of_ports = 5;
1336 18 unneback 
input [width-1:0] a4, a3, a2, a1, a0;
1337 
input [nr_of_ports-1:0] sel;
1338 22 unneback 
output [width-1:0] dout;
1339 18 unneback 
 
1340 40 unneback 
`define MODULE mux_andor
1341 
`BASE`MODULE
1342 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1343 36 unneback 
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1344 40 unneback 
`undef MODULE
1345 18 unneback 
 
1346 
endmodule
1347 40 unneback 
`endif
1348 18 unneback 
 
1349 40 unneback 
`ifdef MUX6_ANDOR
1350 
`define MODULE mux6_andor
1351 
module `BASE`MODULE ( a5, a4, a3, a2, a1, a0, sel, dout);
1352 
`undef MODULE
1353 18 unneback 
 
1354 
parameter width = 32;
1355 35 unneback 
localparam nr_of_ports = 6;
1356 18 unneback 
input [width-1:0] a5, a4, a3, a2, a1, a0;
1357 
input [nr_of_ports-1:0] sel;
1358 22 unneback 
output [width-1:0] dout;
1359 18 unneback 
 
1360 40 unneback 
`define MODULE mux_andor
1361 
`BASE`MODULE
1362 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
1363 36 unneback 
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
1364 40 unneback 
`undef MODULE
1365 18 unneback 
 
1366 
endmodule
1367 40 unneback 
`endif
1368 43 unneback 
 
1369 
`ifdef PARITY
1370 
 
1371 
`define MODULE parity_generate
1372 
module `BASE`MODULE (data, parity);
1373 
`undef MODULE
1374 
parameter word_size = 32;
1375 
parameter chunk_size = 8;
1376 
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1377 
input [word_size-1:0] data;
1378 
output reg [word_size/chunk_size-1:0] parity;
1379 
integer i,j;
1380 
always @ (data)
1381 
for (i=0;i<word_size/chunk_size;i=i+1) begin
1382 
    parity[i] = parity_type;
1383 
    for (j=0;j<chunk_size;j=j+1) begin
1384 46 unneback 
        parity[i] = data[i*chunk_size+j] ^ parity[i];
1385 43 unneback 
    end
1386 
end
1387 
endmodule
1388 
 
1389 
`define MODULE parity_check
1390 
module `BASE`MODULE( data, parity, parity_error);
1391 
`undef MODULE
1392 
parameter word_size = 32;
1393 
parameter chunk_size = 8;
1394 
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
1395 
input [word_size-1:0] data;
1396 
input [word_size/chunk_size-1:0] parity;
1397 
output parity_error;
1398 44 unneback 
reg [word_size/chunk_size-1:0] error_flag;
1399 43 unneback 
integer i,j;
1400 
always @ (data or parity)
1401 
for (i=0;i<word_size/chunk_size;i=i+1) begin
1402 
    error_flag[i] = parity[i] ^ parity_type;
1403 
    for (j=0;j<chunk_size;j=j+1) begin
1404 46 unneback 
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
1405 43 unneback 
    end
1406 
end
1407 
assign parity_error = |error_flag;
1408 
endmodule
1409 
 
1410 44 unneback 
`endif//////////////////////////////////////////////////////////////////////
1411 
////                                                              ////
1412 
////  IO functions                                                ////
1413 
////                                                              ////
1414 
////  Description                                                 ////
1415 
////  IO functions such as IOB flip-flops                         ////
1416 
////                                                              ////
1417 
////                                                              ////
1418 
////  To Do:                                                      ////
1419 
////   -                                                          ////
1420 
////                                                              ////
1421 
////  Author(s):                                                  ////
1422 
////      - Michael Unneback, unneback@opencores.org              ////
1423 
////        ORSoC AB                                              ////
1424 
////                                                              ////
1425 18 unneback 
//////////////////////////////////////////////////////////////////////
1426 
////                                                              ////
1427 44 unneback 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1428 
////                                                              ////
1429 
//// This source file may be used and distributed without         ////
1430 
//// restriction provided that this copyright statement is not    ////
1431 
//// removed from the file and that any derivative work contains  ////
1432 
//// the original copyright notice and the associated disclaimer. ////
1433 
////                                                              ////
1434 
//// This source file is free software; you can redistribute it   ////
1435 
//// and/or modify it under the terms of the GNU Lesser General   ////
1436 
//// Public License as published by the Free Software Foundation; ////
1437 
//// either version 2.1 of the License, or (at your option) any   ////
1438 
//// later version.                                               ////
1439 
////                                                              ////
1440 
//// This source is distributed in the hope that it will be       ////
1441 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1442 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1443 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1444 
//// details.                                                     ////
1445 
////                                                              ////
1446 
//// You should have received a copy of the GNU Lesser General    ////
1447 
//// Public License along with this source; if not, download it   ////
1448 
//// from http://www.opencores.org/lgpl.shtml                     ////
1449 
////                                                              ////
1450 
//////////////////////////////////////////////////////////////////////
1451 45 unneback 
`timescale 1ns/1ns
1452 44 unneback 
`ifdef O_DFF
1453 
`define MODULE o_dff
1454 
module `BASE`MODULE (d_i, o_pad, clk, rst);
1455 
`undef MODULE
1456 
parameter width = 1;
1457 45 unneback 
parameter reset_value = {width{1'b0}};
1458 
input  [width-1:0]  d_i;
1459 44 unneback 
output [width-1:0] o_pad;
1460 
input clk, rst;
1461 
wire [width-1:0] d_i_int `SYN_KEEP;
1462 45 unneback 
reg  [width-1:0] o_pad_int;
1463 44 unneback 
assign d_i_int = d_i;
1464 
genvar i;
1465 45 unneback 
generate
1466 44 unneback 
for (i=0;i<width;i=i+1) begin
1467 
    always @ (posedge clk or posedge rst)
1468 
    if (rst)
1469 45 unneback 
        o_pad_int[i] <= reset_value[i];
1470 44 unneback 
    else
1471 45 unneback 
        o_pad_int[i] <= d_i_int[i];
1472 
    assign #1 o_pad[i] = o_pad_int[i];
1473 44 unneback 
end
1474 
endgenerate
1475 
endmodule
1476 
`endif
1477 
 
1478 45 unneback 
`timescale 1ns/1ns
1479 44 unneback 
`ifdef IO_DFF_OE
1480 
`define MODULE io_dff_oe
1481 
module `BASE`MODULE ( d_i, d_o, oe, io_pad, clk, rst);
1482 
`undef MODULE
1483 
parameter width = 1;
1484 
input  [width-1:0] d_o;
1485 
output reg [width-1:0] d_i;
1486 
input oe;
1487 
inout [width-1:0] io_pad;
1488 
input clk, rst;
1489 
wire [width-1:0] oe_d `SYN_KEEP;
1490 
reg [width-1:0] oe_q;
1491 
reg [width-1:0] d_o_q;
1492 
assign oe_d = {width{oe}};
1493 
genvar i;
1494 
generate
1495 
for (i=0;i<width;i=i+1) begin
1496 
    always @ (posedge clk or posedge rst)
1497 
    if (rst)
1498 
        oe_q[i] <= 1'b0;
1499 
    else
1500 
        oe_q[i] <= oe_d[i];
1501 
    always @ (posedge clk or posedge rst)
1502 
    if (rst)
1503 
        d_o_q[i] <= 1'b0;
1504 
    else
1505 
        d_o_q[i] <= d_o[i];
1506 
    always @ (posedge clk or posedge rst)
1507 
    if (rst)
1508 
        d_i[i] <= 1'b0;
1509 
    else
1510 
        d_i[i] <= io_pad[i];
1511 45 unneback 
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
1512 44 unneback 
end
1513 
endgenerate
1514 
endmodule
1515 
`endif
1516 
`ifdef CNT_BIN
1517 
//////////////////////////////////////////////////////////////////////
1518 
////                                                              ////
1519 6 unneback 
////  Versatile counter                                           ////
1520 
////                                                              ////
1521 
////  Description                                                 ////
1522 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1523 
////  counter                                                     ////
1524 
////                                                              ////
1525 
////  To Do:                                                      ////
1526 
////   - add LFSR with more taps                                  ////
1527 
////                                                              ////
1528 
////  Author(s):                                                  ////
1529 
////      - Michael Unneback, unneback@opencores.org              ////
1530 
////        ORSoC AB                                              ////
1531 
////                                                              ////
1532 
//////////////////////////////////////////////////////////////////////
1533 
////                                                              ////
1534 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1535 
////                                                              ////
1536 
//// This source file may be used and distributed without         ////
1537 
//// restriction provided that this copyright statement is not    ////
1538 
//// removed from the file and that any derivative work contains  ////
1539 
//// the original copyright notice and the associated disclaimer. ////
1540 
////                                                              ////
1541 
//// This source file is free software; you can redistribute it   ////
1542 
//// and/or modify it under the terms of the GNU Lesser General   ////
1543 
//// Public License as published by the Free Software Foundation; ////
1544 
//// either version 2.1 of the License, or (at your option) any   ////
1545 
//// later version.                                               ////
1546 
////                                                              ////
1547 
//// This source is distributed in the hope that it will be       ////
1548 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1549 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1550 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1551 
//// details.                                                     ////
1552 
////                                                              ////
1553 
//// You should have received a copy of the GNU Lesser General    ////
1554 
//// Public License along with this source; if not, download it   ////
1555 
//// from http://www.opencores.org/lgpl.shtml                     ////
1556 
////                                                              ////
1557 
//////////////////////////////////////////////////////////////////////
1558 
 
1559 
// binary counter
1560 22 unneback 
 
1561 40 unneback 
`define MODULE cnt_bin
1562 
module `BASE`MODULE (
1563 
`undef MODULE
1564 
 q, rst, clk);
1565 
 
1566 22 unneback 
   parameter length = 4;
1567 
   output [length:1] q;
1568 
   input rst;
1569 
   input clk;
1570 
 
1571 
   parameter clear_value = 0;
1572 
   parameter set_value = 1;
1573 
   parameter wrap_value = 0;
1574 
   parameter level1_value = 15;
1575 
 
1576 
   reg  [length:1] qi;
1577 
   wire [length:1] q_next;
1578 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1579 
 
1580 
   always @ (posedge clk or posedge rst)
1581 
     if (rst)
1582 
       qi <= {length{1'b0}};
1583 
     else
1584 
       qi <= q_next;
1585 
 
1586 
   assign q = qi;
1587 
 
1588 
endmodule
1589 40 unneback 
`endif
1590 
`ifdef CNT_BIN_CLEAR
1591 22 unneback 
//////////////////////////////////////////////////////////////////////
1592 
////                                                              ////
1593 
////  Versatile counter                                           ////
1594 
////                                                              ////
1595 
////  Description                                                 ////
1596 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1597 
////  counter                                                     ////
1598 
////                                                              ////
1599 
////  To Do:                                                      ////
1600 
////   - add LFSR with more taps                                  ////
1601 
////                                                              ////
1602 
////  Author(s):                                                  ////
1603 
////      - Michael Unneback, unneback@opencores.org              ////
1604 
////        ORSoC AB                                              ////
1605 
////                                                              ////
1606 
//////////////////////////////////////////////////////////////////////
1607 
////                                                              ////
1608 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1609 
////                                                              ////
1610 
//// This source file may be used and distributed without         ////
1611 
//// restriction provided that this copyright statement is not    ////
1612 
//// removed from the file and that any derivative work contains  ////
1613 
//// the original copyright notice and the associated disclaimer. ////
1614 
////                                                              ////
1615 
//// This source file is free software; you can redistribute it   ////
1616 
//// and/or modify it under the terms of the GNU Lesser General   ////
1617 
//// Public License as published by the Free Software Foundation; ////
1618 
//// either version 2.1 of the License, or (at your option) any   ////
1619 
//// later version.                                               ////
1620 
////                                                              ////
1621 
//// This source is distributed in the hope that it will be       ////
1622 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1623 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1624 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1625 
//// details.                                                     ////
1626 
////                                                              ////
1627 
//// You should have received a copy of the GNU Lesser General    ////
1628 
//// Public License along with this source; if not, download it   ////
1629 
//// from http://www.opencores.org/lgpl.shtml                     ////
1630 
////                                                              ////
1631 
//////////////////////////////////////////////////////////////////////
1632 
 
1633 
// binary counter
1634 
 
1635 40 unneback 
`define MODULE cnt_bin_clear
1636 
module `BASE`MODULE (
1637 
`undef MODULE
1638 
 clear, q, rst, clk);
1639 
 
1640 22 unneback 
   parameter length = 4;
1641 
   input clear;
1642 
   output [length:1] q;
1643 
   input rst;
1644 
   input clk;
1645 
 
1646 
   parameter clear_value = 0;
1647 
   parameter set_value = 1;
1648 
   parameter wrap_value = 0;
1649 
   parameter level1_value = 15;
1650 
 
1651 
   reg  [length:1] qi;
1652 
   wire [length:1] q_next;
1653 
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1654 
 
1655 
   always @ (posedge clk or posedge rst)
1656 
     if (rst)
1657 
       qi <= {length{1'b0}};
1658 
     else
1659 
       qi <= q_next;
1660 
 
1661 
   assign q = qi;
1662 
 
1663 
endmodule
1664 40 unneback 
`endif
1665 
`ifdef CNT_BIN_CE
1666 22 unneback 
//////////////////////////////////////////////////////////////////////
1667 
////                                                              ////
1668 
////  Versatile counter                                           ////
1669 
////                                                              ////
1670 
////  Description                                                 ////
1671 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1672 
////  counter                                                     ////
1673 
////                                                              ////
1674 
////  To Do:                                                      ////
1675 
////   - add LFSR with more taps                                  ////
1676 
////                                                              ////
1677 
////  Author(s):                                                  ////
1678 
////      - Michael Unneback, unneback@opencores.org              ////
1679 
////        ORSoC AB                                              ////
1680 
////                                                              ////
1681 
//////////////////////////////////////////////////////////////////////
1682 
////                                                              ////
1683 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1684 
////                                                              ////
1685 
//// This source file may be used and distributed without         ////
1686 
//// restriction provided that this copyright statement is not    ////
1687 
//// removed from the file and that any derivative work contains  ////
1688 
//// the original copyright notice and the associated disclaimer. ////
1689 
////                                                              ////
1690 
//// This source file is free software; you can redistribute it   ////
1691 
//// and/or modify it under the terms of the GNU Lesser General   ////
1692 
//// Public License as published by the Free Software Foundation; ////
1693 
//// either version 2.1 of the License, or (at your option) any   ////
1694 
//// later version.                                               ////
1695 
////                                                              ////
1696 
//// This source is distributed in the hope that it will be       ////
1697 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1698 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1699 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1700 
//// details.                                                     ////
1701 
////                                                              ////
1702 
//// You should have received a copy of the GNU Lesser General    ////
1703 
//// Public License along with this source; if not, download it   ////
1704 
//// from http://www.opencores.org/lgpl.shtml                     ////
1705 
////                                                              ////
1706 
//////////////////////////////////////////////////////////////////////
1707 
 
1708 
// binary counter
1709 6 unneback 
 
1710 40 unneback 
`define MODULE cnt_bin_ce
1711 
module `BASE`MODULE (
1712 
`undef MODULE
1713 
 cke, q, rst, clk);
1714 
 
1715 6 unneback 
   parameter length = 4;
1716 
   input cke;
1717 
   output [length:1] q;
1718 
   input rst;
1719 
   input clk;
1720 
 
1721 
   parameter clear_value = 0;
1722 
   parameter set_value = 1;
1723 
   parameter wrap_value = 0;
1724 
   parameter level1_value = 15;
1725 
 
1726 
   reg  [length:1] qi;
1727 
   wire [length:1] q_next;
1728 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1729 
 
1730 
   always @ (posedge clk or posedge rst)
1731 
     if (rst)
1732 
       qi <= {length{1'b0}};
1733 
     else
1734 
     if (cke)
1735 
       qi <= q_next;
1736 
 
1737 
   assign q = qi;
1738 
 
1739 
endmodule
1740 40 unneback 
`endif
1741 
`ifdef CNT_BIN_CE_CLEAR
1742 6 unneback 
//////////////////////////////////////////////////////////////////////
1743 
////                                                              ////
1744 
////  Versatile counter                                           ////
1745 
////                                                              ////
1746 
////  Description                                                 ////
1747 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1748 
////  counter                                                     ////
1749 
////                                                              ////
1750 
////  To Do:                                                      ////
1751 
////   - add LFSR with more taps                                  ////
1752 
////                                                              ////
1753 
////  Author(s):                                                  ////
1754 
////      - Michael Unneback, unneback@opencores.org              ////
1755 
////        ORSoC AB                                              ////
1756 
////                                                              ////
1757 
//////////////////////////////////////////////////////////////////////
1758 
////                                                              ////
1759 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1760 
////                                                              ////
1761 
//// This source file may be used and distributed without         ////
1762 
//// restriction provided that this copyright statement is not    ////
1763 
//// removed from the file and that any derivative work contains  ////
1764 
//// the original copyright notice and the associated disclaimer. ////
1765 
////                                                              ////
1766 
//// This source file is free software; you can redistribute it   ////
1767 
//// and/or modify it under the terms of the GNU Lesser General   ////
1768 
//// Public License as published by the Free Software Foundation; ////
1769 
//// either version 2.1 of the License, or (at your option) any   ////
1770 
//// later version.                                               ////
1771 
////                                                              ////
1772 
//// This source is distributed in the hope that it will be       ////
1773 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1774 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1775 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1776 
//// details.                                                     ////
1777 
////                                                              ////
1778 
//// You should have received a copy of the GNU Lesser General    ////
1779 
//// Public License along with this source; if not, download it   ////
1780 
//// from http://www.opencores.org/lgpl.shtml                     ////
1781 
////                                                              ////
1782 
//////////////////////////////////////////////////////////////////////
1783 
 
1784 
// binary counter
1785 
 
1786 40 unneback 
`define MODULE cnt_bin_ce_clear
1787 
module `BASE`MODULE (
1788 
`undef MODULE
1789 
 clear, cke, q, rst, clk);
1790 
 
1791 6 unneback 
   parameter length = 4;
1792 
   input clear;
1793 
   input cke;
1794 
   output [length:1] q;
1795 
   input rst;
1796 
   input clk;
1797 
 
1798 
   parameter clear_value = 0;
1799 
   parameter set_value = 1;
1800 
   parameter wrap_value = 0;
1801 
   parameter level1_value = 15;
1802 
 
1803 
   reg  [length:1] qi;
1804 
   wire [length:1] q_next;
1805 
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1806 
 
1807 
   always @ (posedge clk or posedge rst)
1808 
     if (rst)
1809 
       qi <= {length{1'b0}};
1810 
     else
1811 
     if (cke)
1812 
       qi <= q_next;
1813 
 
1814 
   assign q = qi;
1815 
 
1816 
endmodule
1817 40 unneback 
`endif
1818 
`ifdef CNT_BIN_CE_CLEAR_L1_L2
1819 6 unneback 
//////////////////////////////////////////////////////////////////////
1820 
////                                                              ////
1821 
////  Versatile counter                                           ////
1822 
////                                                              ////
1823 
////  Description                                                 ////
1824 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1825 
////  counter                                                     ////
1826 
////                                                              ////
1827 
////  To Do:                                                      ////
1828 
////   - add LFSR with more taps                                  ////
1829 
////                                                              ////
1830 
////  Author(s):                                                  ////
1831 
////      - Michael Unneback, unneback@opencores.org              ////
1832 
////        ORSoC AB                                              ////
1833 
////                                                              ////
1834 
//////////////////////////////////////////////////////////////////////
1835 
////                                                              ////
1836 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1837 
////                                                              ////
1838 
//// This source file may be used and distributed without         ////
1839 
//// restriction provided that this copyright statement is not    ////
1840 
//// removed from the file and that any derivative work contains  ////
1841 
//// the original copyright notice and the associated disclaimer. ////
1842 
////                                                              ////
1843 
//// This source file is free software; you can redistribute it   ////
1844 
//// and/or modify it under the terms of the GNU Lesser General   ////
1845 
//// Public License as published by the Free Software Foundation; ////
1846 
//// either version 2.1 of the License, or (at your option) any   ////
1847 
//// later version.                                               ////
1848 
////                                                              ////
1849 
//// This source is distributed in the hope that it will be       ////
1850 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1851 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1852 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1853 
//// details.                                                     ////
1854 
////                                                              ////
1855 
//// You should have received a copy of the GNU Lesser General    ////
1856 
//// Public License along with this source; if not, download it   ////
1857 
//// from http://www.opencores.org/lgpl.shtml                     ////
1858 
////                                                              ////
1859 
//////////////////////////////////////////////////////////////////////
1860 
 
1861 
// binary counter
1862 29 unneback 
 
1863 40 unneback 
`define MODULE cnt_bin_ce_clear_l1_l2
1864 
module `BASE`MODULE (
1865 
`undef MODULE
1866 
 clear, cke, q, level1, level2, rst, clk);
1867 
 
1868 29 unneback 
   parameter length = 4;
1869 
   input clear;
1870 
   input cke;
1871 
   output [length:1] q;
1872 
   output reg level1;
1873 
   output reg level2;
1874 
   input rst;
1875 
   input clk;
1876 
 
1877 
   parameter clear_value = 0;
1878 
   parameter set_value = 1;
1879 30 unneback 
   parameter wrap_value = 15;
1880 
   parameter level1_value = 8;
1881 
   parameter level2_value = 15;
1882 29 unneback 
 
1883 
   wire rew;
1884 30 unneback 
   assign rew = 1'b0;
1885 29 unneback 
   reg  [length:1] qi;
1886 
   wire [length:1] q_next;
1887 
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1888 
 
1889 
   always @ (posedge clk or posedge rst)
1890 
     if (rst)
1891 
       qi <= {length{1'b0}};
1892 
     else
1893 
     if (cke)
1894 
       qi <= q_next;
1895 
 
1896 
   assign q = qi;
1897 
 
1898 
 
1899 
    always @ (posedge clk or posedge rst)
1900 
    if (rst)
1901 
        level1 <= 1'b0;
1902 
    else
1903 
    if (cke)
1904 
    if (clear)
1905 
        level1 <= 1'b0;
1906 
    else if (q_next == level1_value)
1907 
        level1 <= 1'b1;
1908 
    else if (qi == level1_value & rew)
1909 
        level1 <= 1'b0;
1910 
 
1911 
    always @ (posedge clk or posedge rst)
1912 
    if (rst)
1913 
        level2 <= 1'b0;
1914 
    else
1915 
    if (cke)
1916 
    if (clear)
1917 
        level2 <= 1'b0;
1918 
    else if (q_next == level2_value)
1919 
        level2 <= 1'b1;
1920 
    else if (qi == level2_value & rew)
1921 
        level2 <= 1'b0;
1922 
endmodule
1923 40 unneback 
`endif
1924 
`ifdef CNT_BIN_CE_CLEAR_SET_REW
1925 29 unneback 
//////////////////////////////////////////////////////////////////////
1926 
////                                                              ////
1927 
////  Versatile counter                                           ////
1928 
////                                                              ////
1929 
////  Description                                                 ////
1930 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1931 
////  counter                                                     ////
1932 
////                                                              ////
1933 
////  To Do:                                                      ////
1934 
////   - add LFSR with more taps                                  ////
1935 
////                                                              ////
1936 
////  Author(s):                                                  ////
1937 
////      - Michael Unneback, unneback@opencores.org              ////
1938 
////        ORSoC AB                                              ////
1939 
////                                                              ////
1940 
//////////////////////////////////////////////////////////////////////
1941 
////                                                              ////
1942 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1943 
////                                                              ////
1944 
//// This source file may be used and distributed without         ////
1945 
//// restriction provided that this copyright statement is not    ////
1946 
//// removed from the file and that any derivative work contains  ////
1947 
//// the original copyright notice and the associated disclaimer. ////
1948 
////                                                              ////
1949 
//// This source file is free software; you can redistribute it   ////
1950 
//// and/or modify it under the terms of the GNU Lesser General   ////
1951 
//// Public License as published by the Free Software Foundation; ////
1952 
//// either version 2.1 of the License, or (at your option) any   ////
1953 
//// later version.                                               ////
1954 
////                                                              ////
1955 
//// This source is distributed in the hope that it will be       ////
1956 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1957 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1958 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1959 
//// details.                                                     ////
1960 
////                                                              ////
1961 
//// You should have received a copy of the GNU Lesser General    ////
1962 
//// Public License along with this source; if not, download it   ////
1963 
//// from http://www.opencores.org/lgpl.shtml                     ////
1964 
////                                                              ////
1965 
//////////////////////////////////////////////////////////////////////
1966 
 
1967 
// binary counter
1968 6 unneback 
 
1969 40 unneback 
`define MODULE cnt_bin_ce_clear_set_rew
1970 
module `BASE`MODULE (
1971 
`undef MODULE
1972 
 clear, set, cke, rew, q, rst, clk);
1973 
 
1974 6 unneback 
   parameter length = 4;
1975 
   input clear;
1976 
   input set;
1977 
   input cke;
1978 
   input rew;
1979 
   output [length:1] q;
1980 
   input rst;
1981 
   input clk;
1982 
 
1983 
   parameter clear_value = 0;
1984 
   parameter set_value = 1;
1985 
   parameter wrap_value = 0;
1986 
   parameter level1_value = 15;
1987 
 
1988 
   reg  [length:1] qi;
1989 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1990 
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
1991 
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
1992 
   assign q_next = rew ? q_next_rew : q_next_fw;
1993 
 
1994 
   always @ (posedge clk or posedge rst)
1995 
     if (rst)
1996 
       qi <= {length{1'b0}};
1997 
     else
1998 
     if (cke)
1999 
       qi <= q_next;
2000 
 
2001 
   assign q = qi;
2002 
 
2003 
endmodule
2004 40 unneback 
`endif
2005 
`ifdef CNT_BIN_CE_REW_L1
2006 6 unneback 
//////////////////////////////////////////////////////////////////////
2007 
////                                                              ////
2008 
////  Versatile counter                                           ////
2009 
////                                                              ////
2010 
////  Description                                                 ////
2011 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2012 
////  counter                                                     ////
2013 
////                                                              ////
2014 
////  To Do:                                                      ////
2015 
////   - add LFSR with more taps                                  ////
2016 
////                                                              ////
2017 
////  Author(s):                                                  ////
2018 
////      - Michael Unneback, unneback@opencores.org              ////
2019 
////        ORSoC AB                                              ////
2020 
////                                                              ////
2021 
//////////////////////////////////////////////////////////////////////
2022 
////                                                              ////
2023 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2024 
////                                                              ////
2025 
//// This source file may be used and distributed without         ////
2026 
//// restriction provided that this copyright statement is not    ////
2027 
//// removed from the file and that any derivative work contains  ////
2028 
//// the original copyright notice and the associated disclaimer. ////
2029 
////                                                              ////
2030 
//// This source file is free software; you can redistribute it   ////
2031 
//// and/or modify it under the terms of the GNU Lesser General   ////
2032 
//// Public License as published by the Free Software Foundation; ////
2033 
//// either version 2.1 of the License, or (at your option) any   ////
2034 
//// later version.                                               ////
2035 
////                                                              ////
2036 
//// This source is distributed in the hope that it will be       ////
2037 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2038 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2039 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2040 
//// details.                                                     ////
2041 
////                                                              ////
2042 
//// You should have received a copy of the GNU Lesser General    ////
2043 
//// Public License along with this source; if not, download it   ////
2044 
//// from http://www.opencores.org/lgpl.shtml                     ////
2045 
////                                                              ////
2046 
//////////////////////////////////////////////////////////////////////
2047 
 
2048 
// binary counter
2049 
 
2050 40 unneback 
`define MODULE cnt_bin_ce_rew_l1
2051 
module `BASE`MODULE (
2052 
`undef MODULE
2053 
 cke, rew, level1, rst, clk);
2054 
 
2055 6 unneback 
   parameter length = 4;
2056 
   input cke;
2057 
   input rew;
2058 
   output reg level1;
2059 
   input rst;
2060 
   input clk;
2061 
 
2062 
   parameter clear_value = 0;
2063 
   parameter set_value = 1;
2064 
   parameter wrap_value = 1;
2065 
   parameter level1_value = 15;
2066 
 
2067 29 unneback 
   wire clear;
2068 30 unneback 
   assign clear = 1'b0;
2069 6 unneback 
   reg  [length:1] qi;
2070 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2071 
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2072 
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2073 
   assign q_next = rew ? q_next_rew : q_next_fw;
2074 
 
2075 
   always @ (posedge clk or posedge rst)
2076 
     if (rst)
2077 
       qi <= {length{1'b0}};
2078 
     else
2079 
     if (cke)
2080 
       qi <= q_next;
2081 
 
2082 
 
2083 
 
2084 
    always @ (posedge clk or posedge rst)
2085 
    if (rst)
2086 
        level1 <= 1'b0;
2087 
    else
2088 
    if (cke)
2089 29 unneback 
    if (clear)
2090 
        level1 <= 1'b0;
2091 
    else if (q_next == level1_value)
2092 6 unneback 
        level1 <= 1'b1;
2093 
    else if (qi == level1_value & rew)
2094 
        level1 <= 1'b0;
2095 
endmodule
2096 40 unneback 
`endif
2097 
`ifdef CNT_BIN_CE_REW_ZQ_L1
2098 6 unneback 
//////////////////////////////////////////////////////////////////////
2099 
////                                                              ////
2100 
////  Versatile counter                                           ////
2101 
////                                                              ////
2102 
////  Description                                                 ////
2103 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2104 
////  counter                                                     ////
2105 
////                                                              ////
2106 
////  To Do:                                                      ////
2107 
////   - add LFSR with more taps                                  ////
2108 
////                                                              ////
2109 
////  Author(s):                                                  ////
2110 
////      - Michael Unneback, unneback@opencores.org              ////
2111 
////        ORSoC AB                                              ////
2112 
////                                                              ////
2113 
//////////////////////////////////////////////////////////////////////
2114 
////                                                              ////
2115 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2116 
////                                                              ////
2117 
//// This source file may be used and distributed without         ////
2118 
//// restriction provided that this copyright statement is not    ////
2119 
//// removed from the file and that any derivative work contains  ////
2120 
//// the original copyright notice and the associated disclaimer. ////
2121 
////                                                              ////
2122 
//// This source file is free software; you can redistribute it   ////
2123 
//// and/or modify it under the terms of the GNU Lesser General   ////
2124 
//// Public License as published by the Free Software Foundation; ////
2125 
//// either version 2.1 of the License, or (at your option) any   ////
2126 
//// later version.                                               ////
2127 
////                                                              ////
2128 
//// This source is distributed in the hope that it will be       ////
2129 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2130 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2131 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2132 
//// details.                                                     ////
2133 
////                                                              ////
2134 
//// You should have received a copy of the GNU Lesser General    ////
2135 
//// Public License along with this source; if not, download it   ////
2136 
//// from http://www.opencores.org/lgpl.shtml                     ////
2137 
////                                                              ////
2138 
//////////////////////////////////////////////////////////////////////
2139 
 
2140 25 unneback 
// binary counter
2141 
 
2142 40 unneback 
`define MODULE cnt_bin_ce_rew_zq_l1
2143 
module `BASE`MODULE (
2144 
`undef MODULE
2145 
 cke, rew, zq, level1, rst, clk);
2146 
 
2147 25 unneback 
   parameter length = 4;
2148 
   input cke;
2149 
   input rew;
2150 
   output reg zq;
2151 
   output reg level1;
2152 
   input rst;
2153 
   input clk;
2154 
 
2155 
   parameter clear_value = 0;
2156 
   parameter set_value = 1;
2157 
   parameter wrap_value = 1;
2158 
   parameter level1_value = 15;
2159 
 
2160 29 unneback 
   wire clear;
2161 30 unneback 
   assign clear = 1'b0;
2162 25 unneback 
   reg  [length:1] qi;
2163 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2164 
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2165 
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2166 
   assign q_next = rew ? q_next_rew : q_next_fw;
2167 
 
2168 
   always @ (posedge clk or posedge rst)
2169 
     if (rst)
2170 
       qi <= {length{1'b0}};
2171 
     else
2172 
     if (cke)
2173 
       qi <= q_next;
2174 
 
2175 
 
2176 
 
2177 
   always @ (posedge clk or posedge rst)
2178 
     if (rst)
2179 
       zq <= 1'b1;
2180 
     else
2181 
     if (cke)
2182 
       zq <= q_next == {length{1'b0}};
2183 
 
2184 
    always @ (posedge clk or posedge rst)
2185 
    if (rst)
2186 
        level1 <= 1'b0;
2187 
    else
2188 
    if (cke)
2189 29 unneback 
    if (clear)
2190 
        level1 <= 1'b0;
2191 
    else if (q_next == level1_value)
2192 25 unneback 
        level1 <= 1'b1;
2193 
    else if (qi == level1_value & rew)
2194 
        level1 <= 1'b0;
2195 
endmodule
2196 40 unneback 
`endif
2197 
`ifdef CNT_BIN_CE_REW_Q_ZQ_L1
2198 25 unneback 
//////////////////////////////////////////////////////////////////////
2199 
////                                                              ////
2200 
////  Versatile counter                                           ////
2201 
////                                                              ////
2202 
////  Description                                                 ////
2203 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2204 
////  counter                                                     ////
2205 
////                                                              ////
2206 
////  To Do:                                                      ////
2207 
////   - add LFSR with more taps                                  ////
2208 
////                                                              ////
2209 
////  Author(s):                                                  ////
2210 
////      - Michael Unneback, unneback@opencores.org              ////
2211 
////        ORSoC AB                                              ////
2212 
////                                                              ////
2213 
//////////////////////////////////////////////////////////////////////
2214 
////                                                              ////
2215 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2216 
////                                                              ////
2217 
//// This source file may be used and distributed without         ////
2218 
//// restriction provided that this copyright statement is not    ////
2219 
//// removed from the file and that any derivative work contains  ////
2220 
//// the original copyright notice and the associated disclaimer. ////
2221 
////                                                              ////
2222 
//// This source file is free software; you can redistribute it   ////
2223 
//// and/or modify it under the terms of the GNU Lesser General   ////
2224 
//// Public License as published by the Free Software Foundation; ////
2225 
//// either version 2.1 of the License, or (at your option) any   ////
2226 
//// later version.                                               ////
2227 
////                                                              ////
2228 
//// This source is distributed in the hope that it will be       ////
2229 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2230 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2231 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2232 
//// details.                                                     ////
2233 
////                                                              ////
2234 
//// You should have received a copy of the GNU Lesser General    ////
2235 
//// Public License along with this source; if not, download it   ////
2236 
//// from http://www.opencores.org/lgpl.shtml                     ////
2237 
////                                                              ////
2238 
//////////////////////////////////////////////////////////////////////
2239 
 
2240 
// binary counter
2241 
 
2242 40 unneback 
`define MODULE cnt_bin_ce_rew_q_zq_l1
2243 
module `BASE`MODULE (
2244 
`undef MODULE
2245 
 cke, rew, q, zq, level1, rst, clk);
2246 
 
2247 25 unneback 
   parameter length = 4;
2248 
   input cke;
2249 
   input rew;
2250 
   output [length:1] q;
2251 
   output reg zq;
2252 
   output reg level1;
2253 
   input rst;
2254 
   input clk;
2255 
 
2256 
   parameter clear_value = 0;
2257 
   parameter set_value = 1;
2258 
   parameter wrap_value = 1;
2259 
   parameter level1_value = 15;
2260 
 
2261 29 unneback 
   wire clear;
2262 30 unneback 
   assign clear = 1'b0;
2263 25 unneback 
   reg  [length:1] qi;
2264 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2265 
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
2266 
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
2267 
   assign q_next = rew ? q_next_rew : q_next_fw;
2268 
 
2269 
   always @ (posedge clk or posedge rst)
2270 
     if (rst)
2271 
       qi <= {length{1'b0}};
2272 
     else
2273 
     if (cke)
2274 
       qi <= q_next;
2275 
 
2276 
   assign q = qi;
2277 
 
2278 
 
2279 
   always @ (posedge clk or posedge rst)
2280 
     if (rst)
2281 
       zq <= 1'b1;
2282 
     else
2283 
     if (cke)
2284 
       zq <= q_next == {length{1'b0}};
2285 
 
2286 
    always @ (posedge clk or posedge rst)
2287 
    if (rst)
2288 
        level1 <= 1'b0;
2289 
    else
2290 
    if (cke)
2291 29 unneback 
    if (clear)
2292 
        level1 <= 1'b0;
2293 
    else if (q_next == level1_value)
2294 25 unneback 
        level1 <= 1'b1;
2295 
    else if (qi == level1_value & rew)
2296 
        level1 <= 1'b0;
2297 
endmodule
2298 40 unneback 
`endif
2299 
`ifdef CNT_LFSR_ZQ
2300 25 unneback 
//////////////////////////////////////////////////////////////////////
2301 
////                                                              ////
2302 
////  Versatile counter                                           ////
2303 
////                                                              ////
2304 
////  Description                                                 ////
2305 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2306 
////  counter                                                     ////
2307 
////                                                              ////
2308 
////  To Do:                                                      ////
2309 
////   - add LFSR with more taps                                  ////
2310 
////                                                              ////
2311 
////  Author(s):                                                  ////
2312 
////      - Michael Unneback, unneback@opencores.org              ////
2313 
////        ORSoC AB                                              ////
2314 
////                                                              ////
2315 
//////////////////////////////////////////////////////////////////////
2316 
////                                                              ////
2317 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2318 
////                                                              ////
2319 
//// This source file may be used and distributed without         ////
2320 
//// restriction provided that this copyright statement is not    ////
2321 
//// removed from the file and that any derivative work contains  ////
2322 
//// the original copyright notice and the associated disclaimer. ////
2323 
////                                                              ////
2324 
//// This source file is free software; you can redistribute it   ////
2325 
//// and/or modify it under the terms of the GNU Lesser General   ////
2326 
//// Public License as published by the Free Software Foundation; ////
2327 
//// either version 2.1 of the License, or (at your option) any   ////
2328 
//// later version.                                               ////
2329 
////                                                              ////
2330 
//// This source is distributed in the hope that it will be       ////
2331 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2332 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2333 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2334 
//// details.                                                     ////
2335 
////                                                              ////
2336 
//// You should have received a copy of the GNU Lesser General    ////
2337 
//// Public License along with this source; if not, download it   ////
2338 
//// from http://www.opencores.org/lgpl.shtml                     ////
2339 
////                                                              ////
2340 
//////////////////////////////////////////////////////////////////////
2341 
 
2342 6 unneback 
// LFSR counter
2343 
 
2344 40 unneback 
`define MODULE cnt_lfsr_zq
2345 
module `BASE`MODULE (
2346 
`undef MODULE
2347 
 zq, rst, clk);
2348 
 
2349 6 unneback 
   parameter length = 4;
2350 
   output reg zq;
2351 
   input rst;
2352 
   input clk;
2353 
 
2354 
   parameter clear_value = 0;
2355 
   parameter set_value = 1;
2356 
   parameter wrap_value = 8;
2357 
   parameter level1_value = 15;
2358 
 
2359 
   reg  [length:1] qi;
2360 
   reg lfsr_fb;
2361 
   wire [length:1] q_next;
2362 
   reg [32:1] polynom;
2363 
   integer i;
2364 
 
2365 
   always @ (qi)
2366 
   begin
2367 
        case (length)
2368 
         2: polynom = 32'b11;                               // 0x3
2369 
         3: polynom = 32'b110;                              // 0x6
2370 
         4: polynom = 32'b1100;                             // 0xC
2371 
         5: polynom = 32'b10100;                            // 0x14
2372 
         6: polynom = 32'b110000;                           // 0x30
2373 
         7: polynom = 32'b1100000;                          // 0x60
2374 
         8: polynom = 32'b10111000;                         // 0xb8
2375 
         9: polynom = 32'b100010000;                        // 0x110
2376 
        10: polynom = 32'b1001000000;                       // 0x240
2377 
        11: polynom = 32'b10100000000;                      // 0x500
2378 
        12: polynom = 32'b100000101001;                     // 0x829
2379 
        13: polynom = 32'b1000000001100;                    // 0x100C
2380 
        14: polynom = 32'b10000000010101;                   // 0x2015
2381 
        15: polynom = 32'b110000000000000;                  // 0x6000
2382 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2383 
        17: polynom = 32'b10010000000000000;                // 0x12000
2384 
        18: polynom = 32'b100000010000000000;               // 0x20400
2385 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2386 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2387 6 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2388 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2389 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2390 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2391 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2392 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2393 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2394 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2395 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2396 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2397 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2398 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2399 
        default: polynom = 32'b0;
2400 
        endcase
2401 
        lfsr_fb = qi[length];
2402 
        for (i=length-1; i>=1; i=i-1) begin
2403 
            if (polynom[i])
2404 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2405 
        end
2406 
    end
2407 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2408 
 
2409 
   always @ (posedge clk or posedge rst)
2410 
     if (rst)
2411 
       qi <= {length{1'b0}};
2412 
     else
2413 
       qi <= q_next;
2414 
 
2415 
 
2416 
 
2417 
   always @ (posedge clk or posedge rst)
2418 
     if (rst)
2419 
       zq <= 1'b1;
2420 
     else
2421 
       zq <= q_next == {length{1'b0}};
2422 
endmodule
2423 40 unneback 
`endif
2424 75 unneback 
`ifdef CNT_LFSR_CE
2425 
//////////////////////////////////////////////////////////////////////
2426 
////                                                              ////
2427 
////  Versatile counter                                           ////
2428 
////                                                              ////
2429 
////  Description                                                 ////
2430 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2431 
////  counter                                                     ////
2432 
////                                                              ////
2433 
////  To Do:                                                      ////
2434 
////   - add LFSR with more taps                                  ////
2435 
////                                                              ////
2436 
////  Author(s):                                                  ////
2437 
////      - Michael Unneback, unneback@opencores.org              ////
2438 
////        ORSoC AB                                              ////
2439 
////                                                              ////
2440 
//////////////////////////////////////////////////////////////////////
2441 
////                                                              ////
2442 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2443 
////                                                              ////
2444 
//// This source file may be used and distributed without         ////
2445 
//// restriction provided that this copyright statement is not    ////
2446 
//// removed from the file and that any derivative work contains  ////
2447 
//// the original copyright notice and the associated disclaimer. ////
2448 
////                                                              ////
2449 
//// This source file is free software; you can redistribute it   ////
2450 
//// and/or modify it under the terms of the GNU Lesser General   ////
2451 
//// Public License as published by the Free Software Foundation; ////
2452 
//// either version 2.1 of the License, or (at your option) any   ////
2453 
//// later version.                                               ////
2454 
////                                                              ////
2455 
//// This source is distributed in the hope that it will be       ////
2456 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2457 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2458 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2459 
//// details.                                                     ////
2460 
////                                                              ////
2461 
//// You should have received a copy of the GNU Lesser General    ////
2462 
//// Public License along with this source; if not, download it   ////
2463 
//// from http://www.opencores.org/lgpl.shtml                     ////
2464 
////                                                              ////
2465 
//////////////////////////////////////////////////////////////////////
2466 
 
2467 
// LFSR counter
2468 
 
2469 
`define MODULE cnt_lfsr_ce
2470 
module `BASE`MODULE (
2471 
`undef MODULE
2472 
 cke, zq, rst, clk);
2473 
 
2474 
   parameter length = 4;
2475 
   input cke;
2476 
   output reg zq;
2477 
   input rst;
2478 
   input clk;
2479 
 
2480 
   parameter clear_value = 0;
2481 
   parameter set_value = 1;
2482 
   parameter wrap_value = 0;
2483 
   parameter level1_value = 15;
2484 
 
2485 
   reg  [length:1] qi;
2486 
   reg lfsr_fb;
2487 
   wire [length:1] q_next;
2488 
   reg [32:1] polynom;
2489 
   integer i;
2490 
 
2491 
   always @ (qi)
2492 
   begin
2493 
        case (length)
2494 
         2: polynom = 32'b11;                               // 0x3
2495 
         3: polynom = 32'b110;                              // 0x6
2496 
         4: polynom = 32'b1100;                             // 0xC
2497 
         5: polynom = 32'b10100;                            // 0x14
2498 
         6: polynom = 32'b110000;                           // 0x30
2499 
         7: polynom = 32'b1100000;                          // 0x60
2500 
         8: polynom = 32'b10111000;                         // 0xb8
2501 
         9: polynom = 32'b100010000;                        // 0x110
2502 
        10: polynom = 32'b1001000000;                       // 0x240
2503 
        11: polynom = 32'b10100000000;                      // 0x500
2504 
        12: polynom = 32'b100000101001;                     // 0x829
2505 
        13: polynom = 32'b1000000001100;                    // 0x100C
2506 
        14: polynom = 32'b10000000010101;                   // 0x2015
2507 
        15: polynom = 32'b110000000000000;                  // 0x6000
2508 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2509 
        17: polynom = 32'b10010000000000000;                // 0x12000
2510 
        18: polynom = 32'b100000010000000000;               // 0x20400
2511 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2512 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2513 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2514 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2515 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2516 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2517 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2518 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2519 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2520 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2521 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2522 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2523 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2524 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2525 
        default: polynom = 32'b0;
2526 
        endcase
2527 
        lfsr_fb = qi[length];
2528 
        for (i=length-1; i>=1; i=i-1) begin
2529 
            if (polynom[i])
2530 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2531 
        end
2532 
    end
2533 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2534 
 
2535 
   always @ (posedge clk or posedge rst)
2536 
     if (rst)
2537 
       qi <= {length{1'b0}};
2538 
     else
2539 
     if (cke)
2540 
       qi <= q_next;
2541 
 
2542 
 
2543 
 
2544 
   always @ (posedge clk or posedge rst)
2545 
     if (rst)
2546 
       zq <= 1'b1;
2547 
     else
2548 
     if (cke)
2549 
       zq <= q_next == {length{1'b0}};
2550 
endmodule
2551 
`endif
2552 40 unneback 
`ifdef CNT_LFSR_CE_ZQ
2553 6 unneback 
//////////////////////////////////////////////////////////////////////
2554 
////                                                              ////
2555 
////  Versatile counter                                           ////
2556 
////                                                              ////
2557 
////  Description                                                 ////
2558 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2559 
////  counter                                                     ////
2560 
////                                                              ////
2561 
////  To Do:                                                      ////
2562 
////   - add LFSR with more taps                                  ////
2563 
////                                                              ////
2564 
////  Author(s):                                                  ////
2565 
////      - Michael Unneback, unneback@opencores.org              ////
2566 
////        ORSoC AB                                              ////
2567 
////                                                              ////
2568 
//////////////////////////////////////////////////////////////////////
2569 
////                                                              ////
2570 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2571 
////                                                              ////
2572 
//// This source file may be used and distributed without         ////
2573 
//// restriction provided that this copyright statement is not    ////
2574 
//// removed from the file and that any derivative work contains  ////
2575 
//// the original copyright notice and the associated disclaimer. ////
2576 
////                                                              ////
2577 
//// This source file is free software; you can redistribute it   ////
2578 
//// and/or modify it under the terms of the GNU Lesser General   ////
2579 
//// Public License as published by the Free Software Foundation; ////
2580 
//// either version 2.1 of the License, or (at your option) any   ////
2581 
//// later version.                                               ////
2582 
////                                                              ////
2583 
//// This source is distributed in the hope that it will be       ////
2584 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2585 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2586 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2587 
//// details.                                                     ////
2588 
////                                                              ////
2589 
//// You should have received a copy of the GNU Lesser General    ////
2590 
//// Public License along with this source; if not, download it   ////
2591 
//// from http://www.opencores.org/lgpl.shtml                     ////
2592 
////                                                              ////
2593 
//////////////////////////////////////////////////////////////////////
2594 
 
2595 
// LFSR counter
2596 
 
2597 40 unneback 
`define MODULE cnt_lfsr_ce_zq
2598 
module `BASE`MODULE (
2599 
`undef MODULE
2600 
 cke, zq, rst, clk);
2601 
 
2602 6 unneback 
   parameter length = 4;
2603 
   input cke;
2604 
   output reg zq;
2605 
   input rst;
2606 
   input clk;
2607 
 
2608 
   parameter clear_value = 0;
2609 
   parameter set_value = 1;
2610 
   parameter wrap_value = 8;
2611 
   parameter level1_value = 15;
2612 
 
2613 
   reg  [length:1] qi;
2614 
   reg lfsr_fb;
2615 
   wire [length:1] q_next;
2616 
   reg [32:1] polynom;
2617 
   integer i;
2618 
 
2619 
   always @ (qi)
2620 
   begin
2621 
        case (length)
2622 
         2: polynom = 32'b11;                               // 0x3
2623 
         3: polynom = 32'b110;                              // 0x6
2624 
         4: polynom = 32'b1100;                             // 0xC
2625 
         5: polynom = 32'b10100;                            // 0x14
2626 
         6: polynom = 32'b110000;                           // 0x30
2627 
         7: polynom = 32'b1100000;                          // 0x60
2628 
         8: polynom = 32'b10111000;                         // 0xb8
2629 
         9: polynom = 32'b100010000;                        // 0x110
2630 
        10: polynom = 32'b1001000000;                       // 0x240
2631 
        11: polynom = 32'b10100000000;                      // 0x500
2632 
        12: polynom = 32'b100000101001;                     // 0x829
2633 
        13: polynom = 32'b1000000001100;                    // 0x100C
2634 
        14: polynom = 32'b10000000010101;                   // 0x2015
2635 
        15: polynom = 32'b110000000000000;                  // 0x6000
2636 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2637 
        17: polynom = 32'b10010000000000000;                // 0x12000
2638 
        18: polynom = 32'b100000010000000000;               // 0x20400
2639 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2640 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2641 6 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2642 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2643 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2644 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2645 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2646 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2647 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2648 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2649 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2650 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2651 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2652 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2653 
        default: polynom = 32'b0;
2654 
        endcase
2655 
        lfsr_fb = qi[length];
2656 
        for (i=length-1; i>=1; i=i-1) begin
2657 
            if (polynom[i])
2658 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2659 
        end
2660 
    end
2661 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2662 
 
2663 
   always @ (posedge clk or posedge rst)
2664 
     if (rst)
2665 
       qi <= {length{1'b0}};
2666 
     else
2667 
     if (cke)
2668 
       qi <= q_next;
2669 
 
2670 
 
2671 
 
2672 
   always @ (posedge clk or posedge rst)
2673 
     if (rst)
2674 
       zq <= 1'b1;
2675 
     else
2676 
     if (cke)
2677 
       zq <= q_next == {length{1'b0}};
2678 
endmodule
2679 40 unneback 
`endif
2680 
`ifdef CNT_LFSR_CE_Q
2681 6 unneback 
//////////////////////////////////////////////////////////////////////
2682 
////                                                              ////
2683 
////  Versatile counter                                           ////
2684 
////                                                              ////
2685 
////  Description                                                 ////
2686 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2687 
////  counter                                                     ////
2688 
////                                                              ////
2689 
////  To Do:                                                      ////
2690 
////   - add LFSR with more taps                                  ////
2691 
////                                                              ////
2692 
////  Author(s):                                                  ////
2693 
////      - Michael Unneback, unneback@opencores.org              ////
2694 
////        ORSoC AB                                              ////
2695 
////                                                              ////
2696 
//////////////////////////////////////////////////////////////////////
2697 
////                                                              ////
2698 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2699 
////                                                              ////
2700 
//// This source file may be used and distributed without         ////
2701 
//// restriction provided that this copyright statement is not    ////
2702 
//// removed from the file and that any derivative work contains  ////
2703 
//// the original copyright notice and the associated disclaimer. ////
2704 
////                                                              ////
2705 
//// This source file is free software; you can redistribute it   ////
2706 
//// and/or modify it under the terms of the GNU Lesser General   ////
2707 
//// Public License as published by the Free Software Foundation; ////
2708 
//// either version 2.1 of the License, or (at your option) any   ////
2709 
//// later version.                                               ////
2710 
////                                                              ////
2711 
//// This source is distributed in the hope that it will be       ////
2712 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2713 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2714 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2715 
//// details.                                                     ////
2716 
////                                                              ////
2717 
//// You should have received a copy of the GNU Lesser General    ////
2718 
//// Public License along with this source; if not, download it   ////
2719 
//// from http://www.opencores.org/lgpl.shtml                     ////
2720 
////                                                              ////
2721 
//////////////////////////////////////////////////////////////////////
2722 22 unneback 
 
2723 
// LFSR counter
2724 27 unneback 
 
2725 40 unneback 
`define MODULE cnt_lfsr_ce_q
2726 
module `BASE`MODULE (
2727 
`undef MODULE
2728 
 cke, q, rst, clk);
2729 
 
2730 27 unneback 
   parameter length = 4;
2731 
   input cke;
2732 
   output [length:1] q;
2733 
   input rst;
2734 
   input clk;
2735 
 
2736 
   parameter clear_value = 0;
2737 
   parameter set_value = 1;
2738 
   parameter wrap_value = 8;
2739 
   parameter level1_value = 15;
2740 
 
2741 
   reg  [length:1] qi;
2742 
   reg lfsr_fb;
2743 
   wire [length:1] q_next;
2744 
   reg [32:1] polynom;
2745 
   integer i;
2746 
 
2747 
   always @ (qi)
2748 
   begin
2749 
        case (length)
2750 
         2: polynom = 32'b11;                               // 0x3
2751 
         3: polynom = 32'b110;                              // 0x6
2752 
         4: polynom = 32'b1100;                             // 0xC
2753 
         5: polynom = 32'b10100;                            // 0x14
2754 
         6: polynom = 32'b110000;                           // 0x30
2755 
         7: polynom = 32'b1100000;                          // 0x60
2756 
         8: polynom = 32'b10111000;                         // 0xb8
2757 
         9: polynom = 32'b100010000;                        // 0x110
2758 
        10: polynom = 32'b1001000000;                       // 0x240
2759 
        11: polynom = 32'b10100000000;                      // 0x500
2760 
        12: polynom = 32'b100000101001;                     // 0x829
2761 
        13: polynom = 32'b1000000001100;                    // 0x100C
2762 
        14: polynom = 32'b10000000010101;                   // 0x2015
2763 
        15: polynom = 32'b110000000000000;                  // 0x6000
2764 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2765 
        17: polynom = 32'b10010000000000000;                // 0x12000
2766 
        18: polynom = 32'b100000010000000000;               // 0x20400
2767 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2768 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2769 27 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2770 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2771 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2772 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2773 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2774 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2775 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2776 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2777 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2778 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2779 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2780 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2781 
        default: polynom = 32'b0;
2782 
        endcase
2783 
        lfsr_fb = qi[length];
2784 
        for (i=length-1; i>=1; i=i-1) begin
2785 
            if (polynom[i])
2786 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2787 
        end
2788 
    end
2789 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2790 
 
2791 
   always @ (posedge clk or posedge rst)
2792 
     if (rst)
2793 
       qi <= {length{1'b0}};
2794 
     else
2795 
     if (cke)
2796 
       qi <= q_next;
2797 
 
2798 
   assign q = qi;
2799 
 
2800 
endmodule
2801 40 unneback 
`endif
2802 
`ifdef CNT_LFSR_CE_CLEAR_Q
2803 27 unneback 
//////////////////////////////////////////////////////////////////////
2804 
////                                                              ////
2805 
////  Versatile counter                                           ////
2806 
////                                                              ////
2807 
////  Description                                                 ////
2808 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2809 
////  counter                                                     ////
2810 
////                                                              ////
2811 
////  To Do:                                                      ////
2812 
////   - add LFSR with more taps                                  ////
2813 
////                                                              ////
2814 
////  Author(s):                                                  ////
2815 
////      - Michael Unneback, unneback@opencores.org              ////
2816 
////        ORSoC AB                                              ////
2817 
////                                                              ////
2818 
//////////////////////////////////////////////////////////////////////
2819 
////                                                              ////
2820 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2821 
////                                                              ////
2822 
//// This source file may be used and distributed without         ////
2823 
//// restriction provided that this copyright statement is not    ////
2824 
//// removed from the file and that any derivative work contains  ////
2825 
//// the original copyright notice and the associated disclaimer. ////
2826 
////                                                              ////
2827 
//// This source file is free software; you can redistribute it   ////
2828 
//// and/or modify it under the terms of the GNU Lesser General   ////
2829 
//// Public License as published by the Free Software Foundation; ////
2830 
//// either version 2.1 of the License, or (at your option) any   ////
2831 
//// later version.                                               ////
2832 
////                                                              ////
2833 
//// This source is distributed in the hope that it will be       ////
2834 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2835 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2836 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2837 
//// details.                                                     ////
2838 
////                                                              ////
2839 
//// You should have received a copy of the GNU Lesser General    ////
2840 
//// Public License along with this source; if not, download it   ////
2841 
//// from http://www.opencores.org/lgpl.shtml                     ////
2842 
////                                                              ////
2843 
//////////////////////////////////////////////////////////////////////
2844 
 
2845 
// LFSR counter
2846 
 
2847 40 unneback 
`define MODULE cnt_lfsr_ce_clear_q
2848 
module `BASE`MODULE (
2849 
`undef MODULE
2850 
 clear, cke, q, rst, clk);
2851 
 
2852 27 unneback 
   parameter length = 4;
2853 
   input clear;
2854 
   input cke;
2855 
   output [length:1] q;
2856 
   input rst;
2857 
   input clk;
2858 
 
2859 
   parameter clear_value = 0;
2860 
   parameter set_value = 1;
2861 
   parameter wrap_value = 8;
2862 
   parameter level1_value = 15;
2863 
 
2864 
   reg  [length:1] qi;
2865 
   reg lfsr_fb;
2866 
   wire [length:1] q_next;
2867 
   reg [32:1] polynom;
2868 
   integer i;
2869 
 
2870 
   always @ (qi)
2871 
   begin
2872 
        case (length)
2873 
         2: polynom = 32'b11;                               // 0x3
2874 
         3: polynom = 32'b110;                              // 0x6
2875 
         4: polynom = 32'b1100;                             // 0xC
2876 
         5: polynom = 32'b10100;                            // 0x14
2877 
         6: polynom = 32'b110000;                           // 0x30
2878 
         7: polynom = 32'b1100000;                          // 0x60
2879 
         8: polynom = 32'b10111000;                         // 0xb8
2880 
         9: polynom = 32'b100010000;                        // 0x110
2881 
        10: polynom = 32'b1001000000;                       // 0x240
2882 
        11: polynom = 32'b10100000000;                      // 0x500
2883 
        12: polynom = 32'b100000101001;                     // 0x829
2884 
        13: polynom = 32'b1000000001100;                    // 0x100C
2885 
        14: polynom = 32'b10000000010101;                   // 0x2015
2886 
        15: polynom = 32'b110000000000000;                  // 0x6000
2887 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2888 
        17: polynom = 32'b10010000000000000;                // 0x12000
2889 
        18: polynom = 32'b100000010000000000;               // 0x20400
2890 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2891 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2892 27 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2893 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2894 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2895 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2896 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2897 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2898 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2899 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2900 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2901 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2902 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2903 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2904 
        default: polynom = 32'b0;
2905 
        endcase
2906 
        lfsr_fb = qi[length];
2907 
        for (i=length-1; i>=1; i=i-1) begin
2908 
            if (polynom[i])
2909 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2910 
        end
2911 
    end
2912 
   assign q_next =  clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2913 
 
2914 
   always @ (posedge clk or posedge rst)
2915 
     if (rst)
2916 
       qi <= {length{1'b0}};
2917 
     else
2918 
     if (cke)
2919 
       qi <= q_next;
2920 
 
2921 
   assign q = qi;
2922 
 
2923 
endmodule
2924 40 unneback 
`endif
2925 
`ifdef CNT_LFSR_CE_Q_ZQ
2926 27 unneback 
//////////////////////////////////////////////////////////////////////
2927 
////                                                              ////
2928 
////  Versatile counter                                           ////
2929 
////                                                              ////
2930 
////  Description                                                 ////
2931 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2932 
////  counter                                                     ////
2933 
////                                                              ////
2934 
////  To Do:                                                      ////
2935 
////   - add LFSR with more taps                                  ////
2936 
////                                                              ////
2937 
////  Author(s):                                                  ////
2938 
////      - Michael Unneback, unneback@opencores.org              ////
2939 
////        ORSoC AB                                              ////
2940 
////                                                              ////
2941 
//////////////////////////////////////////////////////////////////////
2942 
////                                                              ////
2943 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2944 
////                                                              ////
2945 
//// This source file may be used and distributed without         ////
2946 
//// restriction provided that this copyright statement is not    ////
2947 
//// removed from the file and that any derivative work contains  ////
2948 
//// the original copyright notice and the associated disclaimer. ////
2949 
////                                                              ////
2950 
//// This source file is free software; you can redistribute it   ////
2951 
//// and/or modify it under the terms of the GNU Lesser General   ////
2952 
//// Public License as published by the Free Software Foundation; ////
2953 
//// either version 2.1 of the License, or (at your option) any   ////
2954 
//// later version.                                               ////
2955 
////                                                              ////
2956 
//// This source is distributed in the hope that it will be       ////
2957 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2958 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2959 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2960 
//// details.                                                     ////
2961 
////                                                              ////
2962 
//// You should have received a copy of the GNU Lesser General    ////
2963 
//// Public License along with this source; if not, download it   ////
2964 
//// from http://www.opencores.org/lgpl.shtml                     ////
2965 
////                                                              ////
2966 
//////////////////////////////////////////////////////////////////////
2967 
 
2968 
// LFSR counter
2969 22 unneback 
 
2970 40 unneback 
`define MODULE cnt_lfsr_ce_q_zq
2971 
module `BASE`MODULE (
2972 
`undef MODULE
2973 
 cke, q, zq, rst, clk);
2974 
 
2975 22 unneback 
   parameter length = 4;
2976 
   input cke;
2977 
   output [length:1] q;
2978 
   output reg zq;
2979 
   input rst;
2980 
   input clk;
2981 
 
2982 
   parameter clear_value = 0;
2983 
   parameter set_value = 1;
2984 
   parameter wrap_value = 8;
2985 
   parameter level1_value = 15;
2986 
 
2987 
   reg  [length:1] qi;
2988 
   reg lfsr_fb;
2989 
   wire [length:1] q_next;
2990 
   reg [32:1] polynom;
2991 
   integer i;
2992 
 
2993 
   always @ (qi)
2994 
   begin
2995 
        case (length)
2996 
         2: polynom = 32'b11;                               // 0x3
2997 
         3: polynom = 32'b110;                              // 0x6
2998 
         4: polynom = 32'b1100;                             // 0xC
2999 
         5: polynom = 32'b10100;                            // 0x14
3000 
         6: polynom = 32'b110000;                           // 0x30
3001 
         7: polynom = 32'b1100000;                          // 0x60
3002 
         8: polynom = 32'b10111000;                         // 0xb8
3003 
         9: polynom = 32'b100010000;                        // 0x110
3004 
        10: polynom = 32'b1001000000;                       // 0x240
3005 
        11: polynom = 32'b10100000000;                      // 0x500
3006 
        12: polynom = 32'b100000101001;                     // 0x829
3007 
        13: polynom = 32'b1000000001100;                    // 0x100C
3008 
        14: polynom = 32'b10000000010101;                   // 0x2015
3009 
        15: polynom = 32'b110000000000000;                  // 0x6000
3010 
        16: polynom = 32'b1101000000001000;                 // 0xD008
3011 
        17: polynom = 32'b10010000000000000;                // 0x12000
3012 
        18: polynom = 32'b100000010000000000;               // 0x20400
3013 
        19: polynom = 32'b1000000000000100011;              // 0x40023
3014 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
3015 22 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
3016 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
3017 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
3018 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
3019 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
3020 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
3021 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
3022 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
3023 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
3024 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
3025 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
3026 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
3027 
        default: polynom = 32'b0;
3028 
        endcase
3029 
        lfsr_fb = qi[length];
3030 
        for (i=length-1; i>=1; i=i-1) begin
3031 
            if (polynom[i])
3032 
                lfsr_fb = lfsr_fb  ~^ qi[i];
3033 
        end
3034 
    end
3035 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
3036 
 
3037 
   always @ (posedge clk or posedge rst)
3038 
     if (rst)
3039 
       qi <= {length{1'b0}};
3040 
     else
3041 
     if (cke)
3042 
       qi <= q_next;
3043 
 
3044 
   assign q = qi;
3045 
 
3046 
 
3047 
   always @ (posedge clk or posedge rst)
3048 
     if (rst)
3049 
       zq <= 1'b1;
3050 
     else
3051 
     if (cke)
3052 
       zq <= q_next == {length{1'b0}};
3053 
endmodule
3054 40 unneback 
`endif
3055 
`ifdef CNT_LFSR_CE_REW_L1
3056 22 unneback 
//////////////////////////////////////////////////////////////////////
3057 
////                                                              ////
3058 
////  Versatile counter                                           ////
3059 
////                                                              ////
3060 
////  Description                                                 ////
3061 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3062 
////  counter                                                     ////
3063 
////                                                              ////
3064 
////  To Do:                                                      ////
3065 
////   - add LFSR with more taps                                  ////
3066 
////                                                              ////
3067 
////  Author(s):                                                  ////
3068 
////      - Michael Unneback, unneback@opencores.org              ////
3069 
////        ORSoC AB                                              ////
3070 
////                                                              ////
3071 
//////////////////////////////////////////////////////////////////////
3072 
////                                                              ////
3073 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3074 
////                                                              ////
3075 
//// This source file may be used and distributed without         ////
3076 
//// restriction provided that this copyright statement is not    ////
3077 
//// removed from the file and that any derivative work contains  ////
3078 
//// the original copyright notice and the associated disclaimer. ////
3079 
////                                                              ////
3080 
//// This source file is free software; you can redistribute it   ////
3081 
//// and/or modify it under the terms of the GNU Lesser General   ////
3082 
//// Public License as published by the Free Software Foundation; ////
3083 
//// either version 2.1 of the License, or (at your option) any   ////
3084 
//// later version.                                               ////
3085 
////                                                              ////
3086 
//// This source is distributed in the hope that it will be       ////
3087 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3088 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3089 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3090 
//// details.                                                     ////
3091 
////                                                              ////
3092 
//// You should have received a copy of the GNU Lesser General    ////
3093 
//// Public License along with this source; if not, download it   ////
3094 
//// from http://www.opencores.org/lgpl.shtml                     ////
3095 
////                                                              ////
3096 
//////////////////////////////////////////////////////////////////////
3097 6 unneback 
 
3098 
// LFSR counter
3099 
 
3100 40 unneback 
`define MODULE cnt_lfsr_ce_rew_l1
3101 
module `BASE`MODULE (
3102 
`undef MODULE
3103 
 cke, rew, level1, rst, clk);
3104 
 
3105 6 unneback 
   parameter length = 4;
3106 
   input cke;
3107 
   input rew;
3108 
   output reg level1;
3109 
   input rst;
3110 
   input clk;
3111 
 
3112 
   parameter clear_value = 0;
3113 
   parameter set_value = 1;
3114 
   parameter wrap_value = 8;
3115 
   parameter level1_value = 15;
3116 
 
3117 29 unneback 
   wire clear;
3118 30 unneback 
   assign clear = 1'b0;
3119 6 unneback 
   reg  [length:1] qi;
3120 
   reg lfsr_fb, lfsr_fb_rew;
3121 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
3122 
   reg [32:1] polynom_rew;
3123 
   integer j;
3124 
   reg [32:1] polynom;
3125 
   integer i;
3126 
 
3127 
   always @ (qi)
3128 
   begin
3129 
        case (length)
3130 
         2: polynom = 32'b11;                               // 0x3
3131 
         3: polynom = 32'b110;                              // 0x6
3132 
         4: polynom = 32'b1100;                             // 0xC
3133 
         5: polynom = 32'b10100;                            // 0x14
3134 
         6: polynom = 32'b110000;                           // 0x30
3135 
         7: polynom = 32'b1100000;                          // 0x60
3136 
         8: polynom = 32'b10111000;                         // 0xb8
3137 
         9: polynom = 32'b100010000;                        // 0x110
3138 
        10: polynom = 32'b1001000000;                       // 0x240
3139 
        11: polynom = 32'b10100000000;                      // 0x500
3140 
        12: polynom = 32'b100000101001;                     // 0x829
3141 
        13: polynom = 32'b1000000001100;                    // 0x100C
3142 
        14: polynom = 32'b10000000010101;                   // 0x2015
3143 
        15: polynom = 32'b110000000000000;                  // 0x6000
3144 
        16: polynom = 32'b1101000000001000;                 // 0xD008
3145 
        17: polynom = 32'b10010000000000000;                // 0x12000
3146 
        18: polynom = 32'b100000010000000000;               // 0x20400
3147 
        19: polynom = 32'b1000000000000100011;              // 0x40023
3148 37 unneback 
        20: polynom = 32'b10010000000000000000;             // 0x90000
3149 6 unneback 
        21: polynom = 32'b101000000000000000000;            // 0x140000
3150 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
3151 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
3152 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
3153 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
3154 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
3155 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
3156 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
3157 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
3158 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
3159 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
3160 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
3161 
        default: polynom = 32'b0;
3162 
        endcase
3163 
        lfsr_fb = qi[length];
3164 
        for (i=length-1; i>=1; i=i-1) begin
3165 
            if (polynom[i])
3166 
                lfsr_fb = lfsr_fb  ~^ qi[i];
3167 
        end
3168 
    end
3169 
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
3170 
   always @ (qi)
3171 
   begin
3172 
        case (length)
3173 
         2: polynom_rew = 32'b11;
3174 
         3: polynom_rew = 32'b110;
3175 
         4: polynom_rew = 32'b1100;
3176 
         5: polynom_rew = 32'b10100;
3177 
         6: polynom_rew = 32'b110000;
3178 
         7: polynom_rew = 32'b1100000;
3179 
         8: polynom_rew = 32'b10111000;
3180 
         9: polynom_rew = 32'b100010000;
3181 
        10: polynom_rew = 32'b1001000000;
3182 
        11: polynom_rew = 32'b10100000000;
3183 
        12: polynom_rew = 32'b100000101001;
3184 
        13: polynom_rew = 32'b1000000001100;
3185 
        14: polynom_rew = 32'b10000000010101;
3186 
        15: polynom_rew = 32'b110000000000000;
3187 
        16: polynom_rew = 32'b1101000000001000;
3188 
        17: polynom_rew = 32'b10010000000000000;
3189 
        18: polynom_rew = 32'b100000010000000000;
3190 
        19: polynom_rew = 32'b1000000000000100011;
3191 
        20: polynom_rew = 32'b10000010000000000000;
3192 
        21: polynom_rew = 32'b101000000000000000000;
3193 
        22: polynom_rew = 32'b1100000000000000000000;
3194 
        23: polynom_rew = 32'b10000100000000000000000;
3195 
        24: polynom_rew = 32'b111000010000000000000000;
3196 
        25: polynom_rew = 32'b1001000000000000000000000;
3197 
        26: polynom_rew = 32'b10000000000000000000100011;
3198 
        27: polynom_rew = 32'b100000000000000000000010011;
3199 
        28: polynom_rew = 32'b1100100000000000000000000000;
3200 
        29: polynom_rew = 32'b10100000000000000000000000000;
3201 
        30: polynom_rew = 32'b100000000000000000000000101001;
3202 
        31: polynom_rew = 32'b1001000000000000000000000000000;
3203 
        32: polynom_rew = 32'b10000000001000000000000000000011;
3204 
        default: polynom_rew = 32'b0;
3205 
        endcase
3206 
        // rotate left
3207 
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
3208 
        lfsr_fb_rew = qi[length];
3209 
        for (i=length-1; i>=1; i=i-1) begin
3210 
            if (polynom_rew[i])
3211 
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
3212 
        end
3213 
    end
3214 
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
3215 
   assign q_next = rew ? q_next_rew : q_next_fw;
3216 
 
3217 
   always @ (posedge clk or posedge rst)
3218 
     if (rst)
3219 
       qi <= {length{1'b0}};
3220 
     else
3221 
     if (cke)
3222 
       qi <= q_next;
3223 
 
3224 
 
3225 
 
3226 
    always @ (posedge clk or posedge rst)
3227 
    if (rst)
3228 
        level1 <= 1'b0;
3229 
    else
3230 
    if (cke)
3231 29 unneback 
    if (clear)
3232 
        level1 <= 1'b0;
3233 
    else if (q_next == level1_value)
3234 6 unneback 
        level1 <= 1'b1;
3235 
    else if (qi == level1_value & rew)
3236 
        level1 <= 1'b0;
3237 
endmodule
3238 40 unneback 
`endif
3239 
`ifdef CNT_GRAY
3240 6 unneback 
//////////////////////////////////////////////////////////////////////
3241 
////                                                              ////
3242 
////  Versatile counter                                           ////
3243 
////                                                              ////
3244 
////  Description                                                 ////
3245 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3246 
////  counter                                                     ////
3247 
////                                                              ////
3248 
////  To Do:                                                      ////
3249 
////   - add LFSR with more taps                                  ////
3250 
////                                                              ////
3251 
////  Author(s):                                                  ////
3252 
////      - Michael Unneback, unneback@opencores.org              ////
3253 
////        ORSoC AB                                              ////
3254 
////                                                              ////
3255 
//////////////////////////////////////////////////////////////////////
3256 
////                                                              ////
3257 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3258 
////                                                              ////
3259 
//// This source file may be used and distributed without         ////
3260 
//// restriction provided that this copyright statement is not    ////
3261 
//// removed from the file and that any derivative work contains  ////
3262 
//// the original copyright notice and the associated disclaimer. ////
3263 
////                                                              ////
3264 
//// This source file is free software; you can redistribute it   ////
3265 
//// and/or modify it under the terms of the GNU Lesser General   ////
3266 
//// Public License as published by the Free Software Foundation; ////
3267 
//// either version 2.1 of the License, or (at your option) any   ////
3268 
//// later version.                                               ////
3269 
////                                                              ////
3270 
//// This source is distributed in the hope that it will be       ////
3271 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3272 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3273 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3274 
//// details.                                                     ////
3275 
////                                                              ////
3276 
//// You should have received a copy of the GNU Lesser General    ////
3277 
//// Public License along with this source; if not, download it   ////
3278 
//// from http://www.opencores.org/lgpl.shtml                     ////
3279 
////                                                              ////
3280 
//////////////////////////////////////////////////////////////////////
3281 
 
3282 
// GRAY counter
3283 
 
3284 40 unneback 
`define MODULE cnt_gray
3285 
module `BASE`MODULE (
3286 
`undef MODULE
3287 
 q, rst, clk);
3288 
 
3289 6 unneback 
   parameter length = 4;
3290 
   output reg [length:1] q;
3291 
   input rst;
3292 
   input clk;
3293 
 
3294 
   parameter clear_value = 0;
3295 
   parameter set_value = 1;
3296 
   parameter wrap_value = 8;
3297 
   parameter level1_value = 15;
3298 
 
3299 
   reg  [length:1] qi;
3300 
   wire [length:1] q_next;
3301 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3302 
 
3303 
   always @ (posedge clk or posedge rst)
3304 
     if (rst)
3305 
       qi <= {length{1'b0}};
3306 
     else
3307 
       qi <= q_next;
3308 
 
3309 
   always @ (posedge clk or posedge rst)
3310 
     if (rst)
3311 
       q <= {length{1'b0}};
3312 
     else
3313 
         q <= (q_next>>1) ^ q_next;
3314 
 
3315 
endmodule
3316 40 unneback 
`endif
3317 
`ifdef CNT_GRAY_CE
3318 6 unneback 
//////////////////////////////////////////////////////////////////////
3319 
////                                                              ////
3320 
////  Versatile counter                                           ////
3321 
////                                                              ////
3322 
////  Description                                                 ////
3323 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3324 
////  counter                                                     ////
3325 
////                                                              ////
3326 
////  To Do:                                                      ////
3327 
////   - add LFSR with more taps                                  ////
3328 
////                                                              ////
3329 
////  Author(s):                                                  ////
3330 
////      - Michael Unneback, unneback@opencores.org              ////
3331 
////        ORSoC AB                                              ////
3332 
////                                                              ////
3333 
//////////////////////////////////////////////////////////////////////
3334 
////                                                              ////
3335 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3336 
////                                                              ////
3337 
//// This source file may be used and distributed without         ////
3338 
//// restriction provided that this copyright statement is not    ////
3339 
//// removed from the file and that any derivative work contains  ////
3340 
//// the original copyright notice and the associated disclaimer. ////
3341 
////                                                              ////
3342 
//// This source file is free software; you can redistribute it   ////
3343 
//// and/or modify it under the terms of the GNU Lesser General   ////
3344 
//// Public License as published by the Free Software Foundation; ////
3345 
//// either version 2.1 of the License, or (at your option) any   ////
3346 
//// later version.                                               ////
3347 
////                                                              ////
3348 
//// This source is distributed in the hope that it will be       ////
3349 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3350 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3351 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3352 
//// details.                                                     ////
3353 
////                                                              ////
3354 
//// You should have received a copy of the GNU Lesser General    ////
3355 
//// Public License along with this source; if not, download it   ////
3356 
//// from http://www.opencores.org/lgpl.shtml                     ////
3357 
////                                                              ////
3358 
//////////////////////////////////////////////////////////////////////
3359 
 
3360 
// GRAY counter
3361 
 
3362 40 unneback 
`define MODULE cnt_gray_ce
3363 
module `BASE`MODULE (
3364 
`undef MODULE
3365 
 cke, q, rst, clk);
3366 
 
3367 6 unneback 
   parameter length = 4;
3368 
   input cke;
3369 
   output reg [length:1] q;
3370 
   input rst;
3371 
   input clk;
3372 
 
3373 
   parameter clear_value = 0;
3374 
   parameter set_value = 1;
3375 
   parameter wrap_value = 8;
3376 
   parameter level1_value = 15;
3377 
 
3378 
   reg  [length:1] qi;
3379 
   wire [length:1] q_next;
3380 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3381 
 
3382 
   always @ (posedge clk or posedge rst)
3383 
     if (rst)
3384 
       qi <= {length{1'b0}};
3385 
     else
3386 
     if (cke)
3387 
       qi <= q_next;
3388 
 
3389 
   always @ (posedge clk or posedge rst)
3390 
     if (rst)
3391 
       q <= {length{1'b0}};
3392 
     else
3393 
       if (cke)
3394 
         q <= (q_next>>1) ^ q_next;
3395 
 
3396 
endmodule
3397 40 unneback 
`endif
3398 
`ifdef CNT_GRAY_CE_BIN
3399 6 unneback 
//////////////////////////////////////////////////////////////////////
3400 
////                                                              ////
3401 
////  Versatile counter                                           ////
3402 
////                                                              ////
3403 
////  Description                                                 ////
3404 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
3405 
////  counter                                                     ////
3406 
////                                                              ////
3407 
////  To Do:                                                      ////
3408 
////   - add LFSR with more taps                                  ////
3409 
////                                                              ////
3410 
////  Author(s):                                                  ////
3411 
////      - Michael Unneback, unneback@opencores.org              ////
3412 
////        ORSoC AB                                              ////
3413 
////                                                              ////
3414 
//////////////////////////////////////////////////////////////////////
3415 
////                                                              ////
3416 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
3417 
////                                                              ////
3418 
//// This source file may be used and distributed without         ////
3419 
//// restriction provided that this copyright statement is not    ////
3420 
//// removed from the file and that any derivative work contains  ////
3421 
//// the original copyright notice and the associated disclaimer. ////
3422 
////                                                              ////
3423 
//// This source file is free software; you can redistribute it   ////
3424 
//// and/or modify it under the terms of the GNU Lesser General   ////
3425 
//// Public License as published by the Free Software Foundation; ////
3426 
//// either version 2.1 of the License, or (at your option) any   ////
3427 
//// later version.                                               ////
3428 
////                                                              ////
3429 
//// This source is distributed in the hope that it will be       ////
3430 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3431 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3432 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3433 
//// details.                                                     ////
3434 
////                                                              ////
3435 
//// You should have received a copy of the GNU Lesser General    ////
3436 
//// Public License along with this source; if not, download it   ////
3437 
//// from http://www.opencores.org/lgpl.shtml                     ////
3438 
////                                                              ////
3439 
//////////////////////////////////////////////////////////////////////
3440 
 
3441 
// GRAY counter
3442 
 
3443 40 unneback 
`define MODULE cnt_gray_ce_bin
3444 
module `BASE`MODULE (
3445 
`undef MODULE
3446 
 cke, q, q_bin, rst, clk);
3447 
 
3448 6 unneback 
   parameter length = 4;
3449 
   input cke;
3450 
   output reg [length:1] q;
3451 
   output [length:1] q_bin;
3452 
   input rst;
3453 
   input clk;
3454 
 
3455 
   parameter clear_value = 0;
3456 
   parameter set_value = 1;
3457 
   parameter wrap_value = 8;
3458 
   parameter level1_value = 15;
3459 
 
3460 
   reg  [length:1] qi;
3461 
   wire [length:1] q_next;
3462 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
3463 
 
3464 
   always @ (posedge clk or posedge rst)
3465 
     if (rst)
3466 
       qi <= {length{1'b0}};
3467 
     else
3468 
     if (cke)
3469 
       qi <= q_next;
3470 
 
3471 
   always @ (posedge clk or posedge rst)
3472 
     if (rst)
3473 
       q <= {length{1'b0}};
3474 
     else
3475 
       if (cke)
3476 
         q <= (q_next>>1) ^ q_next;
3477 
 
3478 
   assign q_bin = qi;
3479 
 
3480 
endmodule
3481 40 unneback 
`endif
3482 6 unneback 
//////////////////////////////////////////////////////////////////////
3483 
////                                                              ////
3484 
////  Versatile library, counters                                 ////
3485 
////                                                              ////
3486 
////  Description                                                 ////
3487 
////  counters                                                    ////
3488 
////                                                              ////
3489 
////                                                              ////
3490 
////  To Do:                                                      ////
3491 
////   - add more counters                                        ////
3492 
////                                                              ////
3493 
////  Author(s):                                                  ////
3494 
////      - Michael Unneback, unneback@opencores.org              ////
3495 
////        ORSoC AB                                              ////
3496 
////                                                              ////
3497 
//////////////////////////////////////////////////////////////////////
3498 
////                                                              ////
3499 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
3500 
////                                                              ////
3501 
//// This source file may be used and distributed without         ////
3502 
//// restriction provided that this copyright statement is not    ////
3503 
//// removed from the file and that any derivative work contains  ////
3504 
//// the original copyright notice and the associated disclaimer. ////
3505 
////                                                              ////
3506 
//// This source file is free software; you can redistribute it   ////
3507 
//// and/or modify it under the terms of the GNU Lesser General   ////
3508 
//// Public License as published by the Free Software Foundation; ////
3509 
//// either version 2.1 of the License, or (at your option) any   ////
3510 
//// later version.                                               ////
3511 
////                                                              ////
3512 
//// This source is distributed in the hope that it will be       ////
3513 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3514 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3515 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3516 
//// details.                                                     ////
3517 
////                                                              ////
3518 
//// You should have received a copy of the GNU Lesser General    ////
3519 
//// Public License along with this source; if not, download it   ////
3520 
//// from http://www.opencores.org/lgpl.shtml                     ////
3521 
////                                                              ////
3522 
//////////////////////////////////////////////////////////////////////
3523 
 
3524 40 unneback 
`ifdef CNT_SHREG_WRAP
3525 
`define MODULE cnt_shreg_wrap
3526 
module `BASE`MODULE ( q, rst, clk);
3527 
`undef MODULE
3528 6 unneback 
 
3529 
   parameter length = 4;
3530 
   output reg [0:length-1] q;
3531 
   input rst;
3532 
   input clk;
3533 
 
3534 
    always @ (posedge clk or posedge rst)
3535 
    if (rst)
3536 
        q <= {1'b1,{length-1{1'b0}}};
3537 
    else
3538 
        q <= {q[length-1],q[0:length-2]};
3539 
 
3540 
endmodule
3541 40 unneback 
`endif
3542 6 unneback 
 
3543 40 unneback 
`ifdef CNT_SHREG_CE_WRAP
3544 
`define MODULE cnt_shreg_ce_wrap
3545 
module `BASE`MODULE ( cke, q, rst, clk);
3546 
`undef MODULE
3547 6 unneback 
 
3548 
   parameter length = 4;
3549 
   input cke;
3550 
   output reg [0:length-1] q;
3551 
   input rst;
3552 
   input clk;
3553 
 
3554 
    always @ (posedge clk or posedge rst)
3555 
    if (rst)
3556 
        q <= {1'b1,{length-1{1'b0}}};
3557 
    else
3558 
        if (cke)
3559 
            q <= {q[length-1],q[0:length-2]};
3560 
 
3561 
endmodule
3562 40 unneback 
`endif
3563 6 unneback 
 
3564 40 unneback 
`ifdef CNT_SHREG_CE_CLEAR
3565 
`define MODULE cnt_shreg_ce_clear
3566 
module `BASE`MODULE ( cke, clear, q, rst, clk);
3567 
`undef MODULE
3568 6 unneback 
 
3569 
   parameter length = 4;
3570 
   input cke, clear;
3571 
   output reg [0:length-1] q;
3572 
   input rst;
3573 
   input clk;
3574 
 
3575 
    always @ (posedge clk or posedge rst)
3576 
    if (rst)
3577 
        q <= {1'b1,{length-1{1'b0}}};
3578 
    else
3579 
        if (cke)
3580 
            if (clear)
3581 
                q <= {1'b1,{length-1{1'b0}}};
3582 
            else
3583 
                q <= q >> 1;
3584 
 
3585 
endmodule
3586 40 unneback 
`endif
3587 6 unneback 
 
3588 40 unneback 
`ifdef CNT_SHREG_CE_CLEAR_WRAP
3589 
`define MODULE cnt_shreg_ce_clear_wrap
3590 
module `BASE`MODULE ( cke, clear, q, rst, clk);
3591 
`undef MODULE
3592 6 unneback 
 
3593 
   parameter length = 4;
3594 
   input cke, clear;
3595 
   output reg [0:length-1] q;
3596 
   input rst;
3597 
   input clk;
3598 
 
3599 
    always @ (posedge clk or posedge rst)
3600 
    if (rst)
3601 
        q <= {1'b1,{length-1{1'b0}}};
3602 
    else
3603 
        if (cke)
3604 
            if (clear)
3605 
                q <= {1'b1,{length-1{1'b0}}};
3606 
            else
3607 
            q <= {q[length-1],q[0:length-2]};
3608 
 
3609 
endmodule
3610 40 unneback 
`endif
3611 6 unneback 
//////////////////////////////////////////////////////////////////////
3612 
////                                                              ////
3613 
////  Versatile library, memories                                 ////
3614 
////                                                              ////
3615 
////  Description                                                 ////
3616 
////  memories                                                    ////
3617 
////                                                              ////
3618 
////                                                              ////
3619 
////  To Do:                                                      ////
3620 
////   - add more memory types                                    ////
3621 
////                                                              ////
3622 
////  Author(s):                                                  ////
3623 
////      - Michael Unneback, unneback@opencores.org              ////
3624 
////        ORSoC AB                                              ////
3625 
////                                                              ////
3626 
//////////////////////////////////////////////////////////////////////
3627 
////                                                              ////
3628 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
3629 
////                                                              ////
3630 
//// This source file may be used and distributed without         ////
3631 
//// restriction provided that this copyright statement is not    ////
3632 
//// removed from the file and that any derivative work contains  ////
3633 
//// the original copyright notice and the associated disclaimer. ////
3634 
////                                                              ////
3635 
//// This source file is free software; you can redistribute it   ////
3636 
//// and/or modify it under the terms of the GNU Lesser General   ////
3637 
//// Public License as published by the Free Software Foundation; ////
3638 
//// either version 2.1 of the License, or (at your option) any   ////
3639 
//// later version.                                               ////
3640 
////                                                              ////
3641 
//// This source is distributed in the hope that it will be       ////
3642 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3643 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3644 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3645 
//// details.                                                     ////
3646 
////                                                              ////
3647 
//// You should have received a copy of the GNU Lesser General    ////
3648 
//// Public License along with this source; if not, download it   ////
3649 
//// from http://www.opencores.org/lgpl.shtml                     ////
3650 
////                                                              ////
3651 
//////////////////////////////////////////////////////////////////////
3652 
 
3653 40 unneback 
`ifdef ROM_INIT
3654 6 unneback 
/// ROM
3655 40 unneback 
`define MODULE rom_init
3656 
module `BASE`MODULE ( adr, q, clk);
3657 
`undef MODULE
3658 6 unneback 
 
3659 7 unneback 
   parameter data_width = 32;
3660 
   parameter addr_width = 8;
3661 75 unneback 
   parameter mem_size = 1<<addr_width;
3662 7 unneback 
   input [(addr_width-1):0]       adr;
3663 
   output reg [(data_width-1):0] q;
3664 
   input                         clk;
3665 75 unneback 
   reg [data_width-1:0] rom [mem_size-1:0];
3666 7 unneback 
   parameter memory_file = "vl_rom.vmem";
3667 
   initial
3668 
     begin
3669 
        $readmemh(memory_file, rom);
3670 
     end
3671 
 
3672 
   always @ (posedge clk)
3673 
     q <= rom[adr];
3674 6 unneback 
 
3675 7 unneback 
endmodule
3676 40 unneback 
`endif
3677 7 unneback 
 
3678 40 unneback 
`ifdef RAM
3679 
`define MODULE ram
3680 6 unneback 
// Single port RAM
3681 40 unneback 
module `BASE`MODULE ( d, adr, we, q, clk);
3682 
`undef MODULE
3683 6 unneback 
 
3684 
   parameter data_width = 32;
3685 
   parameter addr_width = 8;
3686 75 unneback 
   parameter mem_size = 1<<addr_width;
3687 6 unneback 
   input [(data_width-1):0]      d;
3688 
   input [(addr_width-1):0]       adr;
3689 
   input                         we;
3690 7 unneback 
   output reg [(data_width-1):0] q;
3691 6 unneback 
   input                         clk;
3692 75 unneback 
   reg [data_width-1:0] ram [mem_szie-1:0];
3693 7 unneback 
   parameter init = 0;
3694 
   parameter memory_file = "vl_ram.vmem";
3695 
   generate if (init) begin : init_mem
3696 
   initial
3697 
     begin
3698 
        $readmemh(memory_file, ram);
3699 
     end
3700 
   end
3701 
   endgenerate
3702 
 
3703 6 unneback 
   always @ (posedge clk)
3704 
   begin
3705 
   if (we)
3706 
     ram[adr] <= d;
3707 
   q <= ram[adr];
3708 
   end
3709 
 
3710 
endmodule
3711 40 unneback 
`endif
3712 6 unneback 
 
3713 40 unneback 
`ifdef RAM_BE
3714 
`define MODULE ram_be
3715 
module `BASE`MODULE ( d, adr, be, we, q, clk);
3716 
`undef MODULE
3717 
 
3718 7 unneback 
   parameter data_width = 32;
3719 72 unneback 
   parameter addr_width = 6;
3720 75 unneback 
   parameter mem_size = 1<<addr_width;
3721 7 unneback 
   input [(data_width-1):0]      d;
3722 
   input [(addr_width-1):0]       adr;
3723 73 unneback 
   input [(data_width/8)-1:0]    be;
3724 7 unneback 
   input                         we;
3725 
   output reg [(data_width-1):0] q;
3726 
   input                         clk;
3727 
 
3728 65 unneback 
`ifdef SYSTEMVERILOG
3729 68 unneback 
   logic [data_width/8-1:0][7:0] ram[0:mem_size-1];// # words = 1 << address width
3730 65 unneback 
`else
3731 68 unneback 
   reg [data_width-1:0] ram [mem_size-1:0];
3732 65 unneback 
`endif
3733 
 
3734 60 unneback 
   parameter memory_init = 0;
3735 7 unneback 
   parameter memory_file = "vl_ram.vmem";
3736 60 unneback 
   generate if (memory_init) begin : init_mem
3737 7 unneback 
   initial
3738 
     begin
3739 
        $readmemh(memory_file, ram);
3740 
     end
3741 
   end
3742 
   endgenerate
3743 
 
3744 60 unneback 
`ifdef SYSTEMVERILOG
3745 
// use a multi-dimensional packed array
3746 
//to model individual bytes within the word
3747 
 
3748 
always_ff@(posedge clk)
3749 
begin
3750 
    if(we) begin // note: we should have a for statement to support any bus width
3751 65 unneback 
        if(be[3]) ram[adr[addr_width-2:0]][3] <= d[31:24];
3752 
        if(be[2]) ram[adr[addr_width-2:0]][2] <= d[23:16];
3753 
        if(be[1]) ram[adr[addr_width-2:0]][1] <= d[15:8];
3754 
        if(be[0]) ram[adr[addr_width-2:0]][0] <= d[7:0];
3755 60 unneback 
    end
3756 65 unneback 
    q <= ram[adr];
3757 60 unneback 
end
3758 
 
3759 
`else
3760 
 
3761 7 unneback 
   genvar i;
3762 
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
3763 
      always @ (posedge clk)
3764 
      if (we & be[i])
3765 
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
3766 
   end
3767 
   endgenerate
3768 
 
3769 
   always @ (posedge clk)
3770 
      q <= ram[adr];
3771 
 
3772 60 unneback 
`endif
3773 
 
3774 7 unneback 
endmodule
3775 40 unneback 
`endif
3776 7 unneback 
 
3777 6 unneback 
`ifdef ACTEL
3778 48 unneback 
        // ACTEL FPGA should not use logic to handle rw collision
3779 6 unneback 
        `define SYN /*synthesis syn_ramstyle = "no_rw_check"*/
3780 
`else
3781 
        `define SYN
3782 
`endif
3783 
 
3784 40 unneback 
`ifdef DPRAM_1R1W
3785 
`define MODULE dpram_1r1w
3786 
module `BASE`MODULE ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
3787 
`undef MODULE
3788 6 unneback 
   parameter data_width = 32;
3789 
   parameter addr_width = 8;
3790 75 unneback 
   parameter mem_size = 1<<addr_width;
3791 6 unneback 
   input [(data_width-1):0]      d_a;
3792 
   input [(addr_width-1):0]       adr_a;
3793 
   input [(addr_width-1):0]       adr_b;
3794 
   input                         we_a;
3795 
   output [(data_width-1):0]      q_b;
3796 
   input                         clk_a, clk_b;
3797 
   reg [(addr_width-1):0]         adr_b_reg;
3798 75 unneback 
   reg [data_width-1:0] ram [mem_szie-1:0] `SYN;
3799 7 unneback 
 
3800 
   parameter init = 0;
3801 
   parameter memory_file = "vl_ram.vmem";
3802 
   generate if (init) begin : init_mem
3803 
   initial
3804 
     begin
3805 
        $readmemh(memory_file, ram);
3806 
     end
3807 
   end
3808 
   endgenerate
3809 
 
3810 6 unneback 
   always @ (posedge clk_a)
3811 
   if (we_a)
3812 
     ram[adr_a] <= d_a;
3813 
   always @ (posedge clk_b)
3814 
   adr_b_reg <= adr_b;
3815 
   assign q_b = ram[adr_b_reg];
3816 40 unneback 
 
3817 6 unneback 
endmodule
3818 40 unneback 
`endif
3819 6 unneback 
 
3820 40 unneback 
`ifdef DPRAM_2R1W
3821 
`define MODULE dpram_2r1w
3822 
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
3823 
`undef MODULE
3824 
 
3825 6 unneback 
   parameter data_width = 32;
3826 
   parameter addr_width = 8;
3827 75 unneback 
   parameter mem_size = 1<<addr_width;
3828 6 unneback 
   input [(data_width-1):0]      d_a;
3829 
   input [(addr_width-1):0]       adr_a;
3830 
   input [(addr_width-1):0]       adr_b;
3831 
   input                         we_a;
3832 
   output [(data_width-1):0]      q_b;
3833 
   output reg [(data_width-1):0] q_a;
3834 
   input                         clk_a, clk_b;
3835 
   reg [(data_width-1):0]         q_b;
3836 75 unneback 
   reg [data_width-1:0] ram [mem_szie-1:0] `SYN;
3837 7 unneback 
 
3838 
   parameter init = 0;
3839 
   parameter memory_file = "vl_ram.vmem";
3840 
   generate if (init) begin : init_mem
3841 
   initial
3842 
     begin
3843 
        $readmemh(memory_file, ram);
3844 
     end
3845 
   end
3846 
   endgenerate
3847 
 
3848 6 unneback 
   always @ (posedge clk_a)
3849 
     begin
3850 
        q_a <= ram[adr_a];
3851 
        if (we_a)
3852 
             ram[adr_a] <= d_a;
3853 
     end
3854 
   always @ (posedge clk_b)
3855 
          q_b <= ram[adr_b];
3856 
endmodule
3857 40 unneback 
`endif
3858 6 unneback 
 
3859 40 unneback 
`ifdef DPRAM_2R2W
3860 
`define MODULE dpram_2r2w
3861 
module `BASE`MODULE ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
3862 
`undef MODULE
3863 
 
3864 6 unneback 
   parameter data_width = 32;
3865 
   parameter addr_width = 8;
3866 75 unneback 
   parameter mem_size = 1<<addr_width;
3867 6 unneback 
   input [(data_width-1):0]      d_a;
3868 
   input [(addr_width-1):0]       adr_a;
3869 
   input [(addr_width-1):0]       adr_b;
3870 
   input                         we_a;
3871 
   output [(data_width-1):0]      q_b;
3872 
   input [(data_width-1):0]       d_b;
3873 
   output reg [(data_width-1):0] q_a;
3874 
   input                         we_b;
3875 
   input                         clk_a, clk_b;
3876 
   reg [(data_width-1):0]         q_b;
3877 75 unneback 
   reg [data_width-1:0] ram [mem_size-1:0] `SYN;
3878 7 unneback 
 
3879 
   parameter init = 0;
3880 
   parameter memory_file = "vl_ram.vmem";
3881 
   generate if (init) begin : init_mem
3882 
   initial
3883 
     begin
3884 
        $readmemh(memory_file, ram);
3885 
     end
3886 
   end
3887 
   endgenerate
3888 
 
3889 6 unneback 
   always @ (posedge clk_a)
3890 
     begin
3891 
        q_a <= ram[adr_a];
3892 
        if (we_a)
3893 
             ram[adr_a] <= d_a;
3894 
     end
3895 
   always @ (posedge clk_b)
3896 
     begin
3897 
        q_b <= ram[adr_b];
3898 
        if (we_b)
3899 
          ram[adr_b] <= d_b;
3900 
     end
3901 
endmodule
3902 40 unneback 
`endif
3903 6 unneback 
 
3904 75 unneback 
`ifdef DPRAM_BE_2R2W
3905 
`define MODULE dpram_be_2r2w
3906 
module `BASE`MODULE ( d_a, q_a, adr_a, be_a, we_a, clk_a, d_b, q_b, adr_b, be_b, we_b, clk_b );
3907 
`undef MODULE
3908 
 
3909 
   parameter a_data_width = 32;
3910 
   parameter a_addr_width = 8;
3911 
   parameter b_data_width = 64;
3912 
   parameter b_addr_width = 7;
3913 
   //parameter mem_size = (a_addr_width>b_addr_width) ? (1<<a_addr_width) : (1<<b_addr_width);
3914 
   parameter mem_size = 1024;
3915 
   input [(a_data_width-1):0]      d_a;
3916 
   input [(a_addr_width-1):0]     adr_a;
3917 
   input [(b_addr_width-1):0]     adr_b;
3918 
   input [(a_data_width/4-1):0]    be_a;
3919 
   input                         we_a;
3920 
   output [(b_data_width-1):0]    q_b;
3921 
   input [(b_data_width-1):0]     d_b;
3922 
   output reg [(a_data_width-1):0] q_a;
3923 
   input [(b_data_width/4-1):0]    be_b;
3924 
   input                         we_b;
3925 
   input                         clk_a, clk_b;
3926 
   reg [(b_data_width-1):0]       q_b;
3927 
 
3928 
generate
3929 
if (a_data_width==32 & b_data_width==64) begin : inst32to64
3930 
 
3931 77 unneback 
    wire [63:0] tmp;
3932 75 unneback 
    `define MODULE dpram_2r2w
3933 
    `BASE`MODULE
3934 
    # (.data_width(8), .addr_width(b_addr_width-3))
3935 
    ram0 (
3936 
        .d_a(d_a[7:0]),
3937 
        .q_a(tmp[7:0]),
3938 
        .adr_a(adr_a[a_addr_width-3-1:0]),
3939 
        .we_a(we_a & be_a[0] & !adr_a[0]),
3940 
        .clk_a(clk_a),
3941 
        .d_b(d_b[7:0]),
3942 
        .q_b(q_b[7:0]),
3943 
        .adr_b(adr_b[b_addr_width-3-1:0]),
3944 
        .we_b(we_b),
3945 
        .clk_b(clk_b) );
3946 
    `BASE`MODULE
3947 
    # (.data_width(8), .addr_width(b_addr_width-3))
3948 
    ram1 (
3949 
        .d_a(d_a[7:0]),
3950 
        .q_a(tmp[7:0]),
3951 
        .adr_a(adr_a[a_addr_width-3-1:0]),
3952 
        .we_a(we_a),
3953 
        .clk_a(clk_a),
3954 
        .d_b(d_b[7:0]),
3955 
        .q_b(q_b[7:0]),
3956 
        .adr_b(adr_b[b_addr_width-3-1:0]),
3957 
        .we_b(we_b),
3958 
        .clk_b(clk_b) );
3959 
    `BASE`MODULE
3960 
    # (.data_width(8), .addr_width(b_addr_width-3))
3961 
    ram2 (
3962 
        .d_a(d_a[15:8]),
3963 
        .q_a(tmp[7:0]),
3964 
        .adr_a(adr_a[a_addr_width-3-1:0]),
3965 
        .we_a(we_a),
3966 
        .clk_a(clk_a),
3967 
        .d_b(d_b[7:0]),
3968 
        .q_b(q_b[7:0]),
3969 
        .adr_b(adr_b[b_addr_width-3-1:0]),
3970 
        .we_b(we_b),
3971 
        .clk_b(clk_b) );
3972 
    `BASE`MODULE
3973 
    # (.data_width(8), .addr_width(b_addr_width-3))
3974 
    ram3 (
3975 
        .d_a(d_a[15:8]),
3976 
        .q_a(tmp[7:0]),
3977 
        .adr_a(adr_a[a_addr_width-3-1:0]),
3978 
        .we_a(we_a),
3979 
        .clk_a(clk_a),
3980 
        .d_b(d_b[7:0]),
3981 
        .q_b(q_b[7:0]),
3982 
        .adr_b(adr_b[b_addr_width-3-1:0]),
3983 
        .we_b(we_b),
3984 
        .clk_b(clk_b) );
3985 
    `BASE`MODULE
3986 
    # (.data_width(8), .addr_width(b_addr_width-3))
3987 
    ram4 (
3988 
        .d_a(d_a[23:16]),
3989 
        .q_a(tmp[7:0]),
3990 
        .adr_a(adr_a[a_addr_width-3-1:0]),
3991 
        .we_a(we_a),
3992 
        .clk_a(clk_a),
3993 
        .d_b(d_b[7:0]),
3994 
        .q_b(q_b[7:0]),
3995 
        .adr_b(adr_b[b_addr_width-3-1:0]),
3996 
        .we_b(we_b),
3997 
        .clk_b(clk_b) );
3998 
    `BASE`MODULE
3999 
    # (.data_width(8), .addr_width(b_addr_width-3))
4000 
    ram5 (
4001 
        .d_a(d_a[23:16]),
4002 
        .q_a(tmp[7:0]),
4003 
        .adr_a(adr_a[a_addr_width-3-1:0]),
4004 
        .we_a(we_a),
4005 
        .clk_a(clk_a),
4006 
        .d_b(d_b[7:0]),
4007 
        .q_b(q_b[7:0]),
4008 
        .adr_b(adr_b[b_addr_width-3-1:0]),
4009 
        .we_b(we_b),
4010 
        .clk_b(clk_b) );
4011 
    `BASE`MODULE
4012 
    # (.data_width(8), .addr_width(b_addr_width-3))
4013 
    ram6 (
4014 
        .d_a(d_a[31:24]),
4015 
        .q_a(tmp[7:0]),
4016 
        .adr_a(adr_a[a_addr_width-3-1:0]),
4017 
        .we_a(we_a),
4018 
        .clk_a(clk_a),
4019 
        .d_b(d_b[7:0]),
4020 
        .q_b(q_b[7:0]),
4021 
        .adr_b(adr_b[b_addr_width-3-1:0]),
4022 
        .we_b(we_b),
4023 
        .clk_b(clk_b) );
4024 
    `BASE`MODULE
4025 
    # (.data_width(8), .addr_width(b_addr_width-3))
4026 
    ram7 (
4027 
        .d_a(d_a[31:24]),
4028 
        .q_a(tmp[7:0]),
4029 
        .adr_a(adr_a[a_addr_width-3-1:0]),
4030 
        .we_a(we_a),
4031 
        .clk_a(clk_a),
4032 
        .d_b(d_b[7:0]),
4033 
        .q_b(q_b[7:0]),
4034 
        .adr_b(adr_b[b_addr_width-3-1:0]),
4035 
        .we_b(we_b),
4036 
        .clk_b(clk_b) );
4037 
`undef MODULE
4038 
/*
4039 
   reg [7:0] ram0 [mem_size/8-1:0];
4040 
   wire [7:0] wea, web;
4041 
   assign wea = we_a & be_a[0];
4042 
   assign web = we_b & be_b[0];
4043 
   always @ (posedge clk_a)
4044 
    if (wea)
4045 
        ram0[adr_a] <= d_a[7:0];
4046 
    always @ (posedge clk_a)
4047 
        q_a[7:0] <= ram0[adr_a];
4048 
   always @ (posedge clk_a)
4049 
    if (web)
4050 
        ram0[adr_b] <= d_b[7:0];
4051 
    always @ (posedge clk_b)
4052 
        q_b[7:0] <= ram0[adr_b];
4053 
*/
4054 
end
4055 
endgenerate
4056 
/*
4057 
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_rama
4058 
      always @ (posedge clk_a)
4059 
      if (we_a & be_a[i])
4060 
        ram[adr_a][(i+1)*8-1:i*8] <= d_a[(i+1)*8-1:i*8];
4061 
   end
4062 
   endgenerate
4063 
 
4064 
   always @ (posedge clk_a)
4065 
      q_a <= ram[adr_a];
4066 
 
4067 
   genvar i;
4068 
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ramb
4069 
      always @ (posedge clk_a)
4070 
      if (we_b & be_b[i])
4071 
        ram[adr_b][(i+1)*8-1:i*8] <= d_b[(i+1)*8-1:i*8];
4072 
   end
4073 
   endgenerate
4074 
 
4075 
   always @ (posedge clk_b)
4076 
      q_b <= ram[adr_b];
4077 
*/
4078 
/*
4079 
   always @ (posedge clk_a)
4080 
     begin
4081 
        q_a <= ram[adr_a];
4082 
        if (we_a)
4083 
             ram[adr_a] <= d_a;
4084 
     end
4085 
   always @ (posedge clk_b)
4086 
     begin
4087 
        q_b <= ram[adr_b];
4088 
        if (we_b)
4089 
          ram[adr_b] <= d_b;
4090 
     end
4091 
*/
4092 
endmodule
4093 
`endif
4094 
 
4095 6 unneback 
// Content addresable memory, CAM
4096 
 
4097 40 unneback 
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
4098 6 unneback 
// FIFO
4099 40 unneback 
`define MODULE fifo_1r1w_fill_level_sync
4100 
module `BASE`MODULE (
4101 
`undef MODULE
4102 25 unneback 
    d, wr, fifo_full,
4103 
    q, rd, fifo_empty,
4104 
    fill_level,
4105 
    clk, rst
4106 
    );
4107 
 
4108 
parameter data_width = 18;
4109 
parameter addr_width = 4;
4110 6 unneback 
 
4111 25 unneback 
// write side
4112 
input  [data_width-1:0] d;
4113 
input                   wr;
4114 
output                  fifo_full;
4115 
// read side
4116 
output [data_width-1:0] q;
4117 
input                   rd;
4118 
output                  fifo_empty;
4119 
// common
4120 
output [addr_width:0]   fill_level;
4121 
input rst, clk;
4122 
 
4123 
wire [addr_width:1] wadr, radr;
4124 
 
4125 40 unneback 
`define MODULE cnt_bin_ce
4126 
`BASE`MODULE
4127 25 unneback 
    # ( .length(addr_width))
4128 
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
4129 40 unneback 
`BASE`MODULE
4130 25 unneback 
    # (.length(addr_width))
4131 
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
4132 40 unneback 
`undef MODULE
4133 25 unneback 
 
4134 40 unneback 
`define MODULE dpram_1r1w
4135 
`BASE`MODULE
4136 25 unneback 
    # (.data_width(data_width), .addr_width(addr_width))
4137 
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
4138 40 unneback 
`undef MODULE
4139 25 unneback 
 
4140 40 unneback 
`define MODULE cnt_bin_ce_rew_q_zq_l1
4141 
`BASE`MODULE
4142 27 unneback 
    # (.length(addr_width+1), .level1_value(1<<addr_width))
4143 25 unneback 
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
4144 40 unneback 
`undef MODULE
4145 25 unneback 
endmodule
4146 40 unneback 
`endif
4147 25 unneback 
 
4148 40 unneback 
`ifdef FIFO_2R2W_SYNC_SIMPLEX
4149 27 unneback 
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
4150 
// RAM is supposed to be larger than the two FIFOs
4151 
// LFSR counters used adr pointers
4152 40 unneback 
`define MODULE fifo_2r2w_sync_simplex
4153 
module `BASE`MODULE (
4154 
`undef MODULE
4155 27 unneback 
    // a side
4156 
    a_d, a_wr, a_fifo_full,
4157 
    a_q, a_rd, a_fifo_empty,
4158 
    a_fill_level,
4159 
    // b side
4160 
    b_d, b_wr, b_fifo_full,
4161 
    b_q, b_rd, b_fifo_empty,
4162 
    b_fill_level,
4163 
    // common
4164 
    clk, rst
4165 
    );
4166 
parameter data_width = 8;
4167 
parameter addr_width = 5;
4168 
parameter fifo_full_level = (1<<addr_width)-1;
4169 
 
4170 
// a side
4171 
input  [data_width-1:0] a_d;
4172 
input                   a_wr;
4173 
output                  a_fifo_full;
4174 
output [data_width-1:0] a_q;
4175 
input                   a_rd;
4176 
output                  a_fifo_empty;
4177 
output [addr_width-1:0] a_fill_level;
4178 
 
4179 
// b side
4180 
input  [data_width-1:0] b_d;
4181 
input                   b_wr;
4182 
output                  b_fifo_full;
4183 
output [data_width-1:0] b_q;
4184 
input                   b_rd;
4185 
output                  b_fifo_empty;
4186 
output [addr_width-1:0] b_fill_level;
4187 
 
4188 
input                   clk;
4189 
input                   rst;
4190 
 
4191 
// adr_gen
4192 
wire [addr_width:1] a_wadr, a_radr;
4193 
wire [addr_width:1] b_wadr, b_radr;
4194 
// dpram
4195 
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
4196 
 
4197 40 unneback 
`define MODULE cnt_lfsr_ce
4198 
`BASE`MODULE
4199 27 unneback 
    # ( .length(addr_width))
4200 
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
4201 
 
4202 40 unneback 
`BASE`MODULE
4203 27 unneback 
    # (.length(addr_width))
4204 
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
4205 
 
4206 40 unneback 
`BASE`MODULE
4207 27 unneback 
    # ( .length(addr_width))
4208 
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
4209 
 
4210 40 unneback 
`BASE`MODULE
4211 27 unneback 
    # (.length(addr_width))
4212 
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
4213 40 unneback 
`undef MODULE
4214 27 unneback 
 
4215 
// mux read or write adr to DPRAM
4216 
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
4217 
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
4218 
 
4219 40 unneback 
`define MODULE dpram_2r2w
4220 
`BASE`MODULE
4221 27 unneback 
    # (.data_width(data_width), .addr_width(addr_width+1))
4222 
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
4223 
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
4224 40 unneback 
`undef MODULE
4225 
 
4226 
`define MODULE cnt_bin_ce_rew_zq_l1
4227 
`BASE`MODULE
4228 28 unneback 
    # (.length(addr_width), .level1_value(fifo_full_level))
4229 27 unneback 
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
4230 
 
4231 40 unneback 
`BASE`MODULE
4232 28 unneback 
    # (.length(addr_width), .level1_value(fifo_full_level))
4233 27 unneback 
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
4234 40 unneback 
`undef MODULE
4235 27 unneback 
 
4236 
endmodule
4237 40 unneback 
`endif
4238 27 unneback 
 
4239 40 unneback 
`ifdef FIFO_CMP_ASYNC
4240 
`define MODULE fifo_cmp_async
4241 
module `BASE`MODULE ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
4242 
`undef MODULE
4243 6 unneback 
 
4244 11 unneback 
   parameter addr_width = 4;
4245 
   parameter N = addr_width-1;
4246 6 unneback 
 
4247 
   parameter Q1 = 2'b00;
4248 
   parameter Q2 = 2'b01;
4249 
   parameter Q3 = 2'b11;
4250 
   parameter Q4 = 2'b10;
4251 
 
4252 
   parameter going_empty = 1'b0;
4253 
   parameter going_full  = 1'b1;
4254 
 
4255 
   input [N:0]  wptr, rptr;
4256 14 unneback 
   output       fifo_empty;
4257 6 unneback 
   output       fifo_full;
4258 
   input        wclk, rclk, rst;
4259 
 
4260 
`ifndef GENERATE_DIRECTION_AS_LATCH
4261 
   wire direction;
4262 
`endif
4263 
`ifdef GENERATE_DIRECTION_AS_LATCH
4264 
   reg direction;
4265 
`endif
4266 
   reg  direction_set, direction_clr;
4267 
 
4268 
   wire async_empty, async_full;
4269 
   wire fifo_full2;
4270 14 unneback 
   wire fifo_empty2;
4271 6 unneback 
 
4272 
   // direction_set
4273 
   always @ (wptr[N:N-1] or rptr[N:N-1])
4274 
     case ({wptr[N:N-1],rptr[N:N-1]})
4275 
       {Q1,Q2} : direction_set <= 1'b1;
4276 
       {Q2,Q3} : direction_set <= 1'b1;
4277 
       {Q3,Q4} : direction_set <= 1'b1;
4278 
       {Q4,Q1} : direction_set <= 1'b1;
4279 
       default : direction_set <= 1'b0;
4280 
     endcase
4281 
 
4282 
   // direction_clear
4283 
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
4284 
     if (rst)
4285 
       direction_clr <= 1'b1;
4286 
     else
4287 
       case ({wptr[N:N-1],rptr[N:N-1]})
4288 
         {Q2,Q1} : direction_clr <= 1'b1;
4289 
         {Q3,Q2} : direction_clr <= 1'b1;
4290 
         {Q4,Q3} : direction_clr <= 1'b1;
4291 
         {Q1,Q4} : direction_clr <= 1'b1;
4292 
         default : direction_clr <= 1'b0;
4293 
       endcase
4294 
 
4295 40 unneback 
`define MODULE dff_sr
4296 6 unneback 
`ifndef GENERATE_DIRECTION_AS_LATCH
4297 40 unneback 
    `BASE`MODULE dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
4298 6 unneback 
`endif
4299 
 
4300 
`ifdef GENERATE_DIRECTION_AS_LATCH
4301 
   always @ (posedge direction_set or posedge direction_clr)
4302 
     if (direction_clr)
4303 
       direction <= going_empty;
4304 
     else
4305 
       direction <= going_full;
4306 
`endif
4307 
 
4308 
   assign async_empty = (wptr == rptr) && (direction==going_empty);
4309 
   assign async_full  = (wptr == rptr) && (direction==going_full);
4310 
 
4311 40 unneback 
    `BASE`MODULE dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
4312 
    `BASE`MODULE dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
4313 
`undef MODULE
4314 6 unneback 
 
4315 
/*
4316 
   always @ (posedge wclk or posedge rst or posedge async_full)
4317 
     if (rst)
4318 
       {fifo_full, fifo_full2} <= 2'b00;
4319 
     else if (async_full)
4320 
       {fifo_full, fifo_full2} <= 2'b11;
4321 
     else
4322 
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
4323 
*/
4324 14 unneback 
/*   always @ (posedge rclk or posedge async_empty)
4325 6 unneback 
     if (async_empty)
4326 
       {fifo_empty, fifo_empty2} <= 2'b11;
4327 
     else
4328 14 unneback 
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
4329 40 unneback 
`define MODULE dff
4330 
    `BASE`MODULE # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
4331 
    `BASE`MODULE # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
4332 
`undef MODULE
4333 27 unneback 
endmodule // async_compb
4334 40 unneback 
`endif
4335 6 unneback 
 
4336 40 unneback 
`ifdef FIFO_1R1W_ASYNC
4337 
`define MODULE fifo_1r1w_async
4338 
module `BASE`MODULE (
4339 
`undef MODULE
4340 6 unneback 
    d, wr, fifo_full, wr_clk, wr_rst,
4341 
    q, rd, fifo_empty, rd_clk, rd_rst
4342 
    );
4343 
 
4344 
parameter data_width = 18;
4345 
parameter addr_width = 4;
4346 
 
4347 
// write side
4348 
input  [data_width-1:0] d;
4349 
input                   wr;
4350 
output                  fifo_full;
4351 
input                   wr_clk;
4352 
input                   wr_rst;
4353 
// read side
4354 
output [data_width-1:0] q;
4355 
input                   rd;
4356 
output                  fifo_empty;
4357 
input                   rd_clk;
4358 
input                   rd_rst;
4359 
 
4360 
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
4361 23 unneback 
 
4362 40 unneback 
`define MODULE cnt_gray_ce_bin
4363 
`BASE`MODULE
4364 6 unneback 
    # ( .length(addr_width))
4365 
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
4366 
 
4367 40 unneback 
`BASE`MODULE
4368 6 unneback 
    # (.length(addr_width))
4369 23 unneback 
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
4370 40 unneback 
`undef MODULE
4371 6 unneback 
 
4372 40 unneback 
`define MODULE dpram_1r1w
4373 
`BASE`MODULE
4374 6 unneback 
    # (.data_width(data_width), .addr_width(addr_width))
4375 
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
4376 40 unneback 
`undef MODULE
4377 6 unneback 
 
4378 40 unneback 
`define MODULE fifo_cmp_async
4379 
`BASE`MODULE
4380 6 unneback 
    # (.addr_width(addr_width))
4381 
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
4382 40 unneback 
`undef MODULE
4383 6 unneback 
 
4384 
endmodule
4385 40 unneback 
`endif
4386 6 unneback 
 
4387 40 unneback 
`ifdef FIFO_2R2W_ASYNC
4388 
`define MODULE fifo_2r2w_async
4389 
module `BASE`MODULE (
4390 
`undef MODULE
4391 6 unneback 
    // a side
4392 
    a_d, a_wr, a_fifo_full,
4393 
    a_q, a_rd, a_fifo_empty,
4394 
    a_clk, a_rst,
4395 
    // b side
4396 
    b_d, b_wr, b_fifo_full,
4397 
    b_q, b_rd, b_fifo_empty,
4398 
    b_clk, b_rst
4399 
    );
4400 
 
4401 
parameter data_width = 18;
4402 
parameter addr_width = 4;
4403 
 
4404 
// a side
4405 
input  [data_width-1:0] a_d;
4406 
input                   a_wr;
4407 
output                  a_fifo_full;
4408 
output [data_width-1:0] a_q;
4409 
input                   a_rd;
4410 
output                  a_fifo_empty;
4411 
input                   a_clk;
4412 
input                   a_rst;
4413 
 
4414 
// b side
4415 
input  [data_width-1:0] b_d;
4416 
input                   b_wr;
4417 
output                  b_fifo_full;
4418 
output [data_width-1:0] b_q;
4419 
input                   b_rd;
4420 
output                  b_fifo_empty;
4421 
input                   b_clk;
4422 
input                   b_rst;
4423 
 
4424 40 unneback 
`define MODULE fifo_1r1w_async
4425 
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
4426 6 unneback 
vl_fifo_1r1w_async_a (
4427 
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
4428 
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
4429 
    );
4430 
 
4431 40 unneback 
`BASE`MODULE # (.data_width(data_width), .addr_width(addr_width))
4432 6 unneback 
vl_fifo_1r1w_async_b (
4433 
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
4434 
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
4435 
    );
4436 40 unneback 
`undef MODULE
4437 
 
4438 6 unneback 
endmodule
4439 40 unneback 
`endif
4440 6 unneback 
 
4441 40 unneback 
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
4442 
`define MODULE fifo_2r2w_async_simplex
4443 
module `BASE`MODULE (
4444 
`undef MODULE
4445 6 unneback 
    // a side
4446 
    a_d, a_wr, a_fifo_full,
4447 
    a_q, a_rd, a_fifo_empty,
4448 
    a_clk, a_rst,
4449 
    // b side
4450 
    b_d, b_wr, b_fifo_full,
4451 
    b_q, b_rd, b_fifo_empty,
4452 
    b_clk, b_rst
4453 
    );
4454 
 
4455 
parameter data_width = 18;
4456 
parameter addr_width = 4;
4457 
 
4458 
// a side
4459 
input  [data_width-1:0] a_d;
4460 
input                   a_wr;
4461 
output                  a_fifo_full;
4462 
output [data_width-1:0] a_q;
4463 
input                   a_rd;
4464 
output                  a_fifo_empty;
4465 
input                   a_clk;
4466 
input                   a_rst;
4467 
 
4468 
// b side
4469 
input  [data_width-1:0] b_d;
4470 
input                   b_wr;
4471 
output                  b_fifo_full;
4472 
output [data_width-1:0] b_q;
4473 
input                   b_rd;
4474 
output                  b_fifo_empty;
4475 
input                   b_clk;
4476 
input                   b_rst;
4477 
 
4478 
// adr_gen
4479 
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
4480 
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
4481 
// dpram
4482 
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
4483 
 
4484 40 unneback 
`define MODULE cnt_gray_ce_bin
4485 
`BASE`MODULE
4486 6 unneback 
    # ( .length(addr_width))
4487 
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
4488 
 
4489 40 unneback 
`BASE`MODULE
4490 6 unneback 
    # (.length(addr_width))
4491 
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
4492 
 
4493 40 unneback 
`BASE`MODULE
4494 6 unneback 
    # ( .length(addr_width))
4495 
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
4496 
 
4497 40 unneback 
`BASE`MODULE
4498 6 unneback 
    # (.length(addr_width))
4499 
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
4500 40 unneback 
`undef MODULE
4501 6 unneback 
 
4502 
// mux read or write adr to DPRAM
4503 
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
4504 
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
4505 
 
4506 40 unneback 
`define MODULE dpram_2r2w
4507 
`BASE`MODULE
4508 6 unneback 
    # (.data_width(data_width), .addr_width(addr_width+1))
4509 
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
4510 
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
4511 40 unneback 
`undef MODULE
4512 6 unneback 
 
4513 40 unneback 
`define MODULE fifo_cmp_async
4514 
`BASE`MODULE
4515 6 unneback 
    # (.addr_width(addr_width))
4516 
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
4517 
 
4518 40 unneback 
`BASE`MODULE
4519 6 unneback 
    # (.addr_width(addr_width))
4520 
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
4521 40 unneback 
`undef MODULE
4522 6 unneback 
 
4523 
endmodule
4524 40 unneback 
`endif
4525 48 unneback 
 
4526 
`ifdef REG_FILE
4527 
`define MODULE reg_file
4528 
module `BASE`MODULE (
4529 
`undef MODULE
4530 
    a1, a2, a3, wd3, we3, rd1, rd2, clk
4531 
);
4532 
parameter data_width = 32;
4533 
parameter addr_width = 5;
4534 
input [addr_width-1:0] a1, a2, a3;
4535 
input [data_width-1:0] wd3;
4536 
input we3;
4537 
output [data_width-1:0] rd1, rd2;
4538 
input clk;
4539 
 
4540 
`ifdef ACTEL
4541 
reg [data_width-1:0] wd3_reg;
4542 
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
4543 
reg we3_reg;
4544 
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] `SYN;
4545 
reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] `SYN;
4546 
always @ (posedge clk or posedge rst)
4547 
if (rst)
4548 
    {wd3_reg, a3_reg, we3_reg} <= {(data_width+addr_width+1){1'b0}};
4549 
else
4550 
    {wd3_reg, a3_reg, we3_reg} <= {wd3,a3,wd3};
4551 
 
4552 
    always @ (negedge clk)
4553 
    if (we3_reg)
4554 
        ram1[a3_reg] <= wd3;
4555 
    always @ (posedge clk)
4556 
        a1_reg <= a1;
4557 
    assign rd1 = ram1[a1_reg];
4558 
 
4559 
    always @ (negedge clk)
4560 
    if (we3_reg)
4561 
        ram2[a3_reg] <= wd3;
4562 
    always @ (posedge clk)
4563 
        a2_reg <= a2;
4564 
    assign rd2 = ram2[a2_reg];
4565 
 
4566 
`else
4567 
 
4568 
`define MODULE dpram_1r1w
4569 
`BASE`MODULE
4570 
    # ( .data_width(data_width), .addr_width(addr_width))
4571 
    ram1 (
4572 
        .d_a(wd3),
4573 
        .adr_a(a3),
4574 
        .we_a(we3),
4575 
        .clk_a(clk),
4576 
        .q_b(rd1),
4577 
        .adr_b(a1),
4578 
        .clk_b(clk) );
4579 
 
4580 
`BASE`MODULE
4581 
    # ( .data_width(data_width), .addr_width(addr_width))
4582 
    ram2 (
4583 
        .d_a(wd3),
4584 
        .adr_a(a3),
4585 
        .we_a(we3),
4586 
        .clk_a(clk),
4587 
        .q_b(rd2),
4588 
        .adr_b(a2),
4589 
        .clk_b(clk) );
4590 
`undef MODULE
4591 
 
4592 
`endif
4593 
 
4594 
endmodule
4595 
`endif
4596 12 unneback 
//////////////////////////////////////////////////////////////////////
4597 
////                                                              ////
4598 
////  Versatile library, wishbone stuff                           ////
4599 
////                                                              ////
4600 
////  Description                                                 ////
4601 
////  Wishbone compliant modules                                  ////
4602 
////                                                              ////
4603 
////                                                              ////
4604 
////  To Do:                                                      ////
4605 
////   -                                                          ////
4606 
////                                                              ////
4607 
////  Author(s):                                                  ////
4608 
////      - Michael Unneback, unneback@opencores.org              ////
4609 
////        ORSoC AB                                              ////
4610 
////                                                              ////
4611 
//////////////////////////////////////////////////////////////////////
4612 
////                                                              ////
4613 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
4614 
////                                                              ////
4615 
//// This source file may be used and distributed without         ////
4616 
//// restriction provided that this copyright statement is not    ////
4617 
//// removed from the file and that any derivative work contains  ////
4618 
//// the original copyright notice and the associated disclaimer. ////
4619 
////                                                              ////
4620 
//// This source file is free software; you can redistribute it   ////
4621 
//// and/or modify it under the terms of the GNU Lesser General   ////
4622 
//// Public License as published by the Free Software Foundation; ////
4623 
//// either version 2.1 of the License, or (at your option) any   ////
4624 
//// later version.                                               ////
4625 
////                                                              ////
4626 
//// This source is distributed in the hope that it will be       ////
4627 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
4628 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
4629 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
4630 
//// details.                                                     ////
4631 
////                                                              ////
4632 
//// You should have received a copy of the GNU Lesser General    ////
4633 
//// Public License along with this source; if not, download it   ////
4634 
//// from http://www.opencores.org/lgpl.shtml                     ////
4635 
////                                                              ////
4636 
//////////////////////////////////////////////////////////////////////
4637 
 
4638 75 unneback 
`ifdef WB_ADR_INC
4639 
// async wb3 - wb3 bridge
4640 
`timescale 1ns/1ns
4641 
`define MODULE wb_adr_inc
4642 
module `BASE`MODULE (
4643 
`undef MODULE
4644 
 
4645 
    always @ (posedge clk or posedge rst)
4646 
        if (rst)
4647 
           col_reg <= {col_reg_width{1'b0}};
4648 
        else
4649 
            case (state)
4650 
            `FSM_IDLE:
4651 
               col_reg <= col[col_reg_width-1:0];
4652 
            `FSM_RW:
4653 
               if (~stall)
4654 
                  case (bte_i)
4655 
`ifdef SDR_BEAT4
4656 
                        beat4:  col_reg[2:0] <= col_reg[2:0] + 3'd1;
4657 
`endif
4658 
`ifdef SDR_BEAT8
4659 
                        beat8:  col_reg[3:0] <= col_reg[3:0] + 4'd1;
4660 
`endif
4661 
`ifdef SDR_BEAT16
4662 
                        beat16: col_reg[4:0] <= col_reg[4:0] + 5'd1;
4663 
`endif
4664 
                  endcase
4665 
            endcase
4666 
`endif
4667 
 
4668 40 unneback 
`ifdef WB3WB3_BRIDGE
4669 12 unneback 
// async wb3 - wb3 bridge
4670 
`timescale 1ns/1ns
4671 40 unneback 
`define MODULE wb3wb3_bridge
4672 
module `BASE`MODULE (
4673 
`undef MODULE
4674 12 unneback 
        // wishbone slave side
4675 
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
4676 
        // wishbone master side
4677 
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
4678 
 
4679 
input [31:0] wbs_dat_i;
4680 
input [31:2] wbs_adr_i;
4681 
input [3:0]  wbs_sel_i;
4682 
input [1:0]  wbs_bte_i;
4683 
input [2:0]  wbs_cti_i;
4684 
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
4685 
output [31:0] wbs_dat_o;
4686 14 unneback 
output wbs_ack_o;
4687 12 unneback 
input wbs_clk, wbs_rst;
4688 
 
4689 
output [31:0] wbm_dat_o;
4690 
output reg [31:2] wbm_adr_o;
4691 
output [3:0]  wbm_sel_o;
4692 
output reg [1:0]  wbm_bte_o;
4693 
output reg [2:0]  wbm_cti_o;
4694 14 unneback 
output reg wbm_we_o;
4695 
output wbm_cyc_o;
4696 12 unneback 
output wbm_stb_o;
4697 
input [31:0]  wbm_dat_i;
4698 
input wbm_ack_i;
4699 
input wbm_clk, wbm_rst;
4700 
 
4701 
parameter addr_width = 4;
4702 
 
4703 
// bte
4704 
parameter linear       = 2'b00;
4705 
parameter wrap4        = 2'b01;
4706 
parameter wrap8        = 2'b10;
4707 
parameter wrap16       = 2'b11;
4708 
// cti
4709 
parameter classic      = 3'b000;
4710 
parameter incburst     = 3'b010;
4711 
parameter endofburst   = 3'b111;
4712 
 
4713 
parameter wbs_adr  = 1'b0;
4714 
parameter wbs_data = 1'b1;
4715 
 
4716 33 unneback 
parameter wbm_adr0      = 2'b00;
4717 
parameter wbm_adr1      = 2'b01;
4718 
parameter wbm_data      = 2'b10;
4719 
parameter wbm_data_wait = 2'b11;
4720 12 unneback 
 
4721 
reg [1:0] wbs_bte_reg;
4722 
reg wbs;
4723 
wire wbs_eoc_alert, wbm_eoc_alert;
4724 
reg wbs_eoc, wbm_eoc;
4725 
reg [1:0] wbm;
4726 
 
4727 14 unneback 
wire [1:16] wbs_count, wbm_count;
4728 12 unneback 
 
4729 
wire [35:0] a_d, a_q, b_d, b_q;
4730 
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
4731 
reg a_rd_reg;
4732 
wire b_rd_adr, b_rd_data;
4733 14 unneback 
wire b_rd_data_reg;
4734 
wire [35:0] temp;
4735 12 unneback 
 
4736 
`define WE 5
4737 
`define BTE 4:3
4738 
`define CTI 2:0
4739 
 
4740 
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
4741 
always @ (posedge wbs_clk or posedge wbs_rst)
4742 
if (wbs_rst)
4743 
        wbs_eoc <= 1'b0;
4744 
else
4745 
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
4746 78 unneback 
                wbs_eoc <= (wbs_bte_i==linear) | (wbs_cti_i==3'b111);
4747 12 unneback 
        else if (wbs_eoc_alert & (a_rd | a_wr))
4748 
                wbs_eoc <= 1'b1;
4749 
 
4750 40 unneback 
`define MODULE cnt_shreg_ce_clear
4751 
`BASE`MODULE # ( .length(16))
4752 
`undef MODULE
4753 12 unneback 
    cnt0 (
4754 
        .cke(wbs_ack_o),
4755 
        .clear(wbs_eoc),
4756 
        .q(wbs_count),
4757 
        .rst(wbs_rst),
4758 
        .clk(wbs_clk));
4759 
 
4760 
always @ (posedge wbs_clk or posedge wbs_rst)
4761 
if (wbs_rst)
4762 
        wbs <= wbs_adr;
4763 
else
4764 75 unneback 
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & a_fifo_empty)
4765 12 unneback 
                wbs <= wbs_data;
4766 
        else if (wbs_eoc & wbs_ack_o)
4767 
                wbs <= wbs_adr;
4768 
 
4769 
// wbs FIFO
4770 75 unneback 
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,((wbs_cti_i==3'b111) ? {2'b00,3'b000} : {wbs_bte_i,wbs_cti_i})} : {wbs_dat_i,wbs_sel_i};
4771 
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & a_fifo_empty :
4772 12 unneback 
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
4773 
              1'b0;
4774 
assign a_rd = !a_fifo_empty;
4775 
always @ (posedge wbs_clk or posedge wbs_rst)
4776 
if (wbs_rst)
4777 
        a_rd_reg <= 1'b0;
4778 
else
4779 
        a_rd_reg <= a_rd;
4780 
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
4781 
 
4782 
assign wbs_dat_o = a_q[35:4];
4783 
 
4784 
always @ (posedge wbs_clk or posedge wbs_rst)
4785 
if (wbs_rst)
4786 13 unneback 
        wbs_bte_reg <= 2'b00;
4787 12 unneback 
else
4788 13 unneback 
        wbs_bte_reg <= wbs_bte_i;
4789 12 unneback 
 
4790 
// wbm FIFO
4791 
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
4792 
always @ (posedge wbm_clk or posedge wbm_rst)
4793 
if (wbm_rst)
4794 
        wbm_eoc <= 1'b0;
4795 
else
4796 
        if (wbm==wbm_adr0 & !b_fifo_empty)
4797 
                wbm_eoc <= b_q[`BTE] == linear;
4798 
        else if (wbm_eoc_alert & wbm_ack_i)
4799 
                wbm_eoc <= 1'b1;
4800 
 
4801 
always @ (posedge wbm_clk or posedge wbm_rst)
4802 
if (wbm_rst)
4803 
        wbm <= wbm_adr0;
4804 
else
4805 33 unneback 
/*
4806 12 unneback 
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
4807 
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
4808 
        (wbm==wbm_adr1 & !wbm_we_o) |
4809 
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
4810 
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
4811 33 unneback 
*/
4812 
    case (wbm)
4813 
    wbm_adr0:
4814 
        if (!b_fifo_empty)
4815 
            wbm <= wbm_adr1;
4816 
    wbm_adr1:
4817 
        if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
4818 
            wbm <= wbm_data;
4819 
    wbm_data:
4820 
        if (wbm_ack_i & wbm_eoc)
4821 
            wbm <= wbm_adr0;
4822 
        else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
4823 
            wbm <= wbm_data_wait;
4824 
    wbm_data_wait:
4825 
        if (!b_fifo_empty)
4826 
            wbm <= wbm_data;
4827 
    endcase
4828 12 unneback 
 
4829 
assign b_d = {wbm_dat_i,4'b1111};
4830 
assign b_wr = !wbm_we_o & wbm_ack_i;
4831 
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
4832 
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
4833 
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
4834 33 unneback 
                   (wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
4835 12 unneback 
                   1'b0;
4836 
assign b_rd = b_rd_adr | b_rd_data;
4837 
 
4838 40 unneback 
`define MODULE dff
4839 
`BASE`MODULE dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
4840 
`undef MODULE
4841 
`define MODULE dff_ce
4842 
`BASE`MODULE # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
4843 
`undef MODULE
4844 12 unneback 
 
4845 
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
4846 
 
4847 40 unneback 
`define MODULE cnt_shreg_ce_clear
4848 42 unneback 
`BASE`MODULE # ( .length(16))
4849 40 unneback 
`undef MODULE
4850 12 unneback 
    cnt1 (
4851 
        .cke(wbm_ack_i),
4852 
        .clear(wbm_eoc),
4853 
        .q(wbm_count),
4854 
        .rst(wbm_rst),
4855 
        .clk(wbm_clk));
4856 
 
4857 33 unneback 
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
4858 
assign wbm_stb_o = (wbm==wbm_data);
4859 12 unneback 
 
4860 
always @ (posedge wbm_clk or posedge wbm_rst)
4861 
if (wbm_rst)
4862 
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
4863 
else begin
4864 
        if (wbm==wbm_adr0 & !b_fifo_empty)
4865 
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
4866 
        else if (wbm_eoc_alert & wbm_ack_i)
4867 
                wbm_cti_o <= endofburst;
4868 
end
4869 
 
4870 
//async_fifo_dw_simplex_top
4871 40 unneback 
`define MODULE fifo_2r2w_async_simplex
4872 
`BASE`MODULE
4873 
`undef MODULE
4874 12 unneback 
# ( .data_width(36), .addr_width(addr_width))
4875 
fifo (
4876 
    // a side
4877 
    .a_d(a_d),
4878 
    .a_wr(a_wr),
4879 
    .a_fifo_full(a_fifo_full),
4880 
    .a_q(a_q),
4881 
    .a_rd(a_rd),
4882 
    .a_fifo_empty(a_fifo_empty),
4883 
    .a_clk(wbs_clk),
4884 
    .a_rst(wbs_rst),
4885 
    // b side
4886 
    .b_d(b_d),
4887 
    .b_wr(b_wr),
4888 
    .b_fifo_full(b_fifo_full),
4889 
    .b_q(b_q),
4890 
    .b_rd(b_rd),
4891 
    .b_fifo_empty(b_fifo_empty),
4892 
    .b_clk(wbm_clk),
4893 
    .b_rst(wbm_rst)
4894 
    );
4895 
 
4896 
endmodule
4897 40 unneback 
`undef WE
4898 
`undef BTE
4899 
`undef CTI
4900 
`endif
4901 17 unneback 
 
4902 75 unneback 
`ifdef WB3AVALON_BRIDGE
4903 
`define MODULE wb3avalon_bridge
4904 
module `BASE`MODULE (
4905 
`undef MODULE
4906 
        // wishbone slave side
4907 
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
4908 77 unneback 
        // avalon master side
4909 75 unneback 
        readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst);
4910 
 
4911 
input [31:0] wbs_dat_i;
4912 
input [31:2] wbs_adr_i;
4913 
input [3:0]  wbs_sel_i;
4914 
input [1:0]  wbs_bte_i;
4915 
input [2:0]  wbs_cti_i;
4916 
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
4917 
output [31:0] wbs_dat_o;
4918 
output wbs_ack_o;
4919 
input wbs_clk, wbs_rst;
4920 
 
4921 
input [31:0] readdata;
4922 
output [31:0] writedata;
4923 
output [31:2] address;
4924 
output [3:0]  be;
4925 
output write;
4926 81 unneback 
output read;
4927 75 unneback 
output beginbursttransfer;
4928 
output [3:0] burstcount;
4929 
input readdatavalid;
4930 
input waitrequest;
4931 
input clk;
4932 
input rst;
4933 
 
4934 
wire [1:0] wbm_bte_o;
4935 
wire [2:0] wbm_cti_o;
4936 
wire wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_ack_i;
4937 
reg last_cyc;
4938 79 unneback 
reg [3:0] counter;
4939 75 unneback 
 
4940 
always @ (posedge clk or posedge rst)
4941 
if (rst)
4942 
    last_cyc <= 1'b0;
4943 
else
4944 
    last_cyc <= wbm_cyc_o;
4945 
 
4946 81 unneback 
/*
4947 79 unneback 
always @ (posedge clk or posedge rst)
4948 
if (rst)
4949 
    read <= 1'b0;
4950 
else
4951 80 unneback 
    if (!last_cyc & wbm_cyc_o & !wbm_we_o)
4952 79 unneback 
        read <= 1'b1;
4953 
    else if (!waitrequest)
4954 
        read <= 1'b0;
4955 81 unneback 
*/
4956 
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o & counter!=4'd0;
4957 
 
4958 75 unneback 
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010;
4959 
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 :
4960 
                    (wbm_bte_o==2'b10) ? 4'd8 :
4961 78 unneback 
                    (wbm_bte_o==2'b11) ? 4'd16:
4962 
                    4'd1;
4963 75 unneback 
assign wbm_ack_i = (readdatavalid & !waitrequest) | (write & !waitrequest);
4964 
 
4965 79 unneback 
always @ (posedge clk or posedge rst)
4966 
if (rst) begin
4967 
    counter <= 4'd0;
4968 
end else
4969 80 unneback 
    if (wbm_we_o) begin
4970 
        if (!waitrequest & !last_cyc & wbm_cyc_o) begin
4971 
            counter <= burstcount -1;
4972 
        end else if (waitrequest & !last_cyc & wbm_cyc_o) begin
4973 
            counter <= burstcount;
4974 
        end else if (!waitrequest & wbm_stb_o) begin
4975 
            counter <= counter - 4'd1;
4976 
        end
4977 79 unneback 
    end
4978 81 unneback 
assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o & counter!=4'd0;
4979 79 unneback 
 
4980 75 unneback 
`define MODULE wb3wb3_bridge
4981 77 unneback 
`BASE`MODULE wbwb3inst (
4982 75 unneback 
`undef MODULE
4983 
    // wishbone slave side
4984 
    .wbs_dat_i(wbs_dat_i),
4985 
    .wbs_adr_i(wbs_adr_i),
4986 
    .wbs_sel_i(wbs_sel_i),
4987 
    .wbs_bte_i(wbs_bte_i),
4988 
    .wbs_cti_i(wbs_cti_i),
4989 
    .wbs_we_i(wbs_we_i),
4990 
    .wbs_cyc_i(wbs_cyc_i),
4991 
    .wbs_stb_i(wbs_stb_i),
4992 
    .wbs_dat_o(wbs_dat_o),
4993 
    .wbs_ack_o(wbs_ack_o),
4994 
    .wbs_clk(wbs_clk),
4995 
    .wbs_rst(wbs_rst),
4996 
    // wishbone master side
4997 
    .wbm_dat_o(writedata),
4998 78 unneback 
    .wbm_adr_o(address),
4999 75 unneback 
    .wbm_sel_o(be),
5000 
    .wbm_bte_o(wbm_bte_o),
5001 
    .wbm_cti_o(wbm_cti_o),
5002 
    .wbm_we_o(wbm_we_o),
5003 
    .wbm_cyc_o(wbm_cyc_o),
5004 
    .wbm_stb_o(wbm_stb_o),
5005 
    .wbm_dat_i(readdata),
5006 
    .wbm_ack_i(wbm_ack_i),
5007 
    .wbm_clk(clk),
5008 
    .wbm_rst(rst));
5009 
 
5010 
 
5011 
endmodule
5012 
`endif
5013 
 
5014 40 unneback 
`ifdef WB3_ARBITER_TYPE1
5015 
`define MODULE wb3_arbiter_type1
5016 42 unneback 
module `BASE`MODULE (
5017 40 unneback 
`undef MODULE
5018 39 unneback 
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
5019 
    wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
5020 
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
5021 
    wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
5022 
    wb_clk, wb_rst
5023 
);
5024 
 
5025 
parameter nr_of_ports = 3;
5026 
parameter adr_size = 26;
5027 
parameter adr_lo   = 2;
5028 
parameter dat_size = 32;
5029 
parameter sel_size = dat_size/8;
5030 
 
5031 
localparam aw = (adr_size - adr_lo) * nr_of_ports;
5032 
localparam dw = dat_size * nr_of_ports;
5033 
localparam sw = sel_size * nr_of_ports;
5034 
localparam cw = 3 * nr_of_ports;
5035 
localparam bw = 2 * nr_of_ports;
5036 
 
5037 
input  [dw-1:0] wbm_dat_o;
5038 
input  [aw-1:0] wbm_adr_o;
5039 
input  [sw-1:0] wbm_sel_o;
5040 
input  [cw-1:0] wbm_cti_o;
5041 
input  [bw-1:0] wbm_bte_o;
5042 
input  [nr_of_ports-1:0] wbm_we_o, wbm_stb_o, wbm_cyc_o;
5043 
output [dw-1:0] wbm_dat_i;
5044 
output [nr_of_ports-1:0] wbm_ack_i, wbm_err_i, wbm_rty_i;
5045 
 
5046 
output [dat_size-1:0] wbs_dat_i;
5047 
output [adr_size-1:adr_lo] wbs_adr_i;
5048 
output [sel_size-1:0] wbs_sel_i;
5049 
output [2:0] wbs_cti_i;
5050 
output [1:0] wbs_bte_i;
5051 
output wbs_we_i, wbs_stb_i, wbs_cyc_i;
5052 
input  [dat_size-1:0] wbs_dat_o;
5053 
input  wbs_ack_o, wbs_err_o, wbs_rty_o;
5054 
 
5055 
input wb_clk, wb_rst;
5056 
 
5057 44 unneback 
reg  [nr_of_ports-1:0] select;
5058 39 unneback 
wire [nr_of_ports-1:0] state;
5059 
wire [nr_of_ports-1:0] eoc; // end-of-cycle
5060 
wire [nr_of_ports-1:0] sel;
5061 
wire idle;
5062 
 
5063 
genvar i;
5064 
 
5065 
assign idle = !(|state);
5066 
 
5067 
generate
5068 
if (nr_of_ports == 2) begin
5069 
 
5070 
    wire [2:0] wbm1_cti_o, wbm0_cti_o;
5071 
 
5072 
    assign {wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5073 
 
5074 44 unneback 
    //assign select = (idle) ? {wbm_cyc_o[1],!wbm_cyc_o[1] & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5075 
 
5076 
    always @ (idle or wbm_cyc_o)
5077 
    if (idle)
5078 
        casex (wbm_cyc_o)
5079 
        2'b1x : select = 2'b10;
5080 
        2'b01 : select = 2'b01;
5081 
        default : select = {nr_of_ports{1'b0}};
5082 
        endcase
5083 
    else
5084 
        select = {nr_of_ports{1'b0}};
5085 
 
5086 39 unneback 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5087 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5088 
 
5089 
end
5090 
endgenerate
5091 
 
5092 
generate
5093 
if (nr_of_ports == 3) begin
5094 
 
5095 
    wire [2:0] wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5096 
 
5097 
    assign {wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5098 
 
5099 44 unneback 
    always @ (idle or wbm_cyc_o)
5100 
    if (idle)
5101 
        casex (wbm_cyc_o)
5102 
        3'b1xx : select = 3'b100;
5103 
        3'b01x : select = 3'b010;
5104 
        3'b001 : select = 3'b001;
5105 
        default : select = {nr_of_ports{1'b0}};
5106 
        endcase
5107 
    else
5108 
        select = {nr_of_ports{1'b0}};
5109 
 
5110 
//    assign select = (idle) ? {wbm_cyc_o[2],!wbm_cyc_o[2] & wbm_cyc_o[1],wbm_cyc_o[2:1]==2'b00 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5111 39 unneback 
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5112 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5113 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5114 
 
5115 
end
5116 
endgenerate
5117 
 
5118 
generate
5119 44 unneback 
if (nr_of_ports == 4) begin
5120 
 
5121 
    wire [2:0] wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5122 
 
5123 
    assign {wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5124 
 
5125 
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5126 
 
5127 
    always @ (idle or wbm_cyc_o)
5128 
    if (idle)
5129 
        casex (wbm_cyc_o)
5130 
        4'b1xxx : select = 4'b1000;
5131 
        4'b01xx : select = 4'b0100;
5132 
        4'b001x : select = 4'b0010;
5133 
        4'b0001 : select = 4'b0001;
5134 
        default : select = {nr_of_ports{1'b0}};
5135 
        endcase
5136 
    else
5137 
        select = {nr_of_ports{1'b0}};
5138 
 
5139 
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5140 
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5141 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5142 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5143 
 
5144 
end
5145 
endgenerate
5146 
 
5147 
generate
5148 
if (nr_of_ports == 5) begin
5149 
 
5150 
    wire [2:0] wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5151 
 
5152 
    assign {wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5153 
 
5154 
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5155 
 
5156 
    always @ (idle or wbm_cyc_o)
5157 
    if (idle)
5158 
        casex (wbm_cyc_o)
5159 
        5'b1xxxx : select = 5'b10000;
5160 
        5'b01xxx : select = 5'b01000;
5161 
        5'b001xx : select = 5'b00100;
5162 
        5'b0001x : select = 5'b00010;
5163 
        5'b00001 : select = 5'b00001;
5164 
        default : select = {nr_of_ports{1'b0}};
5165 
        endcase
5166 
    else
5167 
        select = {nr_of_ports{1'b0}};
5168 
 
5169 
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
5170 
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5171 
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5172 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5173 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5174 
 
5175 
end
5176 
endgenerate
5177 
 
5178 
generate
5179 67 unneback 
if (nr_of_ports == 6) begin
5180 
 
5181 
    wire [2:0] wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5182 
 
5183 
    assign {wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5184 
 
5185 
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5186 
 
5187 
    always @ (idle or wbm_cyc_o)
5188 
    if (idle)
5189 
        casex (wbm_cyc_o)
5190 
        6'b1xxxxx : select = 6'b100000;
5191 
        6'b01xxxx : select = 6'b010000;
5192 
        6'b001xxx : select = 6'b001000;
5193 
        6'b0001xx : select = 6'b000100;
5194 
        6'b00001x : select = 6'b000010;
5195 
        6'b000001 : select = 6'b000001;
5196 
        default : select = {nr_of_ports{1'b0}};
5197 
        endcase
5198 
    else
5199 
        select = {nr_of_ports{1'b0}};
5200 
 
5201 
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
5202 
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
5203 
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5204 
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5205 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5206 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5207 
 
5208 
end
5209 
endgenerate
5210 
 
5211 
generate
5212 
if (nr_of_ports == 7) begin
5213 
 
5214 
    wire [2:0] wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5215 
 
5216 
    assign {wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5217 
 
5218 
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5219 
 
5220 
    always @ (idle or wbm_cyc_o)
5221 
    if (idle)
5222 
        casex (wbm_cyc_o)
5223 
        7'b1xxxxxx : select = 7'b1000000;
5224 
        7'b01xxxxx : select = 7'b0100000;
5225 
        7'b001xxxx : select = 7'b0010000;
5226 
        7'b0001xxx : select = 7'b0001000;
5227 
        7'b00001xx : select = 7'b0000100;
5228 
        7'b000001x : select = 7'b0000010;
5229 
        7'b0000001 : select = 7'b0000001;
5230 
        default : select = {nr_of_ports{1'b0}};
5231 
        endcase
5232 
    else
5233 
        select = {nr_of_ports{1'b0}};
5234 
 
5235 
    assign eoc[6] = (wbm_ack_i[6] & (wbm6_cti_o == 3'b000 | wbm6_cti_o == 3'b111)) | !wbm_cyc_o[6];
5236 
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
5237 
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
5238 
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5239 
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5240 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5241 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5242 
 
5243 
end
5244 
endgenerate
5245 
 
5246 
generate
5247 
if (nr_of_ports == 8) begin
5248 
 
5249 
    wire [2:0] wbm7_cti_o, wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
5250 
 
5251 
    assign {wbm7_cti_o, wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
5252 
 
5253 
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
5254 
 
5255 
    always @ (idle or wbm_cyc_o)
5256 
    if (idle)
5257 
        casex (wbm_cyc_o)
5258 
        8'b1xxxxxxx : select = 8'b10000000;
5259 
        8'b01xxxxxx : select = 8'b01000000;
5260 
        8'b001xxxxx : select = 8'b00100000;
5261 
        8'b0001xxxx : select = 8'b00010000;
5262 
        8'b00001xxx : select = 8'b00001000;
5263 
        8'b000001xx : select = 8'b00000100;
5264 
        8'b0000001x : select = 8'b00000010;
5265 
        8'b00000001 : select = 8'b00000001;
5266 
        default : select = {nr_of_ports{1'b0}};
5267 
        endcase
5268 
    else
5269 
        select = {nr_of_ports{1'b0}};
5270 
 
5271 
    assign eoc[7] = (wbm_ack_i[7] & (wbm7_cti_o == 3'b000 | wbm7_cti_o == 3'b111)) | !wbm_cyc_o[7];
5272 
    assign eoc[6] = (wbm_ack_i[6] & (wbm6_cti_o == 3'b000 | wbm6_cti_o == 3'b111)) | !wbm_cyc_o[6];
5273 
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
5274 
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
5275 
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
5276 
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
5277 
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
5278 
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
5279 
 
5280 
end
5281 
endgenerate
5282 
 
5283 
generate
5284 63 unneback 
for (i=0;i<nr_of_ports;i=i+1) begin : spr0
5285 42 unneback 
`define MODULE spr
5286 
    `BASE`MODULE sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));
5287 
`undef MODULE
5288 39 unneback 
end
5289 
endgenerate
5290 
 
5291 
    assign sel = select | state;
5292 
 
5293 40 unneback 
`define MODULE mux_andor
5294 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i));
5295 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(adr_size-adr_lo)) mux1 ( .a(wbm_adr_o), .sel(sel), .dout(wbs_adr_i));
5296 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(sel_size)) mux2 ( .a(wbm_sel_o), .sel(sel), .dout(wbs_sel_i));
5297 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(3)) mux3 ( .a(wbm_cti_o), .sel(sel), .dout(wbs_cti_i));
5298 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(2)) mux4 ( .a(wbm_bte_o), .sel(sel), .dout(wbs_bte_i));
5299 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux5 ( .a(wbm_we_o), .sel(sel), .dout(wbs_we_i));
5300 
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux6 ( .a(wbm_stb_o), .sel(sel), .dout(wbs_stb_i));
5301 
`undef MODULE
5302 39 unneback 
    assign wbs_cyc_i = |sel;
5303 
 
5304 
    assign wbm_dat_i = {nr_of_ports{wbs_dat_o}};
5305 
    assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
5306 
    assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
5307 
    assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
5308 
 
5309 
endmodule
5310 40 unneback 
`endif
5311 39 unneback 
 
5312 60 unneback 
`ifdef WB_B3_RAM_BE
5313 49 unneback 
// WB RAM with byte enable
5314 59 unneback 
`define MODULE wb_b3_ram_be
5315 
module `BASE`MODULE (
5316 
`undef MODULE
5317 69 unneback 
    wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
5318 
    wbs_dat_o, wbs_ack_o, wb_clk, wb_rst);
5319 59 unneback 
 
5320 68 unneback 
parameter adr_size = 16;
5321 60 unneback 
parameter adr_lo   = 2;
5322 68 unneback 
parameter mem_size = 1<<16;
5323 60 unneback 
parameter dat_size = 32;
5324 
parameter memory_init = 1;
5325 
parameter memory_file = "vl_ram.vmem";
5326 59 unneback 
 
5327 69 unneback 
localparam aw = (adr_size - adr_lo);
5328 
localparam dw = dat_size;
5329 
localparam sw = dat_size/8;
5330 
localparam cw = 3;
5331 
localparam bw = 2;
5332 60 unneback 
 
5333 70 unneback 
input [dw-1:0] wbs_dat_i;
5334 
input [aw-1:0] wbs_adr_i;
5335 
input [cw-1:0] wbs_cti_i;
5336 
input [bw-1:0] wbs_bte_i;
5337 
input [sw-1:0] wbs_sel_i;
5338 
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
5339 
output [dw-1:0] wbs_dat_o;
5340 
output wbs_ack_o;
5341 71 unneback 
input wb_clk, wb_rst;
5342 59 unneback 
 
5343 60 unneback 
wire [sw-1:0] cke;
5344 59 unneback 
 
5345 60 unneback 
reg wbs_ack_o;
5346 
 
5347 
`define MODULE ram_be
5348 
`BASE`MODULE # (
5349 
    .data_width(dat_size),
5350 72 unneback 
    .addr_width(adr_size-2),
5351 69 unneback 
    .mem_size(mem_size),
5352 68 unneback 
    .memory_init(memory_init),
5353 
    .memory_file(memory_file))
5354 60 unneback 
ram0(
5355 
`undef MODULE
5356 
    .d(wbs_dat_i),
5357 
    .adr(wbs_adr_i[adr_size-1:2]),
5358 
    .be(wbs_sel_i),
5359 
    .we(wbs_we_i),
5360 
    .q(wbs_dat_o),
5361 
    .clk(wb_clk)
5362 
);
5363 
 
5364 59 unneback 
always @ (posedge wb_clk or posedge wb_rst)
5365 
if (wb_rst)
5366 60 unneback 
    wbs_ack_o <= 1'b0;
5367 59 unneback 
else
5368 60 unneback 
    if (wbs_cti_i==3'b000 | wbs_cti_i==3'b111)
5369 
        wbs_ack_o <= wbs_stb_i & wbs_cyc_i & !wbs_ack_o;
5370 59 unneback 
    else
5371 60 unneback 
        wbs_ack_o <= wbs_stb_i & wbs_cyc_i;
5372 
 
5373 59 unneback 
endmodule
5374 
`endif
5375 
 
5376 
`ifdef WB_B4_RAM_BE
5377 
// WB RAM with byte enable
5378 49 unneback 
`define MODULE wb_b4_ram_be
5379 
module `BASE`MODULE (
5380 
`undef MODULE
5381 
    wb_dat_i, wb_adr_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
5382 52 unneback 
    wb_dat_o, wb_stall_o, wb_ack_o, wb_clk, wb_rst);
5383 49 unneback 
 
5384 
    parameter dat_width = 32;
5385 
    parameter adr_width = 8;
5386 
 
5387 
input [dat_width-1:0] wb_dat_i;
5388 
input [adr_width-1:0] wb_adr_i;
5389 
input [dat_width/8-1:0] wb_sel_i;
5390 
input wb_we_i, wb_stb_i, wb_cyc_i;
5391 
output [dat_width-1:0] wb_dat_o;
5392 51 unneback 
reg [dat_width-1:0] wb_dat_o;
5393 52 unneback 
output wb_stall_o;
5394 49 unneback 
output wb_ack_o;
5395 
reg wb_ack_o;
5396 
input wb_clk, wb_rst;
5397 
 
5398 56 unneback 
wire [dat_width/8-1:0] cke;
5399 
 
5400 49 unneback 
generate
5401 
if (dat_width==32) begin
5402 51 unneback 
reg [7:0] ram3 [1<<(adr_width-2)-1:0];
5403 
reg [7:0] ram2 [1<<(adr_width-2)-1:0];
5404 
reg [7:0] ram1 [1<<(adr_width-2)-1:0];
5405 
reg [7:0] ram0 [1<<(adr_width-2)-1:0];
5406 56 unneback 
assign cke = wb_sel_i & {(dat_width/8){wb_we_i}};
5407 49 unneback 
    always @ (posedge wb_clk)
5408 
    begin
5409 56 unneback 
        if (cke[3]) ram3[wb_adr_i[adr_width-1:2]] <= wb_dat_i[31:24];
5410 
        if (cke[2]) ram2[wb_adr_i[adr_width-1:2]] <= wb_dat_i[23:16];
5411 
        if (cke[1]) ram1[wb_adr_i[adr_width-1:2]] <= wb_dat_i[15:8];
5412 
        if (cke[0]) ram0[wb_adr_i[adr_width-1:2]] <= wb_dat_i[7:0];
5413 49 unneback 
    end
5414 59 unneback 
    always @ (posedge wb_clk or posedge wb_rst)
5415 
    begin
5416 
        if (wb_rst)
5417 
            wb_dat_o <= 32'h0;
5418 
        else
5419 
            wb_dat_o <= {ram3[wb_adr_i[adr_width-1:2]],ram2[wb_adr_i[adr_width-1:2]],ram1[wb_adr_i[adr_width-1:2]],ram0[wb_adr_i[adr_width-1:2]]};
5420 
    end
5421 49 unneback 
end
5422 
endgenerate
5423 
 
5424 52 unneback 
always @ (posedge wb_clk or posedge wb_rst)
5425 55 unneback 
if (wb_rst)
5426 52 unneback 
    wb_ack_o <= 1'b0;
5427 
else
5428 54 unneback 
    wb_ack_o <= wb_stb_i & wb_cyc_i;
5429 52 unneback 
 
5430 
assign wb_stall_o = 1'b0;
5431 
 
5432 49 unneback 
endmodule
5433 
`endif
5434 
 
5435 48 unneback 
`ifdef WB_B4_ROM
5436 
// WB ROM
5437 
`define MODULE wb_b4_rom
5438 
module `BASE`MODULE (
5439 
`undef MODULE
5440 
    wb_adr_i, wb_stb_i, wb_cyc_i,
5441 
    wb_dat_o, stall_o, wb_ack_o, wb_clk, wb_rst);
5442 
 
5443 
    parameter dat_width = 32;
5444 
    parameter dat_default = 32'h15000000;
5445 
    parameter adr_width = 32;
5446 
 
5447 
/*
5448 
`ifndef ROM
5449 
`define ROM "rom.v"
5450 
`endif
5451 
*/
5452 
    input [adr_width-1:2]   wb_adr_i;
5453 
    input                   wb_stb_i;
5454 
    input                   wb_cyc_i;
5455 
    output [dat_width-1:0]  wb_dat_o;
5456 
    reg [dat_width-1:0]     wb_dat_o;
5457 
    output                  wb_ack_o;
5458 
    reg                     wb_ack_o;
5459 
    output                  stall_o;
5460 
    input                   wb_clk;
5461 
    input                   wb_rst;
5462 
 
5463 
always @ (posedge wb_clk or posedge wb_rst)
5464 
    if (wb_rst)
5465 
        wb_dat_o <= {dat_width{1'b0}};
5466 
    else
5467 
         case (wb_adr_i[adr_width-1:2])
5468 
`ifdef ROM
5469 
`include `ROM
5470 
`endif
5471 
           default:
5472 
             wb_dat_o <= dat_default;
5473 
 
5474 
         endcase // case (wb_adr_i)
5475 
 
5476 
 
5477 
always @ (posedge wb_clk or posedge wb_rst)
5478 
    if (wb_rst)
5479 
        wb_ack_o <= 1'b0;
5480 
    else
5481 
        wb_ack_o <= wb_stb_i & wb_cyc_i;
5482 
 
5483 
assign stall_o = 1'b0;
5484 
 
5485 
endmodule
5486 
`endif
5487 
 
5488 
 
5489 40 unneback 
`ifdef WB_BOOT_ROM
5490 17 unneback 
// WB ROM
5491 40 unneback 
`define MODULE wb_boot_rom
5492 
module `BASE`MODULE (
5493 
`undef MODULE
5494 17 unneback 
    wb_adr_i, wb_stb_i, wb_cyc_i,
5495 18 unneback 
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
5496 17 unneback 
 
5497 18 unneback 
    parameter adr_hi = 31;
5498 
    parameter adr_lo = 28;
5499 
    parameter adr_sel = 4'hf;
5500 
    parameter addr_width = 5;
5501 33 unneback 
/*
5502 17 unneback 
`ifndef BOOT_ROM
5503 
`define BOOT_ROM "boot_rom.v"
5504 
`endif
5505 33 unneback 
*/
5506 18 unneback 
    input [adr_hi:2]    wb_adr_i;
5507 
    input               wb_stb_i;
5508 
    input               wb_cyc_i;
5509 
    output [31:0]        wb_dat_o;
5510 
    output              wb_ack_o;
5511 
    output              hit_o;
5512 
    input               wb_clk;
5513 
    input               wb_rst;
5514 
 
5515 
    wire hit;
5516 
    reg [31:0] wb_dat;
5517 
    reg wb_ack;
5518 
 
5519 
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
5520 17 unneback 
 
5521 
always @ (posedge wb_clk or posedge wb_rst)
5522 
    if (wb_rst)
5523 18 unneback 
        wb_dat <= 32'h15000000;
5524 17 unneback 
    else
5525 18 unneback 
         case (wb_adr_i[addr_width-1:2])
5526 33 unneback 
`ifdef BOOT_ROM
5527 17 unneback 
`include `BOOT_ROM
5528 33 unneback 
`endif
5529 17 unneback 
           /*
5530 
            // Zero r0 and jump to 0x00000100
5531 18 unneback 
 
5532 
            1 : wb_dat <= 32'hA8200000;
5533 
            2 : wb_dat <= 32'hA8C00100;
5534 
            3 : wb_dat <= 32'h44003000;
5535 
            4 : wb_dat <= 32'h15000000;
5536 17 unneback 
            */
5537 
           default:
5538 18 unneback 
             wb_dat <= 32'h00000000;
5539 17 unneback 
 
5540 
         endcase // case (wb_adr_i)
5541 
 
5542 
 
5543 
always @ (posedge wb_clk or posedge wb_rst)
5544 
    if (wb_rst)
5545 18 unneback 
        wb_ack <= 1'b0;
5546 17 unneback 
    else
5547 18 unneback 
        wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
5548 17 unneback 
 
5549 18 unneback 
assign hit_o = hit;
5550 
assign wb_dat_o = wb_dat & {32{wb_ack}};
5551 
assign wb_ack_o = wb_ack;
5552 
 
5553 17 unneback 
endmodule
5554 40 unneback 
`endif
5555 32 unneback 
 
5556 40 unneback 
`ifdef WB_DPRAM
5557 
`define MODULE wb_dpram
5558 
module `BASE`MODULE (
5559 
`undef MODULE
5560 32 unneback 
        // wishbone slave side a
5561 
        wbsa_dat_i, wbsa_adr_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o,
5562 
        wbsa_clk, wbsa_rst,
5563 
        // wishbone slave side a
5564 
        wbsb_dat_i, wbsb_adr_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o,
5565 
        wbsb_clk, wbsb_rst);
5566 
 
5567 
parameter data_width = 32;
5568 
parameter addr_width = 8;
5569 
 
5570 
parameter dat_o_mask_a = 1;
5571 
parameter dat_o_mask_b = 1;
5572 
 
5573 
input [31:0] wbsa_dat_i;
5574 
input [addr_width-1:2] wbsa_adr_i;
5575 
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
5576 
output [31:0] wbsa_dat_o;
5577 
output wbsa_ack_o;
5578 
input wbsa_clk, wbsa_rst;
5579 
 
5580 
input [31:0] wbsb_dat_i;
5581 
input [addr_width-1:2] wbsb_adr_i;
5582 
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
5583 
output [31:0] wbsb_dat_o;
5584 
output wbsb_ack_o;
5585 
input wbsb_clk, wbsb_rst;
5586 
 
5587 
wire wbsa_dat_tmp, wbsb_dat_tmp;
5588 
 
5589 40 unneback 
`define MODULE dpram_2r2w
5590 
`BASE`MODULE # (
5591 
`undef MODULE
5592 33 unneback 
    .data_width(data_width), .addr_width(addr_width) )
5593 32 unneback 
dpram0(
5594 
    .d_a(wbsa_dat_i),
5595 
    .q_a(wbsa_dat_tmp),
5596 
    .adr_a(wbsa_adr_i),
5597 
    .we_a(wbsa_we_i),
5598 
    .clk_a(wbsa_clk),
5599 
    .d_b(wbsb_dat_i),
5600 
    .q_b(wbsb_dat_tmp),
5601 
    .adr_b(wbsb_adr_i),
5602 
    .we_b(wbsb_we_i),
5603 
    .clk_b(wbsb_clk) );
5604 
 
5605 33 unneback 
generate if (dat_o_mask_a==1)
5606 32 unneback 
    assign wbsa_dat_o = wbsa_dat_tmp & {data_width{wbsa_ack_o}};
5607 
endgenerate
5608 33 unneback 
generate if (dat_o_mask_a==0)
5609 32 unneback 
    assign wbsa_dat_o = wbsa_dat_tmp;
5610 
endgenerate
5611 
 
5612 33 unneback 
generate if (dat_o_mask_b==1)
5613 32 unneback 
    assign wbsb_dat_o = wbsb_dat_tmp & {data_width{wbsb_ack_o}};
5614 
endgenerate
5615 33 unneback 
generate if (dat_o_mask_b==0)
5616 32 unneback 
    assign wbsb_dat_o = wbsb_dat_tmp;
5617 
endgenerate
5618 
 
5619 40 unneback 
`define MODULE spr
5620 
`BASE`MODULE ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
5621 
`BASE`MODULE ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
5622 
`undef MODULE
5623 32 unneback 
 
5624 
endmodule
5625 40 unneback 
`endif
5626 18 unneback 
//////////////////////////////////////////////////////////////////////
5627 
////                                                              ////
5628 
////  Arithmetic functions                                        ////
5629 
////                                                              ////
5630 
////  Description                                                 ////
5631 
////  Arithmetic functions for ALU and DSP                        ////
5632 
////                                                              ////
5633 
////                                                              ////
5634 
////  To Do:                                                      ////
5635 
////   -                                                          ////
5636 
////                                                              ////
5637 
////  Author(s):                                                  ////
5638 
////      - Michael Unneback, unneback@opencores.org              ////
5639 
////        ORSoC AB                                              ////
5640 
////                                                              ////
5641 
//////////////////////////////////////////////////////////////////////
5642 
////                                                              ////
5643 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
5644 
////                                                              ////
5645 
//// This source file may be used and distributed without         ////
5646 
//// restriction provided that this copyright statement is not    ////
5647 
//// removed from the file and that any derivative work contains  ////
5648 
//// the original copyright notice and the associated disclaimer. ////
5649 
////                                                              ////
5650 
//// This source file is free software; you can redistribute it   ////
5651 
//// and/or modify it under the terms of the GNU Lesser General   ////
5652 
//// Public License as published by the Free Software Foundation; ////
5653 
//// either version 2.1 of the License, or (at your option) any   ////
5654 
//// later version.                                               ////
5655 
////                                                              ////
5656 
//// This source is distributed in the hope that it will be       ////
5657 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
5658 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
5659 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
5660 
//// details.                                                     ////
5661 
////                                                              ////
5662 
//// You should have received a copy of the GNU Lesser General    ////
5663 
//// Public License along with this source; if not, download it   ////
5664 
//// from http://www.opencores.org/lgpl.shtml                     ////
5665 
////                                                              ////
5666 
//////////////////////////////////////////////////////////////////////
5667 
 
5668 40 unneback 
`ifdef MULTS
5669 18 unneback 
// signed multiplication
5670 40 unneback 
`define MODULE mults
5671 
module `BASE`MODULE (a,b,p);
5672 
`undef MODULE
5673 18 unneback 
parameter operand_a_width = 18;
5674 
parameter operand_b_width = 18;
5675 
parameter result_hi = 35;
5676 
parameter result_lo = 0;
5677 
input [operand_a_width-1:0] a;
5678 
input [operand_b_width-1:0] b;
5679 
output [result_hi:result_lo] p;
5680 
wire signed [operand_a_width-1:0] ai;
5681 
wire signed [operand_b_width-1:0] bi;
5682 
wire signed [operand_a_width+operand_b_width-1:0] result;
5683 
 
5684 
    assign ai = a;
5685 
    assign bi = b;
5686 
    assign result = ai * bi;
5687 
    assign p = result[result_hi:result_lo];
5688 
 
5689 
endmodule
5690 40 unneback 
`endif
5691 
`ifdef MULTS18X18
5692 
`define MODULE mults18x18
5693 
module `BASE`MODULE (a,b,p);
5694 
`undef MODULE
5695 18 unneback 
input [17:0] a,b;
5696 
output [35:0] p;
5697 
vl_mult
5698 
    # (.operand_a_width(18), .operand_b_width(18))
5699 
    mult0 (.a(a), .b(b), .p(p));
5700 
endmodule
5701 40 unneback 
`endif
5702 18 unneback 
 
5703 40 unneback 
`ifdef MULT
5704 
`define MODULE mult
5705 18 unneback 
// unsigned multiplication
5706 40 unneback 
module `BASE`MODULE (a,b,p);
5707 
`undef MODULE
5708 18 unneback 
parameter operand_a_width = 18;
5709 
parameter operand_b_width = 18;
5710 
parameter result_hi = 35;
5711 
parameter result_lo = 0;
5712 
input [operand_a_width-1:0] a;
5713 
input [operand_b_width-1:0] b;
5714 
output [result_hi:result_hi] p;
5715 
 
5716 
wire [operand_a_width+operand_b_width-1:0] result;
5717 
 
5718 
    assign result = a * b;
5719 
    assign p = result[result_hi:result_lo];
5720 
 
5721 
endmodule
5722 40 unneback 
`endif
5723 18 unneback 
 
5724 40 unneback 
`ifdef SHIFT_UNIT_32
5725 
`define MODULE shift_unit_32
5726 18 unneback 
// shift unit
5727 
// supporting the following shift functions
5728 
//   SLL
5729 
//   SRL
5730 
//   SRA
5731 
`define SHIFT_UNIT_MULT # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7))
5732 40 unneback 
module `BASE`MODULE( din, s, dout, opcode);
5733 
`undef MODULE
5734 18 unneback 
input [31:0] din; // data in operand
5735 
input [4:0] s; // shift operand
5736 
input [1:0] opcode;
5737 
output [31:0] dout;
5738 
 
5739 
parameter opcode_sll = 2'b00;
5740 
//parameter opcode_srl = 2'b01;
5741 
parameter opcode_sra = 2'b10;
5742 
//parameter opcode_ror = 2'b11;
5743 
 
5744 
wire sll, sra;
5745 
assign sll = opcode == opcode_sll;
5746 
assign sra = opcode == opcode_sra;
5747 
 
5748 
wire [15:1] s1;
5749 
wire [3:0] sign;
5750 
wire [7:0] tmp [0:3];
5751 
 
5752 
// first stage is multiplier based
5753 
// shift operand as fractional 8.7
5754 
assign s1[15] = sll & s[2:0]==3'd7;
5755 
assign s1[14] = sll & s[2:0]==3'd6;
5756 
assign s1[13] = sll & s[2:0]==3'd5;
5757 
assign s1[12] = sll & s[2:0]==3'd4;
5758 
assign s1[11] = sll & s[2:0]==3'd3;
5759 
assign s1[10] = sll & s[2:0]==3'd2;
5760 
assign s1[ 9] = sll & s[2:0]==3'd1;
5761 
assign s1[ 8] = s[2:0]==3'd0;
5762 
assign s1[ 7] = !sll & s[2:0]==3'd1;
5763 
assign s1[ 6] = !sll & s[2:0]==3'd2;
5764 
assign s1[ 5] = !sll & s[2:0]==3'd3;
5765 
assign s1[ 4] = !sll & s[2:0]==3'd4;
5766 
assign s1[ 3] = !sll & s[2:0]==3'd5;
5767 
assign s1[ 2] = !sll & s[2:0]==3'd6;
5768 
assign s1[ 1] = !sll & s[2:0]==3'd7;
5769 
 
5770 
assign sign[3] = din[31] & sra;
5771 
assign sign[2] = sign[3] & (&din[31:24]);
5772 
assign sign[1] = sign[2] & (&din[23:16]);
5773 
assign sign[0] = sign[1] & (&din[15:8]);
5774 40 unneback 
`define MODULE mults
5775 
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte3 ( .a({sign[3], {8{sign[3]}},din[31:24], din[23:16]}), .b({1'b0,s1}), .p(tmp[3]));
5776 
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte2 ( .a({sign[2], din[31:24]  ,din[23:16],  din[15:8]}), .b({1'b0,s1}), .p(tmp[2]));
5777 
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte1 ( .a({sign[1], din[23:16]  ,din[15:8],   din[7:0]}), .b({1'b0,s1}), .p(tmp[1]));
5778 
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte0 ( .a({sign[0], din[15:8]   ,din[7:0],    8'h00}),      .b({1'b0,s1}), .p(tmp[0]));
5779 
`undef MODULE
5780 18 unneback 
// second stage is multiplexer based
5781 
// shift on byte level
5782 
 
5783 
// mux byte 3
5784 
assign dout[31:24] = (s[4:3]==2'b00) ? tmp[3] :
5785 
                     (sll & s[4:3]==2'b01) ? tmp[2] :
5786 
                     (sll & s[4:3]==2'b10) ? tmp[1] :
5787 
                     (sll & s[4:3]==2'b11) ? tmp[0] :
5788 
                     {8{sign[3]}};
5789 
 
5790 
// mux byte 2
5791 
assign dout[23:16] = (s[4:3]==2'b00) ? tmp[2] :
5792 
                     (sll & s[4:3]==2'b01) ? tmp[1] :
5793 
                     (sll & s[4:3]==2'b10) ? tmp[0] :
5794 
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
5795 
                     (s[4:3]==2'b01) ? tmp[3] :
5796 
                     {8{sign[3]}};
5797 
 
5798 
// mux byte 1
5799 
assign dout[15:8]  = (s[4:3]==2'b00) ? tmp[1] :
5800 
                     (sll & s[4:3]==2'b01) ? tmp[0] :
5801 
                     (sll & s[4:3]==2'b10) ? {8{1'b0}} :
5802 
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
5803 
                     (s[4:3]==2'b01) ? tmp[2] :
5804 
                     (s[4:3]==2'b10) ? tmp[3] :
5805 
                     {8{sign[3]}};
5806 
 
5807 
// mux byte 0
5808 
assign dout[7:0]   = (s[4:3]==2'b00) ? tmp[0] :
5809 
                     (sll) ?  {8{1'b0}}:
5810 
                     (s[4:3]==2'b01) ? tmp[1] :
5811 
                     (s[4:3]==2'b10) ? tmp[2] :
5812 
                     tmp[3];
5813 
 
5814 
endmodule
5815 40 unneback 
`endif
5816 18 unneback 
 
5817 40 unneback 
`ifdef LOGIC_UNIT
5818 18 unneback 
// logic unit
5819 
// supporting the following logic functions
5820 
//    a and b
5821 
//    a or  b
5822 
//    a xor b
5823 
//    not b
5824 40 unneback 
`define MODULE logic_unit
5825 
module `BASE`MODULE( a, b, result, opcode);
5826 
`undef MODULE
5827 18 unneback 
parameter width = 32;
5828 
parameter opcode_and = 2'b00;
5829 
parameter opcode_or  = 2'b01;
5830 
parameter opcode_xor = 2'b10;
5831 
input [width-1:0] a,b;
5832 
output [width-1:0] result;
5833 
input [1:0] opcode;
5834 
 
5835 
assign result = (opcode==opcode_and) ? a & b :
5836 
                (opcode==opcode_or)  ? a | b :
5837 
                (opcode==opcode_xor) ? a ^ b :
5838 
                b;
5839 
 
5840 
endmodule
5841 48 unneback 
`endif
5842 18 unneback 
 
5843 48 unneback 
`ifdef ARITH_UNIT
5844 
`define MODULE arith_unit
5845 
module `BASE`MODULE ( a, b, c_in, add_sub, sign, result, c_out, z, ovfl);
5846 
`undef MODULE
5847 18 unneback 
parameter width = 32;
5848 
parameter opcode_add = 1'b0;
5849 
parameter opcode_sub = 1'b1;
5850 
input [width-1:0] a,b;
5851 
input c_in, add_sub, sign;
5852 
output [width-1:0] result;
5853 
output c_out, z, ovfl;
5854 
 
5855 
assign {c_out,result} = {(a[width-1] & sign),a} + ({a[width-1] & sign,b} ^ {(width+1){(add_sub==opcode_sub)}}) + {{(width-1){1'b0}},(c_in | (add_sub==opcode_sub))};
5856 
assign z = (result=={width{1'b0}});
5857 
assign ovfl = ( a[width-1] &  b[width-1] & ~result[width-1]) |
5858 
               (~a[width-1] & ~b[width-1] &  result[width-1]);
5859 
endmodule
5860 40 unneback 
`endif
5861 48 unneback 
 
5862 
`ifdef COUNT_UNIT
5863 
`define MODULE count_unit
5864 
module `BASE`MODULE (din, dout, opcode);
5865 
`undef MODULE
5866 
parameter width = 32;
5867 
input [width-1:0] din;
5868 
output [width-1:0] dout;
5869 
input opcode;
5870 
 
5871 
integer i;
5872 58 unneback 
wire [width/32+4:0] ff1, fl1;
5873 48 unneback 
 
5874 57 unneback 
/*
5875 48 unneback 
always @(din) begin
5876 
    ff1 = 0; i = 0;
5877 
    while (din[i] == 0 && i < width) begin // complex condition
5878 
        ff1 = ff1 + 1;
5879 
        i = i + 1;
5880 
    end
5881 
end
5882 
 
5883 
always @(din) begin
5884 
    fl1 = width; i = width-1;
5885 
    while (din[i] == 0 && i >= width) begin // complex condition
5886 
        fl1 = fl1 - 1;
5887 
        i = i - 1;
5888 
    end
5889 
end
5890 57 unneback 
*/
5891 48 unneback 
 
5892 
generate
5893 
if (width==32) begin
5894 57 unneback 
 
5895 
    assign ff1 = din[0] ? 6'd1 :
5896 
                 din[1] ? 6'd2 :
5897 
                 din[2] ? 6'd3 :
5898 
                 din[3] ? 6'd4 :
5899 
                 din[4] ? 6'd5 :
5900 
                 din[5] ? 6'd6 :
5901 
                 din[6] ? 6'd7 :
5902 
                 din[7] ? 6'd8 :
5903 
                 din[8] ? 6'd9 :
5904 
                 din[9] ? 6'd10 :
5905 
                 din[10] ? 6'd11 :
5906 
                 din[11] ? 6'd12 :
5907 
                 din[12] ? 6'd13 :
5908 
                 din[13] ? 6'd14 :
5909 
                 din[14] ? 6'd15 :
5910 
                 din[15] ? 6'd16 :
5911 
                 din[16] ? 6'd17 :
5912 
                 din[17] ? 6'd18 :
5913 
                 din[18] ? 6'd19 :
5914 
                 din[19] ? 6'd20 :
5915 
                 din[20] ? 6'd21 :
5916 
                 din[21] ? 6'd22 :
5917 
                 din[22] ? 6'd23 :
5918 
                 din[23] ? 6'd24 :
5919 
                 din[24] ? 6'd25 :
5920 
                 din[25] ? 6'd26 :
5921 
                 din[26] ? 6'd27 :
5922 
                 din[27] ? 6'd28 :
5923 
                 din[28] ? 6'd29 :
5924 
                 din[29] ? 6'd30 :
5925 
                 din[30] ? 6'd31 :
5926 
                 din[31] ? 6'd32 :
5927 
                 6'd0;
5928 
 
5929 
    assign fl1 = din[31] ? 6'd32 :
5930 
                 din[30] ? 6'd31 :
5931 
                 din[29] ? 6'd30 :
5932 
                 din[28] ? 6'd29 :
5933 
                 din[27] ? 6'd28 :
5934 
                 din[26] ? 6'd27 :
5935 
                 din[25] ? 6'd26 :
5936 
                 din[24] ? 6'd25 :
5937 
                 din[23] ? 6'd24 :
5938 
                 din[22] ? 6'd23 :
5939 
                 din[21] ? 6'd22 :
5940 
                 din[20] ? 6'd21 :
5941 
                 din[19] ? 6'd20 :
5942 
                 din[18] ? 6'd19 :
5943 
                 din[17] ? 6'd18 :
5944 
                 din[16] ? 6'd17 :
5945 
                 din[15] ? 6'd16 :
5946 
                 din[14] ? 6'd15 :
5947 
                 din[13] ? 6'd14 :
5948 
                 din[12] ? 6'd13 :
5949 
                 din[11] ? 6'd12 :
5950 
                 din[10] ? 6'd11 :
5951 
                 din[9] ? 6'd10 :
5952 
                 din[8] ? 6'd9 :
5953 
                 din[7] ? 6'd8 :
5954 
                 din[6] ? 6'd7 :
5955 
                 din[5] ? 6'd6 :
5956 
                 din[4] ? 6'd5 :
5957 
                 din[3] ? 6'd4 :
5958 
                 din[2] ? 6'd3 :
5959 
                 din[1] ? 6'd2 :
5960 
                 din[0] ? 6'd1 :
5961 
                 6'd0;
5962 
 
5963 
    assign dout = (!opcode) ? {{26{1'b0}}, ff1} : {{26{1'b0}}, fl1};
5964 48 unneback 
end
5965 
endgenerate
5966 57 unneback 
 
5967 48 unneback 
generate
5968 
if (width==64) begin
5969 57 unneback 
    assign ff1 = 7'd0;
5970 
    assign fl1 = 7'd0;
5971 
    assign dout = (!opcode) ? {{57{1'b0}}, ff1} : {{57{1'b0}}, fl1};
5972 48 unneback 
end
5973 
endgenerate
5974 
 
5975 
endmodule
5976 
`endif
5977 
 
5978 
`ifdef EXT_UNIT
5979 
`define MODULE ext_unit
5980 
module `BASE`MODULE ( a, b, F, result, opcode);
5981 
`undef MODULE
5982 
parameter width = 32;
5983 
input [width-1:0] a, b;
5984 
input F;
5985 
output reg [width-1:0] result;
5986 
input [2:0] opcode;
5987 
 
5988 
generate
5989 
if (width==32) begin
5990 
always @ (a or b or F or opcode)
5991 
begin
5992 
    case (opcode)
5993 
    3'b000: result = {{24{1'b0}},a[7:0]};
5994 
    3'b001: result = {{24{a[7]}},a[7:0]};
5995 
    3'b010: result = {{16{1'b0}},a[7:0]};
5996 
    3'b011: result = {{16{a[15]}},a[15:0]};
5997 
    3'b110: result = (F) ? a : b;
5998 
    default: result = {b[15:0],16'h0000};
5999 
    endcase
6000 
end
6001 
end
6002 
endgenerate
6003 
 
6004 
generate
6005 
if (width==64) begin
6006 
always @ (a or b or F or opcode)
6007 
begin
6008 
    case (opcode)
6009 
    3'b000: result = {{56{1'b0}},a[7:0]};
6010 
    3'b001: result = {{56{a[7]}},a[7:0]};
6011 
    3'b010: result = {{48{1'b0}},a[7:0]};
6012 
    3'b011: result = {{48{a[15]}},a[15:0]};
6013 57 unneback 
    3'b110: result = (F) ? a : b;
6014 48 unneback 
    default: result = {32'h00000000,b[15:0],16'h0000};
6015 
    endcase
6016 
end
6017 
end
6018 
endgenerate
6019 
endmodule
6020 
`endif

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