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1 6 unneback 
//////////////////////////////////////////////////////////////////////
2 
////                                                              ////
3 
////  Versatile library, clock and reset                          ////
4 
////                                                              ////
5 
////  Description                                                 ////
6 
////  Logic related to clock and reset                            ////
7 
////                                                              ////
8 
////                                                              ////
9 
////  To Do:                                                      ////
10 
////   - add more different registers                             ////
11 
////                                                              ////
12 
////  Author(s):                                                  ////
13 
////      - Michael Unneback, unneback@opencores.org              ////
14 
////        ORSoC AB                                              ////
15 
////                                                              ////
16 
//////////////////////////////////////////////////////////////////////
17 
////                                                              ////
18 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
19 
////                                                              ////
20 
//// This source file may be used and distributed without         ////
21 
//// restriction provided that this copyright statement is not    ////
22 
//// removed from the file and that any derivative work contains  ////
23 
//// the original copyright notice and the associated disclaimer. ////
24 
////                                                              ////
25 
//// This source file is free software; you can redistribute it   ////
26 
//// and/or modify it under the terms of the GNU Lesser General   ////
27 
//// Public License as published by the Free Software Foundation; ////
28 
//// either version 2.1 of the License, or (at your option) any   ////
29 
//// later version.                                               ////
30 
////                                                              ////
31 
//// This source is distributed in the hope that it will be       ////
32 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35 
//// details.                                                     ////
36 
////                                                              ////
37 
//// You should have received a copy of the GNU Lesser General    ////
38 
//// Public License along with this source; if not, download it   ////
39 
//// from http://www.opencores.org/lgpl.shtml                     ////
40 
////                                                              ////
41 
//////////////////////////////////////////////////////////////////////
42 
// Global buffer
43 
// usage:
44 
// use to enable global buffers for high fan out signals such as clock and reset
45 
`timescale 1 ns/100 ps
46 
// Version: 8.4 8.4.0.33
47 
module gbuf(GL,CLK);
48 
output GL;
49 
input  CLK;
50 
    wire GND;
51 
    GND GND_1_net(.Y(GND));
52 
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
53 
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
54 
endmodule
55 
`timescale 1 ns/1 ns
56 
module vl_gbuf ( i, o);
57 
input i;
58 
output o;
59 
`ifdef SIM_GBUF
60 
assign o=i;
61 
`else
62 
gbuf gbuf_i0 ( .CLK(i), .GL(o));
63 
`endif
64 
endmodule
65 
 //ACTEL
66 
// sync reset
67 
// input active lo async reset, normally from external reset generetaor and/or switch
68 
// output active high global reset sync with two DFFs
69 
`timescale 1 ns/100 ps
70 
module vl_sync_rst ( rst_n_i, rst_o, clk);
71 
input rst_n_i, clk;
72 
output rst_o;
73 
reg [0:1] tmp;
74 
always @ (posedge clk or negedge rst_n_i)
75 
if (!rst_n_i)
76 
        tmp <= 2'b00;
77 
else
78 
        tmp <= {1'b1,tmp[0]};
79 
vl_gbuf buf_i0( .i(tmp[1]), .o(rst_o));
80 
endmodule
81 
// vl_pll
82 
`timescale 1 ns/100 ps
83 
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
84 
parameter index = 0;
85 
parameter number_of_clk = 1;
86 
parameter period_time_0 = 20;
87 
parameter period_time_1 = 20;
88 
parameter period_time_2 = 20;
89 
parameter lock_delay = 2000;
90 
input clk_i, rst_n_i;
91 
output lock;
92 
output reg [0:number_of_clk-1] clk_o;
93 
output [0:number_of_clk-1] rst_o;
94 
`ifdef SIM_PLL
95 
always
96 
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
97 
generate if (number_of_clk > 1)
98 
always
99 
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
100 
endgenerate
101 
generate if (number_of_clk > 2)
102 
always
103 
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
104 
endgenerate
105 
genvar i;
106 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
107 
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
108 
end
109 
endgenerate
110 
assign #lock_delay lock = rst_n_i;
111 
endmodule
112 
`else
113 
generate if (number_of_clk==1 & index==0) begin
114 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
115 
end
116 
endgenerate // index==0
117 
generate if (number_of_clk==1 & index==1) begin
118 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
119 
end
120 
endgenerate // index==1
121 
generate if (number_of_clk==1 & index==2) begin
122 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
123 
end
124 
endgenerate // index==2
125 
generate if (number_of_clk==1 & index==3) begin
126 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
127 
end
128 
endgenerate // index==0
129 
generate if (number_of_clk==2 & index==0) begin
130 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
131 
end
132 
endgenerate // index==0
133 
generate if (number_of_clk==2 & index==1) begin
134 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
135 
end
136 
endgenerate // index==1
137 
generate if (number_of_clk==2 & index==2) begin
138 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
139 
end
140 
endgenerate // index==2
141 
generate if (number_of_clk==2 & index==3) begin
142 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
143 
end
144 
endgenerate // index==0
145 
generate if (number_of_clk==3 & index==0) begin
146 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
147 
end
148 
endgenerate // index==0
149 
generate if (number_of_clk==3 & index==1) begin
150 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
151 
end
152 
endgenerate // index==1
153 
generate if (number_of_clk==3 & index==2) begin
154 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
155 
end
156 
endgenerate // index==2
157 
generate if (number_of_clk==3 & index==3) begin
158 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
159 
end
160 
endgenerate // index==0
161 
genvar i;
162 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
163 
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
164 
end
165 
endgenerate
166 
endmodule
167 
`endif
168 
 //actel
169 
//////////////////////////////////////////////////////////////////////
170 
////                                                              ////
171 
////  Versatile library, registers                                ////
172 
////                                                              ////
173 
////  Description                                                 ////
174 
////  Different type of registers                                 ////
175 
////                                                              ////
176 
////                                                              ////
177 
////  To Do:                                                      ////
178 
////   - add more different registers                             ////
179 
////                                                              ////
180 
////  Author(s):                                                  ////
181 
////      - Michael Unneback, unneback@opencores.org              ////
182 
////        ORSoC AB                                              ////
183 
////                                                              ////
184 
//////////////////////////////////////////////////////////////////////
185 
////                                                              ////
186 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
187 
////                                                              ////
188 
//// This source file may be used and distributed without         ////
189 
//// restriction provided that this copyright statement is not    ////
190 
//// removed from the file and that any derivative work contains  ////
191 
//// the original copyright notice and the associated disclaimer. ////
192 
////                                                              ////
193 
//// This source file is free software; you can redistribute it   ////
194 
//// and/or modify it under the terms of the GNU Lesser General   ////
195 
//// Public License as published by the Free Software Foundation; ////
196 
//// either version 2.1 of the License, or (at your option) any   ////
197 
//// later version.                                               ////
198 
////                                                              ////
199 
//// This source is distributed in the hope that it will be       ////
200 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
201 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
202 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
203 
//// details.                                                     ////
204 
////                                                              ////
205 
//// You should have received a copy of the GNU Lesser General    ////
206 
//// Public License along with this source; if not, download it   ////
207 
//// from http://www.opencores.org/lgpl.shtml                     ////
208 
////                                                              ////
209 
//////////////////////////////////////////////////////////////////////
210 
module dff ( d, q, clk, rst);
211 
        parameter width = 1;
212 
        parameter reset_value = 0;
213 
        input [width-1:0] d;
214 
        input clk, rst;
215 
        output reg [width-1:0] q;
216 
        always @ (posedge clk or posedge rst)
217 
        if (rst)
218 
                q <= reset_value;
219 
        else
220 
                q <= d;
221 
endmodule
222 
module dff_array ( d, q, clk, rst);
223 
        parameter width = 1;
224 
        parameter depth = 2;
225 
        parameter reset_value = 1'b0;
226 
        input [width-1:0] d;
227 
        input clk, rst;
228 
        output [width-1:0] q;
229 
        reg  [0:depth-1] q_tmp [width-1:0];
230 
        integer i;
231 
        always @ (posedge clk or posedge rst)
232 
        if (rst) begin
233 
            for (i=0;i<depth;i=i+1)
234 
                q_tmp[i] <= {width{reset_value}};
235 
        end else begin
236 
            q_tmp[0] <= d;
237 
            for (i=1;i<depth;i=i+1)
238 
                q_tmp[i] <= q_tmp[i-1];
239 
        end
240 
    assign q = q_tmp[depth-1];
241 
endmodule
242 
module dff_ce ( d, ce, q, clk, rst);
243 
        parameter width = 1;
244 
        parameter reset_value = 0;
245 
        input [width-1:0] d;
246 
        input ce, clk, rst;
247 
        output reg [width-1:0] q;
248 
        always @ (posedge clk or posedge rst)
249 
        if (rst)
250 
                q <= reset_value;
251 
        else
252 
                if (ce)
253 
                        q <= d;
254 
endmodule
255 8 unneback 
module dff_ce_clear ( d, ce, clear, q, clk, rst);
256 
        parameter width = 1;
257 
        parameter reset_value = 0;
258 
        input [width-1:0] d;
259 10 unneback 
        input ce, clear, clk, rst;
260 8 unneback 
        output reg [width-1:0] q;
261 
        always @ (posedge clk or posedge rst)
262 
        if (rst)
263 
            q <= reset_value;
264 
        else
265 
            if (ce)
266 
                if (clear)
267 
                    q <= {width{1'b0}};
268 
                else
269 
                    q <= d;
270 
endmodule
271 6 unneback 
module dff_sr ( aclr, aset, clock, data, q);
272 
    input         aclr;
273 
    input         aset;
274 
    input         clock;
275 
    input         data;
276 
    output reg    q;
277 
   always @ (posedge clock or posedge aclr or posedge aset)
278 
     if (aclr)
279 
       q <= 1'b0;
280 
     else if (aset)
281 
       q <= 1'b1;
282 
     else
283 
       q <= data;
284 
endmodule
285 
// LATCH
286 
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
287 
module latch ( d, le, q, clk);
288 
input d, le;
289 
output q;
290 
input clk;/*
291 
   always @ (posedge direction_set or posedge direction_clr)
292 
     if (direction_clr)
293 
       direction <= going_empty;
294 
     else
295 
       direction <= going_full;*/
296 
endmodule
297 
//////////////////////////////////////////////////////////////////////
298 
////                                                              ////
299 
////  Versatile counter                                           ////
300 
////                                                              ////
301 
////  Description                                                 ////
302 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
303 
////  counter                                                     ////
304 
////                                                              ////
305 
////  To Do:                                                      ////
306 
////   - add LFSR with more taps                                  ////
307 
////                                                              ////
308 
////  Author(s):                                                  ////
309 
////      - Michael Unneback, unneback@opencores.org              ////
310 
////        ORSoC AB                                              ////
311 
////                                                              ////
312 
//////////////////////////////////////////////////////////////////////
313 
////                                                              ////
314 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
315 
////                                                              ////
316 
//// This source file may be used and distributed without         ////
317 
//// restriction provided that this copyright statement is not    ////
318 
//// removed from the file and that any derivative work contains  ////
319 
//// the original copyright notice and the associated disclaimer. ////
320 
////                                                              ////
321 
//// This source file is free software; you can redistribute it   ////
322 
//// and/or modify it under the terms of the GNU Lesser General   ////
323 
//// Public License as published by the Free Software Foundation; ////
324 
//// either version 2.1 of the License, or (at your option) any   ////
325 
//// later version.                                               ////
326 
////                                                              ////
327 
//// This source is distributed in the hope that it will be       ////
328 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
329 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
330 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
331 
//// details.                                                     ////
332 
////                                                              ////
333 
//// You should have received a copy of the GNU Lesser General    ////
334 
//// Public License along with this source; if not, download it   ////
335 
//// from http://www.opencores.org/lgpl.shtml                     ////
336 
////                                                              ////
337 
//////////////////////////////////////////////////////////////////////
338 
// binary counter
339 
module cnt_bin_ce ( cke, q, rst, clk);
340 
   parameter length = 4;
341 
   input cke;
342 
   output [length:1] q;
343 
   input rst;
344 
   input clk;
345 
   parameter clear_value = 0;
346 
   parameter set_value = 1;
347 
   parameter wrap_value = 0;
348 
   parameter level1_value = 15;
349 
   reg  [length:1] qi;
350 
   wire [length:1] q_next;
351 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
352 
   always @ (posedge clk or posedge rst)
353 
     if (rst)
354 
       qi <= {length{1'b0}};
355 
     else
356 
     if (cke)
357 
       qi <= q_next;
358 
   assign q = qi;
359 
endmodule
360 
//////////////////////////////////////////////////////////////////////
361 
////                                                              ////
362 
////  Versatile counter                                           ////
363 
////                                                              ////
364 
////  Description                                                 ////
365 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
366 
////  counter                                                     ////
367 
////                                                              ////
368 
////  To Do:                                                      ////
369 
////   - add LFSR with more taps                                  ////
370 
////                                                              ////
371 
////  Author(s):                                                  ////
372 
////      - Michael Unneback, unneback@opencores.org              ////
373 
////        ORSoC AB                                              ////
374 
////                                                              ////
375 
//////////////////////////////////////////////////////////////////////
376 
////                                                              ////
377 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
378 
////                                                              ////
379 
//// This source file may be used and distributed without         ////
380 
//// restriction provided that this copyright statement is not    ////
381 
//// removed from the file and that any derivative work contains  ////
382 
//// the original copyright notice and the associated disclaimer. ////
383 
////                                                              ////
384 
//// This source file is free software; you can redistribute it   ////
385 
//// and/or modify it under the terms of the GNU Lesser General   ////
386 
//// Public License as published by the Free Software Foundation; ////
387 
//// either version 2.1 of the License, or (at your option) any   ////
388 
//// later version.                                               ////
389 
////                                                              ////
390 
//// This source is distributed in the hope that it will be       ////
391 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
392 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
393 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
394 
//// details.                                                     ////
395 
////                                                              ////
396 
//// You should have received a copy of the GNU Lesser General    ////
397 
//// Public License along with this source; if not, download it   ////
398 
//// from http://www.opencores.org/lgpl.shtml                     ////
399 
////                                                              ////
400 
//////////////////////////////////////////////////////////////////////
401 
// binary counter
402 
module cnt_bin_ce_clear ( clear, cke, q, rst, clk);
403 
   parameter length = 4;
404 
   input clear;
405 
   input cke;
406 
   output [length:1] q;
407 
   input rst;
408 
   input clk;
409 
   parameter clear_value = 0;
410 
   parameter set_value = 1;
411 
   parameter wrap_value = 0;
412 
   parameter level1_value = 15;
413 
   reg  [length:1] qi;
414 
   wire [length:1] q_next;
415 
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
416 
   always @ (posedge clk or posedge rst)
417 
     if (rst)
418 
       qi <= {length{1'b0}};
419 
     else
420 
     if (cke)
421 
       qi <= q_next;
422 
   assign q = qi;
423 
endmodule
424 
//////////////////////////////////////////////////////////////////////
425 
////                                                              ////
426 
////  Versatile counter                                           ////
427 
////                                                              ////
428 
////  Description                                                 ////
429 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
430 
////  counter                                                     ////
431 
////                                                              ////
432 
////  To Do:                                                      ////
433 
////   - add LFSR with more taps                                  ////
434 
////                                                              ////
435 
////  Author(s):                                                  ////
436 
////      - Michael Unneback, unneback@opencores.org              ////
437 
////        ORSoC AB                                              ////
438 
////                                                              ////
439 
//////////////////////////////////////////////////////////////////////
440 
////                                                              ////
441 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
442 
////                                                              ////
443 
//// This source file may be used and distributed without         ////
444 
//// restriction provided that this copyright statement is not    ////
445 
//// removed from the file and that any derivative work contains  ////
446 
//// the original copyright notice and the associated disclaimer. ////
447 
////                                                              ////
448 
//// This source file is free software; you can redistribute it   ////
449 
//// and/or modify it under the terms of the GNU Lesser General   ////
450 
//// Public License as published by the Free Software Foundation; ////
451 
//// either version 2.1 of the License, or (at your option) any   ////
452 
//// later version.                                               ////
453 
////                                                              ////
454 
//// This source is distributed in the hope that it will be       ////
455 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
456 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
457 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
458 
//// details.                                                     ////
459 
////                                                              ////
460 
//// You should have received a copy of the GNU Lesser General    ////
461 
//// Public License along with this source; if not, download it   ////
462 
//// from http://www.opencores.org/lgpl.shtml                     ////
463 
////                                                              ////
464 
//////////////////////////////////////////////////////////////////////
465 
// binary counter
466 
module cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk);
467 
   parameter length = 4;
468 
   input clear;
469 
   input set;
470 
   input cke;
471 
   input rew;
472 
   output [length:1] q;
473 
   input rst;
474 
   input clk;
475 
   parameter clear_value = 0;
476 
   parameter set_value = 1;
477 
   parameter wrap_value = 0;
478 
   parameter level1_value = 15;
479 
   reg  [length:1] qi;
480 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
481 
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
482 
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
483 
   assign q_next = rew ? q_next_rew : q_next_fw;
484 
   always @ (posedge clk or posedge rst)
485 
     if (rst)
486 
       qi <= {length{1'b0}};
487 
     else
488 
     if (cke)
489 
       qi <= q_next;
490 
   assign q = qi;
491 
endmodule
492 
//////////////////////////////////////////////////////////////////////
493 
////                                                              ////
494 
////  Versatile counter                                           ////
495 
////                                                              ////
496 
////  Description                                                 ////
497 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
498 
////  counter                                                     ////
499 
////                                                              ////
500 
////  To Do:                                                      ////
501 
////   - add LFSR with more taps                                  ////
502 
////                                                              ////
503 
////  Author(s):                                                  ////
504 
////      - Michael Unneback, unneback@opencores.org              ////
505 
////        ORSoC AB                                              ////
506 
////                                                              ////
507 
//////////////////////////////////////////////////////////////////////
508 
////                                                              ////
509 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
510 
////                                                              ////
511 
//// This source file may be used and distributed without         ////
512 
//// restriction provided that this copyright statement is not    ////
513 
//// removed from the file and that any derivative work contains  ////
514 
//// the original copyright notice and the associated disclaimer. ////
515 
////                                                              ////
516 
//// This source file is free software; you can redistribute it   ////
517 
//// and/or modify it under the terms of the GNU Lesser General   ////
518 
//// Public License as published by the Free Software Foundation; ////
519 
//// either version 2.1 of the License, or (at your option) any   ////
520 
//// later version.                                               ////
521 
////                                                              ////
522 
//// This source is distributed in the hope that it will be       ////
523 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
524 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
525 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
526 
//// details.                                                     ////
527 
////                                                              ////
528 
//// You should have received a copy of the GNU Lesser General    ////
529 
//// Public License along with this source; if not, download it   ////
530 
//// from http://www.opencores.org/lgpl.shtml                     ////
531 
////                                                              ////
532 
//////////////////////////////////////////////////////////////////////
533 
// binary counter
534 
module cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk);
535 
   parameter length = 4;
536 
   input cke;
537 
   input rew;
538 
   output reg level1;
539 
   input rst;
540 
   input clk;
541 
   parameter clear_value = 0;
542 
   parameter set_value = 1;
543 
   parameter wrap_value = 1;
544 
   parameter level1_value = 15;
545 
   reg  [length:1] qi;
546 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
547 
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
548 
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
549 
   assign q_next = rew ? q_next_rew : q_next_fw;
550 
   always @ (posedge clk or posedge rst)
551 
     if (rst)
552 
       qi <= {length{1'b0}};
553 
     else
554 
     if (cke)
555 
       qi <= q_next;
556 
    always @ (posedge clk or posedge rst)
557 
    if (rst)
558 
        level1 <= 1'b0;
559 
    else
560 
    if (cke)
561 
    if (q_next == level1_value)
562 
        level1 <= 1'b1;
563 
    else if (qi == level1_value & rew)
564 
        level1 <= 1'b0;
565 
endmodule
566 
//////////////////////////////////////////////////////////////////////
567 
////                                                              ////
568 
////  Versatile counter                                           ////
569 
////                                                              ////
570 
////  Description                                                 ////
571 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
572 
////  counter                                                     ////
573 
////                                                              ////
574 
////  To Do:                                                      ////
575 
////   - add LFSR with more taps                                  ////
576 
////                                                              ////
577 
////  Author(s):                                                  ////
578 
////      - Michael Unneback, unneback@opencores.org              ////
579 
////        ORSoC AB                                              ////
580 
////                                                              ////
581 
//////////////////////////////////////////////////////////////////////
582 
////                                                              ////
583 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
584 
////                                                              ////
585 
//// This source file may be used and distributed without         ////
586 
//// restriction provided that this copyright statement is not    ////
587 
//// removed from the file and that any derivative work contains  ////
588 
//// the original copyright notice and the associated disclaimer. ////
589 
////                                                              ////
590 
//// This source file is free software; you can redistribute it   ////
591 
//// and/or modify it under the terms of the GNU Lesser General   ////
592 
//// Public License as published by the Free Software Foundation; ////
593 
//// either version 2.1 of the License, or (at your option) any   ////
594 
//// later version.                                               ////
595 
////                                                              ////
596 
//// This source is distributed in the hope that it will be       ////
597 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
598 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
599 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
600 
//// details.                                                     ////
601 
////                                                              ////
602 
//// You should have received a copy of the GNU Lesser General    ////
603 
//// Public License along with this source; if not, download it   ////
604 
//// from http://www.opencores.org/lgpl.shtml                     ////
605 
////                                                              ////
606 
//////////////////////////////////////////////////////////////////////
607 
// LFSR counter
608 
module cnt_lfsr_zq ( zq, rst, clk);
609 
   parameter length = 4;
610 
   output reg zq;
611 
   input rst;
612 
   input clk;
613 
   parameter clear_value = 0;
614 
   parameter set_value = 1;
615 
   parameter wrap_value = 8;
616 
   parameter level1_value = 15;
617 
   reg  [length:1] qi;
618 
   reg lfsr_fb;
619 
   wire [length:1] q_next;
620 
   reg [32:1] polynom;
621 
   integer i;
622 
   always @ (qi)
623 
   begin
624 
        case (length)
625 
         2: polynom = 32'b11;                               // 0x3
626 
         3: polynom = 32'b110;                              // 0x6
627 
         4: polynom = 32'b1100;                             // 0xC
628 
         5: polynom = 32'b10100;                            // 0x14
629 
         6: polynom = 32'b110000;                           // 0x30
630 
         7: polynom = 32'b1100000;                          // 0x60
631 
         8: polynom = 32'b10111000;                         // 0xb8
632 
         9: polynom = 32'b100010000;                        // 0x110
633 
        10: polynom = 32'b1001000000;                       // 0x240
634 
        11: polynom = 32'b10100000000;                      // 0x500
635 
        12: polynom = 32'b100000101001;                     // 0x829
636 
        13: polynom = 32'b1000000001100;                    // 0x100C
637 
        14: polynom = 32'b10000000010101;                   // 0x2015
638 
        15: polynom = 32'b110000000000000;                  // 0x6000
639 
        16: polynom = 32'b1101000000001000;                 // 0xD008
640 
        17: polynom = 32'b10010000000000000;                // 0x12000
641 
        18: polynom = 32'b100000010000000000;               // 0x20400
642 
        19: polynom = 32'b1000000000000100011;              // 0x40023
643 
        20: polynom = 32'b10000010000000000000;             // 0x82000
644 
        21: polynom = 32'b101000000000000000000;            // 0x140000
645 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
646 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
647 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
648 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
649 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
650 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
651 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
652 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
653 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
654 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
655 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
656 
        default: polynom = 32'b0;
657 
        endcase
658 
        lfsr_fb = qi[length];
659 
        for (i=length-1; i>=1; i=i-1) begin
660 
            if (polynom[i])
661 
                lfsr_fb = lfsr_fb  ~^ qi[i];
662 
        end
663 
    end
664 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
665 
   always @ (posedge clk or posedge rst)
666 
     if (rst)
667 
       qi <= {length{1'b0}};
668 
     else
669 
       qi <= q_next;
670 
   always @ (posedge clk or posedge rst)
671 
     if (rst)
672 
       zq <= 1'b1;
673 
     else
674 
       zq <= q_next == {length{1'b0}};
675 
endmodule
676 
//////////////////////////////////////////////////////////////////////
677 
////                                                              ////
678 
////  Versatile counter                                           ////
679 
////                                                              ////
680 
////  Description                                                 ////
681 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
682 
////  counter                                                     ////
683 
////                                                              ////
684 
////  To Do:                                                      ////
685 
////   - add LFSR with more taps                                  ////
686 
////                                                              ////
687 
////  Author(s):                                                  ////
688 
////      - Michael Unneback, unneback@opencores.org              ////
689 
////        ORSoC AB                                              ////
690 
////                                                              ////
691 
//////////////////////////////////////////////////////////////////////
692 
////                                                              ////
693 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
694 
////                                                              ////
695 
//// This source file may be used and distributed without         ////
696 
//// restriction provided that this copyright statement is not    ////
697 
//// removed from the file and that any derivative work contains  ////
698 
//// the original copyright notice and the associated disclaimer. ////
699 
////                                                              ////
700 
//// This source file is free software; you can redistribute it   ////
701 
//// and/or modify it under the terms of the GNU Lesser General   ////
702 
//// Public License as published by the Free Software Foundation; ////
703 
//// either version 2.1 of the License, or (at your option) any   ////
704 
//// later version.                                               ////
705 
////                                                              ////
706 
//// This source is distributed in the hope that it will be       ////
707 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
708 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
709 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
710 
//// details.                                                     ////
711 
////                                                              ////
712 
//// You should have received a copy of the GNU Lesser General    ////
713 
//// Public License along with this source; if not, download it   ////
714 
//// from http://www.opencores.org/lgpl.shtml                     ////
715 
////                                                              ////
716 
//////////////////////////////////////////////////////////////////////
717 
// LFSR counter
718 
module cnt_lfsr_ce_zq ( cke, zq, rst, clk);
719 
   parameter length = 4;
720 
   input cke;
721 
   output reg zq;
722 
   input rst;
723 
   input clk;
724 
   parameter clear_value = 0;
725 
   parameter set_value = 1;
726 
   parameter wrap_value = 8;
727 
   parameter level1_value = 15;
728 
   reg  [length:1] qi;
729 
   reg lfsr_fb;
730 
   wire [length:1] q_next;
731 
   reg [32:1] polynom;
732 
   integer i;
733 
   always @ (qi)
734 
   begin
735 
        case (length)
736 
         2: polynom = 32'b11;                               // 0x3
737 
         3: polynom = 32'b110;                              // 0x6
738 
         4: polynom = 32'b1100;                             // 0xC
739 
         5: polynom = 32'b10100;                            // 0x14
740 
         6: polynom = 32'b110000;                           // 0x30
741 
         7: polynom = 32'b1100000;                          // 0x60
742 
         8: polynom = 32'b10111000;                         // 0xb8
743 
         9: polynom = 32'b100010000;                        // 0x110
744 
        10: polynom = 32'b1001000000;                       // 0x240
745 
        11: polynom = 32'b10100000000;                      // 0x500
746 
        12: polynom = 32'b100000101001;                     // 0x829
747 
        13: polynom = 32'b1000000001100;                    // 0x100C
748 
        14: polynom = 32'b10000000010101;                   // 0x2015
749 
        15: polynom = 32'b110000000000000;                  // 0x6000
750 
        16: polynom = 32'b1101000000001000;                 // 0xD008
751 
        17: polynom = 32'b10010000000000000;                // 0x12000
752 
        18: polynom = 32'b100000010000000000;               // 0x20400
753 
        19: polynom = 32'b1000000000000100011;              // 0x40023
754 
        20: polynom = 32'b10000010000000000000;             // 0x82000
755 
        21: polynom = 32'b101000000000000000000;            // 0x140000
756 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
757 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
758 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
759 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
760 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
761 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
762 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
763 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
764 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
765 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
766 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
767 
        default: polynom = 32'b0;
768 
        endcase
769 
        lfsr_fb = qi[length];
770 
        for (i=length-1; i>=1; i=i-1) begin
771 
            if (polynom[i])
772 
                lfsr_fb = lfsr_fb  ~^ qi[i];
773 
        end
774 
    end
775 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
776 
   always @ (posedge clk or posedge rst)
777 
     if (rst)
778 
       qi <= {length{1'b0}};
779 
     else
780 
     if (cke)
781 
       qi <= q_next;
782 
   always @ (posedge clk or posedge rst)
783 
     if (rst)
784 
       zq <= 1'b1;
785 
     else
786 
     if (cke)
787 
       zq <= q_next == {length{1'b0}};
788 
endmodule
789 
//////////////////////////////////////////////////////////////////////
790 
////                                                              ////
791 
////  Versatile counter                                           ////
792 
////                                                              ////
793 
////  Description                                                 ////
794 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
795 
////  counter                                                     ////
796 
////                                                              ////
797 
////  To Do:                                                      ////
798 
////   - add LFSR with more taps                                  ////
799 
////                                                              ////
800 
////  Author(s):                                                  ////
801 
////      - Michael Unneback, unneback@opencores.org              ////
802 
////        ORSoC AB                                              ////
803 
////                                                              ////
804 
//////////////////////////////////////////////////////////////////////
805 
////                                                              ////
806 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
807 
////                                                              ////
808 
//// This source file may be used and distributed without         ////
809 
//// restriction provided that this copyright statement is not    ////
810 
//// removed from the file and that any derivative work contains  ////
811 
//// the original copyright notice and the associated disclaimer. ////
812 
////                                                              ////
813 
//// This source file is free software; you can redistribute it   ////
814 
//// and/or modify it under the terms of the GNU Lesser General   ////
815 
//// Public License as published by the Free Software Foundation; ////
816 
//// either version 2.1 of the License, or (at your option) any   ////
817 
//// later version.                                               ////
818 
////                                                              ////
819 
//// This source is distributed in the hope that it will be       ////
820 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
821 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
822 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
823 
//// details.                                                     ////
824 
////                                                              ////
825 
//// You should have received a copy of the GNU Lesser General    ////
826 
//// Public License along with this source; if not, download it   ////
827 
//// from http://www.opencores.org/lgpl.shtml                     ////
828 
////                                                              ////
829 
//////////////////////////////////////////////////////////////////////
830 
// LFSR counter
831 
module cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk);
832 
   parameter length = 4;
833 
   input cke;
834 
   input rew;
835 
   output reg level1;
836 
   input rst;
837 
   input clk;
838 
   parameter clear_value = 0;
839 
   parameter set_value = 1;
840 
   parameter wrap_value = 8;
841 
   parameter level1_value = 15;
842 
   reg  [length:1] qi;
843 
   reg lfsr_fb, lfsr_fb_rew;
844 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
845 
   reg [32:1] polynom_rew;
846 
   integer j;
847 
   reg [32:1] polynom;
848 
   integer i;
849 
   always @ (qi)
850 
   begin
851 
        case (length)
852 
         2: polynom = 32'b11;                               // 0x3
853 
         3: polynom = 32'b110;                              // 0x6
854 
         4: polynom = 32'b1100;                             // 0xC
855 
         5: polynom = 32'b10100;                            // 0x14
856 
         6: polynom = 32'b110000;                           // 0x30
857 
         7: polynom = 32'b1100000;                          // 0x60
858 
         8: polynom = 32'b10111000;                         // 0xb8
859 
         9: polynom = 32'b100010000;                        // 0x110
860 
        10: polynom = 32'b1001000000;                       // 0x240
861 
        11: polynom = 32'b10100000000;                      // 0x500
862 
        12: polynom = 32'b100000101001;                     // 0x829
863 
        13: polynom = 32'b1000000001100;                    // 0x100C
864 
        14: polynom = 32'b10000000010101;                   // 0x2015
865 
        15: polynom = 32'b110000000000000;                  // 0x6000
866 
        16: polynom = 32'b1101000000001000;                 // 0xD008
867 
        17: polynom = 32'b10010000000000000;                // 0x12000
868 
        18: polynom = 32'b100000010000000000;               // 0x20400
869 
        19: polynom = 32'b1000000000000100011;              // 0x40023
870 
        20: polynom = 32'b10000010000000000000;             // 0x82000
871 
        21: polynom = 32'b101000000000000000000;            // 0x140000
872 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
873 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
874 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
875 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
876 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
877 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
878 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
879 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
880 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
881 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
882 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
883 
        default: polynom = 32'b0;
884 
        endcase
885 
        lfsr_fb = qi[length];
886 
        for (i=length-1; i>=1; i=i-1) begin
887 
            if (polynom[i])
888 
                lfsr_fb = lfsr_fb  ~^ qi[i];
889 
        end
890 
    end
891 
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
892 
   always @ (qi)
893 
   begin
894 
        case (length)
895 
         2: polynom_rew = 32'b11;
896 
         3: polynom_rew = 32'b110;
897 
         4: polynom_rew = 32'b1100;
898 
         5: polynom_rew = 32'b10100;
899 
         6: polynom_rew = 32'b110000;
900 
         7: polynom_rew = 32'b1100000;
901 
         8: polynom_rew = 32'b10111000;
902 
         9: polynom_rew = 32'b100010000;
903 
        10: polynom_rew = 32'b1001000000;
904 
        11: polynom_rew = 32'b10100000000;
905 
        12: polynom_rew = 32'b100000101001;
906 
        13: polynom_rew = 32'b1000000001100;
907 
        14: polynom_rew = 32'b10000000010101;
908 
        15: polynom_rew = 32'b110000000000000;
909 
        16: polynom_rew = 32'b1101000000001000;
910 
        17: polynom_rew = 32'b10010000000000000;
911 
        18: polynom_rew = 32'b100000010000000000;
912 
        19: polynom_rew = 32'b1000000000000100011;
913 
        20: polynom_rew = 32'b10000010000000000000;
914 
        21: polynom_rew = 32'b101000000000000000000;
915 
        22: polynom_rew = 32'b1100000000000000000000;
916 
        23: polynom_rew = 32'b10000100000000000000000;
917 
        24: polynom_rew = 32'b111000010000000000000000;
918 
        25: polynom_rew = 32'b1001000000000000000000000;
919 
        26: polynom_rew = 32'b10000000000000000000100011;
920 
        27: polynom_rew = 32'b100000000000000000000010011;
921 
        28: polynom_rew = 32'b1100100000000000000000000000;
922 
        29: polynom_rew = 32'b10100000000000000000000000000;
923 
        30: polynom_rew = 32'b100000000000000000000000101001;
924 
        31: polynom_rew = 32'b1001000000000000000000000000000;
925 
        32: polynom_rew = 32'b10000000001000000000000000000011;
926 
        default: polynom_rew = 32'b0;
927 
        endcase
928 
        // rotate left
929 
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
930 
        lfsr_fb_rew = qi[length];
931 
        for (i=length-1; i>=1; i=i-1) begin
932 
            if (polynom_rew[i])
933 
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
934 
        end
935 
    end
936 
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
937 
   assign q_next = rew ? q_next_rew : q_next_fw;
938 
   always @ (posedge clk or posedge rst)
939 
     if (rst)
940 
       qi <= {length{1'b0}};
941 
     else
942 
     if (cke)
943 
       qi <= q_next;
944 
    always @ (posedge clk or posedge rst)
945 
    if (rst)
946 
        level1 <= 1'b0;
947 
    else
948 
    if (cke)
949 
    if (q_next == level1_value)
950 
        level1 <= 1'b1;
951 
    else if (qi == level1_value & rew)
952 
        level1 <= 1'b0;
953 
endmodule
954 
//////////////////////////////////////////////////////////////////////
955 
////                                                              ////
956 
////  Versatile counter                                           ////
957 
////                                                              ////
958 
////  Description                                                 ////
959 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
960 
////  counter                                                     ////
961 
////                                                              ////
962 
////  To Do:                                                      ////
963 
////   - add LFSR with more taps                                  ////
964 
////                                                              ////
965 
////  Author(s):                                                  ////
966 
////      - Michael Unneback, unneback@opencores.org              ////
967 
////        ORSoC AB                                              ////
968 
////                                                              ////
969 
//////////////////////////////////////////////////////////////////////
970 
////                                                              ////
971 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
972 
////                                                              ////
973 
//// This source file may be used and distributed without         ////
974 
//// restriction provided that this copyright statement is not    ////
975 
//// removed from the file and that any derivative work contains  ////
976 
//// the original copyright notice and the associated disclaimer. ////
977 
////                                                              ////
978 
//// This source file is free software; you can redistribute it   ////
979 
//// and/or modify it under the terms of the GNU Lesser General   ////
980 
//// Public License as published by the Free Software Foundation; ////
981 
//// either version 2.1 of the License, or (at your option) any   ////
982 
//// later version.                                               ////
983 
////                                                              ////
984 
//// This source is distributed in the hope that it will be       ////
985 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
986 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
987 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
988 
//// details.                                                     ////
989 
////                                                              ////
990 
//// You should have received a copy of the GNU Lesser General    ////
991 
//// Public License along with this source; if not, download it   ////
992 
//// from http://www.opencores.org/lgpl.shtml                     ////
993 
////                                                              ////
994 
//////////////////////////////////////////////////////////////////////
995 
// GRAY counter
996 
module cnt_gray ( q, rst, clk);
997 
   parameter length = 4;
998 
   output reg [length:1] q;
999 
   input rst;
1000 
   input clk;
1001 
   parameter clear_value = 0;
1002 
   parameter set_value = 1;
1003 
   parameter wrap_value = 8;
1004 
   parameter level1_value = 15;
1005 
   reg  [length:1] qi;
1006 
   wire [length:1] q_next;
1007 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1008 
   always @ (posedge clk or posedge rst)
1009 
     if (rst)
1010 
       qi <= {length{1'b0}};
1011 
     else
1012 
       qi <= q_next;
1013 
   always @ (posedge clk or posedge rst)
1014 
     if (rst)
1015 
       q <= {length{1'b0}};
1016 
     else
1017 
         q <= (q_next>>1) ^ q_next;
1018 
endmodule
1019 
//////////////////////////////////////////////////////////////////////
1020 
////                                                              ////
1021 
////  Versatile counter                                           ////
1022 
////                                                              ////
1023 
////  Description                                                 ////
1024 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1025 
////  counter                                                     ////
1026 
////                                                              ////
1027 
////  To Do:                                                      ////
1028 
////   - add LFSR with more taps                                  ////
1029 
////                                                              ////
1030 
////  Author(s):                                                  ////
1031 
////      - Michael Unneback, unneback@opencores.org              ////
1032 
////        ORSoC AB                                              ////
1033 
////                                                              ////
1034 
//////////////////////////////////////////////////////////////////////
1035 
////                                                              ////
1036 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1037 
////                                                              ////
1038 
//// This source file may be used and distributed without         ////
1039 
//// restriction provided that this copyright statement is not    ////
1040 
//// removed from the file and that any derivative work contains  ////
1041 
//// the original