1 |
6 |
unneback |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// Versatile library, clock and reset ////
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4 |
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//// ////
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//// Description ////
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//// Logic related to clock and reset ////
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//// ////
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//// ////
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//// To Do: ////
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//// - add more different registers ////
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//// ////
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//// Author(s): ////
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//// - Michael Unneback, unneback@opencores.org ////
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//// ORSoC AB ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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23 |
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//// the original copyright notice and the associated disclaimer. ////
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24 |
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//// ////
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25 |
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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33 |
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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35 |
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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// Global buffer
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// usage:
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// use to enable global buffers for high fan out signals such as clock and reset
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`timescale 1 ns/100 ps
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// Version: 8.4 8.4.0.33
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module gbuf(GL,CLK);
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output GL;
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input CLK;
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wire GND;
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GND GND_1_net(.Y(GND));
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CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
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.DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
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endmodule
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`timescale 1 ns/1 ns
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module vl_gbuf ( i, o);
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input i;
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output o;
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`ifdef SIM_GBUF
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assign o=i;
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`else
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gbuf gbuf_i0 ( .CLK(i), .GL(o));
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`endif
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endmodule
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//ACTEL
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// sync reset
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// input active lo async reset, normally from external reset generetaor and/or switch
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// output active high global reset sync with two DFFs
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69 |
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`timescale 1 ns/100 ps
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module vl_sync_rst ( rst_n_i, rst_o, clk);
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input rst_n_i, clk;
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output rst_o;
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reg [0:1] tmp;
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always @ (posedge clk or negedge rst_n_i)
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if (!rst_n_i)
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tmp <= 2'b00;
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else
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tmp <= {1'b1,tmp[0]};
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vl_gbuf buf_i0( .i(tmp[1]), .o(rst_o));
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endmodule
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// vl_pll
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`timescale 1 ns/100 ps
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module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
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parameter index = 0;
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parameter number_of_clk = 1;
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parameter period_time_0 = 20;
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parameter period_time_1 = 20;
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parameter period_time_2 = 20;
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parameter lock_delay = 2000;
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input clk_i, rst_n_i;
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output lock;
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output reg [0:number_of_clk-1] clk_o;
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output [0:number_of_clk-1] rst_o;
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`ifdef SIM_PLL
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always
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#((period_time_0)/2) clk_o[0] <= (!rst_n_i) ? 0 : ~clk_o[0];
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generate if (number_of_clk > 1)
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always
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#((period_time_1)/2) clk_o[1] <= (!rst_n_i) ? 0 : ~clk_o[1];
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endgenerate
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generate if (number_of_clk > 2)
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always
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#((period_time_2)/2) clk_o[2] <= (!rst_n_i) ? 0 : ~clk_o[2];
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endgenerate
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genvar i;
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generate for (i=0;i<number_of_clk;i=i+1) begin: clock
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vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
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end
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endgenerate
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assign #lock_delay lock = rst_n_i;
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endmodule
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`else
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generate if (number_of_clk==1 & index==0) begin
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pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
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end
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endgenerate // index==0
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generate if (number_of_clk==1 & index==1) begin
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pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
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end
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endgenerate // index==1
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generate if (number_of_clk==1 & index==2) begin
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pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
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end
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endgenerate // index==2
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generate if (number_of_clk==1 & index==3) begin
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pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
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end
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endgenerate // index==0
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generate if (number_of_clk==2 & index==0) begin
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pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
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end
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132 |
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endgenerate // index==0
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generate if (number_of_clk==2 & index==1) begin
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pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
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135 |
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end
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136 |
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endgenerate // index==1
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137 |
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generate if (number_of_clk==2 & index==2) begin
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138 |
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pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
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end
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140 |
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endgenerate // index==2
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generate if (number_of_clk==2 & index==3) begin
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pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
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end
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endgenerate // index==0
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generate if (number_of_clk==3 & index==0) begin
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pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
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end
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148 |
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endgenerate // index==0
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149 |
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generate if (number_of_clk==3 & index==1) begin
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150 |
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pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
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end
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152 |
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endgenerate // index==1
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generate if (number_of_clk==3 & index==2) begin
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pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
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end
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156 |
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endgenerate // index==2
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generate if (number_of_clk==3 & index==3) begin
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158 |
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pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
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end
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160 |
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endgenerate // index==0
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161 |
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genvar i;
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162 |
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generate for (i=0;i<number_of_clk;i=i+1) begin: clock
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163 |
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vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
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end
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165 |
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endgenerate
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166 |
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endmodule
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`endif
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//actel
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//////////////////////////////////////////////////////////////////////
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170 |
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//// ////
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171 |
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//// Versatile library, registers ////
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172 |
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//// ////
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173 |
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//// Description ////
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174 |
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//// Different type of registers ////
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175 |
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//// ////
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176 |
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//// ////
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177 |
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//// To Do: ////
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178 |
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//// - add more different registers ////
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179 |
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//// ////
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180 |
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//// Author(s): ////
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181 |
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//// - Michael Unneback, unneback@opencores.org ////
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182 |
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//// ORSoC AB ////
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183 |
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//// ////
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184 |
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//////////////////////////////////////////////////////////////////////
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185 |
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//// ////
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186 |
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//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
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187 |
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//// ////
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188 |
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//// This source file may be used and distributed without ////
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189 |
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//// restriction provided that this copyright statement is not ////
|
190 |
|
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//// removed from the file and that any derivative work contains ////
|
191 |
|
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//// the original copyright notice and the associated disclaimer. ////
|
192 |
|
|
//// ////
|
193 |
|
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//// This source file is free software; you can redistribute it ////
|
194 |
|
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//// and/or modify it under the terms of the GNU Lesser General ////
|
195 |
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//// Public License as published by the Free Software Foundation; ////
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196 |
|
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//// either version 2.1 of the License, or (at your option) any ////
|
197 |
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//// later version. ////
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198 |
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//// ////
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199 |
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//// This source is distributed in the hope that it will be ////
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200 |
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
201 |
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
202 |
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//// PURPOSE. See the GNU Lesser General Public License for more ////
|
203 |
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//// details. ////
|
204 |
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//// ////
|
205 |
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//// You should have received a copy of the GNU Lesser General ////
|
206 |
|
|
//// Public License along with this source; if not, download it ////
|
207 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
208 |
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//// ////
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209 |
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//////////////////////////////////////////////////////////////////////
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210 |
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module dff ( d, q, clk, rst);
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211 |
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parameter width = 1;
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212 |
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parameter reset_value = 0;
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213 |
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input [width-1:0] d;
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214 |
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input clk, rst;
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215 |
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output reg [width-1:0] q;
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216 |
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always @ (posedge clk or posedge rst)
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217 |
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if (rst)
|
218 |
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q <= reset_value;
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219 |
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else
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220 |
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q <= d;
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221 |
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endmodule
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222 |
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module dff_array ( d, q, clk, rst);
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223 |
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parameter width = 1;
|
224 |
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parameter depth = 2;
|
225 |
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parameter reset_value = 1'b0;
|
226 |
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input [width-1:0] d;
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227 |
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input clk, rst;
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228 |
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output [width-1:0] q;
|
229 |
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reg [0:depth-1] q_tmp [width-1:0];
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230 |
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integer i;
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231 |
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always @ (posedge clk or posedge rst)
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232 |
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if (rst) begin
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233 |
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for (i=0;i<depth;i=i+1)
|
234 |
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q_tmp[i] <= {width{reset_value}};
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235 |
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end else begin
|
236 |
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q_tmp[0] <= d;
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237 |
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for (i=1;i<depth;i=i+1)
|
238 |
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q_tmp[i] <= q_tmp[i-1];
|
239 |
|
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end
|
240 |
|
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assign q = q_tmp[depth-1];
|
241 |
|
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endmodule
|
242 |
|
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module dff_ce ( d, ce, q, clk, rst);
|
243 |
|
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parameter width = 1;
|
244 |
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parameter reset_value = 0;
|
245 |
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input [width-1:0] d;
|
246 |
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input ce, clk, rst;
|
247 |
|
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output reg [width-1:0] q;
|
248 |
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always @ (posedge clk or posedge rst)
|
249 |
|
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if (rst)
|
250 |
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q <= reset_value;
|
251 |
|
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else
|
252 |
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if (ce)
|
253 |
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q <= d;
|
254 |
|
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endmodule
|
255 |
8 |
unneback |
module dff_ce_clear ( d, ce, clear, q, clk, rst);
|
256 |
|
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parameter width = 1;
|
257 |
|
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parameter reset_value = 0;
|
258 |
|
|
input [width-1:0] d;
|
259 |
10 |
unneback |
input ce, clear, clk, rst;
|
260 |
8 |
unneback |
output reg [width-1:0] q;
|
261 |
|
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always @ (posedge clk or posedge rst)
|
262 |
|
|
if (rst)
|
263 |
|
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q <= reset_value;
|
264 |
|
|
else
|
265 |
|
|
if (ce)
|
266 |
|
|
if (clear)
|
267 |
|
|
q <= {width{1'b0}};
|
268 |
|
|
else
|
269 |
|
|
q <= d;
|
270 |
|
|
endmodule
|
271 |
6 |
unneback |
module dff_sr ( aclr, aset, clock, data, q);
|
272 |
|
|
input aclr;
|
273 |
|
|
input aset;
|
274 |
|
|
input clock;
|
275 |
|
|
input data;
|
276 |
|
|
output reg q;
|
277 |
|
|
always @ (posedge clock or posedge aclr or posedge aset)
|
278 |
|
|
if (aclr)
|
279 |
|
|
q <= 1'b0;
|
280 |
|
|
else if (aset)
|
281 |
|
|
q <= 1'b1;
|
282 |
|
|
else
|
283 |
|
|
q <= data;
|
284 |
|
|
endmodule
|
285 |
|
|
// LATCH
|
286 |
|
|
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
|
287 |
|
|
module latch ( d, le, q, clk);
|
288 |
|
|
input d, le;
|
289 |
|
|
output q;
|
290 |
|
|
input clk;/*
|
291 |
|
|
always @ (posedge direction_set or posedge direction_clr)
|
292 |
|
|
if (direction_clr)
|
293 |
|
|
direction <= going_empty;
|
294 |
|
|
else
|
295 |
|
|
direction <= going_full;*/
|
296 |
|
|
endmodule
|
297 |
|
|
//////////////////////////////////////////////////////////////////////
|
298 |
|
|
//// ////
|
299 |
|
|
//// Versatile counter ////
|
300 |
|
|
//// ////
|
301 |
|
|
//// Description ////
|
302 |
|
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
303 |
|
|
//// counter ////
|
304 |
|
|
//// ////
|
305 |
|
|
//// To Do: ////
|
306 |
|
|
//// - add LFSR with more taps ////
|
307 |
|
|
//// ////
|
308 |
|
|
//// Author(s): ////
|
309 |
|
|
//// - Michael Unneback, unneback@opencores.org ////
|
310 |
|
|
//// ORSoC AB ////
|
311 |
|
|
//// ////
|
312 |
|
|
//////////////////////////////////////////////////////////////////////
|
313 |
|
|
//// ////
|
314 |
|
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
315 |
|
|
//// ////
|
316 |
|
|
//// This source file may be used and distributed without ////
|
317 |
|
|
//// restriction provided that this copyright statement is not ////
|
318 |
|
|
//// removed from the file and that any derivative work contains ////
|
319 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
320 |
|
|
//// ////
|
321 |
|
|
//// This source file is free software; you can redistribute it ////
|
322 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
323 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
324 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
325 |
|
|
//// later version. ////
|
326 |
|
|
//// ////
|
327 |
|
|
//// This source is distributed in the hope that it will be ////
|
328 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
329 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
330 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
331 |
|
|
//// details. ////
|
332 |
|
|
//// ////
|
333 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
334 |
|
|
//// Public License along with this source; if not, download it ////
|
335 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
336 |
|
|
//// ////
|
337 |
|
|
//////////////////////////////////////////////////////////////////////
|
338 |
|
|
// binary counter
|
339 |
|
|
module cnt_bin_ce ( cke, q, rst, clk);
|
340 |
|
|
parameter length = 4;
|
341 |
|
|
input cke;
|
342 |
|
|
output [length:1] q;
|
343 |
|
|
input rst;
|
344 |
|
|
input clk;
|
345 |
|
|
parameter clear_value = 0;
|
346 |
|
|
parameter set_value = 1;
|
347 |
|
|
parameter wrap_value = 0;
|
348 |
|
|
parameter level1_value = 15;
|
349 |
|
|
reg [length:1] qi;
|
350 |
|
|
wire [length:1] q_next;
|
351 |
|
|
assign q_next = qi + {{length-1{1'b0}},1'b1};
|
352 |
|
|
always @ (posedge clk or posedge rst)
|
353 |
|
|
if (rst)
|
354 |
|
|
qi <= {length{1'b0}};
|
355 |
|
|
else
|
356 |
|
|
if (cke)
|
357 |
|
|
qi <= q_next;
|
358 |
|
|
assign q = qi;
|
359 |
|
|
endmodule
|
360 |
|
|
//////////////////////////////////////////////////////////////////////
|
361 |
|
|
//// ////
|
362 |
|
|
//// Versatile counter ////
|
363 |
|
|
//// ////
|
364 |
|
|
//// Description ////
|
365 |
|
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
366 |
|
|
//// counter ////
|
367 |
|
|
//// ////
|
368 |
|
|
//// To Do: ////
|
369 |
|
|
//// - add LFSR with more taps ////
|
370 |
|
|
//// ////
|
371 |
|
|
//// Author(s): ////
|
372 |
|
|
//// - Michael Unneback, unneback@opencores.org ////
|
373 |
|
|
//// ORSoC AB ////
|
374 |
|
|
//// ////
|
375 |
|
|
//////////////////////////////////////////////////////////////////////
|
376 |
|
|
//// ////
|
377 |
|
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
378 |
|
|
//// ////
|
379 |
|
|
//// This source file may be used and distributed without ////
|
380 |
|
|
//// restriction provided that this copyright statement is not ////
|
381 |
|
|
//// removed from the file and that any derivative work contains ////
|
382 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
383 |
|
|
//// ////
|
384 |
|
|
//// This source file is free software; you can redistribute it ////
|
385 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
386 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
387 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
388 |
|
|
//// later version. ////
|
389 |
|
|
//// ////
|
390 |
|
|
//// This source is distributed in the hope that it will be ////
|
391 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
392 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
393 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
394 |
|
|
//// details. ////
|
395 |
|
|
//// ////
|
396 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
397 |
|
|
//// Public License along with this source; if not, download it ////
|
398 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
399 |
|
|
//// ////
|
400 |
|
|
//////////////////////////////////////////////////////////////////////
|
401 |
|
|
// binary counter
|
402 |
|
|
module cnt_bin_ce_clear ( clear, cke, q, rst, clk);
|
403 |
|
|
parameter length = 4;
|
404 |
|
|
input clear;
|
405 |
|
|
input cke;
|
406 |
|
|
output [length:1] q;
|
407 |
|
|
input rst;
|
408 |
|
|
input clk;
|
409 |
|
|
parameter clear_value = 0;
|
410 |
|
|
parameter set_value = 1;
|
411 |
|
|
parameter wrap_value = 0;
|
412 |
|
|
parameter level1_value = 15;
|
413 |
|
|
reg [length:1] qi;
|
414 |
|
|
wire [length:1] q_next;
|
415 |
|
|
assign q_next = clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
|
416 |
|
|
always @ (posedge clk or posedge rst)
|
417 |
|
|
if (rst)
|
418 |
|
|
qi <= {length{1'b0}};
|
419 |
|
|
else
|
420 |
|
|
if (cke)
|
421 |
|
|
qi <= q_next;
|
422 |
|
|
assign q = qi;
|
423 |
|
|
endmodule
|
424 |
|
|
//////////////////////////////////////////////////////////////////////
|
425 |
|
|
//// ////
|
426 |
|
|
//// Versatile counter ////
|
427 |
|
|
//// ////
|
428 |
|
|
//// Description ////
|
429 |
|
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
430 |
|
|
//// counter ////
|
431 |
|
|
//// ////
|
432 |
|
|
//// To Do: ////
|
433 |
|
|
//// - add LFSR with more taps ////
|
434 |
|
|
//// ////
|
435 |
|
|
//// Author(s): ////
|
436 |
|
|
//// - Michael Unneback, unneback@opencores.org ////
|
437 |
|
|
//// ORSoC AB ////
|
438 |
|
|
//// ////
|
439 |
|
|
//////////////////////////////////////////////////////////////////////
|
440 |
|
|
//// ////
|
441 |
|
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
442 |
|
|
//// ////
|
443 |
|
|
//// This source file may be used and distributed without ////
|
444 |
|
|
//// restriction provided that this copyright statement is not ////
|
445 |
|
|
//// removed from the file and that any derivative work contains ////
|
446 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
447 |
|
|
//// ////
|
448 |
|
|
//// This source file is free software; you can redistribute it ////
|
449 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
450 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
451 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
452 |
|
|
//// later version. ////
|
453 |
|
|
//// ////
|
454 |
|
|
//// This source is distributed in the hope that it will be ////
|
455 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
456 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
457 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
458 |
|
|
//// details. ////
|
459 |
|
|
//// ////
|
460 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
461 |
|
|
//// Public License along with this source; if not, download it ////
|
462 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
463 |
|
|
//// ////
|
464 |
|
|
//////////////////////////////////////////////////////////////////////
|
465 |
|
|
// binary counter
|
466 |
|
|
module cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk);
|
467 |
|
|
parameter length = 4;
|
468 |
|
|
input clear;
|
469 |
|
|
input set;
|
470 |
|
|
input cke;
|
471 |
|
|
input rew;
|
472 |
|
|
output [length:1] q;
|
473 |
|
|
input rst;
|
474 |
|
|
input clk;
|
475 |
|
|
parameter clear_value = 0;
|
476 |
|
|
parameter set_value = 1;
|
477 |
|
|
parameter wrap_value = 0;
|
478 |
|
|
parameter level1_value = 15;
|
479 |
|
|
reg [length:1] qi;
|
480 |
|
|
wire [length:1] q_next, q_next_fw, q_next_rew;
|
481 |
|
|
assign q_next_fw = clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
|
482 |
|
|
assign q_next_rew = clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
|
483 |
|
|
assign q_next = rew ? q_next_rew : q_next_fw;
|
484 |
|
|
always @ (posedge clk or posedge rst)
|
485 |
|
|
if (rst)
|
486 |
|
|
qi <= {length{1'b0}};
|
487 |
|
|
else
|
488 |
|
|
if (cke)
|
489 |
|
|
qi <= q_next;
|
490 |
|
|
assign q = qi;
|
491 |
|
|
endmodule
|
492 |
|
|
//////////////////////////////////////////////////////////////////////
|
493 |
|
|
//// ////
|
494 |
|
|
//// Versatile counter ////
|
495 |
|
|
//// ////
|
496 |
|
|
//// Description ////
|
497 |
|
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
498 |
|
|
//// counter ////
|
499 |
|
|
//// ////
|
500 |
|
|
//// To Do: ////
|
501 |
|
|
//// - add LFSR with more taps ////
|
502 |
|
|
//// ////
|
503 |
|
|
//// Author(s): ////
|
504 |
|
|
//// - Michael Unneback, unneback@opencores.org ////
|
505 |
|
|
//// ORSoC AB ////
|
506 |
|
|
//// ////
|
507 |
|
|
//////////////////////////////////////////////////////////////////////
|
508 |
|
|
//// ////
|
509 |
|
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
510 |
|
|
//// ////
|
511 |
|
|
//// This source file may be used and distributed without ////
|
512 |
|
|
//// restriction provided that this copyright statement is not ////
|
513 |
|
|
//// removed from the file and that any derivative work contains ////
|
514 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
515 |
|
|
//// ////
|
516 |
|
|
//// This source file is free software; you can redistribute it ////
|
517 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
518 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
519 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
520 |
|
|
//// later version. ////
|
521 |
|
|
//// ////
|
522 |
|
|
//// This source is distributed in the hope that it will be ////
|
523 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
524 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
525 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
526 |
|
|
//// details. ////
|
527 |
|
|
//// ////
|
528 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
529 |
|
|
//// Public License along with this source; if not, download it ////
|
530 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
531 |
|
|
//// ////
|
532 |
|
|
//////////////////////////////////////////////////////////////////////
|
533 |
|
|
// binary counter
|
534 |
|
|
module cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk);
|
535 |
|
|
parameter length = 4;
|
536 |
|
|
input cke;
|
537 |
|
|
input rew;
|
538 |
|
|
output reg level1;
|
539 |
|
|
input rst;
|
540 |
|
|
input clk;
|
541 |
|
|
parameter clear_value = 0;
|
542 |
|
|
parameter set_value = 1;
|
543 |
|
|
parameter wrap_value = 1;
|
544 |
|
|
parameter level1_value = 15;
|
545 |
|
|
reg [length:1] qi;
|
546 |
|
|
wire [length:1] q_next, q_next_fw, q_next_rew;
|
547 |
|
|
assign q_next_fw = qi + {{length-1{1'b0}},1'b1};
|
548 |
|
|
assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
|
549 |
|
|
assign q_next = rew ? q_next_rew : q_next_fw;
|
550 |
|
|
always @ (posedge clk or posedge rst)
|
551 |
|
|
if (rst)
|
552 |
|
|
qi <= {length{1'b0}};
|
553 |
|
|
else
|
554 |
|
|
if (cke)
|
555 |
|
|
qi <= q_next;
|
556 |
|
|
always @ (posedge clk or posedge rst)
|
557 |
|
|
if (rst)
|
558 |
|
|
level1 <= 1'b0;
|
559 |
|
|
else
|
560 |
|
|
if (cke)
|
561 |
|
|
if (q_next == level1_value)
|
562 |
|
|
level1 <= 1'b1;
|
563 |
|
|
else if (qi == level1_value & rew)
|
564 |
|
|
level1 <= 1'b0;
|
565 |
|
|
endmodule
|
566 |
|
|
//////////////////////////////////////////////////////////////////////
|
567 |
|
|
//// ////
|
568 |
|
|
//// Versatile counter ////
|
569 |
|
|
//// ////
|
570 |
|
|
//// Description ////
|
571 |
|
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
572 |
|
|
//// counter ////
|
573 |
|
|
//// ////
|
574 |
|
|
//// To Do: ////
|
575 |
|
|
//// - add LFSR with more taps ////
|
576 |
|
|
//// ////
|
577 |
|
|
//// Author(s): ////
|
578 |
|
|
//// - Michael Unneback, unneback@opencores.org ////
|
579 |
|
|
//// ORSoC AB ////
|
580 |
|
|
//// ////
|
581 |
|
|
//////////////////////////////////////////////////////////////////////
|
582 |
|
|
//// ////
|
583 |
|
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
584 |
|
|
//// ////
|
585 |
|
|
//// This source file may be used and distributed without ////
|
586 |
|
|
//// restriction provided that this copyright statement is not ////
|
587 |
|
|
//// removed from the file and that any derivative work contains ////
|
588 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
589 |
|
|
//// ////
|
590 |
|
|
//// This source file is free software; you can redistribute it ////
|
591 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
592 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
593 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
594 |
|
|
//// later version. ////
|
595 |
|
|
//// ////
|
596 |
|
|
//// This source is distributed in the hope that it will be ////
|
597 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
598 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
599 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
600 |
|
|
//// details. ////
|
601 |
|
|
//// ////
|
602 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
603 |
|
|
//// Public License along with this source; if not, download it ////
|
604 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
605 |
|
|
//// ////
|
606 |
|
|
//////////////////////////////////////////////////////////////////////
|
607 |
|
|
// LFSR counter
|
608 |
|
|
module cnt_lfsr_zq ( zq, rst, clk);
|
609 |
|
|
parameter length = 4;
|
610 |
|
|
output reg zq;
|
611 |
|
|
input rst;
|
612 |
|
|
input clk;
|
613 |
|
|
parameter clear_value = 0;
|
614 |
|
|
parameter set_value = 1;
|
615 |
|
|
parameter wrap_value = 8;
|
616 |
|
|
parameter level1_value = 15;
|
617 |
|
|
reg [length:1] qi;
|
618 |
|
|
reg lfsr_fb;
|
619 |
|
|
wire [length:1] q_next;
|
620 |
|
|
reg [32:1] polynom;
|
621 |
|
|
integer i;
|
622 |
|
|
always @ (qi)
|
623 |
|
|
begin
|
624 |
|
|
case (length)
|
625 |
|
|
2: polynom = 32'b11; // 0x3
|
626 |
|
|
3: polynom = 32'b110; // 0x6
|
627 |
|
|
4: polynom = 32'b1100; // 0xC
|
628 |
|
|
5: polynom = 32'b10100; // 0x14
|
629 |
|
|
6: polynom = 32'b110000; // 0x30
|
630 |
|
|
7: polynom = 32'b1100000; // 0x60
|
631 |
|
|
8: polynom = 32'b10111000; // 0xb8
|
632 |
|
|
9: polynom = 32'b100010000; // 0x110
|
633 |
|
|
10: polynom = 32'b1001000000; // 0x240
|
634 |
|
|
11: polynom = 32'b10100000000; // 0x500
|
635 |
|
|
12: polynom = 32'b100000101001; // 0x829
|
636 |
|
|
13: polynom = 32'b1000000001100; // 0x100C
|
637 |
|
|
14: polynom = 32'b10000000010101; // 0x2015
|
638 |
|
|
15: polynom = 32'b110000000000000; // 0x6000
|
639 |
|
|
16: polynom = 32'b1101000000001000; // 0xD008
|
640 |
|
|
17: polynom = 32'b10010000000000000; // 0x12000
|
641 |
|
|
18: polynom = 32'b100000010000000000; // 0x20400
|
642 |
|
|
19: polynom = 32'b1000000000000100011; // 0x40023
|
643 |
|
|
20: polynom = 32'b10000010000000000000; // 0x82000
|
644 |
|
|
21: polynom = 32'b101000000000000000000; // 0x140000
|
645 |
|
|
22: polynom = 32'b1100000000000000000000; // 0x300000
|
646 |
|
|
23: polynom = 32'b10000100000000000000000; // 0x420000
|
647 |
|
|
24: polynom = 32'b111000010000000000000000; // 0xE10000
|
648 |
|
|
25: polynom = 32'b1001000000000000000000000; // 0x1200000
|
649 |
|
|
26: polynom = 32'b10000000000000000000100011; // 0x2000023
|
650 |
|
|
27: polynom = 32'b100000000000000000000010011; // 0x4000013
|
651 |
|
|
28: polynom = 32'b1100100000000000000000000000; // 0xC800000
|
652 |
|
|
29: polynom = 32'b10100000000000000000000000000; // 0x14000000
|
653 |
|
|
30: polynom = 32'b100000000000000000000000101001; // 0x20000029
|
654 |
|
|
31: polynom = 32'b1001000000000000000000000000000; // 0x48000000
|
655 |
|
|
32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
|
656 |
|
|
default: polynom = 32'b0;
|
657 |
|
|
endcase
|
658 |
|
|
lfsr_fb = qi[length];
|
659 |
|
|
for (i=length-1; i>=1; i=i-1) begin
|
660 |
|
|
if (polynom[i])
|
661 |
|
|
lfsr_fb = lfsr_fb ~^ qi[i];
|
662 |
|
|
end
|
663 |
|
|
end
|
664 |
|
|
assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
|
665 |
|
|
always @ (posedge clk or posedge rst)
|
666 |
|
|
if (rst)
|
667 |
|
|
qi <= {length{1'b0}};
|
668 |
|
|
else
|
669 |
|
|
qi <= q_next;
|
670 |
|
|
always @ (posedge clk or posedge rst)
|
671 |
|
|
if (rst)
|
672 |
|
|
zq <= 1'b1;
|
673 |
|
|
else
|
674 |
|
|
zq <= q_next == {length{1'b0}};
|
675 |
|
|
endmodule
|
676 |
|
|
//////////////////////////////////////////////////////////////////////
|
677 |
|
|
//// ////
|
678 |
|
|
//// Versatile counter ////
|
679 |
|
|
//// ////
|
680 |
|
|
//// Description ////
|
681 |
|
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
682 |
|
|
//// counter ////
|
683 |
|
|
//// ////
|
684 |
|
|
//// To Do: ////
|
685 |
|
|
//// - add LFSR with more taps ////
|
686 |
|
|
//// ////
|
687 |
|
|
//// Author(s): ////
|
688 |
|
|
//// - Michael Unneback, unneback@opencores.org ////
|
689 |
|
|
//// ORSoC AB ////
|
690 |
|
|
//// ////
|
691 |
|
|
//////////////////////////////////////////////////////////////////////
|
692 |
|
|
//// ////
|
693 |
|
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
694 |
|
|
//// ////
|
695 |
|
|
//// This source file may be used and distributed without ////
|
696 |
|
|
//// restriction provided that this copyright statement is not ////
|
697 |
|
|
//// removed from the file and that any derivative work contains ////
|
698 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
699 |
|
|
//// ////
|
700 |
|
|
//// This source file is free software; you can redistribute it ////
|
701 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
702 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
703 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
704 |
|
|
//// later version. ////
|
705 |
|
|
//// ////
|
706 |
|
|
//// This source is distributed in the hope that it will be ////
|
707 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
708 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
709 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
710 |
|
|
//// details. ////
|
711 |
|
|
//// ////
|
712 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
713 |
|
|
//// Public License along with this source; if not, download it ////
|
714 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
715 |
|
|
//// ////
|
716 |
|
|
//////////////////////////////////////////////////////////////////////
|
717 |
|
|
// LFSR counter
|
718 |
|
|
module cnt_lfsr_ce_zq ( cke, zq, rst, clk);
|
719 |
|
|
parameter length = 4;
|
720 |
|
|
input cke;
|
721 |
|
|
output reg zq;
|
722 |
|
|
input rst;
|
723 |
|
|
input clk;
|
724 |
|
|
parameter clear_value = 0;
|
725 |
|
|
parameter set_value = 1;
|
726 |
|
|
parameter wrap_value = 8;
|
727 |
|
|
parameter level1_value = 15;
|
728 |
|
|
reg [length:1] qi;
|
729 |
|
|
reg lfsr_fb;
|
730 |
|
|
wire [length:1] q_next;
|
731 |
|
|
reg [32:1] polynom;
|
732 |
|
|
integer i;
|
733 |
|
|
always @ (qi)
|
734 |
|
|
begin
|
735 |
|
|
case (length)
|
736 |
|
|
2: polynom = 32'b11; // 0x3
|
737 |
|
|
3: polynom = 32'b110; // 0x6
|
738 |
|
|
4: polynom = 32'b1100; // 0xC
|
739 |
|
|
5: polynom = 32'b10100; // 0x14
|
740 |
|
|
6: polynom = 32'b110000; // 0x30
|
741 |
|
|
7: polynom = 32'b1100000; // 0x60
|
742 |
|
|
8: polynom = 32'b10111000; // 0xb8
|
743 |
|
|
9: polynom = 32'b100010000; // 0x110
|
744 |
|
|
10: polynom = 32'b1001000000; // 0x240
|
745 |
|
|
11: polynom = 32'b10100000000; // 0x500
|
746 |
|
|
12: polynom = 32'b100000101001; // 0x829
|
747 |
|
|
13: polynom = 32'b1000000001100; // 0x100C
|
748 |
|
|
14: polynom = 32'b10000000010101; // 0x2015
|
749 |
|
|
15: polynom = 32'b110000000000000; // 0x6000
|
750 |
|
|
16: polynom = 32'b1101000000001000; // 0xD008
|
751 |
|
|
17: polynom = 32'b10010000000000000; // 0x12000
|
752 |
|
|
18: polynom = 32'b100000010000000000; // 0x20400
|
753 |
|
|
19: polynom = 32'b1000000000000100011; // 0x40023
|
754 |
|
|
20: polynom = 32'b10000010000000000000; // 0x82000
|
755 |
|
|
21: polynom = 32'b101000000000000000000; // 0x140000
|
756 |
|
|
22: polynom = 32'b1100000000000000000000; // 0x300000
|
757 |
|
|
23: polynom = 32'b10000100000000000000000; // 0x420000
|
758 |
|
|
24: polynom = 32'b111000010000000000000000; // 0xE10000
|
759 |
|
|
25: polynom = 32'b1001000000000000000000000; // 0x1200000
|
760 |
|
|
26: polynom = 32'b10000000000000000000100011; // 0x2000023
|
761 |
|
|
27: polynom = 32'b100000000000000000000010011; // 0x4000013
|
762 |
|
|
28: polynom = 32'b1100100000000000000000000000; // 0xC800000
|
763 |
|
|
29: polynom = 32'b10100000000000000000000000000; // 0x14000000
|
764 |
|
|
30: polynom = 32'b100000000000000000000000101001; // 0x20000029
|
765 |
|
|
31: polynom = 32'b1001000000000000000000000000000; // 0x48000000
|
766 |
|
|
32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
|
767 |
|
|
default: polynom = 32'b0;
|
768 |
|
|
endcase
|
769 |
|
|
lfsr_fb = qi[length];
|
770 |
|
|
for (i=length-1; i>=1; i=i-1) begin
|
771 |
|
|
if (polynom[i])
|
772 |
|
|
lfsr_fb = lfsr_fb ~^ qi[i];
|
773 |
|
|
end
|
774 |
|
|
end
|
775 |
|
|
assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
|
776 |
|
|
always @ (posedge clk or posedge rst)
|
777 |
|
|
if (rst)
|
778 |
|
|
qi <= {length{1'b0}};
|
779 |
|
|
else
|
780 |
|
|
if (cke)
|
781 |
|
|
qi <= q_next;
|
782 |
|
|
always @ (posedge clk or posedge rst)
|
783 |
|
|
if (rst)
|
784 |
|
|
zq <= 1'b1;
|
785 |
|
|
else
|
786 |
|
|
if (cke)
|
787 |
|
|
zq <= q_next == {length{1'b0}};
|
788 |
|
|
endmodule
|
789 |
|
|
//////////////////////////////////////////////////////////////////////
|
790 |
|
|
//// ////
|
791 |
|
|
//// Versatile counter ////
|
792 |
|
|
//// ////
|
793 |
|
|
//// Description ////
|
794 |
|
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
795 |
|
|
//// counter ////
|
796 |
|
|
//// ////
|
797 |
|
|
//// To Do: ////
|
798 |
|
|
//// - add LFSR with more taps ////
|
799 |
|
|
//// ////
|
800 |
|
|
//// Author(s): ////
|
801 |
|
|
//// - Michael Unneback, unneback@opencores.org ////
|
802 |
|
|
//// ORSoC AB ////
|
803 |
|
|
//// ////
|
804 |
|
|
//////////////////////////////////////////////////////////////////////
|
805 |
|
|
//// ////
|
806 |
|
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
807 |
|
|
//// ////
|
808 |
|
|
//// This source file may be used and distributed without ////
|
809 |
|
|
//// restriction provided that this copyright statement is not ////
|
810 |
|
|
//// removed from the file and that any derivative work contains ////
|
811 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
812 |
|
|
//// ////
|
813 |
|
|
//// This source file is free software; you can redistribute it ////
|
814 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
815 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
816 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
817 |
|
|
//// later version. ////
|
818 |
|
|
//// ////
|
819 |
|
|
//// This source is distributed in the hope that it will be ////
|
820 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
821 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
822 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
823 |
|
|
//// details. ////
|
824 |
|
|
//// ////
|
825 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
826 |
|
|
//// Public License along with this source; if not, download it ////
|
827 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
828 |
|
|
//// ////
|
829 |
|
|
//////////////////////////////////////////////////////////////////////
|
830 |
|
|
// LFSR counter
|
831 |
|
|
module cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk);
|
832 |
|
|
parameter length = 4;
|
833 |
|
|
input cke;
|
834 |
|
|
input rew;
|
835 |
|
|
output reg level1;
|
836 |
|
|
input rst;
|
837 |
|
|
input clk;
|
838 |
|
|
parameter clear_value = 0;
|
839 |
|
|
parameter set_value = 1;
|
840 |
|
|
parameter wrap_value = 8;
|
841 |
|
|
parameter level1_value = 15;
|
842 |
|
|
reg [length:1] qi;
|
843 |
|
|
reg lfsr_fb, lfsr_fb_rew;
|
844 |
|
|
wire [length:1] q_next, q_next_fw, q_next_rew;
|
845 |
|
|
reg [32:1] polynom_rew;
|
846 |
|
|
integer j;
|
847 |
|
|
reg [32:1] polynom;
|
848 |
|
|
integer i;
|
849 |
|
|
always @ (qi)
|
850 |
|
|
begin
|
851 |
|
|
case (length)
|
852 |
|
|
2: polynom = 32'b11; // 0x3
|
853 |
|
|
3: polynom = 32'b110; // 0x6
|
854 |
|
|
4: polynom = 32'b1100; // 0xC
|
855 |
|
|
5: polynom = 32'b10100; // 0x14
|
856 |
|
|
6: polynom = 32'b110000; // 0x30
|
857 |
|
|
7: polynom = 32'b1100000; // 0x60
|
858 |
|
|
8: polynom = 32'b10111000; // 0xb8
|
859 |
|
|
9: polynom = 32'b100010000; // 0x110
|
860 |
|
|
10: polynom = 32'b1001000000; // 0x240
|
861 |
|
|
11: polynom = 32'b10100000000; // 0x500
|
862 |
|
|
12: polynom = 32'b100000101001; // 0x829
|
863 |
|
|
13: polynom = 32'b1000000001100; // 0x100C
|
864 |
|
|
14: polynom = 32'b10000000010101; // 0x2015
|
865 |
|
|
15: polynom = 32'b110000000000000; // 0x6000
|
866 |
|
|
16: polynom = 32'b1101000000001000; // 0xD008
|
867 |
|
|
17: polynom = 32'b10010000000000000; // 0x12000
|
868 |
|
|
18: polynom = 32'b100000010000000000; // 0x20400
|
869 |
|
|
19: polynom = 32'b1000000000000100011; // 0x40023
|
870 |
|
|
20: polynom = 32'b10000010000000000000; // 0x82000
|
871 |
|
|
21: polynom = 32'b101000000000000000000; // 0x140000
|
872 |
|
|
22: polynom = 32'b1100000000000000000000; // 0x300000
|
873 |
|
|
23: polynom = 32'b10000100000000000000000; // 0x420000
|
874 |
|
|
24: polynom = 32'b111000010000000000000000; // 0xE10000
|
875 |
|
|
25: polynom = 32'b1001000000000000000000000; // 0x1200000
|
876 |
|
|
26: polynom = 32'b10000000000000000000100011; // 0x2000023
|
877 |
|
|
27: polynom = 32'b100000000000000000000010011; // 0x4000013
|
878 |
|
|
28: polynom = 32'b1100100000000000000000000000; // 0xC800000
|
879 |
|
|
29: polynom = 32'b10100000000000000000000000000; // 0x14000000
|
880 |
|
|
30: polynom = 32'b100000000000000000000000101001; // 0x20000029
|
881 |
|
|
31: polynom = 32'b1001000000000000000000000000000; // 0x48000000
|
882 |
|
|
32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
|
883 |
|
|
default: polynom = 32'b0;
|
884 |
|
|
endcase
|
885 |
|
|
lfsr_fb = qi[length];
|
886 |
|
|
for (i=length-1; i>=1; i=i-1) begin
|
887 |
|
|
if (polynom[i])
|
888 |
|
|
lfsr_fb = lfsr_fb ~^ qi[i];
|
889 |
|
|
end
|
890 |
|
|
end
|
891 |
|
|
assign q_next_fw = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
|
892 |
|
|
always @ (qi)
|
893 |
|
|
begin
|
894 |
|
|
case (length)
|
895 |
|
|
2: polynom_rew = 32'b11;
|
896 |
|
|
3: polynom_rew = 32'b110;
|
897 |
|
|
4: polynom_rew = 32'b1100;
|
898 |
|
|
5: polynom_rew = 32'b10100;
|
899 |
|
|
6: polynom_rew = 32'b110000;
|
900 |
|
|
7: polynom_rew = 32'b1100000;
|
901 |
|
|
8: polynom_rew = 32'b10111000;
|
902 |
|
|
9: polynom_rew = 32'b100010000;
|
903 |
|
|
10: polynom_rew = 32'b1001000000;
|
904 |
|
|
11: polynom_rew = 32'b10100000000;
|
905 |
|
|
12: polynom_rew = 32'b100000101001;
|
906 |
|
|
13: polynom_rew = 32'b1000000001100;
|
907 |
|
|
14: polynom_rew = 32'b10000000010101;
|
908 |
|
|
15: polynom_rew = 32'b110000000000000;
|
909 |
|
|
16: polynom_rew = 32'b1101000000001000;
|
910 |
|
|
17: polynom_rew = 32'b10010000000000000;
|
911 |
|
|
18: polynom_rew = 32'b100000010000000000;
|
912 |
|
|
19: polynom_rew = 32'b1000000000000100011;
|
913 |
|
|
20: polynom_rew = 32'b10000010000000000000;
|
914 |
|
|
21: polynom_rew = 32'b101000000000000000000;
|
915 |
|
|
22: polynom_rew = 32'b1100000000000000000000;
|
916 |
|
|
23: polynom_rew = 32'b10000100000000000000000;
|
917 |
|
|
24: polynom_rew = 32'b111000010000000000000000;
|
918 |
|
|
25: polynom_rew = 32'b1001000000000000000000000;
|
919 |
|
|
26: polynom_rew = 32'b10000000000000000000100011;
|
920 |
|
|
27: polynom_rew = 32'b100000000000000000000010011;
|
921 |
|
|
28: polynom_rew = 32'b1100100000000000000000000000;
|
922 |
|
|
29: polynom_rew = 32'b10100000000000000000000000000;
|
923 |
|
|
30: polynom_rew = 32'b100000000000000000000000101001;
|
924 |
|
|
31: polynom_rew = 32'b1001000000000000000000000000000;
|
925 |
|
|
32: polynom_rew = 32'b10000000001000000000000000000011;
|
926 |
|
|
default: polynom_rew = 32'b0;
|
927 |
|
|
endcase
|
928 |
|
|
// rotate left
|
929 |
|
|
polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
|
930 |
|
|
lfsr_fb_rew = qi[length];
|
931 |
|
|
for (i=length-1; i>=1; i=i-1) begin
|
932 |
|
|
if (polynom_rew[i])
|
933 |
|
|
lfsr_fb_rew = lfsr_fb_rew ~^ qi[i];
|
934 |
|
|
end
|
935 |
|
|
end
|
936 |
|
|
assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
|
937 |
|
|
assign q_next = rew ? q_next_rew : q_next_fw;
|
938 |
|
|
always @ (posedge clk or posedge rst)
|
939 |
|
|
if (rst)
|
940 |
|
|
qi <= {length{1'b0}};
|
941 |
|
|
else
|
942 |
|
|
if (cke)
|
943 |
|
|
qi <= q_next;
|
944 |
|
|
always @ (posedge clk or posedge rst)
|
945 |
|
|
if (rst)
|
946 |
|
|
level1 <= 1'b0;
|
947 |
|
|
else
|
948 |
|
|
if (cke)
|
949 |
|
|
if (q_next == level1_value)
|
950 |
|
|
level1 <= 1'b1;
|
951 |
|
|
else if (qi == level1_value & rew)
|
952 |
|
|
level1 <= 1'b0;
|
953 |
|
|
endmodule
|
954 |
|
|
//////////////////////////////////////////////////////////////////////
|
955 |
|
|
//// ////
|
956 |
|
|
//// Versatile counter ////
|
957 |
|
|
//// ////
|
958 |
|
|
//// Description ////
|
959 |
|
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
960 |
|
|
//// counter ////
|
961 |
|
|
//// ////
|
962 |
|
|
//// To Do: ////
|
963 |
|
|
//// - add LFSR with more taps ////
|
964 |
|
|
//// ////
|
965 |
|
|
//// Author(s): ////
|
966 |
|
|
//// - Michael Unneback, unneback@opencores.org ////
|
967 |
|
|
//// ORSoC AB ////
|
968 |
|
|
//// ////
|
969 |
|
|
//////////////////////////////////////////////////////////////////////
|
970 |
|
|
//// ////
|
971 |
|
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
972 |
|
|
//// ////
|
973 |
|
|
//// This source file may be used and distributed without ////
|
974 |
|
|
//// restriction provided that this copyright statement is not ////
|
975 |
|
|
//// removed from the file and that any derivative work contains ////
|
976 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
977 |
|
|
//// ////
|
978 |
|
|
//// This source file is free software; you can redistribute it ////
|
979 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
980 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
981 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
982 |
|
|
//// later version. ////
|
983 |
|
|
//// ////
|
984 |
|
|
//// This source is distributed in the hope that it will be ////
|
985 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
986 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
987 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
988 |
|
|
//// details. ////
|
989 |
|
|
//// ////
|
990 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
991 |
|
|
//// Public License along with this source; if not, download it ////
|
992 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
993 |
|
|
//// ////
|
994 |
|
|
//////////////////////////////////////////////////////////////////////
|
995 |
|
|
// GRAY counter
|
996 |
|
|
module cnt_gray ( q, rst, clk);
|
997 |
|
|
parameter length = 4;
|
998 |
|
|
output reg [length:1] q;
|
999 |
|
|
input rst;
|
1000 |
|
|
input clk;
|
1001 |
|
|
parameter clear_value = 0;
|
1002 |
|
|
parameter set_value = 1;
|
1003 |
|
|
parameter wrap_value = 8;
|
1004 |
|
|
parameter level1_value = 15;
|
1005 |
|
|
reg [length:1] qi;
|
1006 |
|
|
wire [length:1] q_next;
|
1007 |
|
|
assign q_next = qi + {{length-1{1'b0}},1'b1};
|
1008 |
|
|
always @ (posedge clk or posedge rst)
|
1009 |
|
|
if (rst)
|
1010 |
|
|
qi <= {length{1'b0}};
|
1011 |
|
|
else
|
1012 |
|
|
qi <= q_next;
|
1013 |
|
|
always @ (posedge clk or posedge rst)
|
1014 |
|
|
if (rst)
|
1015 |
|
|
q <= {length{1'b0}};
|
1016 |
|
|
else
|
1017 |
|
|
q <= (q_next>>1) ^ q_next;
|
1018 |
|
|
endmodule
|
1019 |
|
|
//////////////////////////////////////////////////////////////////////
|
1020 |
|
|
//// ////
|
1021 |
|
|
//// Versatile counter ////
|
1022 |
|
|
//// ////
|
1023 |
|
|
//// Description ////
|
1024 |
|
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
1025 |
|
|
//// counter ////
|
1026 |
|
|
//// ////
|
1027 |
|
|
//// To Do: ////
|
1028 |
|
|
//// - add LFSR with more taps ////
|
1029 |
|
|
//// ////
|
1030 |
|
|
//// Author(s): ////
|
1031 |
|
|
//// - Michael Unneback, unneback@opencores.org ////
|
1032 |
|
|
//// ORSoC AB ////
|
1033 |
|
|
//// ////
|
1034 |
|
|
//////////////////////////////////////////////////////////////////////
|
1035 |
|
|
//// ////
|
1036 |
|
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
1037 |
|
|
//// ////
|
1038 |
|
|
//// This source file may be used and distributed without ////
|
1039 |
|
|
//// restriction provided that this copyright statement is not ////
|
1040 |
|
|
//// removed from the file and that any derivative work contains ////
|
1041 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
1042 |
|
|
//// ////
|
1043 |
|
|
//// This source file is free software; you can redistribute it ////
|
1044 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
1045 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
1046 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
1047 |
|
|
//// later version. ////
|
1048 |
|
|
//// ////
|
1049 |
|
|
//// This source is distributed in the hope that it will be ////
|
1050 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
1051 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
1052 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
1053 |
|
|
//// details. ////
|
1054 |
|
|
//// ////
|
1055 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
1056 |
|
|
//// Public License along with this source; if not, download it ////
|
1057 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
1058 |
|
|
//// ////
|
1059 |
|
|
//////////////////////////////////////////////////////////////////////
|
1060 |
|
|
// GRAY counter
|
1061 |
|
|
module cnt_gray_ce ( cke, q, rst, clk);
|
1062 |
|
|
parameter length = 4;
|
1063 |
|
|
input cke;
|
1064 |
|
|
output reg [length:1] q;
|
1065 |
|
|
input rst;
|
1066 |
|
|
input clk;
|
1067 |
|
|
parameter clear_value = 0;
|
1068 |
|
|
parameter set_value = 1;
|
1069 |
|
|
parameter wrap_value = 8;
|
1070 |
|
|
parameter level1_value = 15;
|
1071 |
|
|
reg [length:1] qi;
|
1072 |
|
|
wire [length:1] q_next;
|
1073 |
|
|
assign q_next = qi + {{length-1{1'b0}},1'b1};
|
1074 |
|
|
always @ (posedge clk or posedge rst)
|
1075 |
|
|
if (rst)
|
1076 |
|
|
qi <= {length{1'b0}};
|
1077 |
|
|
else
|
1078 |
|
|
if (cke)
|
1079 |
|
|
qi <= q_next;
|
1080 |
|
|
always @ (posedge clk or posedge rst)
|
1081 |
|
|
if (rst)
|
1082 |
|
|
q <= {length{1'b0}};
|
1083 |
|
|
else
|
1084 |
|
|
if (cke)
|
1085 |
|
|
q <= (q_next>>1) ^ q_next;
|
1086 |
|
|
endmodule
|
1087 |
|
|
//////////////////////////////////////////////////////////////////////
|
1088 |
|
|
//// ////
|
1089 |
|
|
//// Versatile counter ////
|
1090 |
|
|
//// ////
|
1091 |
|
|
//// Description ////
|
1092 |
|
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
1093 |
|
|
//// counter ////
|
1094 |
|
|
//// ////
|
1095 |
|
|
//// To Do: ////
|
1096 |
|
|
//// - add LFSR with more taps ////
|
1097 |
|
|
//// ////
|
1098 |
|
|
//// Author(s): ////
|
1099 |
|
|
//// - Michael Unneback, unneback@opencores.org ////
|
1100 |
|
|
//// ORSoC AB ////
|
1101 |
|
|
//// ////
|
1102 |
|
|
//////////////////////////////////////////////////////////////////////
|
1103 |
|
|
//// ////
|
1104 |
|
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
1105 |
|
|
//// ////
|
1106 |
|
|
//// This source file may be used and distributed without ////
|
1107 |
|
|
//// restriction provided that this copyright statement is not ////
|
1108 |
|
|
//// removed from the file and that any derivative work contains ////
|
1109 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
1110 |
|
|
//// ////
|
1111 |
|
|
//// This source file is free software; you can redistribute it ////
|
1112 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
1113 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
1114 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
1115 |
|
|
//// later version. ////
|
1116 |
|
|
//// ////
|
1117 |
|
|
//// This source is distributed in the hope that it will be ////
|
1118 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
1119 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
1120 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
1121 |
|
|
//// details. ////
|
1122 |
|
|
//// ////
|
1123 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
1124 |
|
|
//// Public License along with this source; if not, download it ////
|
1125 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
1126 |
|
|
//// ////
|
1127 |
|
|
//////////////////////////////////////////////////////////////////////
|
1128 |
|
|
// GRAY counter
|
1129 |
|
|
module cnt_gray_ce_bin ( cke, q, q_bin, rst, clk);
|
1130 |
|
|
parameter length = 4;
|
1131 |
|
|
input cke;
|
1132 |
|
|
output reg [length:1] q;
|
1133 |
|
|
output [length:1] q_bin;
|
1134 |
|
|
input rst;
|
1135 |
|
|
input clk;
|
1136 |
|
|
parameter clear_value = 0;
|
1137 |
|
|
parameter set_value = 1;
|
1138 |
|
|
parameter wrap_value = 8;
|
1139 |
|
|
parameter level1_value = 15;
|
1140 |
|
|
reg [length:1] qi;
|
1141 |
|
|
wire [length:1] q_next;
|
1142 |
|
|
assign q_next = qi + {{length-1{1'b0}},1'b1};
|
1143 |
|
|
always @ (posedge clk or posedge rst)
|
1144 |
|
|
if (rst)
|
1145 |
|
|
qi <= {length{1'b0}};
|
1146 |
|
|
else
|
1147 |
|
|
if (cke)
|
1148 |
|
|
qi <= q_next;
|
1149 |
|
|
always @ (posedge clk or posedge rst)
|
1150 |
|
|
if (rst)
|
1151 |
|
|
q <= {length{1'b0}};
|
1152 |
|
|
else
|
1153 |
|
|
if (cke)
|
1154 |
|
|
q <= (q_next>>1) ^ q_next;
|
1155 |
|
|
assign q_bin = qi;
|
1156 |
|
|
endmodule
|
1157 |
|
|
//////////////////////////////////////////////////////////////////////
|
1158 |
|
|
//// ////
|
1159 |
|
|
//// Versatile library, counters ////
|
1160 |
|
|
//// ////
|
1161 |
|
|
//// Description ////
|
1162 |
|
|
//// counters ////
|
1163 |
|
|
//// ////
|
1164 |
|
|
//// ////
|
1165 |
|
|
//// To Do: ////
|
1166 |
|
|
//// - add more counters ////
|
1167 |
|
|
//// ////
|
1168 |
|
|
//// Author(s): ////
|
1169 |
|
|
//// - Michael Unneback, unneback@opencores.org ////
|
1170 |
|
|
//// ORSoC AB ////
|
1171 |
|
|
//// ////
|
1172 |
|
|
//////////////////////////////////////////////////////////////////////
|
1173 |
|
|
//// ////
|
1174 |
|
|
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
|
1175 |
|
|
//// ////
|
1176 |
|
|
//// This source file may be used and distributed without ////
|
1177 |
|
|
//// restriction provided that this copyright statement is not ////
|
1178 |
|
|
//// removed from the file and that any derivative work contains ////
|
1179 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
1180 |
|
|
//// ////
|
1181 |
|
|
//// This source file is free software; you can redistribute it ////
|
1182 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
1183 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
1184 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
1185 |
|
|
//// later version. ////
|
1186 |
|
|
//// ////
|
1187 |
|
|
//// This source is distributed in the hope that it will be ////
|
1188 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
1189 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
1190 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
1191 |
|
|
//// details. ////
|
1192 |
|
|
//// ////
|
1193 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
1194 |
|
|
//// Public License along with this source; if not, download it ////
|
1195 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
1196 |
|
|
//// ////
|
1197 |
|
|
//////////////////////////////////////////////////////////////////////
|
1198 |
|
|
module cnt_shreg_wrap ( q, rst, clk);
|
1199 |
|
|
parameter length = 4;
|
1200 |
|
|
output reg [0:length-1] q;
|
1201 |
|
|
input rst;
|
1202 |
|
|
input clk;
|
1203 |
|
|
always @ (posedge clk or posedge rst)
|
1204 |
|
|
if (rst)
|
1205 |
|
|
q <= {1'b1,{length-1{1'b0}}};
|
1206 |
|
|
else
|
1207 |
|
|
q <= {q[length-1],q[0:length-2]};
|
1208 |
|
|
endmodule
|
1209 |
|
|
module cnt_shreg_ce_wrap ( cke, q, rst, clk);
|
1210 |
|
|
parameter length = 4;
|
1211 |
|
|
input cke;
|
1212 |
|
|
output reg [0:length-1] q;
|
1213 |
|
|
input rst;
|
1214 |
|
|
input clk;
|
1215 |
|
|
always @ (posedge clk or posedge rst)
|
1216 |
|
|
if (rst)
|
1217 |
|
|
q <= {1'b1,{length-1{1'b0}}};
|
1218 |
|
|
else
|
1219 |
|
|
if (cke)
|
1220 |
|
|
q <= {q[length-1],q[0:length-2]};
|
1221 |
|
|
endmodule
|
1222 |
|
|
module cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
|
1223 |
|
|
parameter length = 4;
|
1224 |
|
|
input cke, clear;
|
1225 |
|
|
output reg [0:length-1] q;
|
1226 |
|
|
input rst;
|
1227 |
|
|
input clk;
|
1228 |
|
|
always @ (posedge clk or posedge rst)
|
1229 |
|
|
if (rst)
|
1230 |
|
|
q <= {1'b1,{length-1{1'b0}}};
|
1231 |
|
|
else
|
1232 |
|
|
if (cke)
|
1233 |
|
|
if (clear)
|
1234 |
|
|
q <= {1'b1,{length-1{1'b0}}};
|
1235 |
|
|
else
|
1236 |
|
|
q <= q >> 1;
|
1237 |
|
|
endmodule
|
1238 |
|
|
module cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
|
1239 |
|
|
parameter length = 4;
|
1240 |
|
|
input cke, clear;
|
1241 |
|
|
output reg [0:length-1] q;
|
1242 |
|
|
input rst;
|
1243 |
|
|
input clk;
|
1244 |
|
|
always @ (posedge clk or posedge rst)
|
1245 |
|
|
if (rst)
|
1246 |
|
|
q <= {1'b1,{length-1{1'b0}}};
|
1247 |
|
|
else
|
1248 |
|
|
if (cke)
|
1249 |
|
|
if (clear)
|
1250 |
|
|
q <= {1'b1,{length-1{1'b0}}};
|
1251 |
|
|
else
|
1252 |
|
|
q <= {q[length-1],q[0:length-2]};
|
1253 |
|
|
endmodule
|
1254 |
|
|
//////////////////////////////////////////////////////////////////////
|
1255 |
|
|
//// ////
|
1256 |
|
|
//// Versatile library, memories ////
|
1257 |
|
|
//// ////
|
1258 |
|
|
//// Description ////
|
1259 |
|
|
//// memories ////
|
1260 |
|
|
//// ////
|
1261 |
|
|
//// ////
|
1262 |
|
|
//// To Do: ////
|
1263 |
|
|
//// - add more memory types ////
|
1264 |
|
|
//// ////
|
1265 |
|
|
//// Author(s): ////
|
1266 |
|
|
//// - Michael Unneback, unneback@opencores.org ////
|
1267 |
|
|
//// ORSoC AB ////
|
1268 |
|
|
//// ////
|
1269 |
|
|
//////////////////////////////////////////////////////////////////////
|
1270 |
|
|
//// ////
|
1271 |
|
|
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
|
1272 |
|
|
//// ////
|
1273 |
|
|
//// This source file may be used and distributed without ////
|
1274 |
|
|
//// restriction provided that this copyright statement is not ////
|
1275 |
|
|
//// removed from the file and that any derivative work contains ////
|
1276 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
1277 |
|
|
//// ////
|
1278 |
|
|
//// This source file is free software; you can redistribute it ////
|
1279 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
1280 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
1281 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
1282 |
|
|
//// later version. ////
|
1283 |
|
|
//// ////
|
1284 |
|
|
//// This source is distributed in the hope that it will be ////
|
1285 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
1286 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
1287 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
1288 |
|
|
//// details. ////
|
1289 |
|
|
//// ////
|
1290 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
1291 |
|
|
//// Public License along with this source; if not, download it ////
|
1292 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
1293 |
|
|
//// ////
|
1294 |
|
|
//////////////////////////////////////////////////////////////////////
|
1295 |
|
|
/// ROM
|
1296 |
7 |
unneback |
module vl_rom_init ( adr, q, clk);
|
1297 |
|
|
parameter data_width = 32;
|
1298 |
|
|
parameter addr_width = 8;
|
1299 |
|
|
input [(addr_width-1):0] adr;
|
1300 |
|
|
output reg [(data_width-1):0] q;
|
1301 |
|
|
input clk;
|
1302 |
|
|
reg [data_width-1:0] rom [(1<<addr_width)-1:0];
|
1303 |
|
|
parameter memory_file = "vl_rom.vmem";
|
1304 |
|
|
initial
|
1305 |
|
|
begin
|
1306 |
|
|
$readmemh(memory_file, rom);
|
1307 |
|
|
end
|
1308 |
|
|
always @ (posedge clk)
|
1309 |
|
|
q <= rom[adr];
|
1310 |
|
|
endmodule
|
1311 |
|
|
module vl_rom ( adr, q, clk);
|
1312 |
6 |
unneback |
parameter data_width = 32;
|
1313 |
|
|
parameter addr_width = 4;
|
1314 |
|
|
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
|
1315 |
|
|
{32'h18000000},
|
1316 |
|
|
{32'hA8200000},
|
1317 |
|
|
{32'hA8200000},
|
1318 |
|
|
{32'hA8200000},
|
1319 |
|
|
{32'h44003000},
|
1320 |
|
|
{32'h15000000},
|
1321 |
|
|
{32'h15000000},
|
1322 |
|
|
{32'h15000000},
|
1323 |
|
|
{32'h15000000},
|
1324 |
|
|
{32'h15000000},
|
1325 |
|
|
{32'h15000000},
|
1326 |
|
|
{32'h15000000},
|
1327 |
|
|
{32'h15000000},
|
1328 |
|
|
{32'h15000000},
|
1329 |
|
|
{32'h15000000},
|
1330 |
|
|
{32'h15000000}};
|
1331 |
7 |
unneback |
input [addr_width-1:0] adr;
|
1332 |
6 |
unneback |
output reg [data_width-1:0] q;
|
1333 |
|
|
input clk;
|
1334 |
|
|
always @ (posedge clk)
|
1335 |
7 |
unneback |
q <= data[adr];
|
1336 |
6 |
unneback |
endmodule
|
1337 |
|
|
// Single port RAM
|
1338 |
|
|
module vl_ram ( d, adr, we, q, clk);
|
1339 |
|
|
parameter data_width = 32;
|
1340 |
|
|
parameter addr_width = 8;
|
1341 |
|
|
input [(data_width-1):0] d;
|
1342 |
|
|
input [(addr_width-1):0] adr;
|
1343 |
|
|
input we;
|
1344 |
7 |
unneback |
output reg [(data_width-1):0] q;
|
1345 |
6 |
unneback |
input clk;
|
1346 |
|
|
reg [data_width-1:0] ram [(1<<addr_width)-1:0];
|
1347 |
7 |
unneback |
parameter init = 0;
|
1348 |
|
|
parameter memory_file = "vl_ram.vmem";
|
1349 |
|
|
generate if (init) begin : init_mem
|
1350 |
|
|
initial
|
1351 |
|
|
begin
|
1352 |
|
|
$readmemh(memory_file, ram);
|
1353 |
|
|
end
|
1354 |
|
|
end
|
1355 |
|
|
endgenerate
|
1356 |
6 |
unneback |
always @ (posedge clk)
|
1357 |
|
|
begin
|
1358 |
|
|
if (we)
|
1359 |
|
|
ram[adr] <= d;
|
1360 |
|
|
q <= ram[adr];
|
1361 |
|
|
end
|
1362 |
|
|
endmodule
|
1363 |
7 |
unneback |
module vl_ram_be ( d, adr, be, we, q, clk);
|
1364 |
|
|
parameter data_width = 32;
|
1365 |
|
|
parameter addr_width = 8;
|
1366 |
|
|
input [(data_width-1):0] d;
|
1367 |
|
|
input [(addr_width-1):0] adr;
|
1368 |
|
|
input [(addr_width/4)-1:0] be;
|
1369 |
|
|
input we;
|
1370 |
|
|
output reg [(data_width-1):0] q;
|
1371 |
|
|
input clk;
|
1372 |
|
|
reg [data_width-1:0] ram [(1<<addr_width)-1:0];
|
1373 |
|
|
parameter init = 0;
|
1374 |
|
|
parameter memory_file = "vl_ram.vmem";
|
1375 |
|
|
generate if (init) begin : init_mem
|
1376 |
|
|
initial
|
1377 |
|
|
begin
|
1378 |
|
|
$readmemh(memory_file, ram);
|
1379 |
|
|
end
|
1380 |
|
|
end
|
1381 |
|
|
endgenerate
|
1382 |
|
|
genvar i;
|
1383 |
|
|
generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
|
1384 |
|
|
always @ (posedge clk)
|
1385 |
|
|
if (we & be[i])
|
1386 |
|
|
ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
|
1387 |
|
|
end
|
1388 |
|
|
endgenerate
|
1389 |
|
|
always @ (posedge clk)
|
1390 |
|
|
q <= ram[adr];
|
1391 |
|
|
endmodule
|
1392 |
6 |
unneback |
// Dual port RAM
|
1393 |
|
|
// ACTEL FPGA should not use logic to handle rw collision
|
1394 |
7 |
unneback |
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
|
1395 |
6 |
unneback |
parameter data_width = 32;
|
1396 |
|
|
parameter addr_width = 8;
|
1397 |
|
|
input [(data_width-1):0] d_a;
|
1398 |
|
|
input [(addr_width-1):0] adr_a;
|
1399 |
|
|
input [(addr_width-1):0] adr_b;
|
1400 |
|
|
input we_a;
|
1401 |
|
|
output [(data_width-1):0] q_b;
|
1402 |
|
|
input clk_a, clk_b;
|
1403 |
|
|
reg [(addr_width-1):0] adr_b_reg;
|
1404 |
|
|
reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
|
1405 |
7 |
unneback |
parameter init = 0;
|
1406 |
|
|
parameter memory_file = "vl_ram.vmem";
|
1407 |
|
|
generate if (init) begin : init_mem
|
1408 |
|
|
initial
|
1409 |
|
|
begin
|
1410 |
|
|
$readmemh(memory_file, ram);
|
1411 |
|
|
end
|
1412 |
|
|
end
|
1413 |
|
|
endgenerate
|
1414 |
6 |
unneback |
always @ (posedge clk_a)
|
1415 |
|
|
if (we_a)
|
1416 |
|
|
ram[adr_a] <= d_a;
|
1417 |
|
|
always @ (posedge clk_b)
|
1418 |
|
|
adr_b_reg <= adr_b;
|
1419 |
|
|
assign q_b = ram[adr_b_reg];
|
1420 |
|
|
endmodule
|
1421 |
7 |
unneback |
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
|
1422 |
6 |
unneback |
parameter data_width = 32;
|
1423 |
|
|
parameter addr_width = 8;
|
1424 |
|
|
input [(data_width-1):0] d_a;
|
1425 |
|
|
input [(addr_width-1):0] adr_a;
|
1426 |
|
|
input [(addr_width-1):0] adr_b;
|
1427 |
|
|
input we_a;
|
1428 |
|
|
output [(data_width-1):0] q_b;
|
1429 |
|
|
output reg [(data_width-1):0] q_a;
|
1430 |
|
|
input clk_a, clk_b;
|
1431 |
|
|
reg [(data_width-1):0] q_b;
|
1432 |
|
|
reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
|
1433 |
7 |
unneback |
parameter init = 0;
|
1434 |
|
|
parameter memory_file = "vl_ram.vmem";
|
1435 |
|
|
generate if (init) begin : init_mem
|
1436 |
|
|
initial
|
1437 |
|
|
begin
|
1438 |
|
|
$readmemh(memory_file, ram);
|
1439 |
|
|
end
|
1440 |
|
|
end
|
1441 |
|
|
endgenerate
|
1442 |
6 |
unneback |
always @ (posedge clk_a)
|
1443 |
|
|
begin
|
1444 |
|
|
q_a <= ram[adr_a];
|
1445 |
|
|
if (we_a)
|
1446 |
|
|
ram[adr_a] <= d_a;
|
1447 |
|
|
end
|
1448 |
|
|
always @ (posedge clk_b)
|
1449 |
|
|
q_b <= ram[adr_b];
|
1450 |
|
|
endmodule
|
1451 |
7 |
unneback |
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
|
1452 |
6 |
unneback |
parameter data_width = 32;
|
1453 |
|
|
parameter addr_width = 8;
|
1454 |
|
|
input [(data_width-1):0] d_a;
|
1455 |
|
|
input [(addr_width-1):0] adr_a;
|
1456 |
|
|
input [(addr_width-1):0] adr_b;
|
1457 |
|
|
input we_a;
|
1458 |
|
|
output [(data_width-1):0] q_b;
|
1459 |
|
|
input [(data_width-1):0] d_b;
|
1460 |
|
|
output reg [(data_width-1):0] q_a;
|
1461 |
|
|
input we_b;
|
1462 |
|
|
input clk_a, clk_b;
|
1463 |
|
|
reg [(data_width-1):0] q_b;
|
1464 |
|
|
reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
|
1465 |
7 |
unneback |
parameter init = 0;
|
1466 |
|
|
parameter memory_file = "vl_ram.vmem";
|
1467 |
|
|
generate if (init) begin : init_mem
|
1468 |
|
|
initial
|
1469 |
|
|
begin
|
1470 |
|
|
$readmemh(memory_file, ram);
|
1471 |
|
|
end
|
1472 |
|
|
end
|
1473 |
|
|
endgenerate
|
1474 |
6 |
unneback |
always @ (posedge clk_a)
|
1475 |
|
|
begin
|
1476 |
|
|
q_a <= ram[adr_a];
|
1477 |
|
|
if (we_a)
|
1478 |
|
|
ram[adr_a] <= d_a;
|
1479 |
|
|
end
|
1480 |
|
|
always @ (posedge clk_b)
|
1481 |
|
|
begin
|
1482 |
|
|
q_b <= ram[adr_b];
|
1483 |
|
|
if (we_b)
|
1484 |
|
|
ram[adr_b] <= d_b;
|
1485 |
|
|
end
|
1486 |
|
|
endmodule
|
1487 |
|
|
// Content addresable memory, CAM
|
1488 |
|
|
// FIFO
|
1489 |
|
|
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
|
1490 |
11 |
unneback |
parameter addr_width = 4;
|
1491 |
|
|
parameter N = addr_width-1;
|
1492 |
6 |
unneback |
parameter Q1 = 2'b00;
|
1493 |
|
|
parameter Q2 = 2'b01;
|
1494 |
|
|
parameter Q3 = 2'b11;
|
1495 |
|
|
parameter Q4 = 2'b10;
|
1496 |
|
|
parameter going_empty = 1'b0;
|
1497 |
|
|
parameter going_full = 1'b1;
|
1498 |
|
|
input [N:0] wptr, rptr;
|
1499 |
|
|
output reg fifo_empty;
|
1500 |
|
|
output fifo_full;
|
1501 |
|
|
input wclk, rclk, rst;
|
1502 |
|
|
wire direction;
|
1503 |
|
|
reg direction_set, direction_clr;
|
1504 |
|
|
wire async_empty, async_full;
|
1505 |
|
|
wire fifo_full2;
|
1506 |
|
|
reg fifo_empty2;
|
1507 |
|
|
// direction_set
|
1508 |
|
|
always @ (wptr[N:N-1] or rptr[N:N-1])
|
1509 |
|
|
case ({wptr[N:N-1],rptr[N:N-1]})
|
1510 |
|
|
{Q1,Q2} : direction_set <= 1'b1;
|
1511 |
|
|
{Q2,Q3} : direction_set <= 1'b1;
|
1512 |
|
|
{Q3,Q4} : direction_set <= 1'b1;
|
1513 |
|
|
{Q4,Q1} : direction_set <= 1'b1;
|
1514 |
|
|
default : direction_set <= 1'b0;
|
1515 |
|
|
endcase
|
1516 |
|
|
// direction_clear
|
1517 |
|
|
always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
|
1518 |
|
|
if (rst)
|
1519 |
|
|
direction_clr <= 1'b1;
|
1520 |
|
|
else
|
1521 |
|
|
case ({wptr[N:N-1],rptr[N:N-1]})
|
1522 |
|
|
{Q2,Q1} : direction_clr <= 1'b1;
|
1523 |
|
|
{Q3,Q2} : direction_clr <= 1'b1;
|
1524 |
|
|
{Q4,Q3} : direction_clr <= 1'b1;
|
1525 |
|
|
{Q1,Q4} : direction_clr <= 1'b1;
|
1526 |
|
|
default : direction_clr <= 1'b0;
|
1527 |
|
|
endcase
|
1528 |
|
|
dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
|
1529 |
|
|
assign async_empty = (wptr == rptr) && (direction==going_empty);
|
1530 |
|
|
assign async_full = (wptr == rptr) && (direction==going_full);
|
1531 |
|
|
dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
|
1532 |
|
|
dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
|
1533 |
|
|
/*
|
1534 |
|
|
always @ (posedge wclk or posedge rst or posedge async_full)
|
1535 |
|
|
if (rst)
|
1536 |
|
|
{fifo_full, fifo_full2} <= 2'b00;
|
1537 |
|
|
else if (async_full)
|
1538 |
|
|
{fifo_full, fifo_full2} <= 2'b11;
|
1539 |
|
|
else
|
1540 |
|
|
{fifo_full, fifo_full2} <= {fifo_full2, async_full};
|
1541 |
|
|
*/
|
1542 |
|
|
always @ (posedge rclk or posedge async_empty)
|
1543 |
|
|
if (async_empty)
|
1544 |
|
|
{fifo_empty, fifo_empty2} <= 2'b11;
|
1545 |
|
|
else
|
1546 |
|
|
{fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty};
|
1547 |
|
|
endmodule // async_comp
|
1548 |
|
|
module vl_fifo_1r1w_async (
|
1549 |
|
|
d, wr, fifo_full, wr_clk, wr_rst,
|
1550 |
|
|
q, rd, fifo_empty, rd_clk, rd_rst
|
1551 |
|
|
);
|
1552 |
|
|
parameter data_width = 18;
|
1553 |
|
|
parameter addr_width = 4;
|
1554 |
|
|
// write side
|
1555 |
|
|
input [data_width-1:0] d;
|
1556 |
|
|
input wr;
|
1557 |
|
|
output fifo_full;
|
1558 |
|
|
input wr_clk;
|
1559 |
|
|
input wr_rst;
|
1560 |
|
|
// read side
|
1561 |
|
|
output [data_width-1:0] q;
|
1562 |
|
|
input rd;
|
1563 |
|
|
output fifo_empty;
|
1564 |
|
|
input rd_clk;
|
1565 |
|
|
input rd_rst;
|
1566 |
|
|
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
|
1567 |
|
|
vl_fifo_1r1w_async (
|
1568 |
|
|
d, wr, fifo_full, wr_clk, wr_rst,
|
1569 |
|
|
q, rd, fifo_empty, rd_clk, rd_rst
|
1570 |
|
|
);
|
1571 |
7 |
unneback |
cnt_gray_ce_bin
|
1572 |
6 |
unneback |
# ( .length(addr_width))
|
1573 |
|
|
fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
|
1574 |
7 |
unneback |
cnt_gray_ce_bin
|
1575 |
6 |
unneback |
# (.length(addr_width))
|
1576 |
|
|
fifo_rd_adr( .cke(wr), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_rst));
|
1577 |
7 |
unneback |
vl_dpram_1r1w
|
1578 |
6 |
unneback |
# (.data_width(data_width), .addr_width(addr_width))
|
1579 |
|
|
dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
|
1580 |
|
|
vl_fifo_cmp_async
|
1581 |
|
|
# (.addr_width(addr_width))
|
1582 |
|
|
cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
|
1583 |
|
|
endmodule
|
1584 |
8 |
unneback |
module vl_fifo_2r2w_async (
|
1585 |
6 |
unneback |
// a side
|
1586 |
|
|
a_d, a_wr, a_fifo_full,
|
1587 |
|
|
a_q, a_rd, a_fifo_empty,
|
1588 |
|
|
a_clk, a_rst,
|
1589 |
|
|
// b side
|
1590 |
|
|
b_d, b_wr, b_fifo_full,
|
1591 |
|
|
b_q, b_rd, b_fifo_empty,
|
1592 |
|
|
b_clk, b_rst
|
1593 |
|
|
);
|
1594 |
|
|
parameter data_width = 18;
|
1595 |
|
|
parameter addr_width = 4;
|
1596 |
|
|
// a side
|
1597 |
|
|
input [data_width-1:0] a_d;
|
1598 |
|
|
input a_wr;
|
1599 |
|
|
output a_fifo_full;
|
1600 |
|
|
output [data_width-1:0] a_q;
|
1601 |
|
|
input a_rd;
|
1602 |
|
|
output a_fifo_empty;
|
1603 |
|
|
input a_clk;
|
1604 |
|
|
input a_rst;
|
1605 |
|
|
// b side
|
1606 |
|
|
input [data_width-1:0] b_d;
|
1607 |
|
|
input b_wr;
|
1608 |
|
|
output b_fifo_full;
|
1609 |
|
|
output [data_width-1:0] b_q;
|
1610 |
|
|
input b_rd;
|
1611 |
|
|
output b_fifo_empty;
|
1612 |
|
|
input b_clk;
|
1613 |
|
|
input b_rst;
|
1614 |
|
|
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
|
1615 |
|
|
vl_fifo_1r1w_async_a (
|
1616 |
|
|
.d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
|
1617 |
|
|
.q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
|
1618 |
|
|
);
|
1619 |
|
|
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
|
1620 |
|
|
vl_fifo_1r1w_async_b (
|
1621 |
|
|
.d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
|
1622 |
|
|
.q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
|
1623 |
|
|
);
|
1624 |
|
|
endmodule
|
1625 |
8 |
unneback |
module vl_fifo_2r2w_async_simplex (
|
1626 |
6 |
unneback |
// a side
|
1627 |
|
|
a_d, a_wr, a_fifo_full,
|
1628 |
|
|
a_q, a_rd, a_fifo_empty,
|
1629 |
|
|
a_clk, a_rst,
|
1630 |
|
|
// b side
|
1631 |
|
|
b_d, b_wr, b_fifo_full,
|
1632 |
|
|
b_q, b_rd, b_fifo_empty,
|
1633 |
|
|
b_clk, b_rst
|
1634 |
|
|
);
|
1635 |
|
|
parameter data_width = 18;
|
1636 |
|
|
parameter addr_width = 4;
|
1637 |
|
|
// a side
|
1638 |
|
|
input [data_width-1:0] a_d;
|
1639 |
|
|
input a_wr;
|
1640 |
|
|
output a_fifo_full;
|
1641 |
|
|
output [data_width-1:0] a_q;
|
1642 |
|
|
input a_rd;
|
1643 |
|
|
output a_fifo_empty;
|
1644 |
|
|
input a_clk;
|
1645 |
|
|
input a_rst;
|
1646 |
|
|
// b side
|
1647 |
|
|
input [data_width-1:0] b_d;
|
1648 |
|
|
input b_wr;
|
1649 |
|
|
output b_fifo_full;
|
1650 |
|
|
output [data_width-1:0] b_q;
|
1651 |
|
|
input b_rd;
|
1652 |
|
|
output b_fifo_empty;
|
1653 |
|
|
input b_clk;
|
1654 |
|
|
input b_rst;
|
1655 |
|
|
// adr_gen
|
1656 |
|
|
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
|
1657 |
|
|
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
|
1658 |
|
|
// dpram
|
1659 |
|
|
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
|
1660 |
7 |
unneback |
cnt_gray_ce_bin
|
1661 |
6 |
unneback |
# ( .length(addr_width))
|
1662 |
|
|
fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
|
1663 |
7 |
unneback |
cnt_gray_ce_bin
|
1664 |
6 |
unneback |
# (.length(addr_width))
|
1665 |
|
|
fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
|
1666 |
7 |
unneback |
cnt_gray_ce_bin
|
1667 |
6 |
unneback |
# ( .length(addr_width))
|
1668 |
|
|
fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
|
1669 |
7 |
unneback |
cnt_gray_ce_bin
|
1670 |
6 |
unneback |
# (.length(addr_width))
|
1671 |
|
|
fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
|
1672 |
|
|
// mux read or write adr to DPRAM
|
1673 |
|
|
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
|
1674 |
|
|
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
|
1675 |
11 |
unneback |
vl_dpram_2r2w
|
1676 |
6 |
unneback |
# (.data_width(data_width), .addr_width(addr_width+1))
|
1677 |
|
|
dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
|
1678 |
|
|
.d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
|
1679 |
11 |
unneback |
vl_fifo_cmp_async
|
1680 |
6 |
unneback |
# (.addr_width(addr_width))
|
1681 |
|
|
cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
|
1682 |
11 |
unneback |
vl_fifo_cmp_async
|
1683 |
6 |
unneback |
# (.addr_width(addr_width))
|
1684 |
|
|
cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
|
1685 |
|
|
endmodule
|
1686 |
12 |
unneback |
//////////////////////////////////////////////////////////////////////
|
1687 |
|
|
//// ////
|
1688 |
|
|
//// Versatile library, wishbone stuff ////
|
1689 |
|
|
//// ////
|
1690 |
|
|
//// Description ////
|
1691 |
|
|
//// Wishbone compliant modules ////
|
1692 |
|
|
//// ////
|
1693 |
|
|
//// ////
|
1694 |
|
|
//// To Do: ////
|
1695 |
|
|
//// - ////
|
1696 |
|
|
//// ////
|
1697 |
|
|
//// Author(s): ////
|
1698 |
|
|
//// - Michael Unneback, unneback@opencores.org ////
|
1699 |
|
|
//// ORSoC AB ////
|
1700 |
|
|
//// ////
|
1701 |
|
|
//////////////////////////////////////////////////////////////////////
|
1702 |
|
|
//// ////
|
1703 |
|
|
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
|
1704 |
|
|
//// ////
|
1705 |
|
|
//// This source file may be used and distributed without ////
|
1706 |
|
|
//// restriction provided that this copyright statement is not ////
|
1707 |
|
|
//// removed from the file and that any derivative work contains ////
|
1708 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
1709 |
|
|
//// ////
|
1710 |
|
|
//// This source file is free software; you can redistribute it ////
|
1711 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
1712 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
1713 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
1714 |
|
|
//// later version. ////
|
1715 |
|
|
//// ////
|
1716 |
|
|
//// This source is distributed in the hope that it will be ////
|
1717 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
1718 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
1719 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
1720 |
|
|
//// details. ////
|
1721 |
|
|
//// ////
|
1722 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
1723 |
|
|
//// Public License along with this source; if not, download it ////
|
1724 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
1725 |
|
|
//// ////
|
1726 |
|
|
//////////////////////////////////////////////////////////////////////
|
1727 |
|
|
// async wb3 - wb3 bridge
|
1728 |
|
|
`timescale 1ns/1ns
|
1729 |
|
|
module wb3wb3_bridge (
|
1730 |
|
|
// wishbone slave side
|
1731 |
|
|
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
|
1732 |
|
|
// wishbone master side
|
1733 |
|
|
wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
|
1734 |
|
|
input [31:0] wbs_dat_i;
|
1735 |
|
|
input [31:2] wbs_adr_i;
|
1736 |
|
|
input [3:0] wbs_sel_i;
|
1737 |
|
|
input [1:0] wbs_bte_i;
|
1738 |
|
|
input [2:0] wbs_cti_i;
|
1739 |
|
|
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
|
1740 |
|
|
output [31:0] wbs_dat_o;
|
1741 |
|
|
output reg wbs_ack_o;
|
1742 |
|
|
input wbs_clk, wbs_rst;
|
1743 |
|
|
output [31:0] wbm_dat_o;
|
1744 |
|
|
output reg [31:2] wbm_adr_o;
|
1745 |
|
|
output [3:0] wbm_sel_o;
|
1746 |
|
|
output reg [1:0] wbm_bte_o;
|
1747 |
|
|
output reg [2:0] wbm_cti_o;
|
1748 |
|
|
output reg wbm_we_o, wbm_cyc_o;
|
1749 |
|
|
output wbm_stb_o;
|
1750 |
|
|
input [31:0] wbm_dat_i;
|
1751 |
|
|
input wbm_ack_i;
|
1752 |
|
|
input wbm_clk, wbm_rst;
|
1753 |
|
|
parameter addr_width = 4;
|
1754 |
|
|
// bte
|
1755 |
|
|
parameter linear = 2'b00;
|
1756 |
|
|
parameter wrap4 = 2'b01;
|
1757 |
|
|
parameter wrap8 = 2'b10;
|
1758 |
|
|
parameter wrap16 = 2'b11;
|
1759 |
|
|
// cti
|
1760 |
|
|
parameter classic = 3'b000;
|
1761 |
|
|
parameter incburst = 3'b010;
|
1762 |
|
|
parameter endofburst = 3'b111;
|
1763 |
|
|
parameter wbs_adr = 1'b0;
|
1764 |
|
|
parameter wbs_data = 1'b1;
|
1765 |
|
|
parameter wbm_adr0 = 2'b00;
|
1766 |
|
|
parameter wbm_adr1 = 2'b01;
|
1767 |
|
|
parameter wbm_data = 2'b10;
|
1768 |
|
|
reg wbs_we_reg;
|
1769 |
|
|
reg [1:0] wbs_bte_reg;
|
1770 |
|
|
reg wbs;
|
1771 |
|
|
wire wbs_eoc_alert, wbm_eoc_alert;
|
1772 |
|
|
reg wbs_eoc, wbm_eoc;
|
1773 |
|
|
reg [1:0] wbm;
|
1774 |
|
|
reg [1:16] wbs_count, wbm_count;
|
1775 |
|
|
reg wbs_ack_o_rd;
|
1776 |
|
|
wire wbs_ack_o_wr;
|
1777 |
|
|
wire [35:0] a_d, a_q, b_d, b_q;
|
1778 |
|
|
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
|
1779 |
|
|
reg a_rd_reg;
|
1780 |
|
|
wire b_rd_adr, b_rd_data;
|
1781 |
|
|
reg b_rd_data_reg;
|
1782 |
|
|
reg [35:0] temp;
|
1783 |
|
|
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
|
1784 |
|
|
always @ (posedge wbs_clk or posedge wbs_rst)
|
1785 |
|
|
if (wbs_rst)
|
1786 |
|
|
wbs_eoc <= 1'b0;
|
1787 |
|
|
else
|
1788 |
|
|
if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
|
1789 |
|
|
wbs_eoc <= wbs_bte_i==linear;
|
1790 |
|
|
else if (wbs_eoc_alert & (a_rd | a_wr))
|
1791 |
|
|
wbs_eoc <= 1'b1;
|
1792 |
|
|
cnt_shreg_ce_clear # ( .length(16))
|
1793 |
|
|
cnt0 (
|
1794 |
|
|
.cke(wbs_ack_o),
|
1795 |
|
|
.clear(wbs_eoc),
|
1796 |
|
|
.q(wbs_count),
|
1797 |
|
|
.rst(wbs_rst),
|
1798 |
|
|
.clk(wbs_clk));
|
1799 |
|
|
always @ (posedge wbs_clk or posedge wbs_rst)
|
1800 |
|
|
if (wbs_rst)
|
1801 |
|
|
wbs <= wbs_adr;
|
1802 |
|
|
else
|
1803 |
|
|
if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & !a_fifo_full)
|
1804 |
|
|
wbs <= wbs_data;
|
1805 |
|
|
else if (wbs_eoc & wbs_ack_o)
|
1806 |
|
|
wbs <= wbs_adr;
|
1807 |
|
|
// wbs FIFO
|
1808 |
|
|
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,wbs_bte_i,wbs_cti_i} : {wbs_dat_i,wbs_sel_i};
|
1809 |
|
|
assign a_wr = (wbs==wbs_adr) ? wbs_cyc_i & wbs_stb_i & !a_fifo_full :
|
1810 |
|
|
(wbs==wbs_data) ? wbs_we_i & wbs_stb_i & !a_fifo_full :
|
1811 |
|
|
1'b0;
|
1812 |
|
|
assign a_rd = !a_fifo_empty;
|
1813 |
|
|
always @ (posedge wbs_clk or posedge wbs_rst)
|
1814 |
|
|
if (wbs_rst)
|
1815 |
|
|
a_rd_reg <= 1'b0;
|
1816 |
|
|
else
|
1817 |
|
|
a_rd_reg <= a_rd;
|
1818 |
|
|
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
|
1819 |
|
|
assign wbs_dat_o = a_q[35:4];
|
1820 |
|
|
always @ (posedge wbs_clk or posedge wbs_rst)
|
1821 |
|
|
if (wbs_rst)
|
1822 |
|
|
{wbs_we_reg,wbs_bte_reg} <= {1'b0,2'b00};
|
1823 |
|
|
else
|
1824 |
|
|
{wbs_we_reg,wbs_bte_reg} <= {wbs_we_i,wbs_bte_i};
|
1825 |
|
|
// wbm FIFO
|
1826 |
|
|
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
|
1827 |
|
|
always @ (posedge wbm_clk or posedge wbm_rst)
|
1828 |
|
|
if (wbm_rst)
|
1829 |
|
|
wbm_eoc <= 1'b0;
|
1830 |
|
|
else
|
1831 |
|
|
if (wbm==wbm_adr0 & !b_fifo_empty)
|
1832 |
|
|
wbm_eoc <= b_q[4:3] == linear;
|
1833 |
|
|
else if (wbm_eoc_alert & wbm_ack_i)
|
1834 |
|
|
wbm_eoc <= 1'b1;
|
1835 |
|
|
always @ (posedge wbm_clk or posedge wbm_rst)
|
1836 |
|
|
if (wbm_rst)
|
1837 |
|
|
wbm <= wbm_adr0;
|
1838 |
|
|
else
|
1839 |
|
|
if ((wbm==wbm_adr0 & !b_fifo_empty) |
|
1840 |
|
|
(wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
|
1841 |
|
|
(wbm==wbm_adr1 & !wbm_we_o) |
|
1842 |
|
|
(wbm==wbm_data & wbm_ack_i & wbm_eoc))
|
1843 |
|
|
wbm <= {wbm[0],!(wbm[1] ^ wbm[0])}; // count sequence 00,01,10
|
1844 |
|
|
assign b_d = {wbm_dat_i,4'b1111};
|
1845 |
|
|
assign b_wr = !wbm_we_o & wbm_ack_i;
|
1846 |
|
|
assign b_rd_adr = (wbm==wbm_adr0 & !b_fifo_empty);
|
1847 |
|
|
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
|
1848 |
|
|
(wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
|
1849 |
|
|
1'b0;
|
1850 |
|
|
assign b_rd = b_rd_adr | b_rd_data;
|
1851 |
|
|
dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
|
1852 |
|
|
dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
|
1853 |
|
|
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
|
1854 |
|
|
cnt_shreg_ce_clear # ( .length(16))
|
1855 |
|
|
cnt1 (
|
1856 |
|
|
.cke(wbm_ack_i),
|
1857 |
|
|
.clear(wbm_eoc),
|
1858 |
|
|
.q(wbm_count),
|
1859 |
|
|
.rst(wbm_rst),
|
1860 |
|
|
.clk(wbm_clk));
|
1861 |
|
|
assign wbm_cyc_o = wbm==wbm_data;
|
1862 |
|
|
assign wbm_stb_o = (wbm==wbm_data & wbm_we_o) ? !b_fifo_empty :
|
1863 |
|
|
(wbm==wbm_data) ? 1'b1 :
|
1864 |
|
|
1'b0;
|
1865 |
|
|
always @ (posedge wbm_clk or posedge wbm_rst)
|
1866 |
|
|
if (wbm_rst)
|
1867 |
|
|
{wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
|
1868 |
|
|
else begin
|
1869 |
|
|
if (wbm==wbm_adr0 & !b_fifo_empty)
|
1870 |
|
|
{wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
|
1871 |
|
|
else if (wbm_eoc_alert & wbm_ack_i)
|
1872 |
|
|
wbm_cti_o <= endofburst;
|
1873 |
|
|
end
|
1874 |
|
|
//async_fifo_dw_simplex_top
|
1875 |
|
|
vl_fifo_2r2w_async_simplex
|
1876 |
|
|
# ( .data_width(36), .addr_width(addr_width))
|
1877 |
|
|
fifo (
|
1878 |
|
|
// a side
|
1879 |
|
|
.a_d(a_d),
|
1880 |
|
|
.a_wr(a_wr),
|
1881 |
|
|
.a_fifo_full(a_fifo_full),
|
1882 |
|
|
.a_q(a_q),
|
1883 |
|
|
.a_rd(a_rd),
|
1884 |
|
|
.a_fifo_empty(a_fifo_empty),
|
1885 |
|
|
.a_clk(wbs_clk),
|
1886 |
|
|
.a_rst(wbs_rst),
|
1887 |
|
|
// b side
|
1888 |
|
|
.b_d(b_d),
|
1889 |
|
|
.b_wr(b_wr),
|
1890 |
|
|
.b_fifo_full(b_fifo_full),
|
1891 |
|
|
.b_q(b_q),
|
1892 |
|
|
.b_rd(b_rd),
|
1893 |
|
|
.b_fifo_empty(b_fifo_empty),
|
1894 |
|
|
.b_clk(wbm_clk),
|
1895 |
|
|
.b_rst(wbm_rst)
|
1896 |
|
|
);
|
1897 |
|
|
endmodule
|