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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Blame information for rev 130

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Line No. Rev Author Line
1 60 unneback
// default SYN_KEEP definition
2 98 unneback
    // ACTEL FPGA should not use logic to handle rw collision
3 97 unneback
// size to width
4 6 unneback
//////////////////////////////////////////////////////////////////////
5
////                                                              ////
6
////  Versatile library, clock and reset                          ////
7
////                                                              ////
8
////  Description                                                 ////
9
////  Logic related to clock and reset                            ////
10
////                                                              ////
11
////                                                              ////
12
////  To Do:                                                      ////
13
////   - add more different registers                             ////
14
////                                                              ////
15
////  Author(s):                                                  ////
16
////      - Michael Unneback, unneback@opencores.org              ////
17
////        ORSoC AB                                              ////
18
////                                                              ////
19
//////////////////////////////////////////////////////////////////////
20
////                                                              ////
21
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
22
////                                                              ////
23
//// This source file may be used and distributed without         ////
24
//// restriction provided that this copyright statement is not    ////
25
//// removed from the file and that any derivative work contains  ////
26
//// the original copyright notice and the associated disclaimer. ////
27
////                                                              ////
28
//// This source file is free software; you can redistribute it   ////
29
//// and/or modify it under the terms of the GNU Lesser General   ////
30
//// Public License as published by the Free Software Foundation; ////
31
//// either version 2.1 of the License, or (at your option) any   ////
32
//// later version.                                               ////
33
////                                                              ////
34
//// This source is distributed in the hope that it will be       ////
35
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
36
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
37
//// PURPOSE.  See the GNU Lesser General Public License for more ////
38
//// details.                                                     ////
39
////                                                              ////
40
//// You should have received a copy of the GNU Lesser General    ////
41
//// Public License along with this source; if not, download it   ////
42
//// from http://www.opencores.org/lgpl.shtml                     ////
43
////                                                              ////
44
//////////////////////////////////////////////////////////////////////
45 48 unneback
`timescale 1 ns/100 ps
46 6 unneback
// Global buffer
47
// usage:
48
// use to enable global buffers for high fan out signals such as clock and reset
49
// Version: 8.4 8.4.0.33
50
module gbuf(GL,CLK);
51
output GL;
52
input  CLK;
53
    wire GND;
54
    GND GND_1_net(.Y(GND));
55
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
56
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
57
endmodule
58
`timescale 1 ns/1 ns
59
module vl_gbuf ( i, o);
60
input i;
61
output o;
62
`ifdef SIM_GBUF
63
assign o=i;
64
`else
65
gbuf gbuf_i0 ( .CLK(i), .GL(o));
66
`endif
67
endmodule
68
 //ACTEL
69
// sync reset
70 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
71 6 unneback
// output active high global reset sync with two DFFs 
72
`timescale 1 ns/100 ps
73
module vl_sync_rst ( rst_n_i, rst_o, clk);
74
input rst_n_i, clk;
75
output rst_o;
76 18 unneback
reg [1:0] tmp;
77 6 unneback
always @ (posedge clk or negedge rst_n_i)
78
if (!rst_n_i)
79 17 unneback
        tmp <= 2'b11;
80 6 unneback
else
81 33 unneback
        tmp <= {1'b0,tmp[1]};
82 17 unneback
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
83 6 unneback
endmodule
84
// vl_pll
85 32 unneback
///////////////////////////////////////////////////////////////////////////////
86 17 unneback
`timescale 1 ps/1 ps
87 6 unneback
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
88
parameter index = 0;
89
parameter number_of_clk = 1;
90 17 unneback
parameter period_time_0 = 20000;
91
parameter period_time_1 = 20000;
92
parameter period_time_2 = 20000;
93
parameter lock_delay = 2000000;
94 6 unneback
input clk_i, rst_n_i;
95
output lock;
96
output reg [0:number_of_clk-1] clk_o;
97
output [0:number_of_clk-1] rst_o;
98
`ifdef SIM_PLL
99
always
100
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
101
generate if (number_of_clk > 1)
102
always
103
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
104
endgenerate
105
generate if (number_of_clk > 2)
106
always
107
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
108
endgenerate
109
genvar i;
110
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
111
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
112
end
113
endgenerate
114
assign #lock_delay lock = rst_n_i;
115
endmodule
116
`else
117
generate if (number_of_clk==1 & index==0) begin
118
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
119
end
120
endgenerate // index==0
121
generate if (number_of_clk==1 & index==1) begin
122
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
123
end
124
endgenerate // index==1
125
generate if (number_of_clk==1 & index==2) begin
126
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
127
end
128
endgenerate // index==2
129
generate if (number_of_clk==1 & index==3) begin
130
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
131
end
132
endgenerate // index==0
133
generate if (number_of_clk==2 & index==0) begin
134
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
135
end
136
endgenerate // index==0
137
generate if (number_of_clk==2 & index==1) begin
138
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
139
end
140
endgenerate // index==1
141
generate if (number_of_clk==2 & index==2) begin
142
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
143
end
144
endgenerate // index==2
145
generate if (number_of_clk==2 & index==3) begin
146
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
147
end
148
endgenerate // index==0
149
generate if (number_of_clk==3 & index==0) begin
150
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
151
end
152
endgenerate // index==0
153
generate if (number_of_clk==3 & index==1) begin
154
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
155
end
156
endgenerate // index==1
157
generate if (number_of_clk==3 & index==2) begin
158
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
159
end
160
endgenerate // index==2
161
generate if (number_of_clk==3 & index==3) begin
162
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
163
end
164
endgenerate // index==0
165
genvar i;
166
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
167 40 unneback
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
168 6 unneback
end
169
endgenerate
170
endmodule
171
`endif
172 32 unneback
///////////////////////////////////////////////////////////////////////////////
173 6 unneback
 //actel
174
//////////////////////////////////////////////////////////////////////
175
////                                                              ////
176
////  Versatile library, registers                                ////
177
////                                                              ////
178
////  Description                                                 ////
179
////  Different type of registers                                 ////
180
////                                                              ////
181
////                                                              ////
182
////  To Do:                                                      ////
183
////   - add more different registers                             ////
184
////                                                              ////
185
////  Author(s):                                                  ////
186
////      - Michael Unneback, unneback@opencores.org              ////
187
////        ORSoC AB                                              ////
188
////                                                              ////
189
//////////////////////////////////////////////////////////////////////
190
////                                                              ////
191
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
192
////                                                              ////
193
//// This source file may be used and distributed without         ////
194
//// restriction provided that this copyright statement is not    ////
195
//// removed from the file and that any derivative work contains  ////
196
//// the original copyright notice and the associated disclaimer. ////
197
////                                                              ////
198
//// This source file is free software; you can redistribute it   ////
199
//// and/or modify it under the terms of the GNU Lesser General   ////
200
//// Public License as published by the Free Software Foundation; ////
201
//// either version 2.1 of the License, or (at your option) any   ////
202
//// later version.                                               ////
203
////                                                              ////
204
//// This source is distributed in the hope that it will be       ////
205
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
206
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
207
//// PURPOSE.  See the GNU Lesser General Public License for more ////
208
//// details.                                                     ////
209
////                                                              ////
210
//// You should have received a copy of the GNU Lesser General    ////
211
//// Public License along with this source; if not, download it   ////
212
//// from http://www.opencores.org/lgpl.shtml                     ////
213
////                                                              ////
214
//////////////////////////////////////////////////////////////////////
215 18 unneback
module vl_dff ( d, q, clk, rst);
216 6 unneback
        parameter width = 1;
217
        parameter reset_value = 0;
218
        input [width-1:0] d;
219
        input clk, rst;
220
        output reg [width-1:0] q;
221
        always @ (posedge clk or posedge rst)
222
        if (rst)
223
                q <= reset_value;
224
        else
225
                q <= d;
226
endmodule
227 18 unneback
module vl_dff_array ( d, q, clk, rst);
228 6 unneback
        parameter width = 1;
229
        parameter depth = 2;
230
        parameter reset_value = 1'b0;
231
        input [width-1:0] d;
232
        input clk, rst;
233
        output [width-1:0] q;
234
        reg  [0:depth-1] q_tmp [width-1:0];
235
        integer i;
236
        always @ (posedge clk or posedge rst)
237
        if (rst) begin
238
            for (i=0;i<depth;i=i+1)
239
                q_tmp[i] <= {width{reset_value}};
240
        end else begin
241
            q_tmp[0] <= d;
242
            for (i=1;i<depth;i=i+1)
243
                q_tmp[i] <= q_tmp[i-1];
244
        end
245
    assign q = q_tmp[depth-1];
246
endmodule
247 18 unneback
module vl_dff_ce ( d, ce, q, clk, rst);
248 6 unneback
        parameter width = 1;
249
        parameter reset_value = 0;
250
        input [width-1:0] d;
251
        input ce, clk, rst;
252
        output reg [width-1:0] q;
253
        always @ (posedge clk or posedge rst)
254
        if (rst)
255
                q <= reset_value;
256
        else
257
                if (ce)
258
                        q <= d;
259
endmodule
260 18 unneback
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
261 8 unneback
        parameter width = 1;
262
        parameter reset_value = 0;
263
        input [width-1:0] d;
264 10 unneback
        input ce, clear, clk, rst;
265 8 unneback
        output reg [width-1:0] q;
266
        always @ (posedge clk or posedge rst)
267
        if (rst)
268
            q <= reset_value;
269
        else
270
            if (ce)
271
                if (clear)
272
                    q <= {width{1'b0}};
273
                else
274
                    q <= d;
275
endmodule
276 24 unneback
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
277
        parameter width = 1;
278
        parameter reset_value = 0;
279
        input [width-1:0] d;
280
        input ce, set, clk, rst;
281
        output reg [width-1:0] q;
282
        always @ (posedge clk or posedge rst)
283
        if (rst)
284
            q <= reset_value;
285
        else
286
            if (ce)
287
                if (set)
288
                    q <= {width{1'b1}};
289
                else
290
                    q <= d;
291
endmodule
292 29 unneback
module vl_spr ( sp, r, q, clk, rst);
293 64 unneback
        //parameter width = 1;
294
        parameter reset_value = 1'b0;
295 29 unneback
        input sp, r;
296
        output reg q;
297
        input clk, rst;
298
        always @ (posedge clk or posedge rst)
299
        if (rst)
300
            q <= reset_value;
301
        else
302
            if (sp)
303
                q <= 1'b1;
304
            else if (r)
305
                q <= 1'b0;
306
endmodule
307
module vl_srp ( s, rp, q, clk, rst);
308
        parameter width = 1;
309
        parameter reset_value = 0;
310
        input s, rp;
311
        output reg q;
312
        input clk, rst;
313
        always @ (posedge clk or posedge rst)
314
        if (rst)
315
            q <= reset_value;
316
        else
317
            if (rp)
318
                q <= 1'b0;
319
            else if (s)
320
                q <= 1'b1;
321
endmodule
322 18 unneback
module vl_dff_sr ( aclr, aset, clock, data, q);
323 6 unneback
    input         aclr;
324
    input         aset;
325
    input         clock;
326
    input         data;
327
    output reg    q;
328
   always @ (posedge clock or posedge aclr or posedge aset)
329
     if (aclr)
330
       q <= 1'b0;
331
     else if (aset)
332
       q <= 1'b1;
333
     else
334
       q <= data;
335
endmodule
336
// LATCH
337
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
338 40 unneback
module vl_latch ( d, le, q, clk);
339 6 unneback
input d, le;
340 48 unneback
input clk;
341
always @ (le or d)
342 60 unneback
if (le)
343 48 unneback
    d <= q;
344 6 unneback
endmodule
345 18 unneback
module vl_shreg ( d, q, clk, rst);
346 17 unneback
parameter depth = 10;
347
input d;
348
output q;
349
input clk, rst;
350
reg [1:depth] dffs;
351
always @ (posedge clk or posedge rst)
352
if (rst)
353
    dffs <= {depth{1'b0}};
354
else
355
    dffs <= {d,dffs[1:depth-1]};
356
assign q = dffs[depth];
357
endmodule
358 18 unneback
module vl_shreg_ce ( d, ce, q, clk, rst);
359 17 unneback
parameter depth = 10;
360
input d, ce;
361
output q;
362
input clk, rst;
363
reg [1:depth] dffs;
364
always @ (posedge clk or posedge rst)
365
if (rst)
366
    dffs <= {depth{1'b0}};
367
else
368
    if (ce)
369
        dffs <= {d,dffs[1:depth-1]};
370
assign q = dffs[depth];
371
endmodule
372 18 unneback
module vl_delay ( d, q, clk, rst);
373 15 unneback
parameter depth = 10;
374
input d;
375
output q;
376
input clk, rst;
377
reg [1:depth] dffs;
378
always @ (posedge clk or posedge rst)
379
if (rst)
380
    dffs <= {depth{1'b0}};
381
else
382
    dffs <= {d,dffs[1:depth-1]};
383
assign q = dffs[depth];
384
endmodule
385 18 unneback
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
386 17 unneback
parameter depth = 10;
387
input d;
388
output q, emptyflag;
389
input clk, rst;
390
reg [1:depth] dffs;
391
always @ (posedge clk or posedge rst)
392
if (rst)
393
    dffs <= {depth{1'b0}};
394
else
395
    dffs <= {d,dffs[1:depth-1]};
396
assign q = dffs[depth];
397
assign emptyflag = !(|dffs);
398
endmodule
399 98 unneback
module vl_pulse2toggle ( pl, q, clk, rst);
400 94 unneback
input pl;
401 98 unneback
output reg q;
402 94 unneback
input clk, rst;
403
always @ (posedge clk or posedge rst)
404
if (rst)
405
    q <= 1'b0;
406
else
407
    q <= pl ^ q;
408
endmodule
409 98 unneback
module vl_toggle2pulse (d, pl, clk, rst);
410 94 unneback
input d;
411
output pl;
412
input clk, rst;
413
reg dff;
414
always @ (posedge clk or posedge rst)
415
if (rst)
416
    dff <= 1'b0;
417
else
418
    dff <= d;
419 98 unneback
assign pl = d ^ dff;
420 94 unneback
endmodule
421
module vl_synchronizer (d, q, clk, rst);
422
input d;
423
output reg q;
424 116 unneback
input clk, rst;
425 94 unneback
reg dff;
426
always @ (posedge clk or posedge rst)
427
if (rst)
428 100 unneback
    {q,dff} <= 2'b00;
429 94 unneback
else
430 100 unneback
    {q,dff} <= {dff,d};
431 94 unneback
endmodule
432 97 unneback
module vl_cdc ( start_pl, take_it_pl, take_it_grant_pl, got_it_pl, clk_src, rst_src, clk_dst, rst_dst);
433 94 unneback
input start_pl;
434
output take_it_pl;
435
input take_it_grant_pl; // note: connect to take_it_pl to generate automatic ack
436
output got_it_pl;
437
input clk_src, rst_src;
438
input clk_dst, rst_dst;
439
wire take_it_tg, take_it_tg_sync;
440
wire got_it_tg, got_it_tg_sync;
441
// src -> dst
442
vl_pulse2toggle p2t0 (
443
    .pl(start_pl),
444
    .q(take_it_tg),
445
    .clk(clk_src),
446
    .rst(rst_src));
447
vl_synchronizer sync0 (
448
    .d(take_it_tg),
449
    .q(take_it_tg_sync),
450
    .clk(clk_dst),
451
    .rst(rst_dst));
452
vl_toggle2pulse t2p0 (
453 100 unneback
    .d(take_it_tg_sync),
454 94 unneback
    .pl(take_it_pl),
455
    .clk(clk_dst),
456
    .rst(rst_dst));
457
// dst -> src
458 98 unneback
vl_pulse2toggle p2t1 (
459 94 unneback
    .pl(take_it_grant_pl),
460
    .q(got_it_tg),
461
    .clk(clk_dst),
462
    .rst(rst_dst));
463
vl_synchronizer sync1 (
464
    .d(got_it_tg),
465
    .q(got_it_tg_sync),
466
    .clk(clk_src),
467
    .rst(rst_src));
468
vl_toggle2pulse t2p1 (
469 100 unneback
    .d(got_it_tg_sync),
470 94 unneback
    .pl(got_it_pl),
471
    .clk(clk_src),
472
    .rst(rst_src));
473
endmodule
474 6 unneback
//////////////////////////////////////////////////////////////////////
475
////                                                              ////
476 18 unneback
////  Logic functions                                             ////
477
////                                                              ////
478
////  Description                                                 ////
479
////  Logic functions such as multiplexers                        ////
480
////                                                              ////
481
////                                                              ////
482
////  To Do:                                                      ////
483
////   -                                                          ////
484
////                                                              ////
485
////  Author(s):                                                  ////
486
////      - Michael Unneback, unneback@opencores.org              ////
487
////        ORSoC AB                                              ////
488
////                                                              ////
489
//////////////////////////////////////////////////////////////////////
490
////                                                              ////
491
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
492
////                                                              ////
493
//// This source file may be used and distributed without         ////
494
//// restriction provided that this copyright statement is not    ////
495
//// removed from the file and that any derivative work contains  ////
496
//// the original copyright notice and the associated disclaimer. ////
497
////                                                              ////
498
//// This source file is free software; you can redistribute it   ////
499
//// and/or modify it under the terms of the GNU Lesser General   ////
500
//// Public License as published by the Free Software Foundation; ////
501
//// either version 2.1 of the License, or (at your option) any   ////
502
//// later version.                                               ////
503
////                                                              ////
504
//// This source is distributed in the hope that it will be       ////
505
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
506
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
507
//// PURPOSE.  See the GNU Lesser General Public License for more ////
508
//// details.                                                     ////
509
////                                                              ////
510
//// You should have received a copy of the GNU Lesser General    ////
511
//// Public License along with this source; if not, download it   ////
512
//// from http://www.opencores.org/lgpl.shtml                     ////
513
////                                                              ////
514
//////////////////////////////////////////////////////////////////////
515 36 unneback
module vl_mux_andor ( a, sel, dout);
516
parameter width = 32;
517
parameter nr_of_ports = 4;
518
input [nr_of_ports*width-1:0] a;
519
input [nr_of_ports-1:0] sel;
520
output reg [width-1:0] dout;
521 38 unneback
integer i,j;
522 36 unneback
always @ (a, sel)
523
begin
524
    dout = a[width-1:0] & {width{sel[0]}};
525 42 unneback
    for (i=1;i<nr_of_ports;i=i+1)
526
        for (j=0;j<width;j=j+1)
527
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
528 36 unneback
end
529
endmodule
530 34 unneback
module vl_mux2_andor ( a1, a0, sel, dout);
531
parameter width = 32;
532 35 unneback
localparam nr_of_ports = 2;
533 34 unneback
input [width-1:0] a1, a0;
534
input [nr_of_ports-1:0] sel;
535
output [width-1:0] dout;
536 36 unneback
vl_mux_andor
537 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
538 36 unneback
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
539 34 unneback
endmodule
540
module vl_mux3_andor ( a2, a1, a0, sel, dout);
541
parameter width = 32;
542 35 unneback
localparam nr_of_ports = 3;
543 34 unneback
input [width-1:0] a2, a1, a0;
544
input [nr_of_ports-1:0] sel;
545
output [width-1:0] dout;
546 36 unneback
vl_mux_andor
547 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
548 36 unneback
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
549 34 unneback
endmodule
550 18 unneback
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
551
parameter width = 32;
552 35 unneback
localparam nr_of_ports = 4;
553 18 unneback
input [width-1:0] a3, a2, a1, a0;
554
input [nr_of_ports-1:0] sel;
555 22 unneback
output [width-1:0] dout;
556 36 unneback
vl_mux_andor
557 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
558 36 unneback
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
559 18 unneback
endmodule
560
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
561
parameter width = 32;
562 35 unneback
localparam nr_of_ports = 5;
563 18 unneback
input [width-1:0] a4, a3, a2, a1, a0;
564
input [nr_of_ports-1:0] sel;
565 22 unneback
output [width-1:0] dout;
566 36 unneback
vl_mux_andor
567 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
568 36 unneback
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
569 18 unneback
endmodule
570
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
571
parameter width = 32;
572 35 unneback
localparam nr_of_ports = 6;
573 18 unneback
input [width-1:0] a5, a4, a3, a2, a1, a0;
574
input [nr_of_ports-1:0] sel;
575 22 unneback
output [width-1:0] dout;
576 36 unneback
vl_mux_andor
577 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
578 36 unneback
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
579 18 unneback
endmodule
580 43 unneback
module vl_parity_generate (data, parity);
581
parameter word_size = 32;
582
parameter chunk_size = 8;
583
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
584
input [word_size-1:0] data;
585
output reg [word_size/chunk_size-1:0] parity;
586
integer i,j;
587
always @ (data)
588
for (i=0;i<word_size/chunk_size;i=i+1) begin
589
    parity[i] = parity_type;
590
    for (j=0;j<chunk_size;j=j+1) begin
591 46 unneback
        parity[i] = data[i*chunk_size+j] ^ parity[i];
592 43 unneback
    end
593
end
594
endmodule
595
module vl_parity_check( data, parity, parity_error);
596
parameter word_size = 32;
597
parameter chunk_size = 8;
598
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
599
input [word_size-1:0] data;
600
input [word_size/chunk_size-1:0] parity;
601
output parity_error;
602 44 unneback
reg [word_size/chunk_size-1:0] error_flag;
603 43 unneback
integer i,j;
604
always @ (data or parity)
605
for (i=0;i<word_size/chunk_size;i=i+1) begin
606
    error_flag[i] = parity[i] ^ parity_type;
607
    for (j=0;j<chunk_size;j=j+1) begin
608 46 unneback
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
609 43 unneback
    end
610
end
611
assign parity_error = |error_flag;
612
endmodule
613 18 unneback
//////////////////////////////////////////////////////////////////////
614
////                                                              ////
615 44 unneback
////  IO functions                                                ////
616
////                                                              ////
617
////  Description                                                 ////
618
////  IO functions such as IOB flip-flops                         ////
619
////                                                              ////
620
////                                                              ////
621
////  To Do:                                                      ////
622
////   -                                                          ////
623
////                                                              ////
624
////  Author(s):                                                  ////
625
////      - Michael Unneback, unneback@opencores.org              ////
626
////        ORSoC AB                                              ////
627
////                                                              ////
628
//////////////////////////////////////////////////////////////////////
629
////                                                              ////
630
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
631
////                                                              ////
632
//// This source file may be used and distributed without         ////
633
//// restriction provided that this copyright statement is not    ////
634
//// removed from the file and that any derivative work contains  ////
635
//// the original copyright notice and the associated disclaimer. ////
636
////                                                              ////
637
//// This source file is free software; you can redistribute it   ////
638
//// and/or modify it under the terms of the GNU Lesser General   ////
639
//// Public License as published by the Free Software Foundation; ////
640
//// either version 2.1 of the License, or (at your option) any   ////
641
//// later version.                                               ////
642
////                                                              ////
643
//// This source is distributed in the hope that it will be       ////
644
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
645
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
646
//// PURPOSE.  See the GNU Lesser General Public License for more ////
647
//// details.                                                     ////
648
////                                                              ////
649
//// You should have received a copy of the GNU Lesser General    ////
650
//// Public License along with this source; if not, download it   ////
651
//// from http://www.opencores.org/lgpl.shtml                     ////
652
////                                                              ////
653
//////////////////////////////////////////////////////////////////////
654 45 unneback
`timescale 1ns/1ns
655 44 unneback
module vl_o_dff (d_i, o_pad, clk, rst);
656
parameter width = 1;
657 45 unneback
parameter reset_value = {width{1'b0}};
658
input  [width-1:0]  d_i;
659 44 unneback
output [width-1:0] o_pad;
660
input clk, rst;
661
wire [width-1:0] d_i_int /*synthesis syn_keep = 1*/;
662 45 unneback
reg  [width-1:0] o_pad_int;
663 44 unneback
assign d_i_int = d_i;
664
genvar i;
665 45 unneback
generate
666 44 unneback
for (i=0;i<width;i=i+1) begin
667
    always @ (posedge clk or posedge rst)
668
    if (rst)
669 45 unneback
        o_pad_int[i] <= reset_value[i];
670 44 unneback
    else
671 45 unneback
        o_pad_int[i] <= d_i_int[i];
672
    assign #1 o_pad[i] = o_pad_int[i];
673 44 unneback
end
674
endgenerate
675
endmodule
676 45 unneback
`timescale 1ns/1ns
677 44 unneback
module vl_io_dff_oe ( d_i, d_o, oe, io_pad, clk, rst);
678
parameter width = 1;
679
input  [width-1:0] d_o;
680
output reg [width-1:0] d_i;
681
input oe;
682
inout [width-1:0] io_pad;
683
input clk, rst;
684
wire [width-1:0] oe_d /*synthesis syn_keep = 1*/;
685
reg [width-1:0] oe_q;
686
reg [width-1:0] d_o_q;
687
assign oe_d = {width{oe}};
688
genvar i;
689
generate
690
for (i=0;i<width;i=i+1) begin
691
    always @ (posedge clk or posedge rst)
692
    if (rst)
693
        oe_q[i] <= 1'b0;
694
    else
695
        oe_q[i] <= oe_d[i];
696
    always @ (posedge clk or posedge rst)
697
    if (rst)
698
        d_o_q[i] <= 1'b0;
699
    else
700
        d_o_q[i] <= d_o[i];
701
    always @ (posedge clk or posedge rst)
702
    if (rst)
703
        d_i[i] <= 1'b0;
704
    else
705
        d_i[i] <= io_pad[i];
706 45 unneback
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
707 44 unneback
end
708
endgenerate
709
endmodule
710
//////////////////////////////////////////////////////////////////////
711
////                                                              ////
712 6 unneback
////  Versatile counter                                           ////
713
////                                                              ////
714
////  Description                                                 ////
715
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
716
////  counter                                                     ////
717
////                                                              ////
718
////  To Do:                                                      ////
719
////   - add LFSR with more taps                                  ////
720
////                                                              ////
721
////  Author(s):                                                  ////
722
////      - Michael Unneback, unneback@opencores.org              ////
723
////        ORSoC AB                                              ////
724
////                                                              ////
725
//////////////////////////////////////////////////////////////////////
726
////                                                              ////
727
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
728
////                                                              ////
729
//// This source file may be used and distributed without         ////
730
//// restriction provided that this copyright statement is not    ////
731
//// removed from the file and that any derivative work contains  ////
732
//// the original copyright notice and the associated disclaimer. ////
733
////                                                              ////
734
//// This source file is free software; you can redistribute it   ////
735
//// and/or modify it under the terms of the GNU Lesser General   ////
736
//// Public License as published by the Free Software Foundation; ////
737
//// either version 2.1 of the License, or (at your option) any   ////
738
//// later version.                                               ////
739
////                                                              ////
740
//// This source is distributed in the hope that it will be       ////
741
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
742
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
743
//// PURPOSE.  See the GNU Lesser General Public License for more ////
744
//// details.                                                     ////
745
////                                                              ////
746
//// You should have received a copy of the GNU Lesser General    ////
747
//// Public License along with this source; if not, download it   ////
748
//// from http://www.opencores.org/lgpl.shtml                     ////
749
////                                                              ////
750
//////////////////////////////////////////////////////////////////////
751
// binary counter
752 40 unneback
module vl_cnt_bin_ce (
753
 cke, q, rst, clk);
754 22 unneback
   parameter length = 4;
755 6 unneback
   input cke;
756
   output [length:1] q;
757
   input rst;
758
   input clk;
759
   parameter clear_value = 0;
760
   parameter set_value = 1;
761
   parameter wrap_value = 0;
762
   parameter level1_value = 15;
763
   reg  [length:1] qi;
764
   wire [length:1] q_next;
765
   assign q_next = qi + {{length-1{1'b0}},1'b1};
766
   always @ (posedge clk or posedge rst)
767
     if (rst)
768
       qi <= {length{1'b0}};
769
     else
770
     if (cke)
771
       qi <= q_next;
772
   assign q = qi;
773
endmodule
774
//////////////////////////////////////////////////////////////////////
775
////                                                              ////
776
////  Versatile counter                                           ////
777
////                                                              ////
778
////  Description                                                 ////
779
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
780
////  counter                                                     ////
781
////                                                              ////
782
////  To Do:                                                      ////
783
////   - add LFSR with more taps                                  ////
784
////                                                              ////
785
////  Author(s):                                                  ////
786
////      - Michael Unneback, unneback@opencores.org              ////
787
////        ORSoC AB                                              ////
788
////                                                              ////
789
//////////////////////////////////////////////////////////////////////
790
////                                                              ////
791
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
792
////                                                              ////
793
//// This source file may be used and distributed without         ////
794
//// restriction provided that this copyright statement is not    ////
795
//// removed from the file and that any derivative work contains  ////
796
//// the original copyright notice and the associated disclaimer. ////
797
////                                                              ////
798
//// This source file is free software; you can redistribute it   ////
799
//// and/or modify it under the terms of the GNU Lesser General   ////
800
//// Public License as published by the Free Software Foundation; ////
801
//// either version 2.1 of the License, or (at your option) any   ////
802
//// later version.                                               ////
803
////                                                              ////
804
//// This source is distributed in the hope that it will be       ////
805
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
806
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
807
//// PURPOSE.  See the GNU Lesser General Public License for more ////
808
//// details.                                                     ////
809
////                                                              ////
810
//// You should have received a copy of the GNU Lesser General    ////
811
//// Public License along with this source; if not, download it   ////
812
//// from http://www.opencores.org/lgpl.shtml                     ////
813
////                                                              ////
814
//////////////////////////////////////////////////////////////////////
815
// binary counter
816 40 unneback
module vl_cnt_bin_ce_rew_zq_l1 (
817
 cke, rew, zq, level1, rst, clk);
818 6 unneback
   parameter length = 4;
819
   input cke;
820
   input rew;
821 25 unneback
   output reg zq;
822
   output reg level1;
823
   input rst;
824
   input clk;
825
   parameter clear_value = 0;
826
   parameter set_value = 1;
827
   parameter wrap_value = 1;
828
   parameter level1_value = 15;
829 29 unneback
   wire clear;
830 30 unneback
   assign clear = 1'b0;
831 25 unneback
   reg  [length:1] qi;
832
   wire  [length:1] q_next, q_next_fw, q_next_rew;
833
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
834
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
835
   assign q_next = rew ? q_next_rew : q_next_fw;
836
   always @ (posedge clk or posedge rst)
837
     if (rst)
838
       qi <= {length{1'b0}};
839
     else
840
     if (cke)
841
       qi <= q_next;
842
   always @ (posedge clk or posedge rst)
843
     if (rst)
844
       zq <= 1'b1;
845
     else
846
     if (cke)
847
       zq <= q_next == {length{1'b0}};
848
    always @ (posedge clk or posedge rst)
849
    if (rst)
850
        level1 <= 1'b0;
851
    else
852
    if (cke)
853 29 unneback
    if (clear)
854
        level1 <= 1'b0;
855
    else if (q_next == level1_value)
856 25 unneback
        level1 <= 1'b1;
857
    else if (qi == level1_value & rew)
858
        level1 <= 1'b0;
859
endmodule
860
//////////////////////////////////////////////////////////////////////
861
////                                                              ////
862
////  Versatile counter                                           ////
863
////                                                              ////
864
////  Description                                                 ////
865
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
866
////  counter                                                     ////
867
////                                                              ////
868
////  To Do:                                                      ////
869
////   - add LFSR with more taps                                  ////
870
////                                                              ////
871
////  Author(s):                                                  ////
872
////      - Michael Unneback, unneback@opencores.org              ////
873
////        ORSoC AB                                              ////
874
////                                                              ////
875
//////////////////////////////////////////////////////////////////////
876
////                                                              ////
877
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
878
////                                                              ////
879
//// This source file may be used and distributed without         ////
880
//// restriction provided that this copyright statement is not    ////
881
//// removed from the file and that any derivative work contains  ////
882
//// the original copyright notice and the associated disclaimer. ////
883
////                                                              ////
884
//// This source file is free software; you can redistribute it   ////
885
//// and/or modify it under the terms of the GNU Lesser General   ////
886
//// Public License as published by the Free Software Foundation; ////
887
//// either version 2.1 of the License, or (at your option) any   ////
888
//// later version.                                               ////
889
////                                                              ////
890
//// This source is distributed in the hope that it will be       ////
891
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
892
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
893
//// PURPOSE.  See the GNU Lesser General Public License for more ////
894
//// details.                                                     ////
895
////                                                              ////
896
//// You should have received a copy of the GNU Lesser General    ////
897
//// Public License along with this source; if not, download it   ////
898
//// from http://www.opencores.org/lgpl.shtml                     ////
899
////                                                              ////
900
//////////////////////////////////////////////////////////////////////
901
// binary counter
902 40 unneback
module vl_cnt_bin_ce_rew_q_zq_l1 (
903
 cke, rew, q, zq, level1, rst, clk);
904 25 unneback
   parameter length = 4;
905
   input cke;
906
   input rew;
907
   output [length:1] q;
908
   output reg zq;
909
   output reg level1;
910
   input rst;
911
   input clk;
912
   parameter clear_value = 0;
913
   parameter set_value = 1;
914
   parameter wrap_value = 1;
915
   parameter level1_value = 15;
916 29 unneback
   wire clear;
917 30 unneback
   assign clear = 1'b0;
918 25 unneback
   reg  [length:1] qi;
919
   wire  [length:1] q_next, q_next_fw, q_next_rew;
920
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
921
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
922
   assign q_next = rew ? q_next_rew : q_next_fw;
923
   always @ (posedge clk or posedge rst)
924
     if (rst)
925
       qi <= {length{1'b0}};
926
     else
927
     if (cke)
928
       qi <= q_next;
929
   assign q = qi;
930
   always @ (posedge clk or posedge rst)
931
     if (rst)
932
       zq <= 1'b1;
933
     else
934
     if (cke)
935
       zq <= q_next == {length{1'b0}};
936
    always @ (posedge clk or posedge rst)
937
    if (rst)
938
        level1 <= 1'b0;
939
    else
940
    if (cke)
941 29 unneback
    if (clear)
942
        level1 <= 1'b0;
943
    else if (q_next == level1_value)
944 25 unneback
        level1 <= 1'b1;
945
    else if (qi == level1_value & rew)
946
        level1 <= 1'b0;
947
endmodule
948
//////////////////////////////////////////////////////////////////////
949
////                                                              ////
950
////  Versatile counter                                           ////
951
////                                                              ////
952
////  Description                                                 ////
953
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
954
////  counter                                                     ////
955
////                                                              ////
956
////  To Do:                                                      ////
957
////   - add LFSR with more taps                                  ////
958
////                                                              ////
959
////  Author(s):                                                  ////
960
////      - Michael Unneback, unneback@opencores.org              ////
961
////        ORSoC AB                                              ////
962
////                                                              ////
963
//////////////////////////////////////////////////////////////////////
964
////                                                              ////
965
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
966
////                                                              ////
967
//// This source file may be used and distributed without         ////
968
//// restriction provided that this copyright statement is not    ////
969
//// removed from the file and that any derivative work contains  ////
970
//// the original copyright notice and the associated disclaimer. ////
971
////                                                              ////
972
//// This source file is free software; you can redistribute it   ////
973
//// and/or modify it under the terms of the GNU Lesser General   ////
974
//// Public License as published by the Free Software Foundation; ////
975
//// either version 2.1 of the License, or (at your option) any   ////
976
//// later version.                                               ////
977
////                                                              ////
978
//// This source is distributed in the hope that it will be       ////
979
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
980
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
981
//// PURPOSE.  See the GNU Lesser General Public License for more ////
982
//// details.                                                     ////
983
////                                                              ////
984
//// You should have received a copy of the GNU Lesser General    ////
985
//// Public License along with this source; if not, download it   ////
986
//// from http://www.opencores.org/lgpl.shtml                     ////
987
////                                                              ////
988
//////////////////////////////////////////////////////////////////////
989 75 unneback
// LFSR counter
990
module vl_cnt_lfsr_ce (
991
 cke, zq, rst, clk);
992
   parameter length = 4;
993
   input cke;
994
   output reg zq;
995
   input rst;
996
   input clk;
997
   parameter clear_value = 0;
998
   parameter set_value = 1;
999
   parameter wrap_value = 0;
1000
   parameter level1_value = 15;
1001
   reg  [length:1] qi;
1002
   reg lfsr_fb;
1003
   wire [length:1] q_next;
1004
   reg [32:1] polynom;
1005
   integer i;
1006
   always @ (qi)
1007
   begin
1008
        case (length)
1009
         2: polynom = 32'b11;                               // 0x3
1010
         3: polynom = 32'b110;                              // 0x6
1011
         4: polynom = 32'b1100;                             // 0xC
1012
         5: polynom = 32'b10100;                            // 0x14
1013
         6: polynom = 32'b110000;                           // 0x30
1014
         7: polynom = 32'b1100000;                          // 0x60
1015
         8: polynom = 32'b10111000;                         // 0xb8
1016
         9: polynom = 32'b100010000;                        // 0x110
1017
        10: polynom = 32'b1001000000;                       // 0x240
1018
        11: polynom = 32'b10100000000;                      // 0x500
1019
        12: polynom = 32'b100000101001;                     // 0x829
1020
        13: polynom = 32'b1000000001100;                    // 0x100C
1021
        14: polynom = 32'b10000000010101;                   // 0x2015
1022
        15: polynom = 32'b110000000000000;                  // 0x6000
1023
        16: polynom = 32'b1101000000001000;                 // 0xD008
1024
        17: polynom = 32'b10010000000000000;                // 0x12000
1025
        18: polynom = 32'b100000010000000000;               // 0x20400
1026
        19: polynom = 32'b1000000000000100011;              // 0x40023
1027
        20: polynom = 32'b10010000000000000000;             // 0x90000
1028
        21: polynom = 32'b101000000000000000000;            // 0x140000
1029
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1030
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1031
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1032
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1033
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1034
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1035
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1036
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1037
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1038
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1039
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1040
        default: polynom = 32'b0;
1041
        endcase
1042
        lfsr_fb = qi[length];
1043
        for (i=length-1; i>=1; i=i-1) begin
1044
            if (polynom[i])
1045
                lfsr_fb = lfsr_fb  ~^ qi[i];
1046
        end
1047
    end
1048
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1049
   always @ (posedge clk or posedge rst)
1050
     if (rst)
1051
       qi <= {length{1'b0}};
1052
     else
1053
     if (cke)
1054
       qi <= q_next;
1055
   always @ (posedge clk or posedge rst)
1056
     if (rst)
1057
       zq <= 1'b1;
1058
     else
1059
     if (cke)
1060
       zq <= q_next == {length{1'b0}};
1061
endmodule
1062
//////////////////////////////////////////////////////////////////////
1063
////                                                              ////
1064
////  Versatile counter                                           ////
1065
////                                                              ////
1066
////  Description                                                 ////
1067
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1068
////  counter                                                     ////
1069
////                                                              ////
1070
////  To Do:                                                      ////
1071
////   - add LFSR with more taps                                  ////
1072
////                                                              ////
1073
////  Author(s):                                                  ////
1074
////      - Michael Unneback, unneback@opencores.org              ////
1075
////        ORSoC AB                                              ////
1076
////                                                              ////
1077
//////////////////////////////////////////////////////////////////////
1078
////                                                              ////
1079
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1080
////                                                              ////
1081
//// This source file may be used and distributed without         ////
1082
//// restriction provided that this copyright statement is not    ////
1083
//// removed from the file and that any derivative work contains  ////
1084
//// the original copyright notice and the associated disclaimer. ////
1085
////                                                              ////
1086
//// This source file is free software; you can redistribute it   ////
1087
//// and/or modify it under the terms of the GNU Lesser General   ////
1088
//// Public License as published by the Free Software Foundation; ////
1089
//// either version 2.1 of the License, or (at your option) any   ////
1090
//// later version.                                               ////
1091
////                                                              ////
1092
//// This source is distributed in the hope that it will be       ////
1093
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1094
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1095
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1096
//// details.                                                     ////
1097
////                                                              ////
1098
//// You should have received a copy of the GNU Lesser General    ////
1099
//// Public License along with this source; if not, download it   ////
1100
//// from http://www.opencores.org/lgpl.shtml                     ////
1101
////                                                              ////
1102
//////////////////////////////////////////////////////////////////////
1103 6 unneback
// GRAY counter
1104 40 unneback
module vl_cnt_gray_ce_bin (
1105
 cke, q, q_bin, rst, clk);
1106 6 unneback
   parameter length = 4;
1107
   input cke;
1108
   output reg [length:1] q;
1109
   output [length:1] q_bin;
1110
   input rst;
1111
   input clk;
1112
   parameter clear_value = 0;
1113
   parameter set_value = 1;
1114
   parameter wrap_value = 8;
1115
   parameter level1_value = 15;
1116
   reg  [length:1] qi;
1117
   wire [length:1] q_next;
1118
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1119
   always @ (posedge clk or posedge rst)
1120
     if (rst)
1121
       qi <= {length{1'b0}};
1122
     else
1123
     if (cke)
1124
       qi <= q_next;
1125
   always @ (posedge clk or posedge rst)
1126
     if (rst)
1127
       q <= {length{1'b0}};
1128
     else
1129
       if (cke)
1130
         q <= (q_next>>1) ^ q_next;
1131
   assign q_bin = qi;
1132
endmodule
1133
//////////////////////////////////////////////////////////////////////
1134
////                                                              ////
1135
////  Versatile library, counters                                 ////
1136
////                                                              ////
1137
////  Description                                                 ////
1138
////  counters                                                    ////
1139
////                                                              ////
1140
////                                                              ////
1141
////  To Do:                                                      ////
1142
////   - add more counters                                        ////
1143
////                                                              ////
1144
////  Author(s):                                                  ////
1145
////      - Michael Unneback, unneback@opencores.org              ////
1146
////        ORSoC AB                                              ////
1147
////                                                              ////
1148
//////////////////////////////////////////////////////////////////////
1149
////                                                              ////
1150
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1151
////                                                              ////
1152
//// This source file may be used and distributed without         ////
1153
//// restriction provided that this copyright statement is not    ////
1154
//// removed from the file and that any derivative work contains  ////
1155
//// the original copyright notice and the associated disclaimer. ////
1156
////                                                              ////
1157
//// This source file is free software; you can redistribute it   ////
1158
//// and/or modify it under the terms of the GNU Lesser General   ////
1159
//// Public License as published by the Free Software Foundation; ////
1160
//// either version 2.1 of the License, or (at your option) any   ////
1161
//// later version.                                               ////
1162
////                                                              ////
1163
//// This source is distributed in the hope that it will be       ////
1164
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1165
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1166
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1167
//// details.                                                     ////
1168
////                                                              ////
1169
//// You should have received a copy of the GNU Lesser General    ////
1170
//// Public License along with this source; if not, download it   ////
1171
//// from http://www.opencores.org/lgpl.shtml                     ////
1172
////                                                              ////
1173
//////////////////////////////////////////////////////////////////////
1174 18 unneback
module vl_cnt_shreg_wrap ( q, rst, clk);
1175 6 unneback
   parameter length = 4;
1176
   output reg [0:length-1] q;
1177
   input rst;
1178
   input clk;
1179
    always @ (posedge clk or posedge rst)
1180
    if (rst)
1181
        q <= {1'b1,{length-1{1'b0}}};
1182
    else
1183
        q <= {q[length-1],q[0:length-2]};
1184
endmodule
1185 18 unneback
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
1186 6 unneback
   parameter length = 4;
1187
   input cke;
1188
   output reg [0:length-1] q;
1189
   input rst;
1190
   input clk;
1191
    always @ (posedge clk or posedge rst)
1192
    if (rst)
1193
        q <= {1'b1,{length-1{1'b0}}};
1194
    else
1195
        if (cke)
1196
            q <= {q[length-1],q[0:length-2]};
1197
endmodule
1198 105 unneback
module vl_cnt_shreg_clear ( clear, q, rst, clk);
1199
   parameter length = 4;
1200
   input clear;
1201
   output reg [0:length-1] q;
1202
   input rst;
1203
   input clk;
1204
    always @ (posedge clk or posedge rst)
1205
    if (rst)
1206
        q <= {1'b1,{length-1{1'b0}}};
1207
    else
1208
        if (clear)
1209
            q <= {1'b1,{length-1{1'b0}}};
1210
        else
1211
            q <= q >> 1;
1212
endmodule
1213 18 unneback
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
1214 6 unneback
   parameter length = 4;
1215
   input cke, clear;
1216
   output reg [0:length-1] q;
1217
   input rst;
1218
   input clk;
1219
    always @ (posedge clk or posedge rst)
1220
    if (rst)
1221
        q <= {1'b1,{length-1{1'b0}}};
1222
    else
1223
        if (cke)
1224
            if (clear)
1225
                q <= {1'b1,{length-1{1'b0}}};
1226
            else
1227
                q <= q >> 1;
1228
endmodule
1229 18 unneback
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
1230 6 unneback
   parameter length = 4;
1231
   input cke, clear;
1232
   output reg [0:length-1] q;
1233
   input rst;
1234
   input clk;
1235
    always @ (posedge clk or posedge rst)
1236
    if (rst)
1237
        q <= {1'b1,{length-1{1'b0}}};
1238
    else
1239
        if (cke)
1240
            if (clear)
1241
                q <= {1'b1,{length-1{1'b0}}};
1242
            else
1243
            q <= {q[length-1],q[0:length-2]};
1244
endmodule
1245
//////////////////////////////////////////////////////////////////////
1246
////                                                              ////
1247
////  Versatile library, memories                                 ////
1248
////                                                              ////
1249
////  Description                                                 ////
1250
////  memories                                                    ////
1251
////                                                              ////
1252
////                                                              ////
1253
////  To Do:                                                      ////
1254
////   - add more memory types                                    ////
1255
////                                                              ////
1256
////  Author(s):                                                  ////
1257
////      - Michael Unneback, unneback@opencores.org              ////
1258
////        ORSoC AB                                              ////
1259
////                                                              ////
1260
//////////////////////////////////////////////////////////////////////
1261
////                                                              ////
1262
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1263
////                                                              ////
1264
//// This source file may be used and distributed without         ////
1265
//// restriction provided that this copyright statement is not    ////
1266
//// removed from the file and that any derivative work contains  ////
1267
//// the original copyright notice and the associated disclaimer. ////
1268
////                                                              ////
1269
//// This source file is free software; you can redistribute it   ////
1270
//// and/or modify it under the terms of the GNU Lesser General   ////
1271
//// Public License as published by the Free Software Foundation; ////
1272
//// either version 2.1 of the License, or (at your option) any   ////
1273
//// later version.                                               ////
1274
////                                                              ////
1275
//// This source is distributed in the hope that it will be       ////
1276
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1277
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1278
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1279
//// details.                                                     ////
1280
////                                                              ////
1281
//// You should have received a copy of the GNU Lesser General    ////
1282
//// Public License along with this source; if not, download it   ////
1283
//// from http://www.opencores.org/lgpl.shtml                     ////
1284
////                                                              ////
1285
//////////////////////////////////////////////////////////////////////
1286
/// ROM
1287 7 unneback
module vl_rom_init ( adr, q, clk);
1288
   parameter data_width = 32;
1289
   parameter addr_width = 8;
1290 75 unneback
   parameter mem_size = 1<<addr_width;
1291 7 unneback
   input [(addr_width-1):0]       adr;
1292
   output reg [(data_width-1):0] q;
1293
   input                         clk;
1294 75 unneback
   reg [data_width-1:0] rom [mem_size-1:0];
1295 7 unneback
   parameter memory_file = "vl_rom.vmem";
1296
   initial
1297
     begin
1298
        $readmemh(memory_file, rom);
1299
     end
1300
   always @ (posedge clk)
1301
     q <= rom[adr];
1302
endmodule
1303 6 unneback
// Single port RAM
1304
module vl_ram ( d, adr, we, q, clk);
1305
   parameter data_width = 32;
1306
   parameter addr_width = 8;
1307 75 unneback
   parameter mem_size = 1<<addr_width;
1308 100 unneback
   parameter debug = 0;
1309 6 unneback
   input [(data_width-1):0]      d;
1310
   input [(addr_width-1):0]       adr;
1311
   input                         we;
1312 7 unneback
   output reg [(data_width-1):0] q;
1313 6 unneback
   input                         clk;
1314 98 unneback
   reg [data_width-1:0] ram [mem_size-1:0];
1315 100 unneback
    parameter memory_init = 0;
1316
    parameter memory_file = "vl_ram.vmem";
1317
    generate
1318
    if (memory_init == 1) begin : init_mem
1319
        initial
1320
            $readmemh(memory_file, ram);
1321
   end else if (memory_init == 2) begin : init_zero
1322
        integer k;
1323
        initial
1324
            for (k = 0; k < mem_size; k = k + 1)
1325
                ram[k] = 0;
1326 7 unneback
   end
1327
   endgenerate
1328 100 unneback
    generate
1329
    if (debug==1) begin : debug_we
1330
        always @ (posedge clk)
1331
        if (we)
1332
            $display ("Value %h written at address %h : time %t", d, adr, $time);
1333
    end
1334
    endgenerate
1335 6 unneback
   always @ (posedge clk)
1336
   begin
1337
   if (we)
1338
     ram[adr] <= d;
1339
   q <= ram[adr];
1340
   end
1341
endmodule
1342 91 unneback
module vl_ram_be ( d, adr, be, we, q, clk);
1343 7 unneback
   parameter data_width = 32;
1344 72 unneback
   parameter addr_width = 6;
1345 75 unneback
   parameter mem_size = 1<<addr_width;
1346 7 unneback
   input [(data_width-1):0]      d;
1347
   input [(addr_width-1):0]       adr;
1348 73 unneback
   input [(data_width/8)-1:0]    be;
1349 7 unneback
   input                         we;
1350
   output reg [(data_width-1):0] q;
1351
   input                         clk;
1352 65 unneback
`ifdef SYSTEMVERILOG
1353 95 unneback
    // use a multi-dimensional packed array
1354
    //t o model individual bytes within the word
1355
    logic [data_width/8-1:0][7:0] ram [0:mem_size-1];// # words = 1 << address width
1356 65 unneback
`else
1357 85 unneback
    reg [data_width-1:0] ram [mem_size-1:0];
1358
    wire [data_width/8-1:0] cke;
1359 65 unneback
`endif
1360 100 unneback
    parameter memory_init = 0;
1361
    parameter memory_file = "vl_ram.vmem";
1362
    generate
1363
    if (memory_init == 1) begin : init_mem
1364
        initial
1365
            $readmemh(memory_file, ram);
1366
    end else if (memory_init == 2) begin : init_zero
1367
        integer k;
1368
        initial
1369
            for (k = 0; k < mem_size; k = k + 1)
1370
                ram[k] = 0;
1371
    end
1372 7 unneback
   endgenerate
1373 60 unneback
`ifdef SYSTEMVERILOG
1374
always_ff@(posedge clk)
1375
begin
1376 95 unneback
    if(we) begin
1377 86 unneback
        if(be[3]) ram[adr][3] <= d[31:24];
1378
        if(be[2]) ram[adr][2] <= d[23:16];
1379
        if(be[1]) ram[adr][1] <= d[15:8];
1380
        if(be[0]) ram[adr][0] <= d[7:0];
1381 60 unneback
    end
1382 90 unneback
        q <= ram[adr];
1383 60 unneback
end
1384
`else
1385 85 unneback
assign cke = {data_width/8{we}} & be;
1386 7 unneback
   genvar i;
1387 85 unneback
   generate for (i=0;i<data_width/8;i=i+1) begin : be_ram
1388 7 unneback
      always @ (posedge clk)
1389 85 unneback
      if (cke[i])
1390 7 unneback
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
1391
   end
1392
   endgenerate
1393
   always @ (posedge clk)
1394
      q <= ram[adr];
1395 60 unneback
`endif
1396 93 unneback
`ifdef verilator
1397 85 unneback
   // Function to access RAM (for use by Verilator).
1398
   function [31:0] get_mem;
1399
      // verilator public
1400 90 unneback
      input [addr_width-1:0]             addr;
1401 85 unneback
      get_mem = ram[addr];
1402
   endfunction // get_mem
1403
   // Function to write RAM (for use by Verilator).
1404
   function set_mem;
1405
      // verilator public
1406 90 unneback
      input [addr_width-1:0]             addr;
1407
      input [data_width-1:0]             data;
1408 85 unneback
      ram[addr] = data;
1409
   endfunction // set_mem
1410 93 unneback
`endif
1411 7 unneback
endmodule
1412
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1413 6 unneback
   parameter data_width = 32;
1414
   parameter addr_width = 8;
1415 75 unneback
   parameter mem_size = 1<<addr_width;
1416 6 unneback
   input [(data_width-1):0]      d_a;
1417
   input [(addr_width-1):0]       adr_a;
1418
   input [(addr_width-1):0]       adr_b;
1419
   input                         we_a;
1420 118 unneback
   output reg [(data_width-1):0]          q_b;
1421 6 unneback
   input                         clk_a, clk_b;
1422 119 unneback
   reg [data_width-1:0] ram [0:mem_size-1] /*synthesis syn_ramstyle = "no_rw_check"*/;
1423 100 unneback
    parameter memory_init = 0;
1424
    parameter memory_file = "vl_ram.vmem";
1425
    parameter debug = 0;
1426
    generate
1427
    if (memory_init == 1) begin : init_mem
1428
        initial
1429
            $readmemh(memory_file, ram);
1430
    end else if (memory_init == 2) begin : init_zero
1431
        integer k;
1432
        initial
1433
            for (k = 0; k < mem_size; k = k + 1)
1434
                ram[k] = 0;
1435
    end
1436 7 unneback
   endgenerate
1437 100 unneback
    generate
1438
    if (debug==1) begin : debug_we
1439
        always @ (posedge clk_a)
1440
        if (we_a)
1441
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
1442
    end
1443
    endgenerate
1444 6 unneback
   always @ (posedge clk_a)
1445
   if (we_a)
1446
     ram[adr_a] <= d_a;
1447
   always @ (posedge clk_b)
1448 118 unneback
      q_b = ram[adr_b];
1449 6 unneback
endmodule
1450 7 unneback
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1451 6 unneback
   parameter data_width = 32;
1452
   parameter addr_width = 8;
1453 75 unneback
   parameter mem_size = 1<<addr_width;
1454 6 unneback
   input [(data_width-1):0]      d_a;
1455
   input [(addr_width-1):0]       adr_a;
1456
   input [(addr_width-1):0]       adr_b;
1457
   input                         we_a;
1458
   output [(data_width-1):0]      q_b;
1459
   output reg [(data_width-1):0] q_a;
1460
   input                         clk_a, clk_b;
1461
   reg [(data_width-1):0]         q_b;
1462 119 unneback
   reg [data_width-1:0] ram [0:mem_size-1] /*synthesis syn_ramstyle = "no_rw_check"*/;
1463 100 unneback
    parameter memory_init = 0;
1464
    parameter memory_file = "vl_ram.vmem";
1465
    parameter debug = 0;
1466
    generate
1467
    if (memory_init == 1) begin : init_mem
1468
        initial
1469
            $readmemh(memory_file, ram);
1470
    end else if (memory_init == 2) begin : init_zero
1471
        integer k;
1472
        initial
1473
            for (k = 0; k < mem_size; k = k + 1)
1474
                ram[k] = 0;
1475
    end
1476 7 unneback
   endgenerate
1477 100 unneback
    generate
1478
    if (debug==1) begin : debug_we
1479
        always @ (posedge clk_a)
1480
        if (we_a)
1481
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
1482
    end
1483
    endgenerate
1484 6 unneback
   always @ (posedge clk_a)
1485
     begin
1486
        q_a <= ram[adr_a];
1487
        if (we_a)
1488
             ram[adr_a] <= d_a;
1489
     end
1490
   always @ (posedge clk_b)
1491
          q_b <= ram[adr_b];
1492
endmodule
1493 100 unneback
module vl_dpram_1r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, adr_b, we_b, clk_b );
1494
   parameter data_width = 32;
1495
   parameter addr_width = 8;
1496
   parameter mem_size = 1<<addr_width;
1497
   input [(data_width-1):0]      d_a;
1498
   input [(addr_width-1):0]       adr_a;
1499
   input [(addr_width-1):0]       adr_b;
1500
   input                         we_a;
1501
   input [(data_width-1):0]       d_b;
1502
   output reg [(data_width-1):0] q_a;
1503
   input                         we_b;
1504
   input                         clk_a, clk_b;
1505
   reg [(data_width-1):0]         q_b;
1506 119 unneback
   reg [data_width-1:0] ram [0:mem_size-1] /*synthesis syn_ramstyle = "no_rw_check"*/;
1507 100 unneback
    parameter memory_init = 0;
1508
    parameter memory_file = "vl_ram.vmem";
1509
    parameter debug = 0;
1510
    generate
1511
    if (memory_init == 1) begin : init_mem
1512
        initial
1513
            $readmemh(memory_file, ram);
1514
    end else if (memory_init == 2) begin : init_zero
1515
        integer k;
1516
        initial
1517
            for (k = 0; k < mem_size; k = k + 1)
1518
                ram[k] = 0;
1519
    end
1520
   endgenerate
1521
    generate
1522
    if (debug==1) begin : debug_we
1523
        always @ (posedge clk_a)
1524
        if (we_a)
1525
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
1526
        always @ (posedge clk_b)
1527
        if (we_b)
1528
            $display ("Debug: Value %h written at address %h : time %t", d_b, adr_b, $time);
1529
    end
1530
    endgenerate
1531
   always @ (posedge clk_a)
1532
     begin
1533
        q_a <= ram[adr_a];
1534
        if (we_a)
1535
             ram[adr_a] <= d_a;
1536
     end
1537
   always @ (posedge clk_b)
1538
     begin
1539
        if (we_b)
1540
          ram[adr_b] <= d_b;
1541
     end
1542
endmodule
1543 7 unneback
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
1544 6 unneback
   parameter data_width = 32;
1545
   parameter addr_width = 8;
1546 75 unneback
   parameter mem_size = 1<<addr_width;
1547 6 unneback
   input [(data_width-1):0]      d_a;
1548
   input [(addr_width-1):0]       adr_a;
1549
   input [(addr_width-1):0]       adr_b;
1550
   input                         we_a;
1551
   output [(data_width-1):0]      q_b;
1552
   input [(data_width-1):0]       d_b;
1553
   output reg [(data_width-1):0] q_a;
1554
   input                         we_b;
1555
   input                         clk_a, clk_b;
1556
   reg [(data_width-1):0]         q_b;
1557 119 unneback
   reg [data_width-1:0] ram [0:mem_size-1] /*synthesis syn_ramstyle = "no_rw_check"*/;
1558 100 unneback
    parameter memory_init = 0;
1559
    parameter memory_file = "vl_ram.vmem";
1560
    parameter debug = 0;
1561
    generate
1562
    if (memory_init) begin : init_mem
1563
        initial
1564
            $readmemh(memory_file, ram);
1565
    end else if (memory_init == 2) begin : init_zero
1566
        integer k;
1567
        initial
1568
            for (k = 0; k < mem_size; k = k + 1)
1569
                ram[k] = 0;
1570
    end
1571 7 unneback
   endgenerate
1572 100 unneback
    generate
1573
    if (debug==1) begin : debug_we
1574
        always @ (posedge clk_a)
1575
        if (we_a)
1576
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
1577
        always @ (posedge clk_b)
1578
        if (we_b)
1579
            $display ("Debug: Value %h written at address %h : time %t", d_b, adr_b, $time);
1580
    end
1581
    endgenerate
1582 6 unneback
   always @ (posedge clk_a)
1583
     begin
1584
        q_a <= ram[adr_a];
1585
        if (we_a)
1586
             ram[adr_a] <= d_a;
1587
     end
1588
   always @ (posedge clk_b)
1589
     begin
1590
        q_b <= ram[adr_b];
1591
        if (we_b)
1592
          ram[adr_b] <= d_b;
1593
     end
1594
endmodule
1595 92 unneback
module vl_dpram_be_2r2w ( d_a, q_a, adr_a, be_a, we_a, clk_a, d_b, q_b, adr_b, be_b, we_b, clk_b );
1596 75 unneback
   parameter a_data_width = 32;
1597
   parameter a_addr_width = 8;
1598 95 unneback
   parameter b_data_width = 64; //a_data_width;
1599 124 unneback
   //localparam b_addr_width = a_data_width * a_addr_width / b_data_width;
1600
   localparam b_addr_width =
1601 125 unneback
        (a_data_width==b_data_width) ? a_addr_width :
1602
        (a_data_width==b_data_width*2) ? a_addr_width+1 :
1603
        (a_data_width==b_data_width*4) ? a_addr_width+2 :
1604
        (a_data_width==b_data_width*8) ? a_addr_width+3 :
1605
        (a_data_width==b_data_width*16) ? a_addr_width+4 :
1606
        (a_data_width==b_data_width*32) ? a_addr_width+5 :
1607
        (a_data_width==b_data_width/2) ? a_addr_width-1 :
1608
        (a_data_width==b_data_width/4) ? a_addr_width-2 :
1609
        (a_data_width==b_data_width/8) ? a_addr_width-3 :
1610
        (a_data_width==b_data_width/16) ? a_addr_width-4 :
1611
        (a_data_width==b_data_width/32) ? a_addr_width-5 : 0;
1612 95 unneback
   localparam ratio = (a_addr_width>b_addr_width) ? (a_addr_width/b_addr_width) : (b_addr_width/a_addr_width);
1613
   parameter mem_size = (a_addr_width>b_addr_width) ? (1<<b_addr_width) : (1<<a_addr_width);
1614 100 unneback
   parameter memory_init = 0;
1615 95 unneback
   parameter memory_file = "vl_ram.vmem";
1616 100 unneback
   parameter debug = 0;
1617 75 unneback
   input [(a_data_width-1):0]      d_a;
1618 91 unneback
   input [(a_addr_width-1):0]       adr_a;
1619
   input [(a_data_width/8-1):0]    be_a;
1620
   input                           we_a;
1621 75 unneback
   output reg [(a_data_width-1):0] q_a;
1622 91 unneback
   input [(b_data_width-1):0]       d_b;
1623
   input [(b_addr_width-1):0]       adr_b;
1624 92 unneback
   input [(b_data_width/8-1):0]    be_b;
1625
   input                           we_b;
1626
   output reg [(b_data_width-1):0]          q_b;
1627 91 unneback
   input                           clk_a, clk_b;
1628 100 unneback
    generate
1629
    if (debug==1) begin : debug_we
1630
        always @ (posedge clk_a)
1631
        if (we_a)
1632
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
1633
        always @ (posedge clk_b)
1634
        if (we_b)
1635
            $display ("Debug: Value %h written at address %h : time %t", d_b, adr_b, $time);
1636
    end
1637
    endgenerate
1638 91 unneback
`ifdef SYSTEMVERILOG
1639
// use a multi-dimensional packed array
1640
//to model individual bytes within the word
1641 75 unneback
generate
1642 91 unneback
if (a_data_width==32 & b_data_width==32) begin : dpram_3232
1643 98 unneback
    logic [0:3][7:0] ram [0:mem_size-1] /*synthesis syn_ramstyle = "no_rw_check"*/;
1644 95 unneback
    initial
1645 100 unneback
        if (memory_init==1)
1646 95 unneback
            $readmemh(memory_file, ram);
1647 100 unneback
    integer k;
1648
    initial
1649
        if (memory_init==2)
1650
            for (k = 0; k < mem_size; k = k + 1)
1651
                ram[k] = 0;
1652 91 unneback
    always_ff@(posedge clk_a)
1653
    begin
1654
        if(we_a) begin
1655 100 unneback
            if(be_a[3]) ram[adr_a][0] <= d_a[31:24];
1656
            if(be_a[2]) ram[adr_a][1] <= d_a[23:16];
1657
            if(be_a[1]) ram[adr_a][2] <= d_a[15:8];
1658
            if(be_a[0]) ram[adr_a][3] <= d_a[7:0];
1659 91 unneback
        end
1660
    end
1661 92 unneback
    always@(posedge clk_a)
1662
        q_a = ram[adr_a];
1663 91 unneback
    always_ff@(posedge clk_b)
1664 92 unneback
    begin
1665
        if(we_b) begin
1666 100 unneback
            if(be_b[3]) ram[adr_b][0] <= d_b[31:24];
1667
            if(be_b[2]) ram[adr_b][1] <= d_b[23:16];
1668
            if(be_b[1]) ram[adr_b][2] <= d_b[15:8];
1669
            if(be_b[0]) ram[adr_b][3] <= d_b[7:0];
1670 92 unneback
        end
1671
    end
1672
    always@(posedge clk_b)
1673
        q_b = ram[adr_b];
1674 75 unneback
end
1675
endgenerate
1676 95 unneback
generate
1677
if (a_data_width==64 & b_data_width==64) begin : dpram_6464
1678 98 unneback
    logic [0:7][7:0] ram [0:mem_size-1] /*synthesis syn_ramstyle = "no_rw_check"*/;
1679 95 unneback
    initial
1680 100 unneback
        if (memory_init==1)
1681 95 unneback
            $readmemh(memory_file, ram);
1682 100 unneback
    integer k;
1683
    initial
1684
        if (memory_init==2)
1685
            for (k = 0; k < mem_size; k = k + 1)
1686
                ram[k] = 0;
1687 95 unneback
    always_ff@(posedge clk_a)
1688
    begin
1689
        if(we_a) begin
1690
            if(be_a[7]) ram[adr_a][7] <= d_a[63:56];
1691
            if(be_a[6]) ram[adr_a][6] <= d_a[55:48];
1692
            if(be_a[5]) ram[adr_a][5] <= d_a[47:40];
1693
            if(be_a[4]) ram[adr_a][4] <= d_a[39:32];
1694
            if(be_a[3]) ram[adr_a][3] <= d_a[31:24];
1695
            if(be_a[2]) ram[adr_a][2] <= d_a[23:16];
1696
            if(be_a[1]) ram[adr_a][1] <= d_a[15:8];
1697
            if(be_a[0]) ram[adr_a][0] <= d_a[7:0];
1698
        end
1699
    end
1700
    always@(posedge clk_a)
1701
        q_a = ram[adr_a];
1702
    always_ff@(posedge clk_b)
1703
    begin
1704
        if(we_b) begin
1705
            if(be_b[7]) ram[adr_b][7] <= d_b[63:56];
1706
            if(be_b[6]) ram[adr_b][6] <= d_b[55:48];
1707
            if(be_b[5]) ram[adr_b][5] <= d_b[47:40];
1708
            if(be_b[4]) ram[adr_b][4] <= d_b[39:32];
1709
            if(be_b[3]) ram[adr_b][3] <= d_b[31:24];
1710
            if(be_b[2]) ram[adr_b][2] <= d_b[23:16];
1711
            if(be_b[1]) ram[adr_b][1] <= d_b[15:8];
1712
            if(be_b[0]) ram[adr_b][0] <= d_b[7:0];
1713
        end
1714
    end
1715
    always@(posedge clk_b)
1716
        q_b = ram[adr_b];
1717
end
1718
endgenerate
1719
generate
1720
if (a_data_width==32 & b_data_width==16) begin : dpram_3216
1721
logic [31:0] temp;
1722 128 unneback
vl_dpram_be_2r2w # (.a_data_width(32), .b_data_width(32), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file))
1723
dpram3232 (
1724 95 unneback
    .d_a(d_a),
1725
    .q_a(q_a),
1726
    .adr_a(adr_a),
1727
    .be_a(be_a),
1728
    .we_a(we_a),
1729
    .clk_a(clk_a),
1730
    .d_b({d_b,d_b}),
1731
    .q_b(temp),
1732 128 unneback
    .adr_b(adr_b[b_addr_width-1:1]),
1733 95 unneback
    .be_b({be_b,be_b} & {{2{adr_b[0]}},{2{!adr_b[0]}}}),
1734
    .we_b(we_b),
1735
    .clk_b(clk_b)
1736
);
1737 100 unneback
always @ (adr_b[0] or temp)
1738 95 unneback
    if (adr_b[0])
1739
        q_b = temp[31:16];
1740
    else
1741
        q_b = temp[15:0];
1742
end
1743
endgenerate
1744
generate
1745
if (a_data_width==32 & b_data_width==64) begin : dpram_3264
1746
logic [63:0] temp;
1747 128 unneback
vl_dpram_be_2r2w # (.a_data_width(32), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file))
1748 95 unneback
dpram6464 (
1749
    .d_a({d_a,d_a}),
1750
    .q_a(temp),
1751
    .adr_a(adr_a[a_addr_width-1:1]),
1752
    .be_a({be_a,be_a} & {{4{adr_a[0]}},{4{!adr_a[0]}}}),
1753
    .we_a(we_a),
1754
    .clk_a(clk_a),
1755
    .d_b(d_b),
1756
    .q_b(q_b),
1757
    .adr_b(adr_b),
1758
    .be_b(be_b),
1759
    .we_b(we_b),
1760
    .clk_b(clk_b)
1761
);
1762 100 unneback
always @ (adr_a[0] or temp)
1763 95 unneback
    if (adr_a[0])
1764
        q_a = temp[63:32];
1765
    else
1766
        q_a = temp[31:0];
1767
end
1768
endgenerate
1769 91 unneback
`else
1770 92 unneback
    // This modules requires SystemVerilog
1771 98 unneback
    // at this point anyway
1772 91 unneback
`endif
1773 75 unneback
endmodule
1774 6 unneback
// FIFO
1775 25 unneback
module vl_fifo_1r1w_fill_level_sync (
1776
    d, wr, fifo_full,
1777
    q, rd, fifo_empty,
1778
    fill_level,
1779
    clk, rst
1780
    );
1781
parameter data_width = 18;
1782
parameter addr_width = 4;
1783
// write side
1784
input  [data_width-1:0] d;
1785
input                   wr;
1786
output                  fifo_full;
1787
// read side
1788
output [data_width-1:0] q;
1789
input                   rd;
1790
output                  fifo_empty;
1791
// common
1792
output [addr_width:0]   fill_level;
1793
input rst, clk;
1794
wire [addr_width:1] wadr, radr;
1795
vl_cnt_bin_ce
1796
    # ( .length(addr_width))
1797
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
1798
vl_cnt_bin_ce
1799
    # (.length(addr_width))
1800
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
1801
vl_dpram_1r1w
1802
    # (.data_width(data_width), .addr_width(addr_width))
1803
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
1804 31 unneback
vl_cnt_bin_ce_rew_q_zq_l1
1805 27 unneback
    # (.length(addr_width+1), .level1_value(1<<addr_width))
1806 25 unneback
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
1807
endmodule
1808 27 unneback
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
1809
// RAM is supposed to be larger than the two FIFOs
1810
// LFSR counters used adr pointers
1811
module vl_fifo_2r2w_sync_simplex (
1812
    // a side
1813
    a_d, a_wr, a_fifo_full,
1814
    a_q, a_rd, a_fifo_empty,
1815
    a_fill_level,
1816
    // b side
1817
    b_d, b_wr, b_fifo_full,
1818
    b_q, b_rd, b_fifo_empty,
1819
    b_fill_level,
1820
    // common
1821
    clk, rst
1822
    );
1823
parameter data_width = 8;
1824
parameter addr_width = 5;
1825
parameter fifo_full_level = (1<<addr_width)-1;
1826
// a side
1827
input  [data_width-1:0] a_d;
1828
input                   a_wr;
1829
output                  a_fifo_full;
1830
output [data_width-1:0] a_q;
1831
input                   a_rd;
1832
output                  a_fifo_empty;
1833
output [addr_width-1:0] a_fill_level;
1834
// b side
1835
input  [data_width-1:0] b_d;
1836
input                   b_wr;
1837
output                  b_fifo_full;
1838
output [data_width-1:0] b_q;
1839
input                   b_rd;
1840
output                  b_fifo_empty;
1841
output [addr_width-1:0] b_fill_level;
1842
input                   clk;
1843
input                   rst;
1844
// adr_gen
1845
wire [addr_width:1] a_wadr, a_radr;
1846
wire [addr_width:1] b_wadr, b_radr;
1847
// dpram
1848
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
1849
vl_cnt_lfsr_ce
1850
    # ( .length(addr_width))
1851
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
1852
vl_cnt_lfsr_ce
1853
    # (.length(addr_width))
1854
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
1855
vl_cnt_lfsr_ce
1856
    # ( .length(addr_width))
1857
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
1858
vl_cnt_lfsr_ce
1859
    # (.length(addr_width))
1860
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
1861
// mux read or write adr to DPRAM
1862
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
1863
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
1864
vl_dpram_2r2w
1865
    # (.data_width(data_width), .addr_width(addr_width+1))
1866
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
1867
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
1868
vl_cnt_bin_ce_rew_zq_l1
1869 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
1870 27 unneback
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
1871
vl_cnt_bin_ce_rew_zq_l1
1872 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
1873 27 unneback
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
1874
endmodule
1875 6 unneback
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
1876 11 unneback
   parameter addr_width = 4;
1877
   parameter N = addr_width-1;
1878 6 unneback
   parameter Q1 = 2'b00;
1879
   parameter Q2 = 2'b01;
1880
   parameter Q3 = 2'b11;
1881
   parameter Q4 = 2'b10;
1882
   parameter going_empty = 1'b0;
1883
   parameter going_full  = 1'b1;
1884
   input [N:0]  wptr, rptr;
1885 14 unneback
   output       fifo_empty;
1886 6 unneback
   output       fifo_full;
1887
   input        wclk, rclk, rst;
1888
   wire direction;
1889
   reg  direction_set, direction_clr;
1890
   wire async_empty, async_full;
1891
   wire fifo_full2;
1892 14 unneback
   wire fifo_empty2;
1893 6 unneback
   // direction_set
1894
   always @ (wptr[N:N-1] or rptr[N:N-1])
1895
     case ({wptr[N:N-1],rptr[N:N-1]})
1896
       {Q1,Q2} : direction_set <= 1'b1;
1897
       {Q2,Q3} : direction_set <= 1'b1;
1898
       {Q3,Q4} : direction_set <= 1'b1;
1899
       {Q4,Q1} : direction_set <= 1'b1;
1900
       default : direction_set <= 1'b0;
1901
     endcase
1902
   // direction_clear
1903
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
1904
     if (rst)
1905
       direction_clr <= 1'b1;
1906
     else
1907
       case ({wptr[N:N-1],rptr[N:N-1]})
1908
         {Q2,Q1} : direction_clr <= 1'b1;
1909
         {Q3,Q2} : direction_clr <= 1'b1;
1910
         {Q4,Q3} : direction_clr <= 1'b1;
1911
         {Q1,Q4} : direction_clr <= 1'b1;
1912
         default : direction_clr <= 1'b0;
1913
       endcase
1914 18 unneback
    vl_dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
1915 6 unneback
   assign async_empty = (wptr == rptr) && (direction==going_empty);
1916
   assign async_full  = (wptr == rptr) && (direction==going_full);
1917 18 unneback
    vl_dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
1918
    vl_dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
1919 6 unneback
/*
1920
   always @ (posedge wclk or posedge rst or posedge async_full)
1921
     if (rst)
1922
       {fifo_full, fifo_full2} <= 2'b00;
1923
     else if (async_full)
1924
       {fifo_full, fifo_full2} <= 2'b11;
1925
     else
1926
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
1927
*/
1928 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
1929 6 unneback
     if (async_empty)
1930
       {fifo_empty, fifo_empty2} <= 2'b11;
1931
     else
1932 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
1933 18 unneback
    vl_dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
1934
    vl_dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
1935 27 unneback
endmodule // async_compb
1936 6 unneback
module vl_fifo_1r1w_async (
1937
    d, wr, fifo_full, wr_clk, wr_rst,
1938
    q, rd, fifo_empty, rd_clk, rd_rst
1939
    );
1940
parameter data_width = 18;
1941
parameter addr_width = 4;
1942
// write side
1943
input  [data_width-1:0] d;
1944
input                   wr;
1945
output                  fifo_full;
1946
input                   wr_clk;
1947
input                   wr_rst;
1948
// read side
1949
output [data_width-1:0] q;
1950
input                   rd;
1951
output                  fifo_empty;
1952
input                   rd_clk;
1953
input                   rd_rst;
1954
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
1955 18 unneback
vl_cnt_gray_ce_bin
1956 6 unneback
    # ( .length(addr_width))
1957
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
1958 18 unneback
vl_cnt_gray_ce_bin
1959 6 unneback
    # (.length(addr_width))
1960 23 unneback
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
1961 7 unneback
vl_dpram_1r1w
1962 6 unneback
    # (.data_width(data_width), .addr_width(addr_width))
1963
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
1964
vl_fifo_cmp_async
1965
    # (.addr_width(addr_width))
1966
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
1967
endmodule
1968 8 unneback
module vl_fifo_2r2w_async (
1969 6 unneback
    // a side
1970
    a_d, a_wr, a_fifo_full,
1971
    a_q, a_rd, a_fifo_empty,
1972
    a_clk, a_rst,
1973
    // b side
1974
    b_d, b_wr, b_fifo_full,
1975
    b_q, b_rd, b_fifo_empty,
1976
    b_clk, b_rst
1977
    );
1978
parameter data_width = 18;
1979
parameter addr_width = 4;
1980
// a side
1981
input  [data_width-1:0] a_d;
1982
input                   a_wr;
1983
output                  a_fifo_full;
1984
output [data_width-1:0] a_q;
1985
input                   a_rd;
1986
output                  a_fifo_empty;
1987
input                   a_clk;
1988
input                   a_rst;
1989
// b side
1990
input  [data_width-1:0] b_d;
1991
input                   b_wr;
1992
output                  b_fifo_full;
1993
output [data_width-1:0] b_q;
1994
input                   b_rd;
1995
output                  b_fifo_empty;
1996
input                   b_clk;
1997
input                   b_rst;
1998
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
1999
vl_fifo_1r1w_async_a (
2000
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
2001
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
2002
    );
2003
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
2004
vl_fifo_1r1w_async_b (
2005
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
2006
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
2007
    );
2008
endmodule
2009 8 unneback
module vl_fifo_2r2w_async_simplex (
2010 6 unneback
    // a side
2011
    a_d, a_wr, a_fifo_full,
2012
    a_q, a_rd, a_fifo_empty,
2013
    a_clk, a_rst,
2014
    // b side
2015
    b_d, b_wr, b_fifo_full,
2016
    b_q, b_rd, b_fifo_empty,
2017
    b_clk, b_rst
2018
    );
2019
parameter data_width = 18;
2020
parameter addr_width = 4;
2021
// a side
2022
input  [data_width-1:0] a_d;
2023
input                   a_wr;
2024
output                  a_fifo_full;
2025
output [data_width-1:0] a_q;
2026
input                   a_rd;
2027
output                  a_fifo_empty;
2028
input                   a_clk;
2029
input                   a_rst;
2030
// b side
2031
input  [data_width-1:0] b_d;
2032
input                   b_wr;
2033
output                  b_fifo_full;
2034
output [data_width-1:0] b_q;
2035
input                   b_rd;
2036
output                  b_fifo_empty;
2037
input                   b_clk;
2038
input                   b_rst;
2039
// adr_gen
2040
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
2041
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
2042
// dpram
2043
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
2044 18 unneback
vl_cnt_gray_ce_bin
2045 6 unneback
    # ( .length(addr_width))
2046
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
2047 18 unneback
vl_cnt_gray_ce_bin
2048 6 unneback
    # (.length(addr_width))
2049
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
2050 18 unneback
vl_cnt_gray_ce_bin
2051 6 unneback
    # ( .length(addr_width))
2052
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
2053 18 unneback
vl_cnt_gray_ce_bin
2054 6 unneback
    # (.length(addr_width))
2055
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
2056
// mux read or write adr to DPRAM
2057
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
2058
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
2059 11 unneback
vl_dpram_2r2w
2060 6 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
2061
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
2062
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
2063 11 unneback
vl_fifo_cmp_async
2064 6 unneback
    # (.addr_width(addr_width))
2065
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
2066 11 unneback
vl_fifo_cmp_async
2067 6 unneback
    # (.addr_width(addr_width))
2068
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
2069
endmodule
2070 48 unneback
module vl_reg_file (
2071
    a1, a2, a3, wd3, we3, rd1, rd2, clk
2072
);
2073
parameter data_width = 32;
2074
parameter addr_width = 5;
2075
input [addr_width-1:0] a1, a2, a3;
2076
input [data_width-1:0] wd3;
2077
input we3;
2078
output [data_width-1:0] rd1, rd2;
2079
input clk;
2080
reg [data_width-1:0] wd3_reg;
2081
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
2082
reg we3_reg;
2083
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
2084
reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
2085
always @ (posedge clk or posedge rst)
2086
if (rst)
2087
    {wd3_reg, a3_reg, we3_reg} <= {(data_width+addr_width+1){1'b0}};
2088
else
2089
    {wd3_reg, a3_reg, we3_reg} <= {wd3,a3,wd3};
2090
    always @ (negedge clk)
2091
    if (we3_reg)
2092
        ram1[a3_reg] <= wd3;
2093
    always @ (posedge clk)
2094
        a1_reg <= a1;
2095
    assign rd1 = ram1[a1_reg];
2096
    always @ (negedge clk)
2097
    if (we3_reg)
2098
        ram2[a3_reg] <= wd3;
2099
    always @ (posedge clk)
2100
        a2_reg <= a2;
2101
    assign rd2 = ram2[a2_reg];
2102
endmodule
2103 12 unneback
//////////////////////////////////////////////////////////////////////
2104
////                                                              ////
2105
////  Versatile library, wishbone stuff                           ////
2106
////                                                              ////
2107
////  Description                                                 ////
2108
////  Wishbone compliant modules                                  ////
2109
////                                                              ////
2110
////                                                              ////
2111
////  To Do:                                                      ////
2112
////   -                                                          ////
2113
////                                                              ////
2114
////  Author(s):                                                  ////
2115
////      - Michael Unneback, unneback@opencores.org              ////
2116
////        ORSoC AB                                              ////
2117
////                                                              ////
2118
//////////////////////////////////////////////////////////////////////
2119
////                                                              ////
2120
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2121
////                                                              ////
2122
//// This source file may be used and distributed without         ////
2123
//// restriction provided that this copyright statement is not    ////
2124
//// removed from the file and that any derivative work contains  ////
2125
//// the original copyright notice and the associated disclaimer. ////
2126
////                                                              ////
2127
//// This source file is free software; you can redistribute it   ////
2128
//// and/or modify it under the terms of the GNU Lesser General   ////
2129
//// Public License as published by the Free Software Foundation; ////
2130
//// either version 2.1 of the License, or (at your option) any   ////
2131
//// later version.                                               ////
2132
////                                                              ////
2133
//// This source is distributed in the hope that it will be       ////
2134
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2135
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2136
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2137
//// details.                                                     ////
2138
////                                                              ////
2139
//// You should have received a copy of the GNU Lesser General    ////
2140
//// Public License along with this source; if not, download it   ////
2141
//// from http://www.opencores.org/lgpl.shtml                     ////
2142
////                                                              ////
2143
//////////////////////////////////////////////////////////////////////
2144
`timescale 1ns/1ns
2145 85 unneback
module vl_wb_adr_inc ( cyc_i, stb_i, cti_i, bte_i, adr_i, we_i, ack_o, adr_o, clk, rst);
2146 83 unneback
parameter adr_width = 10;
2147
parameter max_burst_width = 4;
2148 85 unneback
input cyc_i, stb_i, we_i;
2149 83 unneback
input [2:0] cti_i;
2150
input [1:0] bte_i;
2151
input [adr_width-1:0] adr_i;
2152
output [adr_width-1:0] adr_o;
2153
output ack_o;
2154
input clk, rst;
2155
reg [adr_width-1:0] adr;
2156 90 unneback
wire [max_burst_width-1:0] to_adr;
2157 91 unneback
reg [max_burst_width-1:0] last_adr;
2158 92 unneback
reg last_cycle;
2159
localparam idle_or_eoc = 1'b0;
2160
localparam cyc_or_ws   = 1'b1;
2161 91 unneback
always @ (posedge clk or posedge rst)
2162
if (rst)
2163
    last_adr <= {max_burst_width{1'b0}};
2164
else
2165
    if (stb_i)
2166 92 unneback
        last_adr <=adr_o[max_burst_width-1:0];
2167 83 unneback
generate
2168
if (max_burst_width==0) begin : inst_0
2169 97 unneback
        reg ack_o;
2170
        assign adr_o = adr_i;
2171
        always @ (posedge clk or posedge rst)
2172
        if (rst)
2173
            ack_o <= 1'b0;
2174
        else
2175
            ack_o <= cyc_i & stb_i & !ack_o;
2176 83 unneback
end else begin
2177
    always @ (posedge clk or posedge rst)
2178
    if (rst)
2179 92 unneback
        last_cycle <= idle_or_eoc;
2180 83 unneback
    else
2181 92 unneback
        last_cycle <= (!cyc_i) ? idle_or_eoc : //idle
2182
                      (cyc_i & ack_o & (cti_i==3'b000 | cti_i==3'b111)) ? idle_or_eoc : // eoc
2183
                      (cyc_i & !stb_i) ? cyc_or_ws : //ws
2184
                      cyc_or_ws; // cyc
2185
    assign to_adr = (last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
2186 85 unneback
    assign adr_o[max_burst_width-1:0] = (we_i) ? adr_i[max_burst_width-1:0] :
2187 91 unneback
                                        (!stb_i) ? last_adr :
2188 92 unneback
                                        (last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] :
2189 85 unneback
                                        adr[max_burst_width-1:0];
2190 92 unneback
    assign ack_o = (last_cycle==cyc_or_ws) & stb_i;
2191 83 unneback
end
2192
endgenerate
2193
generate
2194
if (max_burst_width==2) begin : inst_2
2195
    always @ (posedge clk or posedge rst)
2196
    if (rst)
2197
        adr <= 2'h0;
2198
    else
2199
        if (cyc_i & stb_i)
2200
            adr[1:0] <= to_adr[1:0] + 2'd1;
2201
        else
2202
            adr <= to_adr[1:0];
2203
end
2204
endgenerate
2205
generate
2206
if (max_burst_width==3) begin : inst_3
2207
    always @ (posedge clk or posedge rst)
2208
    if (rst)
2209
        adr <= 3'h0;
2210
    else
2211
        if (cyc_i & stb_i)
2212
            case (bte_i)
2213
            2'b01: adr[2:0] <= {to_adr[2],to_adr[1:0] + 2'd1};
2214
            default: adr[3:0] <= to_adr[2:0] + 3'd1;
2215
            endcase
2216
        else
2217
            adr <= to_adr[2:0];
2218
end
2219
endgenerate
2220
generate
2221
if (max_burst_width==4) begin : inst_4
2222
    always @ (posedge clk or posedge rst)
2223
    if (rst)
2224
        adr <= 4'h0;
2225
    else
2226 91 unneback
        if (stb_i) // | (!stb_i & last_cycle!=ws)) // for !stb_i restart with adr_i +1, only inc once
2227 83 unneback
            case (bte_i)
2228
            2'b01: adr[3:0] <= {to_adr[3:2],to_adr[1:0] + 2'd1};
2229
            2'b10: adr[3:0] <= {to_adr[3],to_adr[2:0] + 3'd1};
2230
            default: adr[3:0] <= to_adr + 4'd1;
2231
            endcase
2232
        else
2233
            adr <= to_adr[3:0];
2234
end
2235
endgenerate
2236
generate
2237
if (adr_width > max_burst_width) begin : pass_through
2238
    assign adr_o[adr_width-1:max_burst_width] = adr_i[adr_width-1:max_burst_width];
2239
end
2240
endgenerate
2241
endmodule
2242
// async wb3 - wb3 bridge
2243
`timescale 1ns/1ns
2244 18 unneback
module vl_wb3wb3_bridge (
2245 12 unneback
        // wishbone slave side
2246
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
2247
        // wishbone master side
2248
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
2249 95 unneback
parameter style = "FIFO"; // valid: simple, FIFO
2250
parameter addr_width = 4;
2251 12 unneback
input [31:0] wbs_dat_i;
2252
input [31:2] wbs_adr_i;
2253
input [3:0]  wbs_sel_i;
2254
input [1:0]  wbs_bte_i;
2255
input [2:0]  wbs_cti_i;
2256
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
2257
output [31:0] wbs_dat_o;
2258 14 unneback
output wbs_ack_o;
2259 12 unneback
input wbs_clk, wbs_rst;
2260
output [31:0] wbm_dat_o;
2261
output reg [31:2] wbm_adr_o;
2262
output [3:0]  wbm_sel_o;
2263
output reg [1:0]  wbm_bte_o;
2264
output reg [2:0]  wbm_cti_o;
2265 14 unneback
output reg wbm_we_o;
2266
output wbm_cyc_o;
2267 12 unneback
output wbm_stb_o;
2268
input [31:0]  wbm_dat_i;
2269
input wbm_ack_i;
2270
input wbm_clk, wbm_rst;
2271
// bte
2272
parameter linear       = 2'b00;
2273
parameter wrap4        = 2'b01;
2274
parameter wrap8        = 2'b10;
2275
parameter wrap16       = 2'b11;
2276
// cti
2277
parameter classic      = 3'b000;
2278
parameter incburst     = 3'b010;
2279
parameter endofburst   = 3'b111;
2280 95 unneback
localparam wbs_adr  = 1'b0;
2281
localparam wbs_data = 1'b1;
2282
localparam wbm_adr0      = 2'b00;
2283
localparam wbm_adr1      = 2'b01;
2284
localparam wbm_data      = 2'b10;
2285
localparam wbm_data_wait = 2'b11;
2286 12 unneback
reg [1:0] wbs_bte_reg;
2287
reg wbs;
2288
wire wbs_eoc_alert, wbm_eoc_alert;
2289
reg wbs_eoc, wbm_eoc;
2290
reg [1:0] wbm;
2291 14 unneback
wire [1:16] wbs_count, wbm_count;
2292 12 unneback
wire [35:0] a_d, a_q, b_d, b_q;
2293
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
2294
reg a_rd_reg;
2295
wire b_rd_adr, b_rd_data;
2296 14 unneback
wire b_rd_data_reg;
2297
wire [35:0] temp;
2298 12 unneback
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
2299
always @ (posedge wbs_clk or posedge wbs_rst)
2300
if (wbs_rst)
2301
        wbs_eoc <= 1'b0;
2302
else
2303
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
2304 78 unneback
                wbs_eoc <= (wbs_bte_i==linear) | (wbs_cti_i==3'b111);
2305 12 unneback
        else if (wbs_eoc_alert & (a_rd | a_wr))
2306
                wbs_eoc <= 1'b1;
2307 18 unneback
vl_cnt_shreg_ce_clear # ( .length(16))
2308 12 unneback
    cnt0 (
2309
        .cke(wbs_ack_o),
2310
        .clear(wbs_eoc),
2311
        .q(wbs_count),
2312
        .rst(wbs_rst),
2313
        .clk(wbs_clk));
2314
always @ (posedge wbs_clk or posedge wbs_rst)
2315
if (wbs_rst)
2316
        wbs <= wbs_adr;
2317
else
2318 75 unneback
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & a_fifo_empty)
2319 12 unneback
                wbs <= wbs_data;
2320
        else if (wbs_eoc & wbs_ack_o)
2321
                wbs <= wbs_adr;
2322
// wbs FIFO
2323 75 unneback
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,((wbs_cti_i==3'b111) ? {2'b00,3'b000} : {wbs_bte_i,wbs_cti_i})} : {wbs_dat_i,wbs_sel_i};
2324
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & a_fifo_empty :
2325 12 unneback
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
2326
              1'b0;
2327
assign a_rd = !a_fifo_empty;
2328
always @ (posedge wbs_clk or posedge wbs_rst)
2329
if (wbs_rst)
2330
        a_rd_reg <= 1'b0;
2331
else
2332
        a_rd_reg <= a_rd;
2333
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
2334
assign wbs_dat_o = a_q[35:4];
2335
always @ (posedge wbs_clk or posedge wbs_rst)
2336
if (wbs_rst)
2337 13 unneback
        wbs_bte_reg <= 2'b00;
2338 12 unneback
else
2339 13 unneback
        wbs_bte_reg <= wbs_bte_i;
2340 12 unneback
// wbm FIFO
2341
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
2342
always @ (posedge wbm_clk or posedge wbm_rst)
2343
if (wbm_rst)
2344
        wbm_eoc <= 1'b0;
2345
else
2346
        if (wbm==wbm_adr0 & !b_fifo_empty)
2347
                wbm_eoc <= b_q[4:3] == linear;
2348
        else if (wbm_eoc_alert & wbm_ack_i)
2349
                wbm_eoc <= 1'b1;
2350
always @ (posedge wbm_clk or posedge wbm_rst)
2351
if (wbm_rst)
2352
        wbm <= wbm_adr0;
2353
else
2354 33 unneback
/*
2355 12 unneback
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
2356
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
2357
        (wbm==wbm_adr1 & !wbm_we_o) |
2358
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
2359
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
2360 33 unneback
*/
2361
    case (wbm)
2362
    wbm_adr0:
2363
        if (!b_fifo_empty)
2364
            wbm <= wbm_adr1;
2365
    wbm_adr1:
2366
        if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
2367
            wbm <= wbm_data;
2368
    wbm_data:
2369
        if (wbm_ack_i & wbm_eoc)
2370
            wbm <= wbm_adr0;
2371
        else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
2372
            wbm <= wbm_data_wait;
2373
    wbm_data_wait:
2374
        if (!b_fifo_empty)
2375
            wbm <= wbm_data;
2376
    endcase
2377 12 unneback
assign b_d = {wbm_dat_i,4'b1111};
2378
assign b_wr = !wbm_we_o & wbm_ack_i;
2379
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
2380
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
2381
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
2382 33 unneback
                   (wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
2383 12 unneback
                   1'b0;
2384
assign b_rd = b_rd_adr | b_rd_data;
2385 18 unneback
vl_dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
2386
vl_dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
2387 12 unneback
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
2388 18 unneback
vl_cnt_shreg_ce_clear # ( .length(16))
2389 12 unneback
    cnt1 (
2390
        .cke(wbm_ack_i),
2391
        .clear(wbm_eoc),
2392
        .q(wbm_count),
2393
        .rst(wbm_rst),
2394
        .clk(wbm_clk));
2395 33 unneback
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
2396
assign wbm_stb_o = (wbm==wbm_data);
2397 12 unneback
always @ (posedge wbm_clk or posedge wbm_rst)
2398
if (wbm_rst)
2399
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
2400
else begin
2401
        if (wbm==wbm_adr0 & !b_fifo_empty)
2402
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
2403
        else if (wbm_eoc_alert & wbm_ack_i)
2404
                wbm_cti_o <= endofburst;
2405
end
2406
//async_fifo_dw_simplex_top
2407
vl_fifo_2r2w_async_simplex
2408
# ( .data_width(36), .addr_width(addr_width))
2409
fifo (
2410
    // a side
2411
    .a_d(a_d),
2412
    .a_wr(a_wr),
2413
    .a_fifo_full(a_fifo_full),
2414
    .a_q(a_q),
2415
    .a_rd(a_rd),
2416
    .a_fifo_empty(a_fifo_empty),
2417
    .a_clk(wbs_clk),
2418
    .a_rst(wbs_rst),
2419
    // b side
2420
    .b_d(b_d),
2421
    .b_wr(b_wr),
2422
    .b_fifo_full(b_fifo_full),
2423
    .b_q(b_q),
2424
    .b_rd(b_rd),
2425
    .b_fifo_empty(b_fifo_empty),
2426
    .b_clk(wbm_clk),
2427
    .b_rst(wbm_rst)
2428
    );
2429
endmodule
2430 75 unneback
module vl_wb3avalon_bridge (
2431
        // wishbone slave side
2432
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
2433 77 unneback
        // avalon master side
2434 75 unneback
        readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst);
2435 85 unneback
parameter linewrapburst = 1'b0;
2436 75 unneback
input [31:0] wbs_dat_i;
2437
input [31:2] wbs_adr_i;
2438
input [3:0]  wbs_sel_i;
2439
input [1:0]  wbs_bte_i;
2440
input [2:0]  wbs_cti_i;
2441 83 unneback
input wbs_we_i;
2442
input wbs_cyc_i;
2443
input wbs_stb_i;
2444 75 unneback
output [31:0] wbs_dat_o;
2445
output wbs_ack_o;
2446
input wbs_clk, wbs_rst;
2447
input [31:0] readdata;
2448
output [31:0] writedata;
2449
output [31:2] address;
2450
output [3:0]  be;
2451
output write;
2452 81 unneback
output read;
2453 75 unneback
output beginbursttransfer;
2454
output [3:0] burstcount;
2455
input readdatavalid;
2456
input waitrequest;
2457
input clk;
2458
input rst;
2459
wire [1:0] wbm_bte_o;
2460
wire [2:0] wbm_cti_o;
2461
wire wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_ack_i;
2462
reg last_cyc;
2463 79 unneback
reg [3:0] counter;
2464 82 unneback
reg read_busy;
2465 75 unneback
always @ (posedge clk or posedge rst)
2466
if (rst)
2467
    last_cyc <= 1'b0;
2468
else
2469
    last_cyc <= wbm_cyc_o;
2470 79 unneback
always @ (posedge clk or posedge rst)
2471
if (rst)
2472 82 unneback
    read_busy <= 1'b0;
2473 79 unneback
else
2474 82 unneback
    if (read & !waitrequest)
2475
        read_busy <= 1'b1;
2476
    else if (wbm_ack_i & wbm_cti_o!=3'b010)
2477
        read_busy <= 1'b0;
2478
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o & !read_busy;
2479 75 unneback
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010;
2480
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 :
2481
                    (wbm_bte_o==2'b10) ? 4'd8 :
2482 78 unneback
                    (wbm_bte_o==2'b11) ? 4'd16:
2483
                    4'd1;
2484 82 unneback
assign wbm_ack_i = (readdatavalid) | (write & !waitrequest);
2485 79 unneback
always @ (posedge clk or posedge rst)
2486
if (rst) begin
2487
    counter <= 4'd0;
2488
end else
2489 80 unneback
    if (wbm_we_o) begin
2490
        if (!waitrequest & !last_cyc & wbm_cyc_o) begin
2491 85 unneback
            counter <= burstcount -4'd1;
2492 80 unneback
        end else if (waitrequest & !last_cyc & wbm_cyc_o) begin
2493
            counter <= burstcount;
2494
        end else if (!waitrequest & wbm_stb_o) begin
2495
            counter <= counter - 4'd1;
2496
        end
2497 82 unneback
    end
2498 81 unneback
assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o & counter!=4'd0;
2499 77 unneback
vl_wb3wb3_bridge wbwb3inst (
2500 75 unneback
    // wishbone slave side
2501
    .wbs_dat_i(wbs_dat_i),
2502
    .wbs_adr_i(wbs_adr_i),
2503
    .wbs_sel_i(wbs_sel_i),
2504
    .wbs_bte_i(wbs_bte_i),
2505
    .wbs_cti_i(wbs_cti_i),
2506
    .wbs_we_i(wbs_we_i),
2507
    .wbs_cyc_i(wbs_cyc_i),
2508
    .wbs_stb_i(wbs_stb_i),
2509
    .wbs_dat_o(wbs_dat_o),
2510
    .wbs_ack_o(wbs_ack_o),
2511
    .wbs_clk(wbs_clk),
2512
    .wbs_rst(wbs_rst),
2513
    // wishbone master side
2514
    .wbm_dat_o(writedata),
2515 78 unneback
    .wbm_adr_o(address),
2516 75 unneback
    .wbm_sel_o(be),
2517
    .wbm_bte_o(wbm_bte_o),
2518
    .wbm_cti_o(wbm_cti_o),
2519
    .wbm_we_o(wbm_we_o),
2520
    .wbm_cyc_o(wbm_cyc_o),
2521
    .wbm_stb_o(wbm_stb_o),
2522
    .wbm_dat_i(readdata),
2523
    .wbm_ack_i(wbm_ack_i),
2524
    .wbm_clk(clk),
2525
    .wbm_rst(rst));
2526
endmodule
2527 49 unneback
// WB RAM with byte enable
2528 101 unneback
module vl_wb_ram (
2529 69 unneback
    wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
2530 101 unneback
    wbs_dat_o, wbs_ack_o, wbs_stall_o, wb_clk, wb_rst);
2531
parameter adr_width = 16;
2532
parameter mem_size = 1<<adr_width;
2533
parameter dat_width = 32;
2534
parameter max_burst_width = 4; // only used for B3
2535
parameter mode = "B3"; // valid options: B3, B4
2536 60 unneback
parameter memory_init = 1;
2537
parameter memory_file = "vl_ram.vmem";
2538 101 unneback
input [dat_width-1:0] wbs_dat_i;
2539
input [adr_width-1:0] wbs_adr_i;
2540
input [2:0] wbs_cti_i;
2541
input [1:0] wbs_bte_i;
2542
input [dat_width/8-1:0] wbs_sel_i;
2543 70 unneback
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
2544 101 unneback
output [dat_width-1:0] wbs_dat_o;
2545 70 unneback
output wbs_ack_o;
2546 101 unneback
output wbs_stall_o;
2547 71 unneback
input wb_clk, wb_rst;
2548 101 unneback
wire [adr_width-1:0] adr;
2549
wire we;
2550
generate
2551
if (mode=="B3") begin : B3_inst
2552
vl_wb_adr_inc # ( .adr_width(adr_width), .max_burst_width(max_burst_width)) adr_inc0 (
2553 83 unneback
    .cyc_i(wbs_cyc_i),
2554
    .stb_i(wbs_stb_i),
2555
    .cti_i(wbs_cti_i),
2556
    .bte_i(wbs_bte_i),
2557
    .adr_i(wbs_adr_i),
2558 85 unneback
    .we_i(wbs_we_i),
2559 83 unneback
    .ack_o(wbs_ack_o),
2560
    .adr_o(adr),
2561
    .clk(wb_clk),
2562
    .rst(wb_rst));
2563 101 unneback
assign we = wbs_we_i & wbs_ack_o;
2564
end else if (mode=="B4") begin : B4_inst
2565
reg wbs_ack_o_reg;
2566
always @ (posedge wb_clk or posedge wb_rst)
2567
    if (wb_rst)
2568
        wbs_ack_o_reg <= 1'b0;
2569
    else
2570
        wbs_ack_o_reg <= wbs_stb_i & wbs_cyc_i;
2571
assign wbs_ack_o = wbs_ack_o_reg;
2572
assign wbs_stall_o = 1'b0;
2573
assign adr = wbs_adr_i;
2574
assign we = wbs_we_i & wbs_cyc_i & wbs_stb_i;
2575
end
2576
endgenerate
2577 100 unneback
vl_ram_be # (
2578
    .data_width(dat_width),
2579
    .addr_width(adr_width),
2580
    .mem_size(mem_size),
2581
    .memory_init(memory_init),
2582
    .memory_file(memory_file))
2583
ram0(
2584 101 unneback
    .d(wbs_dat_i),
2585
    .adr(adr),
2586
    .be(wbs_sel_i),
2587
    .we(we),
2588
    .q(wbs_dat_o),
2589 100 unneback
    .clk(wb_clk)
2590
);
2591 49 unneback
endmodule
2592 103 unneback
// A wishbone compliant RAM module that can be placed in front of other memory controllers
2593
module vl_wb_shadow_ram (
2594
    wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
2595
    wbs_dat_o, wbs_ack_o, wbs_stall_o,
2596
    wbm_dat_o, wbm_adr_o, wbm_cti_o, wbm_bte_o, wbm_sel_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
2597
    wbm_dat_i, wbm_ack_i, wbm_stall_i,
2598
    wb_clk, wb_rst);
2599
parameter dat_width = 32;
2600
parameter mode = "B4";
2601
parameter max_burst_width = 4; // only used for B3
2602
parameter shadow_mem_adr_width = 10;
2603
parameter shadow_mem_size = 1024;
2604
parameter shadow_mem_init = 2;
2605
parameter shadow_mem_file = "vl_ram.v";
2606
parameter main_mem_adr_width = 24;
2607
input [dat_width-1:0] wbs_dat_i;
2608
input [main_mem_adr_width-1:0] wbs_adr_i;
2609
input [2:0] wbs_cti_i;
2610
input [1:0] wbs_bte_i;
2611
input [dat_width/8-1:0] wbs_sel_i;
2612
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
2613
output [dat_width-1:0] wbs_dat_o;
2614
output wbs_ack_o;
2615
output wbs_stall_o;
2616
output [dat_width-1:0] wbm_dat_o;
2617
output [main_mem_adr_width-1:0] wbm_adr_o;
2618
output [2:0] wbm_cti_o;
2619
output [1:0] wbm_bte_o;
2620
output [dat_width/8-1:0] wbm_sel_o;
2621
output wbm_we_o, wbm_stb_o, wbm_cyc_o;
2622
input [dat_width-1:0] wbm_dat_i;
2623
input wbm_ack_i, wbm_stall_i;
2624
input wb_clk, wb_rst;
2625
generate
2626
if (shadow_mem_size>0) begin : shadow_ram_inst
2627
wire cyc;
2628
wire [dat_width-1:0] dat;
2629
wire stall, ack;
2630
assign cyc = wbs_cyc_i & (wbs_adr_i<=shadow_mem_size);
2631
vl_wb_ram # (
2632
    .dat_width(dat_width),
2633
    .adr_width(shadow_mem_adr_width),
2634
    .mem_size(shadow_mem_size),
2635
    .memory_init(shadow_mem_init),
2636 117 unneback
    .memory_file(shadow_mem_file),
2637 103 unneback
    .mode(mode))
2638
shadow_mem0 (
2639
    .wbs_dat_i(wbs_dat_i),
2640
    .wbs_adr_i(wbs_adr_i[shadow_mem_adr_width-1:0]),
2641
    .wbs_sel_i(wbs_sel_i),
2642
    .wbs_we_i (wbs_we_i),
2643
    .wbs_bte_i(wbs_bte_i),
2644
    .wbs_cti_i(wbs_cti_i),
2645
    .wbs_stb_i(wbs_stb_i),
2646
    .wbs_cyc_i(cyc),
2647
    .wbs_dat_o(dat),
2648
    .wbs_stall_o(stall),
2649
    .wbs_ack_o(ack),
2650
    .wb_clk(wb_clk),
2651
    .wb_rst(wb_rst));
2652
assign {wbm_dat_o, wbm_adr_o, wbm_cti_o, wbm_bte_o, wbm_sel_o, wbm_we_o, wbm_stb_o} =
2653
       {wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i};
2654
assign wbm_cyc_o = wbs_cyc_i & (wbs_adr_i>shadow_mem_size);
2655
assign wbs_dat_o = (dat & {dat_width{cyc}}) | (wbm_dat_i & {dat_width{wbm_cyc_o}});
2656
assign wbs_ack_o = (ack & cyc) | (wbm_ack_i & wbm_cyc_o);
2657
assign wbs_stall_o = (stall & cyc) | (wbm_stall_i & wbm_cyc_o);
2658
end else begin : no_shadow_ram_inst
2659
assign {wbm_dat_o, wbm_adr_o, wbm_cti_o, wbm_bte_o, wbm_sel_o, wbm_we_o, wbm_stb_o, wbm_cyc_o} =
2660
       {wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i};
2661
assign {wbs_dat_o, wbs_ack_o, wbs_stall_o} = {wbm_dat_i, wbm_ack_i, wbm_stall_i};
2662
end
2663
endgenerate
2664
endmodule
2665 17 unneback
// WB ROM
2666 48 unneback
module vl_wb_b4_rom (
2667
    wb_adr_i, wb_stb_i, wb_cyc_i,
2668
    wb_dat_o, stall_o, wb_ack_o, wb_clk, wb_rst);
2669
    parameter dat_width = 32;
2670
    parameter dat_default = 32'h15000000;
2671
    parameter adr_width = 32;
2672
/*
2673
`ifndef ROM
2674
`define ROM "rom.v"
2675
`endif
2676
*/
2677
    input [adr_width-1:2]   wb_adr_i;
2678
    input                   wb_stb_i;
2679
    input                   wb_cyc_i;
2680
    output [dat_width-1:0]  wb_dat_o;
2681
    reg [dat_width-1:0]     wb_dat_o;
2682
    output                  wb_ack_o;
2683
    reg                     wb_ack_o;
2684
    output                  stall_o;
2685
    input                   wb_clk;
2686
    input                   wb_rst;
2687
always @ (posedge wb_clk or posedge wb_rst)
2688
    if (wb_rst)
2689
        wb_dat_o <= {dat_width{1'b0}};
2690
    else
2691
         case (wb_adr_i[adr_width-1:2])
2692
`ifdef ROM
2693
`include `ROM
2694
`endif
2695
           default:
2696
             wb_dat_o <= dat_default;
2697
         endcase // case (wb_adr_i)
2698
always @ (posedge wb_clk or posedge wb_rst)
2699
    if (wb_rst)
2700
        wb_ack_o <= 1'b0;
2701
    else
2702
        wb_ack_o <= wb_stb_i & wb_cyc_i;
2703
assign stall_o = 1'b0;
2704
endmodule
2705
// WB ROM
2706 18 unneback
module vl_wb_boot_rom (
2707 17 unneback
    wb_adr_i, wb_stb_i, wb_cyc_i,
2708 18 unneback
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
2709
    parameter adr_hi = 31;
2710
    parameter adr_lo = 28;
2711
    parameter adr_sel = 4'hf;
2712
    parameter addr_width = 5;
2713 33 unneback
/*
2714 17 unneback
`ifndef BOOT_ROM
2715
`define BOOT_ROM "boot_rom.v"
2716
`endif
2717 33 unneback
*/
2718 18 unneback
    input [adr_hi:2]    wb_adr_i;
2719
    input               wb_stb_i;
2720
    input               wb_cyc_i;
2721
    output [31:0]        wb_dat_o;
2722
    output              wb_ack_o;
2723
    output              hit_o;
2724
    input               wb_clk;
2725
    input               wb_rst;
2726
    wire hit;
2727
    reg [31:0] wb_dat;
2728
    reg wb_ack;
2729
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
2730 17 unneback
always @ (posedge wb_clk or posedge wb_rst)
2731
    if (wb_rst)
2732 18 unneback
        wb_dat <= 32'h15000000;
2733 17 unneback
    else
2734 18 unneback
         case (wb_adr_i[addr_width-1:2])
2735 33 unneback
`ifdef BOOT_ROM
2736 17 unneback
`include `BOOT_ROM
2737 33 unneback
`endif
2738 17 unneback
           /*
2739
            // Zero r0 and jump to 0x00000100
2740 18 unneback
 
2741
            1 : wb_dat <= 32'hA8200000;
2742
            2 : wb_dat <= 32'hA8C00100;
2743
            3 : wb_dat <= 32'h44003000;
2744
            4 : wb_dat <= 32'h15000000;
2745 17 unneback
            */
2746
           default:
2747 18 unneback
             wb_dat <= 32'h00000000;
2748 17 unneback
         endcase // case (wb_adr_i)
2749
always @ (posedge wb_clk or posedge wb_rst)
2750
    if (wb_rst)
2751 18 unneback
        wb_ack <= 1'b0;
2752 17 unneback
    else
2753 18 unneback
        wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
2754
assign hit_o = hit;
2755
assign wb_dat_o = wb_dat & {32{wb_ack}};
2756
assign wb_ack_o = wb_ack;
2757 17 unneback
endmodule
2758 106 unneback
module vl_wb_dpram (
2759
        // wishbone slave side a
2760
        wbsa_dat_i, wbsa_adr_i, wbsa_sel_i, wbsa_cti_i, wbsa_bte_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o, wbsa_stall_o,
2761
        wbsa_clk, wbsa_rst,
2762
        // wishbone slave side b
2763
        wbsb_dat_i, wbsb_adr_i, wbsb_sel_i, wbsb_cti_i, wbsb_bte_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o, wbsb_stall_o,
2764
        wbsb_clk, wbsb_rst);
2765
parameter data_width_a = 32;
2766
parameter data_width_b = data_width_a;
2767
parameter addr_width_a = 8;
2768
localparam addr_width_b = data_width_a * addr_width_a / data_width_b;
2769
parameter mem_size = (addr_width_a>addr_width_b) ? (1<<addr_width_a) : (1<<addr_width_b);
2770
parameter max_burst_width_a = 4;
2771
parameter max_burst_width_b = max_burst_width_a;
2772
parameter mode = "B3";
2773 109 unneback
parameter memory_init = 0;
2774
parameter memory_file = "vl_ram.v";
2775 106 unneback
input [data_width_a-1:0] wbsa_dat_i;
2776
input [addr_width_a-1:0] wbsa_adr_i;
2777
input [data_width_a/8-1:0] wbsa_sel_i;
2778
input [2:0] wbsa_cti_i;
2779
input [1:0] wbsa_bte_i;
2780
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
2781
output [data_width_a-1:0] wbsa_dat_o;
2782 109 unneback
output wbsa_ack_o;
2783 106 unneback
output wbsa_stall_o;
2784
input wbsa_clk, wbsa_rst;
2785
input [data_width_b-1:0] wbsb_dat_i;
2786
input [addr_width_b-1:0] wbsb_adr_i;
2787
input [data_width_b/8-1:0] wbsb_sel_i;
2788
input [2:0] wbsb_cti_i;
2789
input [1:0] wbsb_bte_i;
2790
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
2791
output [data_width_b-1:0] wbsb_dat_o;
2792 109 unneback
output wbsb_ack_o;
2793 106 unneback
output wbsb_stall_o;
2794
input wbsb_clk, wbsb_rst;
2795
wire [addr_width_a-1:0] adr_a;
2796
wire [addr_width_b-1:0] adr_b;
2797
wire we_a, we_b;
2798
generate
2799
if (mode=="B3") begin : b3_inst
2800
vl_wb_adr_inc # ( .adr_width(addr_width_a), .max_burst_width(max_burst_width_a)) adr_inc0 (
2801
    .cyc_i(wbsa_cyc_i),
2802
    .stb_i(wbsa_stb_i),
2803
    .cti_i(wbsa_cti_i),
2804
    .bte_i(wbsa_bte_i),
2805
    .adr_i(wbsa_adr_i),
2806
    .we_i(wbsa_we_i),
2807
    .ack_o(wbsa_ack_o),
2808
    .adr_o(adr_a),
2809
    .clk(wbsa_clk),
2810
    .rst(wbsa_rst));
2811
assign we_a = wbsa_we_i & wbsa_ack_o;
2812
vl_wb_adr_inc # ( .adr_width(addr_width_b), .max_burst_width(max_burst_width_b)) adr_inc1 (
2813
    .cyc_i(wbsb_cyc_i),
2814
    .stb_i(wbsb_stb_i),
2815
    .cti_i(wbsb_cti_i),
2816
    .bte_i(wbsb_bte_i),
2817
    .adr_i(wbsb_adr_i),
2818
    .we_i(wbsb_we_i),
2819
    .ack_o(wbsb_ack_o),
2820
    .adr_o(adr_b),
2821
    .clk(wbsb_clk),
2822
    .rst(wbsb_rst));
2823
assign we_b = wbsb_we_i & wbsb_ack_o;
2824
end else if (mode=="B4") begin : b4_inst
2825 109 unneback
vl_dff dffacka ( .d(wbsa_stb_i & wbsa_cyc_i), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
2826 106 unneback
assign wbsa_stall_o = 1'b0;
2827
assign we_a = wbsa_we_i & wbsa_cyc_i & wbsa_stb_i;
2828 109 unneback
vl_dff dffackb ( .d(wbsb_stb_i & wbsb_cyc_i), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
2829 106 unneback
assign wbsb_stall_o = 1'b0;
2830
assign we_b = wbsb_we_i & wbsb_cyc_i & wbsb_stb_i;
2831
end
2832
endgenerate
2833 109 unneback
vl_dpram_be_2r2w # ( .a_data_width(data_width_a), .a_addr_width(addr_width_a), .mem_size(mem_size),
2834 110 unneback
                 .b_data_width(data_width_b),
2835 109 unneback
                 .memory_init(memory_init), .memory_file(memory_file))
2836 106 unneback
ram_i (
2837
    .d_a(wbsa_dat_i),
2838
    .q_a(wbsa_dat_o),
2839
    .adr_a(adr_a),
2840
    .be_a(wbsa_sel_i),
2841
    .we_a(we_a),
2842
    .clk_a(wbsa_clk),
2843
    .d_b(wbsb_dat_i),
2844
    .q_b(wbsb_dat_o),
2845
    .adr_b(adr_b),
2846
    .be_b(wbsb_sel_i),
2847
    .we_b(we_b),
2848
    .clk_b(wbsb_clk) );
2849
endmodule
2850 101 unneback
module vl_wb_cache (
2851 103 unneback
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i, wbs_dat_o, wbs_ack_o, wbs_stall_o, wbs_clk, wbs_rst,
2852 98 unneback
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o, wbm_dat_i, wbm_ack_i, wbm_stall_i, wbm_clk, wbm_rst
2853 97 unneback
);
2854
parameter dw_s = 32;
2855
parameter aw_s = 24;
2856
parameter dw_m = dw_s;
2857 124 unneback
//localparam aw_m = dw_s * aw_s / dw_m;
2858
localparam aw_m =
2859 126 unneback
        (dw_s==dw_m) ? aw_s :
2860
        (dw_s==dw_m*2) ? aw_s+1 :
2861
        (dw_s==dw_m*4) ? aw_s+2 :
2862
        (dw_s==dw_m*8) ? aw_s+3 :
2863
        (dw_s==dw_m*16) ? aw_s+4 :
2864
        (dw_s==dw_m*32) ? aw_s+5 :
2865
        (dw_s==dw_m/2) ? aw_s-1 :
2866 127 unneback
        (dw_s==dw_m/4) ? aw_s-2 :
2867 126 unneback
        (dw_s==dw_m/8) ? aw_s-3 :
2868
        (dw_s==dw_m/16) ? aw_s-4 :
2869
        (dw_s==dw_m/32) ? aw_s-5 : 0;
2870 100 unneback
parameter wbs_max_burst_width = 4;
2871 103 unneback
parameter wbs_mode = "B3";
2872 97 unneback
parameter async = 1; // wbs_clk != wbm_clk
2873
parameter nr_of_ways = 1;
2874
parameter aw_offset = 4; // 4 => 16 words per cache line
2875
parameter aw_slot = 10;
2876 100 unneback
parameter valid_mem = 0;
2877
parameter debug = 0;
2878
localparam aw_b_offset = aw_offset * dw_s / dw_m;
2879 98 unneback
localparam aw_tag = aw_s - aw_slot - aw_offset;
2880 97 unneback
parameter wbm_burst_size = 4; // valid options 4,8,16
2881 98 unneback
localparam bte = (wbm_burst_size==4) ? 2'b01 : (wbm_burst_size==8) ? 2'b10 : 2'b11;
2882 100 unneback
localparam wbm_burst_width = (wbm_burst_size==1) ? 0 : (wbm_burst_size==2) ? 1 : (wbm_burst_size==4) ? 2 : (wbm_burst_size==8) ? 3 : (wbm_burst_size==16) ? 4 : (wbm_burst_size==32) ? 5 : (wbm_burst_size==64) ? 6 : (wbm_burst_size==128) ? 7 : 8;
2883 97 unneback
localparam nr_of_wbm_burst = ((1<<aw_offset)/wbm_burst_size) * dw_s / dw_m;
2884 100 unneback
localparam nr_of_wbm_burst_width = (nr_of_wbm_burst==1) ? 0 : (nr_of_wbm_burst==2) ? 1 : (nr_of_wbm_burst==4) ? 2 : (nr_of_wbm_burst==8) ? 3 : (nr_of_wbm_burst==16) ? 4 : (nr_of_wbm_burst==32) ? 5 : (nr_of_wbm_burst==64) ? 6 : (nr_of_wbm_burst==128) ? 7 : 8;
2885 97 unneback
input [dw_s-1:0] wbs_dat_i;
2886
input [aw_s-1:0] wbs_adr_i; // dont include a1,a0
2887 98 unneback
input [dw_s/8-1:0] wbs_sel_i;
2888 97 unneback
input [2:0] wbs_cti_i;
2889
input [1:0] wbs_bte_i;
2890 98 unneback
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
2891 97 unneback
output [dw_s-1:0] wbs_dat_o;
2892
output wbs_ack_o;
2893 103 unneback
output wbs_stall_o;
2894 97 unneback
input wbs_clk, wbs_rst;
2895
output [dw_m-1:0] wbm_dat_o;
2896
output [aw_m-1:0] wbm_adr_o;
2897
output [dw_m/8-1:0] wbm_sel_o;
2898
output [2:0] wbm_cti_o;
2899
output [1:0] wbm_bte_o;
2900 98 unneback
output wbm_stb_o, wbm_cyc_o, wbm_we_o;
2901 97 unneback
input [dw_m-1:0] wbm_dat_i;
2902
input wbm_ack_i;
2903
input wbm_stall_i;
2904
input wbm_clk, wbm_rst;
2905 100 unneback
wire valid, dirty, hit;
2906 97 unneback
wire [aw_tag-1:0] tag;
2907
wire tag_mem_we;
2908
wire [aw_tag-1:0] wbs_adr_tag;
2909
wire [aw_slot-1:0] wbs_adr_slot;
2910 98 unneback
wire [aw_offset-1:0] wbs_adr_word;
2911
wire [aw_s-1:0] wbs_adr;
2912 97 unneback
reg [1:0] state;
2913
localparam idle = 2'h0;
2914
localparam rdwr = 2'h1;
2915
localparam push = 2'h2;
2916
localparam pull = 2'h3;
2917
wire eoc;
2918 103 unneback
wire we;
2919 97 unneback
// cdc
2920
wire done, mem_alert, mem_done;
2921 98 unneback
// wbm side
2922
reg [aw_m-1:0] wbm_radr;
2923
reg [aw_m-1:0] wbm_wadr;
2924 100 unneback
wire [aw_slot-1:0] wbm_adr;
2925 98 unneback
wire wbm_radr_cke, wbm_wadr_cke;
2926 100 unneback
reg [2:0] phase;
2927
// phase = {we,stb,cyc}
2928
localparam wbm_wait     = 3'b000;
2929
localparam wbm_wr       = 3'b111;
2930
localparam wbm_wr_drain = 3'b101;
2931
localparam wbm_rd       = 3'b011;
2932
localparam wbm_rd_drain = 3'b001;
2933 97 unneback
assign {wbs_adr_tag, wbs_adr_slot, wbs_adr_word} = wbs_adr_i;
2934 100 unneback
generate
2935
if (valid_mem==0) begin : no_valid_mem
2936
assign valid = 1'b1;
2937
end else begin : valid_mem_inst
2938
vl_dpram_1r1w
2939
    # ( .data_width(1), .addr_width(aw_slot), .memory_init(2), .debug(debug))
2940
    valid_mem ( .d_a(1'b1), .adr_a(wbs_adr_slot), .we_a(mem_done), .clk_a(wbm_clk),
2941
                .q_b(valid), .adr_b(wbs_adr_slot), .clk_b(wbs_clk));
2942
end
2943
endgenerate
2944
vl_dpram_1r1w
2945
    # ( .data_width(aw_tag), .addr_width(aw_slot), .memory_init(2), .debug(debug))
2946
    tag_mem ( .d_a(wbs_adr_tag), .adr_a(wbs_adr_slot), .we_a(mem_done), .clk_a(wbm_clk),
2947
              .q_b(tag), .adr_b(wbs_adr_slot), .clk_b(wbs_clk));
2948
assign hit = wbs_adr_tag == tag;
2949
vl_dpram_1r2w
2950
    # ( .data_width(1), .addr_width(aw_slot), .memory_init(2), .debug(debug))
2951
    dirty_mem (
2952
        .d_a(1'b1), .q_a(dirty), .adr_a(wbs_adr_slot), .we_a(wbs_cyc_i & wbs_we_i & wbs_ack_o), .clk_a(wbs_clk),
2953
        .d_b(1'b0), .adr_b(wbs_adr_slot), .we_b(mem_done), .clk_b(wbm_clk));
2954 103 unneback
generate
2955
if (wbs_mode=="B3") begin : inst_b3
2956 100 unneback
vl_wb_adr_inc # ( .adr_width(aw_s), .max_burst_width(wbs_max_burst_width)) adr_inc0 (
2957
    .cyc_i(wbs_cyc_i & (state==rdwr) & hit & valid),
2958
    .stb_i(wbs_stb_i & (state==rdwr) & hit & valid), // throttle depending on valid
2959 97 unneback
    .cti_i(wbs_cti_i),
2960
    .bte_i(wbs_bte_i),
2961
    .adr_i(wbs_adr_i),
2962
    .we_i (wbs_we_i),
2963
    .ack_o(wbs_ack_o),
2964
    .adr_o(wbs_adr),
2965 100 unneback
    .clk(wbs_clk),
2966
    .rst(wbs_rst));
2967 103 unneback
assign eoc = (wbs_cti_i==3'b000 | wbs_cti_i==3'b111) & wbs_ack_o;
2968
assign we = wbs_cyc_i &  wbs_we_i & wbs_ack_o;
2969
end else if (wbs_mode=="B4") begin : inst_b4
2970
end
2971
endgenerate
2972 97 unneback
vl_dpram_be_2r2w
2973 100 unneback
    # ( .a_data_width(dw_s), .a_addr_width(aw_slot+aw_offset), .b_data_width(dw_m), .debug(debug))
2974 103 unneback
    cache_mem ( .d_a(wbs_dat_i), .adr_a(wbs_adr[aw_slot+aw_offset-1:0]),   .be_a(wbs_sel_i), .we_a(we), .q_a(wbs_dat_o), .clk_a(wbs_clk),
2975 100 unneback
                .d_b(wbm_dat_i), .adr_b(wbm_adr_o[aw_slot+aw_offset-1:0]), .be_b(wbm_sel_o), .we_b(wbm_cyc_o & !wbm_we_o & wbs_ack_i), .q_b(wbm_dat_o), .clk_b(wbm_clk));
2976 97 unneback
always @ (posedge wbs_clk or posedge wbs_rst)
2977
if (wbs_rst)
2978 98 unneback
    state <= idle;
2979 97 unneback
else
2980
    case (state)
2981
    idle:
2982
        if (wbs_cyc_i)
2983
            state <= rdwr;
2984
    rdwr:
2985 100 unneback
        casex ({valid, hit, dirty, eoc})
2986
        4'b0xxx: state <= pull;
2987
        4'b11x1: state <= idle;
2988
        4'b101x: state <= push;
2989
        4'b100x: state <= pull;
2990
        endcase
2991 97 unneback
    push:
2992
        if (done)
2993
            state <= rdwr;
2994
    pull:
2995
        if (done)
2996
            state <= rdwr;
2997
    default: state <= idle;
2998
    endcase
2999
// cdc
3000
generate
3001
if (async==1) begin : cdc0
3002 100 unneback
vl_cdc cdc0 ( .start_pl(state==rdwr & (!valid | !hit)), .take_it_pl(mem_alert), .take_it_grant_pl(mem_done), .got_it_pl(done), .clk_src(wbs_clk), .rst_src(wbs_rst), .clk_dst(wbm_clk), .rst_dst(wbm_rst));
3003 97 unneback
end
3004
else begin : nocdc
3005 100 unneback
    assign mem_alert = state==rdwr & (!valid | !hit);
3006 97 unneback
    assign done = mem_done;
3007
end
3008
endgenerate
3009
// FSM generating a number of burts 4 cycles
3010
// actual number depends on data width ratio
3011
// nr_of_wbm_burst
3012 101 unneback
reg [nr_of_wbm_burst_width+wbm_burst_width-1:0]       cnt_rw, cnt_ack;
3013 97 unneback
always @ (posedge wbm_clk or posedge wbm_rst)
3014
if (wbm_rst)
3015 100 unneback
    cnt_rw <= {wbm_burst_width{1'b0}};
3016 97 unneback
else
3017 100 unneback
    if (wbm_cyc_o & wbm_stb_o & !wbm_stall_i)
3018
        cnt_rw <= cnt_rw + 1;
3019 98 unneback
always @ (posedge wbm_clk or posedge wbm_rst)
3020
if (wbm_rst)
3021 100 unneback
    cnt_ack <= {wbm_burst_width{1'b0}};
3022 98 unneback
else
3023 100 unneback
    if (wbm_ack_i)
3024
        cnt_ack <= cnt_ack + 1;
3025
generate
3026 101 unneback
if (nr_of_wbm_burst==1) begin : one_burst
3027 98 unneback
always @ (posedge wbm_clk or posedge wbm_rst)
3028
if (wbm_rst)
3029
    phase <= wbm_wait;
3030
else
3031
    case (phase)
3032
    wbm_wait:
3033
        if (mem_alert)
3034 100 unneback
            if (state==push)
3035
                phase <= wbm_wr;
3036
            else
3037
                phase <= wbm_rd;
3038 98 unneback
    wbm_wr:
3039 100 unneback
        if (&cnt_rw)
3040
            phase <= wbm_wr_drain;
3041
    wbm_wr_drain:
3042
        if (&cnt_ack)
3043 98 unneback
            phase <= wbm_rd;
3044
    wbm_rd:
3045 100 unneback
        if (&cnt_rw)
3046
            phase <= wbm_rd_drain;
3047
    wbm_rd_drain:
3048
        if (&cnt_ack)
3049
            phase <= wbm_wait;
3050 98 unneback
    default: phase <= wbm_wait;
3051
    endcase
3052 100 unneback
end else begin : multiple_burst
3053 101 unneback
always @ (posedge wbm_clk or posedge wbm_rst)
3054
if (wbm_rst)
3055
    phase <= wbm_wait;
3056
else
3057
    case (phase)
3058
    wbm_wait:
3059
        if (mem_alert)
3060
            if (state==push)
3061
                phase <= wbm_wr;
3062
            else
3063
                phase <= wbm_rd;
3064
    wbm_wr:
3065
        if (&cnt_rw[wbm_burst_width-1:0])
3066
            phase <= wbm_wr_drain;
3067
    wbm_wr_drain:
3068
        if (&cnt_ack)
3069
            phase <= wbm_rd;
3070
        else if (&cnt_ack[wbm_burst_width-1:0])
3071
            phase <= wbm_wr;
3072
    wbm_rd:
3073
        if (&cnt_rw[wbm_burst_width-1:0])
3074
            phase <= wbm_rd_drain;
3075
    wbm_rd_drain:
3076
        if (&cnt_ack)
3077
            phase <= wbm_wait;
3078
        else if (&cnt_ack[wbm_burst_width-1:0])
3079
            phase <= wbm_rd;
3080
    default: phase <= wbm_wait;
3081
    endcase
3082 100 unneback
end
3083
endgenerate
3084 101 unneback
assign mem_done = phase==wbm_rd_drain & (&cnt_ack) & wbm_ack_i;
3085 100 unneback
assign wbm_adr_o = (phase[2]) ? {tag, wbs_adr_slot, cnt_rw} : {wbs_adr_tag, wbs_adr_slot, cnt_rw};
3086
assign wbm_adr   = (phase[2]) ? {wbs_adr_slot, cnt_rw} : {wbs_adr_slot, cnt_rw};
3087
assign wbm_sel_o = {dw_m/8{1'b1}};
3088
assign wbm_cti_o = (&cnt_rw | !wbm_stb_o) ? 3'b111 : 3'b010;
3089 98 unneback
assign wbm_bte_o = bte;
3090 100 unneback
assign {wbm_we_o, wbm_stb_o, wbm_cyc_o}  = phase;
3091 97 unneback
endmodule
3092 103 unneback
// Wishbone to avalon bridge supporting one type of burst transfer only
3093
// intended use is together with cache above
3094
// WB B4 -> pipelined avalon
3095
module vl_wb_avalon_bridge (
3096
        // wishbone slave side
3097
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_stall_o,
3098
        // avalon master side
3099
        readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer,
3100
        // common
3101
        clk, rst);
3102
parameter adr_width = 30;
3103
parameter dat_width = 32;
3104
parameter burst_size = 4;
3105
input [dat_width-1:0] wbs_dat_i;
3106
input [adr_width-1:0] wbs_adr_i;
3107
input [dat_width/8-1:0]  wbs_sel_i;
3108
input [1:0]  wbs_bte_i;
3109
input [2:0]  wbs_cti_i;
3110
input wbs_we_i;
3111
input wbs_cyc_i;
3112
input wbs_stb_i;
3113 130 unneback
output [dat_width-1:0] wbs_dat_o;
3114 103 unneback
output wbs_ack_o;
3115
output wbs_stall_o;
3116
input [dat_width-1:0] readdata;
3117
input readdatavalid;
3118
output [dat_width-1:0] writedata;
3119
output [adr_width-1:0] address;
3120
output [dat_width/8-1:0]  be;
3121
output write;
3122
output read;
3123
output beginbursttransfer;
3124
output [3:0] burstcount;
3125
input waitrequest;
3126
input clk, rst;
3127
reg last_cyc_idle_or_eoc;
3128
reg [3:0] cnt;
3129
always @ (posedge clk or posedge rst)
3130
if (rst)
3131
    cnt <= 4'h0;
3132
else
3133
    if (beginbursttransfer & waitrequest)
3134
        cnt <= burst_size - 1;
3135
    else if (beginbursttransfer & !waitrequest)
3136
        cnt <= burst_size - 2;
3137
    else if (wbs_ack_o)
3138
        cnt <= cnt - 1;
3139
reg wr_ack;
3140
always @ (posedge clk or posedge rst)
3141
if (rst)
3142
    wr_ack <= 1'b0;
3143
else
3144
    wr_ack <=  (wbs_we_i & wbs_cyc_i & wbs_stb_i & !wbs_stall_o);
3145
// to avalon
3146
assign writedata = wbs_dat_i;
3147
assign address = wbs_adr_i;
3148
assign be = wbs_sel_i;
3149
assign write = cnt==(burst_size-1) & wbs_cyc_i &  wbs_we_i;
3150
assign read  = cnt==(burst_size-1) & wbs_cyc_i & !wbs_we_i;
3151
assign beginbursttransfer = cnt==4'h0 & wbs_cyc_i;
3152
assign burstcount = burst_size;
3153
// to wishbone
3154
assign wbs_dat_o = readdata;
3155
assign wbs_ack_o = wr_ack | readdatavalid;
3156
assign wbs_stall_o = waitrequest;
3157
endmodule
3158
module vl_wb_avalon_mem_cache (
3159
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i, wbs_dat_o, wbs_ack_o, wbs_stall_o, wbs_clk, wbs_rst,
3160
    readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst
3161
);
3162
// wishbone
3163
parameter wb_dat_width = 32;
3164
parameter wb_adr_width = 22;
3165
parameter wb_max_burst_width = 4;
3166
parameter wb_mode = "B4";
3167
// avalon
3168
parameter avalon_dat_width = 32;
3169 121 unneback
//localparam avalon_adr_width = wb_dat_width * wb_adr_width / avalon_dat_width;
3170 122 unneback
localparam avalon_adr_width =
3171
        (wb_dat_width==avalon_dat_width) ? wb_adr_width :
3172
        (wb_dat_width==avalon_dat_width*2) ? wb_adr_width+1 :
3173
        (wb_dat_width==avalon_dat_width*4) ? wb_adr_width+2 :
3174
        (wb_dat_width==avalon_dat_width*8) ? wb_adr_width+3 :
3175
        (wb_dat_width==avalon_dat_width*16) ? wb_adr_width+4 :
3176
        (wb_dat_width==avalon_dat_width*32) ? wb_adr_width+5 :
3177
        (wb_dat_width==avalon_dat_width/2) ? wb_adr_width-1 :
3178
        (wb_dat_width==avalon_dat_width/4) ? wb_adr_width-2 :
3179
        (wb_dat_width==avalon_dat_width/8) ? wb_adr_width-3 :
3180
        (wb_dat_width==avalon_dat_width/16) ? wb_adr_width-4 :
3181 123 unneback
        (wb_dat_width==avalon_dat_width/32) ? wb_adr_width-5 : 0;
3182 103 unneback
parameter avalon_burst_size = 4;
3183
// cache
3184
parameter async = 1;
3185
parameter nr_of_ways = 1;
3186
parameter aw_offset = 4;
3187
parameter aw_slot = 10;
3188
parameter valid_mem = 1;
3189
// shadow RAM
3190
parameter shadow_ram = 0;
3191
parameter shadow_ram_adr_width = 10;
3192
parameter shadow_ram_size = 1024;
3193
parameter shadow_ram_init = 2; // 0: no init, 1: from file, 2: with zero
3194
parameter shadow_ram_file = "vl_ram.v";
3195
input [wb_dat_width-1:0] wbs_dat_i;
3196
input [wb_adr_width-1:0] wbs_adr_i; // dont include a1,a0
3197
input [wb_dat_width/8-1:0] wbs_sel_i;
3198
input [2:0] wbs_cti_i;
3199
input [1:0] wbs_bte_i;
3200
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
3201
output [wb_dat_width-1:0] wbs_dat_o;
3202
output wbs_ack_o;
3203
output wbs_stall_o;
3204
input wbs_clk, wbs_rst;
3205
input [avalon_dat_width-1:0] readdata;
3206
input readdatavalid;
3207
output [avalon_dat_width-1:0] writedata;
3208
output [avalon_adr_width-1:0] address;
3209
output [avalon_dat_width/8-1:0]  be;
3210
output write;
3211
output read;
3212
output beginbursttransfer;
3213
output [3:0] burstcount;
3214
input waitrequest;
3215
input clk, rst;
3216
wire [wb_dat_width-1:0] wb1_dat_o;
3217
wire [wb_adr_width-1:0] wb1_adr_o;
3218
wire [wb_dat_width/8-1:0] wb1_sel_o;
3219
wire [2:0] wb1_cti_o;
3220
wire [1:0] wb1_bte_o;
3221
wire wb1_we_o;
3222
wire wb1_stb_o;
3223
wire wb1_cyc_o;
3224
wire wb1_stall_i;
3225
wire [wb_dat_width-1:0] wb1_dat_i;
3226
wire wb1_ack_i;
3227 129 unneback
wire [avalon_dat_width-1:0] wb2_dat_o;
3228
wire [avalon_adr_width-1:0] wb2_adr_o;
3229
wire [avalon_dat_width/8-1:0] wb2_sel_o;
3230 103 unneback
wire [2:0] wb2_cti_o;
3231
wire [1:0] wb2_bte_o;
3232
wire wb2_we_o;
3233
wire wb2_stb_o;
3234
wire wb2_cyc_o;
3235
wire wb2_stall_i;
3236 129 unneback
wire [avalon_dat_width-1:0] wb2_dat_i;
3237 103 unneback
wire wb2_ack_i;
3238
vl_wb_shadow_ram # ( .dat_width(wb_dat_width), .mode(wb_mode), .max_burst_width(wb_max_burst_width),
3239 120 unneback
                 .shadow_mem_adr_width(shadow_ram_adr_width), .shadow_mem_size(shadow_ram_size), .shadow_mem_init(shadow_ram_init), .shadow_mem_file(shadow_ram_file),
3240 103 unneback
                 .main_mem_adr_width(wb_adr_width))
3241
shadow_ram0 (
3242
    .wbs_dat_i(wbs_dat_i), .wbs_adr_i(wbs_adr_i), .wbs_cti_i(wbs_cti_i), .wbs_bte_i(wbs_bte_i), .wbs_sel_i(wbs_sel_i), .wbs_we_i(wbs_we_i), .wbs_stb_i(wbs_stb_i), .wbs_cyc_i(wbs_cyc_i),
3243
    .wbs_dat_o(wbs_dat_o), .wbs_ack_o(wbs_ack_o), .wbs_stall_o(wbs_stall_o),
3244
    .wbm_dat_o(wb1_dat_o), .wbm_adr_o(wb1_adr_o), .wbm_cti_o(wb1_cti_o), .wbm_bte_o(wb1_bte_o), .wbm_sel_o(wb1_sel_o), .wbm_we_o(wb1_we_o), .wbm_stb_o(wb1_stb_o), .wbm_cyc_o(wb1_cyc_o),
3245
    .wbm_dat_i(wb1_dat_i), .wbm_ack_i(wb1_ack_i), .wbm_stall_i(wb1_stall_i),
3246
    .wb_clk(wbs_clk), .wb_rst(wbs_rst));
3247
vl_wb_cache
3248
# ( .dw_s(wb_dat_width), .aw_s(wb_adr_width), .dw_m(avalon_dat_width), .wbs_mode(wb_mode), .wbs_max_burst_width(wb_max_burst_width), .async(async), .nr_of_ways(nr_of_ways), .aw_offset(aw_offset), .aw_slot(aw_slot), .valid_mem(valid_mem))
3249
cache0 (
3250
    .wbs_dat_i(wb1_dat_o), .wbs_adr_i(wb1_adr_o), .wbs_sel_i(wb1_sel_o), .wbs_cti_i(wb1_cti_o), .wbs_bte_i(wb1_bte_o), .wbs_we_i(wb1_we_o), .wbs_stb_i(wb1_stb_o), .wbs_cyc_i(wb1_cyc_o),
3251
    .wbs_dat_o(wb1_dat_i), .wbs_ack_o(wb1_ack_i), .wbs_stall_o(wb1_stall_i), .wbs_clk(wbs_clk), .wbs_rst(wbs_rst),
3252
    .wbm_dat_o(wb2_dat_o), .wbm_adr_o(wb2_adr_o), .wbm_sel_o(wb2_sel_o), .wbm_cti_o(wb2_cti_o), .wbm_bte_o(wb2_bte_o), .wbm_we_o(wb2_we_o), .wbm_stb_o(wb2_stb_o), .wbm_cyc_o(wb2_cyc_o),
3253
    .wbm_dat_i(wb2_dat_i), .wbm_ack_i(wb2_ack_i), .wbm_stall_i(wb2_stall_i), .wbm_clk(clk), .wbm_rst(rst));
3254
vl_wb_avalon_bridge # ( .adr_width(avalon_adr_width), .dat_width(avalon_dat_width), .burst_size(avalon_burst_size))
3255
bridge0 (
3256
        // wishbone slave side
3257
        .wbs_dat_i(wb2_dat_o), .wbs_adr_i(wb2_adr_o), .wbs_sel_i(wb2_sel_o), .wbs_bte_i(wb2_bte_o), .wbs_cti_i(wb2_cti_o), .wbs_we_i(wb2_we_o), .wbs_cyc_i(wb2_cyc_o), .wbs_stb_i(wb2_stb_o),
3258
        .wbs_dat_o(wb2_dat_i), .wbs_ack_o(wb2_ack_i), .wbs_stall_o(wb2_stall_i),
3259
        // avalon master side
3260
        .readdata(readdata), .readdatavalid(readdatavalid), .address(address), .read(read), .be(be), .write(write), .burstcount(burstcount), .writedata(writedata), .waitrequest(waitrequest), .beginbursttransfer(beginbursttransfer),
3261
        // common
3262
        .clk(clk), .rst(rst));
3263
endmodule
3264 18 unneback
//////////////////////////////////////////////////////////////////////
3265
////                                                              ////
3266
////  Arithmetic functions                                        ////
3267
////                                                              ////
3268
////  Description                                                 ////
3269
////  Arithmetic functions for ALU and DSP                        ////
3270
////                                                              ////
3271
////                                                              ////
3272
////  To Do:                                                      ////
3273
////   -                                                          ////
3274
////                                                              ////
3275
////  Author(s):                                                  ////
3276
////      - Michael Unneback, unneback@opencores.org              ////
3277
////        ORSoC AB                                              ////
3278
////                                                              ////
3279
//////////////////////////////////////////////////////////////////////
3280
////                                                              ////
3281
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
3282
////                                                              ////
3283
//// This source file may be used and distributed without         ////
3284
//// restriction provided that this copyright statement is not    ////
3285
//// removed from the file and that any derivative work contains  ////
3286
//// the original copyright notice and the associated disclaimer. ////
3287
////                                                              ////
3288
//// This source file is free software; you can redistribute it   ////
3289
//// and/or modify it under the terms of the GNU Lesser General   ////
3290
//// Public License as published by the Free Software Foundation; ////
3291
//// either version 2.1 of the License, or (at your option) any   ////
3292
//// later version.                                               ////
3293
////                                                              ////
3294
//// This source is distributed in the hope that it will be       ////
3295
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3296
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3297
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3298
//// details.                                                     ////
3299
////                                                              ////
3300
//// You should have received a copy of the GNU Lesser General    ////
3301
//// Public License along with this source; if not, download it   ////
3302
//// from http://www.opencores.org/lgpl.shtml                     ////
3303
////                                                              ////
3304
//////////////////////////////////////////////////////////////////////
3305
// signed multiplication
3306
module vl_mults (a,b,p);
3307
parameter operand_a_width = 18;
3308
parameter operand_b_width = 18;
3309
parameter result_hi = 35;
3310
parameter result_lo = 0;
3311
input [operand_a_width-1:0] a;
3312
input [operand_b_width-1:0] b;
3313
output [result_hi:result_lo] p;
3314
wire signed [operand_a_width-1:0] ai;
3315
wire signed [operand_b_width-1:0] bi;
3316
wire signed [operand_a_width+operand_b_width-1:0] result;
3317
    assign ai = a;
3318
    assign bi = b;
3319
    assign result = ai * bi;
3320
    assign p = result[result_hi:result_lo];
3321
endmodule
3322
module vl_mults18x18 (a,b,p);
3323
input [17:0] a,b;
3324
output [35:0] p;
3325
vl_mult
3326
    # (.operand_a_width(18), .operand_b_width(18))
3327
    mult0 (.a(a), .b(b), .p(p));
3328
endmodule
3329
// unsigned multiplication
3330
module vl_mult (a,b,p);
3331
parameter operand_a_width = 18;
3332
parameter operand_b_width = 18;
3333
parameter result_hi = 35;
3334
parameter result_lo = 0;
3335
input [operand_a_width-1:0] a;
3336
input [operand_b_width-1:0] b;
3337
output [result_hi:result_hi] p;
3338
wire [operand_a_width+operand_b_width-1:0] result;
3339
    assign result = a * b;
3340
    assign p = result[result_hi:result_lo];
3341
endmodule
3342
// shift unit
3343
// supporting the following shift functions
3344
//   SLL
3345
//   SRL
3346
//   SRA
3347
module vl_shift_unit_32( din, s, dout, opcode);
3348
input [31:0] din; // data in operand
3349
input [4:0] s; // shift operand
3350
input [1:0] opcode;
3351
output [31:0] dout;
3352
parameter opcode_sll = 2'b00;
3353
//parameter opcode_srl = 2'b01;
3354
parameter opcode_sra = 2'b10;
3355
//parameter opcode_ror = 2'b11;
3356
wire sll, sra;
3357
assign sll = opcode == opcode_sll;
3358
assign sra = opcode == opcode_sra;
3359
wire [15:1] s1;
3360
wire [3:0] sign;
3361
wire [7:0] tmp [0:3];
3362
// first stage is multiplier based
3363
// shift operand as fractional 8.7
3364
assign s1[15] = sll & s[2:0]==3'd7;
3365
assign s1[14] = sll & s[2:0]==3'd6;
3366
assign s1[13] = sll & s[2:0]==3'd5;
3367
assign s1[12] = sll & s[2:0]==3'd4;
3368
assign s1[11] = sll & s[2:0]==3'd3;
3369
assign s1[10] = sll & s[2:0]==3'd2;
3370
assign s1[ 9] = sll & s[2:0]==3'd1;
3371
assign s1[ 8] = s[2:0]==3'd0;
3372
assign s1[ 7] = !sll & s[2:0]==3'd1;
3373
assign s1[ 6] = !sll & s[2:0]==3'd2;
3374
assign s1[ 5] = !sll & s[2:0]==3'd3;
3375
assign s1[ 4] = !sll & s[2:0]==3'd4;
3376
assign s1[ 3] = !sll & s[2:0]==3'd5;
3377
assign s1[ 2] = !sll & s[2:0]==3'd6;
3378
assign s1[ 1] = !sll & s[2:0]==3'd7;
3379
assign sign[3] = din[31] & sra;
3380
assign sign[2] = sign[3] & (&din[31:24]);
3381
assign sign[1] = sign[2] & (&din[23:16]);
3382
assign sign[0] = sign[1] & (&din[15:8]);
3383
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte3 ( .a({sign[3], {8{sign[3]}},din[31:24], din[23:16]}), .b({1'b0,s1}), .p(tmp[3]));
3384
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte2 ( .a({sign[2], din[31:24]  ,din[23:16],  din[15:8]}), .b({1'b0,s1}), .p(tmp[2]));
3385
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte1 ( .a({sign[1], din[23:16]  ,din[15:8],   din[7:0]}), .b({1'b0,s1}), .p(tmp[1]));
3386
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte0 ( .a({sign[0], din[15:8]   ,din[7:0],    8'h00}),      .b({1'b0,s1}), .p(tmp[0]));
3387
// second stage is multiplexer based
3388
// shift on byte level
3389
// mux byte 3
3390
assign dout[31:24] = (s[4:3]==2'b00) ? tmp[3] :
3391
                     (sll & s[4:3]==2'b01) ? tmp[2] :
3392
                     (sll & s[4:3]==2'b10) ? tmp[1] :
3393
                     (sll & s[4:3]==2'b11) ? tmp[0] :
3394
                     {8{sign[3]}};
3395
// mux byte 2
3396
assign dout[23:16] = (s[4:3]==2'b00) ? tmp[2] :
3397
                     (sll & s[4:3]==2'b01) ? tmp[1] :
3398
                     (sll & s[4:3]==2'b10) ? tmp[0] :
3399
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
3400
                     (s[4:3]==2'b01) ? tmp[3] :
3401
                     {8{sign[3]}};
3402
// mux byte 1
3403
assign dout[15:8]  = (s[4:3]==2'b00) ? tmp[1] :
3404
                     (sll & s[4:3]==2'b01) ? tmp[0] :
3405
                     (sll & s[4:3]==2'b10) ? {8{1'b0}} :
3406
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
3407
                     (s[4:3]==2'b01) ? tmp[2] :
3408
                     (s[4:3]==2'b10) ? tmp[3] :
3409
                     {8{sign[3]}};
3410
// mux byte 0
3411
assign dout[7:0]   = (s[4:3]==2'b00) ? tmp[0] :
3412
                     (sll) ?  {8{1'b0}}:
3413
                     (s[4:3]==2'b01) ? tmp[1] :
3414
                     (s[4:3]==2'b10) ? tmp[2] :
3415
                     tmp[3];
3416
endmodule
3417
// logic unit
3418
// supporting the following logic functions
3419
//    a and b
3420
//    a or  b
3421
//    a xor b
3422
//    not b
3423
module vl_logic_unit( a, b, result, opcode);
3424
parameter width = 32;
3425
parameter opcode_and = 2'b00;
3426
parameter opcode_or  = 2'b01;
3427
parameter opcode_xor = 2'b10;
3428
input [width-1:0] a,b;
3429
output [width-1:0] result;
3430
input [1:0] opcode;
3431
assign result = (opcode==opcode_and) ? a & b :
3432
                (opcode==opcode_or)  ? a | b :
3433
                (opcode==opcode_xor) ? a ^ b :
3434
                b;
3435
endmodule

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