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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Blame information for rev 136

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Line No. Rev Author Line
1 60 unneback
// default SYN_KEEP definition
2 98 unneback
    // ACTEL FPGA should not use logic to handle rw collision
3 136 unneback
///////////////////////////////////////
4
// dependencies
5
///////////////////////////////////////
6 97 unneback
// size to width
7 6 unneback
//////////////////////////////////////////////////////////////////////
8
////                                                              ////
9
////  Versatile library, clock and reset                          ////
10
////                                                              ////
11
////  Description                                                 ////
12
////  Logic related to clock and reset                            ////
13
////                                                              ////
14
////                                                              ////
15
////  To Do:                                                      ////
16
////   - add more different registers                             ////
17
////                                                              ////
18
////  Author(s):                                                  ////
19
////      - Michael Unneback, unneback@opencores.org              ////
20
////        ORSoC AB                                              ////
21
////                                                              ////
22
//////////////////////////////////////////////////////////////////////
23
////                                                              ////
24
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
25
////                                                              ////
26
//// This source file may be used and distributed without         ////
27
//// restriction provided that this copyright statement is not    ////
28
//// removed from the file and that any derivative work contains  ////
29
//// the original copyright notice and the associated disclaimer. ////
30
////                                                              ////
31
//// This source file is free software; you can redistribute it   ////
32
//// and/or modify it under the terms of the GNU Lesser General   ////
33
//// Public License as published by the Free Software Foundation; ////
34
//// either version 2.1 of the License, or (at your option) any   ////
35
//// later version.                                               ////
36
////                                                              ////
37
//// This source is distributed in the hope that it will be       ////
38
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
39
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
40
//// PURPOSE.  See the GNU Lesser General Public License for more ////
41
//// details.                                                     ////
42
////                                                              ////
43
//// You should have received a copy of the GNU Lesser General    ////
44
//// Public License along with this source; if not, download it   ////
45
//// from http://www.opencores.org/lgpl.shtml                     ////
46
////                                                              ////
47
//////////////////////////////////////////////////////////////////////
48 48 unneback
`timescale 1 ns/100 ps
49 6 unneback
// Global buffer
50
// usage:
51
// use to enable global buffers for high fan out signals such as clock and reset
52
// Version: 8.4 8.4.0.33
53
module gbuf(GL,CLK);
54
output GL;
55
input  CLK;
56
    wire GND;
57
    GND GND_1_net(.Y(GND));
58
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
59
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
60
endmodule
61
`timescale 1 ns/1 ns
62
module vl_gbuf ( i, o);
63
input i;
64
output o;
65
`ifdef SIM_GBUF
66
assign o=i;
67
`else
68
gbuf gbuf_i0 ( .CLK(i), .GL(o));
69
`endif
70
endmodule
71
 //ACTEL
72
// sync reset
73 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
74 6 unneback
// output active high global reset sync with two DFFs 
75
`timescale 1 ns/100 ps
76
module vl_sync_rst ( rst_n_i, rst_o, clk);
77
input rst_n_i, clk;
78
output rst_o;
79 18 unneback
reg [1:0] tmp;
80 6 unneback
always @ (posedge clk or negedge rst_n_i)
81
if (!rst_n_i)
82 17 unneback
        tmp <= 2'b11;
83 6 unneback
else
84 33 unneback
        tmp <= {1'b0,tmp[1]};
85 17 unneback
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
86 6 unneback
endmodule
87
// vl_pll
88 32 unneback
///////////////////////////////////////////////////////////////////////////////
89 17 unneback
`timescale 1 ps/1 ps
90 6 unneback
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
91
parameter index = 0;
92
parameter number_of_clk = 1;
93 17 unneback
parameter period_time_0 = 20000;
94
parameter period_time_1 = 20000;
95
parameter period_time_2 = 20000;
96
parameter lock_delay = 2000000;
97 6 unneback
input clk_i, rst_n_i;
98
output lock;
99
output reg [0:number_of_clk-1] clk_o;
100
output [0:number_of_clk-1] rst_o;
101
`ifdef SIM_PLL
102
always
103
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
104
generate if (number_of_clk > 1)
105
always
106
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
107
endgenerate
108
generate if (number_of_clk > 2)
109
always
110
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
111
endgenerate
112
genvar i;
113
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
114
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
115
end
116
endgenerate
117
assign #lock_delay lock = rst_n_i;
118
endmodule
119
`else
120
generate if (number_of_clk==1 & index==0) begin
121
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
122
end
123
endgenerate // index==0
124
generate if (number_of_clk==1 & index==1) begin
125
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
126
end
127
endgenerate // index==1
128
generate if (number_of_clk==1 & index==2) begin
129
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
130
end
131
endgenerate // index==2
132
generate if (number_of_clk==1 & index==3) begin
133
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
134
end
135
endgenerate // index==0
136
generate if (number_of_clk==2 & index==0) begin
137
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
138
end
139
endgenerate // index==0
140
generate if (number_of_clk==2 & index==1) begin
141
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
142
end
143
endgenerate // index==1
144
generate if (number_of_clk==2 & index==2) begin
145
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
146
end
147
endgenerate // index==2
148
generate if (number_of_clk==2 & index==3) begin
149
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
150
end
151
endgenerate // index==0
152
generate if (number_of_clk==3 & index==0) begin
153
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
154
end
155
endgenerate // index==0
156
generate if (number_of_clk==3 & index==1) begin
157
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
158
end
159
endgenerate // index==1
160
generate if (number_of_clk==3 & index==2) begin
161
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
162
end
163
endgenerate // index==2
164
generate if (number_of_clk==3 & index==3) begin
165
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
166
end
167
endgenerate // index==0
168
genvar i;
169
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
170 40 unneback
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
171 6 unneback
end
172
endgenerate
173
endmodule
174
`endif
175 32 unneback
///////////////////////////////////////////////////////////////////////////////
176 6 unneback
 //actel
177
//////////////////////////////////////////////////////////////////////
178
////                                                              ////
179
////  Versatile library, registers                                ////
180
////                                                              ////
181
////  Description                                                 ////
182
////  Different type of registers                                 ////
183
////                                                              ////
184
////                                                              ////
185
////  To Do:                                                      ////
186
////   - add more different registers                             ////
187
////                                                              ////
188
////  Author(s):                                                  ////
189
////      - Michael Unneback, unneback@opencores.org              ////
190
////        ORSoC AB                                              ////
191
////                                                              ////
192
//////////////////////////////////////////////////////////////////////
193
////                                                              ////
194
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
195
////                                                              ////
196
//// This source file may be used and distributed without         ////
197
//// restriction provided that this copyright statement is not    ////
198
//// removed from the file and that any derivative work contains  ////
199
//// the original copyright notice and the associated disclaimer. ////
200
////                                                              ////
201
//// This source file is free software; you can redistribute it   ////
202
//// and/or modify it under the terms of the GNU Lesser General   ////
203
//// Public License as published by the Free Software Foundation; ////
204
//// either version 2.1 of the License, or (at your option) any   ////
205
//// later version.                                               ////
206
////                                                              ////
207
//// This source is distributed in the hope that it will be       ////
208
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
209
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
210
//// PURPOSE.  See the GNU Lesser General Public License for more ////
211
//// details.                                                     ////
212
////                                                              ////
213
//// You should have received a copy of the GNU Lesser General    ////
214
//// Public License along with this source; if not, download it   ////
215
//// from http://www.opencores.org/lgpl.shtml                     ////
216
////                                                              ////
217
//////////////////////////////////////////////////////////////////////
218 18 unneback
module vl_dff ( d, q, clk, rst);
219 6 unneback
        parameter width = 1;
220
        parameter reset_value = 0;
221
        input [width-1:0] d;
222
        input clk, rst;
223
        output reg [width-1:0] q;
224
        always @ (posedge clk or posedge rst)
225
        if (rst)
226
                q <= reset_value;
227
        else
228
                q <= d;
229
endmodule
230 18 unneback
module vl_dff_array ( d, q, clk, rst);
231 6 unneback
        parameter width = 1;
232
        parameter depth = 2;
233
        parameter reset_value = 1'b0;
234
        input [width-1:0] d;
235
        input clk, rst;
236
        output [width-1:0] q;
237
        reg  [0:depth-1] q_tmp [width-1:0];
238
        integer i;
239
        always @ (posedge clk or posedge rst)
240
        if (rst) begin
241
            for (i=0;i<depth;i=i+1)
242
                q_tmp[i] <= {width{reset_value}};
243
        end else begin
244
            q_tmp[0] <= d;
245
            for (i=1;i<depth;i=i+1)
246
                q_tmp[i] <= q_tmp[i-1];
247
        end
248
    assign q = q_tmp[depth-1];
249
endmodule
250 18 unneback
module vl_dff_ce ( d, ce, q, clk, rst);
251 6 unneback
        parameter width = 1;
252
        parameter reset_value = 0;
253
        input [width-1:0] d;
254
        input ce, clk, rst;
255
        output reg [width-1:0] q;
256
        always @ (posedge clk or posedge rst)
257
        if (rst)
258
                q <= reset_value;
259
        else
260
                if (ce)
261
                        q <= d;
262
endmodule
263 18 unneback
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
264 8 unneback
        parameter width = 1;
265
        parameter reset_value = 0;
266
        input [width-1:0] d;
267 10 unneback
        input ce, clear, clk, rst;
268 8 unneback
        output reg [width-1:0] q;
269
        always @ (posedge clk or posedge rst)
270
        if (rst)
271
            q <= reset_value;
272
        else
273
            if (ce)
274
                if (clear)
275
                    q <= {width{1'b0}};
276
                else
277
                    q <= d;
278
endmodule
279 24 unneback
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
280
        parameter width = 1;
281
        parameter reset_value = 0;
282
        input [width-1:0] d;
283
        input ce, set, clk, rst;
284
        output reg [width-1:0] q;
285
        always @ (posedge clk or posedge rst)
286
        if (rst)
287
            q <= reset_value;
288
        else
289
            if (ce)
290
                if (set)
291
                    q <= {width{1'b1}};
292
                else
293
                    q <= d;
294
endmodule
295 29 unneback
module vl_spr ( sp, r, q, clk, rst);
296 64 unneback
        //parameter width = 1;
297
        parameter reset_value = 1'b0;
298 29 unneback
        input sp, r;
299
        output reg q;
300
        input clk, rst;
301
        always @ (posedge clk or posedge rst)
302
        if (rst)
303
            q <= reset_value;
304
        else
305
            if (sp)
306
                q <= 1'b1;
307
            else if (r)
308
                q <= 1'b0;
309
endmodule
310
module vl_srp ( s, rp, q, clk, rst);
311
        parameter width = 1;
312
        parameter reset_value = 0;
313
        input s, rp;
314
        output reg q;
315
        input clk, rst;
316
        always @ (posedge clk or posedge rst)
317
        if (rst)
318
            q <= reset_value;
319
        else
320
            if (rp)
321
                q <= 1'b0;
322
            else if (s)
323
                q <= 1'b1;
324
endmodule
325 18 unneback
module vl_dff_sr ( aclr, aset, clock, data, q);
326 6 unneback
    input         aclr;
327
    input         aset;
328
    input         clock;
329
    input         data;
330
    output reg    q;
331
   always @ (posedge clock or posedge aclr or posedge aset)
332
     if (aclr)
333
       q <= 1'b0;
334
     else if (aset)
335
       q <= 1'b1;
336
     else
337
       q <= data;
338
endmodule
339
// LATCH
340
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
341 40 unneback
module vl_latch ( d, le, q, clk);
342 6 unneback
input d, le;
343 48 unneback
input clk;
344
always @ (le or d)
345 60 unneback
if (le)
346 48 unneback
    d <= q;
347 6 unneback
endmodule
348 18 unneback
module vl_shreg ( d, q, clk, rst);
349 17 unneback
parameter depth = 10;
350
input d;
351
output q;
352
input clk, rst;
353
reg [1:depth] dffs;
354
always @ (posedge clk or posedge rst)
355
if (rst)
356
    dffs <= {depth{1'b0}};
357
else
358
    dffs <= {d,dffs[1:depth-1]};
359
assign q = dffs[depth];
360
endmodule
361 18 unneback
module vl_shreg_ce ( d, ce, q, clk, rst);
362 17 unneback
parameter depth = 10;
363
input d, ce;
364
output q;
365
input clk, rst;
366
reg [1:depth] dffs;
367
always @ (posedge clk or posedge rst)
368
if (rst)
369
    dffs <= {depth{1'b0}};
370
else
371
    if (ce)
372
        dffs <= {d,dffs[1:depth-1]};
373
assign q = dffs[depth];
374
endmodule
375 18 unneback
module vl_delay ( d, q, clk, rst);
376 15 unneback
parameter depth = 10;
377
input d;
378
output q;
379
input clk, rst;
380
reg [1:depth] dffs;
381
always @ (posedge clk or posedge rst)
382
if (rst)
383
    dffs <= {depth{1'b0}};
384
else
385
    dffs <= {d,dffs[1:depth-1]};
386
assign q = dffs[depth];
387
endmodule
388 18 unneback
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
389 17 unneback
parameter depth = 10;
390
input d;
391
output q, emptyflag;
392
input clk, rst;
393
reg [1:depth] dffs;
394
always @ (posedge clk or posedge rst)
395
if (rst)
396
    dffs <= {depth{1'b0}};
397
else
398
    dffs <= {d,dffs[1:depth-1]};
399
assign q = dffs[depth];
400
assign emptyflag = !(|dffs);
401
endmodule
402 98 unneback
module vl_pulse2toggle ( pl, q, clk, rst);
403 94 unneback
input pl;
404 98 unneback
output reg q;
405 94 unneback
input clk, rst;
406
always @ (posedge clk or posedge rst)
407
if (rst)
408
    q <= 1'b0;
409
else
410
    q <= pl ^ q;
411
endmodule
412 98 unneback
module vl_toggle2pulse (d, pl, clk, rst);
413 94 unneback
input d;
414
output pl;
415
input clk, rst;
416
reg dff;
417
always @ (posedge clk or posedge rst)
418
if (rst)
419
    dff <= 1'b0;
420
else
421
    dff <= d;
422 98 unneback
assign pl = d ^ dff;
423 94 unneback
endmodule
424
module vl_synchronizer (d, q, clk, rst);
425
input d;
426
output reg q;
427 116 unneback
input clk, rst;
428 94 unneback
reg dff;
429
always @ (posedge clk or posedge rst)
430
if (rst)
431 100 unneback
    {q,dff} <= 2'b00;
432 94 unneback
else
433 100 unneback
    {q,dff} <= {dff,d};
434 94 unneback
endmodule
435 97 unneback
module vl_cdc ( start_pl, take_it_pl, take_it_grant_pl, got_it_pl, clk_src, rst_src, clk_dst, rst_dst);
436 94 unneback
input start_pl;
437
output take_it_pl;
438
input take_it_grant_pl; // note: connect to take_it_pl to generate automatic ack
439
output got_it_pl;
440
input clk_src, rst_src;
441
input clk_dst, rst_dst;
442
wire take_it_tg, take_it_tg_sync;
443
wire got_it_tg, got_it_tg_sync;
444
// src -> dst
445
vl_pulse2toggle p2t0 (
446
    .pl(start_pl),
447
    .q(take_it_tg),
448
    .clk(clk_src),
449
    .rst(rst_src));
450
vl_synchronizer sync0 (
451
    .d(take_it_tg),
452
    .q(take_it_tg_sync),
453
    .clk(clk_dst),
454
    .rst(rst_dst));
455
vl_toggle2pulse t2p0 (
456 100 unneback
    .d(take_it_tg_sync),
457 94 unneback
    .pl(take_it_pl),
458
    .clk(clk_dst),
459
    .rst(rst_dst));
460
// dst -> src
461 98 unneback
vl_pulse2toggle p2t1 (
462 94 unneback
    .pl(take_it_grant_pl),
463
    .q(got_it_tg),
464
    .clk(clk_dst),
465
    .rst(rst_dst));
466
vl_synchronizer sync1 (
467
    .d(got_it_tg),
468
    .q(got_it_tg_sync),
469
    .clk(clk_src),
470
    .rst(rst_src));
471
vl_toggle2pulse t2p1 (
472 100 unneback
    .d(got_it_tg_sync),
473 94 unneback
    .pl(got_it_pl),
474
    .clk(clk_src),
475
    .rst(rst_src));
476
endmodule
477 6 unneback
//////////////////////////////////////////////////////////////////////
478
////                                                              ////
479 18 unneback
////  Logic functions                                             ////
480
////                                                              ////
481
////  Description                                                 ////
482
////  Logic functions such as multiplexers                        ////
483
////                                                              ////
484
////                                                              ////
485
////  To Do:                                                      ////
486
////   -                                                          ////
487
////                                                              ////
488
////  Author(s):                                                  ////
489
////      - Michael Unneback, unneback@opencores.org              ////
490
////        ORSoC AB                                              ////
491
////                                                              ////
492
//////////////////////////////////////////////////////////////////////
493
////                                                              ////
494
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
495
////                                                              ////
496
//// This source file may be used and distributed without         ////
497
//// restriction provided that this copyright statement is not    ////
498
//// removed from the file and that any derivative work contains  ////
499
//// the original copyright notice and the associated disclaimer. ////
500
////                                                              ////
501
//// This source file is free software; you can redistribute it   ////
502
//// and/or modify it under the terms of the GNU Lesser General   ////
503
//// Public License as published by the Free Software Foundation; ////
504
//// either version 2.1 of the License, or (at your option) any   ////
505
//// later version.                                               ////
506
////                                                              ////
507
//// This source is distributed in the hope that it will be       ////
508
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
509
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
510
//// PURPOSE.  See the GNU Lesser General Public License for more ////
511
//// details.                                                     ////
512
////                                                              ////
513
//// You should have received a copy of the GNU Lesser General    ////
514
//// Public License along with this source; if not, download it   ////
515
//// from http://www.opencores.org/lgpl.shtml                     ////
516
////                                                              ////
517
//////////////////////////////////////////////////////////////////////
518 36 unneback
module vl_mux_andor ( a, sel, dout);
519
parameter width = 32;
520
parameter nr_of_ports = 4;
521
input [nr_of_ports*width-1:0] a;
522
input [nr_of_ports-1:0] sel;
523
output reg [width-1:0] dout;
524 38 unneback
integer i,j;
525 36 unneback
always @ (a, sel)
526
begin
527
    dout = a[width-1:0] & {width{sel[0]}};
528 42 unneback
    for (i=1;i<nr_of_ports;i=i+1)
529
        for (j=0;j<width;j=j+1)
530
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
531 36 unneback
end
532
endmodule
533 34 unneback
module vl_mux2_andor ( a1, a0, sel, dout);
534
parameter width = 32;
535 35 unneback
localparam nr_of_ports = 2;
536 34 unneback
input [width-1:0] a1, a0;
537
input [nr_of_ports-1:0] sel;
538
output [width-1:0] dout;
539 36 unneback
vl_mux_andor
540 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
541 36 unneback
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
542 34 unneback
endmodule
543
module vl_mux3_andor ( a2, a1, a0, sel, dout);
544
parameter width = 32;
545 35 unneback
localparam nr_of_ports = 3;
546 34 unneback
input [width-1:0] a2, a1, a0;
547
input [nr_of_ports-1:0] sel;
548
output [width-1:0] dout;
549 36 unneback
vl_mux_andor
550 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
551 36 unneback
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
552 34 unneback
endmodule
553 18 unneback
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
554
parameter width = 32;
555 35 unneback
localparam nr_of_ports = 4;
556 18 unneback
input [width-1:0] a3, a2, a1, a0;
557
input [nr_of_ports-1:0] sel;
558 22 unneback
output [width-1:0] dout;
559 36 unneback
vl_mux_andor
560 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
561 36 unneback
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
562 18 unneback
endmodule
563
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
564
parameter width = 32;
565 35 unneback
localparam nr_of_ports = 5;
566 18 unneback
input [width-1:0] a4, a3, a2, a1, a0;
567
input [nr_of_ports-1:0] sel;
568 22 unneback
output [width-1:0] dout;
569 36 unneback
vl_mux_andor
570 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
571 36 unneback
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
572 18 unneback
endmodule
573
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
574
parameter width = 32;
575 35 unneback
localparam nr_of_ports = 6;
576 18 unneback
input [width-1:0] a5, a4, a3, a2, a1, a0;
577
input [nr_of_ports-1:0] sel;
578 22 unneback
output [width-1:0] dout;
579 36 unneback
vl_mux_andor
580 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
581 36 unneback
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
582 18 unneback
endmodule
583 43 unneback
module vl_parity_generate (data, parity);
584
parameter word_size = 32;
585
parameter chunk_size = 8;
586
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
587
input [word_size-1:0] data;
588
output reg [word_size/chunk_size-1:0] parity;
589
integer i,j;
590
always @ (data)
591
for (i=0;i<word_size/chunk_size;i=i+1) begin
592
    parity[i] = parity_type;
593
    for (j=0;j<chunk_size;j=j+1) begin
594 46 unneback
        parity[i] = data[i*chunk_size+j] ^ parity[i];
595 43 unneback
    end
596
end
597
endmodule
598
module vl_parity_check( data, parity, parity_error);
599
parameter word_size = 32;
600
parameter chunk_size = 8;
601
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
602
input [word_size-1:0] data;
603
input [word_size/chunk_size-1:0] parity;
604
output parity_error;
605 44 unneback
reg [word_size/chunk_size-1:0] error_flag;
606 43 unneback
integer i,j;
607
always @ (data or parity)
608
for (i=0;i<word_size/chunk_size;i=i+1) begin
609
    error_flag[i] = parity[i] ^ parity_type;
610
    for (j=0;j<chunk_size;j=j+1) begin
611 46 unneback
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
612 43 unneback
    end
613
end
614
assign parity_error = |error_flag;
615
endmodule
616 18 unneback
//////////////////////////////////////////////////////////////////////
617
////                                                              ////
618 44 unneback
////  IO functions                                                ////
619
////                                                              ////
620
////  Description                                                 ////
621
////  IO functions such as IOB flip-flops                         ////
622
////                                                              ////
623
////                                                              ////
624
////  To Do:                                                      ////
625
////   -                                                          ////
626
////                                                              ////
627
////  Author(s):                                                  ////
628
////      - Michael Unneback, unneback@opencores.org              ////
629
////        ORSoC AB                                              ////
630
////                                                              ////
631
//////////////////////////////////////////////////////////////////////
632
////                                                              ////
633
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
634
////                                                              ////
635
//// This source file may be used and distributed without         ////
636
//// restriction provided that this copyright statement is not    ////
637
//// removed from the file and that any derivative work contains  ////
638
//// the original copyright notice and the associated disclaimer. ////
639
////                                                              ////
640
//// This source file is free software; you can redistribute it   ////
641
//// and/or modify it under the terms of the GNU Lesser General   ////
642
//// Public License as published by the Free Software Foundation; ////
643
//// either version 2.1 of the License, or (at your option) any   ////
644
//// later version.                                               ////
645
////                                                              ////
646
//// This source is distributed in the hope that it will be       ////
647
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
648
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
649
//// PURPOSE.  See the GNU Lesser General Public License for more ////
650
//// details.                                                     ////
651
////                                                              ////
652
//// You should have received a copy of the GNU Lesser General    ////
653
//// Public License along with this source; if not, download it   ////
654
//// from http://www.opencores.org/lgpl.shtml                     ////
655
////                                                              ////
656
//////////////////////////////////////////////////////////////////////
657 45 unneback
`timescale 1ns/1ns
658 44 unneback
module vl_o_dff (d_i, o_pad, clk, rst);
659
parameter width = 1;
660 45 unneback
parameter reset_value = {width{1'b0}};
661
input  [width-1:0]  d_i;
662 44 unneback
output [width-1:0] o_pad;
663
input clk, rst;
664
wire [width-1:0] d_i_int /*synthesis syn_keep = 1*/;
665 45 unneback
reg  [width-1:0] o_pad_int;
666 44 unneback
assign d_i_int = d_i;
667
genvar i;
668 45 unneback
generate
669 136 unneback
for (i=0;i<width;i=i+1) begin : dffs
670 44 unneback
    always @ (posedge clk or posedge rst)
671
    if (rst)
672 45 unneback
        o_pad_int[i] <= reset_value[i];
673 44 unneback
    else
674 45 unneback
        o_pad_int[i] <= d_i_int[i];
675
    assign #1 o_pad[i] = o_pad_int[i];
676 44 unneback
end
677
endgenerate
678
endmodule
679 45 unneback
`timescale 1ns/1ns
680 44 unneback
module vl_io_dff_oe ( d_i, d_o, oe, io_pad, clk, rst);
681
parameter width = 1;
682
input  [width-1:0] d_o;
683
output reg [width-1:0] d_i;
684
input oe;
685
inout [width-1:0] io_pad;
686
input clk, rst;
687
wire [width-1:0] oe_d /*synthesis syn_keep = 1*/;
688
reg [width-1:0] oe_q;
689
reg [width-1:0] d_o_q;
690
assign oe_d = {width{oe}};
691
genvar i;
692
generate
693 136 unneback
for (i=0;i<width;i=i+1) begin : dffs
694 44 unneback
    always @ (posedge clk or posedge rst)
695
    if (rst)
696
        oe_q[i] <= 1'b0;
697
    else
698
        oe_q[i] <= oe_d[i];
699
    always @ (posedge clk or posedge rst)
700
    if (rst)
701
        d_o_q[i] <= 1'b0;
702
    else
703
        d_o_q[i] <= d_o[i];
704
    always @ (posedge clk or posedge rst)
705
    if (rst)
706
        d_i[i] <= 1'b0;
707
    else
708
        d_i[i] <= io_pad[i];
709 45 unneback
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
710 44 unneback
end
711
endgenerate
712
endmodule
713 136 unneback
module vl_o_ddr (d_h_i, d_l_i, o_pad, clk, rst);
714
parameter width = 1;
715
input  [width-1:0] d_h_i, d_l_i;
716
output [width-1:0] o_pad;
717
input clk, rst;
718
reg [width-1:0] ff1;
719
reg [width-1:0] ff2;
720
genvar i;
721
generate
722
for (i=0;i<width;i=i+1) begin : ddr
723
    always @ (posedge clk or posedge rst)
724
    if (rst)
725
        ff1[i] <= 1'b0;
726
    else
727
        ff1[i] <= d_h_i[i];
728
    always @ (posedge clk or posedge rst)
729
    if (rst)
730
        ff2[i] <= 1'b0;
731
    else
732
        ff2[i] <= d_l_i[i];
733
    assign o_pad = (clk) ? ff1 : ff2;
734
end
735
endgenerate
736
endmodule
737
module vl_o_clk ( clk_o_pad, clk, rst);
738
input clk, rst;
739
output clk_o_pad;
740
vl_o_ddr o_ddr0( .d_h_i(1'b1), .d_l_i(1'b0), .o_pad(clk_o_pad), .clk(clk), .rst(rst));
741
endmodule
742 44 unneback
//////////////////////////////////////////////////////////////////////
743
////                                                              ////
744 6 unneback
////  Versatile counter                                           ////
745
////                                                              ////
746
////  Description                                                 ////
747
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
748
////  counter                                                     ////
749
////                                                              ////
750
////  To Do:                                                      ////
751
////   - add LFSR with more taps                                  ////
752
////                                                              ////
753
////  Author(s):                                                  ////
754
////      - Michael Unneback, unneback@opencores.org              ////
755
////        ORSoC AB                                              ////
756
////                                                              ////
757
//////////////////////////////////////////////////////////////////////
758
////                                                              ////
759
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
760
////                                                              ////
761
//// This source file may be used and distributed without         ////
762
//// restriction provided that this copyright statement is not    ////
763
//// removed from the file and that any derivative work contains  ////
764
//// the original copyright notice and the associated disclaimer. ////
765
////                                                              ////
766
//// This source file is free software; you can redistribute it   ////
767
//// and/or modify it under the terms of the GNU Lesser General   ////
768
//// Public License as published by the Free Software Foundation; ////
769
//// either version 2.1 of the License, or (at your option) any   ////
770
//// later version.                                               ////
771
////                                                              ////
772
//// This source is distributed in the hope that it will be       ////
773
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
774
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
775
//// PURPOSE.  See the GNU Lesser General Public License for more ////
776
//// details.                                                     ////
777
////                                                              ////
778
//// You should have received a copy of the GNU Lesser General    ////
779
//// Public License along with this source; if not, download it   ////
780
//// from http://www.opencores.org/lgpl.shtml                     ////
781
////                                                              ////
782
//////////////////////////////////////////////////////////////////////
783
// binary counter
784 40 unneback
module vl_cnt_bin_ce (
785
 cke, q, rst, clk);
786 22 unneback
   parameter length = 4;
787 6 unneback
   input cke;
788
   output [length:1] q;
789
   input rst;
790
   input clk;
791
   parameter clear_value = 0;
792
   parameter set_value = 1;
793
   parameter wrap_value = 0;
794
   parameter level1_value = 15;
795
   reg  [length:1] qi;
796
   wire [length:1] q_next;
797
   assign q_next = qi + {{length-1{1'b0}},1'b1};
798
   always @ (posedge clk or posedge rst)
799
     if (rst)
800
       qi <= {length{1'b0}};
801
     else
802
     if (cke)
803
       qi <= q_next;
804
   assign q = qi;
805
endmodule
806
//////////////////////////////////////////////////////////////////////
807
////                                                              ////
808
////  Versatile counter                                           ////
809
////                                                              ////
810
////  Description                                                 ////
811
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
812
////  counter                                                     ////
813
////                                                              ////
814
////  To Do:                                                      ////
815
////   - add LFSR with more taps                                  ////
816
////                                                              ////
817
////  Author(s):                                                  ////
818
////      - Michael Unneback, unneback@opencores.org              ////
819
////        ORSoC AB                                              ////
820
////                                                              ////
821
//////////////////////////////////////////////////////////////////////
822
////                                                              ////
823
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
824
////                                                              ////
825
//// This source file may be used and distributed without         ////
826
//// restriction provided that this copyright statement is not    ////
827
//// removed from the file and that any derivative work contains  ////
828
//// the original copyright notice and the associated disclaimer. ////
829
////                                                              ////
830
//// This source file is free software; you can redistribute it   ////
831
//// and/or modify it under the terms of the GNU Lesser General   ////
832
//// Public License as published by the Free Software Foundation; ////
833
//// either version 2.1 of the License, or (at your option) any   ////
834
//// later version.                                               ////
835
////                                                              ////
836
//// This source is distributed in the hope that it will be       ////
837
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
838
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
839
//// PURPOSE.  See the GNU Lesser General Public License for more ////
840
//// details.                                                     ////
841
////                                                              ////
842
//// You should have received a copy of the GNU Lesser General    ////
843
//// Public License along with this source; if not, download it   ////
844
//// from http://www.opencores.org/lgpl.shtml                     ////
845
////                                                              ////
846
//////////////////////////////////////////////////////////////////////
847
// binary counter
848 40 unneback
module vl_cnt_bin_ce_rew_zq_l1 (
849
 cke, rew, zq, level1, rst, clk);
850 6 unneback
   parameter length = 4;
851
   input cke;
852
   input rew;
853 25 unneback
   output reg zq;
854
   output reg level1;
855
   input rst;
856
   input clk;
857
   parameter clear_value = 0;
858
   parameter set_value = 1;
859
   parameter wrap_value = 1;
860
   parameter level1_value = 15;
861 29 unneback
   wire clear;
862 30 unneback
   assign clear = 1'b0;
863 25 unneback
   reg  [length:1] qi;
864
   wire  [length:1] q_next, q_next_fw, q_next_rew;
865
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
866
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
867
   assign q_next = rew ? q_next_rew : q_next_fw;
868
   always @ (posedge clk or posedge rst)
869
     if (rst)
870
       qi <= {length{1'b0}};
871
     else
872
     if (cke)
873
       qi <= q_next;
874
   always @ (posedge clk or posedge rst)
875
     if (rst)
876
       zq <= 1'b1;
877
     else
878
     if (cke)
879
       zq <= q_next == {length{1'b0}};
880
    always @ (posedge clk or posedge rst)
881
    if (rst)
882
        level1 <= 1'b0;
883
    else
884
    if (cke)
885 29 unneback
    if (clear)
886
        level1 <= 1'b0;
887
    else if (q_next == level1_value)
888 25 unneback
        level1 <= 1'b1;
889
    else if (qi == level1_value & rew)
890
        level1 <= 1'b0;
891
endmodule
892
//////////////////////////////////////////////////////////////////////
893
////                                                              ////
894
////  Versatile counter                                           ////
895
////                                                              ////
896
////  Description                                                 ////
897
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
898
////  counter                                                     ////
899
////                                                              ////
900
////  To Do:                                                      ////
901
////   - add LFSR with more taps                                  ////
902
////                                                              ////
903
////  Author(s):                                                  ////
904
////      - Michael Unneback, unneback@opencores.org              ////
905
////        ORSoC AB                                              ////
906
////                                                              ////
907
//////////////////////////////////////////////////////////////////////
908
////                                                              ////
909
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
910
////                                                              ////
911
//// This source file may be used and distributed without         ////
912
//// restriction provided that this copyright statement is not    ////
913
//// removed from the file and that any derivative work contains  ////
914
//// the original copyright notice and the associated disclaimer. ////
915
////                                                              ////
916
//// This source file is free software; you can redistribute it   ////
917
//// and/or modify it under the terms of the GNU Lesser General   ////
918
//// Public License as published by the Free Software Foundation; ////
919
//// either version 2.1 of the License, or (at your option) any   ////
920
//// later version.                                               ////
921
////                                                              ////
922
//// This source is distributed in the hope that it will be       ////
923
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
924
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
925
//// PURPOSE.  See the GNU Lesser General Public License for more ////
926
//// details.                                                     ////
927
////                                                              ////
928
//// You should have received a copy of the GNU Lesser General    ////
929
//// Public License along with this source; if not, download it   ////
930
//// from http://www.opencores.org/lgpl.shtml                     ////
931
////                                                              ////
932
//////////////////////////////////////////////////////////////////////
933
// binary counter
934 40 unneback
module vl_cnt_bin_ce_rew_q_zq_l1 (
935
 cke, rew, q, zq, level1, rst, clk);
936 25 unneback
   parameter length = 4;
937
   input cke;
938
   input rew;
939
   output [length:1] q;
940
   output reg zq;
941
   output reg level1;
942
   input rst;
943
   input clk;
944
   parameter clear_value = 0;
945
   parameter set_value = 1;
946
   parameter wrap_value = 1;
947
   parameter level1_value = 15;
948 29 unneback
   wire clear;
949 30 unneback
   assign clear = 1'b0;
950 25 unneback
   reg  [length:1] qi;
951
   wire  [length:1] q_next, q_next_fw, q_next_rew;
952
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
953
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
954
   assign q_next = rew ? q_next_rew : q_next_fw;
955
   always @ (posedge clk or posedge rst)
956
     if (rst)
957
       qi <= {length{1'b0}};
958
     else
959
     if (cke)
960
       qi <= q_next;
961
   assign q = qi;
962
   always @ (posedge clk or posedge rst)
963
     if (rst)
964
       zq <= 1'b1;
965
     else
966
     if (cke)
967
       zq <= q_next == {length{1'b0}};
968
    always @ (posedge clk or posedge rst)
969
    if (rst)
970
        level1 <= 1'b0;
971
    else
972
    if (cke)
973 29 unneback
    if (clear)
974
        level1 <= 1'b0;
975
    else if (q_next == level1_value)
976 25 unneback
        level1 <= 1'b1;
977
    else if (qi == level1_value & rew)
978
        level1 <= 1'b0;
979
endmodule
980
//////////////////////////////////////////////////////////////////////
981
////                                                              ////
982
////  Versatile counter                                           ////
983
////                                                              ////
984
////  Description                                                 ////
985
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
986
////  counter                                                     ////
987
////                                                              ////
988
////  To Do:                                                      ////
989
////   - add LFSR with more taps                                  ////
990
////                                                              ////
991
////  Author(s):                                                  ////
992
////      - Michael Unneback, unneback@opencores.org              ////
993
////        ORSoC AB                                              ////
994
////                                                              ////
995
//////////////////////////////////////////////////////////////////////
996
////                                                              ////
997
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
998
////                                                              ////
999
//// This source file may be used and distributed without         ////
1000
//// restriction provided that this copyright statement is not    ////
1001
//// removed from the file and that any derivative work contains  ////
1002
//// the original copyright notice and the associated disclaimer. ////
1003
////                                                              ////
1004
//// This source file is free software; you can redistribute it   ////
1005
//// and/or modify it under the terms of the GNU Lesser General   ////
1006
//// Public License as published by the Free Software Foundation; ////
1007
//// either version 2.1 of the License, or (at your option) any   ////
1008
//// later version.                                               ////
1009
////                                                              ////
1010
//// This source is distributed in the hope that it will be       ////
1011
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1012
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1013
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1014
//// details.                                                     ////
1015
////                                                              ////
1016
//// You should have received a copy of the GNU Lesser General    ////
1017
//// Public License along with this source; if not, download it   ////
1018
//// from http://www.opencores.org/lgpl.shtml                     ////
1019
////                                                              ////
1020
//////////////////////////////////////////////////////////////////////
1021 75 unneback
// LFSR counter
1022 136 unneback
module vl_cnt_lfsr_zq (
1023
 zq, rst, clk);
1024
   parameter length = 4;
1025
   output reg zq;
1026
   input rst;
1027
   input clk;
1028
   parameter clear_value = 0;
1029
   parameter set_value = 1;
1030
   parameter wrap_value = 8;
1031
   parameter level1_value = 15;
1032
   reg  [length:1] qi;
1033
   reg lfsr_fb;
1034
   wire [length:1] q_next;
1035
   reg [32:1] polynom;
1036
   integer i;
1037
   always @ (qi)
1038
   begin
1039
        case (length)
1040
         2: polynom = 32'b11;                               // 0x3
1041
         3: polynom = 32'b110;                              // 0x6
1042
         4: polynom = 32'b1100;                             // 0xC
1043
         5: polynom = 32'b10100;                            // 0x14
1044
         6: polynom = 32'b110000;                           // 0x30
1045
         7: polynom = 32'b1100000;                          // 0x60
1046
         8: polynom = 32'b10111000;                         // 0xb8
1047
         9: polynom = 32'b100010000;                        // 0x110
1048
        10: polynom = 32'b1001000000;                       // 0x240
1049
        11: polynom = 32'b10100000000;                      // 0x500
1050
        12: polynom = 32'b100000101001;                     // 0x829
1051
        13: polynom = 32'b1000000001100;                    // 0x100C
1052
        14: polynom = 32'b10000000010101;                   // 0x2015
1053
        15: polynom = 32'b110000000000000;                  // 0x6000
1054
        16: polynom = 32'b1101000000001000;                 // 0xD008
1055
        17: polynom = 32'b10010000000000000;                // 0x12000
1056
        18: polynom = 32'b100000010000000000;               // 0x20400
1057
        19: polynom = 32'b1000000000000100011;              // 0x40023
1058
        20: polynom = 32'b10010000000000000000;             // 0x90000
1059
        21: polynom = 32'b101000000000000000000;            // 0x140000
1060
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1061
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1062
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1063
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1064
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1065
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1066
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1067
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1068
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1069
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1070
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1071
        default: polynom = 32'b0;
1072
        endcase
1073
        lfsr_fb = qi[length];
1074
        for (i=length-1; i>=1; i=i-1) begin
1075
            if (polynom[i])
1076
                lfsr_fb = lfsr_fb  ~^ qi[i];
1077
        end
1078
    end
1079
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1080
   always @ (posedge clk or posedge rst)
1081
     if (rst)
1082
       qi <= {length{1'b0}};
1083
     else
1084
       qi <= q_next;
1085
   always @ (posedge clk or posedge rst)
1086
     if (rst)
1087
       zq <= 1'b1;
1088
     else
1089
       zq <= q_next == {length{1'b0}};
1090
endmodule
1091
//////////////////////////////////////////////////////////////////////
1092
////                                                              ////
1093
////  Versatile counter                                           ////
1094
////                                                              ////
1095
////  Description                                                 ////
1096
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1097
////  counter                                                     ////
1098
////                                                              ////
1099
////  To Do:                                                      ////
1100
////   - add LFSR with more taps                                  ////
1101
////                                                              ////
1102
////  Author(s):                                                  ////
1103
////      - Michael Unneback, unneback@opencores.org              ////
1104
////        ORSoC AB                                              ////
1105
////                                                              ////
1106
//////////////////////////////////////////////////////////////////////
1107
////                                                              ////
1108
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1109
////                                                              ////
1110
//// This source file may be used and distributed without         ////
1111
//// restriction provided that this copyright statement is not    ////
1112
//// removed from the file and that any derivative work contains  ////
1113
//// the original copyright notice and the associated disclaimer. ////
1114
////                                                              ////
1115
//// This source file is free software; you can redistribute it   ////
1116
//// and/or modify it under the terms of the GNU Lesser General   ////
1117
//// Public License as published by the Free Software Foundation; ////
1118
//// either version 2.1 of the License, or (at your option) any   ////
1119
//// later version.                                               ////
1120
////                                                              ////
1121
//// This source is distributed in the hope that it will be       ////
1122
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1123
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1124
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1125
//// details.                                                     ////
1126
////                                                              ////
1127
//// You should have received a copy of the GNU Lesser General    ////
1128
//// Public License along with this source; if not, download it   ////
1129
//// from http://www.opencores.org/lgpl.shtml                     ////
1130
////                                                              ////
1131
//////////////////////////////////////////////////////////////////////
1132
// LFSR counter
1133 75 unneback
module vl_cnt_lfsr_ce (
1134
 cke, zq, rst, clk);
1135
   parameter length = 4;
1136
   input cke;
1137
   output reg zq;
1138
   input rst;
1139
   input clk;
1140
   parameter clear_value = 0;
1141
   parameter set_value = 1;
1142
   parameter wrap_value = 0;
1143
   parameter level1_value = 15;
1144
   reg  [length:1] qi;
1145
   reg lfsr_fb;
1146
   wire [length:1] q_next;
1147
   reg [32:1] polynom;
1148
   integer i;
1149
   always @ (qi)
1150
   begin
1151
        case (length)
1152
         2: polynom = 32'b11;                               // 0x3
1153
         3: polynom = 32'b110;                              // 0x6
1154
         4: polynom = 32'b1100;                             // 0xC
1155
         5: polynom = 32'b10100;                            // 0x14
1156
         6: polynom = 32'b110000;                           // 0x30
1157
         7: polynom = 32'b1100000;                          // 0x60
1158
         8: polynom = 32'b10111000;                         // 0xb8
1159
         9: polynom = 32'b100010000;                        // 0x110
1160
        10: polynom = 32'b1001000000;                       // 0x240
1161
        11: polynom = 32'b10100000000;                      // 0x500
1162
        12: polynom = 32'b100000101001;                     // 0x829
1163
        13: polynom = 32'b1000000001100;                    // 0x100C
1164
        14: polynom = 32'b10000000010101;                   // 0x2015
1165
        15: polynom = 32'b110000000000000;                  // 0x6000
1166
        16: polynom = 32'b1101000000001000;                 // 0xD008
1167
        17: polynom = 32'b10010000000000000;                // 0x12000
1168
        18: polynom = 32'b100000010000000000;               // 0x20400
1169
        19: polynom = 32'b1000000000000100011;              // 0x40023
1170
        20: polynom = 32'b10010000000000000000;             // 0x90000
1171
        21: polynom = 32'b101000000000000000000;            // 0x140000
1172
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1173
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1174
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1175
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1176
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1177
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1178
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1179
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1180
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1181
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1182
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1183
        default: polynom = 32'b0;
1184
        endcase
1185
        lfsr_fb = qi[length];
1186
        for (i=length-1; i>=1; i=i-1) begin
1187
            if (polynom[i])
1188
                lfsr_fb = lfsr_fb  ~^ qi[i];
1189
        end
1190
    end
1191
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1192
   always @ (posedge clk or posedge rst)
1193
     if (rst)
1194
       qi <= {length{1'b0}};
1195
     else
1196
     if (cke)
1197
       qi <= q_next;
1198
   always @ (posedge clk or posedge rst)
1199
     if (rst)
1200
       zq <= 1'b1;
1201
     else
1202
     if (cke)
1203
       zq <= q_next == {length{1'b0}};
1204
endmodule
1205
//////////////////////////////////////////////////////////////////////
1206
////                                                              ////
1207
////  Versatile counter                                           ////
1208
////                                                              ////
1209
////  Description                                                 ////
1210
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1211
////  counter                                                     ////
1212
////                                                              ////
1213
////  To Do:                                                      ////
1214
////   - add LFSR with more taps                                  ////
1215
////                                                              ////
1216
////  Author(s):                                                  ////
1217
////      - Michael Unneback, unneback@opencores.org              ////
1218
////        ORSoC AB                                              ////
1219
////                                                              ////
1220
//////////////////////////////////////////////////////////////////////
1221
////                                                              ////
1222
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1223
////                                                              ////
1224
//// This source file may be used and distributed without         ////
1225
//// restriction provided that this copyright statement is not    ////
1226
//// removed from the file and that any derivative work contains  ////
1227
//// the original copyright notice and the associated disclaimer. ////
1228
////                                                              ////
1229
//// This source file is free software; you can redistribute it   ////
1230
//// and/or modify it under the terms of the GNU Lesser General   ////
1231
//// Public License as published by the Free Software Foundation; ////
1232
//// either version 2.1 of the License, or (at your option) any   ////
1233
//// later version.                                               ////
1234
////                                                              ////
1235
//// This source is distributed in the hope that it will be       ////
1236
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1237
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1238
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1239
//// details.                                                     ////
1240
////                                                              ////
1241
//// You should have received a copy of the GNU Lesser General    ////
1242
//// Public License along with this source; if not, download it   ////
1243
//// from http://www.opencores.org/lgpl.shtml                     ////
1244
////                                                              ////
1245
//////////////////////////////////////////////////////////////////////
1246 6 unneback
// GRAY counter
1247 40 unneback
module vl_cnt_gray_ce_bin (
1248
 cke, q, q_bin, rst, clk);
1249 6 unneback
   parameter length = 4;
1250
   input cke;
1251
   output reg [length:1] q;
1252
   output [length:1] q_bin;
1253
   input rst;
1254
   input clk;
1255
   parameter clear_value = 0;
1256
   parameter set_value = 1;
1257
   parameter wrap_value = 8;
1258
   parameter level1_value = 15;
1259
   reg  [length:1] qi;
1260
   wire [length:1] q_next;
1261
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1262
   always @ (posedge clk or posedge rst)
1263
     if (rst)
1264
       qi <= {length{1'b0}};
1265
     else
1266
     if (cke)
1267
       qi <= q_next;
1268
   always @ (posedge clk or posedge rst)
1269
     if (rst)
1270
       q <= {length{1'b0}};
1271
     else
1272
       if (cke)
1273
         q <= (q_next>>1) ^ q_next;
1274
   assign q_bin = qi;
1275
endmodule
1276
//////////////////////////////////////////////////////////////////////
1277
////                                                              ////
1278
////  Versatile library, counters                                 ////
1279
////                                                              ////
1280
////  Description                                                 ////
1281
////  counters                                                    ////
1282
////                                                              ////
1283
////                                                              ////
1284
////  To Do:                                                      ////
1285
////   - add more counters                                        ////
1286
////                                                              ////
1287
////  Author(s):                                                  ////
1288
////      - Michael Unneback, unneback@opencores.org              ////
1289
////        ORSoC AB                                              ////
1290
////                                                              ////
1291
//////////////////////////////////////////////////////////////////////
1292
////                                                              ////
1293
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1294
////                                                              ////
1295
//// This source file may be used and distributed without         ////
1296
//// restriction provided that this copyright statement is not    ////
1297
//// removed from the file and that any derivative work contains  ////
1298
//// the original copyright notice and the associated disclaimer. ////
1299
////                                                              ////
1300
//// This source file is free software; you can redistribute it   ////
1301
//// and/or modify it under the terms of the GNU Lesser General   ////
1302
//// Public License as published by the Free Software Foundation; ////
1303
//// either version 2.1 of the License, or (at your option) any   ////
1304
//// later version.                                               ////
1305
////                                                              ////
1306
//// This source is distributed in the hope that it will be       ////
1307
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1308
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1309
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1310
//// details.                                                     ////
1311
////                                                              ////
1312
//// You should have received a copy of the GNU Lesser General    ////
1313
//// Public License along with this source; if not, download it   ////
1314
//// from http://www.opencores.org/lgpl.shtml                     ////
1315
////                                                              ////
1316
//////////////////////////////////////////////////////////////////////
1317 18 unneback
module vl_cnt_shreg_wrap ( q, rst, clk);
1318 6 unneback
   parameter length = 4;
1319
   output reg [0:length-1] q;
1320
   input rst;
1321
   input clk;
1322
    always @ (posedge clk or posedge rst)
1323
    if (rst)
1324
        q <= {1'b1,{length-1{1'b0}}};
1325
    else
1326
        q <= {q[length-1],q[0:length-2]};
1327
endmodule
1328 18 unneback
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
1329 6 unneback
   parameter length = 4;
1330
   input cke;
1331
   output reg [0:length-1] q;
1332
   input rst;
1333
   input clk;
1334
    always @ (posedge clk or posedge rst)
1335
    if (rst)
1336
        q <= {1'b1,{length-1{1'b0}}};
1337
    else
1338
        if (cke)
1339
            q <= {q[length-1],q[0:length-2]};
1340
endmodule
1341 105 unneback
module vl_cnt_shreg_clear ( clear, q, rst, clk);
1342
   parameter length = 4;
1343
   input clear;
1344
   output reg [0:length-1] q;
1345
   input rst;
1346
   input clk;
1347
    always @ (posedge clk or posedge rst)
1348
    if (rst)
1349
        q <= {1'b1,{length-1{1'b0}}};
1350
    else
1351
        if (clear)
1352
            q <= {1'b1,{length-1{1'b0}}};
1353
        else
1354
            q <= q >> 1;
1355
endmodule
1356 18 unneback
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
1357 6 unneback
   parameter length = 4;
1358
   input cke, clear;
1359
   output reg [0:length-1] q;
1360
   input rst;
1361
   input clk;
1362
    always @ (posedge clk or posedge rst)
1363
    if (rst)
1364
        q <= {1'b1,{length-1{1'b0}}};
1365
    else
1366
        if (cke)
1367
            if (clear)
1368
                q <= {1'b1,{length-1{1'b0}}};
1369
            else
1370
                q <= q >> 1;
1371
endmodule
1372 18 unneback
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
1373 6 unneback
   parameter length = 4;
1374
   input cke, clear;
1375
   output reg [0:length-1] q;
1376
   input rst;
1377
   input clk;
1378
    always @ (posedge clk or posedge rst)
1379
    if (rst)
1380
        q <= {1'b1,{length-1{1'b0}}};
1381
    else
1382
        if (cke)
1383
            if (clear)
1384
                q <= {1'b1,{length-1{1'b0}}};
1385
            else
1386
            q <= {q[length-1],q[0:length-2]};
1387
endmodule
1388
//////////////////////////////////////////////////////////////////////
1389
////                                                              ////
1390
////  Versatile library, memories                                 ////
1391
////                                                              ////
1392
////  Description                                                 ////
1393
////  memories                                                    ////
1394
////                                                              ////
1395
////                                                              ////
1396
////  To Do:                                                      ////
1397
////   - add more memory types                                    ////
1398
////                                                              ////
1399
////  Author(s):                                                  ////
1400
////      - Michael Unneback, unneback@opencores.org              ////
1401
////        ORSoC AB                                              ////
1402
////                                                              ////
1403
//////////////////////////////////////////////////////////////////////
1404
////                                                              ////
1405
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1406
////                                                              ////
1407
//// This source file may be used and distributed without         ////
1408
//// restriction provided that this copyright statement is not    ////
1409
//// removed from the file and that any derivative work contains  ////
1410
//// the original copyright notice and the associated disclaimer. ////
1411
////                                                              ////
1412
//// This source file is free software; you can redistribute it   ////
1413
//// and/or modify it under the terms of the GNU Lesser General   ////
1414
//// Public License as published by the Free Software Foundation; ////
1415
//// either version 2.1 of the License, or (at your option) any   ////
1416
//// later version.                                               ////
1417
////                                                              ////
1418
//// This source is distributed in the hope that it will be       ////
1419
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1420
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1421
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1422
//// details.                                                     ////
1423
////                                                              ////
1424
//// You should have received a copy of the GNU Lesser General    ////
1425
//// Public License along with this source; if not, download it   ////
1426
//// from http://www.opencores.org/lgpl.shtml                     ////
1427
////                                                              ////
1428
//////////////////////////////////////////////////////////////////////
1429
/// ROM
1430 7 unneback
module vl_rom_init ( adr, q, clk);
1431
   parameter data_width = 32;
1432
   parameter addr_width = 8;
1433 75 unneback
   parameter mem_size = 1<<addr_width;
1434 7 unneback
   input [(addr_width-1):0]       adr;
1435
   output reg [(data_width-1):0] q;
1436
   input                         clk;
1437 75 unneback
   reg [data_width-1:0] rom [mem_size-1:0];
1438 7 unneback
   parameter memory_file = "vl_rom.vmem";
1439
   initial
1440
     begin
1441
        $readmemh(memory_file, rom);
1442
     end
1443
   always @ (posedge clk)
1444
     q <= rom[adr];
1445
endmodule
1446 6 unneback
// Single port RAM
1447
module vl_ram ( d, adr, we, q, clk);
1448
   parameter data_width = 32;
1449
   parameter addr_width = 8;
1450 75 unneback
   parameter mem_size = 1<<addr_width;
1451 100 unneback
   parameter debug = 0;
1452 6 unneback
   input [(data_width-1):0]      d;
1453
   input [(addr_width-1):0]       adr;
1454
   input                         we;
1455 7 unneback
   output reg [(data_width-1):0] q;
1456 6 unneback
   input                         clk;
1457 98 unneback
   reg [data_width-1:0] ram [mem_size-1:0];
1458 100 unneback
    parameter memory_init = 0;
1459
    parameter memory_file = "vl_ram.vmem";
1460
    generate
1461
    if (memory_init == 1) begin : init_mem
1462
        initial
1463
            $readmemh(memory_file, ram);
1464
   end else if (memory_init == 2) begin : init_zero
1465
        integer k;
1466
        initial
1467
            for (k = 0; k < mem_size; k = k + 1)
1468
                ram[k] = 0;
1469 7 unneback
   end
1470
   endgenerate
1471 100 unneback
    generate
1472
    if (debug==1) begin : debug_we
1473
        always @ (posedge clk)
1474
        if (we)
1475
            $display ("Value %h written at address %h : time %t", d, adr, $time);
1476
    end
1477
    endgenerate
1478 6 unneback
   always @ (posedge clk)
1479
   begin
1480
   if (we)
1481
     ram[adr] <= d;
1482
   q <= ram[adr];
1483
   end
1484
endmodule
1485 91 unneback
module vl_ram_be ( d, adr, be, we, q, clk);
1486 7 unneback
   parameter data_width = 32;
1487 72 unneback
   parameter addr_width = 6;
1488 75 unneback
   parameter mem_size = 1<<addr_width;
1489 7 unneback
   input [(data_width-1):0]      d;
1490
   input [(addr_width-1):0]       adr;
1491 73 unneback
   input [(data_width/8)-1:0]    be;
1492 7 unneback
   input                         we;
1493
   output reg [(data_width-1):0] q;
1494
   input                         clk;
1495 65 unneback
`ifdef SYSTEMVERILOG
1496 95 unneback
    // use a multi-dimensional packed array
1497
    //t o model individual bytes within the word
1498
    logic [data_width/8-1:0][7:0] ram [0:mem_size-1];// # words = 1 << address width
1499 65 unneback
`else
1500 85 unneback
    reg [data_width-1:0] ram [mem_size-1:0];
1501
    wire [data_width/8-1:0] cke;
1502 65 unneback
`endif
1503 100 unneback
    parameter memory_init = 0;
1504
    parameter memory_file = "vl_ram.vmem";
1505
    generate
1506
    if (memory_init == 1) begin : init_mem
1507
        initial
1508
            $readmemh(memory_file, ram);
1509
    end else if (memory_init == 2) begin : init_zero
1510
        integer k;
1511
        initial
1512
            for (k = 0; k < mem_size; k = k + 1)
1513
                ram[k] = 0;
1514
    end
1515 7 unneback
   endgenerate
1516 60 unneback
`ifdef SYSTEMVERILOG
1517
always_ff@(posedge clk)
1518
begin
1519 95 unneback
    if(we) begin
1520 86 unneback
        if(be[3]) ram[adr][3] <= d[31:24];
1521
        if(be[2]) ram[adr][2] <= d[23:16];
1522
        if(be[1]) ram[adr][1] <= d[15:8];
1523
        if(be[0]) ram[adr][0] <= d[7:0];
1524 60 unneback
    end
1525 90 unneback
        q <= ram[adr];
1526 60 unneback
end
1527
`else
1528 85 unneback
assign cke = {data_width/8{we}} & be;
1529 7 unneback
   genvar i;
1530 85 unneback
   generate for (i=0;i<data_width/8;i=i+1) begin : be_ram
1531 7 unneback
      always @ (posedge clk)
1532 85 unneback
      if (cke[i])
1533 7 unneback
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
1534
   end
1535
   endgenerate
1536
   always @ (posedge clk)
1537
      q <= ram[adr];
1538 60 unneback
`endif
1539 93 unneback
`ifdef verilator
1540 85 unneback
   // Function to access RAM (for use by Verilator).
1541
   function [31:0] get_mem;
1542
      // verilator public
1543 90 unneback
      input [addr_width-1:0]             addr;
1544 85 unneback
      get_mem = ram[addr];
1545
   endfunction // get_mem
1546
   // Function to write RAM (for use by Verilator).
1547
   function set_mem;
1548
      // verilator public
1549 90 unneback
      input [addr_width-1:0]             addr;
1550
      input [data_width-1:0]             data;
1551 85 unneback
      ram[addr] = data;
1552
   endfunction // set_mem
1553 93 unneback
`endif
1554 7 unneback
endmodule
1555
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1556 6 unneback
   parameter data_width = 32;
1557
   parameter addr_width = 8;
1558 75 unneback
   parameter mem_size = 1<<addr_width;
1559 6 unneback
   input [(data_width-1):0]      d_a;
1560
   input [(addr_width-1):0]       adr_a;
1561
   input [(addr_width-1):0]       adr_b;
1562
   input                         we_a;
1563 118 unneback
   output reg [(data_width-1):0]          q_b;
1564 6 unneback
   input                         clk_a, clk_b;
1565 119 unneback
   reg [data_width-1:0] ram [0:mem_size-1] /*synthesis syn_ramstyle = "no_rw_check"*/;
1566 100 unneback
    parameter memory_init = 0;
1567
    parameter memory_file = "vl_ram.vmem";
1568
    parameter debug = 0;
1569
    generate
1570
    if (memory_init == 1) begin : init_mem
1571
        initial
1572
            $readmemh(memory_file, ram);
1573
    end else if (memory_init == 2) begin : init_zero
1574
        integer k;
1575
        initial
1576
            for (k = 0; k < mem_size; k = k + 1)
1577
                ram[k] = 0;
1578
    end
1579 7 unneback
   endgenerate
1580 100 unneback
    generate
1581
    if (debug==1) begin : debug_we
1582
        always @ (posedge clk_a)
1583
        if (we_a)
1584
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
1585
    end
1586
    endgenerate
1587 6 unneback
   always @ (posedge clk_a)
1588
   if (we_a)
1589
     ram[adr_a] <= d_a;
1590
   always @ (posedge clk_b)
1591 118 unneback
      q_b = ram[adr_b];
1592 6 unneback
endmodule
1593 7 unneback
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1594 6 unneback
   parameter data_width = 32;
1595
   parameter addr_width = 8;
1596 75 unneback
   parameter mem_size = 1<<addr_width;
1597 6 unneback
   input [(data_width-1):0]      d_a;
1598
   input [(addr_width-1):0]       adr_a;
1599
   input [(addr_width-1):0]       adr_b;
1600
   input                         we_a;
1601
   output [(data_width-1):0]      q_b;
1602
   output reg [(data_width-1):0] q_a;
1603
   input                         clk_a, clk_b;
1604
   reg [(data_width-1):0]         q_b;
1605 119 unneback
   reg [data_width-1:0] ram [0:mem_size-1] /*synthesis syn_ramstyle = "no_rw_check"*/;
1606 100 unneback
    parameter memory_init = 0;
1607
    parameter memory_file = "vl_ram.vmem";
1608
    parameter debug = 0;
1609
    generate
1610
    if (memory_init == 1) begin : init_mem
1611
        initial
1612
            $readmemh(memory_file, ram);
1613
    end else if (memory_init == 2) begin : init_zero
1614
        integer k;
1615
        initial
1616
            for (k = 0; k < mem_size; k = k + 1)
1617
                ram[k] = 0;
1618
    end
1619 7 unneback
   endgenerate
1620 100 unneback
    generate
1621
    if (debug==1) begin : debug_we
1622
        always @ (posedge clk_a)
1623
        if (we_a)
1624
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
1625
    end
1626
    endgenerate
1627 6 unneback
   always @ (posedge clk_a)
1628
     begin
1629
        q_a <= ram[adr_a];
1630
        if (we_a)
1631
             ram[adr_a] <= d_a;
1632
     end
1633
   always @ (posedge clk_b)
1634
          q_b <= ram[adr_b];
1635
endmodule
1636 100 unneback
module vl_dpram_1r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, adr_b, we_b, clk_b );
1637
   parameter data_width = 32;
1638
   parameter addr_width = 8;
1639
   parameter mem_size = 1<<addr_width;
1640
   input [(data_width-1):0]      d_a;
1641
   input [(addr_width-1):0]       adr_a;
1642
   input [(addr_width-1):0]       adr_b;
1643
   input                         we_a;
1644
   input [(data_width-1):0]       d_b;
1645
   output reg [(data_width-1):0] q_a;
1646
   input                         we_b;
1647
   input                         clk_a, clk_b;
1648
   reg [(data_width-1):0]         q_b;
1649 119 unneback
   reg [data_width-1:0] ram [0:mem_size-1] /*synthesis syn_ramstyle = "no_rw_check"*/;
1650 100 unneback
    parameter memory_init = 0;
1651
    parameter memory_file = "vl_ram.vmem";
1652
    parameter debug = 0;
1653
    generate
1654
    if (memory_init == 1) begin : init_mem
1655
        initial
1656
            $readmemh(memory_file, ram);
1657
    end else if (memory_init == 2) begin : init_zero
1658
        integer k;
1659
        initial
1660
            for (k = 0; k < mem_size; k = k + 1)
1661
                ram[k] = 0;
1662
    end
1663
   endgenerate
1664
    generate
1665
    if (debug==1) begin : debug_we
1666
        always @ (posedge clk_a)
1667
        if (we_a)
1668
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
1669
        always @ (posedge clk_b)
1670
        if (we_b)
1671
            $display ("Debug: Value %h written at address %h : time %t", d_b, adr_b, $time);
1672
    end
1673
    endgenerate
1674
   always @ (posedge clk_a)
1675
     begin
1676
        q_a <= ram[adr_a];
1677
        if (we_a)
1678
             ram[adr_a] <= d_a;
1679
     end
1680
   always @ (posedge clk_b)
1681
     begin
1682
        if (we_b)
1683
          ram[adr_b] <= d_b;
1684
     end
1685
endmodule
1686 7 unneback
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
1687 6 unneback
   parameter data_width = 32;
1688
   parameter addr_width = 8;
1689 75 unneback
   parameter mem_size = 1<<addr_width;
1690 6 unneback
   input [(data_width-1):0]      d_a;
1691
   input [(addr_width-1):0]       adr_a;
1692
   input [(addr_width-1):0]       adr_b;
1693
   input                         we_a;
1694
   output [(data_width-1):0]      q_b;
1695
   input [(data_width-1):0]       d_b;
1696
   output reg [(data_width-1):0] q_a;
1697
   input                         we_b;
1698
   input                         clk_a, clk_b;
1699
   reg [(data_width-1):0]         q_b;
1700 119 unneback
   reg [data_width-1:0] ram [0:mem_size-1] /*synthesis syn_ramstyle = "no_rw_check"*/;
1701 100 unneback
    parameter memory_init = 0;
1702
    parameter memory_file = "vl_ram.vmem";
1703
    parameter debug = 0;
1704
    generate
1705
    if (memory_init) begin : init_mem
1706
        initial
1707
            $readmemh(memory_file, ram);
1708
    end else if (memory_init == 2) begin : init_zero
1709
        integer k;
1710
        initial
1711
            for (k = 0; k < mem_size; k = k + 1)
1712
                ram[k] = 0;
1713
    end
1714 7 unneback
   endgenerate
1715 100 unneback
    generate
1716
    if (debug==1) begin : debug_we
1717
        always @ (posedge clk_a)
1718
        if (we_a)
1719
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
1720
        always @ (posedge clk_b)
1721
        if (we_b)
1722
            $display ("Debug: Value %h written at address %h : time %t", d_b, adr_b, $time);
1723
    end
1724
    endgenerate
1725 6 unneback
   always @ (posedge clk_a)
1726
     begin
1727
        q_a <= ram[adr_a];
1728
        if (we_a)
1729
             ram[adr_a] <= d_a;
1730
     end
1731
   always @ (posedge clk_b)
1732
     begin
1733
        q_b <= ram[adr_b];
1734
        if (we_b)
1735
          ram[adr_b] <= d_b;
1736
     end
1737
endmodule
1738 92 unneback
module vl_dpram_be_2r2w ( d_a, q_a, adr_a, be_a, we_a, clk_a, d_b, q_b, adr_b, be_b, we_b, clk_b );
1739 75 unneback
   parameter a_data_width = 32;
1740
   parameter a_addr_width = 8;
1741 95 unneback
   parameter b_data_width = 64; //a_data_width;
1742 124 unneback
   //localparam b_addr_width = a_data_width * a_addr_width / b_data_width;
1743
   localparam b_addr_width =
1744 125 unneback
        (a_data_width==b_data_width) ? a_addr_width :
1745
        (a_data_width==b_data_width*2) ? a_addr_width+1 :
1746
        (a_data_width==b_data_width*4) ? a_addr_width+2 :
1747
        (a_data_width==b_data_width*8) ? a_addr_width+3 :
1748
        (a_data_width==b_data_width*16) ? a_addr_width+4 :
1749
        (a_data_width==b_data_width*32) ? a_addr_width+5 :
1750
        (a_data_width==b_data_width/2) ? a_addr_width-1 :
1751
        (a_data_width==b_data_width/4) ? a_addr_width-2 :
1752
        (a_data_width==b_data_width/8) ? a_addr_width-3 :
1753
        (a_data_width==b_data_width/16) ? a_addr_width-4 :
1754
        (a_data_width==b_data_width/32) ? a_addr_width-5 : 0;
1755 95 unneback
   localparam ratio = (a_addr_width>b_addr_width) ? (a_addr_width/b_addr_width) : (b_addr_width/a_addr_width);
1756
   parameter mem_size = (a_addr_width>b_addr_width) ? (1<<b_addr_width) : (1<<a_addr_width);
1757 100 unneback
   parameter memory_init = 0;
1758 95 unneback
   parameter memory_file = "vl_ram.vmem";
1759 100 unneback
   parameter debug = 0;
1760 75 unneback
   input [(a_data_width-1):0]      d_a;
1761 91 unneback
   input [(a_addr_width-1):0]       adr_a;
1762
   input [(a_data_width/8-1):0]    be_a;
1763
   input                           we_a;
1764 75 unneback
   output reg [(a_data_width-1):0] q_a;
1765 91 unneback
   input [(b_data_width-1):0]       d_b;
1766
   input [(b_addr_width-1):0]       adr_b;
1767 92 unneback
   input [(b_data_width/8-1):0]    be_b;
1768
   input                           we_b;
1769
   output reg [(b_data_width-1):0]          q_b;
1770 91 unneback
   input                           clk_a, clk_b;
1771 100 unneback
    generate
1772
    if (debug==1) begin : debug_we
1773
        always @ (posedge clk_a)
1774
        if (we_a)
1775
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
1776
        always @ (posedge clk_b)
1777
        if (we_b)
1778
            $display ("Debug: Value %h written at address %h : time %t", d_b, adr_b, $time);
1779
    end
1780
    endgenerate
1781 91 unneback
`ifdef SYSTEMVERILOG
1782
// use a multi-dimensional packed array
1783
//to model individual bytes within the word
1784 75 unneback
generate
1785 91 unneback
if (a_data_width==32 & b_data_width==32) begin : dpram_3232
1786 98 unneback
    logic [0:3][7:0] ram [0:mem_size-1] /*synthesis syn_ramstyle = "no_rw_check"*/;
1787 95 unneback
    initial
1788 100 unneback
        if (memory_init==1)
1789 95 unneback
            $readmemh(memory_file, ram);
1790 100 unneback
    integer k;
1791
    initial
1792
        if (memory_init==2)
1793
            for (k = 0; k < mem_size; k = k + 1)
1794
                ram[k] = 0;
1795 91 unneback
    always_ff@(posedge clk_a)
1796
    begin
1797
        if(we_a) begin
1798 100 unneback
            if(be_a[3]) ram[adr_a][0] <= d_a[31:24];
1799
            if(be_a[2]) ram[adr_a][1] <= d_a[23:16];
1800
            if(be_a[1]) ram[adr_a][2] <= d_a[15:8];
1801
            if(be_a[0]) ram[adr_a][3] <= d_a[7:0];
1802 91 unneback
        end
1803
    end
1804 92 unneback
    always@(posedge clk_a)
1805
        q_a = ram[adr_a];
1806 91 unneback
    always_ff@(posedge clk_b)
1807 92 unneback
    begin
1808
        if(we_b) begin
1809 100 unneback
            if(be_b[3]) ram[adr_b][0] <= d_b[31:24];
1810
            if(be_b[2]) ram[adr_b][1] <= d_b[23:16];
1811
            if(be_b[1]) ram[adr_b][2] <= d_b[15:8];
1812
            if(be_b[0]) ram[adr_b][3] <= d_b[7:0];
1813 92 unneback
        end
1814
    end
1815
    always@(posedge clk_b)
1816
        q_b = ram[adr_b];
1817 75 unneback
end
1818
endgenerate
1819 95 unneback
generate
1820
if (a_data_width==64 & b_data_width==64) begin : dpram_6464
1821 98 unneback
    logic [0:7][7:0] ram [0:mem_size-1] /*synthesis syn_ramstyle = "no_rw_check"*/;
1822 95 unneback
    initial
1823 100 unneback
        if (memory_init==1)
1824 95 unneback
            $readmemh(memory_file, ram);
1825 100 unneback
    integer k;
1826
    initial
1827
        if (memory_init==2)
1828
            for (k = 0; k < mem_size; k = k + 1)
1829
                ram[k] = 0;
1830 95 unneback
    always_ff@(posedge clk_a)
1831
    begin
1832
        if(we_a) begin
1833
            if(be_a[7]) ram[adr_a][7] <= d_a[63:56];
1834
            if(be_a[6]) ram[adr_a][6] <= d_a[55:48];
1835
            if(be_a[5]) ram[adr_a][5] <= d_a[47:40];
1836
            if(be_a[4]) ram[adr_a][4] <= d_a[39:32];
1837
            if(be_a[3]) ram[adr_a][3] <= d_a[31:24];
1838
            if(be_a[2]) ram[adr_a][2] <= d_a[23:16];
1839
            if(be_a[1]) ram[adr_a][1] <= d_a[15:8];
1840
            if(be_a[0]) ram[adr_a][0] <= d_a[7:0];
1841
        end
1842
    end
1843
    always@(posedge clk_a)
1844
        q_a = ram[adr_a];
1845
    always_ff@(posedge clk_b)
1846
    begin
1847
        if(we_b) begin
1848
            if(be_b[7]) ram[adr_b][7] <= d_b[63:56];
1849
            if(be_b[6]) ram[adr_b][6] <= d_b[55:48];
1850
            if(be_b[5]) ram[adr_b][5] <= d_b[47:40];
1851
            if(be_b[4]) ram[adr_b][4] <= d_b[39:32];
1852
            if(be_b[3]) ram[adr_b][3] <= d_b[31:24];
1853
            if(be_b[2]) ram[adr_b][2] <= d_b[23:16];
1854
            if(be_b[1]) ram[adr_b][1] <= d_b[15:8];
1855
            if(be_b[0]) ram[adr_b][0] <= d_b[7:0];
1856
        end
1857
    end
1858
    always@(posedge clk_b)
1859
        q_b = ram[adr_b];
1860
end
1861
endgenerate
1862
generate
1863
if (a_data_width==32 & b_data_width==16) begin : dpram_3216
1864
logic [31:0] temp;
1865 128 unneback
vl_dpram_be_2r2w # (.a_data_width(32), .b_data_width(32), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file))
1866
dpram3232 (
1867 95 unneback
    .d_a(d_a),
1868
    .q_a(q_a),
1869
    .adr_a(adr_a),
1870
    .be_a(be_a),
1871
    .we_a(we_a),
1872
    .clk_a(clk_a),
1873
    .d_b({d_b,d_b}),
1874
    .q_b(temp),
1875 128 unneback
    .adr_b(adr_b[b_addr_width-1:1]),
1876 95 unneback
    .be_b({be_b,be_b} & {{2{adr_b[0]}},{2{!adr_b[0]}}}),
1877
    .we_b(we_b),
1878
    .clk_b(clk_b)
1879
);
1880 100 unneback
always @ (adr_b[0] or temp)
1881 95 unneback
    if (adr_b[0])
1882
        q_b = temp[31:16];
1883
    else
1884
        q_b = temp[15:0];
1885
end
1886
endgenerate
1887
generate
1888
if (a_data_width==32 & b_data_width==64) begin : dpram_3264
1889
logic [63:0] temp;
1890 128 unneback
vl_dpram_be_2r2w # (.a_data_width(32), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file))
1891 95 unneback
dpram6464 (
1892
    .d_a({d_a,d_a}),
1893
    .q_a(temp),
1894
    .adr_a(adr_a[a_addr_width-1:1]),
1895
    .be_a({be_a,be_a} & {{4{adr_a[0]}},{4{!adr_a[0]}}}),
1896
    .we_a(we_a),
1897
    .clk_a(clk_a),
1898
    .d_b(d_b),
1899
    .q_b(q_b),
1900
    .adr_b(adr_b),
1901
    .be_b(be_b),
1902
    .we_b(we_b),
1903
    .clk_b(clk_b)
1904
);
1905 100 unneback
always @ (adr_a[0] or temp)
1906 95 unneback
    if (adr_a[0])
1907
        q_a = temp[63:32];
1908
    else
1909
        q_a = temp[31:0];
1910
end
1911
endgenerate
1912 91 unneback
`else
1913 92 unneback
    // This modules requires SystemVerilog
1914 98 unneback
    // at this point anyway
1915 91 unneback
`endif
1916 75 unneback
endmodule
1917 6 unneback
// FIFO
1918 25 unneback
module vl_fifo_1r1w_fill_level_sync (
1919
    d, wr, fifo_full,
1920
    q, rd, fifo_empty,
1921
    fill_level,
1922
    clk, rst
1923
    );
1924
parameter data_width = 18;
1925
parameter addr_width = 4;
1926
// write side
1927
input  [data_width-1:0] d;
1928
input                   wr;
1929
output                  fifo_full;
1930
// read side
1931
output [data_width-1:0] q;
1932
input                   rd;
1933
output                  fifo_empty;
1934
// common
1935
output [addr_width:0]   fill_level;
1936
input rst, clk;
1937
wire [addr_width:1] wadr, radr;
1938
vl_cnt_bin_ce
1939
    # ( .length(addr_width))
1940
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
1941
vl_cnt_bin_ce
1942
    # (.length(addr_width))
1943
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
1944
vl_dpram_1r1w
1945
    # (.data_width(data_width), .addr_width(addr_width))
1946
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
1947 31 unneback
vl_cnt_bin_ce_rew_q_zq_l1
1948 27 unneback
    # (.length(addr_width+1), .level1_value(1<<addr_width))
1949 25 unneback
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
1950
endmodule
1951 27 unneback
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
1952
// RAM is supposed to be larger than the two FIFOs
1953
// LFSR counters used adr pointers
1954
module vl_fifo_2r2w_sync_simplex (
1955
    // a side
1956
    a_d, a_wr, a_fifo_full,
1957
    a_q, a_rd, a_fifo_empty,
1958
    a_fill_level,
1959
    // b side
1960
    b_d, b_wr, b_fifo_full,
1961
    b_q, b_rd, b_fifo_empty,
1962
    b_fill_level,
1963
    // common
1964
    clk, rst
1965
    );
1966
parameter data_width = 8;
1967
parameter addr_width = 5;
1968
parameter fifo_full_level = (1<<addr_width)-1;
1969
// a side
1970
input  [data_width-1:0] a_d;
1971
input                   a_wr;
1972
output                  a_fifo_full;
1973
output [data_width-1:0] a_q;
1974
input                   a_rd;
1975
output                  a_fifo_empty;
1976
output [addr_width-1:0] a_fill_level;
1977
// b side
1978
input  [data_width-1:0] b_d;
1979
input                   b_wr;
1980
output                  b_fifo_full;
1981
output [data_width-1:0] b_q;
1982
input                   b_rd;
1983
output                  b_fifo_empty;
1984
output [addr_width-1:0] b_fill_level;
1985
input                   clk;
1986
input                   rst;
1987
// adr_gen
1988
wire [addr_width:1] a_wadr, a_radr;
1989
wire [addr_width:1] b_wadr, b_radr;
1990
// dpram
1991
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
1992
vl_cnt_lfsr_ce
1993
    # ( .length(addr_width))
1994
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
1995
vl_cnt_lfsr_ce
1996
    # (.length(addr_width))
1997
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
1998
vl_cnt_lfsr_ce
1999
    # ( .length(addr_width))
2000
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
2001
vl_cnt_lfsr_ce
2002
    # (.length(addr_width))
2003
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
2004
// mux read or write adr to DPRAM
2005
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
2006
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
2007
vl_dpram_2r2w
2008
    # (.data_width(data_width), .addr_width(addr_width+1))
2009
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
2010
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
2011
vl_cnt_bin_ce_rew_zq_l1
2012 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
2013 27 unneback
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
2014
vl_cnt_bin_ce_rew_zq_l1
2015 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
2016 27 unneback
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
2017
endmodule
2018 6 unneback
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
2019 11 unneback
   parameter addr_width = 4;
2020
   parameter N = addr_width-1;
2021 6 unneback
   parameter Q1 = 2'b00;
2022
   parameter Q2 = 2'b01;
2023
   parameter Q3 = 2'b11;
2024
   parameter Q4 = 2'b10;
2025
   parameter going_empty = 1'b0;
2026
   parameter going_full  = 1'b1;
2027
   input [N:0]  wptr, rptr;
2028 14 unneback
   output       fifo_empty;
2029 6 unneback
   output       fifo_full;
2030
   input        wclk, rclk, rst;
2031
   wire direction;
2032
   reg  direction_set, direction_clr;
2033
   wire async_empty, async_full;
2034
   wire fifo_full2;
2035 14 unneback
   wire fifo_empty2;
2036 6 unneback
   // direction_set
2037
   always @ (wptr[N:N-1] or rptr[N:N-1])
2038
     case ({wptr[N:N-1],rptr[N:N-1]})
2039
       {Q1,Q2} : direction_set <= 1'b1;
2040
       {Q2,Q3} : direction_set <= 1'b1;
2041
       {Q3,Q4} : direction_set <= 1'b1;
2042
       {Q4,Q1} : direction_set <= 1'b1;
2043
       default : direction_set <= 1'b0;
2044
     endcase
2045
   // direction_clear
2046
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
2047
     if (rst)
2048
       direction_clr <= 1'b1;
2049
     else
2050
       case ({wptr[N:N-1],rptr[N:N-1]})
2051
         {Q2,Q1} : direction_clr <= 1'b1;
2052
         {Q3,Q2} : direction_clr <= 1'b1;
2053
         {Q4,Q3} : direction_clr <= 1'b1;
2054
         {Q1,Q4} : direction_clr <= 1'b1;
2055
         default : direction_clr <= 1'b0;
2056
       endcase
2057 18 unneback
    vl_dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
2058 6 unneback
   assign async_empty = (wptr == rptr) && (direction==going_empty);
2059
   assign async_full  = (wptr == rptr) && (direction==going_full);
2060 18 unneback
    vl_dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
2061
    vl_dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
2062 6 unneback
/*
2063
   always @ (posedge wclk or posedge rst or posedge async_full)
2064
     if (rst)
2065
       {fifo_full, fifo_full2} <= 2'b00;
2066
     else if (async_full)
2067
       {fifo_full, fifo_full2} <= 2'b11;
2068
     else
2069
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
2070
*/
2071 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
2072 6 unneback
     if (async_empty)
2073
       {fifo_empty, fifo_empty2} <= 2'b11;
2074
     else
2075 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
2076 18 unneback
    vl_dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
2077
    vl_dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
2078 27 unneback
endmodule // async_compb
2079 6 unneback
module vl_fifo_1r1w_async (
2080
    d, wr, fifo_full, wr_clk, wr_rst,
2081
    q, rd, fifo_empty, rd_clk, rd_rst
2082
    );
2083
parameter data_width = 18;
2084
parameter addr_width = 4;
2085
// write side
2086
input  [data_width-1:0] d;
2087
input                   wr;
2088
output                  fifo_full;
2089
input                   wr_clk;
2090
input                   wr_rst;
2091
// read side
2092
output [data_width-1:0] q;
2093
input                   rd;
2094
output                  fifo_empty;
2095
input                   rd_clk;
2096
input                   rd_rst;
2097
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
2098 18 unneback
vl_cnt_gray_ce_bin
2099 6 unneback
    # ( .length(addr_width))
2100
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
2101 18 unneback
vl_cnt_gray_ce_bin
2102 6 unneback
    # (.length(addr_width))
2103 23 unneback
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
2104 7 unneback
vl_dpram_1r1w
2105 6 unneback
    # (.data_width(data_width), .addr_width(addr_width))
2106
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
2107
vl_fifo_cmp_async
2108
    # (.addr_width(addr_width))
2109
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
2110
endmodule
2111 8 unneback
module vl_fifo_2r2w_async (
2112 6 unneback
    // a side
2113
    a_d, a_wr, a_fifo_full,
2114
    a_q, a_rd, a_fifo_empty,
2115
    a_clk, a_rst,
2116
    // b side
2117
    b_d, b_wr, b_fifo_full,
2118
    b_q, b_rd, b_fifo_empty,
2119
    b_clk, b_rst
2120
    );
2121
parameter data_width = 18;
2122
parameter addr_width = 4;
2123
// a side
2124
input  [data_width-1:0] a_d;
2125
input                   a_wr;
2126
output                  a_fifo_full;
2127
output [data_width-1:0] a_q;
2128
input                   a_rd;
2129
output                  a_fifo_empty;
2130
input                   a_clk;
2131
input                   a_rst;
2132
// b side
2133
input  [data_width-1:0] b_d;
2134
input                   b_wr;
2135
output                  b_fifo_full;
2136
output [data_width-1:0] b_q;
2137
input                   b_rd;
2138
output                  b_fifo_empty;
2139
input                   b_clk;
2140
input                   b_rst;
2141
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
2142
vl_fifo_1r1w_async_a (
2143
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
2144
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
2145
    );
2146
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
2147
vl_fifo_1r1w_async_b (
2148
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
2149
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
2150
    );
2151
endmodule
2152 8 unneback
module vl_fifo_2r2w_async_simplex (
2153 6 unneback
    // a side
2154
    a_d, a_wr, a_fifo_full,
2155
    a_q, a_rd, a_fifo_empty,
2156
    a_clk, a_rst,
2157
    // b side
2158
    b_d, b_wr, b_fifo_full,
2159
    b_q, b_rd, b_fifo_empty,
2160
    b_clk, b_rst
2161
    );
2162
parameter data_width = 18;
2163
parameter addr_width = 4;
2164
// a side
2165
input  [data_width-1:0] a_d;
2166
input                   a_wr;
2167
output                  a_fifo_full;
2168
output [data_width-1:0] a_q;
2169
input                   a_rd;
2170
output                  a_fifo_empty;
2171
input                   a_clk;
2172
input                   a_rst;
2173
// b side
2174
input  [data_width-1:0] b_d;
2175
input                   b_wr;
2176
output                  b_fifo_full;
2177
output [data_width-1:0] b_q;
2178
input                   b_rd;
2179
output                  b_fifo_empty;
2180
input                   b_clk;
2181
input                   b_rst;
2182
// adr_gen
2183
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
2184
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
2185
// dpram
2186
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
2187 18 unneback
vl_cnt_gray_ce_bin
2188 6 unneback
    # ( .length(addr_width))
2189
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
2190 18 unneback
vl_cnt_gray_ce_bin
2191 6 unneback
    # (.length(addr_width))
2192
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
2193 18 unneback
vl_cnt_gray_ce_bin
2194 6 unneback
    # ( .length(addr_width))
2195
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
2196 18 unneback
vl_cnt_gray_ce_bin
2197 6 unneback
    # (.length(addr_width))
2198
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
2199
// mux read or write adr to DPRAM
2200
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
2201
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
2202 11 unneback
vl_dpram_2r2w
2203 6 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
2204
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
2205
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
2206 11 unneback
vl_fifo_cmp_async
2207 6 unneback
    # (.addr_width(addr_width))
2208
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
2209 11 unneback
vl_fifo_cmp_async
2210 6 unneback
    # (.addr_width(addr_width))
2211
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
2212
endmodule
2213 48 unneback
module vl_reg_file (
2214
    a1, a2, a3, wd3, we3, rd1, rd2, clk
2215
);
2216
parameter data_width = 32;
2217
parameter addr_width = 5;
2218
input [addr_width-1:0] a1, a2, a3;
2219
input [data_width-1:0] wd3;
2220
input we3;
2221
output [data_width-1:0] rd1, rd2;
2222
input clk;
2223
reg [data_width-1:0] wd3_reg;
2224
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
2225
reg we3_reg;
2226
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
2227
reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
2228
always @ (posedge clk or posedge rst)
2229
if (rst)
2230
    {wd3_reg, a3_reg, we3_reg} <= {(data_width+addr_width+1){1'b0}};
2231
else
2232
    {wd3_reg, a3_reg, we3_reg} <= {wd3,a3,wd3};
2233
    always @ (negedge clk)
2234
    if (we3_reg)
2235
        ram1[a3_reg] <= wd3;
2236
    always @ (posedge clk)
2237
        a1_reg <= a1;
2238
    assign rd1 = ram1[a1_reg];
2239
    always @ (negedge clk)
2240
    if (we3_reg)
2241
        ram2[a3_reg] <= wd3;
2242
    always @ (posedge clk)
2243
        a2_reg <= a2;
2244
    assign rd2 = ram2[a2_reg];
2245
endmodule
2246 12 unneback
//////////////////////////////////////////////////////////////////////
2247
////                                                              ////
2248
////  Versatile library, wishbone stuff                           ////
2249
////                                                              ////
2250
////  Description                                                 ////
2251
////  Wishbone compliant modules                                  ////
2252
////                                                              ////
2253
////                                                              ////
2254
////  To Do:                                                      ////
2255
////   -                                                          ////
2256
////                                                              ////
2257
////  Author(s):                                                  ////
2258
////      - Michael Unneback, unneback@opencores.org              ////
2259
////        ORSoC AB                                              ////
2260
////                                                              ////
2261
//////////////////////////////////////////////////////////////////////
2262
////                                                              ////
2263
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2264
////                                                              ////
2265
//// This source file may be used and distributed without         ////
2266
//// restriction provided that this copyright statement is not    ////
2267
//// removed from the file and that any derivative work contains  ////
2268
//// the original copyright notice and the associated disclaimer. ////
2269
////                                                              ////
2270
//// This source file is free software; you can redistribute it   ////
2271
//// and/or modify it under the terms of the GNU Lesser General   ////
2272
//// Public License as published by the Free Software Foundation; ////
2273
//// either version 2.1 of the License, or (at your option) any   ////
2274
//// later version.                                               ////
2275
////                                                              ////
2276
//// This source is distributed in the hope that it will be       ////
2277
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2278
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2279
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2280
//// details.                                                     ////
2281
////                                                              ////
2282
//// You should have received a copy of the GNU Lesser General    ////
2283
//// Public License along with this source; if not, download it   ////
2284
//// from http://www.opencores.org/lgpl.shtml                     ////
2285
////                                                              ////
2286
//////////////////////////////////////////////////////////////////////
2287
`timescale 1ns/1ns
2288 85 unneback
module vl_wb_adr_inc ( cyc_i, stb_i, cti_i, bte_i, adr_i, we_i, ack_o, adr_o, clk, rst);
2289 83 unneback
parameter adr_width = 10;
2290
parameter max_burst_width = 4;
2291 85 unneback
input cyc_i, stb_i, we_i;
2292 83 unneback
input [2:0] cti_i;
2293
input [1:0] bte_i;
2294
input [adr_width-1:0] adr_i;
2295
output [adr_width-1:0] adr_o;
2296
output ack_o;
2297
input clk, rst;
2298
reg [adr_width-1:0] adr;
2299 90 unneback
wire [max_burst_width-1:0] to_adr;
2300 91 unneback
reg [max_burst_width-1:0] last_adr;
2301 92 unneback
reg last_cycle;
2302
localparam idle_or_eoc = 1'b0;
2303
localparam cyc_or_ws   = 1'b1;
2304 91 unneback
always @ (posedge clk or posedge rst)
2305
if (rst)
2306
    last_adr <= {max_burst_width{1'b0}};
2307
else
2308
    if (stb_i)
2309 92 unneback
        last_adr <=adr_o[max_burst_width-1:0];
2310 83 unneback
generate
2311
if (max_burst_width==0) begin : inst_0
2312 97 unneback
        reg ack_o;
2313
        assign adr_o = adr_i;
2314
        always @ (posedge clk or posedge rst)
2315
        if (rst)
2316
            ack_o <= 1'b0;
2317
        else
2318
            ack_o <= cyc_i & stb_i & !ack_o;
2319 83 unneback
end else begin
2320
    always @ (posedge clk or posedge rst)
2321
    if (rst)
2322 92 unneback
        last_cycle <= idle_or_eoc;
2323 83 unneback
    else
2324 92 unneback
        last_cycle <= (!cyc_i) ? idle_or_eoc : //idle
2325
                      (cyc_i & ack_o & (cti_i==3'b000 | cti_i==3'b111)) ? idle_or_eoc : // eoc
2326
                      (cyc_i & !stb_i) ? cyc_or_ws : //ws
2327
                      cyc_or_ws; // cyc
2328
    assign to_adr = (last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
2329 85 unneback
    assign adr_o[max_burst_width-1:0] = (we_i) ? adr_i[max_burst_width-1:0] :
2330 91 unneback
                                        (!stb_i) ? last_adr :
2331 92 unneback
                                        (last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] :
2332 85 unneback
                                        adr[max_burst_width-1:0];
2333 92 unneback
    assign ack_o = (last_cycle==cyc_or_ws) & stb_i;
2334 83 unneback
end
2335
endgenerate
2336
generate
2337
if (max_burst_width==2) begin : inst_2
2338
    always @ (posedge clk or posedge rst)
2339
    if (rst)
2340
        adr <= 2'h0;
2341
    else
2342
        if (cyc_i & stb_i)
2343
            adr[1:0] <= to_adr[1:0] + 2'd1;
2344
        else
2345
            adr <= to_adr[1:0];
2346
end
2347
endgenerate
2348
generate
2349
if (max_burst_width==3) begin : inst_3
2350
    always @ (posedge clk or posedge rst)
2351
    if (rst)
2352
        adr <= 3'h0;
2353
    else
2354
        if (cyc_i & stb_i)
2355
            case (bte_i)
2356
            2'b01: adr[2:0] <= {to_adr[2],to_adr[1:0] + 2'd1};
2357
            default: adr[3:0] <= to_adr[2:0] + 3'd1;
2358
            endcase
2359
        else
2360
            adr <= to_adr[2:0];
2361
end
2362
endgenerate
2363
generate
2364
if (max_burst_width==4) begin : inst_4
2365
    always @ (posedge clk or posedge rst)
2366
    if (rst)
2367
        adr <= 4'h0;
2368
    else
2369 91 unneback
        if (stb_i) // | (!stb_i & last_cycle!=ws)) // for !stb_i restart with adr_i +1, only inc once
2370 83 unneback
            case (bte_i)
2371
            2'b01: adr[3:0] <= {to_adr[3:2],to_adr[1:0] + 2'd1};
2372