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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Blame information for rev 139

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Line No. Rev Author Line
1 60 unneback
// default SYN_KEEP definition
2 98 unneback
    // ACTEL FPGA should not use logic to handle rw collision
3 136 unneback
///////////////////////////////////////
4
// dependencies
5
///////////////////////////////////////
6 97 unneback
// size to width
7 6 unneback
//////////////////////////////////////////////////////////////////////
8
////                                                              ////
9
////  Versatile library, clock and reset                          ////
10
////                                                              ////
11
////  Description                                                 ////
12
////  Logic related to clock and reset                            ////
13
////                                                              ////
14
////                                                              ////
15
////  To Do:                                                      ////
16
////   - add more different registers                             ////
17
////                                                              ////
18
////  Author(s):                                                  ////
19
////      - Michael Unneback, unneback@opencores.org              ////
20
////        ORSoC AB                                              ////
21
////                                                              ////
22
//////////////////////////////////////////////////////////////////////
23
////                                                              ////
24
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
25
////                                                              ////
26
//// This source file may be used and distributed without         ////
27
//// restriction provided that this copyright statement is not    ////
28
//// removed from the file and that any derivative work contains  ////
29
//// the original copyright notice and the associated disclaimer. ////
30
////                                                              ////
31
//// This source file is free software; you can redistribute it   ////
32
//// and/or modify it under the terms of the GNU Lesser General   ////
33
//// Public License as published by the Free Software Foundation; ////
34
//// either version 2.1 of the License, or (at your option) any   ////
35
//// later version.                                               ////
36
////                                                              ////
37
//// This source is distributed in the hope that it will be       ////
38
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
39
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
40
//// PURPOSE.  See the GNU Lesser General Public License for more ////
41
//// details.                                                     ////
42
////                                                              ////
43
//// You should have received a copy of the GNU Lesser General    ////
44
//// Public License along with this source; if not, download it   ////
45
//// from http://www.opencores.org/lgpl.shtml                     ////
46
////                                                              ////
47
//////////////////////////////////////////////////////////////////////
48 48 unneback
`timescale 1 ns/100 ps
49 6 unneback
// Global buffer
50
// usage:
51
// use to enable global buffers for high fan out signals such as clock and reset
52
// Version: 8.4 8.4.0.33
53
module gbuf(GL,CLK);
54
output GL;
55
input  CLK;
56
    wire GND;
57
    GND GND_1_net(.Y(GND));
58
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
59
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
60
endmodule
61
`timescale 1 ns/1 ns
62
module vl_gbuf ( i, o);
63
input i;
64
output o;
65
`ifdef SIM_GBUF
66
assign o=i;
67
`else
68
gbuf gbuf_i0 ( .CLK(i), .GL(o));
69
`endif
70
endmodule
71
 //ACTEL
72
// sync reset
73 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
74 6 unneback
// output active high global reset sync with two DFFs 
75
`timescale 1 ns/100 ps
76
module vl_sync_rst ( rst_n_i, rst_o, clk);
77
input rst_n_i, clk;
78
output rst_o;
79 18 unneback
reg [1:0] tmp;
80 6 unneback
always @ (posedge clk or negedge rst_n_i)
81
if (!rst_n_i)
82 17 unneback
        tmp <= 2'b11;
83 6 unneback
else
84 33 unneback
        tmp <= {1'b0,tmp[1]};
85 17 unneback
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
86 6 unneback
endmodule
87
// vl_pll
88 32 unneback
///////////////////////////////////////////////////////////////////////////////
89 17 unneback
`timescale 1 ps/1 ps
90 6 unneback
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
91
parameter index = 0;
92
parameter number_of_clk = 1;
93 17 unneback
parameter period_time_0 = 20000;
94
parameter period_time_1 = 20000;
95
parameter period_time_2 = 20000;
96
parameter lock_delay = 2000000;
97 6 unneback
input clk_i, rst_n_i;
98
output lock;
99
output reg [0:number_of_clk-1] clk_o;
100
output [0:number_of_clk-1] rst_o;
101
`ifdef SIM_PLL
102
always
103
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
104
generate if (number_of_clk > 1)
105
always
106
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
107
endgenerate
108
generate if (number_of_clk > 2)
109
always
110
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
111
endgenerate
112
genvar i;
113
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
114
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
115
end
116
endgenerate
117
assign #lock_delay lock = rst_n_i;
118
endmodule
119
`else
120
generate if (number_of_clk==1 & index==0) begin
121
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
122
end
123
endgenerate // index==0
124
generate if (number_of_clk==1 & index==1) begin
125
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
126
end
127
endgenerate // index==1
128
generate if (number_of_clk==1 & index==2) begin
129
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
130
end
131
endgenerate // index==2
132
generate if (number_of_clk==1 & index==3) begin
133
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
134
end
135
endgenerate // index==0
136
generate if (number_of_clk==2 & index==0) begin
137
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
138
end
139
endgenerate // index==0
140
generate if (number_of_clk==2 & index==1) begin
141
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
142
end
143
endgenerate // index==1
144
generate if (number_of_clk==2 & index==2) begin
145
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
146
end
147
endgenerate // index==2
148
generate if (number_of_clk==2 & index==3) begin
149
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
150
end
151
endgenerate // index==0
152
generate if (number_of_clk==3 & index==0) begin
153
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
154
end
155
endgenerate // index==0
156
generate if (number_of_clk==3 & index==1) begin
157
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
158
end
159
endgenerate // index==1
160
generate if (number_of_clk==3 & index==2) begin
161
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
162
end
163
endgenerate // index==2
164
generate if (number_of_clk==3 & index==3) begin
165
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
166
end
167
endgenerate // index==0
168
genvar i;
169
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
170 40 unneback
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
171 6 unneback
end
172
endgenerate
173
endmodule
174
`endif
175 32 unneback
///////////////////////////////////////////////////////////////////////////////
176 6 unneback
 //actel
177
//////////////////////////////////////////////////////////////////////
178
////                                                              ////
179
////  Versatile library, registers                                ////
180
////                                                              ////
181
////  Description                                                 ////
182
////  Different type of registers                                 ////
183
////                                                              ////
184
////                                                              ////
185
////  To Do:                                                      ////
186
////   - add more different registers                             ////
187
////                                                              ////
188
////  Author(s):                                                  ////
189
////      - Michael Unneback, unneback@opencores.org              ////
190
////        ORSoC AB                                              ////
191
////                                                              ////
192
//////////////////////////////////////////////////////////////////////
193
////                                                              ////
194
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
195
////                                                              ////
196
//// This source file may be used and distributed without         ////
197
//// restriction provided that this copyright statement is not    ////
198
//// removed from the file and that any derivative work contains  ////
199
//// the original copyright notice and the associated disclaimer. ////
200
////                                                              ////
201
//// This source file is free software; you can redistribute it   ////
202
//// and/or modify it under the terms of the GNU Lesser General   ////
203
//// Public License as published by the Free Software Foundation; ////
204
//// either version 2.1 of the License, or (at your option) any   ////
205
//// later version.                                               ////
206
////                                                              ////
207
//// This source is distributed in the hope that it will be       ////
208
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
209
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
210
//// PURPOSE.  See the GNU Lesser General Public License for more ////
211
//// details.                                                     ////
212
////                                                              ////
213
//// You should have received a copy of the GNU Lesser General    ////
214
//// Public License along with this source; if not, download it   ////
215
//// from http://www.opencores.org/lgpl.shtml                     ////
216
////                                                              ////
217
//////////////////////////////////////////////////////////////////////
218 18 unneback
module vl_dff ( d, q, clk, rst);
219 6 unneback
        parameter width = 1;
220 139 unneback
        parameter reset_value = {width{1'b0}};
221 6 unneback
        input [width-1:0] d;
222
        input clk, rst;
223
        output reg [width-1:0] q;
224
        always @ (posedge clk or posedge rst)
225
        if (rst)
226
                q <= reset_value;
227
        else
228
                q <= d;
229
endmodule
230 18 unneback
module vl_dff_array ( d, q, clk, rst);
231 6 unneback
        parameter width = 1;
232
        parameter depth = 2;
233
        parameter reset_value = 1'b0;
234
        input [width-1:0] d;
235
        input clk, rst;
236
        output [width-1:0] q;
237
        reg  [0:depth-1] q_tmp [width-1:0];
238
        integer i;
239
        always @ (posedge clk or posedge rst)
240
        if (rst) begin
241
            for (i=0;i<depth;i=i+1)
242
                q_tmp[i] <= {width{reset_value}};
243
        end else begin
244
            q_tmp[0] <= d;
245
            for (i=1;i<depth;i=i+1)
246
                q_tmp[i] <= q_tmp[i-1];
247
        end
248
    assign q = q_tmp[depth-1];
249
endmodule
250 18 unneback
module vl_dff_ce ( d, ce, q, clk, rst);
251 6 unneback
        parameter width = 1;
252 139 unneback
        parameter reset_value = {width{1'b0}};
253 6 unneback
        input [width-1:0] d;
254
        input ce, clk, rst;
255
        output reg [width-1:0] q;
256
        always @ (posedge clk or posedge rst)
257
        if (rst)
258
                q <= reset_value;
259
        else
260
                if (ce)
261
                        q <= d;
262
endmodule
263 18 unneback
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
264 8 unneback
        parameter width = 1;
265 139 unneback
        parameter reset_value = {width{1'b0}};
266 8 unneback
        input [width-1:0] d;
267 10 unneback
        input ce, clear, clk, rst;
268 8 unneback
        output reg [width-1:0] q;
269
        always @ (posedge clk or posedge rst)
270
        if (rst)
271
            q <= reset_value;
272
        else
273
            if (ce)
274
                if (clear)
275
                    q <= {width{1'b0}};
276
                else
277
                    q <= d;
278
endmodule
279 24 unneback
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
280
        parameter width = 1;
281 139 unneback
        parameter reset_value = {width{1'b0}};
282 24 unneback
        input [width-1:0] d;
283
        input ce, set, clk, rst;
284
        output reg [width-1:0] q;
285
        always @ (posedge clk or posedge rst)
286
        if (rst)
287
            q <= reset_value;
288
        else
289
            if (ce)
290
                if (set)
291
                    q <= {width{1'b1}};
292
                else
293
                    q <= d;
294
endmodule
295 29 unneback
module vl_spr ( sp, r, q, clk, rst);
296 64 unneback
        //parameter width = 1;
297
        parameter reset_value = 1'b0;
298 29 unneback
        input sp, r;
299
        output reg q;
300
        input clk, rst;
301
        always @ (posedge clk or posedge rst)
302
        if (rst)
303
            q <= reset_value;
304
        else
305
            if (sp)
306
                q <= 1'b1;
307
            else if (r)
308
                q <= 1'b0;
309
endmodule
310
module vl_srp ( s, rp, q, clk, rst);
311
        parameter width = 1;
312
        parameter reset_value = 0;
313
        input s, rp;
314
        output reg q;
315
        input clk, rst;
316
        always @ (posedge clk or posedge rst)
317
        if (rst)
318
            q <= reset_value;
319
        else
320
            if (rp)
321
                q <= 1'b0;
322
            else if (s)
323
                q <= 1'b1;
324
endmodule
325 18 unneback
module vl_dff_sr ( aclr, aset, clock, data, q);
326 6 unneback
    input         aclr;
327
    input         aset;
328
    input         clock;
329
    input         data;
330
    output reg    q;
331
   always @ (posedge clock or posedge aclr or posedge aset)
332
     if (aclr)
333
       q <= 1'b0;
334
     else if (aset)
335
       q <= 1'b1;
336
     else
337
       q <= data;
338
endmodule
339
// LATCH
340
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
341 40 unneback
module vl_latch ( d, le, q, clk);
342 6 unneback
input d, le;
343 48 unneback
input clk;
344
always @ (le or d)
345 60 unneback
if (le)
346 48 unneback
    d <= q;
347 6 unneback
endmodule
348 18 unneback
module vl_shreg ( d, q, clk, rst);
349 17 unneback
parameter depth = 10;
350
input d;
351
output q;
352
input clk, rst;
353
reg [1:depth] dffs;
354
always @ (posedge clk or posedge rst)
355
if (rst)
356
    dffs <= {depth{1'b0}};
357
else
358
    dffs <= {d,dffs[1:depth-1]};
359
assign q = dffs[depth];
360
endmodule
361 18 unneback
module vl_shreg_ce ( d, ce, q, clk, rst);
362 17 unneback
parameter depth = 10;
363
input d, ce;
364
output q;
365
input clk, rst;
366
reg [1:depth] dffs;
367
always @ (posedge clk or posedge rst)
368
if (rst)
369
    dffs <= {depth{1'b0}};
370
else
371
    if (ce)
372
        dffs <= {d,dffs[1:depth-1]};
373
assign q = dffs[depth];
374
endmodule
375 18 unneback
module vl_delay ( d, q, clk, rst);
376 15 unneback
parameter depth = 10;
377
input d;
378
output q;
379
input clk, rst;
380
reg [1:depth] dffs;
381
always @ (posedge clk or posedge rst)
382
if (rst)
383
    dffs <= {depth{1'b0}};
384
else
385
    dffs <= {d,dffs[1:depth-1]};
386
assign q = dffs[depth];
387
endmodule
388 18 unneback
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
389 17 unneback
parameter depth = 10;
390
input d;
391
output q, emptyflag;
392
input clk, rst;
393
reg [1:depth] dffs;
394
always @ (posedge clk or posedge rst)
395
if (rst)
396
    dffs <= {depth{1'b0}};
397
else
398
    dffs <= {d,dffs[1:depth-1]};
399
assign q = dffs[depth];
400
assign emptyflag = !(|dffs);
401
endmodule
402 98 unneback
module vl_pulse2toggle ( pl, q, clk, rst);
403 94 unneback
input pl;
404 98 unneback
output reg q;
405 94 unneback
input clk, rst;
406
always @ (posedge clk or posedge rst)
407
if (rst)
408
    q <= 1'b0;
409
else
410
    q <= pl ^ q;
411
endmodule
412 98 unneback
module vl_toggle2pulse (d, pl, clk, rst);
413 94 unneback
input d;
414
output pl;
415
input clk, rst;
416
reg dff;
417
always @ (posedge clk or posedge rst)
418
if (rst)
419
    dff <= 1'b0;
420
else
421
    dff <= d;
422 98 unneback
assign pl = d ^ dff;
423 94 unneback
endmodule
424
module vl_synchronizer (d, q, clk, rst);
425
input d;
426
output reg q;
427 116 unneback
input clk, rst;
428 94 unneback
reg dff;
429
always @ (posedge clk or posedge rst)
430
if (rst)
431 100 unneback
    {q,dff} <= 2'b00;
432 94 unneback
else
433 100 unneback
    {q,dff} <= {dff,d};
434 94 unneback
endmodule
435 97 unneback
module vl_cdc ( start_pl, take_it_pl, take_it_grant_pl, got_it_pl, clk_src, rst_src, clk_dst, rst_dst);
436 94 unneback
input start_pl;
437
output take_it_pl;
438
input take_it_grant_pl; // note: connect to take_it_pl to generate automatic ack
439
output got_it_pl;
440
input clk_src, rst_src;
441
input clk_dst, rst_dst;
442
wire take_it_tg, take_it_tg_sync;
443
wire got_it_tg, got_it_tg_sync;
444
// src -> dst
445
vl_pulse2toggle p2t0 (
446
    .pl(start_pl),
447
    .q(take_it_tg),
448
    .clk(clk_src),
449
    .rst(rst_src));
450
vl_synchronizer sync0 (
451
    .d(take_it_tg),
452
    .q(take_it_tg_sync),
453
    .clk(clk_dst),
454
    .rst(rst_dst));
455
vl_toggle2pulse t2p0 (
456 100 unneback
    .d(take_it_tg_sync),
457 94 unneback
    .pl(take_it_pl),
458
    .clk(clk_dst),
459
    .rst(rst_dst));
460
// dst -> src
461 98 unneback
vl_pulse2toggle p2t1 (
462 94 unneback
    .pl(take_it_grant_pl),
463
    .q(got_it_tg),
464
    .clk(clk_dst),
465
    .rst(rst_dst));
466
vl_synchronizer sync1 (
467
    .d(got_it_tg),
468
    .q(got_it_tg_sync),
469
    .clk(clk_src),
470
    .rst(rst_src));
471
vl_toggle2pulse t2p1 (
472 100 unneback
    .d(got_it_tg_sync),
473 94 unneback
    .pl(got_it_pl),
474
    .clk(clk_src),
475
    .rst(rst_src));
476
endmodule
477 6 unneback
//////////////////////////////////////////////////////////////////////
478
////                                                              ////
479 18 unneback
////  Logic functions                                             ////
480
////                                                              ////
481
////  Description                                                 ////
482
////  Logic functions such as multiplexers                        ////
483
////                                                              ////
484
////                                                              ////
485
////  To Do:                                                      ////
486
////   -                                                          ////
487
////                                                              ////
488
////  Author(s):                                                  ////
489
////      - Michael Unneback, unneback@opencores.org              ////
490
////        ORSoC AB                                              ////
491
////                                                              ////
492
//////////////////////////////////////////////////////////////////////
493
////                                                              ////
494
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
495
////                                                              ////
496
//// This source file may be used and distributed without         ////
497
//// restriction provided that this copyright statement is not    ////
498
//// removed from the file and that any derivative work contains  ////
499
//// the original copyright notice and the associated disclaimer. ////
500
////                                                              ////
501
//// This source file is free software; you can redistribute it   ////
502
//// and/or modify it under the terms of the GNU Lesser General   ////
503
//// Public License as published by the Free Software Foundation; ////
504
//// either version 2.1 of the License, or (at your option) any   ////
505
//// later version.                                               ////
506
////                                                              ////
507
//// This source is distributed in the hope that it will be       ////
508
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
509
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
510
//// PURPOSE.  See the GNU Lesser General Public License for more ////
511
//// details.                                                     ////
512
////                                                              ////
513
//// You should have received a copy of the GNU Lesser General    ////
514
//// Public License along with this source; if not, download it   ////
515
//// from http://www.opencores.org/lgpl.shtml                     ////
516
////                                                              ////
517
//////////////////////////////////////////////////////////////////////
518 36 unneback
module vl_mux_andor ( a, sel, dout);
519
parameter width = 32;
520
parameter nr_of_ports = 4;
521
input [nr_of_ports*width-1:0] a;
522
input [nr_of_ports-1:0] sel;
523
output reg [width-1:0] dout;
524 38 unneback
integer i,j;
525 36 unneback
always @ (a, sel)
526
begin
527
    dout = a[width-1:0] & {width{sel[0]}};
528 42 unneback
    for (i=1;i<nr_of_ports;i=i+1)
529
        for (j=0;j<width;j=j+1)
530
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
531 36 unneback
end
532
endmodule
533 34 unneback
module vl_mux2_andor ( a1, a0, sel, dout);
534
parameter width = 32;
535 35 unneback
localparam nr_of_ports = 2;
536 34 unneback
input [width-1:0] a1, a0;
537
input [nr_of_ports-1:0] sel;
538
output [width-1:0] dout;
539 36 unneback
vl_mux_andor
540 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
541 36 unneback
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
542 34 unneback
endmodule
543
module vl_mux3_andor ( a2, a1, a0, sel, dout);
544
parameter width = 32;
545 35 unneback
localparam nr_of_ports = 3;
546 34 unneback
input [width-1:0] a2, a1, a0;
547
input [nr_of_ports-1:0] sel;
548
output [width-1:0] dout;
549 36 unneback
vl_mux_andor
550 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
551 36 unneback
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
552 34 unneback
endmodule
553 18 unneback
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
554
parameter width = 32;
555 35 unneback
localparam nr_of_ports = 4;
556 18 unneback
input [width-1:0] a3, a2, a1, a0;
557
input [nr_of_ports-1:0] sel;
558 22 unneback
output [width-1:0] dout;
559 36 unneback
vl_mux_andor
560 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
561 36 unneback
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
562 18 unneback
endmodule
563
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
564
parameter width = 32;
565 35 unneback
localparam nr_of_ports = 5;
566 18 unneback
input [width-1:0] a4, a3, a2, a1, a0;
567
input [nr_of_ports-1:0] sel;
568 22 unneback
output [width-1:0] dout;
569 36 unneback
vl_mux_andor
570 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
571 36 unneback
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
572 18 unneback
endmodule
573
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
574
parameter width = 32;
575 35 unneback
localparam nr_of_ports = 6;
576 18 unneback
input [width-1:0] a5, a4, a3, a2, a1, a0;
577
input [nr_of_ports-1:0] sel;
578 22 unneback
output [width-1:0] dout;
579 36 unneback
vl_mux_andor
580 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
581 36 unneback
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
582 18 unneback
endmodule
583 43 unneback
module vl_parity_generate (data, parity);
584
parameter word_size = 32;
585
parameter chunk_size = 8;
586
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
587
input [word_size-1:0] data;
588
output reg [word_size/chunk_size-1:0] parity;
589
integer i,j;
590
always @ (data)
591
for (i=0;i<word_size/chunk_size;i=i+1) begin
592
    parity[i] = parity_type;
593
    for (j=0;j<chunk_size;j=j+1) begin
594 46 unneback
        parity[i] = data[i*chunk_size+j] ^ parity[i];
595 43 unneback
    end
596
end
597
endmodule
598
module vl_parity_check( data, parity, parity_error);
599
parameter word_size = 32;
600
parameter chunk_size = 8;
601
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
602
input [word_size-1:0] data;
603
input [word_size/chunk_size-1:0] parity;
604
output parity_error;
605 44 unneback
reg [word_size/chunk_size-1:0] error_flag;
606 43 unneback
integer i,j;
607
always @ (data or parity)
608
for (i=0;i<word_size/chunk_size;i=i+1) begin
609
    error_flag[i] = parity[i] ^ parity_type;
610
    for (j=0;j<chunk_size;j=j+1) begin
611 46 unneback
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
612 43 unneback
    end
613
end
614
assign parity_error = |error_flag;
615
endmodule
616 18 unneback
//////////////////////////////////////////////////////////////////////
617
////                                                              ////
618 44 unneback
////  IO functions                                                ////
619
////                                                              ////
620
////  Description                                                 ////
621
////  IO functions such as IOB flip-flops                         ////
622
////                                                              ////
623
////                                                              ////
624
////  To Do:                                                      ////
625
////   -                                                          ////
626
////                                                              ////
627
////  Author(s):                                                  ////
628
////      - Michael Unneback, unneback@opencores.org              ////
629
////        ORSoC AB                                              ////
630
////                                                              ////
631
//////////////////////////////////////////////////////////////////////
632
////                                                              ////
633
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
634
////                                                              ////
635
//// This source file may be used and distributed without         ////
636
//// restriction provided that this copyright statement is not    ////
637
//// removed from the file and that any derivative work contains  ////
638
//// the original copyright notice and the associated disclaimer. ////
639
////                                                              ////
640
//// This source file is free software; you can redistribute it   ////
641
//// and/or modify it under the terms of the GNU Lesser General   ////
642
//// Public License as published by the Free Software Foundation; ////
643
//// either version 2.1 of the License, or (at your option) any   ////
644
//// later version.                                               ////
645
////                                                              ////
646
//// This source is distributed in the hope that it will be       ////
647
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
648
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
649
//// PURPOSE.  See the GNU Lesser General Public License for more ////
650
//// details.                                                     ////
651
////                                                              ////
652
//// You should have received a copy of the GNU Lesser General    ////
653
//// Public License along with this source; if not, download it   ////
654
//// from http://www.opencores.org/lgpl.shtml                     ////
655
////                                                              ////
656
//////////////////////////////////////////////////////////////////////
657 45 unneback
`timescale 1ns/1ns
658 44 unneback
module vl_o_dff (d_i, o_pad, clk, rst);
659
parameter width = 1;
660 45 unneback
parameter reset_value = {width{1'b0}};
661
input  [width-1:0]  d_i;
662 44 unneback
output [width-1:0] o_pad;
663
input clk, rst;
664
wire [width-1:0] d_i_int /*synthesis syn_keep = 1*/;
665 45 unneback
reg  [width-1:0] o_pad_int;
666 44 unneback
assign d_i_int = d_i;
667
genvar i;
668 45 unneback
generate
669 136 unneback
for (i=0;i<width;i=i+1) begin : dffs
670 44 unneback
    always @ (posedge clk or posedge rst)
671
    if (rst)
672 45 unneback
        o_pad_int[i] <= reset_value[i];
673 44 unneback
    else
674 45 unneback
        o_pad_int[i] <= d_i_int[i];
675
    assign #1 o_pad[i] = o_pad_int[i];
676 44 unneback
end
677
endgenerate
678
endmodule
679 45 unneback
`timescale 1ns/1ns
680 44 unneback
module vl_io_dff_oe ( d_i, d_o, oe, io_pad, clk, rst);
681
parameter width = 1;
682
input  [width-1:0] d_o;
683
output reg [width-1:0] d_i;
684
input oe;
685
inout [width-1:0] io_pad;
686
input clk, rst;
687
wire [width-1:0] oe_d /*synthesis syn_keep = 1*/;
688
reg [width-1:0] oe_q;
689
reg [width-1:0] d_o_q;
690
assign oe_d = {width{oe}};
691
genvar i;
692
generate
693 136 unneback
for (i=0;i<width;i=i+1) begin : dffs
694 44 unneback
    always @ (posedge clk or posedge rst)
695
    if (rst)
696
        oe_q[i] <= 1'b0;
697
    else
698
        oe_q[i] <= oe_d[i];
699
    always @ (posedge clk or posedge rst)
700
    if (rst)
701
        d_o_q[i] <= 1'b0;
702
    else
703
        d_o_q[i] <= d_o[i];
704
    always @ (posedge clk or posedge rst)
705
    if (rst)
706
        d_i[i] <= 1'b0;
707
    else
708
        d_i[i] <= io_pad[i];
709 45 unneback
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
710 44 unneback
end
711
endgenerate
712
endmodule
713 136 unneback
module vl_o_ddr (d_h_i, d_l_i, o_pad, clk, rst);
714
parameter width = 1;
715
input  [width-1:0] d_h_i, d_l_i;
716
output [width-1:0] o_pad;
717
input clk, rst;
718
reg [width-1:0] ff1;
719
reg [width-1:0] ff2;
720
genvar i;
721
generate
722
for (i=0;i<width;i=i+1) begin : ddr
723
    always @ (posedge clk or posedge rst)
724
    if (rst)
725
        ff1[i] <= 1'b0;
726
    else
727
        ff1[i] <= d_h_i[i];
728
    always @ (posedge clk or posedge rst)
729
    if (rst)
730
        ff2[i] <= 1'b0;
731
    else
732
        ff2[i] <= d_l_i[i];
733
    assign o_pad = (clk) ? ff1 : ff2;
734
end
735
endgenerate
736
endmodule
737
module vl_o_clk ( clk_o_pad, clk, rst);
738
input clk, rst;
739
output clk_o_pad;
740
vl_o_ddr o_ddr0( .d_h_i(1'b1), .d_l_i(1'b0), .o_pad(clk_o_pad), .clk(clk), .rst(rst));
741
endmodule
742 44 unneback
//////////////////////////////////////////////////////////////////////
743
////                                                              ////
744 6 unneback
////  Versatile counter                                           ////
745
////                                                              ////
746
////  Description                                                 ////
747
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
748
////  counter                                                     ////
749
////                                                              ////
750
////  To Do:                                                      ////
751
////   - add LFSR with more taps                                  ////
752
////                                                              ////
753
////  Author(s):                                                  ////
754
////      - Michael Unneback, unneback@opencores.org              ////
755
////        ORSoC AB                                              ////
756
////                                                              ////
757
//////////////////////////////////////////////////////////////////////
758
////                                                              ////
759
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
760
////                                                              ////
761
//// This source file may be used and distributed without         ////
762
//// restriction provided that this copyright statement is not    ////
763
//// removed from the file and that any derivative work contains  ////
764
//// the original copyright notice and the associated disclaimer. ////
765
////                                                              ////
766
//// This source file is free software; you can redistribute it   ////
767
//// and/or modify it under the terms of the GNU Lesser General   ////
768
//// Public License as published by the Free Software Foundation; ////
769
//// either version 2.1 of the License, or (at your option) any   ////
770
//// later version.                                               ////
771
////                                                              ////
772
//// This source is distributed in the hope that it will be       ////
773
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
774
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
775
//// PURPOSE.  See the GNU Lesser General Public License for more ////
776
//// details.                                                     ////
777
////                                                              ////
778
//// You should have received a copy of the GNU Lesser General    ////
779
//// Public License along with this source; if not, download it   ////
780
//// from http://www.opencores.org/lgpl.shtml                     ////
781
////                                                              ////
782
//////////////////////////////////////////////////////////////////////
783
// binary counter
784 139 unneback
module vl_cnt_bin (
785
 q, rst, clk);
786
   parameter length = 4;
787
   output [length:1] q;
788
   input rst;
789
   input clk;
790
   parameter clear_value = 0;
791
   parameter set_value = 1;
792
   parameter wrap_value = 0;
793
   parameter level1_value = 15;
794
   reg  [length:1] qi;
795
   wire [length:1] q_next;
796
   assign q_next = qi + {{length-1{1'b0}},1'b1};
797
   always @ (posedge clk or posedge rst)
798
     if (rst)
799
       qi <= {length{1'b0}};
800
     else
801
       qi <= q_next;
802
   assign q = qi;
803
endmodule
804
//////////////////////////////////////////////////////////////////////
805
////                                                              ////
806
////  Versatile counter                                           ////
807
////                                                              ////
808
////  Description                                                 ////
809
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
810
////  counter                                                     ////
811
////                                                              ////
812
////  To Do:                                                      ////
813
////   - add LFSR with more taps                                  ////
814
////                                                              ////
815
////  Author(s):                                                  ////
816
////      - Michael Unneback, unneback@opencores.org              ////
817
////        ORSoC AB                                              ////
818
////                                                              ////
819
//////////////////////////////////////////////////////////////////////
820
////                                                              ////
821
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
822
////                                                              ////
823
//// This source file may be used and distributed without         ////
824
//// restriction provided that this copyright statement is not    ////
825
//// removed from the file and that any derivative work contains  ////
826
//// the original copyright notice and the associated disclaimer. ////
827
////                                                              ////
828
//// This source file is free software; you can redistribute it   ////
829
//// and/or modify it under the terms of the GNU Lesser General   ////
830
//// Public License as published by the Free Software Foundation; ////
831
//// either version 2.1 of the License, or (at your option) any   ////
832
//// later version.                                               ////
833
////                                                              ////
834
//// This source is distributed in the hope that it will be       ////
835
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
836
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
837
//// PURPOSE.  See the GNU Lesser General Public License for more ////
838
//// details.                                                     ////
839
////                                                              ////
840
//// You should have received a copy of the GNU Lesser General    ////
841
//// Public License along with this source; if not, download it   ////
842
//// from http://www.opencores.org/lgpl.shtml                     ////
843
////                                                              ////
844
//////////////////////////////////////////////////////////////////////
845
// binary counter
846
module vl_cnt_bin_clear (
847
 clear, q, rst, clk);
848
   parameter length = 4;
849
   input clear;
850
   output [length:1] q;
851
   input rst;
852
   input clk;
853
   parameter clear_value = 0;
854
   parameter set_value = 1;
855
   parameter wrap_value = 0;
856
   parameter level1_value = 15;
857
   reg  [length:1] qi;
858
   wire [length:1] q_next;
859
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
860
   always @ (posedge clk or posedge rst)
861
     if (rst)
862
       qi <= {length{1'b0}};
863
     else
864
       qi <= q_next;
865
   assign q = qi;
866
endmodule
867
//////////////////////////////////////////////////////////////////////
868
////                                                              ////
869
////  Versatile counter                                           ////
870
////                                                              ////
871
////  Description                                                 ////
872
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
873
////  counter                                                     ////
874
////                                                              ////
875
////  To Do:                                                      ////
876
////   - add LFSR with more taps                                  ////
877
////                                                              ////
878
////  Author(s):                                                  ////
879
////      - Michael Unneback, unneback@opencores.org              ////
880
////        ORSoC AB                                              ////
881
////                                                              ////
882
//////////////////////////////////////////////////////////////////////
883
////                                                              ////
884
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
885
////                                                              ////
886
//// This source file may be used and distributed without         ////
887
//// restriction provided that this copyright statement is not    ////
888
//// removed from the file and that any derivative work contains  ////
889
//// the original copyright notice and the associated disclaimer. ////
890
////                                                              ////
891
//// This source file is free software; you can redistribute it   ////
892
//// and/or modify it under the terms of the GNU Lesser General   ////
893
//// Public License as published by the Free Software Foundation; ////
894
//// either version 2.1 of the License, or (at your option) any   ////
895
//// later version.                                               ////
896
////                                                              ////
897
//// This source is distributed in the hope that it will be       ////
898
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
899
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
900
//// PURPOSE.  See the GNU Lesser General Public License for more ////
901
//// details.                                                     ////
902
////                                                              ////
903
//// You should have received a copy of the GNU Lesser General    ////
904
//// Public License along with this source; if not, download it   ////
905
//// from http://www.opencores.org/lgpl.shtml                     ////
906
////                                                              ////
907
//////////////////////////////////////////////////////////////////////
908
// binary counter
909 40 unneback
module vl_cnt_bin_ce (
910
 cke, q, rst, clk);
911 22 unneback
   parameter length = 4;
912 6 unneback
   input cke;
913
   output [length:1] q;
914
   input rst;
915
   input clk;
916
   parameter clear_value = 0;
917
   parameter set_value = 1;
918
   parameter wrap_value = 0;
919
   parameter level1_value = 15;
920
   reg  [length:1] qi;
921
   wire [length:1] q_next;
922
   assign q_next = qi + {{length-1{1'b0}},1'b1};
923
   always @ (posedge clk or posedge rst)
924
     if (rst)
925
       qi <= {length{1'b0}};
926
     else
927
     if (cke)
928
       qi <= q_next;
929
   assign q = qi;
930
endmodule
931
//////////////////////////////////////////////////////////////////////
932
////                                                              ////
933
////  Versatile counter                                           ////
934
////                                                              ////
935
////  Description                                                 ////
936
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
937
////  counter                                                     ////
938
////                                                              ////
939
////  To Do:                                                      ////
940
////   - add LFSR with more taps                                  ////
941
////                                                              ////
942
////  Author(s):                                                  ////
943
////      - Michael Unneback, unneback@opencores.org              ////
944
////        ORSoC AB                                              ////
945
////                                                              ////
946
//////////////////////////////////////////////////////////////////////
947
////                                                              ////
948
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
949
////                                                              ////
950
//// This source file may be used and distributed without         ////
951
//// restriction provided that this copyright statement is not    ////
952
//// removed from the file and that any derivative work contains  ////
953
//// the original copyright notice and the associated disclaimer. ////
954
////                                                              ////
955
//// This source file is free software; you can redistribute it   ////
956
//// and/or modify it under the terms of the GNU Lesser General   ////
957
//// Public License as published by the Free Software Foundation; ////
958
//// either version 2.1 of the License, or (at your option) any   ////
959
//// later version.                                               ////
960
////                                                              ////
961
//// This source is distributed in the hope that it will be       ////
962
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
963
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
964
//// PURPOSE.  See the GNU Lesser General Public License for more ////
965
//// details.                                                     ////
966
////                                                              ////
967
//// You should have received a copy of the GNU Lesser General    ////
968
//// Public License along with this source; if not, download it   ////
969
//// from http://www.opencores.org/lgpl.shtml                     ////
970
////                                                              ////
971
//////////////////////////////////////////////////////////////////////
972
// binary counter
973 139 unneback
module vl_cnt_bin_ce_clear (
974
 clear, cke, q, rst, clk);
975
   parameter length = 4;
976
   input clear;
977
   input cke;
978
   output [length:1] q;
979
   input rst;
980
   input clk;
981
   parameter clear_value = 0;
982
   parameter set_value = 1;
983
   parameter wrap_value = 0;
984
   parameter level1_value = 15;
985
   reg  [length:1] qi;
986
   wire [length:1] q_next;
987
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
988
   always @ (posedge clk or posedge rst)
989
     if (rst)
990
       qi <= {length{1'b0}};
991
     else
992
     if (cke)
993
       qi <= q_next;
994
   assign q = qi;
995
endmodule
996
//////////////////////////////////////////////////////////////////////
997
////                                                              ////
998
////  Versatile counter                                           ////
999
////                                                              ////
1000
////  Description                                                 ////
1001
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1002
////  counter                                                     ////
1003
////                                                              ////
1004
////  To Do:                                                      ////
1005
////   - add LFSR with more taps                                  ////
1006
////                                                              ////
1007
////  Author(s):                                                  ////
1008
////      - Michael Unneback, unneback@opencores.org              ////
1009
////        ORSoC AB                                              ////
1010
////                                                              ////
1011
//////////////////////////////////////////////////////////////////////
1012
////                                                              ////
1013
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1014
////                                                              ////
1015
//// This source file may be used and distributed without         ////
1016
//// restriction provided that this copyright statement is not    ////
1017
//// removed from the file and that any derivative work contains  ////
1018
//// the original copyright notice and the associated disclaimer. ////
1019
////                                                              ////
1020
//// This source file is free software; you can redistribute it   ////
1021
//// and/or modify it under the terms of the GNU Lesser General   ////
1022
//// Public License as published by the Free Software Foundation; ////
1023
//// either version 2.1 of the License, or (at your option) any   ////
1024
//// later version.                                               ////
1025
////                                                              ////
1026
//// This source is distributed in the hope that it will be       ////
1027
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1028
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1029
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1030
//// details.                                                     ////
1031
////                                                              ////
1032
//// You should have received a copy of the GNU Lesser General    ////
1033
//// Public License along with this source; if not, download it   ////
1034
//// from http://www.opencores.org/lgpl.shtml                     ////
1035
////                                                              ////
1036
//////////////////////////////////////////////////////////////////////
1037
// binary counter
1038
module vl_cnt_bin_ce_clear_l1_l2 (
1039
 clear, cke, q, level1, level2, rst, clk);
1040
   parameter length = 4;
1041
   input clear;
1042
   input cke;
1043
   output [length:1] q;
1044
   output reg level1;
1045
   output reg level2;
1046
   input rst;
1047
   input clk;
1048
   parameter clear_value = 0;
1049
   parameter set_value = 1;
1050
   parameter wrap_value = 15;
1051
   parameter level1_value = 8;
1052
   parameter level2_value = 15;
1053
   wire rew;
1054
   assign rew = 1'b0;
1055
   reg  [length:1] qi;
1056
   wire [length:1] q_next;
1057
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1058
   always @ (posedge clk or posedge rst)
1059
     if (rst)
1060
       qi <= {length{1'b0}};
1061
     else
1062
     if (cke)
1063
       qi <= q_next;
1064
   assign q = qi;
1065
    always @ (posedge clk or posedge rst)
1066
    if (rst)
1067
        level1 <= 1'b0;
1068
    else
1069
    if (cke)
1070
    if (clear)
1071
        level1 <= 1'b0;
1072
    else if (q_next == level1_value)
1073
        level1 <= 1'b1;
1074
    else if (qi == level1_value & rew)
1075
        level1 <= 1'b0;
1076
    always @ (posedge clk or posedge rst)
1077
    if (rst)
1078
        level2 <= 1'b0;
1079
    else
1080
    if (cke)
1081
    if (clear)
1082
        level2 <= 1'b0;
1083
    else if (q_next == level2_value)
1084
        level2 <= 1'b1;
1085
    else if (qi == level2_value & rew)
1086
        level2 <= 1'b0;
1087
endmodule
1088
//////////////////////////////////////////////////////////////////////
1089
////                                                              ////
1090
////  Versatile counter                                           ////
1091
////                                                              ////
1092
////  Description                                                 ////
1093
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1094
////  counter                                                     ////
1095
////                                                              ////
1096
////  To Do:                                                      ////
1097
////   - add LFSR with more taps                                  ////
1098
////                                                              ////
1099
////  Author(s):                                                  ////
1100
////      - Michael Unneback, unneback@opencores.org              ////
1101
////        ORSoC AB                                              ////
1102
////                                                              ////
1103
//////////////////////////////////////////////////////////////////////
1104
////                                                              ////
1105
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1106
////                                                              ////
1107
//// This source file may be used and distributed without         ////
1108
//// restriction provided that this copyright statement is not    ////
1109
//// removed from the file and that any derivative work contains  ////
1110
//// the original copyright notice and the associated disclaimer. ////
1111
////                                                              ////
1112
//// This source file is free software; you can redistribute it   ////
1113
//// and/or modify it under the terms of the GNU Lesser General   ////
1114
//// Public License as published by the Free Software Foundation; ////
1115
//// either version 2.1 of the License, or (at your option) any   ////
1116
//// later version.                                               ////
1117
////                                                              ////
1118
//// This source is distributed in the hope that it will be       ////
1119
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1120
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1121
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1122
//// details.                                                     ////
1123
////                                                              ////
1124
//// You should have received a copy of the GNU Lesser General    ////
1125
//// Public License along with this source; if not, download it   ////
1126
//// from http://www.opencores.org/lgpl.shtml                     ////
1127
////                                                              ////
1128
//////////////////////////////////////////////////////////////////////
1129
// binary counter
1130
module vl_cnt_bin_ce_clear_set_rew (
1131
 clear, set, cke, rew, q, rst, clk);
1132
   parameter length = 4;
1133
   input clear;
1134
   input set;
1135
   input cke;
1136
   input rew;
1137
   output [length:1] q;
1138
   input rst;
1139
   input clk;
1140
   parameter clear_value = 0;
1141
   parameter set_value = 1;
1142
   parameter wrap_value = 0;
1143
   parameter level1_value = 15;
1144
   reg  [length:1] qi;
1145
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1146
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
1147
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
1148
   assign q_next = rew ? q_next_rew : q_next_fw;
1149
   always @ (posedge clk or posedge rst)
1150
     if (rst)
1151
       qi <= {length{1'b0}};
1152
     else
1153
     if (cke)
1154
       qi <= q_next;
1155
   assign q = qi;
1156
endmodule
1157
//////////////////////////////////////////////////////////////////////
1158
////                                                              ////
1159
////  Versatile counter                                           ////
1160
////                                                              ////
1161
////  Description                                                 ////
1162
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1163
////  counter                                                     ////
1164
////                                                              ////
1165
////  To Do:                                                      ////
1166
////   - add LFSR with more taps                                  ////
1167
////                                                              ////
1168
////  Author(s):                                                  ////
1169
////      - Michael Unneback, unneback@opencores.org              ////
1170
////        ORSoC AB                                              ////
1171
////                                                              ////
1172
//////////////////////////////////////////////////////////////////////
1173
////                                                              ////
1174
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1175
////                                                              ////
1176
//// This source file may be used and distributed without         ////
1177
//// restriction provided that this copyright statement is not    ////
1178
//// removed from the file and that any derivative work contains  ////
1179
//// the original copyright notice and the associated disclaimer. ////
1180
////                                                              ////
1181
//// This source file is free software; you can redistribute it   ////
1182
//// and/or modify it under the terms of the GNU Lesser General   ////
1183
//// Public License as published by the Free Software Foundation; ////
1184
//// either version 2.1 of the License, or (at your option) any   ////
1185
//// later version.                                               ////
1186
////                                                              ////
1187
//// This source is distributed in the hope that it will be       ////
1188
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1189
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1190
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1191
//// details.                                                     ////
1192
////                                                              ////
1193
//// You should have received a copy of the GNU Lesser General    ////
1194
//// Public License along with this source; if not, download it   ////
1195
//// from http://www.opencores.org/lgpl.shtml                     ////
1196
////                                                              ////
1197
//////////////////////////////////////////////////////////////////////
1198
// binary counter
1199
module vl_cnt_bin_ce_rew_l1 (
1200
 cke, rew, level1, rst, clk);
1201
   parameter length = 4;
1202
   input cke;
1203
   input rew;
1204
   output reg level1;
1205
   input rst;
1206
   input clk;
1207
   parameter clear_value = 0;
1208
   parameter set_value = 1;
1209
   parameter wrap_value = 1;
1210
   parameter level1_value = 15;
1211
   wire clear;
1212
   assign clear = 1'b0;
1213
   reg  [length:1] qi;
1214
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1215
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1216
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1217
   assign q_next = rew ? q_next_rew : q_next_fw;
1218
   always @ (posedge clk or posedge rst)
1219
     if (rst)
1220
       qi <= {length{1'b0}};
1221
     else
1222
     if (cke)
1223
       qi <= q_next;
1224
    always @ (posedge clk or posedge rst)
1225
    if (rst)
1226
        level1 <= 1'b0;
1227
    else
1228
    if (cke)
1229
    if (clear)
1230
        level1 <= 1'b0;
1231
    else if (q_next == level1_value)
1232
        level1 <= 1'b1;
1233
    else if (qi == level1_value & rew)
1234
        level1 <= 1'b0;
1235
endmodule
1236
//////////////////////////////////////////////////////////////////////
1237
////                                                              ////
1238
////  Versatile counter                                           ////
1239
////                                                              ////
1240
////  Description                                                 ////
1241
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1242
////  counter                                                     ////
1243
////                                                              ////
1244
////  To Do:                                                      ////
1245
////   - add LFSR with more taps                                  ////
1246
////                                                              ////
1247
////  Author(s):                                                  ////
1248
////      - Michael Unneback, unneback@opencores.org              ////
1249
////        ORSoC AB                                              ////
1250
////                                                              ////
1251
//////////////////////////////////////////////////////////////////////
1252
////                                                              ////
1253
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1254
////                                                              ////
1255
//// This source file may be used and distributed without         ////
1256
//// restriction provided that this copyright statement is not    ////
1257
//// removed from the file and that any derivative work contains  ////
1258
//// the original copyright notice and the associated disclaimer. ////
1259
////                                                              ////
1260
//// This source file is free software; you can redistribute it   ////
1261
//// and/or modify it under the terms of the GNU Lesser General   ////
1262
//// Public License as published by the Free Software Foundation; ////
1263
//// either version 2.1 of the License, or (at your option) any   ////
1264
//// later version.                                               ////
1265
////                                                              ////
1266
//// This source is distributed in the hope that it will be       ////
1267
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1268
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1269
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1270
//// details.                                                     ////
1271
////                                                              ////
1272
//// You should have received a copy of the GNU Lesser General    ////
1273
//// Public License along with this source; if not, download it   ////
1274
//// from http://www.opencores.org/lgpl.shtml                     ////
1275
////                                                              ////
1276
//////////////////////////////////////////////////////////////////////
1277
// binary counter
1278 40 unneback
module vl_cnt_bin_ce_rew_zq_l1 (
1279
 cke, rew, zq, level1, rst, clk);
1280 6 unneback
   parameter length = 4;
1281
   input cke;
1282
   input rew;
1283 25 unneback
   output reg zq;
1284
   output reg level1;
1285
   input rst;
1286
   input clk;
1287
   parameter clear_value = 0;
1288
   parameter set_value = 1;
1289
   parameter wrap_value = 1;
1290
   parameter level1_value = 15;
1291 29 unneback
   wire clear;
1292 30 unneback
   assign clear = 1'b0;
1293 25 unneback
   reg  [length:1] qi;
1294
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1295
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1296
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1297
   assign q_next = rew ? q_next_rew : q_next_fw;
1298
   always @ (posedge clk or posedge rst)
1299
     if (rst)
1300
       qi <= {length{1'b0}};
1301
     else
1302
     if (cke)
1303
       qi <= q_next;
1304
   always @ (posedge clk or posedge rst)
1305
     if (rst)
1306
       zq <= 1'b1;
1307
     else
1308
     if (cke)
1309
       zq <= q_next == {length{1'b0}};
1310
    always @ (posedge clk or posedge rst)
1311
    if (rst)
1312
        level1 <= 1'b0;
1313
    else
1314
    if (cke)
1315 29 unneback
    if (clear)
1316
        level1 <= 1'b0;
1317
    else if (q_next == level1_value)
1318 25 unneback
        level1 <= 1'b1;
1319
    else if (qi == level1_value & rew)
1320
        level1 <= 1'b0;
1321
endmodule
1322
//////////////////////////////////////////////////////////////////////
1323
////                                                              ////
1324
////  Versatile counter                                           ////
1325
////                                                              ////
1326
////  Description                                                 ////
1327
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1328
////  counter                                                     ////
1329
////                                                              ////
1330
////  To Do:                                                      ////
1331
////   - add LFSR with more taps                                  ////
1332
////                                                              ////
1333
////  Author(s):                                                  ////
1334
////      - Michael Unneback, unneback@opencores.org              ////
1335
////        ORSoC AB                                              ////
1336
////                                                              ////
1337
//////////////////////////////////////////////////////////////////////
1338
////                                                              ////
1339
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1340
////                                                              ////
1341
//// This source file may be used and distributed without         ////
1342
//// restriction provided that this copyright statement is not    ////
1343
//// removed from the file and that any derivative work contains  ////
1344
//// the original copyright notice and the associated disclaimer. ////
1345
////                                                              ////
1346
//// This source file is free software; you can redistribute it   ////
1347
//// and/or modify it under the terms of the GNU Lesser General   ////
1348
//// Public License as published by the Free Software Foundation; ////
1349
//// either version 2.1 of the License, or (at your option) any   ////
1350
//// later version.                                               ////
1351
////                                                              ////
1352
//// This source is distributed in the hope that it will be       ////
1353
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1354
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1355
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1356
//// details.                                                     ////
1357
////                                                              ////
1358
//// You should have received a copy of the GNU Lesser General    ////
1359
//// Public License along with this source; if not, download it   ////
1360
//// from http://www.opencores.org/lgpl.shtml                     ////
1361
////                                                              ////
1362
//////////////////////////////////////////////////////////////////////
1363
// binary counter
1364 40 unneback
module vl_cnt_bin_ce_rew_q_zq_l1 (
1365
 cke, rew, q, zq, level1, rst, clk);
1366 25 unneback
   parameter length = 4;
1367
   input cke;
1368
   input rew;
1369
   output [length:1] q;
1370
   output reg zq;
1371
   output reg level1;
1372
   input rst;
1373
   input clk;
1374
   parameter clear_value = 0;
1375
   parameter set_value = 1;
1376
   parameter wrap_value = 1;
1377
   parameter level1_value = 15;
1378 29 unneback
   wire clear;
1379 30 unneback
   assign clear = 1'b0;
1380 25 unneback
   reg  [length:1] qi;
1381
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1382
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1383
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1384
   assign q_next = rew ? q_next_rew : q_next_fw;
1385
   always @ (posedge clk or posedge rst)
1386
     if (rst)
1387
       qi <= {length{1'b0}};
1388
     else
1389
     if (cke)
1390
       qi <= q_next;
1391
   assign q = qi;
1392
   always @ (posedge clk or posedge rst)
1393
     if (rst)
1394
       zq <= 1'b1;
1395
     else
1396
     if (cke)
1397
       zq <= q_next == {length{1'b0}};
1398
    always @ (posedge clk or posedge rst)
1399
    if (rst)
1400
        level1 <= 1'b0;
1401
    else
1402
    if (cke)
1403 29 unneback
    if (clear)
1404
        level1 <= 1'b0;
1405
    else if (q_next == level1_value)
1406 25 unneback
        level1 <= 1'b1;
1407
    else if (qi == level1_value & rew)
1408
        level1 <= 1'b0;
1409
endmodule
1410
//////////////////////////////////////////////////////////////////////
1411
////                                                              ////
1412
////  Versatile counter                                           ////
1413
////                                                              ////
1414
////  Description                                                 ////
1415
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1416
////  counter                                                     ////
1417
////                                                              ////
1418
////  To Do:                                                      ////
1419
////   - add LFSR with more taps                                  ////
1420
////                                                              ////
1421
////  Author(s):                                                  ////
1422
////      - Michael Unneback, unneback@opencores.org              ////
1423
////        ORSoC AB                                              ////
1424
////                                                              ////
1425
//////////////////////////////////////////////////////////////////////
1426
////                                                              ////
1427
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1428
////                                                              ////
1429
//// This source file may be used and distributed without         ////
1430
//// restriction provided that this copyright statement is not    ////
1431
//// removed from the file and that any derivative work contains  ////
1432
//// the original copyright notice and the associated disclaimer. ////
1433
////                                                              ////
1434
//// This source file is free software; you can redistribute it   ////
1435
//// and/or modify it under the terms of the GNU Lesser General   ////
1436
//// Public License as published by the Free Software Foundation; ////
1437
//// either version 2.1 of the License, or (at your option) any   ////
1438
//// later version.                                               ////
1439
////                                                              ////
1440
//// This source is distributed in the hope that it will be       ////
1441
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1442
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1443
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1444
//// details.                                                     ////
1445
////                                                              ////
1446
//// You should have received a copy of the GNU Lesser General    ////
1447
//// Public License along with this source; if not, download it   ////
1448
//// from http://www.opencores.org/lgpl.shtml                     ////
1449
////                                                              ////
1450
//////////////////////////////////////////////////////////////////////
1451 75 unneback
// LFSR counter
1452 136 unneback
module vl_cnt_lfsr_zq (
1453
 zq, rst, clk);
1454
   parameter length = 4;
1455
   output reg zq;
1456
   input rst;
1457
   input clk;
1458
   parameter clear_value = 0;
1459
   parameter set_value = 1;
1460
   parameter wrap_value = 8;
1461
   parameter level1_value = 15;
1462
   reg  [length:1] qi;
1463
   reg lfsr_fb;
1464
   wire [length:1] q_next;
1465
   reg [32:1] polynom;
1466
   integer i;
1467
   always @ (qi)
1468
   begin
1469
        case (length)
1470
         2: polynom = 32'b11;                               // 0x3
1471
         3: polynom = 32'b110;                              // 0x6
1472
         4: polynom = 32'b1100;                             // 0xC
1473
         5: polynom = 32'b10100;                            // 0x14
1474
         6: polynom = 32'b110000;                           // 0x30
1475
         7: polynom = 32'b1100000;                          // 0x60
1476
         8: polynom = 32'b10111000;                         // 0xb8
1477
         9: polynom = 32'b100010000;                        // 0x110
1478
        10: polynom = 32'b1001000000;                       // 0x240
1479
        11: polynom = 32'b10100000000;                      // 0x500
1480
        12: polynom = 32'b100000101001;                     // 0x829
1481
        13: polynom = 32'b1000000001100;                    // 0x100C
1482
        14: polynom = 32'b10000000010101;                   // 0x2015
1483
        15: polynom = 32'b110000000000000;                  // 0x6000
1484
        16: polynom = 32'b1101000000001000;                 // 0xD008
1485
        17: polynom = 32'b10010000000000000;                // 0x12000
1486
        18: polynom = 32'b100000010000000000;               // 0x20400
1487
        19: polynom = 32'b1000000000000100011;              // 0x40023
1488
        20: polynom = 32'b10010000000000000000;             // 0x90000
1489
        21: polynom = 32'b101000000000000000000;            // 0x140000
1490
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1491
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1492
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1493
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1494
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1495
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1496
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1497
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1498
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1499
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1500
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1501
        default: polynom = 32'b0;
1502
        endcase
1503
        lfsr_fb = qi[length];
1504
        for (i=length-1; i>=1; i=i-1) begin
1505
            if (polynom[i])
1506
                lfsr_fb = lfsr_fb  ~^ qi[i];
1507
        end
1508
    end
1509
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1510
   always @ (posedge clk or posedge rst)
1511
     if (rst)
1512
       qi <= {length{1'b0}};
1513
     else
1514
       qi <= q_next;
1515
   always @ (posedge clk or posedge rst)
1516
     if (rst)
1517
       zq <= 1'b1;
1518
     else
1519
       zq <= q_next == {length{1'b0}};
1520
endmodule
1521
//////////////////////////////////////////////////////////////////////
1522
////                                                              ////
1523
////  Versatile counter                                           ////
1524
////                                                              ////
1525
////  Description                                                 ////
1526
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1527
////  counter                                                     ////
1528
////                                                              ////
1529
////  To Do:                                                      ////
1530
////   - add LFSR with more taps                                  ////
1531
////                                                              ////
1532
////  Author(s):                                                  ////
1533
////      - Michael Unneback, unneback@opencores.org              ////
1534
////        ORSoC AB                                              ////
1535
////                                                              ////
1536
//////////////////////////////////////////////////////////////////////
1537
////                                                              ////
1538
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1539
////                                                              ////
1540
//// This source file may be used and distributed without         ////
1541
//// restriction provided that this copyright statement is not    ////
1542
//// removed from the file and that any derivative work contains  ////
1543
//// the original copyright notice and the associated disclaimer. ////
1544
////                                                              ////
1545
//// This source file is free software; you can redistribute it   ////
1546
//// and/or modify it under the terms of the GNU Lesser General   ////
1547
//// Public License as published by the Free Software Foundation; ////
1548
//// either version 2.1 of the License, or (at your option) any   ////
1549
//// later version.                                               ////
1550
////                                                              ////
1551
//// This source is distributed in the hope that it will be       ////
1552
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1553
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1554
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1555
//// details.                                                     ////
1556
////                                                              ////
1557
//// You should have received a copy of the GNU Lesser General    ////
1558
//// Public License along with this source; if not, download it   ////
1559
//// from http://www.opencores.org/lgpl.shtml                     ////
1560
////                                                              ////
1561
//////////////////////////////////////////////////////////////////////
1562
// LFSR counter
1563 75 unneback
module vl_cnt_lfsr_ce (
1564
 cke, zq, rst, clk);
1565
   parameter length = 4;
1566
   input cke;
1567
   output reg zq;
1568
   input rst;
1569
   input clk;
1570
   parameter clear_value = 0;
1571
   parameter set_value = 1;
1572
   parameter wrap_value = 0;
1573
   parameter level1_value = 15;
1574
   reg  [length:1] qi;
1575
   reg lfsr_fb;
1576
   wire [length:1] q_next;
1577
   reg [32:1] polynom;
1578
   integer i;
1579
   always @ (qi)
1580
   begin
1581
        case (length)
1582
         2: polynom = 32'b11;                               // 0x3
1583
         3: polynom = 32'b110;                              // 0x6
1584
         4: polynom = 32'b1100;                             // 0xC
1585
         5: polynom = 32'b10100;                            // 0x14
1586
         6: polynom = 32'b110000;                           // 0x30
1587
         7: polynom = 32'b1100000;                          // 0x60
1588
         8: polynom = 32'b10111000;                         // 0xb8
1589
         9: polynom = 32'b100010000;                        // 0x110
1590
        10: polynom = 32'b1001000000;                       // 0x240
1591
        11: polynom = 32'b10100000000;                      // 0x500
1592
        12: polynom = 32'b100000101001;                     // 0x829
1593
        13: polynom = 32'b1000000001100;                    // 0x100C
1594
        14: polynom = 32'b10000000010101;                   // 0x2015
1595
        15: polynom = 32'b110000000000000;                  // 0x6000
1596
        16: polynom = 32'b1101000000001000;                 // 0xD008
1597
        17: polynom = 32'b10010000000000000;                // 0x12000
1598
        18: polynom = 32'b100000010000000000;               // 0x20400
1599
        19: polynom = 32'b1000000000000100011;              // 0x40023
1600
        20: polynom = 32'b10010000000000000000;             // 0x90000
1601
        21: polynom = 32'b101000000000000000000;            // 0x140000
1602
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1603
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1604
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1605
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1606
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1607
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1608
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1609
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1610
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1611
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1612
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1613
        default: polynom = 32'b0;
1614
        endcase
1615
        lfsr_fb = qi[length];
1616
        for (i=length-1; i>=1; i=i-1) begin
1617
            if (polynom[i])
1618
                lfsr_fb = lfsr_fb  ~^ qi[i];
1619
        end
1620
    end
1621
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1622
   always @ (posedge clk or posedge rst)
1623
     if (rst)
1624
       qi <= {length{1'b0}};
1625
     else
1626
     if (cke)
1627
       qi <= q_next;
1628
   always @ (posedge clk or posedge rst)
1629
     if (rst)
1630
       zq <= 1'b1;
1631
     else
1632
     if (cke)
1633
       zq <= q_next == {length{1'b0}};
1634
endmodule
1635
//////////////////////////////////////////////////////////////////////
1636
////                                                              ////
1637
////  Versatile counter                                           ////
1638
////                                                              ////
1639
////  Description                                                 ////
1640
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1641
////  counter                                                     ////
1642
////                                                              ////
1643
////  To Do:                                                      ////
1644
////   - add LFSR with more taps                                  ////
1645
////                                                              ////
1646
////  Author(s):                                                  ////
1647
////      - Michael Unneback, unneback@opencores.org              ////
1648
////        ORSoC AB                                              ////
1649
////                                                              ////
1650
//////////////////////////////////////////////////////////////////////
1651
////                                                              ////
1652
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1653
////                                                              ////
1654
//// This source file may be used and distributed without         ////
1655
//// restriction provided that this copyright statement is not    ////
1656
//// removed from the file and that any derivative work contains  ////
1657
//// the original copyright notice and the associated disclaimer. ////
1658
////                                                              ////
1659
//// This source file is free software; you can redistribute it   ////
1660
//// and/or modify it under the terms of the GNU Lesser General   ////
1661
//// Public License as published by the Free Software Foundation; ////
1662
//// either version 2.1 of the License, or (at your option) any   ////
1663
//// later version.                                               ////
1664
////                                                              ////
1665
//// This source is distributed in the hope that it will be       ////
1666
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1667
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1668
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1669
//// details.                                                     ////
1670
////                                                              ////
1671
//// You should have received a copy of the GNU Lesser General    ////
1672
//// Public License along with this source; if not, download it   ////
1673
//// from http://www.opencores.org/lgpl.shtml                     ////
1674
////                                                              ////
1675
//////////////////////////////////////////////////////////////////////
1676 139 unneback
// LFSR counter
1677
module vl_cnt_lfsr_ce_zq (
1678
 cke, zq, rst, clk);
1679
   parameter length = 4;
1680
   input cke;
1681
   output reg zq;
1682
   input rst;
1683
   input clk;
1684
   parameter clear_value = 0;
1685
   parameter set_value = 1;
1686
   parameter wrap_value = 8;
1687
   parameter level1_value = 15;
1688
   reg  [length:1] qi;
1689
   reg lfsr_fb;
1690
   wire [length:1] q_next;
1691
   reg [32:1] polynom;
1692
   integer i;
1693
   always @ (qi)
1694
   begin
1695
        case (length)
1696
         2: polynom = 32'b11;                               // 0x3
1697
         3: polynom = 32'b110;                              // 0x6
1698
         4: polynom = 32'b1100;                             // 0xC
1699
         5: polynom = 32'b10100;                            // 0x14
1700
         6: polynom = 32'b110000;                           // 0x30
1701
         7: polynom = 32'b1100000;                          // 0x60
1702
         8: polynom = 32'b10111000;                         // 0xb8
1703
         9: polynom = 32'b100010000;                        // 0x110
1704
        10: polynom = 32'b1001000000;                       // 0x240
1705
        11: polynom = 32'b10100000000;                      // 0x500
1706
        12: polynom = 32'b100000101001;                     // 0x829
1707
        13: polynom = 32'b1000000001100;                    // 0x100C
1708
        14: polynom = 32'b10000000010101;                   // 0x2015
1709
        15: polynom = 32'b110000000000000;                  // 0x6000
1710
        16: polynom = 32'b1101000000001000;                 // 0xD008
1711
        17: polynom = 32'b10010000000000000;                // 0x12000
1712
        18: polynom = 32'b100000010000000000;               // 0x20400
1713
        19: polynom = 32'b1000000000000100011;              // 0x40023
1714
        20: polynom = 32'b10010000000000000000;             // 0x90000
1715
        21: polynom = 32'b101000000000000000000;            // 0x140000
1716
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1717
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1718
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1719
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1720
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1721
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1722
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1723
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1724
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1725
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1726
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1727
        default: polynom = 32'b0;
1728
        endcase
1729
        lfsr_fb = qi[length];
1730
        for (i=length-1; i>=1; i=i-1) begin
1731
            if (polynom[i])
1732
                lfsr_fb = lfsr_fb  ~^ qi[i];
1733
        end
1734
    end
1735
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1736
   always @ (posedge clk or posedge rst)
1737
     if (rst)
1738
       qi <= {length{1'b0}};
1739
     else
1740
     if (cke)
1741
       qi <= q_next;
1742
   always @ (posedge clk or posedge rst)
1743
     if (rst)
1744
       zq <= 1'b1;
1745
     else
1746
     if (cke)
1747
       zq <= q_next == {length{1'b0}};
1748
endmodule
1749
//////////////////////////////////////////////////////////////////////
1750
////                                                              ////
1751
////  Versatile counter                                           ////
1752
////                                                              ////
1753
////  Description                                                 ////
1754
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1755
////  counter                                                     ////
1756
////                                                              ////
1757
////  To Do:                                                      ////
1758
////   - add LFSR with more taps                                  ////
1759
////                                                              ////
1760
////  Author(s):                                                  ////
1761
////      - Michael Unneback, unneback@opencores.org              ////
1762
////        ORSoC AB                                              ////
1763
////                                                              ////
1764
//////////////////////////////////////////////////////////////////////
1765
////                                                              ////
1766
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1767
////                                                              ////
1768
//// This source file may be used and distributed without         ////
1769
//// restriction provided that this copyright statement is not    ////
1770
//// removed from the file and that any derivative work contains  ////
1771
//// the original copyright notice and the associated disclaimer. ////
1772
////                                                              ////
1773
//// This source file is free software; you can redistribute it   ////
1774
//// and/or modify it under the terms of the GNU Lesser General   ////
1775
//// Public License as published by the Free Software Foundation; ////
1776
//// either version 2.1 of the License, or (at your option) any   ////
1777
//// later version.                                               ////
1778
////                                                              ////
1779
//// This source is distributed in the hope that it will be       ////
1780
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1781
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1782
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1783
//// details.                                                     ////
1784
////                                                              ////
1785
//// You should have received a copy of the GNU Lesser General    ////
1786
//// Public License along with this source; if not, download it   ////
1787
//// from http://www.opencores.org/lgpl.shtml                     ////
1788
////                                                              ////
1789
//////////////////////////////////////////////////////////////////////
1790
// LFSR counter
1791
module vl_cnt_lfsr_ce_q (
1792
 cke, q, rst, clk);
1793
   parameter length = 4;
1794
   input cke;
1795
   output [length:1] q;
1796
   input rst;
1797
   input clk;
1798
   parameter clear_value = 0;
1799
   parameter set_value = 1;
1800
   parameter wrap_value = 8;
1801
   parameter level1_value = 15;
1802
   reg  [length:1] qi;
1803
   reg lfsr_fb;
1804
   wire [length:1] q_next;
1805
   reg [32:1] polynom;
1806
   integer i;
1807
   always @ (qi)
1808
   begin
1809
        case (length)
1810
         2: polynom = 32'b11;                               // 0x3
1811
         3: polynom = 32'b110;                              // 0x6
1812
         4: polynom = 32'b1100;                             // 0xC
1813
         5: polynom = 32'b10100;                            // 0x14
1814
         6: polynom = 32'b110000;                           // 0x30
1815
         7: polynom = 32'b1100000;                          // 0x60
1816
         8: polynom = 32'b10111000;                         // 0xb8
1817
         9: polynom = 32'b100010000;                        // 0x110
1818
        10: polynom = 32'b1001000000;                       // 0x240
1819
        11: polynom = 32'b10100000000;                      // 0x500
1820
        12: polynom = 32'b100000101001;                     // 0x829
1821
        13: polynom = 32'b1000000001100;                    // 0x100C
1822
        14: polynom = 32'b10000000010101;                   // 0x2015
1823
        15: polynom = 32'b110000000000000;                  // 0x6000
1824
        16: polynom = 32'b1101000000001000;                 // 0xD008
1825
        17: polynom = 32'b10010000000000000;                // 0x12000
1826
        18: polynom = 32'b100000010000000000;               // 0x20400
1827
        19: polynom = 32'b1000000000000100011;              // 0x40023
1828
        20: polynom = 32'b10010000000000000000;             // 0x90000
1829
        21: polynom = 32'b101000000000000000000;            // 0x140000
1830
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1831
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1832
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1833
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1834
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1835
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1836
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1837
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1838
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1839
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1840
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1841
        default: polynom = 32'b0;
1842
        endcase
1843
        lfsr_fb = qi[length];
1844
        for (i=length-1; i>=1; i=i-1) begin
1845
            if (polynom[i])
1846
                lfsr_fb = lfsr_fb  ~^ qi[i];
1847
        end
1848
    end
1849
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1850
   always @ (posedge clk or posedge rst)
1851
     if (rst)
1852
       qi <= {length{1'b0}};
1853
     else
1854
     if (cke)
1855
       qi <= q_next;
1856
   assign q = qi;
1857
endmodule
1858
//////////////////////////////////////////////////////////////////////
1859
////                                                              ////
1860
////  Versatile counter                                           ////
1861
////                                                              ////
1862
////  Description                                                 ////
1863
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1864
////  counter                                                     ////
1865
////                                                              ////
1866
////  To Do:                                                      ////
1867
////   - add LFSR with more taps                                  ////
1868
////                                                              ////
1869
////  Author(s):                                                  ////
1870
////      - Michael Unneback, unneback@opencores.org              ////
1871
////        ORSoC AB                                              ////
1872
////                                                              ////
1873
//////////////////////////////////////////////////////////////////////
1874
////                                                              ////
1875
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1876
////                                                              ////
1877
//// This source file may be used and distributed without         ////
1878
//// restriction provided that this copyright statement is not    ////
1879
//// removed from the file and that any derivative work contains  ////
1880
//// the original copyright notice and the associated disclaimer. ////
1881
////                                                              ////
1882
//// This source file is free software; you can redistribute it   ////
1883
//// and/or modify it under the terms of the GNU Lesser General   ////
1884
//// Public License as published by the Free Software Foundation; ////
1885
//// either version 2.1 of the License, or (at your option) any   ////
1886
//// later version.                                               ////
1887
////                                                              ////
1888
//// This source is distributed in the hope that it will be       ////
1889
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1890
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1891
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1892
//// details.                                                     ////
1893
////                                                              ////
1894
//// You should have received a copy of the GNU Lesser General    ////
1895
//// Public License along with this source; if not, download it   ////
1896
//// from http://www.opencores.org/lgpl.shtml                     ////
1897
////                                                              ////
1898
//////////////////////////////////////////////////////////////////////
1899
// LFSR counter
1900
module vl_cnt_lfsr_ce_clear_q (
1901
 clear, cke, q, rst, clk);
1902
   parameter length = 4;
1903
   input clear;
1904
   input cke;
1905
   output [length:1] q;
1906
   input rst;
1907
   input clk;
1908
   parameter clear_value = 0;
1909
   parameter set_value = 1;
1910
   parameter wrap_value = 8;
1911
   parameter level1_value = 15;
1912
   reg  [length:1] qi;
1913
   reg lfsr_fb;
1914
   wire [length:1] q_next;
1915
   reg [32:1] polynom;
1916
   integer i;
1917
   always @ (qi)
1918
   begin
1919
        case (length)
1920
         2: polynom = 32'b11;                               // 0x3
1921
         3: polynom = 32'b110;                              // 0x6
1922
         4: polynom = 32'b1100;                             // 0xC
1923
         5: polynom = 32'b10100;                            // 0x14
1924
         6: polynom = 32'b110000;                           // 0x30
1925
         7: polynom = 32'b1100000;                          // 0x60
1926
         8: polynom = 32'b10111000;                         // 0xb8
1927
         9: polynom = 32'b100010000;                        // 0x110
1928
        10: polynom = 32'b1001000000;                       // 0x240
1929
        11: polynom = 32'b10100000000;                      // 0x500
1930
        12: polynom = 32'b100000101001;                     // 0x829
1931
        13: polynom = 32'b1000000001100;                    // 0x100C
1932
        14: polynom = 32'b10000000010101;                   // 0x2015
1933
        15: polynom = 32'b110000000000000;                  // 0x6000
1934
        16: polynom = 32'b1101000000001000;                 // 0xD008
1935
        17: polynom = 32'b10010000000000000;                // 0x12000
1936
        18: polynom = 32'b100000010000000000;               // 0x20400
1937
        19: polynom = 32'b1000000000000100011;              // 0x40023
1938
        20: polynom = 32'b10010000000000000000;             // 0x90000
1939
        21: polynom = 32'b101000000000000000000;            // 0x140000
1940
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1941
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1942
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1943
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1944
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1945
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1946
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1947
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1948
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1949
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1950
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1951
        default: polynom = 32'b0;
1952
        endcase
1953
        lfsr_fb = qi[length];
1954
        for (i=length-1; i>=1; i=i-1) begin
1955
            if (polynom[i])
1956
                lfsr_fb = lfsr_fb  ~^ qi[i];
1957
        end
1958
    end
1959
   assign q_next =  clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1960
   always @ (posedge clk or posedge rst)
1961
     if (rst)
1962
       qi <= {length{1'b0}};
1963
     else
1964
     if (cke)
1965
       qi <= q_next;
1966
   assign q = qi;
1967
endmodule
1968
//////////////////////////////////////////////////////////////////////
1969
////                                                              ////
1970
////  Versatile counter                                           ////
1971
////                                                              ////
1972
////  Description                                                 ////
1973
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1974
////  counter                                                     ////
1975
////                                                              ////
1976
////  To Do:                                                      ////
1977
////   - add LFSR with more taps                                  ////
1978
////                                                              ////
1979
////  Author(s):                                                  ////
1980
////      - Michael Unneback, unneback@opencores.org              ////
1981
////        ORSoC AB                                              ////
1982
////                                                              ////
1983
//////////////////////////////////////////////////////////////////////
1984
////                                                              ////
1985
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1986
////                                                              ////
1987
//// This source file may be used and distributed without         ////
1988
//// restriction provided that this copyright statement is not    ////
1989
//// removed from the file and that any derivative work contains  ////
1990
//// the original copyright notice and the associated disclaimer. ////
1991
////                                                              ////
1992
//// This source file is free software; you can redistribute it   ////
1993
//// and/or modify it under the terms of the GNU Lesser General   ////
1994
//// Public License as published by the Free Software Foundation; ////
1995
//// either version 2.1 of the License, or (at your option) any   ////
1996
//// later version.                                               ////
1997
////                                                              ////
1998
//// This source is distributed in the hope that it will be       ////
1999
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2000
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2001
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2002
//// details.                                                     ////
2003
////                                                              ////
2004
//// You should have received a copy of the GNU Lesser General    ////
2005
//// Public License along with this source; if not, download it   ////
2006
//// from http://www.opencores.org/lgpl.shtml                     ////
2007
////                                                              ////
2008
//////////////////////////////////////////////////////////////////////
2009
// LFSR counter
2010
module vl_cnt_lfsr_ce_q_zq (
2011
 cke, q, zq, rst, clk);
2012
   parameter length = 4;
2013
   input cke;
2014
   output [length:1] q;
2015
   output reg zq;
2016
   input rst;
2017
   input clk;
2018
   parameter clear_value = 0;
2019
   parameter set_value = 1;
2020
   parameter wrap_value = 8;
2021
   parameter level1_value = 15;
2022
   reg  [length:1] qi;
2023
   reg lfsr_fb;
2024
   wire [length:1] q_next;
2025
   reg [32:1] polynom;
2026
   integer i;
2027
   always @ (qi)
2028
   begin
2029
        case (length)
2030
         2: polynom = 32'b11;                               // 0x3
2031
         3: polynom = 32'b110;                              // 0x6
2032
         4: polynom = 32'b1100;                             // 0xC
2033
         5: polynom = 32'b10100;                            // 0x14
2034
         6: polynom = 32'b110000;                           // 0x30
2035
         7: polynom = 32'b1100000;                          // 0x60
2036
         8: polynom = 32'b10111000;                         // 0xb8
2037
         9: polynom = 32'b100010000;                        // 0x110
2038
        10: polynom = 32'b1001000000;                       // 0x240
2039
        11: polynom = 32'b10100000000;                      // 0x500
2040
        12: polynom = 32'b100000101001;                     // 0x829
2041
        13: polynom = 32'b1000000001100;                    // 0x100C
2042
        14: polynom = 32'b10000000010101;                   // 0x2015
2043
        15: polynom = 32'b110000000000000;                  // 0x6000
2044
        16: polynom = 32'b1101000000001000;                 // 0xD008
2045
        17: polynom = 32'b10010000000000000;                // 0x12000
2046
        18: polynom = 32'b100000010000000000;               // 0x20400
2047
        19: polynom = 32'b1000000000000100011;              // 0x40023
2048
        20: polynom = 32'b10010000000000000000;             // 0x90000
2049
        21: polynom = 32'b101000000000000000000;            // 0x140000
2050
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2051
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2052
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2053
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2054
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2055
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2056
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2057
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2058
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2059
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2060
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2061
        default: polynom = 32'b0;
2062
        endcase
2063
        lfsr_fb = qi[length];
2064
        for (i=length-1; i>=1; i=i-1) begin
2065
            if (polynom[i])
2066
                lfsr_fb = lfsr_fb  ~^ qi[i];
2067
        end
2068
    end
2069
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2070
   always @ (posedge clk or posedge rst)
2071
     if (rst)
2072
       qi <= {length{1'b0}};
2073
     else
2074
     if (cke)
2075
       qi <= q_next;
2076
   assign q = qi;
2077
   always @ (posedge clk or posedge rst)
2078
     if (rst)
2079
       zq <= 1'b1;
2080
     else
2081
     if (cke)
2082
       zq <= q_next == {length{1'b0}};
2083
endmodule
2084
//////////////////////////////////////////////////////////////////////
2085
////                                                              ////
2086
////  Versatile counter                                           ////
2087
////                                                              ////
2088
////  Description                                                 ////
2089
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2090
////  counter                                                     ////
2091
////                                                              ////
2092
////  To Do:                                                      ////
2093
////   - add LFSR with more taps                                  ////
2094
////                                                              ////
2095
////  Author(s):                                                  ////
2096
////      - Michael Unneback, unneback@opencores.org              ////
2097
////        ORSoC AB                                              ////
2098
////                                                              ////
2099
//////////////////////////////////////////////////////////////////////
2100
////                                                              ////
2101
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2102
////                                                              ////
2103
//// This source file may be used and distributed without         ////
2104
//// restriction provided that this copyright statement is not    ////
2105
//// removed from the file and that any derivative work contains  ////
2106
//// the original copyright notice and the associated disclaimer. ////
2107
////                                                              ////
2108
//// This source file is free software; you can redistribute it   ////
2109
//// and/or modify it under the terms of the GNU Lesser General   ////
2110
//// Public License as published by the Free Software Foundation; ////
2111
//// either version 2.1 of the License, or (at your option) any   ////
2112
//// later version.                                               ////
2113
////                                                              ////
2114
//// This source is distributed in the hope that it will be       ////
2115
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2116
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2117
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2118
//// details.                                                     ////
2119
////                                                              ////
2120
//// You should have received a copy of the GNU Lesser General    ////
2121
//// Public License along with this source; if not, download it   ////
2122
//// from http://www.opencores.org/lgpl.shtml                     ////
2123
////                                                              ////
2124
//////////////////////////////////////////////////////////////////////
2125
// LFSR counter
2126
module vl_cnt_lfsr_ce_rew_l1 (
2127
 cke, rew, level1, rst, clk);
2128
   parameter length = 4;
2129
   input cke;
2130
   input rew;
2131
   output reg level1;
2132
   input rst;
2133
   input clk;
2134
   parameter clear_value = 0;
2135
   parameter set_value = 1;
2136
   parameter wrap_value = 8;
2137
   parameter level1_value = 15;
2138
   wire clear;
2139
   assign clear = 1'b0;
2140
   reg  [length:1] qi;
2141
   reg lfsr_fb, lfsr_fb_rew;
2142
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2143
   reg [32:1] polynom_rew;
2144
   integer j;
2145
   reg [32:1] polynom;
2146
   integer i;
2147
   always @ (qi)
2148
   begin
2149
        case (length)
2150
         2: polynom = 32'b11;                               // 0x3
2151
         3: polynom = 32'b110;                              // 0x6
2152
         4: polynom = 32'b1100;                             // 0xC
2153
         5: polynom = 32'b10100;                            // 0x14
2154
         6: polynom = 32'b110000;                           // 0x30
2155
         7: polynom = 32'b1100000;                          // 0x60
2156
         8: polynom = 32'b10111000;                         // 0xb8
2157
         9: polynom = 32'b100010000;                        // 0x110
2158
        10: polynom = 32'b1001000000;                       // 0x240
2159
        11: polynom = 32'b10100000000;                      // 0x500
2160
        12: polynom = 32'b100000101001;                     // 0x829
2161
        13: polynom = 32'b1000000001100;                    // 0x100C
2162
        14: polynom = 32'b10000000010101;                   // 0x2015
2163
        15: polynom = 32'b110000000000000;                  // 0x6000
2164
        16: polynom = 32'b1101000000001000;                 // 0xD008
2165
        17: polynom = 32'b10010000000000000;                // 0x12000
2166
        18: polynom = 32'b100000010000000000;               // 0x20400
2167
        19: polynom = 32'b1000000000000100011;              // 0x40023
2168
        20: polynom = 32'b10010000000000000000;             // 0x90000
2169
        21: polynom = 32'b101000000000000000000;            // 0x140000
2170
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2171
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2172
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2173
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2174
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2175
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2176
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2177
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2178
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2179
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2180
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2181
        default: polynom = 32'b0;
2182
        endcase
2183
        lfsr_fb = qi[length];
2184
        for (i=length-1; i>=1; i=i-1) begin
2185
            if (polynom[i])
2186
                lfsr_fb = lfsr_fb  ~^ qi[i];
2187
        end
2188
    end
2189
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2190
   always @ (qi)
2191
   begin
2192
        case (length)
2193
         2: polynom_rew = 32'b11;
2194
         3: polynom_rew = 32'b110;
2195
         4: polynom_rew = 32'b1100;
2196
         5: polynom_rew = 32'b10100;
2197
         6: polynom_rew = 32'b110000;
2198
         7: polynom_rew = 32'b1100000;
2199
         8: polynom_rew = 32'b10111000;
2200
         9: polynom_rew = 32'b100010000;
2201
        10: polynom_rew = 32'b1001000000;
2202
        11: polynom_rew = 32'b10100000000;
2203
        12: polynom_rew = 32'b100000101001;
2204
        13: polynom_rew = 32'b1000000001100;
2205
        14: polynom_rew = 32'b10000000010101;
2206
        15: polynom_rew = 32'b110000000000000;
2207
        16: polynom_rew = 32'b1101000000001000;
2208
        17: polynom_rew = 32'b10010000000000000;
2209
        18: polynom_rew = 32'b100000010000000000;
2210
        19: polynom_rew = 32'b1000000000000100011;
2211
        20: polynom_rew = 32'b10000010000000000000;
2212
        21: polynom_rew = 32'b101000000000000000000;
2213
        22: polynom_rew = 32'b1100000000000000000000;
2214
        23: polynom_rew = 32'b10000100000000000000000;
2215
        24: polynom_rew = 32'b111000010000000000000000;
2216
        25: polynom_rew = 32'b1001000000000000000000000;
2217
        26: polynom_rew = 32'b10000000000000000000100011;
2218
        27: polynom_rew = 32'b100000000000000000000010011;
2219
        28: polynom_rew = 32'b1100100000000000000000000000;
2220
        29: polynom_rew = 32'b10100000000000000000000000000;
2221
        30: polynom_rew = 32'b100000000000000000000000101001;
2222
        31: polynom_rew = 32'b1001000000000000000000000000000;
2223
        32: polynom_rew = 32'b10000000001000000000000000000011;
2224
        default: polynom_rew = 32'b0;
2225
        endcase
2226
        // rotate left
2227
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
2228
        lfsr_fb_rew = qi[length];
2229
        for (i=length-1; i>=1; i=i-1) begin
2230
            if (polynom_rew[i])
2231
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
2232
        end
2233
    end
2234
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
2235
   assign q_next = rew ? q_next_rew : q_next_fw;
2236
   always @ (posedge clk or posedge rst)
2237
     if (rst)
2238
       qi <= {length{1'b0}};
2239
     else
2240
     if (cke)
2241
       qi <= q_next;
2242
    always @ (posedge clk or posedge rst)
2243
    if (rst)
2244
        level1 <= 1'b0;
2245
    else
2246
    if (cke)
2247
    if (clear)
2248
        level1 <= 1'b0;
2249
    else if (q_next == level1_value)
2250
        level1 <= 1'b1;
2251
    else if (qi == level1_value & rew)
2252
        level1 <= 1'b0;
2253
endmodule
2254
//////////////////////////////////////////////////////////////////////
2255
////                                                              ////
2256
////  Versatile counter                                           ////
2257
////                                                              ////
2258
////  Description                                                 ////
2259
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2260
////  counter                                                     ////
2261
////                                                              ////
2262
////  To Do:                                                      ////
2263
////   - add LFSR with more taps                                  ////
2264
////                                                              ////
2265
////  Author(s):                                                  ////
2266
////      - Michael Unneback, unneback@opencores.org              ////
2267
////        ORSoC AB                                              ////
2268
////                                                              ////
2269
//////////////////////////////////////////////////////////////////////
2270
////                                                              ////
2271
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2272
////                                                              ////
2273
//// This source file may be used and distributed without         ////
2274
//// restriction provided that this copyright statement is not    ////
2275
//// removed from the file and that any derivative work contains  ////
2276
//// the original copyright notice and the associated disclaimer. ////
2277
////                                                              ////
2278
//// This source file is free software; you can redistribute it   ////
2279
//// and/or modify it under the terms of the GNU Lesser General   ////
2280
//// Public License as published by the Free Software Foundation; ////
2281
//// either version 2.1 of the License, or (at your option) any   ////
2282
//// later version.                                               ////
2283
////                                                              ////
2284
//// This source is distributed in the hope that it will be       ////
2285
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2286
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2287
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2288
//// details.                                                     ////
2289
////                                                              ////
2290
//// You should have received a copy of the GNU Lesser General    ////
2291
//// Public License along with this source; if not, download it   ////
2292
//// from http://www.opencores.org/lgpl.shtml                     ////
2293
////                                                              ////
2294
//////////////////////////////////////////////////////////////////////
2295 6 unneback
// GRAY counter
2296 139 unneback
module vl_cnt_gray (
2297
 q, rst, clk);
2298
   parameter length = 4;
2299
   output reg [length:1] q;
2300
   input rst;
2301
   input clk;
2302
   parameter clear_value = 0;
2303
   parameter set_value = 1;
2304
   parameter wrap_value = 8;
2305
   parameter level1_value = 15;
2306
   reg  [length:1] qi;
2307
   wire [length:1] q_next;
2308
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2309
   always @ (posedge clk or posedge rst)
2310
     if (rst)
2311
       qi <= {length{1'b0}};
2312
     else
2313
       qi <= q_next;
2314
   always @ (posedge clk or posedge rst)
2315
     if (rst)
2316
       q <= {length{1'b0}};
2317
     else
2318
         q <= (q_next>>1) ^ q_next;
2319
endmodule
2320
//////////////////////////////////////////////////////////////////////
2321
////                                                              ////
2322
////  Versatile counter                                           ////
2323
////                                                              ////
2324
////  Description                                                 ////
2325
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2326
////  counter                                                     ////
2327
////                                                              ////
2328
////  To Do:                                                      ////
2329
////   - add LFSR with more taps                                  ////
2330
////                                                              ////
2331
////  Author(s):                                                  ////
2332
////      - Michael Unneback, unneback@opencores.org              ////
2333
////        ORSoC AB                                              ////
2334
////                                                              ////
2335
//////////////////////////////////////////////////////////////////////
2336
////                                                              ////
2337
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2338
////                                                              ////
2339
//// This source file may be used and distributed without         ////
2340
//// restriction provided that this copyright statement is not    ////
2341
//// removed from the file and that any derivative work contains  ////
2342
//// the original copyright notice and the associated disclaimer. ////
2343
////                                                              ////
2344
//// This source file is free software; you can redistribute it   ////
2345
//// and/or modify it under the terms of the GNU Lesser General   ////
2346
//// Public License as published by the Free Software Foundation; ////
2347
//// either version 2.1 of the License, or (at your option) any   ////
2348
//// later version.                                               ////
2349
////                                                              ////
2350
//// This source is distributed in the hope that it will be       ////
2351
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2352
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2353
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2354
//// details.                                                     ////
2355
////                                                              ////
2356
//// You should have received a copy of the GNU Lesser General    ////
2357
//// Public License along with this source; if not, download it   ////
2358
//// from http://www.opencores.org/lgpl.shtml                     ////
2359
////                                                              ////
2360
//////////////////////////////////////////////////////////////////////
2361
// GRAY counter
2362
module vl_cnt_gray_ce (
2363
 cke, q, rst, clk);
2364
   parameter length = 4;
2365
   input cke;
2366
   output reg [length:1] q;
2367
   input rst;
2368
   input clk;
2369
   parameter clear_value = 0;
2370
   parameter set_value = 1;
2371
   parameter wrap_value = 8;
2372
   parameter level1_value = 15;
2373
   reg  [length:1] qi;
2374
   wire [length:1] q_next;
2375
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2376
   always @ (posedge clk or posedge rst)
2377
     if (rst)
2378
       qi <= {length{1'b0}};
2379
     else
2380
     if (cke)
2381
       qi <= q_next;
2382
   always @ (posedge clk or posedge rst)
2383
     if (rst)
2384
       q <= {length{1'b0}};
2385
     else
2386
       if (cke)
2387
         q <= (q_next>>1) ^ q_next;
2388
endmodule
2389
//////////////////////////////////////////////////////////////////////
2390
////                                                              ////
2391
////  Versatile counter                                           ////
2392
////                                                              ////
2393
////  Description                                                 ////
2394
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2395
////  counter                                                     ////
2396
////                                                              ////
2397
////  To Do:                                                      ////
2398
////   - add LFSR with more taps                                  ////
2399
////                                                              ////
2400
////  Author(s):                                                  ////
2401
////      - Michael Unneback, unneback@opencores.org              ////
2402
////        ORSoC AB                                              ////
2403
////                                                              ////
2404
//////////////////////////////////////////////////////////////////////
2405
////                                                              ////
2406
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2407
////                                                              ////
2408
//// This source file may be used and distributed without         ////
2409
//// restriction provided that this copyright statement is not    ////
2410
//// removed from the file and that any derivative work contains  ////
2411
//// the original copyright notice and the associated disclaimer. ////
2412
////                                                              ////
2413
//// This source file is free software; you can redistribute it   ////
2414
//// and/or modify it under the terms of the GNU Lesser General   ////
2415
//// Public License as published by the Free Software Foundation; ////
2416
//// either version 2.1 of the License, or (at your option) any   ////
2417
//// later version.                                               ////
2418
////                                                              ////
2419
//// This source is distributed in the hope that it will be       ////
2420
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2421
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2422
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2423
//// details.                                                     ////
2424
////                                                              ////
2425
//// You should have received a copy of the GNU Lesser General    ////
2426
//// Public License along with this source; if not, download it   ////
2427
//// from http://www.opencores.org/lgpl.shtml                     ////
2428
////                                                              ////
2429
//////////////////////////////////////////////////////////////////////
2430
// GRAY counter
2431 40 unneback
module vl_cnt_gray_ce_bin (
2432
 cke, q, q_bin, rst, clk);
2433 6 unneback
   parameter length = 4;
2434
   input cke;
2435
   output reg [length:1] q;
2436
   output [length:1] q_bin;
2437
   input rst;
2438
   input clk;
2439
   parameter clear_value = 0;
2440
   parameter set_value = 1;
2441
   parameter wrap_value = 8;
2442
   parameter level1_value = 15;
2443
   reg  [length:1] qi;
2444
   wire [length:1] q_next;
2445
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2446
   always @ (posedge clk or posedge rst)
2447
     if (rst)
2448
       qi <= {length{1'b0}};
2449
     else
2450
     if (cke)
2451
       qi <= q_next;
2452
   always @ (posedge clk or posedge rst)
2453
     if (rst)
2454
       q <= {length{1'b0}};
2455
     else
2456
       if (cke)
2457
         q <= (q_next>>1) ^ q_next;
2458
   assign q_bin = qi;
2459
endmodule
2460
//////////////////////////////////////////////////////////////////////
2461
////                                                              ////
2462
////  Versatile library, counters                                 ////
2463
////                                                              ////
2464
////  Description                                                 ////
2465
////  counters                                                    ////
2466
////                                                              ////
2467
////                                                              ////
2468
////  To Do:                                                      ////
2469
////   - add more counters                                        ////
2470
////                                                              ////
2471
////  Author(s):                                                  ////
2472
////      - Michael Unneback, unneback@opencores.org              ////
2473
////        ORSoC AB                                              ////
2474
////                                                              ////
2475
//////////////////////////////////////////////////////////////////////
2476
////                                                              ////
2477
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2478
////                                                              ////
2479
//// This source file may be used and distributed without         ////
2480
//// restriction provided that this copyright statement is not    ////
2481
//// removed from the file and that any derivative work contains  ////
2482
//// the original copyright notice and the associated disclaimer. ////
2483
////                                                              ////
2484
//// This source file is free software; you can redistribute it   ////
2485
//// and/or modify it under the terms of the GNU Lesser General   ////
2486
//// Public License as published by the Free Software Foundation; ////
2487
//// either version 2.1 of the License, or (at your option) any   ////
2488
//// later version.                                               ////
2489
////                                                              ////
2490
//// This source is distributed in the hope that it will be       ////
2491
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2492
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2493
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2494
//// details.                                                     ////
2495
////                                                              ////
2496
//// You should have received a copy of the GNU Lesser General    ////
2497
//// Public License along with this source; if not, download it   ////
2498
//// from http://www.opencores.org/lgpl.shtml                     ////
2499
////                                                              ////
2500
//////////////////////////////////////////////////////////////////////
2501 18 unneback
module vl_cnt_shreg_wrap ( q, rst, clk);
2502 6 unneback
   parameter length = 4;
2503
   output reg [0:length-1] q;
2504
   input rst;
2505
   input clk;
2506
    always @ (posedge clk or posedge rst)
2507
    if (rst)
2508
        q <= {1'b1,{length-1{1'b0}}};
2509
    else
2510
        q <= {q[length-1],q[0:length-2]};
2511
endmodule
2512 18 unneback
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
2513 6 unneback
   parameter length = 4;
2514
   input cke;
2515
   output reg [0:length-1] q;
2516
   input rst;
2517
   input clk;
2518
    always @ (posedge clk or posedge rst)
2519
    if (rst)
2520
        q <= {1'b1,{length-1{1'b0}}};
2521
    else
2522
        if (cke)
2523
            q <= {q[length-1],q[0:length-2]};
2524
endmodule
2525 105 unneback
module vl_cnt_shreg_clear ( clear, q, rst, clk);
2526
   parameter length = 4;
2527
   input clear;
2528
   output reg [0:length-1] q;
2529
   input rst;
2530
   input clk;
2531
    always @ (posedge clk or posedge rst)
2532
    if (rst)
2533
        q <= {1'b1,{length-1{1'b0}}};
2534
    else
2535
        if (clear)
2536
            q <= {1'b1,{length-1{1'b0}}};
2537
        else
2538
            q <= q >> 1;
2539
endmodule
2540 18 unneback
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
2541 6 unneback
   parameter length = 4;
2542
   input cke, clear;
2543
   output reg [0:length-1] q;
2544
   input rst;
2545
   input clk;
2546
    always @ (posedge clk or posedge rst)
2547
    if (rst)
2548
        q <= {1'b1,{length-1{1'b0}}};
2549
    else
2550
        if (cke)
2551
            if (clear)
2552
                q <= {1'b1,{length-1{1'b0}}};
2553
            else
2554
                q <= q >> 1;
2555
endmodule
2556 18 unneback
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
2557 6 unneback
   parameter length = 4;
2558
   input cke, clear;
2559
   output reg [0:length-1] q;
2560
   input rst;
2561
   input clk;
2562
    always @ (posedge clk or posedge rst)
2563
    if (rst)
2564
        q <= {1'b1,{length-1{1'b0}}};
2565
    else
2566
        if (cke)
2567
            if (clear)
2568
                q <= {1'b1,{length-1{1'b0}}};
2569
            else
2570
            q <= {q[length-1],q[0:length-2]};
2571
endmodule
2572
//////////////////////////////////////////////////////////////////////
2573
////                                                              ////
2574
////  Versatile library, memories                                 ////
2575
////                                                              ////
2576
////  Description                                                 ////
2577
////  memories                                                    ////
2578
////                                                              ////
2579
////                                                              ////
2580
////  To Do:                                                      ////
2581
////   - add more memory types                                    ////
2582
////                                                              ////
2583
////  Author(s):                                                  ////
2584
////      - Michael Unneback, unneback@opencores.org              ////
2585
////        ORSoC AB                                              ////
2586
////                                                              ////
2587
//////////////////////////////////////////////////////////////////////
2588
////                                                              ////
2589
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2590
////                                                              ////
2591
//// This source file may be used and distributed without         ////
2592
//// restriction provided that this copyright statement is not    ////
2593
//// removed from the file and that any derivative work contains  ////
2594
//// the original copyright notice and the associated disclaimer. ////
2595
////                                                              ////
2596
//// This source file is free software; you can redistribute it   ////
2597
//// and/or modify it under the terms of the GNU Lesser General   ////
2598