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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Blame information for rev 139

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Line No. Rev Author Line
1 60 unneback 
// default SYN_KEEP definition
2 98 unneback 
    // ACTEL FPGA should not use logic to handle rw collision
3 136 unneback 
///////////////////////////////////////
4 
// dependencies
5 
///////////////////////////////////////
6 97 unneback 
// size to width
7 6 unneback 
//////////////////////////////////////////////////////////////////////
8 
////                                                              ////
9 
////  Versatile library, clock and reset                          ////
10 
////                                                              ////
11 
////  Description                                                 ////
12 
////  Logic related to clock and reset                            ////
13 
////                                                              ////
14 
////                                                              ////
15 
////  To Do:                                                      ////
16 
////   - add more different registers                             ////
17 
////                                                              ////
18 
////  Author(s):                                                  ////
19 
////      - Michael Unneback, unneback@opencores.org              ////
20 
////        ORSoC AB                                              ////
21 
////                                                              ////
22 
//////////////////////////////////////////////////////////////////////
23 
////                                                              ////
24 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
25 
////                                                              ////
26 
//// This source file may be used and distributed without         ////
27 
//// restriction provided that this copyright statement is not    ////
28 
//// removed from the file and that any derivative work contains  ////
29 
//// the original copyright notice and the associated disclaimer. ////
30 
////                                                              ////
31 
//// This source file is free software; you can redistribute it   ////
32 
//// and/or modify it under the terms of the GNU Lesser General   ////
33 
//// Public License as published by the Free Software Foundation; ////
34 
//// either version 2.1 of the License, or (at your option) any   ////
35 
//// later version.                                               ////
36 
////                                                              ////
37 
//// This source is distributed in the hope that it will be       ////
38 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
39 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
40 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
41 
//// details.                                                     ////
42 
////                                                              ////
43 
//// You should have received a copy of the GNU Lesser General    ////
44 
//// Public License along with this source; if not, download it   ////
45 
//// from http://www.opencores.org/lgpl.shtml                     ////
46 
////                                                              ////
47 
//////////////////////////////////////////////////////////////////////
48 48 unneback 
`timescale 1 ns/100 ps
49 6 unneback 
// Global buffer
50 
// usage:
51 
// use to enable global buffers for high fan out signals such as clock and reset
52 
// Version: 8.4 8.4.0.33
53 
module gbuf(GL,CLK);
54 
output GL;
55 
input  CLK;
56 
    wire GND;
57 
    GND GND_1_net(.Y(GND));
58 
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
59 
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
60 
endmodule
61 
`timescale 1 ns/1 ns
62 
module vl_gbuf ( i, o);
63 
input i;
64 
output o;
65 
`ifdef SIM_GBUF
66 
assign o=i;
67 
`else
68 
gbuf gbuf_i0 ( .CLK(i), .GL(o));
69 
`endif
70 
endmodule
71 
 //ACTEL
72 
// sync reset
73 17 unneback 
// input active lo async reset, normally from external reset generator and/or switch
74 6 unneback 
// output active high global reset sync with two DFFs
75 
`timescale 1 ns/100 ps
76 
module vl_sync_rst ( rst_n_i, rst_o, clk);
77 
input rst_n_i, clk;
78 
output rst_o;
79 18 unneback 
reg [1:0] tmp;
80 6 unneback 
always @ (posedge clk or negedge rst_n_i)
81 
if (!rst_n_i)
82 17 unneback 
        tmp <= 2'b11;
83 6 unneback 
else
84 33 unneback 
        tmp <= {1'b0,tmp[1]};
85 17 unneback 
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
86 6 unneback 
endmodule
87 
// vl_pll
88 32 unneback 
///////////////////////////////////////////////////////////////////////////////
89 17 unneback 
`timescale 1 ps/1 ps
90 6 unneback 
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
91 
parameter index = 0;
92 
parameter number_of_clk = 1;
93 17 unneback 
parameter period_time_0 = 20000;
94 
parameter period_time_1 = 20000;
95 
parameter period_time_2 = 20000;
96 
parameter lock_delay = 2000000;
97 6 unneback 
input clk_i, rst_n_i;
98 
output lock;
99 
output reg [0:number_of_clk-1] clk_o;
100 
output [0:number_of_clk-1] rst_o;
101 
`ifdef SIM_PLL
102 
always
103 
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
104 
generate if (number_of_clk > 1)
105 
always
106 
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
107 
endgenerate
108 
generate if (number_of_clk > 2)
109 
always
110 
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
111 
endgenerate
112 
genvar i;
113 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
114 
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
115 
end
116 
endgenerate
117 
assign #lock_delay lock = rst_n_i;
118 
endmodule
119 
`else
120 
generate if (number_of_clk==1 & index==0) begin
121 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
122 
end
123 
endgenerate // index==0
124 
generate if (number_of_clk==1 & index==1) begin
125 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
126 
end
127 
endgenerate // index==1
128 
generate if (number_of_clk==1 & index==2) begin
129 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
130 
end
131 
endgenerate // index==2
132 
generate if (number_of_clk==1 & index==3) begin
133 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
134 
end
135 
endgenerate // index==0
136 
generate if (number_of_clk==2 & index==0) begin
137 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
138 
end
139 
endgenerate // index==0
140 
generate if (number_of_clk==2 & index==1) begin
141 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
142 
end
143 
endgenerate // index==1
144 
generate if (number_of_clk==2 & index==2) begin
145 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
146 
end
147 
endgenerate // index==2
148 
generate if (number_of_clk==2 & index==3) begin
149 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
150 
end
151 
endgenerate // index==0
152 
generate if (number_of_clk==3 & index==0) begin
153 
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
154 
end
155 
endgenerate // index==0
156 
generate if (number_of_clk==3 & index==1) begin
157 
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
158 
end
159 
endgenerate // index==1
160 
generate if (number_of_clk==3 & index==2) begin
161 
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
162 
end
163 
endgenerate // index==2
164 
generate if (number_of_clk==3 & index==3) begin
165 
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
166 
end
167 
endgenerate // index==0
168 
genvar i;
169 
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
170 40 unneback 
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
171 6 unneback 
end
172 
endgenerate
173 
endmodule
174 
`endif
175 32 unneback 
///////////////////////////////////////////////////////////////////////////////
176 6 unneback 
 //actel
177 
//////////////////////////////////////////////////////////////////////
178 
////                                                              ////
179 
////  Versatile library, registers                                ////
180 
////                                                              ////
181 
////  Description                                                 ////
182 
////  Different type of registers                                 ////
183 
////                                                              ////
184 
////                                                              ////
185 
////  To Do:                                                      ////
186 
////   - add more different registers                             ////
187 
////                                                              ////
188 
////  Author(s):                                                  ////
189 
////      - Michael Unneback, unneback@opencores.org              ////
190 
////        ORSoC AB                                              ////
191 
////                                                              ////
192 
//////////////////////////////////////////////////////////////////////
193 
////                                                              ////
194 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
195 
////                                                              ////
196 
//// This source file may be used and distributed without         ////
197 
//// restriction provided that this copyright statement is not    ////
198 
//// removed from the file and that any derivative work contains  ////
199 
//// the original copyright notice and the associated disclaimer. ////
200 
////                                                              ////
201 
//// This source file is free software; you can redistribute it   ////
202 
//// and/or modify it under the terms of the GNU Lesser General   ////
203 
//// Public License as published by the Free Software Foundation; ////
204 
//// either version 2.1 of the License, or (at your option) any   ////
205 
//// later version.                                               ////
206 
////                                                              ////
207 
//// This source is distributed in the hope that it will be       ////
208 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
209 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
210 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
211 
//// details.                                                     ////
212 
////                                                              ////
213 
//// You should have received a copy of the GNU Lesser General    ////
214 
//// Public License along with this source; if not, download it   ////
215 
//// from http://www.opencores.org/lgpl.shtml                     ////
216 
////                                                              ////
217 
//////////////////////////////////////////////////////////////////////
218 18 unneback 
module vl_dff ( d, q, clk, rst);
219 6 unneback 
        parameter width = 1;
220 139 unneback 
        parameter reset_value = {width{1'b0}};
221 6 unneback 
        input [width-1:0] d;
222 
        input clk, rst;
223 
        output reg [width-1:0] q;
224 
        always @ (posedge clk or posedge rst)
225 
        if (rst)
226 
                q <= reset_value;
227 
        else
228 
                q <= d;
229 
endmodule
230 18 unneback 
module vl_dff_array ( d, q, clk, rst);
231 6 unneback 
        parameter width = 1;
232 
        parameter depth = 2;
233 
        parameter reset_value = 1'b0;
234 
        input [width-1:0] d;
235 
        input clk, rst;
236 
        output [width-1:0] q;
237 
        reg  [0:depth-1] q_tmp [width-1:0];
238 
        integer i;
239 
        always @ (posedge clk or posedge rst)
240 
        if (rst) begin
241 
            for (i=0;i<depth;i=i+1)
242 
                q_tmp[i] <= {width{reset_value}};
243 
        end else begin
244 
            q_tmp[0] <= d;
245 
            for (i=1;i<depth;i=i+1)
246 
                q_tmp[i] <= q_tmp[i-1];
247 
        end
248 
    assign q = q_tmp[depth-1];
249 
endmodule
250 18 unneback 
module vl_dff_ce ( d, ce, q, clk, rst);
251 6 unneback 
        parameter width = 1;
252 139 unneback 
        parameter reset_value = {width{1'b0}};
253 6 unneback 
        input [width-1:0] d;
254 
        input ce, clk, rst;
255 
        output reg [width-1:0] q;
256 
        always @ (posedge clk or posedge rst)
257 
        if (rst)
258 
                q <= reset_value;
259 
        else
260 
                if (ce)
261 
                        q <= d;
262 
endmodule
263 18 unneback 
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
264 8 unneback 
        parameter width = 1;
265 139 unneback 
        parameter reset_value = {width{1'b0}};
266 8 unneback 
        input [width-1:0] d;
267 10 unneback 
        input ce, clear, clk, rst;
268 8 unneback 
        output reg [width-1:0] q;
269 
        always @ (posedge clk or posedge rst)
270 
        if (rst)
271 
            q <= reset_value;
272 
        else
273 
            if (ce)
274 
                if (clear)
275 
                    q <= {width{1'b0}};
276 
                else
277 
                    q <= d;
278 
endmodule
279 24 unneback 
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
280 
        parameter width = 1;
281 139 unneback 
        parameter reset_value = {width{1'b0}};
282 24 unneback 
        input [width-1:0] d;
283 
        input ce, set, clk, rst;
284 
        output reg [width-1:0] q;
285 
        always @ (posedge clk or posedge rst)
286 
        if (rst)
287 
            q <= reset_value;
288 
        else
289 
            if (ce)
290 
                if (set)
291 
                    q <= {width{1'b1}};
292 
                else
293 
                    q <= d;
294 
endmodule
295 29 unneback 
module vl_spr ( sp, r, q, clk, rst);
296 64 unneback 
        //parameter width = 1;
297 
        parameter reset_value = 1'b0;
298 29 unneback 
        input sp, r;
299 
        output reg q;
300 
        input clk, rst;
301 
        always @ (posedge clk or posedge rst)
302 
        if (rst)
303 
            q <= reset_value;
304 
        else
305 
            if (sp)
306 
                q <= 1'b1;
307 
            else if (r)
308 
                q <= 1'b0;
309 
endmodule
310 
module vl_srp ( s, rp, q, clk, rst);
311 
        parameter width = 1;
312 
        parameter reset_value = 0;
313 
        input s, rp;
314 
        output reg q;
315 
        input clk, rst;
316 
        always @ (posedge clk or posedge rst)
317 
        if (rst)
318 
            q <= reset_value;
319 
        else
320 
            if (rp)
321 
                q <= 1'b0;
322 
            else if (s)
323 
                q <= 1'b1;
324 
endmodule
325 18 unneback 
module vl_dff_sr ( aclr, aset, clock, data, q);
326 6 unneback 
    input         aclr;
327 
    input         aset;
328 
    input         clock;
329 
    input         data;
330 
    output reg    q;
331 
   always @ (posedge clock or posedge aclr or posedge aset)
332 
     if (aclr)
333 
       q <= 1'b0;
334 
     else if (aset)
335 
       q <= 1'b1;
336 
     else
337 
       q <= data;
338 
endmodule
339 
// LATCH
340 
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
341 40 unneback 
module vl_latch ( d, le, q, clk);
342 6 unneback 
input d, le;
343 48 unneback 
input clk;
344 
always @ (le or d)
345 60 unneback 
if (le)
346 48 unneback 
    d <= q;
347 6 unneback 
endmodule
348 18 unneback 
module vl_shreg ( d, q, clk, rst);
349 17 unneback 
parameter depth = 10;
350 
input d;
351 
output q;
352 
input clk, rst;
353 
reg [1:depth] dffs;
354 
always @ (posedge clk or posedge rst)
355 
if (rst)
356 
    dffs <= {depth{1'b0}};
357 
else
358 
    dffs <= {d,dffs[1:depth-1]};
359 
assign q = dffs[depth];
360 
endmodule
361 18 unneback 
module vl_shreg_ce ( d, ce, q, clk, rst);
362 17 unneback 
parameter depth = 10;
363 
input d, ce;
364 
output q;
365 
input clk, rst;
366 
reg [1:depth] dffs;
367 
always @ (posedge clk or posedge rst)
368 
if (rst)
369 
    dffs <= {depth{1'b0}};
370 
else
371 
    if (ce)
372 
        dffs <= {d,dffs[1:depth-1]};
373 
assign q = dffs[depth];
374 
endmodule
375 18 unneback 
module vl_delay ( d, q, clk, rst);
376 15 unneback 
parameter depth = 10;
377 
input d;
378 
output q;
379 
input clk, rst;
380 
reg [1:depth] dffs;
381 
always @ (posedge clk or posedge rst)
382 
if (rst)
383 
    dffs <= {depth{1'b0}};
384 
else
385 
    dffs <= {d,dffs[1:depth-1]};
386 
assign q = dffs[depth];
387 
endmodule
388 18 unneback 
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
389 17 unneback 
parameter depth = 10;
390 
input d;
391 
output q, emptyflag;
392 
input clk, rst;
393 
reg [1:depth] dffs;
394 
always @ (posedge clk or posedge rst)
395 
if (rst)
396 
    dffs <= {depth{1'b0}};
397 
else
398 
    dffs <= {d,dffs[1:depth-1]};
399 
assign q = dffs[depth];
400 
assign emptyflag = !(|dffs);
401 
endmodule
402 98 unneback 
module vl_pulse2toggle ( pl, q, clk, rst);
403 94 unneback 
input pl;
404 98 unneback 
output reg q;
405 94 unneback 
input clk, rst;
406 
always @ (posedge clk or posedge rst)
407 
if (rst)
408 
    q <= 1'b0;
409 
else
410 
    q <= pl ^ q;
411 
endmodule
412 98 unneback 
module vl_toggle2pulse (d, pl, clk, rst);
413 94 unneback 
input d;
414 
output pl;
415 
input clk, rst;
416 
reg dff;
417 
always @ (posedge clk or posedge rst)
418 
if (rst)
419 
    dff <= 1'b0;
420 
else
421 
    dff <= d;
422 98 unneback 
assign pl = d ^ dff;
423 94 unneback 
endmodule
424 
module vl_synchronizer (d, q, clk, rst);
425 
input d;
426 
output reg q;
427 116 unneback 
input clk, rst;
428 94 unneback 
reg dff;
429 
always @ (posedge clk or posedge rst)
430 
if (rst)
431 100 unneback 
    {q,dff} <= 2'b00;
432 94 unneback 
else
433 100 unneback 
    {q,dff} <= {dff,d};
434 94 unneback 
endmodule
435 97 unneback 
module vl_cdc ( start_pl, take_it_pl, take_it_grant_pl, got_it_pl, clk_src, rst_src, clk_dst, rst_dst);
436 94 unneback 
input start_pl;
437 
output take_it_pl;
438 
input take_it_grant_pl; // note: connect to take_it_pl to generate automatic ack
439 
output got_it_pl;
440 
input clk_src, rst_src;
441 
input clk_dst, rst_dst;
442 
wire take_it_tg, take_it_tg_sync;
443 
wire got_it_tg, got_it_tg_sync;
444 
// src -> dst
445 
vl_pulse2toggle p2t0 (
446 
    .pl(start_pl),
447 
    .q(take_it_tg),
448 
    .clk(clk_src),
449 
    .rst(rst_src));
450 
vl_synchronizer sync0 (
451 
    .d(take_it_tg),
452 
    .q(take_it_tg_sync),
453 
    .clk(clk_dst),
454 
    .rst(rst_dst));
455 
vl_toggle2pulse t2p0 (
456 100 unneback 
    .d(take_it_tg_sync),
457 94 unneback 
    .pl(take_it_pl),
458 
    .clk(clk_dst),
459 
    .rst(rst_dst));
460 
// dst -> src
461 98 unneback 
vl_pulse2toggle p2t1 (
462 94 unneback 
    .pl(take_it_grant_pl),
463 
    .q(got_it_tg),
464 
    .clk(clk_dst),
465 
    .rst(rst_dst));
466 
vl_synchronizer sync1 (
467 
    .d(got_it_tg),
468 
    .q(got_it_tg_sync),
469 
    .clk(clk_src),
470 
    .rst(rst_src));
471 
vl_toggle2pulse t2p1 (
472 100 unneback 
    .d(got_it_tg_sync),
473 94 unneback 
    .pl(got_it_pl),
474 
    .clk(clk_src),
475 
    .rst(rst_src));
476 
endmodule
477 6 unneback 
//////////////////////////////////////////////////////////////////////
478 
////                                                              ////
479 18 unneback 
////  Logic functions                                             ////
480 
////                                                              ////
481 
////  Description                                                 ////
482 
////  Logic functions such as multiplexers                        ////
483 
////                                                              ////
484 
////                                                              ////
485 
////  To Do:                                                      ////
486 
////   -                                                          ////
487 
////                                                              ////
488 
////  Author(s):                                                  ////
489 
////      - Michael Unneback, unneback@opencores.org              ////
490 
////        ORSoC AB                                              ////
491 
////                                                              ////
492 
//////////////////////////////////////////////////////////////////////
493 
////                                                              ////
494 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
495 
////                                                              ////
496 
//// This source file may be used and distributed without         ////
497 
//// restriction provided that this copyright statement is not    ////
498 
//// removed from the file and that any derivative work contains  ////
499 
//// the original copyright notice and the associated disclaimer. ////
500 
////                                                              ////
501 
//// This source file is free software; you can redistribute it   ////
502 
//// and/or modify it under the terms of the GNU Lesser General   ////
503 
//// Public License as published by the Free Software Foundation; ////
504 
//// either version 2.1 of the License, or (at your option) any   ////
505 
//// later version.                                               ////
506 
////                                                              ////
507 
//// This source is distributed in the hope that it will be       ////
508 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
509 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
510 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
511 
//// details.                                                     ////
512 
////                                                              ////
513 
//// You should have received a copy of the GNU Lesser General    ////
514 
//// Public License along with this source; if not, download it   ////
515 
//// from http://www.opencores.org/lgpl.shtml                     ////
516 
////                                                              ////
517 
//////////////////////////////////////////////////////////////////////
518 36 unneback 
module vl_mux_andor ( a, sel, dout);
519 
parameter width = 32;
520 
parameter nr_of_ports = 4;
521 
input [nr_of_ports*width-1:0] a;
522 
input [nr_of_ports-1:0] sel;
523 
output reg [width-1:0] dout;
524 38 unneback 
integer i,j;
525 36 unneback 
always @ (a, sel)
526 
begin
527 
    dout = a[width-1:0] & {width{sel[0]}};
528 42 unneback 
    for (i=1;i<nr_of_ports;i=i+1)
529 
        for (j=0;j<width;j=j+1)
530 
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
531 36 unneback 
end
532 
endmodule
533 34 unneback 
module vl_mux2_andor ( a1, a0, sel, dout);
534 
parameter width = 32;
535 35 unneback 
localparam nr_of_ports = 2;
536 34 unneback 
input [width-1:0] a1, a0;
537 
input [nr_of_ports-1:0] sel;
538 
output [width-1:0] dout;
539 36 unneback 
vl_mux_andor
540 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
541 36 unneback 
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
542 34 unneback 
endmodule
543 
module vl_mux3_andor ( a2, a1, a0, sel, dout);
544 
parameter width = 32;
545 35 unneback 
localparam nr_of_ports = 3;
546 34 unneback 
input [width-1:0] a2, a1, a0;
547 
input [nr_of_ports-1:0] sel;
548 
output [width-1:0] dout;
549 36 unneback 
vl_mux_andor
550 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
551 36 unneback 
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
552 34 unneback 
endmodule
553 18 unneback 
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
554 
parameter width = 32;
555 35 unneback 
localparam nr_of_ports = 4;
556 18 unneback 
input [width-1:0] a3, a2, a1, a0;
557 
input [nr_of_ports-1:0] sel;
558 22 unneback 
output [width-1:0] dout;
559 36 unneback 
vl_mux_andor
560 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
561 36 unneback 
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
562 18 unneback 
endmodule
563 
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
564 
parameter width = 32;
565 35 unneback 
localparam nr_of_ports = 5;
566 18 unneback 
input [width-1:0] a4, a3, a2, a1, a0;
567 
input [nr_of_ports-1:0] sel;
568 22 unneback 
output [width-1:0] dout;
569 36 unneback 
vl_mux_andor
570 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
571 36 unneback 
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
572 18 unneback 
endmodule
573 
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
574 
parameter width = 32;
575 35 unneback 
localparam nr_of_ports = 6;
576 18 unneback 
input [width-1:0] a5, a4, a3, a2, a1, a0;
577 
input [nr_of_ports-1:0] sel;
578 22 unneback 
output [width-1:0] dout;
579 36 unneback 
vl_mux_andor
580 38 unneback 
    # ( .width(width), .nr_of_ports(nr_of_ports))
581 36 unneback 
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
582 18 unneback 
endmodule
583 43 unneback 
module vl_parity_generate (data, parity);
584 
parameter word_size = 32;
585 
parameter chunk_size = 8;
586 
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
587 
input [word_size-1:0] data;
588 
output reg [word_size/chunk_size-1:0] parity;
589 
integer i,j;
590 
always @ (data)
591 
for (i=0;i<word_size/chunk_size;i=i+1) begin
592 
    parity[i] = parity_type;
593 
    for (j=0;j<chunk_size;j=j+1) begin
594 46 unneback 
        parity[i] = data[i*chunk_size+j] ^ parity[i];
595 43 unneback 
    end
596 
end
597 
endmodule
598 
module vl_parity_check( data, parity, parity_error);
599 
parameter word_size = 32;
600 
parameter chunk_size = 8;
601 
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
602 
input [word_size-1:0] data;
603 
input [word_size/chunk_size-1:0] parity;
604 
output parity_error;
605 44 unneback 
reg [word_size/chunk_size-1:0] error_flag;
606 43 unneback 
integer i,j;
607 
always @ (data or parity)
608 
for (i=0;i<word_size/chunk_size;i=i+1) begin
609 
    error_flag[i] = parity[i] ^ parity_type;
610 
    for (j=0;j<chunk_size;j=j+1) begin
611 46 unneback 
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
612 43 unneback 
    end
613 
end
614 
assign parity_error = |error_flag;
615 
endmodule
616 18 unneback 
//////////////////////////////////////////////////////////////////////
617 
////                                                              ////
618 44 unneback 
////  IO functions                                                ////
619 
////                                                              ////
620 
////  Description                                                 ////
621 
////  IO functions such as IOB flip-flops                         ////
622 
////                                                              ////
623 
////                                                              ////
624 
////  To Do:                                                      ////
625 
////   -                                                          ////
626 
////                                                              ////
627 
////  Author(s):                                                  ////
628 
////      - Michael Unneback, unneback@opencores.org              ////
629 
////        ORSoC AB                                              ////
630 
////                                                              ////
631 
//////////////////////////////////////////////////////////////////////
632 
////                                                              ////
633 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
634 
////                                                              ////
635 
//// This source file may be used and distributed without         ////
636 
//// restriction provided that this copyright statement is not    ////
637 
//// removed from the file and that any derivative work contains  ////
638 
//// the original copyright notice and the associated disclaimer. ////
639 
////                                                              ////
640 
//// This source file is free software; you can redistribute it   ////
641 
//// and/or modify it under the terms of the GNU Lesser General   ////
642 
//// Public License as published by the Free Software Foundation; ////
643 
//// either version 2.1 of the License, or (at your option) any   ////
644 
//// later version.                                               ////
645 
////                                                              ////
646 
//// This source is distributed in the hope that it will be       ////
647 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
648 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
649 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
650 
//// details.                                                     ////
651 
////                                                              ////
652 
//// You should have received a copy of the GNU Lesser General    ////
653 
//// Public License along with this source; if not, download it   ////
654 
//// from http://www.opencores.org/lgpl.shtml                     ////
655 
////                                                              ////
656 
//////////////////////////////////////////////////////////////////////
657 45 unneback 
`timescale 1ns/1ns
658 44 unneback 
module vl_o_dff (d_i, o_pad, clk, rst);
659 
parameter width = 1;
660 45 unneback 
parameter reset_value = {width{1'b0}};
661 
input  [width-1:0]  d_i;
662 44 unneback 
output [width-1:0] o_pad;
663 
input clk, rst;
664 
wire [width-1:0] d_i_int /*synthesis syn_keep = 1*/;
665 45 unneback 
reg  [width-1:0] o_pad_int;
666 44 unneback 
assign d_i_int = d_i;
667 
genvar i;
668 45 unneback 
generate
669 136 unneback 
for (i=0;i<width;i=i+1) begin : dffs
670 44 unneback 
    always @ (posedge clk or posedge rst)
671 
    if (rst)
672 45 unneback 
        o_pad_int[i] <= reset_value[i];
673 44 unneback 
    else
674 45 unneback 
        o_pad_int[i] <= d_i_int[i];
675 
    assign #1 o_pad[i] = o_pad_int[i];
676 44 unneback 
end
677 
endgenerate
678 
endmodule
679 45 unneback 
`timescale 1ns/1ns
680 44 unneback 
module vl_io_dff_oe ( d_i, d_o, oe, io_pad, clk, rst);
681 
parameter width = 1;
682 
input  [width-1:0] d_o;
683 
output reg [width-1:0] d_i;
684 
input oe;
685 
inout [width-1:0] io_pad;
686 
input clk, rst;
687 
wire [width-1:0] oe_d /*synthesis syn_keep = 1*/;
688 
reg [width-1:0] oe_q;
689 
reg [width-1:0] d_o_q;
690 
assign oe_d = {width{oe}};
691 
genvar i;
692 
generate
693 136 unneback 
for (i=0;i<width;i=i+1) begin : dffs
694 44 unneback 
    always @ (posedge clk or posedge rst)
695 
    if (rst)
696 
        oe_q[i] <= 1'b0;
697 
    else
698 
        oe_q[i] <= oe_d[i];
699 
    always @ (posedge clk or posedge rst)
700 
    if (rst)
701 
        d_o_q[i] <= 1'b0;
702 
    else
703 
        d_o_q[i] <= d_o[i];
704 
    always @ (posedge clk or posedge rst)
705 
    if (rst)
706 
        d_i[i] <= 1'b0;
707 
    else
708 
        d_i[i] <= io_pad[i];
709 45 unneback 
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
710 44 unneback 
end
711 
endgenerate
712 
endmodule
713 136 unneback 
module vl_o_ddr (d_h_i, d_l_i, o_pad, clk, rst);
714 
parameter width = 1;
715 
input  [width-1:0] d_h_i, d_l_i;
716 
output [width-1:0] o_pad;
717 
input clk, rst;
718 
reg [width-1:0] ff1;
719 
reg [width-1:0] ff2;
720 
genvar i;
721 
generate
722 
for (i=0;i<width;i=i+1) begin : ddr
723 
    always @ (posedge clk or posedge rst)
724 
    if (rst)
725 
        ff1[i] <= 1'b0;
726 
    else
727 
        ff1[i] <= d_h_i[i];
728 
    always @ (posedge clk or posedge rst)
729 
    if (rst)
730 
        ff2[i] <= 1'b0;
731 
    else
732 
        ff2[i] <= d_l_i[i];
733 
    assign o_pad = (clk) ? ff1 : ff2;
734 
end
735 
endgenerate
736 
endmodule
737 
module vl_o_clk ( clk_o_pad, clk, rst);
738 
input clk, rst;
739 
output clk_o_pad;
740 
vl_o_ddr o_ddr0( .d_h_i(1'b1), .d_l_i(1'b0), .o_pad(clk_o_pad), .clk(clk), .rst(rst));
741 
endmodule
742 44 unneback 
//////////////////////////////////////////////////////////////////////
743 
////                                                              ////
744 6 unneback 
////  Versatile counter                                           ////
745 
////                                                              ////
746 
////  Description                                                 ////
747 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
748 
////  counter                                                     ////
749 
////                                                              ////
750 
////  To Do:                                                      ////
751 
////   - add LFSR with more taps                                  ////
752 
////                                                              ////
753 
////  Author(s):                                                  ////
754 
////      - Michael Unneback, unneback@opencores.org              ////
755 
////        ORSoC AB                                              ////
756 
////                                                              ////
757 
//////////////////////////////////////////////////////////////////////
758 
////                                                              ////
759 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
760 
////                                                              ////
761 
//// This source file may be used and distributed without         ////
762 
//// restriction provided that this copyright statement is not    ////
763 
//// removed from the file and that any derivative work contains  ////
764 
//// the original copyright notice and the associated disclaimer. ////
765 
////                                                              ////
766 
//// This source file is free software; you can redistribute it   ////
767 
//// and/or modify it under the terms of the GNU Lesser General   ////
768 
//// Public License as published by the Free Software Foundation; ////
769 
//// either version 2.1 of the License, or (at your option) any   ////
770 
//// later version.                                               ////
771 
////                                                              ////
772 
//// This source is distributed in the hope that it will be       ////
773 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
774 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
775 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
776 
//// details.                                                     ////
777 
////                                                              ////
778 
//// You should have received a copy of the GNU Lesser General    ////
779 
//// Public License along with this source; if not, download it   ////
780 
//// from http://www.opencores.org/lgpl.shtml                     ////
781 
////                                                              ////
782 
//////////////////////////////////////////////////////////////////////
783 
// binary counter
784 139 unneback 
module vl_cnt_bin (
785 
 q, rst, clk);
786 
   parameter length = 4;
787 
   output [length:1] q;
788 
   input rst;
789 
   input clk;
790 
   parameter clear_value = 0;
791 
   parameter set_value = 1;
792 
   parameter wrap_value = 0;
793 
   parameter level1_value = 15;
794 
   reg  [length:1] qi;
795 
   wire [length:1] q_next;
796 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
797 
   always @ (posedge clk or posedge rst)
798 
     if (rst)
799 
       qi <= {length{1'b0}};
800 
     else
801 
       qi <= q_next;
802 
   assign q = qi;
803 
endmodule
804 
//////////////////////////////////////////////////////////////////////
805 
////                                                              ////
806 
////  Versatile counter                                           ////
807 
////                                                              ////
808 
////  Description                                                 ////
809 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
810 
////  counter                                                     ////
811 
////                                                              ////
812 
////  To Do:                                                      ////
813 
////   - add LFSR with more taps                                  ////
814 
////                                                              ////
815 
////  Author(s):                                                  ////
816 
////      - Michael Unneback, unneback@opencores.org              ////
817 
////        ORSoC AB                                              ////
818 
////                                                              ////
819 
//////////////////////////////////////////////////////////////////////
820 
////                                                              ////
821 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
822 
////                                                              ////
823 
//// This source file may be used and distributed without         ////
824 
//// restriction provided that this copyright statement is not    ////
825 
//// removed from the file and that any derivative work contains  ////
826 
//// the original copyright notice and the associated disclaimer. ////
827 
////                                                              ////
828 
//// This source file is free software; you can redistribute it   ////
829 
//// and/or modify it under the terms of the GNU Lesser General   ////
830 
//// Public License as published by the Free Software Foundation; ////
831 
//// either version 2.1 of the License, or (at your option) any   ////
832 
//// later version.                                               ////
833 
////                                                              ////
834 
//// This source is distributed in the hope that it will be       ////
835 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
836 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
837 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
838 
//// details.                                                     ////
839 
////                                                              ////
840 
//// You should have received a copy of the GNU Lesser General    ////
841 
//// Public License along with this source; if not, download it   ////
842 
//// from http://www.opencores.org/lgpl.shtml                     ////
843 
////                                                              ////
844 
//////////////////////////////////////////////////////////////////////
845 
// binary counter
846 
module vl_cnt_bin_clear (
847 
 clear, q, rst, clk);
848 
   parameter length = 4;
849 
   input clear;
850 
   output [length:1] q;
851 
   input rst;
852 
   input clk;
853 
   parameter clear_value = 0;
854 
   parameter set_value = 1;
855 
   parameter wrap_value = 0;
856 
   parameter level1_value = 15;
857 
   reg  [length:1] qi;
858 
   wire [length:1] q_next;
859 
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
860 
   always @ (posedge clk or posedge rst)
861 
     if (rst)
862 
       qi <= {length{1'b0}};
863 
     else
864 
       qi <= q_next;
865 
   assign q = qi;
866 
endmodule
867 
//////////////////////////////////////////////////////////////////////
868 
////                                                              ////
869 
////  Versatile counter                                           ////
870 
////                                                              ////
871 
////  Description                                                 ////
872 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
873 
////  counter                                                     ////
874 
////                                                              ////
875 
////  To Do:                                                      ////
876 
////   - add LFSR with more taps                                  ////
877 
////                                                              ////
878 
////  Author(s):                                                  ////
879 
////      - Michael Unneback, unneback@opencores.org              ////
880 
////        ORSoC AB                                              ////
881 
////                                                              ////
882 
//////////////////////////////////////////////////////////////////////
883 
////                                                              ////
884 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
885 
////                                                              ////
886 
//// This source file may be used and distributed without         ////
887 
//// restriction provided that this copyright statement is not    ////
888 
//// removed from the file and that any derivative work contains  ////
889 
//// the original copyright notice and the associated disclaimer. ////
890 
////                                                              ////
891 
//// This source file is free software; you can redistribute it   ////
892 
//// and/or modify it under the terms of the GNU Lesser General   ////
893 
//// Public License as published by the Free Software Foundation; ////
894 
//// either version 2.1 of the License, or (at your option) any   ////
895 
//// later version.                                               ////
896 
////                                                              ////
897 
//// This source is distributed in the hope that it will be       ////
898 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
899 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
900 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
901 
//// details.                                                     ////
902 
////                                                              ////
903 
//// You should have received a copy of the GNU Lesser General    ////
904 
//// Public License along with this source; if not, download it   ////
905 
//// from http://www.opencores.org/lgpl.shtml                     ////
906 
////                                                              ////
907 
//////////////////////////////////////////////////////////////////////
908 
// binary counter
909 40 unneback 
module vl_cnt_bin_ce (
910 
 cke, q, rst, clk);
911 22 unneback 
   parameter length = 4;
912 6 unneback 
   input cke;
913 
   output [length:1] q;
914 
   input rst;
915 
   input clk;
916 
   parameter clear_value = 0;
917 
   parameter set_value = 1;
918 
   parameter wrap_value = 0;
919 
   parameter level1_value = 15;
920 
   reg  [length:1] qi;
921 
   wire [length:1] q_next;
922 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
923 
   always @ (posedge clk or posedge rst)
924 
     if (rst)
925 
       qi <= {length{1'b0}};
926 
     else
927 
     if (cke)
928 
       qi <= q_next;
929 
   assign q = qi;
930 
endmodule
931 
//////////////////////////////////////////////////////////////////////
932 
////                                                              ////
933 
////  Versatile counter                                           ////
934 
////                                                              ////
935 
////  Description                                                 ////
936 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
937 
////  counter                                                     ////
938 
////                                                              ////
939 
////  To Do:                                                      ////
940 
////   - add LFSR with more taps                                  ////
941 
////                                                              ////
942 
////  Author(s):                                                  ////
943 
////      - Michael Unneback, unneback@opencores.org              ////
944 
////        ORSoC AB                                              ////
945 
////                                                              ////
946 
//////////////////////////////////////////////////////////////////////
947 
////                                                              ////
948 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
949 
////                                                              ////
950 
//// This source file may be used and distributed without         ////
951 
//// restriction provided that this copyright statement is not    ////
952 
//// removed from the file and that any derivative work contains  ////
953 
//// the original copyright notice and the associated disclaimer. ////
954 
////                                                              ////
955 
//// This source file is free software; you can redistribute it   ////
956 
//// and/or modify it under the terms of the GNU Lesser General   ////
957 
//// Public License as published by the Free Software Foundation; ////
958 
//// either version 2.1 of the License, or (at your option) any   ////
959 
//// later version.                                               ////
960 
////                                                              ////
961 
//// This source is distributed in the hope that it will be       ////
962 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
963 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
964 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
965 
//// details.                                                     ////
966 
////                                                              ////
967 
//// You should have received a copy of the GNU Lesser General    ////
968 
//// Public License along with this source; if not, download it   ////
969 
//// from http://www.opencores.org/lgpl.shtml                     ////
970 
////                                                              ////
971 
//////////////////////////////////////////////////////////////////////
972 
// binary counter
973 139 unneback 
module vl_cnt_bin_ce_clear (
974 
 clear, cke, q, rst, clk);
975 
   parameter length = 4;
976 
   input clear;
977 
   input cke;
978 
   output [length:1] q;
979 
   input rst;
980 
   input clk;
981 
   parameter clear_value = 0;
982 
   parameter set_value = 1;
983 
   parameter wrap_value = 0;
984 
   parameter level1_value = 15;
985 
   reg  [length:1] qi;
986 
   wire [length:1] q_next;
987 
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
988 
   always @ (posedge clk or posedge rst)
989 
     if (rst)
990 
       qi <= {length{1'b0}};
991 
     else
992 
     if (cke)
993 
       qi <= q_next;
994 
   assign q = qi;
995 
endmodule
996 
//////////////////////////////////////////////////////////////////////
997 
////                                                              ////
998 
////  Versatile counter                                           ////
999 
////                                                              ////
1000 
////  Description                                                 ////
1001 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1002 
////  counter                                                     ////
1003 
////                                                              ////
1004 
////  To Do:                                                      ////
1005 
////   - add LFSR with more taps                                  ////
1006 
////                                                              ////
1007 
////  Author(s):                                                  ////
1008 
////      - Michael Unneback, unneback@opencores.org              ////
1009 
////        ORSoC AB                                              ////
1010 
////                                                              ////
1011 
//////////////////////////////////////////////////////////////////////
1012 
////                                                              ////
1013 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1014 
////                                                              ////
1015 
//// This source file may be used and distributed without         ////
1016 
//// restriction provided that this copyright statement is not    ////
1017 
//// removed from the file and that any derivative work contains  ////
1018 
//// the original copyright notice and the associated disclaimer. ////
1019 
////                                                              ////
1020 
//// This source file is free software; you can redistribute it   ////
1021 
//// and/or modify it under the terms of the GNU Lesser General   ////
1022 
//// Public License as published by the Free Software Foundation; ////
1023 
//// either version 2.1 of the License, or (at your option) any   ////
1024 
//// later version.                                               ////
1025 
////                                                              ////
1026 
//// This source is distributed in the hope that it will be       ////
1027 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1028 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1029 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1030 
//// details.                                                     ////
1031 
////                                                              ////
1032 
//// You should have received a copy of the GNU Lesser General    ////
1033 
//// Public License along with this source; if not, download it   ////
1034 
//// from http://www.opencores.org/lgpl.shtml                     ////
1035 
////                                                              ////
1036 
//////////////////////////////////////////////////////////////////////
1037 
// binary counter
1038 
module vl_cnt_bin_ce_clear_l1_l2 (
1039 
 clear, cke, q, level1, level2, rst, clk);
1040 
   parameter length = 4;
1041 
   input clear;
1042 
   input cke;
1043 
   output [length:1] q;
1044 
   output reg level1;
1045 
   output reg level2;
1046 
   input rst;
1047 
   input clk;
1048 
   parameter clear_value = 0;
1049 
   parameter set_value = 1;
1050 
   parameter wrap_value = 15;
1051 
   parameter level1_value = 8;
1052 
   parameter level2_value = 15;
1053 
   wire rew;
1054 
   assign rew = 1'b0;
1055 
   reg  [length:1] qi;
1056 
   wire [length:1] q_next;
1057 
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1058 
   always @ (posedge clk or posedge rst)
1059 
     if (rst)
1060 
       qi <= {length{1'b0}};
1061 
     else
1062 
     if (cke)
1063 
       qi <= q_next;
1064 
   assign q = qi;
1065 
    always @ (posedge clk or posedge rst)
1066 
    if (rst)
1067 
        level1 <= 1'b0;
1068 
    else
1069 
    if (cke)
1070 
    if (clear)
1071 
        level1 <= 1'b0;
1072 
    else if (q_next == level1_value)
1073 
        level1 <= 1'b1;
1074 
    else if (qi == level1_value & rew)
1075 
        level1 <= 1'b0;
1076 
    always @ (posedge clk or posedge rst)
1077 
    if (rst)
1078 
        level2 <= 1'b0;
1079 
    else
1080 
    if (cke)
1081 
    if (clear)
1082 
        level2 <= 1'b0;
1083 
    else if (q_next == level2_value)
1084 
        level2 <= 1'b1;
1085 
    else if (qi == level2_value & rew)
1086 
        level2 <= 1'b0;
1087 
endmodule
1088 
//////////////////////////////////////////////////////////////////////
1089 
////                                                              ////
1090 
////  Versatile counter                                           ////
1091 
////                                                              ////
1092 
////  Description                                                 ////
1093 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1094 
////  counter                                                     ////
1095 
////                                                              ////
1096 
////  To Do:                                                      ////
1097 
////   - add LFSR with more taps                                  ////
1098 
////                                                              ////
1099 
////  Author(s):                                                  ////
1100 
////      - Michael Unneback, unneback@opencores.org              ////
1101 
////        ORSoC AB                                              ////
1102 
////                                                              ////
1103 
//////////////////////////////////////////////////////////////////////
1104 
////                                                              ////
1105 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1106 
////                                                              ////
1107 
//// This source file may be used and distributed without         ////
1108 
//// restriction provided that this copyright statement is not    ////
1109 
//// removed from the file and that any derivative work contains  ////
1110 
//// the original copyright notice and the associated disclaimer. ////
1111 
////                                                              ////
1112 
//// This source file is free software; you can redistribute it   ////
1113 
//// and/or modify it under the terms of the GNU Lesser General   ////
1114 
//// Public License as published by the Free Software Foundation; ////
1115 
//// either version 2.1 of the License, or (at your option) any   ////
1116 
//// later version.                                               ////
1117 
////                                                              ////
1118 
//// This source is distributed in the hope that it will be       ////
1119 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1120 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1121 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1122 
//// details.                                                     ////
1123 
////                                                              ////
1124 
//// You should have received a copy of the GNU Lesser General    ////
1125 
//// Public License along with this source; if not, download it   ////
1126 
//// from http://www.opencores.org/lgpl.shtml                     ////
1127 
////                                                              ////
1128 
//////////////////////////////////////////////////////////////////////
1129 
// binary counter
1130 
module vl_cnt_bin_ce_clear_set_rew (
1131 
 clear, set, cke, rew, q, rst, clk);
1132 
   parameter length = 4;
1133 
   input clear;
1134 
   input set;
1135 
   input cke;
1136 
   input rew;
1137 
   output [length:1] q;
1138 
   input rst;
1139 
   input clk;
1140 
   parameter clear_value = 0;
1141 
   parameter set_value = 1;
1142 
   parameter wrap_value = 0;
1143 
   parameter level1_value = 15;
1144 
   reg  [length:1] qi;
1145 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1146 
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
1147 
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
1148 
   assign q_next = rew ? q_next_rew : q_next_fw;
1149 
   always @ (posedge clk or posedge rst)
1150 
     if (rst)
1151 
       qi <= {length{1'b0}};
1152 
     else
1153 
     if (cke)
1154 
       qi <= q_next;
1155 
   assign q = qi;
1156 
endmodule
1157 
//////////////////////////////////////////////////////////////////////
1158 
////                                                              ////
1159 
////  Versatile counter                                           ////
1160 
////                                                              ////
1161 
////  Description                                                 ////
1162 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1163 
////  counter                                                     ////
1164 
////                                                              ////
1165 
////  To Do:                                                      ////
1166 
////   - add LFSR with more taps                                  ////
1167 
////                                                              ////
1168 
////  Author(s):                                                  ////
1169 
////      - Michael Unneback, unneback@opencores.org              ////
1170 
////        ORSoC AB                                              ////
1171 
////                                                              ////
1172 
//////////////////////////////////////////////////////////////////////
1173 
////                                                              ////
1174 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1175 
////                                                              ////
1176 
//// This source file may be used and distributed without         ////
1177 
//// restriction provided that this copyright statement is not    ////
1178 
//// removed from the file and that any derivative work contains  ////
1179 
//// the original copyright notice and the associated disclaimer. ////
1180 
////                                                              ////
1181 
//// This source file is free software; you can redistribute it   ////
1182 
//// and/or modify it under the terms of the GNU Lesser General   ////
1183 
//// Public License as published by the Free Software Foundation; ////
1184 
//// either version 2.1 of the License, or (at your option) any   ////
1185 
//// later version.                                               ////
1186 
////                                                              ////
1187 
//// This source is distributed in the hope that it will be       ////
1188 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1189 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1190 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1191 
//// details.                                                     ////
1192 
////                                                              ////
1193 
//// You should have received a copy of the GNU Lesser General    ////
1194 
//// Public License along with this source; if not, download it   ////
1195 
//// from http://www.opencores.org/lgpl.shtml                     ////
1196 
////                                                              ////
1197 
//////////////////////////////////////////////////////////////////////
1198 
// binary counter
1199 
module vl_cnt_bin_ce_rew_l1 (
1200 
 cke, rew, level1, rst, clk);
1201 
   parameter length = 4;
1202 
   input cke;
1203 
   input rew;
1204 
   output reg level1;
1205 
   input rst;
1206 
   input clk;
1207 
   parameter clear_value = 0;
1208 
   parameter set_value = 1;
1209 
   parameter wrap_value = 1;
1210 
   parameter level1_value = 15;
1211 
   wire clear;
1212 
   assign clear = 1'b0;
1213 
   reg  [length:1] qi;
1214 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1215 
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1216 
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1217 
   assign q_next = rew ? q_next_rew : q_next_fw;
1218 
   always @ (posedge clk or posedge rst)
1219 
     if (rst)
1220 
       qi <= {length{1'b0}};
1221 
     else
1222 
     if (cke)
1223 
       qi <= q_next;
1224 
    always @ (posedge clk or posedge rst)
1225 
    if (rst)
1226 
        level1 <= 1'b0;
1227 
    else
1228 
    if (cke)
1229 
    if (clear)
1230 
        level1 <= 1'b0;
1231 
    else if (q_next == level1_value)
1232 
        level1 <= 1'b1;
1233 
    else if (qi == level1_value & rew)
1234 
        level1 <= 1'b0;
1235 
endmodule
1236 
//////////////////////////////////////////////////////////////////////
1237 
////                                                              ////
1238 
////  Versatile counter                                           ////
1239 
////                                                              ////
1240 
////  Description                                                 ////
1241 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1242 
////  counter                                                     ////
1243 
////                                                              ////
1244 
////  To Do:                                                      ////
1245 
////   - add LFSR with more taps                                  ////
1246 
////                                                              ////
1247 
////  Author(s):                                                  ////
1248 
////      - Michael Unneback, unneback@opencores.org              ////
1249 
////        ORSoC AB                                              ////
1250 
////                                                              ////
1251 
//////////////////////////////////////////////////////////////////////
1252 
////                                                              ////
1253 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1254 
////                                                              ////
1255 
//// This source file may be used and distributed without         ////
1256 
//// restriction provided that this copyright statement is not    ////
1257 
//// removed from the file and that any derivative work contains  ////
1258 
//// the original copyright notice and the associated disclaimer. ////
1259 
////                                                              ////
1260 
//// This source file is free software; you can redistribute it   ////
1261 
//// and/or modify it under the terms of the GNU Lesser General   ////
1262 
//// Public License as published by the Free Software Foundation; ////
1263 
//// either version 2.1 of the License, or (at your option) any   ////
1264 
//// later version.                                               ////
1265 
////                                                              ////
1266 
//// This source is distributed in the hope that it will be       ////
1267 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1268 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1269 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1270 
//// details.                                                     ////
1271 
////                                                              ////
1272 
//// You should have received a copy of the GNU Lesser General    ////
1273 
//// Public License along with this source; if not, download it   ////
1274 
//// from http://www.opencores.org/lgpl.shtml                     ////
1275 
////                                                              ////
1276 
//////////////////////////////////////////////////////////////////////
1277 
// binary counter
1278 40 unneback 
module vl_cnt_bin_ce_rew_zq_l1 (
1279 
 cke, rew, zq, level1, rst, clk);
1280 6 unneback 
   parameter length = 4;
1281 
   input cke;
1282 
   input rew;
1283 25 unneback 
   output reg zq;
1284 
   output reg level1;
1285 
   input rst;
1286 
   input clk;
1287 
   parameter clear_value = 0;
1288 
   parameter set_value = 1;
1289 
   parameter wrap_value = 1;
1290 
   parameter level1_value = 15;
1291 29 unneback 
   wire clear;
1292 30 unneback 
   assign clear = 1'b0;
1293 25 unneback 
   reg  [length:1] qi;
1294 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1295 
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1296 
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1297 
   assign q_next = rew ? q_next_rew : q_next_fw;
1298 
   always @ (posedge clk or posedge rst)
1299 
     if (rst)
1300 
       qi <= {length{1'b0}};
1301 
     else
1302 
     if (cke)
1303 
       qi <= q_next;
1304 
   always @ (posedge clk or posedge rst)
1305 
     if (rst)
1306 
       zq <= 1'b1;
1307 
     else
1308 
     if (cke)
1309 
       zq <= q_next == {length{1'b0}};
1310 
    always @ (posedge clk or posedge rst)
1311 
    if (rst)
1312 
        level1 <= 1'b0;
1313 
    else
1314 
    if (cke)
1315 29 unneback 
    if (clear)
1316 
        level1 <= 1'b0;
1317 
    else if (q_next == level1_value)
1318 25 unneback 
        level1 <= 1'b1;
1319 
    else if (qi == level1_value & rew)
1320 
        level1 <= 1'b0;
1321 
endmodule
1322 
//////////////////////////////////////////////////////////////////////
1323 
////                                                              ////
1324 
////  Versatile counter                                           ////
1325 
////                                                              ////
1326 
////  Description                                                 ////
1327 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1328 
////  counter                                                     ////
1329 
////                                                              ////
1330 
////  To Do:                                                      ////
1331 
////   - add LFSR with more taps                                  ////
1332 
////                                                              ////
1333 
////  Author(s):                                                  ////
1334 
////      - Michael Unneback, unneback@opencores.org              ////
1335 
////        ORSoC AB                                              ////
1336 
////                                                              ////
1337 
//////////////////////////////////////////////////////////////////////
1338 
////                                                              ////
1339 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1340 
////                                                              ////
1341 
//// This source file may be used and distributed without         ////
1342 
//// restriction provided that this copyright statement is not    ////
1343 
//// removed from the file and that any derivative work contains  ////
1344 
//// the original copyright notice and the associated disclaimer. ////
1345 
////                                                              ////
1346 
//// This source file is free software; you can redistribute it   ////
1347 
//// and/or modify it under the terms of the GNU Lesser General   ////
1348 
//// Public License as published by the Free Software Foundation; ////
1349 
//// either version 2.1 of the License, or (at your option) any   ////
1350 
//// later version.                                               ////
1351 
////                                                              ////
1352 
//// This source is distributed in the hope that it will be       ////
1353 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1354 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1355 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1356 
//// details.                                                     ////
1357 
////                                                              ////
1358 
//// You should have received a copy of the GNU Lesser General    ////
1359 
//// Public License along with this source; if not, download it   ////
1360 
//// from http://www.opencores.org/lgpl.shtml                     ////
1361 
////                                                              ////
1362 
//////////////////////////////////////////////////////////////////////
1363 
// binary counter
1364 40 unneback 
module vl_cnt_bin_ce_rew_q_zq_l1 (
1365 
 cke, rew, q, zq, level1, rst, clk);
1366 25 unneback 
   parameter length = 4;
1367 
   input cke;
1368 
   input rew;
1369 
   output [length:1] q;
1370 
   output reg zq;
1371 
   output reg level1;
1372 
   input rst;
1373 
   input clk;
1374 
   parameter clear_value = 0;
1375 
   parameter set_value = 1;
1376 
   parameter wrap_value = 1;
1377 
   parameter level1_value = 15;
1378 29 unneback 
   wire clear;
1379 30 unneback 
   assign clear = 1'b0;
1380 25 unneback 
   reg  [length:1] qi;
1381 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1382 
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1383 
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1384 
   assign q_next = rew ? q_next_rew : q_next_fw;
1385 
   always @ (posedge clk or posedge rst)
1386 
     if (rst)
1387 
       qi <= {length{1'b0}};
1388 
     else
1389 
     if (cke)
1390 
       qi <= q_next;
1391 
   assign q = qi;
1392 
   always @ (posedge clk or posedge rst)
1393 
     if (rst)
1394 
       zq <= 1'b1;
1395 
     else
1396 
     if (cke)
1397 
       zq <= q_next == {length{1'b0}};
1398 
    always @ (posedge clk or posedge rst)
1399 
    if (rst)
1400 
        level1 <= 1'b0;
1401 
    else
1402 
    if (cke)
1403 29 unneback 
    if (clear)
1404 
        level1 <= 1'b0;
1405 
    else if (q_next == level1_value)
1406 25 unneback 
        level1 <= 1'b1;
1407 
    else if (qi == level1_value & rew)
1408 
        level1 <= 1'b0;
1409 
endmodule
1410 
//////////////////////////////////////////////////////////////////////
1411 
////                                                              ////
1412 
////  Versatile counter                                           ////
1413 
////                                                              ////
1414 
////  Description                                                 ////
1415 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1416 
////  counter                                                     ////
1417 
////                                                              ////
1418 
////  To Do:                                                      ////
1419 
////   - add LFSR with more taps                                  ////
1420 
////                                                              ////
1421 
////  Author(s):                                                  ////
1422 
////      - Michael Unneback, unneback@opencores.org              ////
1423 
////        ORSoC AB                                              ////
1424 
////                                                              ////
1425 
//////////////////////////////////////////////////////////////////////
1426 
////                                                              ////
1427 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1428 
////                                                              ////
1429 
//// This source file may be used and distributed without         ////
1430 
//// restriction provided that this copyright statement is not    ////
1431 
//// removed from the file and that any derivative work contains  ////
1432 
//// the original copyright notice and the associated disclaimer. ////
1433 
////                                                              ////
1434 
//// This source file is free software; you can redistribute it   ////
1435 
//// and/or modify it under the terms of the GNU Lesser General   ////
1436 
//// Public License as published by the Free Software Foundation; ////
1437 
//// either version 2.1 of the License, or (at your option) any   ////
1438 
//// later version.                                               ////
1439 
////                                                              ////
1440 
//// This source is distributed in the hope that it will be       ////
1441 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1442 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1443 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1444 
//// details.                                                     ////
1445 
////                                                              ////
1446 
//// You should have received a copy of the GNU Lesser General    ////
1447 
//// Public License along with this source; if not, download it   ////
1448 
//// from http://www.opencores.org/lgpl.shtml                     ////
1449 
////                                                              ////
1450 
//////////////////////////////////////////////////////////////////////
1451 75 unneback 
// LFSR counter
1452 136 unneback 
module vl_cnt_lfsr_zq (
1453 
 zq, rst, clk);
1454 
   parameter length = 4;
1455 
   output reg zq;
1456 
   input rst;
1457 
   input clk;
1458 
   parameter clear_value = 0;
1459 
   parameter set_value = 1;
1460 
   parameter wrap_value = 8;
1461 
   parameter level1_value = 15;
1462 
   reg  [length:1] qi;
1463 
   reg lfsr_fb;
1464 
   wire [length:1] q_next;
1465 
   reg [32:1] polynom;
1466 
   integer i;
1467 
   always @ (qi)
1468 
   begin
1469 
        case (length)
1470 
         2: polynom = 32'b11;                               // 0x3
1471 
         3: polynom = 32'b110;                              // 0x6
1472 
         4: polynom = 32'b1100;                             // 0xC
1473 
         5: polynom = 32'b10100;                            // 0x14
1474 
         6: polynom = 32'b110000;                           // 0x30
1475 
         7: polynom = 32'b1100000;                          // 0x60
1476 
         8: polynom = 32'b10111000;                         // 0xb8
1477 
         9: polynom = 32'b100010000;                        // 0x110
1478 
        10: polynom = 32'b1001000000;                       // 0x240
1479 
        11: polynom = 32'b10100000000;                      // 0x500
1480 
        12: polynom = 32'b100000101001;                     // 0x829
1481 
        13: polynom = 32'b1000000001100;                    // 0x100C
1482 
        14: polynom = 32'b10000000010101;                   // 0x2015
1483 
        15: polynom = 32'b110000000000000;                  // 0x6000
1484 
        16: polynom = 32'b1101000000001000;                 // 0xD008
1485 
        17: polynom = 32'b10010000000000000;                // 0x12000
1486 
        18: polynom = 32'b100000010000000000;               // 0x20400
1487 
        19: polynom = 32'b1000000000000100011;              // 0x40023
1488 
        20: polynom = 32'b10010000000000000000;             // 0x90000
1489 
        21: polynom = 32'b101000000000000000000;            // 0x140000
1490 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1491 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1492 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1493 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1494 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1495 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1496 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1497 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1498 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1499 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1500 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1501 
        default: polynom = 32'b0;
1502 
        endcase
1503 
        lfsr_fb = qi[length];
1504 
        for (i=length-1; i>=1; i=i-1) begin
1505 
            if (polynom[i])
1506 
                lfsr_fb = lfsr_fb  ~^ qi[i];
1507 
        end
1508 
    end
1509 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1510 
   always @ (posedge clk or posedge rst)
1511 
     if (rst)
1512 
       qi <= {length{1'b0}};
1513 
     else
1514 
       qi <= q_next;
1515 
   always @ (posedge clk or posedge rst)
1516 
     if (rst)
1517 
       zq <= 1'b1;
1518 
     else
1519 
       zq <= q_next == {length{1'b0}};
1520 
endmodule
1521 
//////////////////////////////////////////////////////////////////////
1522 
////                                                              ////
1523 
////  Versatile counter                                           ////
1524 
////                                                              ////
1525 
////  Description                                                 ////
1526 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1527 
////  counter                                                     ////
1528 
////                                                              ////
1529 
////  To Do:                                                      ////
1530 
////   - add LFSR with more taps                                  ////
1531 
////                                                              ////
1532 
////  Author(s):                                                  ////
1533 
////      - Michael Unneback, unneback@opencores.org              ////
1534 
////        ORSoC AB                                              ////
1535 
////                                                              ////
1536 
//////////////////////////////////////////////////////////////////////
1537 
////                                                              ////
1538 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1539 
////                                                              ////
1540 
//// This source file may be used and distributed without         ////
1541 
//// restriction provided that this copyright statement is not    ////
1542 
//// removed from the file and that any derivative work contains  ////
1543 
//// the original copyright notice and the associated disclaimer. ////
1544 
////                                                              ////
1545 
//// This source file is free software; you can redistribute it   ////
1546 
//// and/or modify it under the terms of the GNU Lesser General   ////
1547 
//// Public License as published by the Free Software Foundation; ////
1548 
//// either version 2.1 of the License, or (at your option) any   ////
1549 
//// later version.                                               ////
1550 
////                                                              ////
1551 
//// This source is distributed in the hope that it will be       ////
1552 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1553 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1554 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1555 
//// details.                                                     ////
1556 
////                                                              ////
1557 
//// You should have received a copy of the GNU Lesser General    ////
1558 
//// Public License along with this source; if not, download it   ////
1559 
//// from http://www.opencores.org/lgpl.shtml                     ////
1560 
////                                                              ////
1561 
//////////////////////////////////////////////////////////////////////
1562 
// LFSR counter
1563 75 unneback 
module vl_cnt_lfsr_ce (
1564 
 cke, zq, rst, clk);
1565 
   parameter length = 4;
1566 
   input cke;
1567 
   output reg zq;
1568 
   input rst;
1569 
   input clk;
1570 
   parameter clear_value = 0;
1571 
   parameter set_value = 1;
1572 
   parameter wrap_value = 0;
1573 
   parameter level1_value = 15;
1574 
   reg  [length:1] qi;
1575 
   reg lfsr_fb;
1576 
   wire [length:1] q_next;
1577 
   reg [32:1] polynom;
1578 
   integer i;
1579 
   always @ (qi)
1580 
   begin
1581 
        case (length)
1582 
         2: polynom = 32'b11;                               // 0x3
1583 
         3: polynom = 32'b110;                              // 0x6
1584 
         4: polynom = 32'b1100;                             // 0xC
1585 
         5: polynom = 32'b10100;                            // 0x14
1586 
         6: polynom = 32'b110000;                           // 0x30
1587 
         7: polynom = 32'b1100000;                          // 0x60
1588 
         8: polynom = 32'b10111000;                         // 0xb8
1589 
         9: polynom = 32'b100010000;                        // 0x110
1590 
        10: polynom = 32'b1001000000;                       // 0x240
1591 
        11: polynom = 32'b10100000000;                      // 0x500
1592 
        12: polynom = 32'b100000101001;                     // 0x829
1593 
        13: polynom = 32'b1000000001100;                    // 0x100C
1594 
        14: polynom = 32'b10000000010101;                   // 0x2015
1595 
        15: polynom = 32'b110000000000000;                  // 0x6000
1596 
        16: polynom = 32'b1101000000001000;                 // 0xD008
1597 
        17: polynom = 32'b10010000000000000;                // 0x12000
1598 
        18: polynom = 32'b100000010000000000;               // 0x20400
1599 
        19: polynom = 32'b1000000000000100011;              // 0x40023
1600 
        20: polynom = 32'b10010000000000000000;             // 0x90000
1601 
        21: polynom = 32'b101000000000000000000;            // 0x140000
1602 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1603 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1604 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1605 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1606 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1607 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1608 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1609 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1610 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1611 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1612 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1613 
        default: polynom = 32'b0;
1614 
        endcase
1615 
        lfsr_fb = qi[length];
1616 
        for (i=length-1; i>=1; i=i-1) begin
1617 
            if (polynom[i])
1618 
                lfsr_fb = lfsr_fb  ~^ qi[i];
1619 
        end
1620 
    end
1621 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1622 
   always @ (posedge clk or posedge rst)
1623 
     if (rst)
1624 
       qi <= {length{1'b0}};
1625 
     else
1626 
     if (cke)
1627 
       qi <= q_next;
1628 
   always @ (posedge clk or posedge rst)
1629 
     if (rst)
1630 
       zq <= 1'b1;
1631 
     else
1632 
     if (cke)
1633 
       zq <= q_next == {length{1'b0}};
1634 
endmodule
1635 
//////////////////////////////////////////////////////////////////////
1636 
////                                                              ////
1637 
////  Versatile counter                                           ////
1638 
////                                                              ////
1639 
////  Description                                                 ////
1640 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1641 
////  counter                                                     ////
1642 
////                                                              ////
1643 
////  To Do:                                                      ////
1644 
////   - add LFSR with more taps                                  ////
1645 
////                                                              ////
1646 
////  Author(s):                                                  ////
1647 
////      - Michael Unneback, unneback@opencores.org              ////
1648 
////        ORSoC AB                                              ////
1649 
////                                                              ////
1650 
//////////////////////////////////////////////////////////////////////
1651 
////                                                              ////
1652 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1653 
////                                                              ////
1654 
//// This source file may be used and distributed without         ////
1655 
//// restriction provided that this copyright statement is not    ////
1656 
//// removed from the file and that any derivative work contains  ////
1657 
//// the original copyright notice and the associated disclaimer. ////
1658 
////                                                              ////
1659 
//// This source file is free software; you can redistribute it   ////
1660 
//// and/or modify it under the terms of the GNU Lesser General   ////
1661 
//// Public License as published by the Free Software Foundation; ////
1662 
//// either version 2.1 of the License, or (at your option) any   ////
1663 
//// later version.                                               ////
1664 
////                                                              ////
1665 
//// This source is distributed in the hope that it will be       ////
1666 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1667 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1668 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1669 
//// details.                                                     ////
1670 
////                                                              ////
1671 
//// You should have received a copy of the GNU Lesser General    ////
1672 
//// Public License along with this source; if not, download it   ////
1673 
//// from http://www.opencores.org/lgpl.shtml                     ////
1674 
////                                                              ////
1675 
//////////////////////////////////////////////////////////////////////
1676 139 unneback 
// LFSR counter
1677 
module vl_cnt_lfsr_ce_zq (
1678 
 cke, zq, rst, clk);
1679 
   parameter length = 4;
1680 
   input cke;
1681 
   output reg zq;
1682 
   input rst;
1683 
   input clk;
1684 
   parameter clear_value = 0;
1685 
   parameter set_value = 1;
1686 
   parameter wrap_value = 8;
1687 
   parameter level1_value = 15;
1688 
   reg  [length:1] qi;
1689 
   reg lfsr_fb;
1690 
   wire [length:1] q_next;
1691 
   reg [32:1] polynom;
1692 
   integer i;
1693 
   always @ (qi)
1694 
   begin
1695 
        case (length)
1696 
         2: polynom = 32'b11;                               // 0x3
1697 
         3: polynom = 32'b110;                              // 0x6
1698 
         4: polynom = 32'b1100;                             // 0xC
1699 
         5: polynom = 32'b10100;                            // 0x14
1700 
         6: polynom = 32'b110000;                           // 0x30
1701 
         7: polynom = 32'b1100000;                          // 0x60
1702 
         8: polynom = 32'b10111000;                         // 0xb8
1703 
         9: polynom = 32'b100010000;                        // 0x110
1704 
        10: polynom = 32'b1001000000;                       // 0x240
1705 
        11: polynom = 32'b10100000000;                      // 0x500
1706 
        12: polynom = 32'b100000101001;                     // 0x829
1707 
        13: polynom = 32'b1000000001100;                    // 0x100C
1708 
        14: polynom = 32'b10000000010101;                   // 0x2015
1709 
        15: polynom = 32'b110000000000000;                  // 0x6000
1710 
        16: polynom = 32'b1101000000001000;                 // 0xD008
1711 
        17: polynom = 32'b10010000000000000;                // 0x12000
1712 
        18: polynom = 32'b100000010000000000;               // 0x20400
1713 
        19: polynom = 32'b1000000000000100011;              // 0x40023
1714 
        20: polynom = 32'b10010000000000000000;             // 0x90000
1715 
        21: polynom = 32'b101000000000000000000;            // 0x140000
1716 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1717 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1718 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1719 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1720 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1721 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1722 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1723 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1724 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1725 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1726 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1727 
        default: polynom = 32'b0;
1728 
        endcase
1729 
        lfsr_fb = qi[length];
1730 
        for (i=length-1; i>=1; i=i-1) begin
1731 
            if (polynom[i])
1732 
                lfsr_fb = lfsr_fb  ~^ qi[i];
1733 
        end
1734 
    end
1735 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1736 
   always @ (posedge clk or posedge rst)
1737 
     if (rst)
1738 
       qi <= {length{1'b0}};
1739 
     else
1740 
     if (cke)
1741 
       qi <= q_next;
1742 
   always @ (posedge clk or posedge rst)
1743 
     if (rst)
1744 
       zq <= 1'b1;
1745 
     else
1746 
     if (cke)
1747 
       zq <= q_next == {length{1'b0}};
1748 
endmodule
1749 
//////////////////////////////////////////////////////////////////////
1750 
////                                                              ////
1751 
////  Versatile counter                                           ////
1752 
////                                                              ////
1753 
////  Description                                                 ////
1754 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1755 
////  counter                                                     ////
1756 
////                                                              ////
1757 
////  To Do:                                                      ////
1758 
////   - add LFSR with more taps                                  ////
1759 
////                                                              ////
1760 
////  Author(s):                                                  ////
1761 
////      - Michael Unneback, unneback@opencores.org              ////
1762 
////        ORSoC AB                                              ////
1763 
////                                                              ////
1764 
//////////////////////////////////////////////////////////////////////
1765 
////                                                              ////
1766 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1767 
////                                                              ////
1768 
//// This source file may be used and distributed without         ////
1769 
//// restriction provided that this copyright statement is not    ////
1770 
//// removed from the file and that any derivative work contains  ////
1771 
//// the original copyright notice and the associated disclaimer. ////
1772 
////                                                              ////
1773 
//// This source file is free software; you can redistribute it   ////
1774 
//// and/or modify it under the terms of the GNU Lesser General   ////
1775 
//// Public License as published by the Free Software Foundation; ////
1776 
//// either version 2.1 of the License, or (at your option) any   ////
1777 
//// later version.                                               ////
1778 
////                                                              ////
1779 
//// This source is distributed in the hope that it will be       ////
1780 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1781 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1782 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1783 
//// details.                                                     ////
1784 
////                                                              ////
1785 
//// You should have received a copy of the GNU Lesser General    ////
1786 
//// Public License along with this source; if not, download it   ////
1787 
//// from http://www.opencores.org/lgpl.shtml                     ////
1788 
////                                                              ////
1789 
//////////////////////////////////////////////////////////////////////
1790 
// LFSR counter
1791 
module vl_cnt_lfsr_ce_q (
1792 
 cke, q, rst, clk);
1793 
   parameter length = 4;
1794 
   input cke;
1795 
   output [length:1] q;
1796 
   input rst;
1797 
   input clk;
1798 
   parameter clear_value = 0;
1799 
   parameter set_value = 1;
1800 
   parameter wrap_value = 8;
1801 
   parameter level1_value = 15;
1802 
   reg  [length:1] qi;
1803 
   reg lfsr_fb;
1804 
   wire [length:1] q_next;
1805 
   reg [32:1] polynom;
1806 
   integer i;
1807 
   always @ (qi)
1808 
   begin
1809 
        case (length)
1810 
         2: polynom = 32'b11;                               // 0x3
1811 
         3: polynom = 32'b110;                              // 0x6
1812 
         4: polynom = 32'b1100;                             // 0xC
1813 
         5: polynom = 32'b10100;                            // 0x14
1814 
         6: polynom = 32'b110000;                           // 0x30
1815 
         7: polynom = 32'b1100000;                          // 0x60
1816 
         8: polynom = 32'b10111000;                         // 0xb8
1817 
         9: polynom = 32'b100010000;                        // 0x110
1818 
        10: polynom = 32'b1001000000;                       // 0x240
1819 
        11: polynom = 32'b10100000000;                      // 0x500
1820 
        12: polynom = 32'b100000101001;                     // 0x829
1821 
        13: polynom = 32'b1000000001100;                    // 0x100C
1822 
        14: polynom = 32'b10000000010101;                   // 0x2015
1823 
        15: polynom = 32'b110000000000000;                  // 0x6000
1824 
        16: polynom = 32'b1101000000001000;                 // 0xD008
1825 
        17: polynom = 32'b10010000000000000;                // 0x12000
1826 
        18: polynom = 32'b100000010000000000;               // 0x20400
1827 
        19: polynom = 32'b1000000000000100011;              // 0x40023
1828 
        20: polynom = 32'b10010000000000000000;             // 0x90000
1829 
        21: polynom = 32'b101000000000000000000;            // 0x140000
1830 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1831 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1832 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1833 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1834 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1835 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1836 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1837 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1838 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1839 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1840 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1841 
        default: polynom = 32'b0;
1842 
        endcase
1843 
        lfsr_fb = qi[length];
1844 
        for (i=length-1; i>=1; i=i-1) begin
1845 
            if (polynom[i])
1846 
                lfsr_fb = lfsr_fb  ~^ qi[i];
1847 
        end
1848 
    end
1849 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1850 
   always @ (posedge clk or posedge rst)
1851 
     if (rst)
1852 
       qi <= {length{1'b0}};
1853 
     else
1854 
     if (cke)
1855 
       qi <= q_next;
1856 
   assign q = qi;
1857 
endmodule
1858 
//////////////////////////////////////////////////////////////////////
1859 
////                                                              ////
1860 
////  Versatile counter                                           ////
1861 
////                                                              ////
1862 
////  Description                                                 ////
1863 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1864 
////  counter                                                     ////
1865 
////                                                              ////
1866 
////  To Do:                                                      ////
1867 
////   - add LFSR with more taps                                  ////
1868 
////                                                              ////
1869 
////  Author(s):                                                  ////
1870 
////      - Michael Unneback, unneback@opencores.org              ////
1871 
////        ORSoC AB                                              ////
1872 
////                                                              ////
1873 
//////////////////////////////////////////////////////////////////////
1874 
////                                                              ////
1875 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1876 
////                                                              ////
1877 
//// This source file may be used and distributed without         ////
1878 
//// restriction provided that this copyright statement is not    ////
1879 
//// removed from the file and that any derivative work contains  ////
1880 
//// the original copyright notice and the associated disclaimer. ////
1881 
////                                                              ////
1882 
//// This source file is free software; you can redistribute it   ////
1883 
//// and/or modify it under the terms of the GNU Lesser General   ////
1884 
//// Public License as published by the Free Software Foundation; ////
1885 
//// either version 2.1 of the License, or (at your option) any   ////
1886 
//// later version.                                               ////
1887 
////                                                              ////
1888 
//// This source is distributed in the hope that it will be       ////
1889 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1890 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1891 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1892 
//// details.                                                     ////
1893 
////                                                              ////
1894 
//// You should have received a copy of the GNU Lesser General    ////
1895 
//// Public License along with this source; if not, download it   ////
1896 
//// from http://www.opencores.org/lgpl.shtml                     ////
1897 
////                                                              ////
1898 
//////////////////////////////////////////////////////////////////////
1899 
// LFSR counter
1900 
module vl_cnt_lfsr_ce_clear_q (
1901 
 clear, cke, q, rst, clk);
1902 
   parameter length = 4;
1903 
   input clear;
1904 
   input cke;
1905 
   output [length:1] q;
1906 
   input rst;
1907 
   input clk;
1908 
   parameter clear_value = 0;
1909 
   parameter set_value = 1;
1910 
   parameter wrap_value = 8;
1911 
   parameter level1_value = 15;
1912 
   reg  [length:1] qi;
1913 
   reg lfsr_fb;
1914 
   wire [length:1] q_next;
1915 
   reg [32:1] polynom;
1916 
   integer i;
1917 
   always @ (qi)
1918 
   begin
1919 
        case (length)
1920 
         2: polynom = 32'b11;                               // 0x3
1921 
         3: polynom = 32'b110;                              // 0x6
1922 
         4: polynom = 32'b1100;                             // 0xC
1923 
         5: polynom = 32'b10100;                            // 0x14
1924 
         6: polynom = 32'b110000;                           // 0x30
1925 
         7: polynom = 32'b1100000;                          // 0x60
1926 
         8: polynom = 32'b10111000;                         // 0xb8
1927 
         9: polynom = 32'b100010000;                        // 0x110
1928 
        10: polynom = 32'b1001000000;                       // 0x240
1929 
        11: polynom = 32'b10100000000;                      // 0x500
1930 
        12: polynom = 32'b100000101001;                     // 0x829
1931 
        13: polynom = 32'b1000000001100;                    // 0x100C
1932 
        14: polynom = 32'b10000000010101;                   // 0x2015
1933 
        15: polynom = 32'b110000000000000;                  // 0x6000
1934 
        16: polynom = 32'b1101000000001000;                 // 0xD008
1935 
        17: polynom = 32'b10010000000000000;                // 0x12000
1936 
        18: polynom = 32'b100000010000000000;               // 0x20400
1937 
        19: polynom = 32'b1000000000000100011;              // 0x40023
1938 
        20: polynom = 32'b10010000000000000000;             // 0x90000
1939 
        21: polynom = 32'b101000000000000000000;            // 0x140000
1940 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1941 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1942 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1943 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1944 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1945 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1946 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1947 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1948 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1949 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1950 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1951 
        default: polynom = 32'b0;
1952 
        endcase
1953 
        lfsr_fb = qi[length];
1954 
        for (i=length-1; i>=1; i=i-1) begin
1955 
            if (polynom[i])
1956 
                lfsr_fb = lfsr_fb  ~^ qi[i];
1957 
        end
1958 
    end
1959 
   assign q_next =  clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1960 
   always @ (posedge clk or posedge rst)
1961 
     if (rst)
1962 
       qi <= {length{1'b0}};
1963 
     else
1964 
     if (cke)
1965 
       qi <= q_next;
1966 
   assign q = qi;
1967 
endmodule
1968 
//////////////////////////////////////////////////////////////////////
1969 
////                                                              ////
1970 
////  Versatile counter                                           ////
1971 
////                                                              ////
1972 
////  Description                                                 ////
1973 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1974 
////  counter                                                     ////
1975 
////                                                              ////
1976 
////  To Do:                                                      ////
1977 
////   - add LFSR with more taps                                  ////
1978 
////                                                              ////
1979 
////  Author(s):                                                  ////
1980 
////      - Michael Unneback, unneback@opencores.org              ////
1981 
////        ORSoC AB                                              ////
1982 
////                                                              ////
1983 
//////////////////////////////////////////////////////////////////////
1984 
////                                                              ////
1985 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1986 
////                                                              ////
1987 
//// This source file may be used and distributed without         ////
1988 
//// restriction provided that this copyright statement is not    ////
1989 
//// removed from the file and that any derivative work contains  ////
1990 
//// the original copyright notice and the associated disclaimer. ////
1991 
////                                                              ////
1992 
//// This source file is free software; you can redistribute it   ////
1993 
//// and/or modify it under the terms of the GNU Lesser General   ////
1994 
//// Public License as published by the Free Software Foundation; ////
1995 
//// either version 2.1 of the License, or (at your option) any   ////
1996 
//// later version.                                               ////
1997 
////                                                              ////
1998 
//// This source is distributed in the hope that it will be       ////
1999 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2000 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2001 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2002 
//// details.                                                     ////
2003 
////                                                              ////
2004 
//// You should have received a copy of the GNU Lesser General    ////
2005 
//// Public License along with this source; if not, download it   ////
2006 
//// from http://www.opencores.org/lgpl.shtml                     ////
2007 
////                                                              ////
2008 
//////////////////////////////////////////////////////////////////////
2009 
// LFSR counter
2010 
module vl_cnt_lfsr_ce_q_zq (
2011 
 cke, q, zq, rst, clk);
2012 
   parameter length = 4;
2013 
   input cke;
2014 
   output [length:1] q;
2015 
   output reg zq;
2016 
   input rst;
2017 
   input clk;
2018 
   parameter clear_value = 0;
2019 
   parameter set_value = 1;
2020 
   parameter wrap_value = 8;
2021 
   parameter level1_value = 15;
2022 
   reg  [length:1] qi;
2023 
   reg lfsr_fb;
2024 
   wire [length:1] q_next;
2025 
   reg [32:1] polynom;
2026 
   integer i;
2027 
   always @ (qi)
2028 
   begin
2029 
        case (length)
2030 
         2: polynom = 32'b11;                               // 0x3
2031 
         3: polynom = 32'b110;                              // 0x6
2032 
         4: polynom = 32'b1100;                             // 0xC
2033 
         5: polynom = 32'b10100;                            // 0x14
2034 
         6: polynom = 32'b110000;                           // 0x30
2035 
         7: polynom = 32'b1100000;                          // 0x60
2036 
         8: polynom = 32'b10111000;                         // 0xb8
2037 
         9: polynom = 32'b100010000;                        // 0x110
2038 
        10: polynom = 32'b1001000000;                       // 0x240
2039 
        11: polynom = 32'b10100000000;                      // 0x500
2040 
        12: polynom = 32'b100000101001;                     // 0x829
2041 
        13: polynom = 32'b1000000001100;                    // 0x100C
2042 
        14: polynom = 32'b10000000010101;                   // 0x2015
2043 
        15: polynom = 32'b110000000000000;                  // 0x6000
2044 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2045 
        17: polynom = 32'b10010000000000000;                // 0x12000
2046 
        18: polynom = 32'b100000010000000000;               // 0x20400
2047 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2048 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2049 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2050 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2051 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2052 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2053 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2054 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2055 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2056 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2057 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2058 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2059 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2060 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2061 
        default: polynom = 32'b0;
2062 
        endcase
2063 
        lfsr_fb = qi[length];
2064 
        for (i=length-1; i>=1; i=i-1) begin
2065 
            if (polynom[i])
2066 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2067 
        end
2068 
    end
2069 
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2070 
   always @ (posedge clk or posedge rst)
2071 
     if (rst)
2072 
       qi <= {length{1'b0}};
2073 
     else
2074 
     if (cke)
2075 
       qi <= q_next;
2076 
   assign q = qi;
2077 
   always @ (posedge clk or posedge rst)
2078 
     if (rst)
2079 
       zq <= 1'b1;
2080 
     else
2081 
     if (cke)
2082 
       zq <= q_next == {length{1'b0}};
2083 
endmodule
2084 
//////////////////////////////////////////////////////////////////////
2085 
////                                                              ////
2086 
////  Versatile counter                                           ////
2087 
////                                                              ////
2088 
////  Description                                                 ////
2089 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2090 
////  counter                                                     ////
2091 
////                                                              ////
2092 
////  To Do:                                                      ////
2093 
////   - add LFSR with more taps                                  ////
2094 
////                                                              ////
2095 
////  Author(s):                                                  ////
2096 
////      - Michael Unneback, unneback@opencores.org              ////
2097 
////        ORSoC AB                                              ////
2098 
////                                                              ////
2099 
//////////////////////////////////////////////////////////////////////
2100 
////                                                              ////
2101 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2102 
////                                                              ////
2103 
//// This source file may be used and distributed without         ////
2104 
//// restriction provided that this copyright statement is not    ////
2105 
//// removed from the file and that any derivative work contains  ////
2106 
//// the original copyright notice and the associated disclaimer. ////
2107 
////                                                              ////
2108 
//// This source file is free software; you can redistribute it   ////
2109 
//// and/or modify it under the terms of the GNU Lesser General   ////
2110 
//// Public License as published by the Free Software Foundation; ////
2111 
//// either version 2.1 of the License, or (at your option) any   ////
2112 
//// later version.                                               ////
2113 
////                                                              ////
2114 
//// This source is distributed in the hope that it will be       ////
2115 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2116 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2117 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2118 
//// details.                                                     ////
2119 
////                                                              ////
2120 
//// You should have received a copy of the GNU Lesser General    ////
2121 
//// Public License along with this source; if not, download it   ////
2122 
//// from http://www.opencores.org/lgpl.shtml                     ////
2123 
////                                                              ////
2124 
//////////////////////////////////////////////////////////////////////
2125 
// LFSR counter
2126 
module vl_cnt_lfsr_ce_rew_l1 (
2127 
 cke, rew, level1, rst, clk);
2128 
   parameter length = 4;
2129 
   input cke;
2130 
   input rew;
2131 
   output reg level1;
2132 
   input rst;
2133 
   input clk;
2134 
   parameter clear_value = 0;
2135 
   parameter set_value = 1;
2136 
   parameter wrap_value = 8;
2137 
   parameter level1_value = 15;
2138 
   wire clear;
2139 
   assign clear = 1'b0;
2140 
   reg  [length:1] qi;
2141 
   reg lfsr_fb, lfsr_fb_rew;
2142 
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2143 
   reg [32:1] polynom_rew;
2144 
   integer j;
2145 
   reg [32:1] polynom;
2146 
   integer i;
2147 
   always @ (qi)
2148 
   begin
2149 
        case (length)
2150 
         2: polynom = 32'b11;                               // 0x3
2151 
         3: polynom = 32'b110;                              // 0x6
2152 
         4: polynom = 32'b1100;                             // 0xC
2153 
         5: polynom = 32'b10100;                            // 0x14
2154 
         6: polynom = 32'b110000;                           // 0x30
2155 
         7: polynom = 32'b1100000;                          // 0x60
2156 
         8: polynom = 32'b10111000;                         // 0xb8
2157 
         9: polynom = 32'b100010000;                        // 0x110
2158 
        10: polynom = 32'b1001000000;                       // 0x240
2159 
        11: polynom = 32'b10100000000;                      // 0x500
2160 
        12: polynom = 32'b100000101001;                     // 0x829
2161 
        13: polynom = 32'b1000000001100;                    // 0x100C
2162 
        14: polynom = 32'b10000000010101;                   // 0x2015
2163 
        15: polynom = 32'b110000000000000;                  // 0x6000
2164 
        16: polynom = 32'b1101000000001000;                 // 0xD008
2165 
        17: polynom = 32'b10010000000000000;                // 0x12000
2166 
        18: polynom = 32'b100000010000000000;               // 0x20400
2167 
        19: polynom = 32'b1000000000000100011;              // 0x40023
2168 
        20: polynom = 32'b10010000000000000000;             // 0x90000
2169 
        21: polynom = 32'b101000000000000000000;            // 0x140000
2170 
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2171 
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2172 
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2173 
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2174 
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2175 
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2176 
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2177 
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2178 
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2179 
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2180 
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2181 
        default: polynom = 32'b0;
2182 
        endcase
2183 
        lfsr_fb = qi[length];
2184 
        for (i=length-1; i>=1; i=i-1) begin
2185 
            if (polynom[i])
2186 
                lfsr_fb = lfsr_fb  ~^ qi[i];
2187 
        end
2188 
    end
2189 
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2190 
   always @ (qi)
2191 
   begin
2192 
        case (length)
2193 
         2: polynom_rew = 32'b11;
2194 
         3: polynom_rew = 32'b110;
2195 
         4: polynom_rew = 32'b1100;
2196 
         5: polynom_rew = 32'b10100;
2197 
         6: polynom_rew = 32'b110000;
2198 
         7: polynom_rew = 32'b1100000;
2199 
         8: polynom_rew = 32'b10111000;
2200 
         9: polynom_rew = 32'b100010000;
2201 
        10: polynom_rew = 32'b1001000000;
2202 
        11: polynom_rew = 32'b10100000000;
2203 
        12: polynom_rew = 32'b100000101001;
2204 
        13: polynom_rew = 32'b1000000001100;
2205 
        14: polynom_rew = 32'b10000000010101;
2206 
        15: polynom_rew = 32'b110000000000000;
2207 
        16: polynom_rew = 32'b1101000000001000;
2208 
        17: polynom_rew = 32'b10010000000000000;
2209 
        18: polynom_rew = 32'b100000010000000000;
2210 
        19: polynom_rew = 32'b1000000000000100011;
2211 
        20: polynom_rew = 32'b10000010000000000000;
2212 
        21: polynom_rew = 32'b101000000000000000000;
2213 
        22: polynom_rew = 32'b1100000000000000000000;
2214 
        23: polynom_rew = 32'b10000100000000000000000;
2215 
        24: polynom_rew = 32'b111000010000000000000000;
2216 
        25: polynom_rew = 32'b1001000000000000000000000;
2217 
        26: polynom_rew = 32'b10000000000000000000100011;
2218 
        27: polynom_rew = 32'b100000000000000000000010011;
2219 
        28: polynom_rew = 32'b1100100000000000000000000000;
2220 
        29: polynom_rew = 32'b10100000000000000000000000000;
2221 
        30: polynom_rew = 32'b100000000000000000000000101001;
2222 
        31: polynom_rew = 32'b1001000000000000000000000000000;
2223 
        32: polynom_rew = 32'b10000000001000000000000000000011;
2224 
        default: polynom_rew = 32'b0;
2225 
        endcase
2226 
        // rotate left
2227 
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
2228 
        lfsr_fb_rew = qi[length];
2229 
        for (i=length-1; i>=1; i=i-1) begin
2230 
            if (polynom_rew[i])
2231 
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
2232 
        end
2233 
    end
2234 
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
2235 
   assign q_next = rew ? q_next_rew : q_next_fw;
2236 
   always @ (posedge clk or posedge rst)
2237 
     if (rst)
2238 
       qi <= {length{1'b0}};
2239 
     else
2240 
     if (cke)
2241 
       qi <= q_next;
2242 
    always @ (posedge clk or posedge rst)
2243 
    if (rst)
2244 
        level1 <= 1'b0;
2245 
    else
2246 
    if (cke)
2247 
    if (clear)
2248 
        level1 <= 1'b0;
2249 
    else if (q_next == level1_value)
2250 
        level1 <= 1'b1;
2251 
    else if (qi == level1_value & rew)
2252 
        level1 <= 1'b0;
2253 
endmodule
2254 
//////////////////////////////////////////////////////////////////////
2255 
////                                                              ////
2256 
////  Versatile counter                                           ////
2257 
////                                                              ////
2258 
////  Description                                                 ////
2259 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2260 
////  counter                                                     ////
2261 
////                                                              ////
2262 
////  To Do:                                                      ////
2263 
////   - add LFSR with more taps                                  ////
2264 
////                                                              ////
2265 
////  Author(s):                                                  ////
2266 
////      - Michael Unneback, unneback@opencores.org              ////
2267 
////        ORSoC AB                                              ////
2268 
////                                                              ////
2269 
//////////////////////////////////////////////////////////////////////
2270 
////                                                              ////
2271 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2272 
////                                                              ////
2273 
//// This source file may be used and distributed without         ////
2274 
//// restriction provided that this copyright statement is not    ////
2275 
//// removed from the file and that any derivative work contains  ////
2276 
//// the original copyright notice and the associated disclaimer. ////
2277 
////                                                              ////
2278 
//// This source file is free software; you can redistribute it   ////
2279 
//// and/or modify it under the terms of the GNU Lesser General   ////
2280 
//// Public License as published by the Free Software Foundation; ////
2281 
//// either version 2.1 of the License, or (at your option) any   ////
2282 
//// later version.                                               ////
2283 
////                                                              ////
2284 
//// This source is distributed in the hope that it will be       ////
2285 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2286 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2287 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2288 
//// details.                                                     ////
2289 
////                                                              ////
2290 
//// You should have received a copy of the GNU Lesser General    ////
2291 
//// Public License along with this source; if not, download it   ////
2292 
//// from http://www.opencores.org/lgpl.shtml                     ////
2293 
////                                                              ////
2294 
//////////////////////////////////////////////////////////////////////
2295 6 unneback 
// GRAY counter
2296 139 unneback 
module vl_cnt_gray (
2297 
 q, rst, clk);
2298 
   parameter length = 4;
2299 
   output reg [length:1] q;
2300 
   input rst;
2301 
   input clk;
2302 
   parameter clear_value = 0;
2303 
   parameter set_value = 1;
2304 
   parameter wrap_value = 8;
2305 
   parameter level1_value = 15;
2306 
   reg  [length:1] qi;
2307 
   wire [length:1] q_next;
2308 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2309 
   always @ (posedge clk or posedge rst)
2310 
     if (rst)
2311 
       qi <= {length{1'b0}};
2312 
     else
2313 
       qi <= q_next;
2314 
   always @ (posedge clk or posedge rst)
2315 
     if (rst)
2316 
       q <= {length{1'b0}};
2317 
     else
2318 
         q <= (q_next>>1) ^ q_next;
2319 
endmodule
2320 
//////////////////////////////////////////////////////////////////////
2321 
////                                                              ////
2322 
////  Versatile counter                                           ////
2323 
////                                                              ////
2324 
////  Description                                                 ////
2325 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2326 
////  counter                                                     ////
2327 
////                                                              ////
2328 
////  To Do:                                                      ////
2329 
////   - add LFSR with more taps                                  ////
2330 
////                                                              ////
2331 
////  Author(s):                                                  ////
2332 
////      - Michael Unneback, unneback@opencores.org              ////
2333 
////        ORSoC AB                                              ////
2334 
////                                                              ////
2335 
//////////////////////////////////////////////////////////////////////
2336 
////                                                              ////
2337 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2338 
////                                                              ////
2339 
//// This source file may be used and distributed without         ////
2340 
//// restriction provided that this copyright statement is not    ////
2341 
//// removed from the file and that any derivative work contains  ////
2342 
//// the original copyright notice and the associated disclaimer. ////
2343 
////                                                              ////
2344 
//// This source file is free software; you can redistribute it   ////
2345 
//// and/or modify it under the terms of the GNU Lesser General   ////
2346 
//// Public License as published by the Free Software Foundation; ////
2347 
//// either version 2.1 of the License, or (at your option) any   ////
2348 
//// later version.                                               ////
2349 
////                                                              ////
2350 
//// This source is distributed in the hope that it will be       ////
2351 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2352 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2353 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2354 
//// details.                                                     ////
2355 
////                                                              ////
2356 
//// You should have received a copy of the GNU Lesser General    ////
2357 
//// Public License along with this source; if not, download it   ////
2358 
//// from http://www.opencores.org/lgpl.shtml                     ////
2359 
////                                                              ////
2360 
//////////////////////////////////////////////////////////////////////
2361 
// GRAY counter
2362 
module vl_cnt_gray_ce (
2363 
 cke, q, rst, clk);
2364 
   parameter length = 4;
2365 
   input cke;
2366 
   output reg [length:1] q;
2367 
   input rst;
2368 
   input clk;
2369 
   parameter clear_value = 0;
2370 
   parameter set_value = 1;
2371 
   parameter wrap_value = 8;
2372 
   parameter level1_value = 15;
2373 
   reg  [length:1] qi;
2374 
   wire [length:1] q_next;
2375 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2376 
   always @ (posedge clk or posedge rst)
2377 
     if (rst)
2378 
       qi <= {length{1'b0}};
2379 
     else
2380 
     if (cke)
2381 
       qi <= q_next;
2382 
   always @ (posedge clk or posedge rst)
2383 
     if (rst)
2384 
       q <= {length{1'b0}};
2385 
     else
2386 
       if (cke)
2387 
         q <= (q_next>>1) ^ q_next;
2388 
endmodule
2389 
//////////////////////////////////////////////////////////////////////
2390 
////                                                              ////
2391 
////  Versatile counter                                           ////
2392 
////                                                              ////
2393 
////  Description                                                 ////
2394 
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2395 
////  counter                                                     ////
2396 
////                                                              ////
2397 
////  To Do:                                                      ////
2398 
////   - add LFSR with more taps                                  ////
2399 
////                                                              ////
2400 
////  Author(s):                                                  ////
2401 
////      - Michael Unneback, unneback@opencores.org              ////
2402 
////        ORSoC AB                                              ////
2403 
////                                                              ////
2404 
//////////////////////////////////////////////////////////////////////
2405 
////                                                              ////
2406 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2407 
////                                                              ////
2408 
//// This source file may be used and distributed without         ////
2409 
//// restriction provided that this copyright statement is not    ////
2410 
//// removed from the file and that any derivative work contains  ////
2411 
//// the original copyright notice and the associated disclaimer. ////
2412 
////                                                              ////
2413 
//// This source file is free software; you can redistribute it   ////
2414 
//// and/or modify it under the terms of the GNU Lesser General   ////
2415 
//// Public License as published by the Free Software Foundation; ////
2416 
//// either version 2.1 of the License, or (at your option) any   ////
2417 
//// later version.                                               ////
2418 
////                                                              ////
2419 
//// This source is distributed in the hope that it will be       ////
2420 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2421 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2422 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2423 
//// details.                                                     ////
2424 
////                                                              ////
2425 
//// You should have received a copy of the GNU Lesser General    ////
2426 
//// Public License along with this source; if not, download it   ////
2427 
//// from http://www.opencores.org/lgpl.shtml                     ////
2428 
////                                                              ////
2429 
//////////////////////////////////////////////////////////////////////
2430 
// GRAY counter
2431 40 unneback 
module vl_cnt_gray_ce_bin (
2432 
 cke, q, q_bin, rst, clk);
2433 6 unneback 
   parameter length = 4;
2434 
   input cke;
2435 
   output reg [length:1] q;
2436 
   output [length:1] q_bin;
2437 
   input rst;
2438 
   input clk;
2439 
   parameter clear_value = 0;
2440 
   parameter set_value = 1;
2441 
   parameter wrap_value = 8;
2442 
   parameter level1_value = 15;
2443 
   reg  [length:1] qi;
2444 
   wire [length:1] q_next;
2445 
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2446 
   always @ (posedge clk or posedge rst)
2447 
     if (rst)
2448 
       qi <= {length{1'b0}};
2449 
     else
2450 
     if (cke)
2451 
       qi <= q_next;
2452 
   always @ (posedge clk or posedge rst)
2453 
     if (rst)
2454 
       q <= {length{1'b0}};
2455 
     else
2456 
       if (cke)
2457 
         q <= (q_next>>1) ^ q_next;
2458 
   assign q_bin = qi;
2459 
endmodule
2460 
//////////////////////////////////////////////////////////////////////
2461 
////                                                              ////
2462 
////  Versatile library, counters                                 ////
2463 
////                                                              ////
2464 
////  Description                                                 ////
2465 
////  counters                                                    ////
2466 
////                                                              ////
2467 
////                                                              ////
2468 
////  To Do:                                                      ////
2469 
////   - add more counters                                        ////
2470 
////                                                              ////
2471 
////  Author(s):                                                  ////
2472 
////      - Michael Unneback, unneback@opencores.org              ////
2473 
////        ORSoC AB                                              ////
2474 
////                                                              ////
2475 
//////////////////////////////////////////////////////////////////////
2476 
////                                                              ////
2477 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2478 
////                                                              ////
2479 
//// This source file may be used and distributed without         ////
2480 
//// restriction provided that this copyright statement is not    ////
2481 
//// removed from the file and that any derivative work contains  ////
2482 
//// the original copyright notice and the associated disclaimer. ////
2483 
////                                                              ////
2484 
//// This source file is free software; you can redistribute it   ////
2485 
//// and/or modify it under the terms of the GNU Lesser General   ////
2486 
//// Public License as published by the Free Software Foundation; ////
2487 
//// either version 2.1 of the License, or (at your option) any   ////
2488 
//// later version.                                               ////
2489 
////                                                              ////
2490 
//// This source is distributed in the hope that it will be       ////
2491 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2492 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2493 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2494 
//// details.                                                     ////
2495 
////                                                              ////
2496 
//// You should have received a copy of the GNU Lesser General    ////
2497 
//// Public License along with this source; if not, download it   ////
2498 
//// from http://www.opencores.org/lgpl.shtml                     ////
2499 
////                                                              ////
2500 
//////////////////////////////////////////////////////////////////////
2501 18 unneback 
module vl_cnt_shreg_wrap ( q, rst, clk);
2502 6 unneback 
   parameter length = 4;
2503 
   output reg [0:length-1] q;
2504 
   input rst;
2505 
   input clk;
2506 
    always @ (posedge clk or posedge rst)
2507 
    if (rst)
2508 
        q <= {1'b1,{length-1{1'b0}}};
2509 
    else
2510 
        q <= {q[length-1],q[0:length-2]};
2511 
endmodule
2512 18 unneback 
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
2513 6 unneback 
   parameter length = 4;
2514 
   input cke;
2515 
   output reg [0:length-1] q;
2516 
   input rst;
2517 
   input clk;
2518 
    always @ (posedge clk or posedge rst)
2519 
    if (rst)
2520 
        q <= {1'b1,{length-1{1'b0}}};
2521 
    else
2522 
        if (cke)
2523 
            q <= {q[length-1],q[0:length-2]};
2524 
endmodule
2525 105 unneback 
module vl_cnt_shreg_clear ( clear, q, rst, clk);
2526 
   parameter length = 4;
2527 
   input clear;
2528 
   output reg [0:length-1] q;
2529 
   input rst;
2530 
   input clk;
2531 
    always @ (posedge clk or posedge rst)
2532 
    if (rst)
2533 
        q <= {1'b1,{length-1{1'b0}}};
2534 
    else
2535 
        if (clear)
2536 
            q <= {1'b1,{length-1{1'b0}}};
2537 
        else
2538 
            q <= q >> 1;
2539 
endmodule
2540 18 unneback 
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
2541 6 unneback 
   parameter length = 4;
2542 
   input cke, clear;
2543 
   output reg [0:length-1] q;
2544 
   input rst;
2545 
   input clk;
2546 
    always @ (posedge clk or posedge rst)
2547 
    if (rst)
2548 
        q <= {1'b1,{length-1{1'b0}}};
2549 
    else
2550 
        if (cke)
2551 
            if (clear)
2552 
                q <= {1'b1,{length-1{1'b0}}};
2553 
            else
2554 
                q <= q >> 1;
2555 
endmodule
2556 18 unneback 
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
2557 6 unneback 
   parameter length = 4;
2558 
   input cke, clear;
2559 
   output reg [0:length-1] q;
2560 
   input rst;
2561 
   input clk;
2562 
    always @ (posedge clk or posedge rst)
2563 
    if (rst)
2564 
        q <= {1'b1,{length-1{1'b0}}};
2565 
    else
2566 
        if (cke)
2567 
            if (clear)
2568 
                q <= {1'b1,{length-1{1'b0}}};
2569 
            else
2570 
            q <= {q[length-1],q[0:length-2]};
2571 
endmodule
2572 
//////////////////////////////////////////////////////////////////////
2573 
////                                                              ////
2574 
////  Versatile library, memories                                 ////
2575 
////                                                              ////
2576 
////  Description                                                 ////
2577 
////  memories                                                    ////
2578 
////                                                              ////
2579 
////                                                              ////
2580 
////  To Do:                                                      ////
2581 
////   - add more memory types                                    ////
2582 
////                                                              ////
2583 
////  Author(s):                                                  ////
2584 
////      - Michael Unneback, unneback@opencores.org              ////
2585 
////        ORSoC AB                                              ////
2586 
////                                                              ////
2587 
//////////////////////////////////////////////////////////////////////
2588 
////                                                              ////
2589 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2590 
////                                                              ////
2591 
//// This source file may be used and distributed without         ////
2592 
//// restriction provided that this copyright statement is not    ////
2593 
//// removed from the file and that any derivative work contains  ////
2594 
//// the original copyright notice and the associated disclaimer. ////
2595 
////                                                              ////
2596 
//// This source file is free software; you can redistribute it   ////
2597 
//// and/or modify it under the terms of the GNU Lesser General   ////
2598 
//// Public License as published by the Free Software Foundation; ////
2599 
//// either version 2.1 of the License, or (at your option) any   ////
2600 
//// later version.                                               ////
2601 
////                                                              ////
2602 
//// This source is distributed in the hope that it will be       ////
2603 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2604 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2605 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2606 
//// details.                                                     ////
2607 
////                                                              ////
2608 
//// You should have received a copy of the GNU Lesser General    ////
2609 
//// Public License along with this source; if not, download it   ////
2610 
//// from http://www.opencores.org/lgpl.shtml                     ////
2611 
////                                                              ////
2612 
//////////////////////////////////////////////////////////////////////
2613 
/// ROM
2614 7 unneback 
module vl_rom_init ( adr, q, clk);
2615 
   parameter data_width = 32;
2616 
   parameter addr_width = 8;
2617 75 unneback 
   parameter mem_size = 1<<addr_width;
2618 7 unneback 
   input [(addr_width-1):0]       adr;
2619 
   output reg [(data_width-1):0] q;
2620 
   input                         clk;
2621 75 unneback 
   reg [data_width-1:0] rom [mem_size-1:0];
2622 7 unneback 
   parameter memory_file = "vl_rom.vmem";
2623 
   initial
2624 
     begin
2625 
        $readmemh(memory_file, rom);
2626 
     end
2627 
   always @ (posedge clk)
2628 
     q <= rom[adr];
2629 
endmodule
2630 6 unneback 
// Single port RAM
2631 
module vl_ram ( d, adr, we, q, clk);
2632 
   parameter data_width = 32;
2633 
   parameter addr_width = 8;
2634 75 unneback 
   parameter mem_size = 1<<addr_width;
2635 100 unneback 
   parameter debug = 0;
2636 6 unneback 
   input [(data_width-1):0]      d;
2637 
   input [(addr_width-1):0]       adr;
2638 
   input                         we;
2639 7 unneback 
   output reg [(data_width-1):0] q;
2640 6 unneback 
   input                         clk;
2641 98 unneback 
   reg [data_width-1:0] ram [mem_size-1:0];
2642 100 unneback 
    parameter memory_init = 0;
2643 
    parameter memory_file = "vl_ram.vmem";
2644 
    generate
2645 
    if (memory_init == 1) begin : init_mem
2646 
        initial
2647 
            $readmemh(memory_file, ram);
2648 
   end else if (memory_init == 2) begin : init_zero
2649 
        integer k;
2650 
        initial
2651 
            for (k = 0; k < mem_size; k = k + 1)
2652 
                ram[k] = 0;
2653 7 unneback 
   end
2654 
   endgenerate
2655 100 unneback 
    generate
2656 
    if (debug==1) begin : debug_we
2657 
        always @ (posedge clk)
2658 
        if (we)
2659 
            $display ("Value %h written at address %h : time %t", d, adr, $time);
2660 
    end
2661 
    endgenerate
2662 6 unneback 
   always @ (posedge clk)
2663 
   begin
2664 
   if (we)
2665 
     ram[adr] <= d;
2666 
   q <= ram[adr];
2667 
   end
2668 
endmodule
2669 91 unneback 
module vl_ram_be ( d, adr, be, we, q, clk);
2670 7 unneback 
   parameter data_width = 32;
2671 72 unneback 
   parameter addr_width = 6;
2672 75 unneback 
   parameter mem_size = 1<<addr_width;
2673 7 unneback 
   input [(data_width-1):0]      d;
2674 
   input [(addr_width-1):0]       adr;
2675 73 unneback 
   input [(data_width/8)-1:0]    be;
2676 7 unneback 
   input                         we;
2677 
   output reg [(data_width-1):0] q;
2678 
   input                         clk;
2679 65 unneback 
`ifdef SYSTEMVERILOG
2680 95 unneback 
    // use a multi-dimensional packed array
2681 
    //t o model individual bytes within the word
2682 
    logic [data_width/8-1:0][7:0] ram [0:mem_size-1];// # words = 1 << address width
2683 65 unneback 
`else
2684 85 unneback 
    reg [data_width-1:0] ram [mem_size-1:0];
2685 
    wire [data_width/8-1:0] cke;
2686 65 unneback 
`endif
2687 100 unneback 
    parameter memory_init = 0;
2688 
    parameter memory_file = "vl_ram.vmem";
2689 
    generate
2690 
    if (memory_init == 1) begin : init_mem
2691 
        initial
2692 
            $readmemh(memory_file, ram);
2693 
    end else if (memory_init == 2) begin : init_zero
2694 
        integer k;
2695 
        initial
2696 
            for (k = 0; k < mem_size; k = k + 1)
2697 
                ram[k] = 0;
2698 
    end
2699 7 unneback 
   endgenerate
2700 60 unneback 
`ifdef SYSTEMVERILOG
2701 
always_ff@(posedge clk)
2702 
begin
2703 95 unneback 
    if(we) begin
2704 86 unneback 
        if(be[3]) ram[adr][3] <= d[31:24];
2705 
        if(be[2]) ram[adr][2] <= d[23:16];
2706 
        if(be[1]) ram[adr][1] <= d[15:8];
2707 
        if(be[0]) ram[adr][0] <= d[7:0];
2708 60 unneback 
    end
2709 90 unneback 
        q <= ram[adr];
2710 60 unneback 
end
2711 
`else
2712 85 unneback 
assign cke = {data_width/8{we}} & be;
2713 7 unneback 
   genvar i;
2714 85 unneback 
   generate for (i=0;i<data_width/8;i=i+1) begin : be_ram
2715 7 unneback 
      always @ (posedge clk)
2716 85 unneback 
      if (cke[i])
2717 7 unneback 
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
2718 
   end
2719 
   endgenerate
2720 
   always @ (posedge clk)
2721 
      q <= ram[adr];
2722 60 unneback 
`endif
2723 93 unneback 
`ifdef verilator
2724 85 unneback 
   // Function to access RAM (for use by Verilator).
2725 
   function [31:0] get_mem;
2726 
      // verilator public
2727 90 unneback 
      input [addr_width-1:0]             addr;
2728 85 unneback 
      get_mem = ram[addr];
2729 
   endfunction // get_mem
2730 
   // Function to write RAM (for use by Verilator).
2731 
   function set_mem;
2732 
      // verilator public
2733 90 unneback 
      input [addr_width-1:0]             addr;
2734 
      input [data_width-1:0]             data;
2735 85 unneback 
      ram[addr] = data;
2736 
   endfunction // set_mem
2737 93 unneback 
`endif
2738 7 unneback 
endmodule
2739 
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
2740 6 unneback 
   parameter data_width = 32;
2741 
   parameter addr_width = 8;
2742 75 unneback 
   parameter mem_size = 1<<addr_width;
2743 6 unneback 
   input [(data_width-1):0]      d_a;
2744 
   input [(addr_width-1):0]       adr_a;
2745 
   input [(addr_width-1):0]       adr_b;
2746 
   input                         we_a;
2747 118 unneback 
   output reg [(data_width-1):0]          q_b;
2748 6 unneback 
   input                         clk_a, clk_b;
2749 119 unneback 
   reg [data_width-1:0] ram [0:mem_size-1] /*synthesis syn_ramstyle = "no_rw_check"*/;
2750 100 unneback 
    parameter memory_init = 0;
2751 
    parameter memory_file = "vl_ram.vmem";
2752 
    parameter debug = 0;
2753 
    generate
2754 
    if (memory_init == 1) begin : init_mem
2755 
        initial
2756 
            $readmemh(memory_file, ram);
2757 
    end else if (memory_init == 2) begin : init_zero
2758 
        integer k;
2759 
        initial
2760 
            for (k = 0; k < mem_size; k = k + 1)
2761 
                ram[k] = 0;
2762 
    end
2763 7 unneback 
   endgenerate
2764 100 unneback 
    generate
2765 
    if (debug==1) begin : debug_we
2766 
        always @ (posedge clk_a)
2767 
        if (we_a)
2768 
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
2769 
    end
2770 
    endgenerate
2771 6 unneback 
   always @ (posedge clk_a)
2772 
   if (we_a)
2773 
     ram[adr_a] <= d_a;
2774 
   always @ (posedge clk_b)
2775 118 unneback 
      q_b = ram[adr_b];
2776 6 unneback 
endmodule
2777 7 unneback 
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
2778 6 unneback 
   parameter data_width = 32;
2779 
   parameter addr_width = 8;
2780 75 unneback 
   parameter mem_size = 1<<addr_width;
2781 6 unneback 
   input [(data_width-1):0]      d_a;
2782 
   input [(addr_width-1):0]       adr_a;
2783 
   input [(addr_width-1):0]       adr_b;
2784 
   input                         we_a;
2785 
   output [(data_width-1):0]      q_b;
2786 
   output reg [(data_width-1):0] q_a;
2787 
   input                         clk_a, clk_b;
2788 
   reg [(data_width-1):0]         q_b;
2789 119 unneback 
   reg [data_width-1:0] ram [0:mem_size-1] /*synthesis syn_ramstyle = "no_rw_check"*/;
2790 100 unneback 
    parameter memory_init = 0;
2791 
    parameter memory_file = "vl_ram.vmem";
2792 
    parameter debug = 0;
2793 
    generate
2794 
    if (memory_init == 1) begin : init_mem
2795 
        initial
2796 
            $readmemh(memory_file, ram);
2797 
    end else if (memory_init == 2) begin : init_zero
2798 
        integer k;
2799 
        initial
2800 
            for (k = 0; k < mem_size; k = k + 1)
2801 
                ram[k] = 0;
2802 
    end
2803 7 unneback 
   endgenerate
2804 100 unneback 
    generate
2805 
    if (debug==1) begin : debug_we
2806 
        always @ (posedge clk_a)
2807 
        if (we_a)
2808 
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
2809 
    end
2810 
    endgenerate
2811 6 unneback 
   always @ (posedge clk_a)
2812 
     begin
2813 
        q_a <= ram[adr_a];
2814 
        if (we_a)
2815 
             ram[adr_a] <= d_a;
2816 
     end
2817 
   always @ (posedge clk_b)
2818 
          q_b <= ram[adr_b];
2819 
endmodule
2820 100 unneback 
module vl_dpram_1r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, adr_b, we_b, clk_b );
2821 
   parameter data_width = 32;
2822 
   parameter addr_width = 8;
2823 
   parameter mem_size = 1<<addr_width;
2824 
   input [(data_width-1):0]      d_a;
2825 
   input [(addr_width-1):0]       adr_a;
2826 
   input [(addr_width-1):0]       adr_b;
2827 
   input                         we_a;
2828 
   input [(data_width-1):0]       d_b;
2829 
   output reg [(data_width-1):0] q_a;
2830 
   input                         we_b;
2831 
   input                         clk_a, clk_b;
2832 
   reg [(data_width-1):0]         q_b;
2833 119 unneback 
   reg [data_width-1:0] ram [0:mem_size-1] /*synthesis syn_ramstyle = "no_rw_check"*/;
2834 100 unneback 
    parameter memory_init = 0;
2835 
    parameter memory_file = "vl_ram.vmem";
2836 
    parameter debug = 0;
2837 
    generate
2838 
    if (memory_init == 1) begin : init_mem
2839 
        initial
2840 
            $readmemh(memory_file, ram);
2841 
    end else if (memory_init == 2) begin : init_zero
2842 
        integer k;
2843 
        initial
2844 
            for (k = 0; k < mem_size; k = k + 1)
2845 
                ram[k] = 0;
2846 
    end
2847 
   endgenerate
2848 
    generate
2849 
    if (debug==1) begin : debug_we
2850 
        always @ (posedge clk_a)
2851 
        if (we_a)
2852 
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
2853 
        always @ (posedge clk_b)
2854 
        if (we_b)
2855 
            $display ("Debug: Value %h written at address %h : time %t", d_b, adr_b, $time);
2856 
    end
2857 
    endgenerate
2858 
   always @ (posedge clk_a)
2859 
     begin
2860 
        q_a <= ram[adr_a];
2861 
        if (we_a)
2862 
             ram[adr_a] <= d_a;
2863 
     end
2864 
   always @ (posedge clk_b)
2865 
     begin
2866 
        if (we_b)
2867 
          ram[adr_b] <= d_b;
2868 
     end
2869 
endmodule
2870 7 unneback 
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
2871 6 unneback 
   parameter data_width = 32;
2872 
   parameter addr_width = 8;
2873 75 unneback 
   parameter mem_size = 1<<addr_width;
2874 6 unneback 
   input [(data_width-1):0]      d_a;
2875 
   input [(addr_width-1):0]       adr_a;
2876 
   input [(addr_width-1):0]       adr_b;
2877 
   input                         we_a;
2878 
   output [(data_width-1):0]      q_b;
2879 
   input [(data_width-1):0]       d_b;
2880 
   output reg [(data_width-1):0] q_a;
2881 
   input                         we_b;
2882 
   input                         clk_a, clk_b;
2883 
   reg [(data_width-1):0]         q_b;
2884 119 unneback 
   reg [data_width-1:0] ram [0:mem_size-1] /*synthesis syn_ramstyle = "no_rw_check"*/;
2885 100 unneback 
    parameter memory_init = 0;
2886 
    parameter memory_file = "vl_ram.vmem";
2887 
    parameter debug = 0;
2888 
    generate
2889 
    if (memory_init) begin : init_mem
2890 
        initial
2891 
            $readmemh(memory_file, ram);
2892 
    end else if (memory_init == 2) begin : init_zero
2893 
        integer k;
2894 
        initial
2895 
            for (k = 0; k < mem_size; k = k + 1)
2896 
                ram[k] = 0;
2897 
    end
2898 7 unneback 
   endgenerate
2899 100 unneback 
    generate
2900 
    if (debug==1) begin : debug_we
2901 
        always @ (posedge clk_a)
2902 
        if (we_a)
2903 
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
2904 
        always @ (posedge clk_b)
2905 
        if (we_b)
2906 
            $display ("Debug: Value %h written at address %h : time %t", d_b, adr_b, $time);
2907 
    end
2908 
    endgenerate
2909 6 unneback 
   always @ (posedge clk_a)
2910 
     begin
2911 
        q_a <= ram[adr_a];
2912 
        if (we_a)
2913 
             ram[adr_a] <= d_a;
2914 
     end
2915 
   always @ (posedge clk_b)
2916 
     begin
2917 
        q_b <= ram[adr_b];
2918 
        if (we_b)
2919 
          ram[adr_b] <= d_b;
2920 
     end
2921 
endmodule
2922 92 unneback 
module vl_dpram_be_2r2w ( d_a, q_a, adr_a, be_a, we_a, clk_a, d_b, q_b, adr_b, be_b, we_b, clk_b );
2923 75 unneback 
   parameter a_data_width = 32;
2924 
   parameter a_addr_width = 8;
2925 95 unneback 
   parameter b_data_width = 64; //a_data_width;
2926 124 unneback 
   //localparam b_addr_width = a_data_width * a_addr_width / b_data_width;
2927 
   localparam b_addr_width =
2928 125 unneback 
        (a_data_width==b_data_width) ? a_addr_width :
2929 
        (a_data_width==b_data_width*2) ? a_addr_width+1 :
2930 
        (a_data_width==b_data_width*4) ? a_addr_width+2 :
2931 
        (a_data_width==b_data_width*8) ? a_addr_width+3 :
2932 
        (a_data_width==b_data_width*16) ? a_addr_width+4 :
2933 
        (a_data_width==b_data_width*32) ? a_addr_width+5 :
2934 
        (a_data_width==b_data_width/2) ? a_addr_width-1 :
2935 
        (a_data_width==b_data_width/4) ? a_addr_width-2 :
2936 
        (a_data_width==b_data_width/8) ? a_addr_width-3 :
2937 
        (a_data_width==b_data_width/16) ? a_addr_width-4 :
2938 
        (a_data_width==b_data_width/32) ? a_addr_width-5 : 0;
2939 95 unneback 
   localparam ratio = (a_addr_width>b_addr_width) ? (a_addr_width/b_addr_width) : (b_addr_width/a_addr_width);
2940 
   parameter mem_size = (a_addr_width>b_addr_width) ? (1<<b_addr_width) : (1<<a_addr_width);
2941 100 unneback 
   parameter memory_init = 0;
2942 95 unneback 
   parameter memory_file = "vl_ram.vmem";
2943 100 unneback 
   parameter debug = 0;
2944 75 unneback 
   input [(a_data_width-1):0]      d_a;
2945 91 unneback 
   input [(a_addr_width-1):0]       adr_a;
2946 
   input [(a_data_width/8-1):0]    be_a;
2947 
   input                           we_a;
2948 75 unneback 
   output reg [(a_data_width-1):0] q_a;
2949 91 unneback 
   input [(b_data_width-1):0]       d_b;
2950 
   input [(b_addr_width-1):0]       adr_b;
2951 92 unneback 
   input [(b_data_width/8-1):0]    be_b;
2952 
   input                           we_b;
2953 
   output reg [(b_data_width-1):0]          q_b;
2954 91 unneback 
   input                           clk_a, clk_b;
2955 100 unneback 
    generate
2956 
    if (debug==1) begin : debug_we
2957 
        always @ (posedge clk_a)
2958 
        if (we_a)
2959 
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
2960 
        always @ (posedge clk_b)
2961 
        if (we_b)
2962 
            $display ("Debug: Value %h written at address %h : time %t", d_b, adr_b, $time);
2963 
    end
2964 
    endgenerate
2965 91 unneback 
`ifdef SYSTEMVERILOG
2966 
// use a multi-dimensional packed array
2967 
//to model individual bytes within the word
2968 75 unneback 
generate
2969 91 unneback 
if (a_data_width==32 & b_data_width==32) begin : dpram_3232
2970 98 unneback 
    logic [0:3][7:0] ram [0:mem_size-1] /*synthesis syn_ramstyle = "no_rw_check"*/;
2971 95 unneback 
    initial
2972 100 unneback 
        if (memory_init==1)
2973 95 unneback 
            $readmemh(memory_file, ram);
2974 100 unneback 
    integer k;
2975 
    initial
2976 
        if (memory_init==2)
2977 
            for (k = 0; k < mem_size; k = k + 1)
2978 
                ram[k] = 0;
2979 91 unneback 
    always_ff@(posedge clk_a)
2980 
    begin
2981 
        if(we_a) begin
2982 100 unneback 
            if(be_a[3]) ram[adr_a][0] <= d_a[31:24];
2983 
            if(be_a[2]) ram[adr_a][1] <= d_a[23:16];
2984 
            if(be_a[1]) ram[adr_a][2] <= d_a[15:8];
2985 
            if(be_a[0]) ram[adr_a][3] <= d_a[7:0];
2986 91 unneback 
        end
2987 
    end
2988 92 unneback 
    always@(posedge clk_a)
2989 
        q_a = ram[adr_a];
2990 91 unneback 
    always_ff@(posedge clk_b)
2991 92 unneback 
    begin
2992 
        if(we_b) begin
2993 100 unneback 
            if(be_b[3]) ram[adr_b][0] <= d_b[31:24];
2994 
            if(be_b[2]) ram[adr_b][1] <= d_b[23:16];
2995 
            if(be_b[1]) ram[adr_b][2] <= d_b[15:8];
2996 
            if(be_b[0]) ram[adr_b][3] <= d_b[7:0];
2997 92 unneback 
        end
2998 
    end
2999 
    always@(posedge clk_b)
3000 
        q_b = ram[adr_b];
3001 75 unneback 
end
3002 
endgenerate
3003 95 unneback 
generate
3004 
if (a_data_width==64 & b_data_width==64) begin : dpram_6464
3005 98 unneback 
    logic [0:7][7:0] ram [0:mem_size-1] /*synthesis syn_ramstyle = "no_rw_check"*/;
3006 95 unneback 
    initial
3007 100 unneback 
        if (memory_init==1)
3008 95 unneback 
            $readmemh(memory_file, ram);
3009 100 unneback 
    integer k;
3010 
    initial
3011 
        if (memory_init==2)
3012 
            for (k = 0; k < mem_size; k = k + 1)
3013 
                ram[k] = 0;
3014 95 unneback 
    always_ff@(posedge clk_a)
3015 
    begin
3016 
        if(we_a) begin
3017 
            if(be_a[7]) ram[adr_a][7] <= d_a[63:56];
3018 
            if(be_a[6]) ram[adr_a][6] <= d_a[55:48];
3019 
            if(be_a[5]) ram[adr_a][5] <= d_a[47:40];
3020 
            if(be_a[4]) ram[adr_a][4] <= d_a[39:32];
3021 
            if(be_a[3]) ram[adr_a][3] <= d_a[31:24];
3022 
            if(be_a[2]) ram[adr_a][2] <= d_a[23:16];
3023 
            if(be_a[1]) ram[adr_a][1] <= d_a[15:8];
3024 
            if(be_a[0]) ram[adr_a][0] <= d_a[7:0];
3025 
        end
3026 
    end
3027 
    always@(posedge clk_a)
3028 
        q_a = ram[adr_a];
3029 
    always_ff@(posedge clk_b)
3030 
    begin
3031 
        if(we_b) begin
3032 
            if(be_b[7]) ram[adr_b][7] <= d_b[63:56];
3033 
            if(be_b[6]) ram[adr_b][6] <= d_b[55:48];
3034 
            if(be_b[5]) ram[adr_b][5] <= d_b[47:40];
3035 
            if(be_b[4]) ram[adr_b][4] <= d_b[39:32];
3036 
            if(be_b[3]) ram[adr_b][3] <= d_b[31:24];
3037 
            if(be_b[2]) ram[adr_b][2] <= d_b[23:16];
3038 
            if(be_b[1]) ram[adr_b][1] <= d_b[15:8];
3039 
            if(be_b[0]) ram[adr_b][0] <= d_b[7:0];
3040 
        end
3041 
    end
3042 
    always@(posedge clk_b)
3043 
        q_b = ram[adr_b];
3044 
end
3045 
endgenerate
3046 
generate
3047 
if (a_data_width==32 & b_data_width==16) begin : dpram_3216
3048 
logic [31:0] temp;
3049 128 unneback 
vl_dpram_be_2r2w # (.a_data_width(32), .b_data_width(32), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file))
3050 
dpram3232 (
3051 95 unneback 
    .d_a(d_a),
3052 
    .q_a(q_a),
3053 
    .adr_a(adr_a),
3054 
    .be_a(be_a),
3055 
    .we_a(we_a),
3056 
    .clk_a(clk_a),
3057 
    .d_b({d_b,d_b}),
3058 
    .q_b(temp),
3059 128 unneback 
    .adr_b(adr_b[b_addr_width-1:1]),
3060 137 unneback 
    .be_b({be_b,be_b} & {{2{!adr_b[0]}},{2{adr_b[0]}}}),
3061 95 unneback 
    .we_b(we_b),
3062 
    .clk_b(clk_b)
3063 
);
3064 100 unneback 
always @ (adr_b[0] or temp)
3065 95 unneback 
    if (adr_b[0])
3066 
        q_b = temp[31:16];
3067 
    else
3068 
        q_b = temp[15:0];
3069 
end
3070 
endgenerate
3071 
generate
3072 
if (a_data_width==32 & b_data_width==64) begin : dpram_3264
3073 
logic [63:0] temp;
3074 128 unneback 
vl_dpram_be_2r2w # (.a_data_width(32), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file))
3075 95 unneback 
dpram6464 (
3076 
    .d_a({d_a,d_a}),
3077 
    .q_a(temp),
3078 
    .adr_a(adr_a[a_addr_width-1:1]),
3079 
    .be_a({be_a,be_a} & {{4{adr_a[0]}},{4{!adr_a[0]}}}),
3080 
    .we_a(we_a),
3081 
    .clk_a(clk_a),
3082 
    .d_b(d_b),
3083 
    .q_b(q_b),
3084 
    .adr_b(adr_b),
3085 
    .be_b(be_b),
3086 
    .we_b(we_b),
3087 
    .clk_b(clk_b)
3088 
);
3089 100 unneback 
always @ (adr_a[0] or temp)
3090 95 unneback 
    if (adr_a[0])
3091 
        q_a = temp[63:32];
3092 
    else
3093 
        q_a = temp[31:0];
3094 
end
3095 
endgenerate
3096 91 unneback 
`else
3097 92 unneback 
    // This modules requires SystemVerilog
3098 98 unneback 
    // at this point anyway
3099 91 unneback 
`endif
3100 75 unneback 
endmodule
3101 6 unneback 
// FIFO
3102 25 unneback 
module vl_fifo_1r1w_fill_level_sync (
3103 
    d, wr, fifo_full,
3104 
    q, rd, fifo_empty,
3105 
    fill_level,
3106 
    clk, rst
3107 
    );
3108 
parameter data_width = 18;
3109 
parameter addr_width = 4;
3110 
// write side
3111 
input  [data_width-1:0] d;
3112 
input                   wr;
3113 
output                  fifo_full;
3114 
// read side
3115 
output [data_width-1:0] q;
3116 
input                   rd;
3117 
output                  fifo_empty;
3118 
// common
3119 
output [addr_width:0]   fill_level;
3120 
input rst, clk;
3121 
wire [addr_width:1] wadr, radr;
3122 
vl_cnt_bin_ce
3123 
    # ( .length(addr_width))
3124 
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
3125 
vl_cnt_bin_ce
3126 
    # (.length(addr_width))
3127 
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
3128 
vl_dpram_1r1w
3129 
    # (.data_width(data_width), .addr_width(addr_width))
3130 
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
3131 31 unneback 
vl_cnt_bin_ce_rew_q_zq_l1
3132 27 unneback 
    # (.length(addr_width+1), .level1_value(1<<addr_width))
3133 25 unneback 
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
3134 
endmodule
3135 27 unneback 
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
3136 
// RAM is supposed to be larger than the two FIFOs
3137 
// LFSR counters used adr pointers
3138 
module vl_fifo_2r2w_sync_simplex (
3139 
    // a side
3140 
    a_d, a_wr, a_fifo_full,
3141 
    a_q, a_rd, a_fifo_empty,
3142 
    a_fill_level,
3143 
    // b side
3144 
    b_d, b_wr, b_fifo_full,
3145 
    b_q, b_rd, b_fifo_empty,
3146 
    b_fill_level,
3147 
    // common
3148 
    clk, rst
3149 
    );
3150 
parameter data_width = 8;
3151 
parameter addr_width = 5;
3152 
parameter fifo_full_level = (1<<addr_width)-1;
3153 
// a side
3154 
input  [data_width-1:0] a_d;
3155 
input                   a_wr;
3156 
output                  a_fifo_full;
3157 
output [data_width-1:0] a_q;
3158 
input                   a_rd;
3159 
output                  a_fifo_empty;
3160 
output [addr_width-1:0] a_fill_level;
3161 
// b side
3162 
input  [data_width-1:0] b_d;
3163 
input                   b_wr;
3164 
output                  b_fifo_full;
3165 
output [data_width-1:0] b_q;
3166 
input                   b_rd;
3167 
output                  b_fifo_empty;
3168 
output [addr_width-1:0] b_fill_level;
3169 
input                   clk;
3170 
input                   rst;
3171 
// adr_gen
3172 
wire [addr_width:1] a_wadr, a_radr;
3173 
wire [addr_width:1] b_wadr, b_radr;
3174 
// dpram
3175 
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
3176 
vl_cnt_lfsr_ce
3177 
    # ( .length(addr_width))
3178 
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
3179 
vl_cnt_lfsr_ce
3180 
    # (.length(addr_width))
3181 
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
3182 
vl_cnt_lfsr_ce
3183 
    # ( .length(addr_width))
3184 
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
3185 
vl_cnt_lfsr_ce
3186 
    # (.length(addr_width))
3187 
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
3188 
// mux read or write adr to DPRAM
3189 
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
3190 
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
3191 
vl_dpram_2r2w
3192 
    # (.data_width(data_width), .addr_width(addr_width+1))
3193 
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
3194 
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
3195 
vl_cnt_bin_ce_rew_zq_l1
3196 28 unneback 
    # (.length(addr_width), .level1_value(fifo_full_level))
3197 27 unneback 
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
3198 
vl_cnt_bin_ce_rew_zq_l1
3199 28 unneback 
    # (.length(addr_width), .level1_value(fifo_full_level))
3200 27 unneback 
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
3201 
endmodule
3202 6 unneback 
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
3203 11 unneback 
   parameter addr_width = 4;
3204 
   parameter N = addr_width-1;
3205 6 unneback 
   parameter Q1 = 2'b00;
3206 
   parameter Q2 = 2'b01;
3207 
   parameter Q3 = 2'b11;
3208 
   parameter Q4 = 2'b10;
3209 
   parameter going_empty = 1'b0;
3210 
   parameter going_full  = 1'b1;
3211 
   input [N:0]  wptr, rptr;
3212 14 unneback 
   output       fifo_empty;
3213 6 unneback 
   output       fifo_full;
3214 
   input        wclk, rclk, rst;
3215 
   wire direction;
3216 
   reg  direction_set, direction_clr;
3217 
   wire async_empty, async_full;
3218 
   wire fifo_full2;
3219 14 unneback 
   wire fifo_empty2;
3220 6 unneback 
   // direction_set
3221 
   always @ (wptr[N:N-1] or rptr[N:N-1])
3222 
     case ({wptr[N:N-1],rptr[N:N-1]})
3223 
       {Q1,Q2} : direction_set <= 1'b1;
3224 
       {Q2,Q3} : direction_set <= 1'b1;
3225 
       {Q3,Q4} : direction_set <= 1'b1;
3226 
       {Q4,Q1} : direction_set <= 1'b1;
3227 
       default : direction_set <= 1'b0;
3228 
     endcase
3229 
   // direction_clear
3230 
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
3231 
     if (rst)
3232 
       direction_clr <= 1'b1;
3233 
     else
3234 
       case ({wptr[N:N-1],rptr[N:N-1]})
3235 
         {Q2,Q1} : direction_clr <= 1'b1;
3236 
         {Q3,Q2} : direction_clr <= 1'b1;
3237 
         {Q4,Q3} : direction_clr <= 1'b1;
3238 
         {Q1,Q4} : direction_clr <= 1'b1;
3239 
         default : direction_clr <= 1'b0;
3240 
       endcase
3241 18 unneback 
    vl_dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
3242 6 unneback 
   assign async_empty = (wptr == rptr) && (direction==going_empty);
3243 
   assign async_full  = (wptr == rptr) && (direction==going_full);
3244 18 unneback 
    vl_dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
3245 
    vl_dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
3246 6 unneback 
/*
3247 
   always @ (posedge wclk or posedge rst or posedge async_full)
3248 
     if (rst)
3249 
       {fifo_full, fifo_full2} <= 2'b00;
3250 
     else if (async_full)
3251 
       {fifo_full, fifo_full2} <= 2'b11;
3252 
     else
3253 
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
3254 
*/
3255 14 unneback 
/*   always @ (posedge rclk or posedge async_empty)
3256 6 unneback 
     if (async_empty)
3257 
       {fifo_empty, fifo_empty2} <= 2'b11;
3258 
     else
3259 14 unneback 
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
3260 18 unneback 
    vl_dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
3261 
    vl_dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
3262 27 unneback 
endmodule // async_compb
3263 6 unneback 
module vl_fifo_1r1w_async (
3264 
    d, wr, fifo_full, wr_clk, wr_rst,
3265 
    q, rd, fifo_empty, rd_clk, rd_rst
3266 
    );
3267 
parameter data_width = 18;
3268 
parameter addr_width = 4;
3269 
// write side
3270 
input  [data_width-1:0] d;
3271 
input                   wr;
3272 
output                  fifo_full;
3273 
input                   wr_clk;
3274 
input                   wr_rst;
3275 
// read side
3276 
output [data_width-1:0] q;
3277 
input                   rd;
3278 
output                  fifo_empty;
3279 
input                   rd_clk;
3280 
input                   rd_rst;
3281 
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
3282 18 unneback 
vl_cnt_gray_ce_bin
3283 6 unneback 
    # ( .length(addr_width))
3284 
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
3285 18 unneback 
vl_cnt_gray_ce_bin
3286 6 unneback 
    # (.length(addr_width))
3287 23 unneback 
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
3288 7 unneback 
vl_dpram_1r1w
3289 6 unneback 
    # (.data_width(data_width), .addr_width(addr_width))
3290 
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
3291 
vl_fifo_cmp_async
3292 
    # (.addr_width(addr_width))
3293 
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
3294 
endmodule
3295 8 unneback 
module vl_fifo_2r2w_async (
3296 6 unneback 
    // a side
3297 
    a_d, a_wr, a_fifo_full,
3298 
    a_q, a_rd, a_fifo_empty,
3299 
    a_clk, a_rst,
3300 
    // b side
3301 
    b_d, b_wr, b_fifo_full,
3302 
    b_q, b_rd, b_fifo_empty,
3303 
    b_clk, b_rst
3304 
    );
3305 
parameter data_width = 18;
3306 
parameter addr_width = 4;
3307 
// a side
3308 
input  [data_width-1:0] a_d;
3309 
input                   a_wr;
3310 
output                  a_fifo_full;
3311 
output [data_width-1:0] a_q;
3312 
input                   a_rd;
3313 
output                  a_fifo_empty;
3314 
input                   a_clk;
3315 
input                   a_rst;
3316 
// b side
3317 
input  [data_width-1:0] b_d;
3318 
input                   b_wr;
3319 
output                  b_fifo_full;
3320 
output [data_width-1:0] b_q;
3321 
input                   b_rd;
3322 
output                  b_fifo_empty;
3323 
input                   b_clk;
3324 
input                   b_rst;
3325 
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
3326 
vl_fifo_1r1w_async_a (
3327 
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
3328 
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
3329 
    );
3330 
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
3331 
vl_fifo_1r1w_async_b (
3332 
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
3333 
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
3334 
    );
3335 
endmodule
3336 8 unneback 
module vl_fifo_2r2w_async_simplex (
3337 6 unneback 
    // a side
3338 
    a_d, a_wr, a_fifo_full,
3339 
    a_q, a_rd, a_fifo_empty,
3340 
    a_clk, a_rst,
3341 
    // b side
3342 
    b_d, b_wr, b_fifo_full,
3343 
    b_q, b_rd, b_fifo_empty,
3344 
    b_clk, b_rst
3345 
    );
3346 
parameter data_width = 18;
3347 
parameter addr_width = 4;
3348 
// a side
3349 
input  [data_width-1:0] a_d;
3350 
input                   a_wr;
3351 
output                  a_fifo_full;
3352 
output [data_width-1:0] a_q;
3353 
input                   a_rd;
3354 
output                  a_fifo_empty;
3355 
input                   a_clk;
3356 
input                   a_rst;
3357 
// b side
3358 
input  [data_width-1:0] b_d;
3359 
input                   b_wr;
3360 
output                  b_fifo_full;
3361 
output [data_width-1:0] b_q;
3362 
input                   b_rd;
3363 
output                  b_fifo_empty;
3364 
input                   b_clk;
3365 
input                   b_rst;
3366 
// adr_gen
3367 
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
3368 
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
3369 
// dpram
3370 
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
3371 18 unneback 
vl_cnt_gray_ce_bin
3372 6 unneback 
    # ( .length(addr_width))
3373 
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
3374 18 unneback 
vl_cnt_gray_ce_bin
3375 6 unneback 
    # (.length(addr_width))
3376 
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
3377 18 unneback 
vl_cnt_gray_ce_bin
3378 6 unneback 
    # ( .length(addr_width))
3379 
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
3380 18 unneback 
vl_cnt_gray_ce_bin
3381 6 unneback 
    # (.length(addr_width))
3382 
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
3383 
// mux read or write adr to DPRAM
3384 
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
3385 
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
3386 11 unneback 
vl_dpram_2r2w
3387 6 unneback 
    # (.data_width(data_width), .addr_width(addr_width+1))
3388 
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
3389 
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
3390 11 unneback 
vl_fifo_cmp_async
3391 6 unneback 
    # (.addr_width(addr_width))
3392 
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
3393 11 unneback 
vl_fifo_cmp_async
3394 6 unneback 
    # (.addr_width(addr_width))
3395 
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
3396 
endmodule
3397 48 unneback 
module vl_reg_file (
3398 
    a1, a2, a3, wd3, we3, rd1, rd2, clk
3399 
);
3400 
parameter data_width = 32;
3401 
parameter addr_width = 5;
3402 
input [addr_width-1:0] a1, a2, a3;
3403 
input [data_width-1:0] wd3;
3404 
input we3;
3405 
output [data_width-1:0] rd1, rd2;
3406 
input clk;
3407 
reg [data_width-1:0] wd3_reg;
3408 
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
3409 
reg we3_reg;
3410 
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
3411 
reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
3412 
always @ (posedge clk or posedge rst)
3413 
if (rst)
3414 
    {wd3_reg, a3_reg, we3_reg} <= {(data_width+addr_width+1){1'b0}};
3415 
else
3416 
    {wd3_reg, a3_reg, we3_reg} <= {wd3,a3,wd3};
3417 
    always @ (negedge clk)
3418 
    if (we3_reg)
3419 
        ram1[a3_reg] <= wd3;
3420 
    always @ (posedge clk)
3421 
        a1_reg <= a1;
3422 
    assign rd1 = ram1[a1_reg];
3423 
    always @ (negedge clk)
3424 
    if (we3_reg)
3425 
        ram2[a3_reg] <= wd3;
3426 
    always @ (posedge clk)
3427 
        a2_reg <= a2;
3428 
    assign rd2 = ram2[a2_reg];
3429 
endmodule
3430 12 unneback 
//////////////////////////////////////////////////////////////////////
3431 
////                                                              ////
3432 
////  Versatile library, wishbone stuff                           ////
3433 
////                                                              ////
3434 
////  Description                                                 ////
3435 
////  Wishbone compliant modules                                  ////
3436 
////                                                              ////
3437 
////                                                              ////
3438 
////  To Do:                                                      ////
3439 
////   -                                                          ////
3440 
////                                                              ////
3441 
////  Author(s):                                                  ////
3442 
////      - Michael Unneback, unneback@opencores.org              ////
3443 
////        ORSoC AB                                              ////
3444 
////                                                              ////
3445 
//////////////////////////////////////////////////////////////////////
3446 
////                                                              ////
3447 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
3448 
////                                                              ////
3449 
//// This source file may be used and distributed without         ////
3450 
//// restriction provided that this copyright statement is not    ////
3451 
//// removed from the file and that any derivative work contains  ////
3452 
//// the original copyright notice and the associated disclaimer. ////
3453 
////                                                              ////
3454 
//// This source file is free software; you can redistribute it   ////
3455 
//// and/or modify it under the terms of the GNU Lesser General   ////
3456 
//// Public License as published by the Free Software Foundation; ////
3457 
//// either version 2.1 of the License, or (at your option) any   ////
3458 
//// later version.                                               ////
3459 
////                                                              ////
3460 
//// This source is distributed in the hope that it will be       ////
3461 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3462 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3463 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3464 
//// details.                                                     ////
3465 
////                                                              ////
3466 
//// You should have received a copy of the GNU Lesser General    ////
3467 
//// Public License along with this source; if not, download it   ////
3468 
//// from http://www.opencores.org/lgpl.shtml                     ////
3469 
////                                                              ////
3470 
//////////////////////////////////////////////////////////////////////
3471 
`timescale 1ns/1ns
3472 85 unneback 
module vl_wb_adr_inc ( cyc_i, stb_i, cti_i, bte_i, adr_i, we_i, ack_o, adr_o, clk, rst);
3473 83 unneback 
parameter adr_width = 10;
3474 
parameter max_burst_width = 4;
3475 85 unneback 
input cyc_i, stb_i, we_i;
3476 83 unneback 
input [2:0] cti_i;
3477 
input [1:0] bte_i;
3478 
input [adr_width-1:0] adr_i;
3479 
output [adr_width-1:0] adr_o;
3480 
output ack_o;
3481 
input clk, rst;
3482 
reg [adr_width-1:0] adr;
3483 90 unneback 
wire [max_burst_width-1:0] to_adr;
3484 91 unneback 
reg [max_burst_width-1:0] last_adr;
3485 92 unneback 
reg last_cycle;
3486 
localparam idle_or_eoc = 1'b0;
3487 
localparam cyc_or_ws   = 1'b1;
3488 91 unneback 
always @ (posedge clk or posedge rst)
3489 
if (rst)
3490 
    last_adr <= {max_burst_width{1'b0}};
3491 
else
3492 
    if (stb_i)
3493 92 unneback 
        last_adr <=adr_o[max_burst_width-1:0];
3494 83 unneback 
generate
3495 
if (max_burst_width==0) begin : inst_0
3496 97 unneback 
        reg ack_o;
3497 
        assign adr_o = adr_i;
3498 
        always @ (posedge clk or posedge rst)
3499 
        if (rst)
3500 
            ack_o <= 1'b0;
3501 
        else
3502 
            ack_o <= cyc_i & stb_i & !ack_o;
3503 83 unneback 
end else begin
3504 
    always @ (posedge clk or posedge rst)
3505 
    if (rst)
3506 92 unneback 
        last_cycle <= idle_or_eoc;
3507 83 unneback 
    else
3508 92 unneback 
        last_cycle <= (!cyc_i) ? idle_or_eoc : //idle
3509 
                      (cyc_i & ack_o & (cti_i==3'b000 | cti_i==3'b111)) ? idle_or_eoc : // eoc
3510 
                      (cyc_i & !stb_i) ? cyc_or_ws : //ws
3511 
                      cyc_or_ws; // cyc
3512 
    assign to_adr = (last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
3513 85 unneback 
    assign adr_o[max_burst_width-1:0] = (we_i) ? adr_i[max_burst_width-1:0] :
3514 91 unneback 
                                        (!stb_i) ? last_adr :
3515 92 unneback 
                                        (last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] :
3516 85 unneback 
                                        adr[max_burst_width-1:0];
3517 92 unneback 
    assign ack_o = (last_cycle==cyc_or_ws) & stb_i;
3518 83 unneback 
end
3519 
endgenerate
3520 
generate
3521 
if (max_burst_width==2) begin : inst_2
3522 
    always @ (posedge clk or posedge rst)
3523 
    if (rst)
3524 
        adr <= 2'h0;
3525 
    else
3526 
        if (cyc_i & stb_i)
3527 
            adr[1:0] <= to_adr[1:0] + 2'd1;
3528 
        else
3529 
            adr <= to_adr[1:0];
3530 
end
3531 
endgenerate
3532 
generate
3533 
if (max_burst_width==3) begin : inst_3
3534 
    always @ (posedge clk or posedge rst)
3535 
    if (rst)
3536 
        adr <= 3'h0;
3537 
    else
3538 
        if (cyc_i & stb_i)
3539 
            case (bte_i)
3540 
            2'b01: adr[2:0] <= {to_adr[2],to_adr[1:0] + 2'd1};
3541 
            default: adr[3:0] <= to_adr[2:0] + 3'd1;
3542 
            endcase
3543 
        else
3544 
            adr <= to_adr[2:0];
3545 
end
3546 
endgenerate
3547 
generate
3548 
if (max_burst_width==4) begin : inst_4
3549 
    always @ (posedge clk or posedge rst)
3550 
    if (rst)
3551 
        adr <= 4'h0;
3552 
    else
3553 91 unneback 
        if (stb_i) // | (!stb_i & last_cycle!=ws)) // for !stb_i restart with adr_i +1, only inc once
3554 83 unneback 
            case (bte_i)
3555 
            2'b01: adr[3:0] <= {to_adr[3:2],to_adr[1:0] + 2'd1};
3556 
            2'b10: adr[3:0] <= {to_adr[3],to_adr[2:0] + 3'd1};
3557 
            default: adr[3:0] <= to_adr + 4'd1;
3558 
            endcase
3559 
        else
3560 
            adr <= to_adr[3:0];
3561 
end
3562 
endgenerate
3563 
generate
3564 
if (adr_width > max_burst_width) begin : pass_through
3565 
    assign adr_o[adr_width-1:max_burst_width] = adr_i[adr_width-1:max_burst_width];
3566 
end
3567 
endgenerate
3568 
endmodule
3569 
// async wb3 - wb3 bridge
3570 
`timescale 1ns/1ns
3571 18 unneback 
module vl_wb3wb3_bridge (
3572 12 unneback 
        // wishbone slave side
3573 
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
3574 
        // wishbone master side
3575 
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
3576 95 unneback 
parameter style = "FIFO"; // valid: simple, FIFO
3577 
parameter addr_width = 4;
3578 12 unneback 
input [31:0] wbs_dat_i;
3579 
input [31:2] wbs_adr_i;
3580 
input [3:0]  wbs_sel_i;
3581 
input [1:0]  wbs_bte_i;
3582 
input [2:0]  wbs_cti_i;
3583 
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
3584 
output [31:0] wbs_dat_o;
3585 14 unneback 
output wbs_ack_o;
3586 12 unneback 
input wbs_clk, wbs_rst;
3587 
output [31:0] wbm_dat_o;
3588 
output reg [31:2] wbm_adr_o;
3589 
output [3:0]  wbm_sel_o;
3590 
output reg [1:0]  wbm_bte_o;
3591 
output reg [2:0]  wbm_cti_o;
3592 14 unneback 
output reg wbm_we_o;
3593 
output wbm_cyc_o;
3594 12 unneback 
output wbm_stb_o;
3595 
input [31:0]  wbm_dat_i;
3596 
input wbm_ack_i;
3597 
input wbm_clk, wbm_rst;
3598 
// bte
3599 
parameter linear       = 2'b00;
3600 
parameter wrap4        = 2'b01;
3601 
parameter wrap8        = 2'b10;
3602 
parameter wrap16       = 2'b11;
3603 
// cti
3604 
parameter classic      = 3'b000;
3605 
parameter incburst     = 3'b010;
3606 
parameter endofburst   = 3'b111;
3607 95 unneback 
localparam wbs_adr  = 1'b0;
3608 
localparam wbs_data = 1'b1;
3609 
localparam wbm_adr0      = 2'b00;
3610 
localparam wbm_adr1      = 2'b01;
3611 
localparam wbm_data      = 2'b10;
3612 
localparam wbm_data_wait = 2'b11;
3613 12 unneback 
reg [1:0] wbs_bte_reg;
3614 
reg wbs;
3615 
wire wbs_eoc_alert, wbm_eoc_alert;
3616 
reg wbs_eoc, wbm_eoc;
3617 
reg [1:0] wbm;
3618 14 unneback 
wire [1:16] wbs_count, wbm_count;
3619 12 unneback 
wire [35:0] a_d, a_q, b_d, b_q;
3620 
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
3621 
reg a_rd_reg;
3622 
wire b_rd_adr, b_rd_data;
3623 14 unneback 
wire b_rd_data_reg;
3624 
wire [35:0] temp;
3625 12 unneback 
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
3626 
always @ (posedge wbs_clk or posedge wbs_rst)
3627 
if (wbs_rst)
3628 
        wbs_eoc <= 1'b0;
3629 
else
3630 
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
3631 78 unneback 
                wbs_eoc <= (wbs_bte_i==linear) | (wbs_cti_i==3'b111);
3632 12 unneback 
        else if (wbs_eoc_alert & (a_rd | a_wr))
3633 
                wbs_eoc <= 1'b1;
3634 18 unneback 
vl_cnt_shreg_ce_clear # ( .length(16))
3635 12 unneback 
    cnt0 (
3636 
        .cke(wbs_ack_o),
3637 
        .clear(wbs_eoc),
3638 
        .q(wbs_count),
3639 
        .rst(wbs_rst),
3640 
        .clk(wbs_clk));
3641 
always @ (posedge wbs_clk or posedge wbs_rst)
3642 
if (wbs_rst)
3643 
        wbs <= wbs_adr;
3644 
else
3645 75 unneback 
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & a_fifo_empty)
3646 12 unneback 
                wbs <= wbs_data;
3647 
        else if (wbs_eoc & wbs_ack_o)
3648 
                wbs <= wbs_adr;
3649 
// wbs FIFO
3650 75 unneback 
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,((wbs_cti_i==3'b111) ? {2'b00,3'b000} : {wbs_bte_i,wbs_cti_i})} : {wbs_dat_i,wbs_sel_i};
3651 
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & a_fifo_empty :
3652 12 unneback 
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
3653 
              1'b0;
3654 
assign a_rd = !a_fifo_empty;
3655 
always @ (posedge wbs_clk or posedge wbs_rst)
3656 
if (wbs_rst)
3657 
        a_rd_reg <= 1'b0;
3658 
else
3659 
        a_rd_reg <= a_rd;
3660 
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
3661 
assign wbs_dat_o = a_q[35:4];
3662 
always @ (posedge wbs_clk or posedge wbs_rst)
3663 
if (wbs_rst)
3664 13 unneback 
        wbs_bte_reg <= 2'b00;
3665 12 unneback 
else
3666 13 unneback 
        wbs_bte_reg <= wbs_bte_i;
3667 12 unneback 
// wbm FIFO
3668 
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
3669 
always @ (posedge wbm_clk or posedge wbm_rst)
3670 
if (wbm_rst)
3671 
        wbm_eoc <= 1'b0;
3672 
else
3673 
        if (wbm==wbm_adr0 & !b_fifo_empty)
3674 
                wbm_eoc <= b_q[4:3] == linear;
3675 
        else if (wbm_eoc_alert & wbm_ack_i)
3676 
                wbm_eoc <= 1'b1;
3677 
always @ (posedge wbm_clk or posedge wbm_rst)
3678 
if (wbm_rst)
3679 
        wbm <= wbm_adr0;
3680 
else
3681 33 unneback 
/*
3682 12 unneback 
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
3683 
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
3684 
        (wbm==wbm_adr1 & !wbm_we_o) |
3685 
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
3686 
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
3687 33 unneback 
*/
3688 
    case (wbm)
3689 
    wbm_adr0:
3690 
        if (!b_fifo_empty)
3691 
            wbm <= wbm_adr1;
3692 
    wbm_adr1:
3693 
        if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
3694 
            wbm <= wbm_data;
3695 
    wbm_data:
3696 
        if (wbm_ack_i & wbm_eoc)
3697 
            wbm <= wbm_adr0;
3698 
        else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
3699 
            wbm <= wbm_data_wait;
3700 
    wbm_data_wait:
3701 
        if (!b_fifo_empty)
3702 
            wbm <= wbm_data;
3703 
    endcase
3704 12 unneback 
assign b_d = {wbm_dat_i,4'b1111};
3705 
assign b_wr = !wbm_we_o & wbm_ack_i;
3706 
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
3707 
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
3708 
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
3709 33 unneback 
                   (wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
3710 12 unneback 
                   1'b0;
3711 
assign b_rd = b_rd_adr | b_rd_data;
3712 18 unneback 
vl_dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
3713 
vl_dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
3714 12 unneback 
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
3715 18 unneback 
vl_cnt_shreg_ce_clear # ( .length(16))
3716 12 unneback 
    cnt1 (
3717 
        .cke(wbm_ack_i),
3718 
        .clear(wbm_eoc),
3719 
        .q(wbm_count),
3720 
        .rst(wbm_rst),
3721 
        .clk(wbm_clk));
3722 33 unneback 
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
3723 
assign wbm_stb_o = (wbm==wbm_data);
3724 12 unneback 
always @ (posedge wbm_clk or posedge wbm_rst)
3725 
if (wbm_rst)
3726 
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
3727 
else begin
3728 
        if (wbm==wbm_adr0 & !b_fifo_empty)
3729 
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
3730 
        else if (wbm_eoc_alert & wbm_ack_i)
3731 
                wbm_cti_o <= endofburst;
3732 
end
3733 
//async_fifo_dw_simplex_top
3734 
vl_fifo_2r2w_async_simplex
3735 
# ( .data_width(36), .addr_width(addr_width))
3736 
fifo (
3737 
    // a side
3738 
    .a_d(a_d),
3739 
    .a_wr(a_wr),
3740 
    .a_fifo_full(a_fifo_full),
3741 
    .a_q(a_q),
3742 
    .a_rd(a_rd),
3743 
    .a_fifo_empty(a_fifo_empty),
3744 
    .a_clk(wbs_clk),
3745 
    .a_rst(wbs_rst),
3746 
    // b side
3747 
    .b_d(b_d),
3748 
    .b_wr(b_wr),
3749 
    .b_fifo_full(b_fifo_full),
3750 
    .b_q(b_q),
3751 
    .b_rd(b_rd),
3752 
    .b_fifo_empty(b_fifo_empty),
3753 
    .b_clk(wbm_clk),
3754 
    .b_rst(wbm_rst)
3755 
    );
3756 
endmodule
3757 75 unneback 
module vl_wb3avalon_bridge (
3758 
        // wishbone slave side
3759 
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
3760 77 unneback 
        // avalon master side
3761 75 unneback 
        readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst);
3762 85 unneback 
parameter linewrapburst = 1'b0;
3763 75 unneback 
input [31:0] wbs_dat_i;
3764 
input [31:2] wbs_adr_i;
3765 
input [3:0]  wbs_sel_i;
3766 
input [1:0]  wbs_bte_i;
3767 
input [2:0]  wbs_cti_i;
3768 83 unneback 
input wbs_we_i;
3769 
input wbs_cyc_i;
3770 
input wbs_stb_i;
3771 75 unneback 
output [31:0] wbs_dat_o;
3772 
output wbs_ack_o;
3773 
input wbs_clk, wbs_rst;
3774 
input [31:0] readdata;
3775 
output [31:0] writedata;
3776 
output [31:2] address;
3777 
output [3:0]  be;
3778 
output write;
3779 81 unneback 
output read;
3780 75 unneback 
output beginbursttransfer;
3781 
output [3:0] burstcount;
3782 
input readdatavalid;
3783 
input waitrequest;
3784 
input clk;
3785 
input rst;
3786 
wire [1:0] wbm_bte_o;
3787 
wire [2:0] wbm_cti_o;
3788 
wire wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_ack_i;
3789 
reg last_cyc;
3790 79 unneback 
reg [3:0] counter;
3791 82 unneback 
reg read_busy;
3792 75 unneback 
always @ (posedge clk or posedge rst)
3793 
if (rst)
3794 
    last_cyc <= 1'b0;
3795 
else
3796 
    last_cyc <= wbm_cyc_o;
3797 79 unneback 
always @ (posedge clk or posedge rst)
3798 
if (rst)
3799 82 unneback 
    read_busy <= 1'b0;
3800 79 unneback 
else
3801 82 unneback 
    if (read & !waitrequest)
3802 
        read_busy <= 1'b1;
3803 
    else if (wbm_ack_i & wbm_cti_o!=3'b010)
3804 
        read_busy <= 1'b0;
3805 
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o & !read_busy;
3806 75 unneback 
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010;
3807 
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 :
3808 
                    (wbm_bte_o==2'b10) ? 4'd8 :
3809 78 unneback 
                    (wbm_bte_o==2'b11) ? 4'd16:
3810 
                    4'd1;
3811 82 unneback 
assign wbm_ack_i = (readdatavalid) | (write & !waitrequest);
3812 79 unneback 
always @ (posedge clk or posedge rst)
3813 
if (rst) begin
3814 
    counter <= 4'd0;
3815 
end else
3816 80 unneback 
    if (wbm_we_o) begin
3817 
        if (!waitrequest & !last_cyc & wbm_cyc_o) begin
3818 85 unneback 
            counter <= burstcount -4'd1;
3819 80 unneback 
        end else if (waitrequest & !last_cyc & wbm_cyc_o) begin
3820 
            counter <= burstcount;
3821 
        end else if (!waitrequest & wbm_stb_o) begin
3822 
            counter <= counter - 4'd1;
3823 
        end
3824 82 unneback 
    end
3825 81 unneback 
assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o & counter!=4'd0;
3826 77 unneback 
vl_wb3wb3_bridge wbwb3inst (
3827 75 unneback 
    // wishbone slave side
3828 
    .wbs_dat_i(wbs_dat_i),
3829 
    .wbs_adr_i(wbs_adr_i),
3830 
    .wbs_sel_i(wbs_sel_i),
3831 
    .wbs_bte_i(wbs_bte_i),
3832 
    .wbs_cti_i(wbs_cti_i),
3833 
    .wbs_we_i(wbs_we_i),
3834 
    .wbs_cyc_i(wbs_cyc_i),
3835 
    .wbs_stb_i(wbs_stb_i),
3836 
    .wbs_dat_o(wbs_dat_o),
3837 
    .wbs_ack_o(wbs_ack_o),
3838 
    .wbs_clk(wbs_clk),
3839 
    .wbs_rst(wbs_rst),
3840 
    // wishbone master side
3841 
    .wbm_dat_o(writedata),
3842 78 unneback 
    .wbm_adr_o(address),
3843 75 unneback 
    .wbm_sel_o(be),
3844 
    .wbm_bte_o(wbm_bte_o),
3845 
    .wbm_cti_o(wbm_cti_o),
3846 
    .wbm_we_o(wbm_we_o),
3847 
    .wbm_cyc_o(wbm_cyc_o),
3848 
    .wbm_stb_o(wbm_stb_o),
3849 
    .wbm_dat_i(readdata),
3850 
    .wbm_ack_i(wbm_ack_i),
3851 
    .wbm_clk(clk),
3852 
    .wbm_rst(rst));
3853 
endmodule
3854 49 unneback 
// WB RAM with byte enable
3855 101 unneback 
module vl_wb_ram (
3856 69 unneback 
    wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
3857 101 unneback 
    wbs_dat_o, wbs_ack_o, wbs_stall_o, wb_clk, wb_rst);
3858 
parameter adr_width = 16;
3859 
parameter mem_size = 1<<adr_width;
3860 
parameter dat_width = 32;
3861 
parameter max_burst_width = 4; // only used for B3
3862 
parameter mode = "B3"; // valid options: B3, B4
3863 60 unneback 
parameter memory_init = 1;
3864 
parameter memory_file = "vl_ram.vmem";
3865 101 unneback 
input [dat_width-1:0] wbs_dat_i;
3866 
input [adr_width-1:0] wbs_adr_i;
3867 
input [2:0] wbs_cti_i;
3868 
input [1:0] wbs_bte_i;
3869 
input [dat_width/8-1:0] wbs_sel_i;
3870 70 unneback 
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
3871 101 unneback 
output [dat_width-1:0] wbs_dat_o;
3872 70 unneback 
output wbs_ack_o;
3873 101 unneback 
output wbs_stall_o;
3874 71 unneback 
input wb_clk, wb_rst;
3875 101 unneback 
wire [adr_width-1:0] adr;
3876 
wire we;
3877 
generate
3878 
if (mode=="B3") begin : B3_inst
3879 
vl_wb_adr_inc # ( .adr_width(adr_width), .max_burst_width(max_burst_width)) adr_inc0 (
3880 83 unneback 
    .cyc_i(wbs_cyc_i),
3881 
    .stb_i(wbs_stb_i),
3882 
    .cti_i(wbs_cti_i),
3883 
    .bte_i(wbs_bte_i),
3884 
    .adr_i(wbs_adr_i),
3885 85 unneback 
    .we_i(wbs_we_i),
3886 83 unneback 
    .ack_o(wbs_ack_o),
3887 
    .adr_o(adr),
3888 
    .clk(wb_clk),
3889 
    .rst(wb_rst));
3890 101 unneback 
assign we = wbs_we_i & wbs_ack_o;
3891 
end else if (mode=="B4") begin : B4_inst
3892 
reg wbs_ack_o_reg;
3893 
always @ (posedge wb_clk or posedge wb_rst)
3894 
    if (wb_rst)
3895 
        wbs_ack_o_reg <= 1'b0;
3896 
    else
3897 
        wbs_ack_o_reg <= wbs_stb_i & wbs_cyc_i;
3898 
assign wbs_ack_o = wbs_ack_o_reg;
3899 
assign wbs_stall_o = 1'b0;
3900 
assign adr = wbs_adr_i;
3901 
assign we = wbs_we_i & wbs_cyc_i & wbs_stb_i;
3902 
end
3903 
endgenerate
3904 100 unneback 
vl_ram_be # (
3905 
    .data_width(dat_width),
3906 
    .addr_width(adr_width),
3907 
    .mem_size(mem_size),
3908 
    .memory_init(memory_init),
3909 
    .memory_file(memory_file))
3910 
ram0(
3911 101 unneback 
    .d(wbs_dat_i),
3912 
    .adr(adr),
3913 
    .be(wbs_sel_i),
3914 
    .we(we),
3915 
    .q(wbs_dat_o),
3916 100 unneback 
    .clk(wb_clk)
3917 
);
3918 49 unneback 
endmodule
3919 103 unneback 
// A wishbone compliant RAM module that can be placed in front of other memory controllers
3920 
module vl_wb_shadow_ram (
3921 
    wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
3922 
    wbs_dat_o, wbs_ack_o, wbs_stall_o,
3923 
    wbm_dat_o, wbm_adr_o, wbm_cti_o, wbm_bte_o, wbm_sel_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
3924 
    wbm_dat_i, wbm_ack_i, wbm_stall_i,
3925 
    wb_clk, wb_rst);
3926 
parameter dat_width = 32;
3927 
parameter mode = "B4";
3928 
parameter max_burst_width = 4; // only used for B3
3929 
parameter shadow_mem_adr_width = 10;
3930 
parameter shadow_mem_size = 1024;
3931 
parameter shadow_mem_init = 2;
3932 
parameter shadow_mem_file = "vl_ram.v";
3933 
parameter main_mem_adr_width = 24;
3934 
input [dat_width-1:0] wbs_dat_i;
3935 
input [main_mem_adr_width-1:0] wbs_adr_i;
3936 
input [2:0] wbs_cti_i;
3937 
input [1:0] wbs_bte_i;
3938 
input [dat_width/8-1:0] wbs_sel_i;
3939 
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
3940 
output [dat_width-1:0] wbs_dat_o;
3941 
output wbs_ack_o;
3942 
output wbs_stall_o;
3943 
output [dat_width-1:0] wbm_dat_o;
3944 
output [main_mem_adr_width-1:0] wbm_adr_o;
3945 
output [2:0] wbm_cti_o;
3946 
output [1:0] wbm_bte_o;
3947 
output [dat_width/8-1:0] wbm_sel_o;
3948 
output wbm_we_o, wbm_stb_o, wbm_cyc_o;
3949 
input [dat_width-1:0] wbm_dat_i;
3950 
input wbm_ack_i, wbm_stall_i;
3951 
input wb_clk, wb_rst;
3952 
generate
3953 
if (shadow_mem_size>0) begin : shadow_ram_inst
3954 
wire cyc;
3955 
wire [dat_width-1:0] dat;
3956 
wire stall, ack;
3957 
assign cyc = wbs_cyc_i & (wbs_adr_i<=shadow_mem_size);
3958 
vl_wb_ram # (
3959 
    .dat_width(dat_width),
3960 
    .adr_width(shadow_mem_adr_width),
3961 
    .mem_size(shadow_mem_size),
3962 
    .memory_init(shadow_mem_init),
3963 117 unneback 
    .memory_file(shadow_mem_file),
3964 103 unneback 
    .mode(mode))
3965 
shadow_mem0 (
3966 
    .wbs_dat_i(wbs_dat_i),
3967 
    .wbs_adr_i(wbs_adr_i[shadow_mem_adr_width-1:0]),
3968 
    .wbs_sel_i(wbs_sel_i),
3969 
    .wbs_we_i (wbs_we_i),
3970 
    .wbs_bte_i(wbs_bte_i),
3971 
    .wbs_cti_i(wbs_cti_i),
3972 
    .wbs_stb_i(wbs_stb_i),
3973 
    .wbs_cyc_i(cyc),
3974 
    .wbs_dat_o(dat),
3975 
    .wbs_stall_o(stall),
3976 
    .wbs_ack_o(ack),
3977 
    .wb_clk(wb_clk),
3978 
    .wb_rst(wb_rst));
3979 
assign {wbm_dat_o, wbm_adr_o, wbm_cti_o, wbm_bte_o, wbm_sel_o, wbm_we_o, wbm_stb_o} =
3980 
       {wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i};
3981 
assign wbm_cyc_o = wbs_cyc_i & (wbs_adr_i>shadow_mem_size);
3982 
assign wbs_dat_o = (dat & {dat_width{cyc}}) | (wbm_dat_i & {dat_width{wbm_cyc_o}});
3983 
assign wbs_ack_o = (ack & cyc) | (wbm_ack_i & wbm_cyc_o);
3984 
assign wbs_stall_o = (stall & cyc) | (wbm_stall_i & wbm_cyc_o);
3985 
end else begin : no_shadow_ram_inst
3986 
assign {wbm_dat_o, wbm_adr_o, wbm_cti_o, wbm_bte_o, wbm_sel_o, wbm_we_o, wbm_stb_o, wbm_cyc_o} =
3987 
       {wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i};
3988 
assign {wbs_dat_o, wbs_ack_o, wbs_stall_o} = {wbm_dat_i, wbm_ack_i, wbm_stall_i};
3989 
end
3990 
endgenerate
3991 
endmodule
3992 17 unneback 
// WB ROM
3993 48 unneback 
module vl_wb_b4_rom (
3994 
    wb_adr_i, wb_stb_i, wb_cyc_i,
3995 
    wb_dat_o, stall_o, wb_ack_o, wb_clk, wb_rst);
3996 
    parameter dat_width = 32;
3997 
    parameter dat_default = 32'h15000000;
3998 
    parameter adr_width = 32;
3999 
/*
4000 
`ifndef ROM
4001 
`define ROM "rom.v"
4002 
`endif
4003 
*/
4004 
    input [adr_width-1:2]   wb_adr_i;
4005 
    input                   wb_stb_i;
4006 
    input                   wb_cyc_i;
4007 
    output [dat_width-1:0]  wb_dat_o;
4008 
    reg [dat_width-1:0]     wb_dat_o;
4009 
    output                  wb_ack_o;
4010 
    reg                     wb_ack_o;
4011 
    output                  stall_o;
4012 
    input                   wb_clk;
4013 
    input                   wb_rst;
4014 
always @ (posedge wb_clk or posedge wb_rst)
4015 
    if (wb_rst)
4016 
        wb_dat_o <= {dat_width{1'b0}};
4017 
    else
4018 
         case (wb_adr_i[adr_width-1:2])
4019 
`ifdef ROM
4020 
`include `ROM
4021 
`endif
4022 
           default:
4023 
             wb_dat_o <= dat_default;
4024 
         endcase // case (wb_adr_i)
4025 
always @ (posedge wb_clk or posedge wb_rst)
4026 
    if (wb_rst)
4027 
        wb_ack_o <= 1'b0;
4028 
    else
4029 
        wb_ack_o <= wb_stb_i & wb_cyc_i;
4030 
assign stall_o = 1'b0;
4031 
endmodule
4032 
// WB ROM
4033 18 unneback 
module vl_wb_boot_rom (
4034 17 unneback 
    wb_adr_i, wb_stb_i, wb_cyc_i,
4035 18 unneback 
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
4036 
    parameter adr_hi = 31;
4037 
    parameter adr_lo = 28;
4038 
    parameter adr_sel = 4'hf;
4039 
    parameter addr_width = 5;
4040 33 unneback 
/*
4041 17 unneback 
`ifndef BOOT_ROM
4042 
`define BOOT_ROM "boot_rom.v"
4043 
`endif
4044 33 unneback 
*/
4045 18 unneback 
    input [adr_hi:2]    wb_adr_i;
4046 
    input               wb_stb_i;
4047 
    input               wb_cyc_i;
4048 
    output [31:0]        wb_dat_o;
4049 
    output              wb_ack_o;
4050 
    output              hit_o;
4051 
    input               wb_clk;
4052 
    input               wb_rst;
4053 
    wire hit;
4054 
    reg [31:0] wb_dat;
4055 
    reg wb_ack;
4056 
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
4057 17 unneback 
always @ (posedge wb_clk or posedge wb_rst)
4058 
    if (wb_rst)
4059 18 unneback 
        wb_dat <= 32'h15000000;
4060 17 unneback 
    else
4061 18 unneback 
         case (wb_adr_i[addr_width-1:2])
4062 33 unneback 
`ifdef BOOT_ROM
4063 17 unneback 
`include `BOOT_ROM
4064 33 unneback 
`endif
4065 17 unneback 
           /*
4066 
            // Zero r0 and jump to 0x00000100
4067 18 unneback 
 
4068 
            1 : wb_dat <= 32'hA8200000;
4069 
            2 : wb_dat <= 32'hA8C00100;
4070 
            3 : wb_dat <= 32'h44003000;
4071 
            4 : wb_dat <= 32'h15000000;
4072 17 unneback 
            */
4073 
           default:
4074 18 unneback 
             wb_dat <= 32'h00000000;
4075 17 unneback 
         endcase // case (wb_adr_i)
4076 
always @ (posedge wb_clk or posedge wb_rst)
4077 
    if (wb_rst)
4078 18 unneback 
        wb_ack <= 1'b0;
4079 17 unneback 
    else
4080 18 unneback 
        wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
4081 
assign hit_o = hit;
4082 
assign wb_dat_o = wb_dat & {32{wb_ack}};
4083 
assign wb_ack_o = wb_ack;
4084 17 unneback 
endmodule
4085 106 unneback 
module vl_wb_dpram (
4086 
        // wishbone slave side a
4087 
        wbsa_dat_i, wbsa_adr_i, wbsa_sel_i, wbsa_cti_i, wbsa_bte_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o, wbsa_stall_o,
4088 
        wbsa_clk, wbsa_rst,
4089 
        // wishbone slave side b
4090 
        wbsb_dat_i, wbsb_adr_i, wbsb_sel_i, wbsb_cti_i, wbsb_bte_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o, wbsb_stall_o,
4091 
        wbsb_clk, wbsb_rst);
4092 
parameter data_width_a = 32;
4093 
parameter data_width_b = data_width_a;
4094 
parameter addr_width_a = 8;
4095 
localparam addr_width_b = data_width_a * addr_width_a / data_width_b;
4096 
parameter mem_size = (addr_width_a>addr_width_b) ? (1<<addr_width_a) : (1<<addr_width_b);
4097 
parameter max_burst_width_a = 4;
4098 
parameter max_burst_width_b = max_burst_width_a;
4099 
parameter mode = "B3";
4100 109 unneback 
parameter memory_init = 0;
4101 
parameter memory_file = "vl_ram.v";
4102 106 unneback 
input [data_width_a-1:0] wbsa_dat_i;
4103 
input [addr_width_a-1:0] wbsa_adr_i;
4104 
input [data_width_a/8-1:0] wbsa_sel_i;
4105 
input [2:0] wbsa_cti_i;
4106 
input [1:0] wbsa_bte_i;
4107 
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
4108 
output [data_width_a-1:0] wbsa_dat_o;
4109 109 unneback 
output wbsa_ack_o;
4110 106 unneback 
output wbsa_stall_o;
4111 
input wbsa_clk, wbsa_rst;
4112 
input [data_width_b-1:0] wbsb_dat_i;
4113 
input [addr_width_b-1:0] wbsb_adr_i;
4114 
input [data_width_b/8-1:0] wbsb_sel_i;
4115 
input [2:0] wbsb_cti_i;
4116 
input [1:0] wbsb_bte_i;
4117 
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
4118 
output [data_width_b-1:0] wbsb_dat_o;
4119 109 unneback 
output wbsb_ack_o;
4120 106 unneback 
output wbsb_stall_o;
4121 
input wbsb_clk, wbsb_rst;
4122 
wire [addr_width_a-1:0] adr_a;
4123 
wire [addr_width_b-1:0] adr_b;
4124 
wire we_a, we_b;
4125 
generate
4126 
if (mode=="B3") begin : b3_inst
4127 
vl_wb_adr_inc # ( .adr_width(addr_width_a), .max_burst_width(max_burst_width_a)) adr_inc0 (
4128 
    .cyc_i(wbsa_cyc_i),
4129 
    .stb_i(wbsa_stb_i),
4130 
    .cti_i(wbsa_cti_i),
4131 
    .bte_i(wbsa_bte_i),
4132 
    .adr_i(wbsa_adr_i),
4133 
    .we_i(wbsa_we_i),
4134 
    .ack_o(wbsa_ack_o),
4135 
    .adr_o(adr_a),
4136 
    .clk(wbsa_clk),
4137 
    .rst(wbsa_rst));
4138 
assign we_a = wbsa_we_i & wbsa_ack_o;
4139 
vl_wb_adr_inc # ( .adr_width(addr_width_b), .max_burst_width(max_burst_width_b)) adr_inc1 (
4140 
    .cyc_i(wbsb_cyc_i),
4141 
    .stb_i(wbsb_stb_i),
4142 
    .cti_i(wbsb_cti_i),
4143 
    .bte_i(wbsb_bte_i),
4144 
    .adr_i(wbsb_adr_i),
4145 
    .we_i(wbsb_we_i),
4146 
    .ack_o(wbsb_ack_o),
4147 
    .adr_o(adr_b),
4148 
    .clk(wbsb_clk),
4149 
    .rst(wbsb_rst));
4150 
assign we_b = wbsb_we_i & wbsb_ack_o;
4151 
end else if (mode=="B4") begin : b4_inst
4152 109 unneback 
vl_dff dffacka ( .d(wbsa_stb_i & wbsa_cyc_i), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
4153 106 unneback 
assign wbsa_stall_o = 1'b0;
4154 
assign we_a = wbsa_we_i & wbsa_cyc_i & wbsa_stb_i;
4155 109 unneback 
vl_dff dffackb ( .d(wbsb_stb_i & wbsb_cyc_i), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
4156 106 unneback 
assign wbsb_stall_o = 1'b0;
4157 
assign we_b = wbsb_we_i & wbsb_cyc_i & wbsb_stb_i;
4158 
end
4159 
endgenerate
4160 109 unneback 
vl_dpram_be_2r2w # ( .a_data_width(data_width_a), .a_addr_width(addr_width_a), .mem_size(mem_size),
4161 110 unneback 
                 .b_data_width(data_width_b),
4162 109 unneback 
                 .memory_init(memory_init), .memory_file(memory_file))
4163 106 unneback 
ram_i (
4164 
    .d_a(wbsa_dat_i),
4165 
    .q_a(wbsa_dat_o),
4166 
    .adr_a(adr_a),
4167 
    .be_a(wbsa_sel_i),
4168 
    .we_a(we_a),
4169 
    .clk_a(wbsa_clk),
4170 
    .d_b(wbsb_dat_i),
4171 
    .q_b(wbsb_dat_o),
4172 
    .adr_b(adr_b),
4173 
    .be_b(wbsb_sel_i),
4174 
    .we_b(we_b),
4175 
    .clk_b(wbsb_clk) );
4176 
endmodule
4177 101 unneback 
module vl_wb_cache (
4178 103 unneback 
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i, wbs_dat_o, wbs_ack_o, wbs_stall_o, wbs_clk, wbs_rst,
4179 98 unneback 
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o, wbm_dat_i, wbm_ack_i, wbm_stall_i, wbm_clk, wbm_rst
4180 97 unneback 
);
4181 
parameter dw_s = 32;
4182 
parameter aw_s = 24;
4183 
parameter dw_m = dw_s;
4184 124 unneback 
//localparam aw_m = dw_s * aw_s / dw_m;
4185 
localparam aw_m =
4186 126 unneback 
        (dw_s==dw_m) ? aw_s :
4187 
        (dw_s==dw_m*2) ? aw_s+1 :
4188 
        (dw_s==dw_m*4) ? aw_s+2 :
4189 
        (dw_s==dw_m*8) ? aw_s+3 :
4190 
        (dw_s==dw_m*16) ? aw_s+4 :
4191 
        (dw_s==dw_m*32) ? aw_s+5 :
4192 
        (dw_s==dw_m/2) ? aw_s-1 :
4193 127 unneback 
        (dw_s==dw_m/4) ? aw_s-2 :
4194 126 unneback 
        (dw_s==dw_m/8) ? aw_s-3 :
4195 
        (dw_s==dw_m/16) ? aw_s-4 :
4196 
        (dw_s==dw_m/32) ? aw_s-5 : 0;
4197 100 unneback 
parameter wbs_max_burst_width = 4;
4198 103 unneback 
parameter wbs_mode = "B3";
4199 97 unneback 
parameter async = 1; // wbs_clk != wbm_clk
4200 
parameter nr_of_ways = 1;
4201 
parameter aw_offset = 4; // 4 => 16 words per cache line
4202 
parameter aw_slot = 10;
4203 100 unneback 
parameter valid_mem = 0;
4204 
parameter debug = 0;
4205 
localparam aw_b_offset = aw_offset * dw_s / dw_m;
4206 98 unneback 
localparam aw_tag = aw_s - aw_slot - aw_offset;
4207 97 unneback 
parameter wbm_burst_size = 4; // valid options 4,8,16
4208 98 unneback 
localparam bte = (wbm_burst_size==4) ? 2'b01 : (wbm_burst_size==8) ? 2'b10 : 2'b11;
4209 100 unneback 
localparam wbm_burst_width = (wbm_burst_size==1) ? 0 : (wbm_burst_size==2) ? 1 : (wbm_burst_size==4) ? 2 : (wbm_burst_size==8) ? 3 : (wbm_burst_size==16) ? 4 : (wbm_burst_size==32) ? 5 : (wbm_burst_size==64) ? 6 : (wbm_burst_size==128) ? 7 : 8;
4210 97 unneback 
localparam nr_of_wbm_burst = ((1<<aw_offset)/wbm_burst_size) * dw_s / dw_m;
4211 100 unneback 
localparam nr_of_wbm_burst_width = (nr_of_wbm_burst==1) ? 0 : (nr_of_wbm_burst==2) ? 1 : (nr_of_wbm_burst==4) ? 2 : (nr_of_wbm_burst==8) ? 3 : (nr_of_wbm_burst==16) ? 4 : (nr_of_wbm_burst==32) ? 5 : (nr_of_wbm_burst==64) ? 6 : (nr_of_wbm_burst==128) ? 7 : 8;
4212 97 unneback 
input [dw_s-1:0] wbs_dat_i;
4213 
input [aw_s-1:0] wbs_adr_i; // dont include a1,a0
4214 98 unneback 
input [dw_s/8-1:0] wbs_sel_i;
4215 97 unneback 
input [2:0] wbs_cti_i;
4216 
input [1:0] wbs_bte_i;
4217 98 unneback 
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
4218 97 unneback 
output [dw_s-1:0] wbs_dat_o;
4219 
output wbs_ack_o;
4220 103 unneback 
output wbs_stall_o;
4221 97 unneback 
input wbs_clk, wbs_rst;
4222 
output [dw_m-1:0] wbm_dat_o;
4223 
output [aw_m-1:0] wbm_adr_o;
4224 
output [dw_m/8-1:0] wbm_sel_o;
4225 
output [2:0] wbm_cti_o;
4226 
output [1:0] wbm_bte_o;
4227 98 unneback 
output wbm_stb_o, wbm_cyc_o, wbm_we_o;
4228 97 unneback 
input [dw_m-1:0] wbm_dat_i;
4229 
input wbm_ack_i;
4230 
input wbm_stall_i;
4231 
input wbm_clk, wbm_rst;
4232 100 unneback 
wire valid, dirty, hit;
4233 97 unneback 
wire [aw_tag-1:0] tag;
4234 
wire tag_mem_we;
4235 
wire [aw_tag-1:0] wbs_adr_tag;
4236 
wire [aw_slot-1:0] wbs_adr_slot;
4237 98 unneback 
wire [aw_offset-1:0] wbs_adr_word;
4238 
wire [aw_s-1:0] wbs_adr;
4239 97 unneback 
reg [1:0] state;
4240 
localparam idle = 2'h0;
4241 
localparam rdwr = 2'h1;
4242 
localparam push = 2'h2;
4243 
localparam pull = 2'h3;
4244 
wire eoc;
4245 103 unneback 
wire we;
4246 97 unneback 
// cdc
4247 
wire done, mem_alert, mem_done;
4248 98 unneback 
// wbm side
4249 
reg [aw_m-1:0] wbm_radr;
4250 
reg [aw_m-1:0] wbm_wadr;
4251 137 unneback 
//wire [aw_slot-1:0] wbm_adr;
4252 
wire [aw_m-1:0] wbm_adr;
4253 98 unneback 
wire wbm_radr_cke, wbm_wadr_cke;
4254 100 unneback 
reg [2:0] phase;
4255 
// phase = {we,stb,cyc}
4256 
localparam wbm_wait     = 3'b000;
4257 
localparam wbm_wr       = 3'b111;
4258 
localparam wbm_wr_drain = 3'b101;
4259 
localparam wbm_rd       = 3'b011;
4260 
localparam wbm_rd_drain = 3'b001;
4261 97 unneback 
assign {wbs_adr_tag, wbs_adr_slot, wbs_adr_word} = wbs_adr_i;
4262 100 unneback 
generate
4263 
if (valid_mem==0) begin : no_valid_mem
4264 
assign valid = 1'b1;
4265 
end else begin : valid_mem_inst
4266 
vl_dpram_1r1w
4267 
    # ( .data_width(1), .addr_width(aw_slot), .memory_init(2), .debug(debug))
4268 
    valid_mem ( .d_a(1'b1), .adr_a(wbs_adr_slot), .we_a(mem_done), .clk_a(wbm_clk),
4269 
                .q_b(valid), .adr_b(wbs_adr_slot), .clk_b(wbs_clk));
4270 
end
4271 
endgenerate
4272 
vl_dpram_1r1w
4273 
    # ( .data_width(aw_tag), .addr_width(aw_slot), .memory_init(2), .debug(debug))
4274 
    tag_mem ( .d_a(wbs_adr_tag), .adr_a(wbs_adr_slot), .we_a(mem_done), .clk_a(wbm_clk),
4275 
              .q_b(tag), .adr_b(wbs_adr_slot), .clk_b(wbs_clk));
4276 
assign hit = wbs_adr_tag == tag;
4277 
vl_dpram_1r2w
4278 
    # ( .data_width(1), .addr_width(aw_slot), .memory_init(2), .debug(debug))
4279 
    dirty_mem (
4280 
        .d_a(1'b1), .q_a(dirty), .adr_a(wbs_adr_slot), .we_a(wbs_cyc_i & wbs_we_i & wbs_ack_o), .clk_a(wbs_clk),
4281 
        .d_b(1'b0), .adr_b(wbs_adr_slot), .we_b(mem_done), .clk_b(wbm_clk));
4282 103 unneback 
generate
4283 
if (wbs_mode=="B3") begin : inst_b3
4284 100 unneback 
vl_wb_adr_inc # ( .adr_width(aw_s), .max_burst_width(wbs_max_burst_width)) adr_inc0 (
4285 
    .cyc_i(wbs_cyc_i & (state==rdwr) & hit & valid),
4286 
    .stb_i(wbs_stb_i & (state==rdwr) & hit & valid), // throttle depending on valid
4287 97 unneback 
    .cti_i(wbs_cti_i),
4288 
    .bte_i(wbs_bte_i),
4289 
    .adr_i(wbs_adr_i),
4290 
    .we_i (wbs_we_i),
4291 
    .ack_o(wbs_ack_o),
4292 
    .adr_o(wbs_adr),
4293 100 unneback 
    .clk(wbs_clk),
4294 
    .rst(wbs_rst));
4295 103 unneback 
assign eoc = (wbs_cti_i==3'b000 | wbs_cti_i==3'b111) & wbs_ack_o;
4296 
assign we = wbs_cyc_i &  wbs_we_i & wbs_ack_o;
4297 
end else if (wbs_mode=="B4") begin : inst_b4
4298 
end
4299 
endgenerate
4300 131 unneback 
localparam cache_mem_b_aw =
4301 
    (dw_s==dw_m) ? aw_slot+aw_offset :
4302 133 unneback 
    (dw_s==dw_m/2) ? aw_slot+aw_offset-1 :
4303 
    (dw_s==dw_m/4) ? aw_slot+aw_offset-2 :
4304 
    (dw_s==dw_m/8) ? aw_slot+aw_offset-3 :
4305 
    (dw_s==dw_m/16) ? aw_slot+aw_offset-4 :
4306 
    (dw_s==dw_m*2) ? aw_slot+aw_offset+1 :
4307 
    (dw_s==dw_m*4) ? aw_slot+aw_offset+2 :
4308 
    (dw_s==dw_m*8) ? aw_slot+aw_offset+3 :
4309 
    (dw_s==dw_m*16) ? aw_slot+aw_offset+4 : 0;
4310 97 unneback 
vl_dpram_be_2r2w
4311 100 unneback 
    # ( .a_data_width(dw_s), .a_addr_width(aw_slot+aw_offset), .b_data_width(dw_m), .debug(debug))
4312 103 unneback 
    cache_mem ( .d_a(wbs_dat_i), .adr_a(wbs_adr[aw_slot+aw_offset-1:0]),   .be_a(wbs_sel_i), .we_a(we), .q_a(wbs_dat_o), .clk_a(wbs_clk),
4313 136 unneback 
                .d_b(wbm_dat_i), .adr_b(wbm_adr[cache_mem_b_aw-1:0]), .be_b(wbm_sel_o), .we_b(wbm_cyc_o & !wbm_we_o & wbm_ack_i), .q_b(wbm_dat_o), .clk_b(wbm_clk));
4314 97 unneback 
always @ (posedge wbs_clk or posedge wbs_rst)
4315 
if (wbs_rst)
4316 98 unneback 
    state <= idle;
4317 97 unneback 
else
4318 
    case (state)
4319 
    idle:
4320 
        if (wbs_cyc_i)
4321 
            state <= rdwr;
4322 
    rdwr:
4323 100 unneback 
        casex ({valid, hit, dirty, eoc})
4324 
        4'b0xxx: state <= pull;
4325 
        4'b11x1: state <= idle;
4326 
        4'b101x: state <= push;
4327 
        4'b100x: state <= pull;
4328 
        endcase
4329 97 unneback 
    push:
4330 
        if (done)
4331 
            state <= rdwr;
4332 
    pull:
4333 
        if (done)
4334 
            state <= rdwr;
4335 
    default: state <= idle;
4336 
    endcase
4337 
// cdc
4338 
generate
4339 
if (async==1) begin : cdc0
4340 100 unneback 
vl_cdc cdc0 ( .start_pl(state==rdwr & (!valid | !hit)), .take_it_pl(mem_alert), .take_it_grant_pl(mem_done), .got_it_pl(done), .clk_src(wbs_clk), .rst_src(wbs_rst), .clk_dst(wbm_clk), .rst_dst(wbm_rst));
4341 97 unneback 
end
4342 
else begin : nocdc
4343 100 unneback 
    assign mem_alert = state==rdwr & (!valid | !hit);
4344 97 unneback 
    assign done = mem_done;
4345 
end
4346 
endgenerate
4347 136 unneback 
// FSM generating a number of bursts 4 cycles
4348 97 unneback 
// actual number depends on data width ratio
4349 
// nr_of_wbm_burst
4350 101 unneback 
reg [nr_of_wbm_burst_width+wbm_burst_width-1:0]       cnt_rw, cnt_ack;
4351 97 unneback 
always @ (posedge wbm_clk or posedge wbm_rst)
4352 
if (wbm_rst)
4353 100 unneback 
    cnt_rw <= {wbm_burst_width{1'b0}};
4354 97 unneback 
else
4355 100 unneback 
    if (wbm_cyc_o & wbm_stb_o & !wbm_stall_i)
4356 
        cnt_rw <= cnt_rw + 1;
4357 98 unneback 
always @ (posedge wbm_clk or posedge wbm_rst)
4358 
if (wbm_rst)
4359 100 unneback 
    cnt_ack <= {wbm_burst_width{1'b0}};
4360 98 unneback 
else
4361 100 unneback 
    if (wbm_ack_i)
4362 
        cnt_ack <= cnt_ack + 1;
4363 
generate
4364 101 unneback 
if (nr_of_wbm_burst==1) begin : one_burst
4365 98 unneback 
always @ (posedge wbm_clk or posedge wbm_rst)
4366 
if (wbm_rst)
4367 
    phase <= wbm_wait;
4368 
else
4369 
    case (phase)
4370 
    wbm_wait:
4371 
        if (mem_alert)
4372 100 unneback 
            if (state==push)
4373 
                phase <= wbm_wr;
4374 
            else
4375 
                phase <= wbm_rd;
4376 98 unneback 
    wbm_wr:
4377 100 unneback 
        if (&cnt_rw)
4378 
            phase <= wbm_wr_drain;
4379 
    wbm_wr_drain:
4380 
        if (&cnt_ack)
4381 98 unneback 
            phase <= wbm_rd;
4382 
    wbm_rd:
4383 100 unneback 
        if (&cnt_rw)
4384 
            phase <= wbm_rd_drain;
4385 
    wbm_rd_drain:
4386 
        if (&cnt_ack)
4387 
            phase <= wbm_wait;
4388 98 unneback 
    default: phase <= wbm_wait;
4389 
    endcase
4390 100 unneback 
end else begin : multiple_burst
4391 101 unneback 
always @ (posedge wbm_clk or posedge wbm_rst)
4392 
if (wbm_rst)
4393 
    phase <= wbm_wait;
4394 
else
4395 
    case (phase)
4396 
    wbm_wait:
4397 
        if (mem_alert)
4398 
            if (state==push)
4399 
                phase <= wbm_wr;
4400 
            else
4401 
                phase <= wbm_rd;
4402 
    wbm_wr:
4403 
        if (&cnt_rw[wbm_burst_width-1:0])
4404 
            phase <= wbm_wr_drain;
4405 
    wbm_wr_drain:
4406 
        if (&cnt_ack)
4407 
            phase <= wbm_rd;
4408 
        else if (&cnt_ack[wbm_burst_width-1:0])
4409 
            phase <= wbm_wr;
4410 
    wbm_rd:
4411 
        if (&cnt_rw[wbm_burst_width-1:0])
4412 
            phase <= wbm_rd_drain;
4413 
    wbm_rd_drain:
4414 
        if (&cnt_ack)
4415 
            phase <= wbm_wait;
4416 
        else if (&cnt_ack[wbm_burst_width-1:0])
4417 
            phase <= wbm_rd;
4418 
    default: phase <= wbm_wait;
4419 
    endcase
4420 100 unneback 
end
4421 
endgenerate
4422 101 unneback 
assign mem_done = phase==wbm_rd_drain & (&cnt_ack) & wbm_ack_i;
4423 100 unneback 
assign wbm_adr_o = (phase[2]) ? {tag, wbs_adr_slot, cnt_rw} : {wbs_adr_tag, wbs_adr_slot, cnt_rw};
4424 137 unneback 
assign wbm_adr   = (phase[2]) ? {wbs_adr_slot, cnt_rw} : {wbs_adr_slot, cnt_ack};
4425 100 unneback 
assign wbm_sel_o = {dw_m/8{1'b1}};
4426 
assign wbm_cti_o = (&cnt_rw | !wbm_stb_o) ? 3'b111 : 3'b010;
4427 98 unneback 
assign wbm_bte_o = bte;
4428 100 unneback 
assign {wbm_we_o, wbm_stb_o, wbm_cyc_o}  = phase;
4429 97 unneback 
endmodule
4430 103 unneback 
// Wishbone to avalon bridge supporting one type of burst transfer only
4431 
// intended use is together with cache above
4432 
// WB B4 -> pipelined avalon
4433 
module vl_wb_avalon_bridge (
4434 
        // wishbone slave side
4435 
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_stall_o,
4436 
        // avalon master side
4437 
        readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer,
4438 136 unneback 
        init_done,
4439 103 unneback 
        // common
4440 
        clk, rst);
4441 
parameter adr_width = 30;
4442 
parameter dat_width = 32;
4443 
parameter burst_size = 4;
4444 
input [dat_width-1:0] wbs_dat_i;
4445 
input [adr_width-1:0] wbs_adr_i;
4446 
input [dat_width/8-1:0]  wbs_sel_i;
4447 
input [1:0]  wbs_bte_i;
4448 
input [2:0]  wbs_cti_i;
4449 
input wbs_we_i;
4450 
input wbs_cyc_i;
4451 
input wbs_stb_i;
4452 130 unneback 
output [dat_width-1:0] wbs_dat_o;
4453 103 unneback 
output wbs_ack_o;
4454 
output wbs_stall_o;
4455 
input [dat_width-1:0] readdata;
4456 
input readdatavalid;
4457 
output [dat_width-1:0] writedata;
4458 
output [adr_width-1:0] address;
4459 
output [dat_width/8-1:0]  be;
4460 
output write;
4461 
output read;
4462 
output beginbursttransfer;
4463 
output [3:0] burstcount;
4464 
input waitrequest;
4465 136 unneback 
input init_done;
4466 103 unneback 
input clk, rst;
4467 136 unneback 
// cnt1 - initiated read or writes
4468 
// cnt2 - # of read or writes in pipeline
4469 
reg [3:0] cnt1;
4470 
reg [3:0] cnt2;
4471 
reg next_state, state;
4472 
localparam s0 = 1'b0;
4473 
localparam s1 = 1'b1;
4474 
wire eoc;
4475 
always @ *
4476 
begin
4477 
    case (state)
4478 
    s0: if (init_done & wbs_cyc_i) next_state <= s1;
4479 
    s1:
4480 
    default: next_state <= state;
4481 
    end
4482 
end
4483 103 unneback 
always @ (posedge clk or posedge rst)
4484 
if (rst)
4485 136 unneback 
    state <= s0;
4486 103 unneback 
else
4487 136 unneback 
    state <= next_state;
4488 
assign eoc = state==s1 & !(read | write) & (& !waitrequest & cnt2=;
4489 
always @ (posedge clk or posedge rst)
4490 
if (rst)
4491 
    cnt1 <= 4'h0;
4492 
else
4493 
    if (read & !waitrequest & init_done)
4494 
        cnt1 <= burst_size - 1;
4495 
    else if (write & !waitrequest & init_done)
4496 
        cnt1 <= cnt1 + 4'h1;
4497 
    else if (next_state==idle)
4498 
        cnt1 <= 4'h0;
4499 
always @ (posedge clk or posedge rst)
4500 
if (rst)
4501 
    cnt2 <= 4'h0;
4502 
else
4503 
    if (read & !waitrequest & init_done)
4504 
        cnt2 <= burst_size - 1;
4505 
    else if (write & !waitrequest & init_done & )
4506 
        cnt2 <= cnt1 + 4'h1;
4507 
    else if (next_state==idle)
4508 
        cnt2 <= 4'h0;
4509 103 unneback 
reg wr_ack;
4510 
always @ (posedge clk or posedge rst)
4511 
if (rst)
4512 
    wr_ack <= 1'b0;
4513 
else
4514 
    wr_ack <=  (wbs_we_i & wbs_cyc_i & wbs_stb_i & !wbs_stall_o);
4515 
// to avalon
4516 
assign writedata = wbs_dat_i;
4517 
assign address = wbs_adr_i;
4518 
assign be = wbs_sel_i;
4519 136 unneback 
assign write = cnt!=4'h0 & wbs_cyc_i &  wbs_we_i;
4520 
assign read  = cnt!=4'h0 & wbs_cyc_i & !wbs_we_i;
4521 
assign beginbursttransfer = state==s0 & next_state==s1;
4522 103 unneback 
assign burstcount = burst_size;
4523 
// to wishbone
4524 
assign wbs_dat_o = readdata;
4525 
assign wbs_ack_o = wr_ack | readdatavalid;
4526 
assign wbs_stall_o = waitrequest;
4527 
endmodule
4528 
module vl_wb_avalon_mem_cache (
4529 
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i, wbs_dat_o, wbs_ack_o, wbs_stall_o, wbs_clk, wbs_rst,
4530 
    readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst
4531 
);
4532 
// wishbone
4533 
parameter wb_dat_width = 32;
4534 
parameter wb_adr_width = 22;
4535 
parameter wb_max_burst_width = 4;
4536 
parameter wb_mode = "B4";
4537 
// avalon
4538 
parameter avalon_dat_width = 32;
4539 121 unneback 
//localparam avalon_adr_width = wb_dat_width * wb_adr_width / avalon_dat_width;
4540 122 unneback 
localparam avalon_adr_width =
4541 
        (wb_dat_width==avalon_dat_width) ? wb_adr_width :
4542 
        (wb_dat_width==avalon_dat_width*2) ? wb_adr_width+1 :
4543 
        (wb_dat_width==avalon_dat_width*4) ? wb_adr_width+2 :
4544 
        (wb_dat_width==avalon_dat_width*8) ? wb_adr_width+3 :
4545 
        (wb_dat_width==avalon_dat_width*16) ? wb_adr_width+4 :
4546 
        (wb_dat_width==avalon_dat_width*32) ? wb_adr_width+5 :
4547 
        (wb_dat_width==avalon_dat_width/2) ? wb_adr_width-1 :
4548 
        (wb_dat_width==avalon_dat_width/4) ? wb_adr_width-2 :
4549 
        (wb_dat_width==avalon_dat_width/8) ? wb_adr_width-3 :
4550 
        (wb_dat_width==avalon_dat_width/16) ? wb_adr_width-4 :
4551 123 unneback 
        (wb_dat_width==avalon_dat_width/32) ? wb_adr_width-5 : 0;
4552 103 unneback 
parameter avalon_burst_size = 4;
4553 
// cache
4554 
parameter async = 1;
4555 
parameter nr_of_ways = 1;
4556 
parameter aw_offset = 4;
4557 
parameter aw_slot = 10;
4558 
parameter valid_mem = 1;
4559 
// shadow RAM
4560 
parameter shadow_ram = 0;
4561 
parameter shadow_ram_adr_width = 10;
4562 
parameter shadow_ram_size = 1024;
4563 
parameter shadow_ram_init = 2; // 0: no init, 1: from file, 2: with zero
4564 
parameter shadow_ram_file = "vl_ram.v";
4565 
input [wb_dat_width-1:0] wbs_dat_i;
4566 
input [wb_adr_width-1:0] wbs_adr_i; // dont include a1,a0
4567 
input [wb_dat_width/8-1:0] wbs_sel_i;
4568 
input [2:0] wbs_cti_i;
4569 
input [1:0] wbs_bte_i;
4570 
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
4571 
output [wb_dat_width-1:0] wbs_dat_o;
4572 
output wbs_ack_o;
4573 
output wbs_stall_o;
4574 
input wbs_clk, wbs_rst;
4575 
input [avalon_dat_width-1:0] readdata;
4576 
input readdatavalid;
4577 
output [avalon_dat_width-1:0] writedata;
4578 
output [avalon_adr_width-1:0] address;
4579 
output [avalon_dat_width/8-1:0]  be;
4580 
output write;
4581 
output read;
4582 
output beginbursttransfer;
4583 
output [3:0] burstcount;
4584 
input waitrequest;
4585 
input clk, rst;
4586 
wire [wb_dat_width-1:0] wb1_dat_o;
4587 
wire [wb_adr_width-1:0] wb1_adr_o;
4588 
wire [wb_dat_width/8-1:0] wb1_sel_o;
4589 
wire [2:0] wb1_cti_o;
4590 
wire [1:0] wb1_bte_o;
4591 
wire wb1_we_o;
4592 
wire wb1_stb_o;
4593 
wire wb1_cyc_o;
4594 
wire wb1_stall_i;
4595 
wire [wb_dat_width-1:0] wb1_dat_i;
4596 
wire wb1_ack_i;
4597 129 unneback 
wire [avalon_dat_width-1:0] wb2_dat_o;
4598 
wire [avalon_adr_width-1:0] wb2_adr_o;
4599 
wire [avalon_dat_width/8-1:0] wb2_sel_o;
4600 103 unneback 
wire [2:0] wb2_cti_o;
4601 
wire [1:0] wb2_bte_o;
4602 
wire wb2_we_o;
4603 
wire wb2_stb_o;
4604 
wire wb2_cyc_o;
4605 
wire wb2_stall_i;
4606 129 unneback 
wire [avalon_dat_width-1:0] wb2_dat_i;
4607 103 unneback 
wire wb2_ack_i;
4608 
vl_wb_shadow_ram # ( .dat_width(wb_dat_width), .mode(wb_mode), .max_burst_width(wb_max_burst_width),
4609 120 unneback 
                 .shadow_mem_adr_width(shadow_ram_adr_width), .shadow_mem_size(shadow_ram_size), .shadow_mem_init(shadow_ram_init), .shadow_mem_file(shadow_ram_file),
4610 103 unneback 
                 .main_mem_adr_width(wb_adr_width))
4611 
shadow_ram0 (
4612 
    .wbs_dat_i(wbs_dat_i), .wbs_adr_i(wbs_adr_i), .wbs_cti_i(wbs_cti_i), .wbs_bte_i(wbs_bte_i), .wbs_sel_i(wbs_sel_i), .wbs_we_i(wbs_we_i), .wbs_stb_i(wbs_stb_i), .wbs_cyc_i(wbs_cyc_i),
4613 
    .wbs_dat_o(wbs_dat_o), .wbs_ack_o(wbs_ack_o), .wbs_stall_o(wbs_stall_o),
4614 
    .wbm_dat_o(wb1_dat_o), .wbm_adr_o(wb1_adr_o), .wbm_cti_o(wb1_cti_o), .wbm_bte_o(wb1_bte_o), .wbm_sel_o(wb1_sel_o), .wbm_we_o(wb1_we_o), .wbm_stb_o(wb1_stb_o), .wbm_cyc_o(wb1_cyc_o),
4615 
    .wbm_dat_i(wb1_dat_i), .wbm_ack_i(wb1_ack_i), .wbm_stall_i(wb1_stall_i),
4616 
    .wb_clk(wbs_clk), .wb_rst(wbs_rst));
4617 
vl_wb_cache
4618 
# ( .dw_s(wb_dat_width), .aw_s(wb_adr_width), .dw_m(avalon_dat_width), .wbs_mode(wb_mode), .wbs_max_burst_width(wb_max_burst_width), .async(async), .nr_of_ways(nr_of_ways), .aw_offset(aw_offset), .aw_slot(aw_slot), .valid_mem(valid_mem))
4619 
cache0 (
4620 
    .wbs_dat_i(wb1_dat_o), .wbs_adr_i(wb1_adr_o), .wbs_sel_i(wb1_sel_o), .wbs_cti_i(wb1_cti_o), .wbs_bte_i(wb1_bte_o), .wbs_we_i(wb1_we_o), .wbs_stb_i(wb1_stb_o), .wbs_cyc_i(wb1_cyc_o),
4621 
    .wbs_dat_o(wb1_dat_i), .wbs_ack_o(wb1_ack_i), .wbs_stall_o(wb1_stall_i), .wbs_clk(wbs_clk), .wbs_rst(wbs_rst),
4622 
    .wbm_dat_o(wb2_dat_o), .wbm_adr_o(wb2_adr_o), .wbm_sel_o(wb2_sel_o), .wbm_cti_o(wb2_cti_o), .wbm_bte_o(wb2_bte_o), .wbm_we_o(wb2_we_o), .wbm_stb_o(wb2_stb_o), .wbm_cyc_o(wb2_cyc_o),
4623 
    .wbm_dat_i(wb2_dat_i), .wbm_ack_i(wb2_ack_i), .wbm_stall_i(wb2_stall_i), .wbm_clk(clk), .wbm_rst(rst));
4624 
vl_wb_avalon_bridge # ( .adr_width(avalon_adr_width), .dat_width(avalon_dat_width), .burst_size(avalon_burst_size))
4625 
bridge0 (
4626 
        // wishbone slave side
4627 
        .wbs_dat_i(wb2_dat_o), .wbs_adr_i(wb2_adr_o), .wbs_sel_i(wb2_sel_o), .wbs_bte_i(wb2_bte_o), .wbs_cti_i(wb2_cti_o), .wbs_we_i(wb2_we_o), .wbs_cyc_i(wb2_cyc_o), .wbs_stb_i(wb2_stb_o),
4628 
        .wbs_dat_o(wb2_dat_i), .wbs_ack_o(wb2_ack_i), .wbs_stall_o(wb2_stall_i),
4629 
        // avalon master side
4630 
        .readdata(readdata), .readdatavalid(readdatavalid), .address(address), .read(read), .be(be), .write(write), .burstcount(burstcount), .writedata(writedata), .waitrequest(waitrequest), .beginbursttransfer(beginbursttransfer),
4631 
        // common
4632 
        .clk(clk), .rst(rst));
4633 
endmodule
4634 136 unneback 
module vl_wb_sdr_sdram (
4635 
    // wisbone i/f
4636 
    dat_i, adr_i, sel_i, we_i, cyc_i, stb_i, dat_o, ack_o, stall_o,
4637 
    // SDR SDRAM
4638 
    ba, a, cmd, cke, cs_n, dqm, dq_i, dq_o, dq_oe,
4639 
    // system
4640 
    clk, rst);
4641 
    // external data bus size
4642 
    parameter dat_size = 16;
4643 
    // memory geometry parameters
4644 
    parameter ba_size  = 2;
4645 
    parameter row_size = 13;
4646 
    parameter col_size = 9;
4647 
    parameter cl = 2;
4648 
    // memory timing parameters
4649 
    parameter tRFC = 9;
4650 
    parameter tRP  = 2;
4651 
    parameter tRCD = 2;
4652 
    parameter tMRD = 2;
4653 
    // LMR
4654 
    // [12:10] reserved
4655 
    // [9]     WB, write burst; 0 - programmed burst length, 1 - single location
4656 
    // [8:7]   OP Mode, 2'b00
4657 
    // [6:4]   CAS Latency; 3'b010 - 2, 3'b011 - 3
4658 
    // [3]     BT, Burst Type; 1'b0 - sequential, 1'b1 - interleaved
4659 
    // [2:0]   Burst length; 3'b000 - 1, 3'b001 - 2, 3'b010 - 4, 3'b011 - 8, 3'b111 - full page
4660 
    localparam init_wb = 1'b1;
4661 
    localparam init_cl = (cl==2) ? 3'b010 : 3'b011;
4662 
    localparam init_bt = 1'b0;
4663 
    localparam init_bl = 3'b000;
4664 
    input [dat_size-1:0] dat_i;
4665 
    input [ba_size+col_size+row_size-1:0] adr_i;
4666 
    input [dat_size/8-1:0] sel_i;
4667 
    input we_i, cyc_i, stb_i;
4668 
    output [dat_size-1:0] dat_o;
4669 
    output ack_o;
4670 
    output reg stall_o;
4671 
    output [ba_size-1:0]    ba;
4672 
    output reg [12:0]   a;
4673 
    output reg [2:0]    cmd; // {ras,cas,we}
4674 
    output cke, cs_n;
4675 
    output reg [dat_size/8-1:0]    dqm;
4676 
    output [dat_size-1:0]       dq_o;
4677 
    output reg          dq_oe;
4678 
    input  [dat_size-1:0]       dq_i;
4679 
    input clk, rst;
4680 
    wire [ba_size-1:0]   bank;
4681 
    wire [row_size-1:0] row;
4682 
    wire [col_size-1:0] col;
4683 
    wire [0:31]  shreg;
4684 
    wire                ref_cnt_zero;
4685 
    reg                 refresh_req;
4686 
    wire ack_rd, rd_ack_emptyflag;
4687 
    wire ack_wr;
4688 
    // to keep track of open rows per bank
4689 
    reg [row_size-1:0]   open_row[0:3];
4690 
    reg [0:3]            open_ba;
4691 
    reg                 current_bank_closed, current_row_open;
4692 
    parameter rfr_length = 10;
4693 
    parameter rfr_wrap_value = 1010;
4694 
    parameter [2:0] cmd_nop = 3'b111,
4695 
                    cmd_act = 3'b011,
4696 
                    cmd_rd  = 3'b101,
4697 
                    cmd_wr  = 3'b100,
4698 
                    cmd_pch = 3'b010,
4699 
                    cmd_rfr = 3'b001,
4700 
                    cmd_lmr = 3'b000;
4701 
// ctrl FSM
4702 
    assign cke = 1'b1;
4703 
    assign cs_n = 1'b0;
4704 
    reg [2:0] state, next;
4705 
    function [12:0] a10_fix;
4706 
        input [col_size-1:0] a;
4707 
        integer i;
4708 
    begin
4709 
        for (i=0;i<13;i=i+1) begin
4710 
            if (i<10)
4711 
              if (i<col_size)
4712 
                a10_fix[i] = a[i];
4713 
              else
4714 
                a10_fix[i] = 1'b0;
4715 
            else if (i==10)
4716 
              a10_fix[i] = 1'b0;
4717 
            else
4718 
              if (i<col_size)
4719 
                a10_fix[i] = a[i-1];
4720 
              else
4721 
                a10_fix[i] = 1'b0;
4722 
        end
4723 
    end
4724 
    endfunction
4725 
    assign {bank,row,col} = adr_i;
4726 
    always @ (posedge clk or posedge rst)
4727 
    if (rst)
4728 
       state <= 3'b000;
4729 
    else
4730 
       state <= next;
4731 
    always @*
4732 
    begin
4733 
        next = state;
4734 
        case (state)
4735 
        3'b000:
4736 
            if (shreg[3+tRP+tRFC+tRFC+tMRD]) next = 3'b001;
4737 
        3'b001:
4738 
            if (refresh_req) next = 3'b010;
4739 
            else if (cyc_i & stb_i & rd_ack_emptyflag) next = 3'b011;
4740 
        3'b010:
4741 
            if (shreg[tRP+tRFC-2]) next = 3'b001; // take away two cycles because no cmd will be issued in idle and adr
4742 
        3'b011:
4743 
            if (current_bank_closed) next = 3'b101;
4744 
            else if (current_row_open) next = 3'b111;
4745 
            else next = 3'b100;
4746 
        3'b100:
4747 
            if (shreg[tRP]) next = 3'b101;
4748 
        3'b101:
4749 
            if (shreg[tRCD]) next = 3'b111;
4750 
        3'b111:
4751 
            if (!stb_i) next = 3'b001;
4752 
        endcase
4753 
    end
4754 
    // counter
4755 
    vl_cnt_shreg_clear # ( .length(32))
4756 
        cnt0 (
4757 
            .clear(state!=next),
4758 
            .q(shreg),
4759 
            .rst(rst),
4760 
            .clk(clk));
4761 
    // ba, a, cmd
4762 
    // outputs dependent on state vector
4763 
    always @ (*)
4764 
        begin
4765 
            {a,cmd} = {13'd0,cmd_nop};
4766 
            dqm = 2'b11;
4767 
            dq_oe = 1'b0;
4768 
            stall_o = 1'b1;
4769 
            case (state)
4770 
            3'b000:
4771 
                if (shreg[3]) begin
4772 
                    {a,cmd} = {13'b0010000000000, cmd_pch};
4773 
                end else if (shreg[3+tRP] | shreg[3+tRP+tRFC])
4774 
                    {a,cmd} = {13'd0, cmd_rfr};
4775 
                else if (shreg[3+tRP+tRFC+tRFC])
4776 
                    {a,cmd} = {3'b000,init_wb,2'b00,init_cl,init_bt,init_bl,cmd_lmr};
4777 
            3'b010:
4778 
                if (shreg[0])
4779 
                    {a,cmd} = {13'b0010000000000, cmd_pch};
4780 
                else if (shreg[tRP])
4781 
                    {a,cmd} = {13'd0, cmd_rfr};
4782 
            3'b100:
4783 
                if (shreg[0])
4784 
                    {a,cmd} = {13'd0,cmd_pch};
4785 
            3'b101:
4786 
                if (shreg[0])
4787 
                    {a[row_size-1:0],cmd} = {row,cmd_act};
4788 
            3'b111:
4789 
                begin
4790 
                    if (we_i)
4791 
                        cmd = cmd_wr;
4792 
                    else
4793 
                        cmd = cmd_rd;
4794 
                    if (we_i)
4795 
                        dqm = ~sel_i;
4796 
                    else
4797 
                        dqm = 2'b00;
4798 
                    if (we_i)
4799 
                        dq_oe = 1'b1;
4800 
                    a = a10_fix(col);
4801 
                    stall_o = 1'b0;
4802 
                end
4803 
            endcase
4804 
        end
4805 
    assign ba = bank;
4806 
    // precharge individual bank A10=0
4807 
    // precharge all bank A10=1
4808 
    genvar i;
4809 
    generate
4810 
    for (i=0;i<2<<ba_size-1;i=i+1) begin : open_ba_logic
4811 
        always @ (posedge clk or posedge rst)
4812 
        if (rst)
4813 
            {open_ba[i],open_row[i]} <= {1'b0,{row_size{1'b0}}};
4814 
        else
4815 
            if (cmd==cmd_pch & (a[10] | bank==i))
4816 
                open_ba[i] <= 1'b0;
4817 
            else if (cmd==cmd_act & bank==i)
4818 
                {open_ba[i],open_row[i]} <= {1'b1,row};
4819 
    end
4820 
    endgenerate
4821 
    // bank and row open ?
4822 
    always @ (posedge clk or posedge rst)
4823 
    if (rst)
4824 
       {current_bank_closed, current_row_open} <= {1'b1, 1'b0};
4825 
    else
4826 
       {current_bank_closed, current_row_open} <= {!(open_ba[bank]), open_row[bank]==row};
4827 
    // refresh counter
4828 
    vl_cnt_lfsr_zq # ( .length(rfr_length), .wrap_value (rfr_wrap_value)) ref_counter0( .zq(ref_cnt_zero), .rst(rst), .clk(clk));
4829 
    always @ (posedge clk or posedge rst)
4830 
    if (rst)
4831 
        refresh_req <= 1'b0;
4832 
    else
4833 
        if (ref_cnt_zero)
4834 
            refresh_req <= 1'b1;
4835 
        else if (state==3'b010)
4836 
            refresh_req <= 1'b0;
4837 
    assign dat_o = dq_i;
4838 
    assign ack_wr = (state==3'b111 & we_i);
4839 
    vl_delay_emptyflag # ( .depth(cl+2)) delay0 ( .d(state==3'b111 & stb_i & !we_i), .q(ack_rd), .emptyflag(rd_ack_emptyflag), .clk(clk), .rst(rst));
4840 
    assign ack_o = ack_rd | ack_wr;
4841 
    assign dq_o = dat_i;
4842 
endmodule
4843 
module vl_wb_sdr_sdram_ctrl (
4844 
    // WB i/f
4845 
    wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
4846 
    wbs_dat_o, wbs_ack_o, wbs_stall_o,
4847 
    // SDR SDRAM
4848 
    mem_ba, mem_a, mem_cmd, mem_cke, mem_cs_n, mem_dqm, mem_dq_i, mem_dq_o, mem_dq_oe,
4849 
    // system
4850 
    wb_clk, wb_rst, mem_clk, mem_rst);
4851 
    // WB slave
4852 
    parameter wbs_dat_width = 32;
4853 
    parameter wbs_adr_width = 24;
4854 
    parameter wbs_mode = "B3";
4855 
    parameter wbs_max_burst_width = 4;
4856 
    // Shadow RAM
4857 
    parameter shadow_mem_adr_width = 10;
4858 
    parameter shadow_mem_size = 1024;
4859 
    parameter shadow_mem_init = 2;
4860 
    parameter shadow_mem_file = "vl_ram.v";
4861 
    // Cache
4862 
    parameter cache_async = 1; // wbs_clk != wbm_clk
4863 
    parameter cache_nr_of_ways = 1;
4864 
    parameter cache_aw_offset = 4; // 4 => 16 words per cache line
4865 
    parameter cache_aw_slot = 10;
4866 
    parameter cache_valid_mem = 0;
4867 
    parameter cache_debug = 0;
4868 
    // SDRAM parameters
4869 
    parameter mem_dat_size = 16;
4870 
    parameter mem_ba_size  = 2;
4871 
    parameter mem_row_size = 13;
4872 
    parameter mem_col_size = 9;
4873 
    parameter mem_cl = 2;
4874 
    parameter mem_tRFC = 9;
4875 
    parameter mem_tRP  = 2;
4876 
    parameter mem_tRCD = 2;
4877 
    parameter mem_tMRD = 2;
4878 
    parameter mem_rfr_length = 10;
4879 
    parameter mem_rfr_wrap_value = 1010;
4880 
    input [wbs_dat_width-1:0] wbs_dat_i;
4881 
    input [wbs_adr_width-1:0] wbs_adr_i;
4882 
    input [2:0] wbs_cti_i;
4883 
    input [1:0] wbs_bte_i;
4884 
    input [wbs_dat_width/8-1:0] wbs_sel_i;
4885 
    input wbs_we_i, wbs_stb_i, wbs_cyc_i;
4886 
    output [wbs_dat_width-1:0] wbs_dat_o;
4887 
    output wbs_ack_o;
4888 
    output wbs_stall_o;
4889 
    output [mem_ba_size-1:0]    mem_ba;
4890 
    output reg [12:0]           mem_a;
4891 
    output reg [2:0]            mem_cmd; // {ras,cas,we}
4892 
    output                      mem_cke, mem_cs_n;
4893 
    output reg [mem_dat_size/8-1:0] mem_dqm;
4894 
    output [mem_dat_size-1:0]       mem_dq_o;
4895 
    output reg                  mem_dq_oe;
4896 
    input  [mem_dat_size-1:0]       mem_dq_i;
4897 
    input wb_clk, wb_rst, mem_clk, mem_rst;
4898 
    // wbm1
4899 
    wire [wbs_dat_width-1:0] wbm1_dat_o;
4900 
    wire [wbs_adr_width-1:0] wbm1_adr_o;
4901 
    wire [2:0] wbm1_cti_o;
4902 
    wire [1:0] wbm1_bte_o;
4903 
    wire [wbs_dat_width/8-1:0] wbm1_sel_o;
4904 
    wire wbm1_we_o, wbm1_stb_o, wbm1_cyc_o;
4905 
    wire [wbs_dat_width-1:0] wbm1_dat_i;
4906 
    wire wbm1_ack_i, wbm1_stall_i;
4907 
    // wbm2
4908 
    wire [mem_dat_size-1:0] wbm2_dat_o;
4909 
    wire [mem_ba_size+mem_row_size+mem_col_size-1:0] wbm2_adr_o;
4910 
    wire [2:0] wbm2_cti_o;
4911 
    wire [1:0] wbm2_bte_o;
4912 
    wire [mem_dat_size/8-1:0] wbm2_sel_o;
4913 
    wire wbm2_we_o, wbm2_stb_o, wbm2_cyc_o;
4914 
    wire [mem_dat_size-1:0] wbm2_dat_i;
4915 
    wire wbm2_ack_i, wbm2_stall_i;
4916 
vl_wb_shadow_ram # (
4917 
    .shadow_mem_adr_width(shadow_mem_adr_width), .shadow_mem_size(shadow_mem_size), .shadow_mem_init(shadow_mem_init), .shadow_mem_file(shadow_mem_file), .main_mem_adr_width(wbs_adr_width), .dat_width(wbs_dat_width), .mode(wbs_mode), .max_burst_width(wbs_max_burst_width) )
4918 
shadow_ram0 (
4919 
    .wbs_dat_i(wbs_dat_i),
4920 
    .wbs_adr_i(wbs_adr_i),
4921 
    .wbs_cti_i(wbs_cti_i),
4922 
    .wbs_bte_i(wbs_bte_i),
4923 
    .wbs_sel_i(wbs_sel_i),
4924 
    .wbs_we_i (wbs_we_i),
4925 
    .wbs_stb_i(wbs_stb_i),
4926 
    .wbs_cyc_i(wbs_cyc_i),
4927 
    .wbs_dat_o(wbs_dat_o),
4928 
    .wbs_ack_o(wbs_ack_o),
4929 
    .wbs_stall_o(wbs_stall_o),
4930 
    .wbm_dat_o(wbm1_dat_o),
4931 
    .wbm_adr_o(wbm1_adr_o),
4932 
    .wbm_cti_o(wbm1_cti_o),
4933 
    .wbm_bte_o(wbm1_bte_o),
4934 
    .wbm_sel_o(wbm1_sel_o),
4935 
    .wbm_we_o(wbm1_we_o),
4936 
    .wbm_stb_o(wbm1_stb_o),
4937 
    .wbm_cyc_o(wbm1_cyc_o),
4938 
    .wbm_dat_i(wbm1_dat_i),
4939 
    .wbm_ack_i(wbm1_ack_i),
4940 
    .wbm_stall_i(wbm1_stall_i),
4941 
    .wb_clk(wb_clk),
4942 
    .wb_rst(wb_rst) );
4943 
vl_wb_cache # (
4944 
    .dw_s(wbs_dat_width), .aw_s(wbs_adr_width), .dw_m(mem_dat_size), .wbs_max_burst_width(cache_aw_offset), .wbs_mode(wbs_mode), .async(cache_async), .nr_of_ways(cache_nr_of_ways), .aw_offset(cache_aw_offset), .aw_slot(cache_aw_slot), .valid_mem(cache_valid_mem) )
4945 
cache0 (
4946 
    .wbs_dat_i(wbm1_dat_o),
4947 
    .wbs_adr_i(wbm1_adr_o),
4948 
    .wbs_sel_i(wbm1_sel_o),
4949 
    .wbs_cti_i(wbm1_cti_o),
4950 
    .wbs_bte_i(wbm1_bte_o),
4951 
    .wbs_we_i (wbm1_we_o),
4952 
    .wbs_stb_i(wbm1_stb_o),
4953 
    .wbs_cyc_i(wbm1_cyc_o),
4954 
    .wbs_dat_o(wbm1_dat_i),
4955 
    .wbs_ack_o(wbm1_ack_i),
4956 
    .wbs_stall_o(wbm1_stall_i),
4957 
    .wbs_clk(wb_clk),
4958 
    .wbs_rst(wb_rst),
4959 
    .wbm_dat_o(wbm2_dat_o),
4960 
    .wbm_adr_o(wbm2_adr_o),
4961 
    .wbm_sel_o(wbm2_sel_o),
4962 
    .wbm_cti_o(wbm2_cti_o),
4963 
    .wbm_bte_o(wbm2_bte_o),
4964 
    .wbm_we_o (wbm2_we_o),
4965 
    .wbm_stb_o(wbm2_stb_o),
4966 
    .wbm_cyc_o(wbm2_cyc_o),
4967 
    .wbm_dat_i(wbm2_dat_i),
4968 
    .wbm_ack_i(wbm2_ack_i),
4969 
    .wbm_stall_i(wbm2_stall_i),
4970 
    .wbm_clk(mem_clk),
4971 
    .wbm_rst(mem_rst) );
4972 
vl_wb_sdr_sdram # (
4973 
    .dat_size(mem_dat_size), .ba_size(mem_ba_size), .row_size(mem_row_size), .col_size(mem_col_size), .cl(mem_cl), .tRFC(mem_tRFC), .tRP(mem_tRP), .tRCD(mem_tRCD), .tMRD(mem_tMRD), .rfr_length(mem_rfr_length), .rfr_wrap_value(mem_rfr_wrap_value) )
4974 
ctrl0(
4975 
    // wisbone i/f
4976 
    .dat_i(wbm2_dat_o),
4977 
    .adr_i(wbm2_adr_o),
4978 
    .sel_i(wbm2_sel_o),
4979 
    .we_i (wbm2_we_o),
4980 
    .cyc_i(wbm2_cyc_o),
4981 
    .stb_i(wbm2_stb_o),
4982 
    .dat_o(wbm2_dat_i),
4983 
    .ack_o(wbm2_ack_i),
4984 
    .stall_o(wbm2_stall_i),
4985 
    // SDR SDRAM
4986 
    .ba(mem_ba),
4987 
    .a(mem_a),
4988 
    .cmd(mem_cmd),
4989 
    .cke(mem_cke),
4990 
    .cs_n(mem_cs_n),
4991 
    .dqm(mem_dqm),
4992 
    .dq_i(mem_dq_i),
4993 
    .dq_o(mem_dq_o),
4994 
    .dq_oe(mem_dq_oe),
4995 
    // system
4996 
    .clk(mem_clk),
4997 
    .rst(mem_rst) );
4998 
endmodule
4999 18 unneback 
//////////////////////////////////////////////////////////////////////
5000 
////                                                              ////
5001 
////  Arithmetic functions                                        ////
5002 
////                                                              ////
5003 
////  Description                                                 ////
5004 
////  Arithmetic functions for ALU and DSP                        ////
5005 
////                                                              ////
5006 
////                                                              ////
5007 
////  To Do:                                                      ////
5008 
////   -                                                          ////
5009 
////                                                              ////
5010 
////  Author(s):                                                  ////
5011 
////      - Michael Unneback, unneback@opencores.org              ////
5012 
////        ORSoC AB                                              ////
5013 
////                                                              ////
5014 
//////////////////////////////////////////////////////////////////////
5015 
////                                                              ////
5016 
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
5017 
////                                                              ////
5018 
//// This source file may be used and distributed without         ////
5019 
//// restriction provided that this copyright statement is not    ////
5020 
//// removed from the file and that any derivative work contains  ////
5021 
//// the original copyright notice and the associated disclaimer. ////
5022 
////                                                              ////
5023 
//// This source file is free software; you can redistribute it   ////
5024 
//// and/or modify it under the terms of the GNU Lesser General   ////
5025 
//// Public License as published by the Free Software Foundation; ////
5026 
//// either version 2.1 of the License, or (at your option) any   ////
5027 
//// later version.                                               ////
5028 
////                                                              ////
5029 
//// This source is distributed in the hope that it will be       ////
5030 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
5031 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
5032 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
5033 
//// details.                                                     ////
5034 
////                                                              ////
5035 
//// You should have received a copy of the GNU Lesser General    ////
5036 
//// Public License along with this source; if not, download it   ////
5037 
//// from http://www.opencores.org/lgpl.shtml                     ////
5038 
////                                                              ////
5039 
//////////////////////////////////////////////////////////////////////
5040 
// signed multiplication
5041 
module vl_mults (a,b,p);
5042 
parameter operand_a_width = 18;
5043 
parameter operand_b_width = 18;
5044 
parameter result_hi = 35;
5045 
parameter result_lo = 0;
5046 
input [operand_a_width-1:0] a;
5047 
input [operand_b_width-1:0] b;
5048 
output [result_hi:result_lo] p;
5049 
wire signed [operand_a_width-1:0] ai;
5050 
wire signed [operand_b_width-1:0] bi;
5051 
wire signed [operand_a_width+operand_b_width-1:0] result;
5052 
    assign ai = a;
5053 
    assign bi = b;
5054 
    assign result = ai * bi;
5055 
    assign p = result[result_hi:result_lo];
5056 
endmodule
5057 
module vl_mults18x18 (a,b,p);
5058 
input [17:0] a,b;
5059 
output [35:0] p;
5060 
vl_mult
5061 
    # (.operand_a_width(18), .operand_b_width(18))
5062 
    mult0 (.a(a), .b(b), .p(p));
5063 
endmodule
5064 
// unsigned multiplication
5065 
module vl_mult (a,b,p);
5066 
parameter operand_a_width = 18;
5067 
parameter operand_b_width = 18;
5068 
parameter result_hi = 35;
5069 
parameter result_lo = 0;
5070 
input [operand_a_width-1:0] a;
5071 
input [operand_b_width-1:0] b;
5072 
output [result_hi:result_hi] p;
5073 
wire [operand_a_width+operand_b_width-1:0] result;
5074 
    assign result = a * b;
5075 
    assign p = result[result_hi:result_lo];
5076 
endmodule
5077 
// shift unit
5078 
// supporting the following shift functions
5079 
//   SLL
5080 
//   SRL
5081 
//   SRA
5082 
module vl_shift_unit_32( din, s, dout, opcode);
5083 
input [31:0] din; // data in operand
5084 
input [4:0] s; // shift operand
5085 
input [1:0] opcode;
5086 
output [31:0] dout;
5087 
parameter opcode_sll = 2'b00;
5088 
//parameter opcode_srl = 2'b01;
5089 
parameter opcode_sra = 2'b10;
5090 
//parameter opcode_ror = 2'b11;
5091 
wire sll, sra;
5092 
assign sll = opcode == opcode_sll;
5093 
assign sra = opcode == opcode_sra;
5094 
wire [15:1] s1;
5095 
wire [3:0] sign;
5096 
wire [7:0] tmp [0:3];
5097 
// first stage is multiplier based
5098 
// shift operand as fractional 8.7
5099 
assign s1[15] = sll & s[2:0]==3'd7;
5100 
assign s1[14] = sll & s[2:0]==3'd6;
5101 
assign s1[13] = sll & s[2:0]==3'd5;
5102 
assign s1[12] = sll & s[2:0]==3'd4;
5103 
assign s1[11] = sll & s[2:0]==3'd3;
5104 
assign s1[10] = sll & s[2:0]==3'd2;
5105 
assign s1[ 9] = sll & s[2:0]==3'd1;
5106 
assign s1[ 8] = s[2:0]==3'd0;
5107 
assign s1[ 7] = !sll & s[2:0]==3'd1;
5108 
assign s1[ 6] = !sll & s[2:0]==3'd2;
5109 
assign s1[ 5] = !sll & s[2:0]==3'd3;
5110 
assign s1[ 4] = !sll & s[2:0]==3'd4;
5111 
assign s1[ 3] = !sll & s[2:0]==3'd5;
5112 
assign s1[ 2] = !sll & s[2:0]==3'd6;
5113 
assign s1[ 1] = !sll & s[2:0]==3'd7;
5114 
assign sign[3] = din[31] & sra;
5115 
assign sign[2] = sign[3] & (&din[31:24]);
5116 
assign sign[1] = sign[2] & (&din[23:16]);
5117 
assign sign[0] = sign[1] & (&din[15:8]);
5118 
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte3 ( .a({sign[3], {8{sign[3]}},din[31:24], din[23:16]}), .b({1'b0,s1}), .p(tmp[3]));
5119 
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte2 ( .a({sign[2], din[31:24]  ,din[23:16],  din[15:8]}), .b({1'b0,s1}), .p(tmp[2]));
5120 
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte1 ( .a({sign[1], din[23:16]  ,din[15:8],   din[7:0]}), .b({1'b0,s1}), .p(tmp[1]));
5121 
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte0 ( .a({sign[0], din[15:8]   ,din[7:0],    8'h00}),      .b({1'b0,s1}), .p(tmp[0]));
5122 
// second stage is multiplexer based
5123 
// shift on byte level
5124 
// mux byte 3
5125 
assign dout[31:24] = (s[4:3]==2'b00) ? tmp[3] :
5126 
                     (sll & s[4:3]==2'b01) ? tmp[2] :
5127 
                     (sll & s[4:3]==2'b10) ? tmp[1] :
5128 
                     (sll & s[4:3]==2'b11) ? tmp[0] :
5129 
                     {8{sign[3]}};
5130 
// mux byte 2
5131 
assign dout[23:16] = (s[4:3]==2'b00) ? tmp[2] :
5132 
                     (sll & s[4:3]==2'b01) ? tmp[1] :
5133 
                     (sll & s[4:3]==2'b10) ? tmp[0] :
5134 
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
5135 
                     (s[4:3]==2'b01) ? tmp[3] :
5136 
                     {8{sign[3]}};
5137 
// mux byte 1
5138 
assign dout[15:8]  = (s[4:3]==2'b00) ? tmp[1] :
5139 
                     (sll & s[4:3]==2'b01) ? tmp[0] :
5140 
                     (sll & s[4:3]==2'b10) ? {8{1'b0}} :
5141 
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
5142 
                     (s[4:3]==2'b01) ? tmp[2] :
5143 
                     (s[4:3]==2'b10) ? tmp[3] :
5144 
                     {8{sign[3]}};
5145 
// mux byte 0
5146 
assign dout[7:0]   = (s[4:3]==2'b00) ? tmp[0] :
5147 
                     (sll) ?  {8{1'b0}}:
5148 
                     (s[4:3]==2'b01) ? tmp[1] :
5149 
                     (s[4:3]==2'b10) ? tmp[2] :
5150 
                     tmp[3];
5151 
endmodule
5152 
// logic unit
5153 
// supporting the following logic functions
5154 
//    a and b
5155 
//    a or  b
5156 
//    a xor b
5157 
//    not b
5158 
module vl_logic_unit( a, b, result, opcode);
5159 
parameter width = 32;
5160 
parameter opcode_and = 2'b00;
5161 
parameter opcode_or  = 2'b01;
5162 
parameter opcode_xor = 2'b10;
5163 
input [width-1:0] a,b;
5164 
output [width-1:0] result;
5165 
input [1:0] opcode;
5166 
assign result = (opcode==opcode_and) ? a & b :
5167 
                (opcode==opcode_or)  ? a | b :
5168 
                (opcode==opcode_xor) ? a ^ b :
5169 
                b;
5170 
endmodule

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