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1 6 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
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////  Versatile library, clock and reset                          ////
4
////                                                              ////
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////  Description                                                 ////
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////  Logic related to clock and reset                            ////
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////                                                              ////
8
////                                                              ////
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////  To Do:                                                      ////
10
////   - add more different registers                             ////
11
////                                                              ////
12
////  Author(s):                                                  ////
13
////      - Michael Unneback, unneback@opencores.org              ////
14
////        ORSoC AB                                              ////
15
////                                                              ////
16
//////////////////////////////////////////////////////////////////////
17
////                                                              ////
18
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
19
////                                                              ////
20
//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
36
////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
// Global buffer
43
// usage:
44
// use to enable global buffers for high fan out signals such as clock and reset
45
`timescale 1 ns/100 ps
46
// Version: 8.4 8.4.0.33
47
module gbuf(GL,CLK);
48
output GL;
49
input  CLK;
50
    wire GND;
51
    GND GND_1_net(.Y(GND));
52
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
53
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
54
endmodule
55
`timescale 1 ns/1 ns
56
module vl_gbuf ( i, o);
57
input i;
58
output o;
59
`ifdef SIM_GBUF
60
assign o=i;
61
`else
62
gbuf gbuf_i0 ( .CLK(i), .GL(o));
63
`endif
64
endmodule
65
 //ACTEL
66
// sync reset
67
// input active lo async reset, normally from external reset generetaor and/or switch
68
// output active high global reset sync with two DFFs 
69
`timescale 1 ns/100 ps
70
module vl_sync_rst ( rst_n_i, rst_o, clk);
71
input rst_n_i, clk;
72
output rst_o;
73
reg [0:1] tmp;
74
always @ (posedge clk or negedge rst_n_i)
75
if (!rst_n_i)
76
        tmp <= 2'b00;
77
else
78
        tmp <= {1'b1,tmp[0]};
79
vl_gbuf buf_i0( .i(tmp[1]), .o(rst_o));
80
endmodule
81
// vl_pll
82
`timescale 1 ns/100 ps
83
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
84
parameter index = 0;
85
parameter number_of_clk = 1;
86
parameter period_time_0 = 20;
87
parameter period_time_1 = 20;
88
parameter period_time_2 = 20;
89
parameter lock_delay = 2000;
90
input clk_i, rst_n_i;
91
output lock;
92
output reg [0:number_of_clk-1] clk_o;
93
output [0:number_of_clk-1] rst_o;
94
`ifdef SIM_PLL
95
always
96
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
97
generate if (number_of_clk > 1)
98
always
99
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
100
endgenerate
101
generate if (number_of_clk > 2)
102
always
103
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
104
endgenerate
105
genvar i;
106
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
107
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
108
end
109
endgenerate
110
assign #lock_delay lock = rst_n_i;
111
endmodule
112
`else
113
generate if (number_of_clk==1 & index==0) begin
114
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
115
end
116
endgenerate // index==0
117
generate if (number_of_clk==1 & index==1) begin
118
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
119
end
120
endgenerate // index==1
121
generate if (number_of_clk==1 & index==2) begin
122
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
123
end
124
endgenerate // index==2
125
generate if (number_of_clk==1 & index==3) begin
126
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
127
end
128
endgenerate // index==0
129
generate if (number_of_clk==2 & index==0) begin
130
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
131
end
132
endgenerate // index==0
133
generate if (number_of_clk==2 & index==1) begin
134
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
135
end
136
endgenerate // index==1
137
generate if (number_of_clk==2 & index==2) begin
138
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
139
end
140
endgenerate // index==2
141
generate if (number_of_clk==2 & index==3) begin
142
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
143
end
144
endgenerate // index==0
145
generate if (number_of_clk==3 & index==0) begin
146
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
147
end
148
endgenerate // index==0
149
generate if (number_of_clk==3 & index==1) begin
150
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
151
end
152
endgenerate // index==1
153
generate if (number_of_clk==3 & index==2) begin
154
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
155
end
156
endgenerate // index==2
157
generate if (number_of_clk==3 & index==3) begin
158
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
159
end
160
endgenerate // index==0
161
genvar i;
162
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
163
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
164
end
165
endgenerate
166
endmodule
167
`endif
168
 //actel
169
//////////////////////////////////////////////////////////////////////
170
////                                                              ////
171
////  Versatile library, registers                                ////
172
////                                                              ////
173
////  Description                                                 ////
174
////  Different type of registers                                 ////
175
////                                                              ////
176
////                                                              ////
177
////  To Do:                                                      ////
178
////   - add more different registers                             ////
179
////                                                              ////
180
////  Author(s):                                                  ////
181
////      - Michael Unneback, unneback@opencores.org              ////
182
////        ORSoC AB                                              ////
183
////                                                              ////
184
//////////////////////////////////////////////////////////////////////
185
////                                                              ////
186
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
187
////                                                              ////
188
//// This source file may be used and distributed without         ////
189
//// restriction provided that this copyright statement is not    ////
190
//// removed from the file and that any derivative work contains  ////
191
//// the original copyright notice and the associated disclaimer. ////
192
////                                                              ////
193
//// This source file is free software; you can redistribute it   ////
194
//// and/or modify it under the terms of the GNU Lesser General   ////
195
//// Public License as published by the Free Software Foundation; ////
196
//// either version 2.1 of the License, or (at your option) any   ////
197
//// later version.                                               ////
198
////                                                              ////
199
//// This source is distributed in the hope that it will be       ////
200
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
201
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
202
//// PURPOSE.  See the GNU Lesser General Public License for more ////
203
//// details.                                                     ////
204
////                                                              ////
205
//// You should have received a copy of the GNU Lesser General    ////
206
//// Public License along with this source; if not, download it   ////
207
//// from http://www.opencores.org/lgpl.shtml                     ////
208
////                                                              ////
209
//////////////////////////////////////////////////////////////////////
210
module dff ( d, q, clk, rst);
211
        parameter width = 1;
212
        parameter reset_value = 0;
213
        input [width-1:0] d;
214
        input clk, rst;
215
        output reg [width-1:0] q;
216
        always @ (posedge clk or posedge rst)
217
        if (rst)
218
                q <= reset_value;
219
        else
220
                q <= d;
221
endmodule
222
module dff_array ( d, q, clk, rst);
223
        parameter width = 1;
224
        parameter depth = 2;
225
        parameter reset_value = 1'b0;
226
        input [width-1:0] d;
227
        input clk, rst;
228
        output [width-1:0] q;
229
        reg  [0:depth-1] q_tmp [width-1:0];
230
        integer i;
231
        always @ (posedge clk or posedge rst)
232
        if (rst) begin
233
            for (i=0;i<depth;i=i+1)
234
                q_tmp[i] <= {width{reset_value}};
235
        end else begin
236
            q_tmp[0] <= d;
237
            for (i=1;i<depth;i=i+1)
238
                q_tmp[i] <= q_tmp[i-1];
239
        end
240
    assign q = q_tmp[depth-1];
241
endmodule
242
module dff_ce ( d, ce, q, clk, rst);
243
        parameter width = 1;
244
        parameter reset_value = 0;
245
        input [width-1:0] d;
246
        input ce, clk, rst;
247
        output reg [width-1:0] q;
248
        always @ (posedge clk or posedge rst)
249
        if (rst)
250
                q <= reset_value;
251
        else
252
                if (ce)
253
                        q <= d;
254
endmodule
255 8 unneback
module dff_ce_clear ( d, ce, clear, q, clk, rst);
256
        parameter width = 1;
257
        parameter reset_value = 0;
258
        input [width-1:0] d;
259 10 unneback
        input ce, clear, clk, rst;
260 8 unneback
        output reg [width-1:0] q;
261
        always @ (posedge clk or posedge rst)
262
        if (rst)
263
            q <= reset_value;
264
        else
265
            if (ce)
266
                if (clear)
267
                    q <= {width{1'b0}};
268
                else
269
                    q <= d;
270
endmodule
271 6 unneback
module dff_sr ( aclr, aset, clock, data, q);
272
    input         aclr;
273
    input         aset;
274
    input         clock;
275
    input         data;
276
    output reg    q;
277
   always @ (posedge clock or posedge aclr or posedge aset)
278
     if (aclr)
279
       q <= 1'b0;
280
     else if (aset)
281
       q <= 1'b1;
282
     else
283
       q <= data;
284
endmodule
285
// LATCH
286
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
287
module latch ( d, le, q, clk);
288
input d, le;
289
output q;
290
input clk;/*
291
   always @ (posedge direction_set or posedge direction_clr)
292
     if (direction_clr)
293
       direction <= going_empty;
294
     else
295
       direction <= going_full;*/
296
endmodule
297
//////////////////////////////////////////////////////////////////////
298
////                                                              ////
299
////  Versatile counter                                           ////
300
////                                                              ////
301
////  Description                                                 ////
302
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
303
////  counter                                                     ////
304
////                                                              ////
305
////  To Do:                                                      ////
306
////   - add LFSR with more taps                                  ////
307
////                                                              ////
308
////  Author(s):                                                  ////
309
////      - Michael Unneback, unneback@opencores.org              ////
310
////        ORSoC AB                                              ////
311
////                                                              ////
312
//////////////////////////////////////////////////////////////////////
313
////                                                              ////
314
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
315
////                                                              ////
316
//// This source file may be used and distributed without         ////
317
//// restriction provided that this copyright statement is not    ////
318
//// removed from the file and that any derivative work contains  ////
319
//// the original copyright notice and the associated disclaimer. ////
320
////                                                              ////
321
//// This source file is free software; you can redistribute it   ////
322
//// and/or modify it under the terms of the GNU Lesser General   ////
323
//// Public License as published by the Free Software Foundation; ////
324
//// either version 2.1 of the License, or (at your option) any   ////
325
//// later version.                                               ////
326
////                                                              ////
327
//// This source is distributed in the hope that it will be       ////
328
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
329
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
330
//// PURPOSE.  See the GNU Lesser General Public License for more ////
331
//// details.                                                     ////
332
////                                                              ////
333
//// You should have received a copy of the GNU Lesser General    ////
334
//// Public License along with this source; if not, download it   ////
335
//// from http://www.opencores.org/lgpl.shtml                     ////
336
////                                                              ////
337
//////////////////////////////////////////////////////////////////////
338
// binary counter
339
module cnt_bin_ce ( cke, q, rst, clk);
340
   parameter length = 4;
341
   input cke;
342
   output [length:1] q;
343
   input rst;
344
   input clk;
345
   parameter clear_value = 0;
346
   parameter set_value = 1;
347
   parameter wrap_value = 0;
348
   parameter level1_value = 15;
349
   reg  [length:1] qi;
350
   wire [length:1] q_next;
351
   assign q_next = qi + {{length-1{1'b0}},1'b1};
352
   always @ (posedge clk or posedge rst)
353
     if (rst)
354
       qi <= {length{1'b0}};
355
     else
356
     if (cke)
357
       qi <= q_next;
358
   assign q = qi;
359
endmodule
360
//////////////////////////////////////////////////////////////////////
361
////                                                              ////
362
////  Versatile counter                                           ////
363
////                                                              ////
364
////  Description                                                 ////
365
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
366
////  counter                                                     ////
367
////                                                              ////
368
////  To Do:                                                      ////
369
////   - add LFSR with more taps                                  ////
370
////                                                              ////
371
////  Author(s):                                                  ////
372
////      - Michael Unneback, unneback@opencores.org              ////
373
////        ORSoC AB                                              ////
374
////                                                              ////
375
//////////////////////////////////////////////////////////////////////
376
////                                                              ////
377
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
378
////                                                              ////
379
//// This source file may be used and distributed without         ////
380
//// restriction provided that this copyright statement is not    ////
381
//// removed from the file and that any derivative work contains  ////
382
//// the original copyright notice and the associated disclaimer. ////
383
////                                                              ////
384
//// This source file is free software; you can redistribute it   ////
385
//// and/or modify it under the terms of the GNU Lesser General   ////
386
//// Public License as published by the Free Software Foundation; ////
387
//// either version 2.1 of the License, or (at your option) any   ////
388
//// later version.                                               ////
389
////                                                              ////
390
//// This source is distributed in the hope that it will be       ////
391
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
392
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
393
//// PURPOSE.  See the GNU Lesser General Public License for more ////
394
//// details.                                                     ////
395
////                                                              ////
396
//// You should have received a copy of the GNU Lesser General    ////
397
//// Public License along with this source; if not, download it   ////
398
//// from http://www.opencores.org/lgpl.shtml                     ////
399
////                                                              ////
400
//////////////////////////////////////////////////////////////////////
401
// binary counter
402
module cnt_bin_ce_clear ( clear, cke, q, rst, clk);
403
   parameter length = 4;
404
   input clear;
405
   input cke;
406
   output [length:1] q;
407
   input rst;
408
   input clk;
409
   parameter clear_value = 0;
410
   parameter set_value = 1;
411
   parameter wrap_value = 0;
412
   parameter level1_value = 15;
413
   reg  [length:1] qi;
414
   wire [length:1] q_next;
415
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
416
   always @ (posedge clk or posedge rst)
417
     if (rst)
418
       qi <= {length{1'b0}};
419
     else
420
     if (cke)
421
       qi <= q_next;
422
   assign q = qi;
423
endmodule
424
//////////////////////////////////////////////////////////////////////
425
////                                                              ////
426
////  Versatile counter                                           ////
427
////                                                              ////
428
////  Description                                                 ////
429
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
430
////  counter                                                     ////
431
////                                                              ////
432
////  To Do:                                                      ////
433
////   - add LFSR with more taps                                  ////
434
////                                                              ////
435
////  Author(s):                                                  ////
436
////      - Michael Unneback, unneback@opencores.org              ////
437
////        ORSoC AB                                              ////
438
////                                                              ////
439
//////////////////////////////////////////////////////////////////////
440
////                                                              ////
441
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
442
////                                                              ////
443
//// This source file may be used and distributed without         ////
444
//// restriction provided that this copyright statement is not    ////
445
//// removed from the file and that any derivative work contains  ////
446
//// the original copyright notice and the associated disclaimer. ////
447
////                                                              ////
448
//// This source file is free software; you can redistribute it   ////
449
//// and/or modify it under the terms of the GNU Lesser General   ////
450
//// Public License as published by the Free Software Foundation; ////
451
//// either version 2.1 of the License, or (at your option) any   ////
452
//// later version.                                               ////
453
////                                                              ////
454
//// This source is distributed in the hope that it will be       ////
455
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
456
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
457
//// PURPOSE.  See the GNU Lesser General Public License for more ////
458
//// details.                                                     ////
459
////                                                              ////
460
//// You should have received a copy of the GNU Lesser General    ////
461
//// Public License along with this source; if not, download it   ////
462
//// from http://www.opencores.org/lgpl.shtml                     ////
463
////                                                              ////
464
//////////////////////////////////////////////////////////////////////
465
// binary counter
466
module cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk);
467
   parameter length = 4;
468
   input clear;
469
   input set;
470
   input cke;
471
   input rew;
472
   output [length:1] q;
473
   input rst;
474
   input clk;
475
   parameter clear_value = 0;
476
   parameter set_value = 1;
477
   parameter wrap_value = 0;
478
   parameter level1_value = 15;
479
   reg  [length:1] qi;
480
   wire  [length:1] q_next, q_next_fw, q_next_rew;
481
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
482
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
483
   assign q_next = rew ? q_next_rew : q_next_fw;
484
   always @ (posedge clk or posedge rst)
485
     if (rst)
486
       qi <= {length{1'b0}};
487
     else
488
     if (cke)
489
       qi <= q_next;
490
   assign q = qi;
491
endmodule
492
//////////////////////////////////////////////////////////////////////
493
////                                                              ////
494
////  Versatile counter                                           ////
495
////                                                              ////
496
////  Description                                                 ////
497
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
498
////  counter                                                     ////
499
////                                                              ////
500
////  To Do:                                                      ////
501
////   - add LFSR with more taps                                  ////
502
////                                                              ////
503
////  Author(s):                                                  ////
504
////      - Michael Unneback, unneback@opencores.org              ////
505
////        ORSoC AB                                              ////
506
////                                                              ////
507
//////////////////////////////////////////////////////////////////////
508
////                                                              ////
509
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
510
////                                                              ////
511
//// This source file may be used and distributed without         ////
512
//// restriction provided that this copyright statement is not    ////
513
//// removed from the file and that any derivative work contains  ////
514
//// the original copyright notice and the associated disclaimer. ////
515
////                                                              ////
516
//// This source file is free software; you can redistribute it   ////
517
//// and/or modify it under the terms of the GNU Lesser General   ////
518
//// Public License as published by the Free Software Foundation; ////
519
//// either version 2.1 of the License, or (at your option) any   ////
520
//// later version.                                               ////
521
////                                                              ////
522
//// This source is distributed in the hope that it will be       ////
523
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
524
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
525
//// PURPOSE.  See the GNU Lesser General Public License for more ////
526
//// details.                                                     ////
527
////                                                              ////
528
//// You should have received a copy of the GNU Lesser General    ////
529
//// Public License along with this source; if not, download it   ////
530
//// from http://www.opencores.org/lgpl.shtml                     ////
531
////                                                              ////
532
//////////////////////////////////////////////////////////////////////
533
// binary counter
534
module cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk);
535
   parameter length = 4;
536
   input cke;
537
   input rew;
538
   output reg level1;
539
   input rst;
540
   input clk;
541
   parameter clear_value = 0;
542
   parameter set_value = 1;
543
   parameter wrap_value = 1;
544
   parameter level1_value = 15;
545
   reg  [length:1] qi;
546
   wire  [length:1] q_next, q_next_fw, q_next_rew;
547
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
548
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
549
   assign q_next = rew ? q_next_rew : q_next_fw;
550
   always @ (posedge clk or posedge rst)
551
     if (rst)
552
       qi <= {length{1'b0}};
553
     else
554
     if (cke)
555
       qi <= q_next;
556
    always @ (posedge clk or posedge rst)
557
    if (rst)
558
        level1 <= 1'b0;
559
    else
560
    if (cke)
561
    if (q_next == level1_value)
562
        level1 <= 1'b1;
563
    else if (qi == level1_value & rew)
564
        level1 <= 1'b0;
565
endmodule
566
//////////////////////////////////////////////////////////////////////
567
////                                                              ////
568
////  Versatile counter                                           ////
569
////                                                              ////
570
////  Description                                                 ////
571
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
572
////  counter                                                     ////
573
////                                                              ////
574
////  To Do:                                                      ////
575
////   - add LFSR with more taps                                  ////
576
////                                                              ////
577
////  Author(s):                                                  ////
578
////      - Michael Unneback, unneback@opencores.org              ////
579
////        ORSoC AB                                              ////
580
////                                                              ////
581
//////////////////////////////////////////////////////////////////////
582
////                                                              ////
583
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
584
////                                                              ////
585
//// This source file may be used and distributed without         ////
586
//// restriction provided that this copyright statement is not    ////
587
//// removed from the file and that any derivative work contains  ////
588
//// the original copyright notice and the associated disclaimer. ////
589
////                                                              ////
590
//// This source file is free software; you can redistribute it   ////
591
//// and/or modify it under the terms of the GNU Lesser General   ////
592
//// Public License as published by the Free Software Foundation; ////
593
//// either version 2.1 of the License, or (at your option) any   ////
594
//// later version.                                               ////
595
////                                                              ////
596
//// This source is distributed in the hope that it will be       ////
597
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
598
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
599
//// PURPOSE.  See the GNU Lesser General Public License for more ////
600
//// details.                                                     ////
601
////                                                              ////
602
//// You should have received a copy of the GNU Lesser General    ////
603
//// Public License along with this source; if not, download it   ////
604
//// from http://www.opencores.org/lgpl.shtml                     ////
605
////                                                              ////
606
//////////////////////////////////////////////////////////////////////
607
// LFSR counter
608
module cnt_lfsr_zq ( zq, rst, clk);
609
   parameter length = 4;
610
   output reg zq;
611
   input rst;
612
   input clk;
613
   parameter clear_value = 0;
614
   parameter set_value = 1;
615
   parameter wrap_value = 8;
616
   parameter level1_value = 15;
617
   reg  [length:1] qi;
618
   reg lfsr_fb;
619
   wire [length:1] q_next;
620
   reg [32:1] polynom;
621
   integer i;
622
   always @ (qi)
623
   begin
624
        case (length)
625
         2: polynom = 32'b11;                               // 0x3
626
         3: polynom = 32'b110;                              // 0x6
627
         4: polynom = 32'b1100;                             // 0xC
628
         5: polynom = 32'b10100;                            // 0x14
629
         6: polynom = 32'b110000;                           // 0x30
630
         7: polynom = 32'b1100000;                          // 0x60
631
         8: polynom = 32'b10111000;                         // 0xb8
632
         9: polynom = 32'b100010000;                        // 0x110
633
        10: polynom = 32'b1001000000;                       // 0x240
634
        11: polynom = 32'b10100000000;                      // 0x500
635
        12: polynom = 32'b100000101001;                     // 0x829
636
        13: polynom = 32'b1000000001100;                    // 0x100C
637
        14: polynom = 32'b10000000010101;                   // 0x2015
638
        15: polynom = 32'b110000000000000;                  // 0x6000
639
        16: polynom = 32'b1101000000001000;                 // 0xD008
640
        17: polynom = 32'b10010000000000000;                // 0x12000
641
        18: polynom = 32'b100000010000000000;               // 0x20400
642
        19: polynom = 32'b1000000000000100011;              // 0x40023
643
        20: polynom = 32'b10000010000000000000;             // 0x82000
644
        21: polynom = 32'b101000000000000000000;            // 0x140000
645
        22: polynom = 32'b1100000000000000000000;           // 0x300000
646
        23: polynom = 32'b10000100000000000000000;          // 0x420000
647
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
648
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
649
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
650
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
651
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
652
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
653
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
654
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
655
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
656
        default: polynom = 32'b0;
657
        endcase
658
        lfsr_fb = qi[length];
659
        for (i=length-1; i>=1; i=i-1) begin
660
            if (polynom[i])
661
                lfsr_fb = lfsr_fb  ~^ qi[i];
662
        end
663
    end
664
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
665
   always @ (posedge clk or posedge rst)
666
     if (rst)
667
       qi <= {length{1'b0}};
668
     else
669
       qi <= q_next;
670
   always @ (posedge clk or posedge rst)
671
     if (rst)
672
       zq <= 1'b1;
673
     else
674
       zq <= q_next == {length{1'b0}};
675
endmodule
676
//////////////////////////////////////////////////////////////////////
677
////                                                              ////
678
////  Versatile counter                                           ////
679
////                                                              ////
680
////  Description                                                 ////
681
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
682
////  counter                                                     ////
683
////                                                              ////
684
////  To Do:                                                      ////
685
////   - add LFSR with more taps                                  ////
686
////                                                              ////
687
////  Author(s):                                                  ////
688
////      - Michael Unneback, unneback@opencores.org              ////
689
////        ORSoC AB                                              ////
690
////                                                              ////
691
//////////////////////////////////////////////////////////////////////
692
////                                                              ////
693
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
694
////                                                              ////
695
//// This source file may be used and distributed without         ////
696
//// restriction provided that this copyright statement is not    ////
697
//// removed from the file and that any derivative work contains  ////
698
//// the original copyright notice and the associated disclaimer. ////
699
////                                                              ////
700
//// This source file is free software; you can redistribute it   ////
701
//// and/or modify it under the terms of the GNU Lesser General   ////
702
//// Public License as published by the Free Software Foundation; ////
703
//// either version 2.1 of the License, or (at your option) any   ////
704
//// later version.                                               ////
705
////                                                              ////
706
//// This source is distributed in the hope that it will be       ////
707
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
708
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
709
//// PURPOSE.  See the GNU Lesser General Public License for more ////
710
//// details.                                                     ////
711
////                                                              ////
712
//// You should have received a copy of the GNU Lesser General    ////
713
//// Public License along with this source; if not, download it   ////
714
//// from http://www.opencores.org/lgpl.shtml                     ////
715
////                                                              ////
716
//////////////////////////////////////////////////////////////////////
717
// LFSR counter
718
module cnt_lfsr_ce_zq ( cke, zq, rst, clk);
719
   parameter length = 4;
720
   input cke;
721
   output reg zq;
722
   input rst;
723
   input clk;
724
   parameter clear_value = 0;
725
   parameter set_value = 1;
726
   parameter wrap_value = 8;
727
   parameter level1_value = 15;
728
   reg  [length:1] qi;
729
   reg lfsr_fb;
730
   wire [length:1] q_next;
731
   reg [32:1] polynom;
732
   integer i;
733
   always @ (qi)
734
   begin
735
        case (length)
736
         2: polynom = 32'b11;                               // 0x3
737
         3: polynom = 32'b110;                              // 0x6
738
         4: polynom = 32'b1100;                             // 0xC
739
         5: polynom = 32'b10100;                            // 0x14
740
         6: polynom = 32'b110000;                           // 0x30
741
         7: polynom = 32'b1100000;                          // 0x60
742
         8: polynom = 32'b10111000;                         // 0xb8
743
         9: polynom = 32'b100010000;                        // 0x110
744
        10: polynom = 32'b1001000000;                       // 0x240
745
        11: polynom = 32'b10100000000;                      // 0x500
746
        12: polynom = 32'b100000101001;                     // 0x829
747
        13: polynom = 32'b1000000001100;                    // 0x100C
748
        14: polynom = 32'b10000000010101;                   // 0x2015
749
        15: polynom = 32'b110000000000000;                  // 0x6000
750
        16: polynom = 32'b1101000000001000;                 // 0xD008
751
        17: polynom = 32'b10010000000000000;                // 0x12000
752
        18: polynom = 32'b100000010000000000;               // 0x20400
753
        19: polynom = 32'b1000000000000100011;              // 0x40023
754
        20: polynom = 32'b10000010000000000000;             // 0x82000
755
        21: polynom = 32'b101000000000000000000;            // 0x140000
756
        22: polynom = 32'b1100000000000000000000;           // 0x300000
757
        23: polynom = 32'b10000100000000000000000;          // 0x420000
758
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
759
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
760
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
761
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
762
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
763
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
764
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
765
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
766
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
767
        default: polynom = 32'b0;
768
        endcase
769
        lfsr_fb = qi[length];
770
        for (i=length-1; i>=1; i=i-1) begin
771
            if (polynom[i])
772
                lfsr_fb = lfsr_fb  ~^ qi[i];
773
        end
774
    end
775
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
776
   always @ (posedge clk or posedge rst)
777
     if (rst)
778
       qi <= {length{1'b0}};
779
     else
780
     if (cke)
781
       qi <= q_next;
782
   always @ (posedge clk or posedge rst)
783
     if (rst)
784
       zq <= 1'b1;
785
     else
786
     if (cke)
787
       zq <= q_next == {length{1'b0}};
788
endmodule
789
//////////////////////////////////////////////////////////////////////
790
////                                                              ////
791
////  Versatile counter                                           ////
792
////                                                              ////
793
////  Description                                                 ////
794
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
795
////  counter                                                     ////
796
////                                                              ////
797
////  To Do:                                                      ////
798
////   - add LFSR with more taps                                  ////
799
////                                                              ////
800
////  Author(s):                                                  ////
801
////      - Michael Unneback, unneback@opencores.org              ////
802
////        ORSoC AB                                              ////
803
////                                                              ////
804
//////////////////////////////////////////////////////////////////////
805
////                                                              ////
806
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
807
////                                                              ////
808
//// This source file may be used and distributed without         ////
809
//// restriction provided that this copyright statement is not    ////
810
//// removed from the file and that any derivative work contains  ////
811
//// the original copyright notice and the associated disclaimer. ////
812
////                                                              ////
813
//// This source file is free software; you can redistribute it   ////
814
//// and/or modify it under the terms of the GNU Lesser General   ////
815
//// Public License as published by the Free Software Foundation; ////
816
//// either version 2.1 of the License, or (at your option) any   ////
817
//// later version.                                               ////
818
////                                                              ////
819
//// This source is distributed in the hope that it will be       ////
820
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
821
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
822
//// PURPOSE.  See the GNU Lesser General Public License for more ////
823
//// details.                                                     ////
824
////                                                              ////
825
//// You should have received a copy of the GNU Lesser General    ////
826
//// Public License along with this source; if not, download it   ////
827
//// from http://www.opencores.org/lgpl.shtml                     ////
828
////                                                              ////
829
//////////////////////////////////////////////////////////////////////
830
// LFSR counter
831
module cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk);
832
   parameter length = 4;
833
   input cke;
834
   input rew;
835
   output reg level1;
836
   input rst;
837
   input clk;
838
   parameter clear_value = 0;
839
   parameter set_value = 1;
840
   parameter wrap_value = 8;
841
   parameter level1_value = 15;
842
   reg  [length:1] qi;
843
   reg lfsr_fb, lfsr_fb_rew;
844
   wire  [length:1] q_next, q_next_fw, q_next_rew;
845
   reg [32:1] polynom_rew;
846
   integer j;
847
   reg [32:1] polynom;
848
   integer i;
849
   always @ (qi)
850
   begin
851
        case (length)
852
         2: polynom = 32'b11;                               // 0x3
853
         3: polynom = 32'b110;                              // 0x6
854
         4: polynom = 32'b1100;                             // 0xC
855
         5: polynom = 32'b10100;                            // 0x14
856
         6: polynom = 32'b110000;                           // 0x30
857
         7: polynom = 32'b1100000;                          // 0x60
858
         8: polynom = 32'b10111000;                         // 0xb8
859
         9: polynom = 32'b100010000;                        // 0x110
860
        10: polynom = 32'b1001000000;                       // 0x240
861
        11: polynom = 32'b10100000000;                      // 0x500
862
        12: polynom = 32'b100000101001;                     // 0x829
863
        13: polynom = 32'b1000000001100;                    // 0x100C
864
        14: polynom = 32'b10000000010101;                   // 0x2015
865
        15: polynom = 32'b110000000000000;                  // 0x6000
866
        16: polynom = 32'b1101000000001000;                 // 0xD008
867
        17: polynom = 32'b10010000000000000;                // 0x12000
868
        18: polynom = 32'b100000010000000000;               // 0x20400
869
        19: polynom = 32'b1000000000000100011;              // 0x40023
870
        20: polynom = 32'b10000010000000000000;             // 0x82000
871
        21: polynom = 32'b101000000000000000000;            // 0x140000
872
        22: polynom = 32'b1100000000000000000000;           // 0x300000
873
        23: polynom = 32'b10000100000000000000000;          // 0x420000
874
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
875
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
876
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
877
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
878
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
879
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
880
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
881
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
882
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
883
        default: polynom = 32'b0;
884
        endcase
885
        lfsr_fb = qi[length];
886
        for (i=length-1; i>=1; i=i-1) begin
887
            if (polynom[i])
888
                lfsr_fb = lfsr_fb  ~^ qi[i];
889
        end
890
    end
891
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
892
   always @ (qi)
893
   begin
894
        case (length)
895
         2: polynom_rew = 32'b11;
896
         3: polynom_rew = 32'b110;
897
         4: polynom_rew = 32'b1100;
898
         5: polynom_rew = 32'b10100;
899
         6: polynom_rew = 32'b110000;
900
         7: polynom_rew = 32'b1100000;
901
         8: polynom_rew = 32'b10111000;
902
         9: polynom_rew = 32'b100010000;
903
        10: polynom_rew = 32'b1001000000;
904
        11: polynom_rew = 32'b10100000000;
905
        12: polynom_rew = 32'b100000101001;
906
        13: polynom_rew = 32'b1000000001100;
907
        14: polynom_rew = 32'b10000000010101;
908
        15: polynom_rew = 32'b110000000000000;
909
        16: polynom_rew = 32'b1101000000001000;
910
        17: polynom_rew = 32'b10010000000000000;
911
        18: polynom_rew = 32'b100000010000000000;
912
        19: polynom_rew = 32'b1000000000000100011;
913
        20: polynom_rew = 32'b10000010000000000000;
914
        21: polynom_rew = 32'b101000000000000000000;
915
        22: polynom_rew = 32'b1100000000000000000000;
916
        23: polynom_rew = 32'b10000100000000000000000;
917
        24: polynom_rew = 32'b111000010000000000000000;
918
        25: polynom_rew = 32'b1001000000000000000000000;
919
        26: polynom_rew = 32'b10000000000000000000100011;
920
        27: polynom_rew = 32'b100000000000000000000010011;
921
        28: polynom_rew = 32'b1100100000000000000000000000;
922
        29: polynom_rew = 32'b10100000000000000000000000000;
923
        30: polynom_rew = 32'b100000000000000000000000101001;
924
        31: polynom_rew = 32'b1001000000000000000000000000000;
925
        32: polynom_rew = 32'b10000000001000000000000000000011;
926
        default: polynom_rew = 32'b0;
927
        endcase
928
        // rotate left
929
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
930
        lfsr_fb_rew = qi[length];
931
        for (i=length-1; i>=1; i=i-1) begin
932
            if (polynom_rew[i])
933
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
934
        end
935
    end
936
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
937
   assign q_next = rew ? q_next_rew : q_next_fw;
938
   always @ (posedge clk or posedge rst)
939
     if (rst)
940
       qi <= {length{1'b0}};
941
     else
942
     if (cke)
943
       qi <= q_next;
944
    always @ (posedge clk or posedge rst)
945
    if (rst)
946
        level1 <= 1'b0;
947
    else
948
    if (cke)
949
    if (q_next == level1_value)
950
        level1 <= 1'b1;
951
    else if (qi == level1_value & rew)
952
        level1 <= 1'b0;
953
endmodule
954
//////////////////////////////////////////////////////////////////////
955
////                                                              ////
956
////  Versatile counter                                           ////
957
////                                                              ////
958
////  Description                                                 ////
959
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
960
////  counter                                                     ////
961
////                                                              ////
962
////  To Do:                                                      ////
963
////   - add LFSR with more taps                                  ////
964
////                                                              ////
965
////  Author(s):                                                  ////
966
////      - Michael Unneback, unneback@opencores.org              ////
967
////        ORSoC AB                                              ////
968
////                                                              ////
969
//////////////////////////////////////////////////////////////////////
970
////                                                              ////
971
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
972
////                                                              ////
973
//// This source file may be used and distributed without         ////
974
//// restriction provided that this copyright statement is not    ////
975
//// removed from the file and that any derivative work contains  ////
976
//// the original copyright notice and the associated disclaimer. ////
977
////                                                              ////
978
//// This source file is free software; you can redistribute it   ////
979
//// and/or modify it under the terms of the GNU Lesser General   ////
980
//// Public License as published by the Free Software Foundation; ////
981
//// either version 2.1 of the License, or (at your option) any   ////
982
//// later version.                                               ////
983
////                                                              ////
984
//// This source is distributed in the hope that it will be       ////
985
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
986
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
987
//// PURPOSE.  See the GNU Lesser General Public License for more ////
988
//// details.                                                     ////
989
////                                                              ////
990
//// You should have received a copy of the GNU Lesser General    ////
991
//// Public License along with this source; if not, download it   ////
992
//// from http://www.opencores.org/lgpl.shtml                     ////
993
////                                                              ////
994
//////////////////////////////////////////////////////////////////////
995
// GRAY counter
996
module cnt_gray ( q, rst, clk);
997
   parameter length = 4;
998
   output reg [length:1] q;
999
   input rst;
1000
   input clk;
1001
   parameter clear_value = 0;
1002
   parameter set_value = 1;
1003
   parameter wrap_value = 8;
1004
   parameter level1_value = 15;
1005
   reg  [length:1] qi;
1006
   wire [length:1] q_next;
1007
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1008
   always @ (posedge clk or posedge rst)
1009
     if (rst)
1010
       qi <= {length{1'b0}};
1011
     else
1012
       qi <= q_next;
1013
   always @ (posedge clk or posedge rst)
1014
     if (rst)
1015
       q <= {length{1'b0}};
1016
     else
1017
         q <= (q_next>>1) ^ q_next;
1018
endmodule
1019
//////////////////////////////////////////////////////////////////////
1020
////                                                              ////
1021
////  Versatile counter                                           ////
1022
////                                                              ////
1023
////  Description                                                 ////
1024
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1025
////  counter                                                     ////
1026
////                                                              ////
1027
////  To Do:                                                      ////
1028
////   - add LFSR with more taps                                  ////
1029
////                                                              ////
1030
////  Author(s):                                                  ////
1031
////      - Michael Unneback, unneback@opencores.org              ////
1032
////        ORSoC AB                                              ////
1033
////                                                              ////
1034
//////////////////////////////////////////////////////////////////////
1035
////                                                              ////
1036
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1037
////                                                              ////
1038
//// This source file may be used and distributed without         ////
1039
//// restriction provided that this copyright statement is not    ////
1040
//// removed from the file and that any derivative work contains  ////
1041
//// the original copyright notice and the associated disclaimer. ////
1042
////                                                              ////
1043
//// This source file is free software; you can redistribute it   ////
1044
//// and/or modify it under the terms of the GNU Lesser General   ////
1045
//// Public License as published by the Free Software Foundation; ////
1046
//// either version 2.1 of the License, or (at your option) any   ////
1047
//// later version.                                               ////
1048
////                                                              ////
1049
//// This source is distributed in the hope that it will be       ////
1050
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1051
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1052
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1053
//// details.                                                     ////
1054
////                                                              ////
1055
//// You should have received a copy of the GNU Lesser General    ////
1056
//// Public License along with this source; if not, download it   ////
1057
//// from http://www.opencores.org/lgpl.shtml                     ////
1058
////                                                              ////
1059
//////////////////////////////////////////////////////////////////////
1060
// GRAY counter
1061
module cnt_gray_ce ( cke, q, rst, clk);
1062
   parameter length = 4;
1063
   input cke;
1064
   output reg [length:1] q;
1065
   input rst;
1066
   input clk;
1067
   parameter clear_value = 0;
1068
   parameter set_value = 1;
1069
   parameter wrap_value = 8;
1070
   parameter level1_value = 15;
1071
   reg  [length:1] qi;
1072
   wire [length:1] q_next;
1073
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1074
   always @ (posedge clk or posedge rst)
1075
     if (rst)
1076
       qi <= {length{1'b0}};
1077
     else
1078
     if (cke)
1079
       qi <= q_next;
1080
   always @ (posedge clk or posedge rst)
1081
     if (rst)
1082
       q <= {length{1'b0}};
1083
     else
1084
       if (cke)
1085
         q <= (q_next>>1) ^ q_next;
1086
endmodule
1087
//////////////////////////////////////////////////////////////////////
1088
////                                                              ////
1089
////  Versatile counter                                           ////
1090
////                                                              ////
1091
////  Description                                                 ////
1092
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1093
////  counter                                                     ////
1094
////                                                              ////
1095
////  To Do:                                                      ////
1096
////   - add LFSR with more taps                                  ////
1097
////                                                              ////
1098
////  Author(s):                                                  ////
1099
////      - Michael Unneback, unneback@opencores.org              ////
1100
////        ORSoC AB                                              ////
1101
////                                                              ////
1102
//////////////////////////////////////////////////////////////////////
1103
////                                                              ////
1104
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1105
////                                                              ////
1106
//// This source file may be used and distributed without         ////
1107
//// restriction provided that this copyright statement is not    ////
1108
//// removed from the file and that any derivative work contains  ////
1109
//// the original copyright notice and the associated disclaimer. ////
1110
////                                                              ////
1111
//// This source file is free software; you can redistribute it   ////
1112
//// and/or modify it under the terms of the GNU Lesser General   ////
1113
//// Public License as published by the Free Software Foundation; ////
1114
//// either version 2.1 of the License, or (at your option) any   ////
1115
//// later version.                                               ////
1116
////                                                              ////
1117
//// This source is distributed in the hope that it will be       ////
1118
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1119
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1120
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1121
//// details.                                                     ////
1122
////                                                              ////
1123
//// You should have received a copy of the GNU Lesser General    ////
1124
//// Public License along with this source; if not, download it   ////
1125
//// from http://www.opencores.org/lgpl.shtml                     ////
1126
////                                                              ////
1127
//////////////////////////////////////////////////////////////////////
1128
// GRAY counter
1129
module cnt_gray_ce_bin ( cke, q, q_bin, rst, clk);
1130
   parameter length = 4;
1131
   input cke;
1132
   output reg [length:1] q;
1133
   output [length:1] q_bin;
1134
   input rst;
1135
   input clk;
1136
   parameter clear_value = 0;
1137
   parameter set_value = 1;
1138
   parameter wrap_value = 8;
1139
   parameter level1_value = 15;
1140
   reg  [length:1] qi;
1141
   wire [length:1] q_next;
1142
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1143
   always @ (posedge clk or posedge rst)
1144
     if (rst)
1145
       qi <= {length{1'b0}};
1146
     else
1147
     if (cke)
1148
       qi <= q_next;
1149
   always @ (posedge clk or posedge rst)
1150
     if (rst)
1151
       q <= {length{1'b0}};
1152
     else
1153
       if (cke)
1154
         q <= (q_next>>1) ^ q_next;
1155
   assign q_bin = qi;
1156
endmodule
1157
//////////////////////////////////////////////////////////////////////
1158
////                                                              ////
1159
////  Versatile library, counters                                 ////
1160
////                                                              ////
1161
////  Description                                                 ////
1162
////  counters                                                    ////
1163
////                                                              ////
1164
////                                                              ////
1165
////  To Do:                                                      ////
1166
////   - add more counters                                        ////
1167
////                                                              ////
1168
////  Author(s):                                                  ////
1169
////      - Michael Unneback, unneback@opencores.org              ////
1170
////        ORSoC AB                                              ////
1171
////                                                              ////
1172
//////////////////////////////////////////////////////////////////////
1173
////                                                              ////
1174
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1175
////                                                              ////
1176
//// This source file may be used and distributed without         ////
1177
//// restriction provided that this copyright statement is not    ////
1178
//// removed from the file and that any derivative work contains  ////
1179
//// the original copyright notice and the associated disclaimer. ////
1180
////                                                              ////
1181
//// This source file is free software; you can redistribute it   ////
1182
//// and/or modify it under the terms of the GNU Lesser General   ////
1183
//// Public License as published by the Free Software Foundation; ////
1184
//// either version 2.1 of the License, or (at your option) any   ////
1185
//// later version.                                               ////
1186
////                                                              ////
1187
//// This source is distributed in the hope that it will be       ////
1188
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1189
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1190
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1191
//// details.                                                     ////
1192
////                                                              ////
1193
//// You should have received a copy of the GNU Lesser General    ////
1194
//// Public License along with this source; if not, download it   ////
1195
//// from http://www.opencores.org/lgpl.shtml                     ////
1196
////                                                              ////
1197
//////////////////////////////////////////////////////////////////////
1198
module cnt_shreg_wrap ( q, rst, clk);
1199
   parameter length = 4;
1200
   output reg [0:length-1] q;
1201
   input rst;
1202
   input clk;
1203
    always @ (posedge clk or posedge rst)
1204
    if (rst)
1205
        q <= {1'b1,{length-1{1'b0}}};
1206
    else
1207
        q <= {q[length-1],q[0:length-2]};
1208
endmodule
1209
module cnt_shreg_ce_wrap ( cke, q, rst, clk);
1210
   parameter length = 4;
1211
   input cke;
1212
   output reg [0:length-1] q;
1213
   input rst;
1214
   input clk;
1215
    always @ (posedge clk or posedge rst)
1216
    if (rst)
1217
        q <= {1'b1,{length-1{1'b0}}};
1218
    else
1219
        if (cke)
1220
            q <= {q[length-1],q[0:length-2]};
1221
endmodule
1222
module cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
1223
   parameter length = 4;
1224
   input cke, clear;
1225
   output reg [0:length-1] q;
1226
   input rst;
1227
   input clk;
1228
    always @ (posedge clk or posedge rst)
1229
    if (rst)
1230
        q <= {1'b1,{length-1{1'b0}}};
1231
    else
1232
        if (cke)
1233
            if (clear)
1234
                q <= {1'b1,{length-1{1'b0}}};
1235
            else
1236
                q <= q >> 1;
1237
endmodule
1238
module cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
1239
   parameter length = 4;
1240
   input cke, clear;
1241
   output reg [0:length-1] q;
1242
   input rst;
1243
   input clk;
1244
    always @ (posedge clk or posedge rst)
1245
    if (rst)
1246
        q <= {1'b1,{length-1{1'b0}}};
1247
    else
1248
        if (cke)
1249
            if (clear)
1250
                q <= {1'b1,{length-1{1'b0}}};
1251
            else
1252
            q <= {q[length-1],q[0:length-2]};
1253
endmodule
1254
//////////////////////////////////////////////////////////////////////
1255
////                                                              ////
1256
////  Versatile library, memories                                 ////
1257
////                                                              ////
1258
////  Description                                                 ////
1259
////  memories                                                    ////
1260
////                                                              ////
1261
////                                                              ////
1262
////  To Do:                                                      ////
1263
////   - add more memory types                                    ////
1264
////                                                              ////
1265
////  Author(s):                                                  ////
1266
////      - Michael Unneback, unneback@opencores.org              ////
1267
////        ORSoC AB                                              ////
1268
////                                                              ////
1269
//////////////////////////////////////////////////////////////////////
1270
////                                                              ////
1271
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1272
////                                                              ////
1273
//// This source file may be used and distributed without         ////
1274
//// restriction provided that this copyright statement is not    ////
1275
//// removed from the file and that any derivative work contains  ////
1276
//// the original copyright notice and the associated disclaimer. ////
1277
////                                                              ////
1278
//// This source file is free software; you can redistribute it   ////
1279
//// and/or modify it under the terms of the GNU Lesser General   ////
1280
//// Public License as published by the Free Software Foundation; ////
1281
//// either version 2.1 of the License, or (at your option) any   ////
1282
//// later version.                                               ////
1283
////                                                              ////
1284
//// This source is distributed in the hope that it will be       ////
1285
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1286
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1287
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1288
//// details.                                                     ////
1289
////                                                              ////
1290
//// You should have received a copy of the GNU Lesser General    ////
1291
//// Public License along with this source; if not, download it   ////
1292
//// from http://www.opencores.org/lgpl.shtml                     ////
1293
////                                                              ////
1294
//////////////////////////////////////////////////////////////////////
1295
/// ROM
1296 7 unneback
module vl_rom_init ( adr, q, clk);
1297
   parameter data_width = 32;
1298
   parameter addr_width = 8;
1299
   input [(addr_width-1):0]       adr;
1300
   output reg [(data_width-1):0] q;
1301
   input                         clk;
1302
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
1303
   parameter memory_file = "vl_rom.vmem";
1304
   initial
1305
     begin
1306
        $readmemh(memory_file, rom);
1307
     end
1308
   always @ (posedge clk)
1309
     q <= rom[adr];
1310
endmodule
1311 14 unneback
/*
1312 7 unneback
module vl_rom ( adr, q, clk);
1313 6 unneback
parameter data_width = 32;
1314
parameter addr_width = 4;
1315
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
1316
    {32'h18000000},
1317
    {32'hA8200000},
1318
    {32'hA8200000},
1319
    {32'hA8200000},
1320
    {32'h44003000},
1321
    {32'h15000000},
1322
    {32'h15000000},
1323
    {32'h15000000},
1324
    {32'h15000000},
1325
    {32'h15000000},
1326
    {32'h15000000},
1327
    {32'h15000000},
1328
    {32'h15000000},
1329
    {32'h15000000},
1330
    {32'h15000000},
1331
    {32'h15000000}};
1332 7 unneback
input [addr_width-1:0] adr;
1333 6 unneback
output reg [data_width-1:0] q;
1334
input clk;
1335
always @ (posedge clk)
1336 7 unneback
    q <= data[adr];
1337 6 unneback
endmodule
1338 14 unneback
*/
1339 6 unneback
// Single port RAM
1340
module vl_ram ( d, adr, we, q, clk);
1341
   parameter data_width = 32;
1342
   parameter addr_width = 8;
1343
   input [(data_width-1):0]      d;
1344
   input [(addr_width-1):0]       adr;
1345
   input                         we;
1346 7 unneback
   output reg [(data_width-1):0] q;
1347 6 unneback
   input                         clk;
1348
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
1349 7 unneback
   parameter init = 0;
1350
   parameter memory_file = "vl_ram.vmem";
1351
   generate if (init) begin : init_mem
1352
   initial
1353
     begin
1354
        $readmemh(memory_file, ram);
1355
     end
1356
   end
1357
   endgenerate
1358 6 unneback
   always @ (posedge clk)
1359
   begin
1360
   if (we)
1361
     ram[adr] <= d;
1362
   q <= ram[adr];
1363
   end
1364
endmodule
1365 7 unneback
module vl_ram_be ( d, adr, be, we, q, clk);
1366
   parameter data_width = 32;
1367
   parameter addr_width = 8;
1368
   input [(data_width-1):0]      d;
1369
   input [(addr_width-1):0]       adr;
1370
   input [(addr_width/4)-1:0]    be;
1371
   input                         we;
1372
   output reg [(data_width-1):0] q;
1373
   input                         clk;
1374
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
1375
   parameter init = 0;
1376
   parameter memory_file = "vl_ram.vmem";
1377
   generate if (init) begin : init_mem
1378
   initial
1379
     begin
1380
        $readmemh(memory_file, ram);
1381
     end
1382
   end
1383
   endgenerate
1384
   genvar i;
1385
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
1386
      always @ (posedge clk)
1387
      if (we & be[i])
1388
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
1389
   end
1390
   endgenerate
1391
   always @ (posedge clk)
1392
      q <= ram[adr];
1393
endmodule
1394 6 unneback
// Dual port RAM
1395
// ACTEL FPGA should not use logic to handle rw collision
1396 7 unneback
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1397 6 unneback
   parameter data_width = 32;
1398
   parameter addr_width = 8;
1399
   input [(data_width-1):0]      d_a;
1400
   input [(addr_width-1):0]       adr_a;
1401
   input [(addr_width-1):0]       adr_b;
1402
   input                         we_a;
1403
   output [(data_width-1):0]      q_b;
1404
   input                         clk_a, clk_b;
1405
   reg [(addr_width-1):0]         adr_b_reg;
1406
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
1407 7 unneback
   parameter init = 0;
1408
   parameter memory_file = "vl_ram.vmem";
1409
   generate if (init) begin : init_mem
1410
   initial
1411
     begin
1412
        $readmemh(memory_file, ram);
1413
     end
1414
   end
1415
   endgenerate
1416 6 unneback
   always @ (posedge clk_a)
1417
   if (we_a)
1418
     ram[adr_a] <= d_a;
1419
   always @ (posedge clk_b)
1420
   adr_b_reg <= adr_b;
1421
   assign q_b = ram[adr_b_reg];
1422
endmodule
1423 7 unneback
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1424 6 unneback
   parameter data_width = 32;
1425
   parameter addr_width = 8;
1426
   input [(data_width-1):0]      d_a;
1427
   input [(addr_width-1):0]       adr_a;
1428
   input [(addr_width-1):0]       adr_b;
1429
   input                         we_a;
1430
   output [(data_width-1):0]      q_b;
1431
   output reg [(data_width-1):0] q_a;
1432
   input                         clk_a, clk_b;
1433
   reg [(data_width-1):0]         q_b;
1434
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
1435 7 unneback
   parameter init = 0;
1436
   parameter memory_file = "vl_ram.vmem";
1437
   generate if (init) begin : init_mem
1438
   initial
1439
     begin
1440
        $readmemh(memory_file, ram);
1441
     end
1442
   end
1443
   endgenerate
1444 6 unneback
   always @ (posedge clk_a)
1445
     begin
1446
        q_a <= ram[adr_a];
1447
        if (we_a)
1448
             ram[adr_a] <= d_a;
1449
     end
1450
   always @ (posedge clk_b)
1451
          q_b <= ram[adr_b];
1452
endmodule
1453 7 unneback
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
1454 6 unneback
   parameter data_width = 32;
1455
   parameter addr_width = 8;
1456
   input [(data_width-1):0]      d_a;
1457
   input [(addr_width-1):0]       adr_a;
1458
   input [(addr_width-1):0]       adr_b;
1459
   input                         we_a;
1460
   output [(data_width-1):0]      q_b;
1461
   input [(data_width-1):0]       d_b;
1462
   output reg [(data_width-1):0] q_a;
1463
   input                         we_b;
1464
   input                         clk_a, clk_b;
1465
   reg [(data_width-1):0]         q_b;
1466
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
1467 7 unneback
   parameter init = 0;
1468
   parameter memory_file = "vl_ram.vmem";
1469
   generate if (init) begin : init_mem
1470
   initial
1471
     begin
1472
        $readmemh(memory_file, ram);
1473
     end
1474
   end
1475
   endgenerate
1476 6 unneback
   always @ (posedge clk_a)
1477
     begin
1478
        q_a <= ram[adr_a];
1479
        if (we_a)
1480
             ram[adr_a] <= d_a;
1481
     end
1482
   always @ (posedge clk_b)
1483
     begin
1484
        q_b <= ram[adr_b];
1485
        if (we_b)
1486
          ram[adr_b] <= d_b;
1487
     end
1488
endmodule
1489
// Content addresable memory, CAM
1490
// FIFO
1491
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
1492 11 unneback
   parameter addr_width = 4;
1493
   parameter N = addr_width-1;
1494 6 unneback
   parameter Q1 = 2'b00;
1495
   parameter Q2 = 2'b01;
1496
   parameter Q3 = 2'b11;
1497
   parameter Q4 = 2'b10;
1498
   parameter going_empty = 1'b0;
1499
   parameter going_full  = 1'b1;
1500
   input [N:0]  wptr, rptr;
1501 14 unneback
   output       fifo_empty;
1502 6 unneback
   output       fifo_full;
1503
   input        wclk, rclk, rst;
1504
   wire direction;
1505
   reg  direction_set, direction_clr;
1506
   wire async_empty, async_full;
1507
   wire fifo_full2;
1508 14 unneback
   wire fifo_empty2;
1509 6 unneback
   // direction_set
1510
   always @ (wptr[N:N-1] or rptr[N:N-1])
1511
     case ({wptr[N:N-1],rptr[N:N-1]})
1512
       {Q1,Q2} : direction_set <= 1'b1;
1513
       {Q2,Q3} : direction_set <= 1'b1;
1514
       {Q3,Q4} : direction_set <= 1'b1;
1515
       {Q4,Q1} : direction_set <= 1'b1;
1516
       default : direction_set <= 1'b0;
1517
     endcase
1518
   // direction_clear
1519
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
1520
     if (rst)
1521
       direction_clr <= 1'b1;
1522
     else
1523
       case ({wptr[N:N-1],rptr[N:N-1]})
1524
         {Q2,Q1} : direction_clr <= 1'b1;
1525
         {Q3,Q2} : direction_clr <= 1'b1;
1526
         {Q4,Q3} : direction_clr <= 1'b1;
1527
         {Q1,Q4} : direction_clr <= 1'b1;
1528
         default : direction_clr <= 1'b0;
1529
       endcase
1530
    dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
1531
   assign async_empty = (wptr == rptr) && (direction==going_empty);
1532
   assign async_full  = (wptr == rptr) && (direction==going_full);
1533
    dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
1534
    dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
1535
/*
1536
   always @ (posedge wclk or posedge rst or posedge async_full)
1537
     if (rst)
1538
       {fifo_full, fifo_full2} <= 2'b00;
1539
     else if (async_full)
1540
       {fifo_full, fifo_full2} <= 2'b11;
1541
     else
1542
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
1543
*/
1544 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
1545 6 unneback
     if (async_empty)
1546
       {fifo_empty, fifo_empty2} <= 2'b11;
1547
     else
1548 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
1549
    dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
1550
    dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
1551 6 unneback
endmodule // async_comp
1552
module vl_fifo_1r1w_async (
1553
    d, wr, fifo_full, wr_clk, wr_rst,
1554
    q, rd, fifo_empty, rd_clk, rd_rst
1555
    );
1556
parameter data_width = 18;
1557
parameter addr_width = 4;
1558
// write side
1559
input  [data_width-1:0] d;
1560
input                   wr;
1561
output                  fifo_full;
1562
input                   wr_clk;
1563
input                   wr_rst;
1564
// read side
1565
output [data_width-1:0] q;
1566
input                   rd;
1567
output                  fifo_empty;
1568
input                   rd_clk;
1569
input                   rd_rst;
1570
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
1571
vl_fifo_1r1w_async (
1572
    d, wr, fifo_full, wr_clk, wr_rst,
1573
    q, rd, fifo_empty, rd_clk, rd_rst
1574
    );
1575 7 unneback
cnt_gray_ce_bin
1576 6 unneback
    # ( .length(addr_width))
1577
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
1578 7 unneback
cnt_gray_ce_bin
1579 6 unneback
    # (.length(addr_width))
1580
    fifo_rd_adr( .cke(wr), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_rst));
1581 7 unneback
vl_dpram_1r1w
1582 6 unneback
    # (.data_width(data_width), .addr_width(addr_width))
1583
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
1584
vl_fifo_cmp_async
1585
    # (.addr_width(addr_width))
1586
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
1587
endmodule
1588 8 unneback
module vl_fifo_2r2w_async (
1589 6 unneback
    // a side
1590
    a_d, a_wr, a_fifo_full,
1591
    a_q, a_rd, a_fifo_empty,
1592
    a_clk, a_rst,
1593
    // b side
1594
    b_d, b_wr, b_fifo_full,
1595
    b_q, b_rd, b_fifo_empty,
1596
    b_clk, b_rst
1597
    );
1598
parameter data_width = 18;
1599
parameter addr_width = 4;
1600
// a side
1601
input  [data_width-1:0] a_d;
1602
input                   a_wr;
1603
output                  a_fifo_full;
1604
output [data_width-1:0] a_q;
1605
input                   a_rd;
1606
output                  a_fifo_empty;
1607
input                   a_clk;
1608
input                   a_rst;
1609
// b side
1610
input  [data_width-1:0] b_d;
1611
input                   b_wr;
1612
output                  b_fifo_full;
1613
output [data_width-1:0] b_q;
1614
input                   b_rd;
1615
output                  b_fifo_empty;
1616
input                   b_clk;
1617
input                   b_rst;
1618
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
1619
vl_fifo_1r1w_async_a (
1620
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
1621
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
1622
    );
1623
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
1624
vl_fifo_1r1w_async_b (
1625
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
1626
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
1627
    );
1628
endmodule
1629 8 unneback
module vl_fifo_2r2w_async_simplex (
1630 6 unneback
    // a side
1631
    a_d, a_wr, a_fifo_full,
1632
    a_q, a_rd, a_fifo_empty,
1633
    a_clk, a_rst,
1634
    // b side
1635
    b_d, b_wr, b_fifo_full,
1636
    b_q, b_rd, b_fifo_empty,
1637
    b_clk, b_rst
1638
    );
1639
parameter data_width = 18;
1640
parameter addr_width = 4;
1641
// a side
1642
input  [data_width-1:0] a_d;
1643
input                   a_wr;
1644
output                  a_fifo_full;
1645
output [data_width-1:0] a_q;
1646
input                   a_rd;
1647
output                  a_fifo_empty;
1648
input                   a_clk;
1649
input                   a_rst;
1650
// b side
1651
input  [data_width-1:0] b_d;
1652
input                   b_wr;
1653
output                  b_fifo_full;
1654
output [data_width-1:0] b_q;
1655
input                   b_rd;
1656
output                  b_fifo_empty;
1657
input                   b_clk;
1658
input                   b_rst;
1659
// adr_gen
1660
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
1661
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
1662
// dpram
1663
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
1664 7 unneback
cnt_gray_ce_bin
1665 6 unneback
    # ( .length(addr_width))
1666
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
1667 7 unneback
cnt_gray_ce_bin
1668 6 unneback
    # (.length(addr_width))
1669
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
1670 7 unneback
cnt_gray_ce_bin
1671 6 unneback
    # ( .length(addr_width))
1672
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
1673 7 unneback
cnt_gray_ce_bin
1674 6 unneback
    # (.length(addr_width))
1675
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
1676
// mux read or write adr to DPRAM
1677
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
1678
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
1679 11 unneback
vl_dpram_2r2w
1680 6 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
1681
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
1682
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
1683 11 unneback
vl_fifo_cmp_async
1684 6 unneback
    # (.addr_width(addr_width))
1685
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
1686 11 unneback
vl_fifo_cmp_async
1687 6 unneback
    # (.addr_width(addr_width))
1688
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
1689
endmodule
1690 12 unneback
//////////////////////////////////////////////////////////////////////
1691
////                                                              ////
1692
////  Versatile library, wishbone stuff                           ////
1693
////                                                              ////
1694
////  Description                                                 ////
1695
////  Wishbone compliant modules                                  ////
1696
////                                                              ////
1697
////                                                              ////
1698
////  To Do:                                                      ////
1699
////   -                                                          ////
1700
////                                                              ////
1701
////  Author(s):                                                  ////
1702
////      - Michael Unneback, unneback@opencores.org              ////
1703
////        ORSoC AB                                              ////
1704
////                                                              ////
1705
//////////////////////////////////////////////////////////////////////
1706
////                                                              ////
1707
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1708
////                                                              ////
1709
//// This source file may be used and distributed without         ////
1710
//// restriction provided that this copyright statement is not    ////
1711
//// removed from the file and that any derivative work contains  ////
1712
//// the original copyright notice and the associated disclaimer. ////
1713
////                                                              ////
1714
//// This source file is free software; you can redistribute it   ////
1715
//// and/or modify it under the terms of the GNU Lesser General   ////
1716
//// Public License as published by the Free Software Foundation; ////
1717
//// either version 2.1 of the License, or (at your option) any   ////
1718
//// later version.                                               ////
1719
////                                                              ////
1720
//// This source is distributed in the hope that it will be       ////
1721
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1722
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1723
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1724
//// details.                                                     ////
1725
////                                                              ////
1726
//// You should have received a copy of the GNU Lesser General    ////
1727
//// Public License along with this source; if not, download it   ////
1728
//// from http://www.opencores.org/lgpl.shtml                     ////
1729
////                                                              ////
1730
//////////////////////////////////////////////////////////////////////
1731
// async wb3 - wb3 bridge
1732
`timescale 1ns/1ns
1733
module wb3wb3_bridge (
1734
        // wishbone slave side
1735
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
1736
        // wishbone master side
1737
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
1738
input [31:0] wbs_dat_i;
1739
input [31:2] wbs_adr_i;
1740
input [3:0]  wbs_sel_i;
1741
input [1:0]  wbs_bte_i;
1742
input [2:0]  wbs_cti_i;
1743
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
1744
output [31:0] wbs_dat_o;
1745 14 unneback
output wbs_ack_o;
1746 12 unneback
input wbs_clk, wbs_rst;
1747
output [31:0] wbm_dat_o;
1748
output reg [31:2] wbm_adr_o;
1749
output [3:0]  wbm_sel_o;
1750
output reg [1:0]  wbm_bte_o;
1751
output reg [2:0]  wbm_cti_o;
1752 14 unneback
output reg wbm_we_o;
1753
output wbm_cyc_o;
1754 12 unneback
output wbm_stb_o;
1755
input [31:0]  wbm_dat_i;
1756
input wbm_ack_i;
1757
input wbm_clk, wbm_rst;
1758
parameter addr_width = 4;
1759
// bte
1760
parameter linear       = 2'b00;
1761
parameter wrap4        = 2'b01;
1762
parameter wrap8        = 2'b10;
1763
parameter wrap16       = 2'b11;
1764
// cti
1765
parameter classic      = 3'b000;
1766
parameter incburst     = 3'b010;
1767
parameter endofburst   = 3'b111;
1768
parameter wbs_adr  = 1'b0;
1769
parameter wbs_data = 1'b1;
1770
parameter wbm_adr0 = 2'b00;
1771
parameter wbm_adr1 = 2'b01;
1772
parameter wbm_data = 2'b10;
1773
reg [1:0] wbs_bte_reg;
1774
reg wbs;
1775
wire wbs_eoc_alert, wbm_eoc_alert;
1776
reg wbs_eoc, wbm_eoc;
1777
reg [1:0] wbm;
1778 14 unneback
wire [1:16] wbs_count, wbm_count;
1779 12 unneback
wire [35:0] a_d, a_q, b_d, b_q;
1780
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
1781
reg a_rd_reg;
1782
wire b_rd_adr, b_rd_data;
1783 14 unneback
wire b_rd_data_reg;
1784
wire [35:0] temp;
1785 12 unneback
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
1786
always @ (posedge wbs_clk or posedge wbs_rst)
1787
if (wbs_rst)
1788
        wbs_eoc <= 1'b0;
1789
else
1790
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
1791
                wbs_eoc <= wbs_bte_i==linear;
1792
        else if (wbs_eoc_alert & (a_rd | a_wr))
1793
                wbs_eoc <= 1'b1;
1794
cnt_shreg_ce_clear # ( .length(16))
1795
    cnt0 (
1796
        .cke(wbs_ack_o),
1797
        .clear(wbs_eoc),
1798
        .q(wbs_count),
1799
        .rst(wbs_rst),
1800
        .clk(wbs_clk));
1801
always @ (posedge wbs_clk or posedge wbs_rst)
1802
if (wbs_rst)
1803
        wbs <= wbs_adr;
1804
else
1805
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & !a_fifo_full)
1806
                wbs <= wbs_data;
1807
        else if (wbs_eoc & wbs_ack_o)
1808
                wbs <= wbs_adr;
1809
// wbs FIFO
1810
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,wbs_bte_i,wbs_cti_i} : {wbs_dat_i,wbs_sel_i};
1811
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & !a_fifo_full :
1812
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
1813
              1'b0;
1814
assign a_rd = !a_fifo_empty;
1815
always @ (posedge wbs_clk or posedge wbs_rst)
1816
if (wbs_rst)
1817
        a_rd_reg <= 1'b0;
1818
else
1819
        a_rd_reg <= a_rd;
1820
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
1821
assign wbs_dat_o = a_q[35:4];
1822
always @ (posedge wbs_clk or posedge wbs_rst)
1823
if (wbs_rst)
1824 13 unneback
        wbs_bte_reg <= 2'b00;
1825 12 unneback
else
1826 13 unneback
        wbs_bte_reg <= wbs_bte_i;
1827 12 unneback
// wbm FIFO
1828
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
1829
always @ (posedge wbm_clk or posedge wbm_rst)
1830
if (wbm_rst)
1831
        wbm_eoc <= 1'b0;
1832
else
1833
        if (wbm==wbm_adr0 & !b_fifo_empty)
1834
                wbm_eoc <= b_q[4:3] == linear;
1835
        else if (wbm_eoc_alert & wbm_ack_i)
1836
                wbm_eoc <= 1'b1;
1837
always @ (posedge wbm_clk or posedge wbm_rst)
1838
if (wbm_rst)
1839
        wbm <= wbm_adr0;
1840
else
1841
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
1842
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
1843
        (wbm==wbm_adr1 & !wbm_we_o) |
1844
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
1845
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
1846
assign b_d = {wbm_dat_i,4'b1111};
1847
assign b_wr = !wbm_we_o & wbm_ack_i;
1848
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
1849
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
1850
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
1851
                   1'b0;
1852
assign b_rd = b_rd_adr | b_rd_data;
1853
dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
1854
dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
1855
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
1856
cnt_shreg_ce_clear # ( .length(16))
1857
    cnt1 (
1858
        .cke(wbm_ack_i),
1859
        .clear(wbm_eoc),
1860
        .q(wbm_count),
1861
        .rst(wbm_rst),
1862
        .clk(wbm_clk));
1863
assign wbm_cyc_o = wbm==wbm_data;
1864
assign wbm_stb_o = (wbm==wbm_data & wbm_we_o) ? !b_fifo_empty :
1865
                   (wbm==wbm_data) ? 1'b1 :
1866
                   1'b0;
1867
always @ (posedge wbm_clk or posedge wbm_rst)
1868
if (wbm_rst)
1869
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
1870
else begin
1871
        if (wbm==wbm_adr0 & !b_fifo_empty)
1872
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
1873
        else if (wbm_eoc_alert & wbm_ack_i)
1874
                wbm_cti_o <= endofburst;
1875
end
1876
//async_fifo_dw_simplex_top
1877
vl_fifo_2r2w_async_simplex
1878
# ( .data_width(36), .addr_width(addr_width))
1879
fifo (
1880
    // a side
1881
    .a_d(a_d),
1882
    .a_wr(a_wr),
1883
    .a_fifo_full(a_fifo_full),
1884
    .a_q(a_q),
1885
    .a_rd(a_rd),
1886
    .a_fifo_empty(a_fifo_empty),
1887
    .a_clk(wbs_clk),
1888
    .a_rst(wbs_rst),
1889
    // b side
1890
    .b_d(b_d),
1891
    .b_wr(b_wr),
1892
    .b_fifo_full(b_fifo_full),
1893
    .b_q(b_q),
1894
    .b_rd(b_rd),
1895
    .b_fifo_empty(b_fifo_empty),
1896
    .b_clk(wbm_clk),
1897
    .b_rst(wbm_rst)
1898
    );
1899
endmodule

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