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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Blame information for rev 153

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Line No. Rev Author Line
1 60 unneback
// default SYN_KEEP definition
2 98 unneback
    // ACTEL FPGA should not use logic to handle rw collision
3 136 unneback
///////////////////////////////////////
4
// dependencies
5
///////////////////////////////////////
6 97 unneback
// size to width
7 6 unneback
//////////////////////////////////////////////////////////////////////
8
////                                                              ////
9
////  Versatile library, clock and reset                          ////
10
////                                                              ////
11
////  Description                                                 ////
12
////  Logic related to clock and reset                            ////
13
////                                                              ////
14
////                                                              ////
15
////  To Do:                                                      ////
16
////   - add more different registers                             ////
17
////                                                              ////
18
////  Author(s):                                                  ////
19
////      - Michael Unneback, unneback@opencores.org              ////
20
////        ORSoC AB                                              ////
21
////                                                              ////
22
//////////////////////////////////////////////////////////////////////
23
////                                                              ////
24
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
25
////                                                              ////
26
//// This source file may be used and distributed without         ////
27
//// restriction provided that this copyright statement is not    ////
28
//// removed from the file and that any derivative work contains  ////
29
//// the original copyright notice and the associated disclaimer. ////
30
////                                                              ////
31
//// This source file is free software; you can redistribute it   ////
32
//// and/or modify it under the terms of the GNU Lesser General   ////
33
//// Public License as published by the Free Software Foundation; ////
34
//// either version 2.1 of the License, or (at your option) any   ////
35
//// later version.                                               ////
36
////                                                              ////
37
//// This source is distributed in the hope that it will be       ////
38
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
39
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
40
//// PURPOSE.  See the GNU Lesser General Public License for more ////
41
//// details.                                                     ////
42
////                                                              ////
43
//// You should have received a copy of the GNU Lesser General    ////
44
//// Public License along with this source; if not, download it   ////
45
//// from http://www.opencores.org/lgpl.shtml                     ////
46
////                                                              ////
47
//////////////////////////////////////////////////////////////////////
48 48 unneback
`timescale 1 ns/100 ps
49 6 unneback
// Global buffer
50
// usage:
51
// use to enable global buffers for high fan out signals such as clock and reset
52
// Version: 8.4 8.4.0.33
53
module gbuf(GL,CLK);
54
output GL;
55
input  CLK;
56
    wire GND;
57
    GND GND_1_net(.Y(GND));
58
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
59
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
60
endmodule
61
`timescale 1 ns/1 ns
62
module vl_gbuf ( i, o);
63
input i;
64
output o;
65
`ifdef SIM_GBUF
66
assign o=i;
67
`else
68
gbuf gbuf_i0 ( .CLK(i), .GL(o));
69
`endif
70
endmodule
71
 //ACTEL
72
// sync reset
73 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
74 6 unneback
// output active high global reset sync with two DFFs 
75
`timescale 1 ns/100 ps
76
module vl_sync_rst ( rst_n_i, rst_o, clk);
77
input rst_n_i, clk;
78
output rst_o;
79 18 unneback
reg [1:0] tmp;
80 6 unneback
always @ (posedge clk or negedge rst_n_i)
81
if (!rst_n_i)
82 17 unneback
        tmp <= 2'b11;
83 6 unneback
else
84 33 unneback
        tmp <= {1'b0,tmp[1]};
85 17 unneback
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
86 6 unneback
endmodule
87
// vl_pll
88 32 unneback
///////////////////////////////////////////////////////////////////////////////
89 17 unneback
`timescale 1 ps/1 ps
90 6 unneback
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
91
parameter index = 0;
92
parameter number_of_clk = 1;
93 17 unneback
parameter period_time_0 = 20000;
94
parameter period_time_1 = 20000;
95
parameter period_time_2 = 20000;
96
parameter lock_delay = 2000000;
97 6 unneback
input clk_i, rst_n_i;
98
output lock;
99
output reg [0:number_of_clk-1] clk_o;
100
output [0:number_of_clk-1] rst_o;
101
`ifdef SIM_PLL
102
always
103
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
104
generate if (number_of_clk > 1)
105
always
106
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
107
endgenerate
108
generate if (number_of_clk > 2)
109
always
110
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
111
endgenerate
112
genvar i;
113
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
114
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
115
end
116
endgenerate
117
assign #lock_delay lock = rst_n_i;
118
endmodule
119
`else
120
generate if (number_of_clk==1 & index==0) begin
121
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
122
end
123
endgenerate // index==0
124
generate if (number_of_clk==1 & index==1) begin
125
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
126
end
127
endgenerate // index==1
128
generate if (number_of_clk==1 & index==2) begin
129
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
130
end
131
endgenerate // index==2
132
generate if (number_of_clk==1 & index==3) begin
133
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
134
end
135
endgenerate // index==0
136
generate if (number_of_clk==2 & index==0) begin
137
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
138
end
139
endgenerate // index==0
140
generate if (number_of_clk==2 & index==1) begin
141
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
142
end
143
endgenerate // index==1
144
generate if (number_of_clk==2 & index==2) begin
145
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
146
end
147
endgenerate // index==2
148
generate if (number_of_clk==2 & index==3) begin
149
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
150
end
151
endgenerate // index==0
152
generate if (number_of_clk==3 & index==0) begin
153
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
154
end
155
endgenerate // index==0
156
generate if (number_of_clk==3 & index==1) begin
157
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
158
end
159
endgenerate // index==1
160
generate if (number_of_clk==3 & index==2) begin
161
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
162
end
163
endgenerate // index==2
164
generate if (number_of_clk==3 & index==3) begin
165
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
166
end
167
endgenerate // index==0
168
genvar i;
169
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
170 40 unneback
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
171 6 unneback
end
172
endgenerate
173
endmodule
174
`endif
175 32 unneback
///////////////////////////////////////////////////////////////////////////////
176 6 unneback
 //actel
177
//////////////////////////////////////////////////////////////////////
178
////                                                              ////
179
////  Versatile library, registers                                ////
180
////                                                              ////
181
////  Description                                                 ////
182
////  Different type of registers                                 ////
183
////                                                              ////
184
////                                                              ////
185
////  To Do:                                                      ////
186
////   - add more different registers                             ////
187
////                                                              ////
188
////  Author(s):                                                  ////
189
////      - Michael Unneback, unneback@opencores.org              ////
190
////        ORSoC AB                                              ////
191
////                                                              ////
192
//////////////////////////////////////////////////////////////////////
193
////                                                              ////
194
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
195
////                                                              ////
196
//// This source file may be used and distributed without         ////
197
//// restriction provided that this copyright statement is not    ////
198
//// removed from the file and that any derivative work contains  ////
199
//// the original copyright notice and the associated disclaimer. ////
200
////                                                              ////
201
//// This source file is free software; you can redistribute it   ////
202
//// and/or modify it under the terms of the GNU Lesser General   ////
203
//// Public License as published by the Free Software Foundation; ////
204
//// either version 2.1 of the License, or (at your option) any   ////
205
//// later version.                                               ////
206
////                                                              ////
207
//// This source is distributed in the hope that it will be       ////
208
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
209
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
210
//// PURPOSE.  See the GNU Lesser General Public License for more ////
211
//// details.                                                     ////
212
////                                                              ////
213
//// You should have received a copy of the GNU Lesser General    ////
214
//// Public License along with this source; if not, download it   ////
215
//// from http://www.opencores.org/lgpl.shtml                     ////
216
////                                                              ////
217
//////////////////////////////////////////////////////////////////////
218 18 unneback
module vl_dff ( d, q, clk, rst);
219 6 unneback
        parameter width = 1;
220 139 unneback
        parameter reset_value = {width{1'b0}};
221 6 unneback
        input [width-1:0] d;
222
        input clk, rst;
223
        output reg [width-1:0] q;
224
        always @ (posedge clk or posedge rst)
225
        if (rst)
226
                q <= reset_value;
227
        else
228
                q <= d;
229
endmodule
230 18 unneback
module vl_dff_array ( d, q, clk, rst);
231 6 unneback
        parameter width = 1;
232
        parameter depth = 2;
233
        parameter reset_value = 1'b0;
234
        input [width-1:0] d;
235
        input clk, rst;
236
        output [width-1:0] q;
237
        reg  [0:depth-1] q_tmp [width-1:0];
238
        integer i;
239
        always @ (posedge clk or posedge rst)
240
        if (rst) begin
241
            for (i=0;i<depth;i=i+1)
242
                q_tmp[i] <= {width{reset_value}};
243
        end else begin
244
            q_tmp[0] <= d;
245
            for (i=1;i<depth;i=i+1)
246
                q_tmp[i] <= q_tmp[i-1];
247
        end
248
    assign q = q_tmp[depth-1];
249
endmodule
250 18 unneback
module vl_dff_ce ( d, ce, q, clk, rst);
251 6 unneback
        parameter width = 1;
252 139 unneback
        parameter reset_value = {width{1'b0}};
253 6 unneback
        input [width-1:0] d;
254
        input ce, clk, rst;
255
        output reg [width-1:0] q;
256
        always @ (posedge clk or posedge rst)
257
        if (rst)
258
                q <= reset_value;
259
        else
260
                if (ce)
261
                        q <= d;
262
endmodule
263 18 unneback
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
264 8 unneback
        parameter width = 1;
265 139 unneback
        parameter reset_value = {width{1'b0}};
266 8 unneback
        input [width-1:0] d;
267 10 unneback
        input ce, clear, clk, rst;
268 8 unneback
        output reg [width-1:0] q;
269
        always @ (posedge clk or posedge rst)
270
        if (rst)
271
            q <= reset_value;
272
        else
273
            if (ce)
274
                if (clear)
275
                    q <= {width{1'b0}};
276
                else
277
                    q <= d;
278
endmodule
279 24 unneback
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
280
        parameter width = 1;
281 139 unneback
        parameter reset_value = {width{1'b0}};
282 24 unneback
        input [width-1:0] d;
283
        input ce, set, clk, rst;
284
        output reg [width-1:0] q;
285
        always @ (posedge clk or posedge rst)
286
        if (rst)
287
            q <= reset_value;
288
        else
289
            if (ce)
290
                if (set)
291
                    q <= {width{1'b1}};
292
                else
293
                    q <= d;
294
endmodule
295 29 unneback
module vl_spr ( sp, r, q, clk, rst);
296 64 unneback
        //parameter width = 1;
297
        parameter reset_value = 1'b0;
298 29 unneback
        input sp, r;
299
        output reg q;
300
        input clk, rst;
301
        always @ (posedge clk or posedge rst)
302
        if (rst)
303
            q <= reset_value;
304
        else
305
            if (sp)
306
                q <= 1'b1;
307
            else if (r)
308
                q <= 1'b0;
309
endmodule
310
module vl_srp ( s, rp, q, clk, rst);
311
        parameter width = 1;
312
        parameter reset_value = 0;
313
        input s, rp;
314
        output reg q;
315
        input clk, rst;
316
        always @ (posedge clk or posedge rst)
317
        if (rst)
318
            q <= reset_value;
319
        else
320
            if (rp)
321
                q <= 1'b0;
322
            else if (s)
323
                q <= 1'b1;
324
endmodule
325 18 unneback
module vl_dff_sr ( aclr, aset, clock, data, q);
326 6 unneback
    input         aclr;
327
    input         aset;
328
    input         clock;
329
    input         data;
330
    output reg    q;
331
   always @ (posedge clock or posedge aclr or posedge aset)
332
     if (aclr)
333
       q <= 1'b0;
334
     else if (aset)
335
       q <= 1'b1;
336
     else
337
       q <= data;
338
endmodule
339
// LATCH
340
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
341 40 unneback
module vl_latch ( d, le, q, clk);
342 6 unneback
input d, le;
343 48 unneback
input clk;
344
always @ (le or d)
345 60 unneback
if (le)
346 48 unneback
    d <= q;
347 6 unneback
endmodule
348 18 unneback
module vl_shreg ( d, q, clk, rst);
349 17 unneback
parameter depth = 10;
350
input d;
351
output q;
352
input clk, rst;
353
reg [1:depth] dffs;
354
always @ (posedge clk or posedge rst)
355
if (rst)
356
    dffs <= {depth{1'b0}};
357
else
358
    dffs <= {d,dffs[1:depth-1]};
359
assign q = dffs[depth];
360
endmodule
361 18 unneback
module vl_shreg_ce ( d, ce, q, clk, rst);
362 17 unneback
parameter depth = 10;
363
input d, ce;
364
output q;
365
input clk, rst;
366
reg [1:depth] dffs;
367
always @ (posedge clk or posedge rst)
368
if (rst)
369
    dffs <= {depth{1'b0}};
370
else
371
    if (ce)
372
        dffs <= {d,dffs[1:depth-1]};
373
assign q = dffs[depth];
374
endmodule
375 18 unneback
module vl_delay ( d, q, clk, rst);
376 15 unneback
parameter depth = 10;
377
input d;
378
output q;
379
input clk, rst;
380
reg [1:depth] dffs;
381
always @ (posedge clk or posedge rst)
382
if (rst)
383
    dffs <= {depth{1'b0}};
384
else
385
    dffs <= {d,dffs[1:depth-1]};
386
assign q = dffs[depth];
387
endmodule
388 18 unneback
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
389 17 unneback
parameter depth = 10;
390
input d;
391
output q, emptyflag;
392
input clk, rst;
393
reg [1:depth] dffs;
394
always @ (posedge clk or posedge rst)
395
if (rst)
396
    dffs <= {depth{1'b0}};
397
else
398
    dffs <= {d,dffs[1:depth-1]};
399
assign q = dffs[depth];
400
assign emptyflag = !(|dffs);
401
endmodule
402 98 unneback
module vl_pulse2toggle ( pl, q, clk, rst);
403 94 unneback
input pl;
404 98 unneback
output reg q;
405 94 unneback
input clk, rst;
406
always @ (posedge clk or posedge rst)
407
if (rst)
408
    q <= 1'b0;
409
else
410
    q <= pl ^ q;
411
endmodule
412 98 unneback
module vl_toggle2pulse (d, pl, clk, rst);
413 94 unneback
input d;
414
output pl;
415
input clk, rst;
416
reg dff;
417
always @ (posedge clk or posedge rst)
418
if (rst)
419
    dff <= 1'b0;
420
else
421
    dff <= d;
422 98 unneback
assign pl = d ^ dff;
423 94 unneback
endmodule
424
module vl_synchronizer (d, q, clk, rst);
425
input d;
426
output reg q;
427 116 unneback
input clk, rst;
428 94 unneback
reg dff;
429
always @ (posedge clk or posedge rst)
430
if (rst)
431 100 unneback
    {q,dff} <= 2'b00;
432 94 unneback
else
433 100 unneback
    {q,dff} <= {dff,d};
434 94 unneback
endmodule
435 97 unneback
module vl_cdc ( start_pl, take_it_pl, take_it_grant_pl, got_it_pl, clk_src, rst_src, clk_dst, rst_dst);
436 94 unneback
input start_pl;
437
output take_it_pl;
438
input take_it_grant_pl; // note: connect to take_it_pl to generate automatic ack
439
output got_it_pl;
440
input clk_src, rst_src;
441
input clk_dst, rst_dst;
442
wire take_it_tg, take_it_tg_sync;
443
wire got_it_tg, got_it_tg_sync;
444
// src -> dst
445
vl_pulse2toggle p2t0 (
446
    .pl(start_pl),
447
    .q(take_it_tg),
448
    .clk(clk_src),
449
    .rst(rst_src));
450
vl_synchronizer sync0 (
451
    .d(take_it_tg),
452
    .q(take_it_tg_sync),
453
    .clk(clk_dst),
454
    .rst(rst_dst));
455
vl_toggle2pulse t2p0 (
456 100 unneback
    .d(take_it_tg_sync),
457 94 unneback
    .pl(take_it_pl),
458
    .clk(clk_dst),
459
    .rst(rst_dst));
460
// dst -> src
461 98 unneback
vl_pulse2toggle p2t1 (
462 94 unneback
    .pl(take_it_grant_pl),
463
    .q(got_it_tg),
464
    .clk(clk_dst),
465
    .rst(rst_dst));
466
vl_synchronizer sync1 (
467
    .d(got_it_tg),
468
    .q(got_it_tg_sync),
469
    .clk(clk_src),
470
    .rst(rst_src));
471
vl_toggle2pulse t2p1 (
472 100 unneback
    .d(got_it_tg_sync),
473 94 unneback
    .pl(got_it_pl),
474
    .clk(clk_src),
475
    .rst(rst_src));
476
endmodule
477 6 unneback
//////////////////////////////////////////////////////////////////////
478
////                                                              ////
479 18 unneback
////  Logic functions                                             ////
480
////                                                              ////
481
////  Description                                                 ////
482
////  Logic functions such as multiplexers                        ////
483
////                                                              ////
484
////                                                              ////
485
////  To Do:                                                      ////
486
////   -                                                          ////
487
////                                                              ////
488
////  Author(s):                                                  ////
489
////      - Michael Unneback, unneback@opencores.org              ////
490
////        ORSoC AB                                              ////
491
////                                                              ////
492
//////////////////////////////////////////////////////////////////////
493
////                                                              ////
494
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
495
////                                                              ////
496
//// This source file may be used and distributed without         ////
497
//// restriction provided that this copyright statement is not    ////
498
//// removed from the file and that any derivative work contains  ////
499
//// the original copyright notice and the associated disclaimer. ////
500
////                                                              ////
501
//// This source file is free software; you can redistribute it   ////
502
//// and/or modify it under the terms of the GNU Lesser General   ////
503
//// Public License as published by the Free Software Foundation; ////
504
//// either version 2.1 of the License, or (at your option) any   ////
505
//// later version.                                               ////
506
////                                                              ////
507
//// This source is distributed in the hope that it will be       ////
508
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
509
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
510
//// PURPOSE.  See the GNU Lesser General Public License for more ////
511
//// details.                                                     ////
512
////                                                              ////
513
//// You should have received a copy of the GNU Lesser General    ////
514
//// Public License along with this source; if not, download it   ////
515
//// from http://www.opencores.org/lgpl.shtml                     ////
516
////                                                              ////
517
//////////////////////////////////////////////////////////////////////
518 36 unneback
module vl_mux_andor ( a, sel, dout);
519
parameter width = 32;
520
parameter nr_of_ports = 4;
521
input [nr_of_ports*width-1:0] a;
522
input [nr_of_ports-1:0] sel;
523
output reg [width-1:0] dout;
524 38 unneback
integer i,j;
525 36 unneback
always @ (a, sel)
526
begin
527
    dout = a[width-1:0] & {width{sel[0]}};
528 42 unneback
    for (i=1;i<nr_of_ports;i=i+1)
529
        for (j=0;j<width;j=j+1)
530
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
531 36 unneback
end
532
endmodule
533 34 unneback
module vl_mux2_andor ( a1, a0, sel, dout);
534
parameter width = 32;
535 35 unneback
localparam nr_of_ports = 2;
536 34 unneback
input [width-1:0] a1, a0;
537
input [nr_of_ports-1:0] sel;
538
output [width-1:0] dout;
539 36 unneback
vl_mux_andor
540 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
541 36 unneback
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
542 34 unneback
endmodule
543
module vl_mux3_andor ( a2, a1, a0, sel, dout);
544
parameter width = 32;
545 35 unneback
localparam nr_of_ports = 3;
546 34 unneback
input [width-1:0] a2, a1, a0;
547
input [nr_of_ports-1:0] sel;
548
output [width-1:0] dout;
549 36 unneback
vl_mux_andor
550 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
551 36 unneback
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
552 34 unneback
endmodule
553 18 unneback
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
554
parameter width = 32;
555 35 unneback
localparam nr_of_ports = 4;
556 18 unneback
input [width-1:0] a3, a2, a1, a0;
557
input [nr_of_ports-1:0] sel;
558 22 unneback
output [width-1:0] dout;
559 36 unneback
vl_mux_andor
560 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
561 36 unneback
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
562 18 unneback
endmodule
563
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
564
parameter width = 32;
565 35 unneback
localparam nr_of_ports = 5;
566 18 unneback
input [width-1:0] a4, a3, a2, a1, a0;
567
input [nr_of_ports-1:0] sel;
568 22 unneback
output [width-1:0] dout;
569 36 unneback
vl_mux_andor
570 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
571 36 unneback
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
572 18 unneback
endmodule
573
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
574
parameter width = 32;
575 35 unneback
localparam nr_of_ports = 6;
576 18 unneback
input [width-1:0] a5, a4, a3, a2, a1, a0;
577
input [nr_of_ports-1:0] sel;
578 22 unneback
output [width-1:0] dout;
579 36 unneback
vl_mux_andor
580 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
581 36 unneback
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
582 18 unneback
endmodule
583 43 unneback
module vl_parity_generate (data, parity);
584
parameter word_size = 32;
585
parameter chunk_size = 8;
586
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
587
input [word_size-1:0] data;
588
output reg [word_size/chunk_size-1:0] parity;
589
integer i,j;
590
always @ (data)
591
for (i=0;i<word_size/chunk_size;i=i+1) begin
592
    parity[i] = parity_type;
593
    for (j=0;j<chunk_size;j=j+1) begin
594 46 unneback
        parity[i] = data[i*chunk_size+j] ^ parity[i];
595 43 unneback
    end
596
end
597
endmodule
598
module vl_parity_check( data, parity, parity_error);
599
parameter word_size = 32;
600
parameter chunk_size = 8;
601
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
602
input [word_size-1:0] data;
603
input [word_size/chunk_size-1:0] parity;
604
output parity_error;
605 44 unneback
reg [word_size/chunk_size-1:0] error_flag;
606 43 unneback
integer i,j;
607
always @ (data or parity)
608
for (i=0;i<word_size/chunk_size;i=i+1) begin
609
    error_flag[i] = parity[i] ^ parity_type;
610
    for (j=0;j<chunk_size;j=j+1) begin
611 46 unneback
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
612 43 unneback
    end
613
end
614
assign parity_error = |error_flag;
615
endmodule
616 18 unneback
//////////////////////////////////////////////////////////////////////
617
////                                                              ////
618 44 unneback
////  IO functions                                                ////
619
////                                                              ////
620
////  Description                                                 ////
621
////  IO functions such as IOB flip-flops                         ////
622
////                                                              ////
623
////                                                              ////
624
////  To Do:                                                      ////
625
////   -                                                          ////
626
////                                                              ////
627
////  Author(s):                                                  ////
628
////      - Michael Unneback, unneback@opencores.org              ////
629
////        ORSoC AB                                              ////
630
////                                                              ////
631
//////////////////////////////////////////////////////////////////////
632
////                                                              ////
633
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
634
////                                                              ////
635
//// This source file may be used and distributed without         ////
636
//// restriction provided that this copyright statement is not    ////
637
//// removed from the file and that any derivative work contains  ////
638
//// the original copyright notice and the associated disclaimer. ////
639
////                                                              ////
640
//// This source file is free software; you can redistribute it   ////
641
//// and/or modify it under the terms of the GNU Lesser General   ////
642
//// Public License as published by the Free Software Foundation; ////
643
//// either version 2.1 of the License, or (at your option) any   ////
644
//// later version.                                               ////
645
////                                                              ////
646
//// This source is distributed in the hope that it will be       ////
647
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
648
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
649
//// PURPOSE.  See the GNU Lesser General Public License for more ////
650
//// details.                                                     ////
651
////                                                              ////
652
//// You should have received a copy of the GNU Lesser General    ////
653
//// Public License along with this source; if not, download it   ////
654
//// from http://www.opencores.org/lgpl.shtml                     ////
655
////                                                              ////
656
//////////////////////////////////////////////////////////////////////
657 45 unneback
`timescale 1ns/1ns
658 44 unneback
module vl_o_dff (d_i, o_pad, clk, rst);
659
parameter width = 1;
660 45 unneback
parameter reset_value = {width{1'b0}};
661
input  [width-1:0]  d_i;
662 44 unneback
output [width-1:0] o_pad;
663
input clk, rst;
664
wire [width-1:0] d_i_int /*synthesis syn_keep = 1*/;
665 45 unneback
reg  [width-1:0] o_pad_int;
666 44 unneback
assign d_i_int = d_i;
667
genvar i;
668 45 unneback
generate
669 136 unneback
for (i=0;i<width;i=i+1) begin : dffs
670 44 unneback
    always @ (posedge clk or posedge rst)
671
    if (rst)
672 45 unneback
        o_pad_int[i] <= reset_value[i];
673 44 unneback
    else
674 45 unneback
        o_pad_int[i] <= d_i_int[i];
675
    assign #1 o_pad[i] = o_pad_int[i];
676 44 unneback
end
677
endgenerate
678
endmodule
679 45 unneback
`timescale 1ns/1ns
680 44 unneback
module vl_io_dff_oe ( d_i, d_o, oe, io_pad, clk, rst);
681
parameter width = 1;
682 140 unneback
parameter reset_value = 1'b0;
683 44 unneback
input  [width-1:0] d_o;
684
output reg [width-1:0] d_i;
685
input oe;
686
inout [width-1:0] io_pad;
687
input clk, rst;
688
wire [width-1:0] oe_d /*synthesis syn_keep = 1*/;
689
reg [width-1:0] oe_q;
690
reg [width-1:0] d_o_q;
691
assign oe_d = {width{oe}};
692
genvar i;
693
generate
694 136 unneback
for (i=0;i<width;i=i+1) begin : dffs
695 44 unneback
    always @ (posedge clk or posedge rst)
696
    if (rst)
697
        oe_q[i] <= 1'b0;
698
    else
699
        oe_q[i] <= oe_d[i];
700
    always @ (posedge clk or posedge rst)
701
    if (rst)
702 140 unneback
        d_o_q[i] <= reset_value;
703 44 unneback
    else
704
        d_o_q[i] <= d_o[i];
705
    always @ (posedge clk or posedge rst)
706
    if (rst)
707 140 unneback
        d_i[i] <= reset_value;
708 44 unneback
    else
709
        d_i[i] <= io_pad[i];
710 45 unneback
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
711 44 unneback
end
712
endgenerate
713
endmodule
714 136 unneback
module vl_o_ddr (d_h_i, d_l_i, o_pad, clk, rst);
715
parameter width = 1;
716
input  [width-1:0] d_h_i, d_l_i;
717
output [width-1:0] o_pad;
718
input clk, rst;
719
reg [width-1:0] ff1;
720
reg [width-1:0] ff2;
721
genvar i;
722
generate
723
for (i=0;i<width;i=i+1) begin : ddr
724
    always @ (posedge clk or posedge rst)
725
    if (rst)
726
        ff1[i] <= 1'b0;
727
    else
728
        ff1[i] <= d_h_i[i];
729
    always @ (posedge clk or posedge rst)
730
    if (rst)
731
        ff2[i] <= 1'b0;
732
    else
733
        ff2[i] <= d_l_i[i];
734
    assign o_pad = (clk) ? ff1 : ff2;
735
end
736
endgenerate
737
endmodule
738
module vl_o_clk ( clk_o_pad, clk, rst);
739
input clk, rst;
740
output clk_o_pad;
741
vl_o_ddr o_ddr0( .d_h_i(1'b1), .d_l_i(1'b0), .o_pad(clk_o_pad), .clk(clk), .rst(rst));
742
endmodule
743 44 unneback
//////////////////////////////////////////////////////////////////////
744
////                                                              ////
745 6 unneback
////  Versatile counter                                           ////
746
////                                                              ////
747
////  Description                                                 ////
748
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
749
////  counter                                                     ////
750
////                                                              ////
751
////  To Do:                                                      ////
752
////   - add LFSR with more taps                                  ////
753
////                                                              ////
754
////  Author(s):                                                  ////
755
////      - Michael Unneback, unneback@opencores.org              ////
756
////        ORSoC AB                                              ////
757
////                                                              ////
758
//////////////////////////////////////////////////////////////////////
759
////                                                              ////
760
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
761
////                                                              ////
762
//// This source file may be used and distributed without         ////
763
//// restriction provided that this copyright statement is not    ////
764
//// removed from the file and that any derivative work contains  ////
765
//// the original copyright notice and the associated disclaimer. ////
766
////                                                              ////
767
//// This source file is free software; you can redistribute it   ////
768
//// and/or modify it under the terms of the GNU Lesser General   ////
769
//// Public License as published by the Free Software Foundation; ////
770
//// either version 2.1 of the License, or (at your option) any   ////
771
//// later version.                                               ////
772
////                                                              ////
773
//// This source is distributed in the hope that it will be       ////
774
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
775
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
776
//// PURPOSE.  See the GNU Lesser General Public License for more ////
777
//// details.                                                     ////
778
////                                                              ////
779
//// You should have received a copy of the GNU Lesser General    ////
780
//// Public License along with this source; if not, download it   ////
781
//// from http://www.opencores.org/lgpl.shtml                     ////
782
////                                                              ////
783
//////////////////////////////////////////////////////////////////////
784
// binary counter
785 139 unneback
module vl_cnt_bin (
786
 q, rst, clk);
787
   parameter length = 4;
788
   output [length:1] q;
789
   input rst;
790
   input clk;
791
   parameter clear_value = 0;
792
   parameter set_value = 1;
793
   parameter wrap_value = 0;
794
   parameter level1_value = 15;
795
   reg  [length:1] qi;
796
   wire [length:1] q_next;
797
   assign q_next = qi + {{length-1{1'b0}},1'b1};
798
   always @ (posedge clk or posedge rst)
799
     if (rst)
800
       qi <= {length{1'b0}};
801
     else
802
       qi <= q_next;
803
   assign q = qi;
804
endmodule
805
//////////////////////////////////////////////////////////////////////
806
////                                                              ////
807
////  Versatile counter                                           ////
808
////                                                              ////
809
////  Description                                                 ////
810
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
811
////  counter                                                     ////
812
////                                                              ////
813
////  To Do:                                                      ////
814
////   - add LFSR with more taps                                  ////
815
////                                                              ////
816
////  Author(s):                                                  ////
817
////      - Michael Unneback, unneback@opencores.org              ////
818
////        ORSoC AB                                              ////
819
////                                                              ////
820
//////////////////////////////////////////////////////////////////////
821
////                                                              ////
822
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
823
////                                                              ////
824
//// This source file may be used and distributed without         ////
825
//// restriction provided that this copyright statement is not    ////
826
//// removed from the file and that any derivative work contains  ////
827
//// the original copyright notice and the associated disclaimer. ////
828
////                                                              ////
829
//// This source file is free software; you can redistribute it   ////
830
//// and/or modify it under the terms of the GNU Lesser General   ////
831
//// Public License as published by the Free Software Foundation; ////
832
//// either version 2.1 of the License, or (at your option) any   ////
833
//// later version.                                               ////
834
////                                                              ////
835
//// This source is distributed in the hope that it will be       ////
836
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
837
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
838
//// PURPOSE.  See the GNU Lesser General Public License for more ////
839
//// details.                                                     ////
840
////                                                              ////
841
//// You should have received a copy of the GNU Lesser General    ////
842
//// Public License along with this source; if not, download it   ////
843
//// from http://www.opencores.org/lgpl.shtml                     ////
844
////                                                              ////
845
//////////////////////////////////////////////////////////////////////
846
// binary counter
847
module vl_cnt_bin_clear (
848
 clear, q, rst, clk);
849
   parameter length = 4;
850
   input clear;
851
   output [length:1] q;
852
   input rst;
853
   input clk;
854
   parameter clear_value = 0;
855
   parameter set_value = 1;
856
   parameter wrap_value = 0;
857
   parameter level1_value = 15;
858
   reg  [length:1] qi;
859
   wire [length:1] q_next;
860
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
861
   always @ (posedge clk or posedge rst)
862
     if (rst)
863
       qi <= {length{1'b0}};
864
     else
865
       qi <= q_next;
866
   assign q = qi;
867
endmodule
868
//////////////////////////////////////////////////////////////////////
869
////                                                              ////
870
////  Versatile counter                                           ////
871
////                                                              ////
872
////  Description                                                 ////
873
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
874
////  counter                                                     ////
875
////                                                              ////
876
////  To Do:                                                      ////
877
////   - add LFSR with more taps                                  ////
878
////                                                              ////
879
////  Author(s):                                                  ////
880
////      - Michael Unneback, unneback@opencores.org              ////
881
////        ORSoC AB                                              ////
882
////                                                              ////
883
//////////////////////////////////////////////////////////////////////
884
////                                                              ////
885
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
886
////                                                              ////
887
//// This source file may be used and distributed without         ////
888
//// restriction provided that this copyright statement is not    ////
889
//// removed from the file and that any derivative work contains  ////
890
//// the original copyright notice and the associated disclaimer. ////
891
////                                                              ////
892
//// This source file is free software; you can redistribute it   ////
893
//// and/or modify it under the terms of the GNU Lesser General   ////
894
//// Public License as published by the Free Software Foundation; ////
895
//// either version 2.1 of the License, or (at your option) any   ////
896
//// later version.                                               ////
897
////                                                              ////
898
//// This source is distributed in the hope that it will be       ////
899
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
900
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
901
//// PURPOSE.  See the GNU Lesser General Public License for more ////
902
//// details.                                                     ////
903
////                                                              ////
904
//// You should have received a copy of the GNU Lesser General    ////
905
//// Public License along with this source; if not, download it   ////
906
//// from http://www.opencores.org/lgpl.shtml                     ////
907
////                                                              ////
908
//////////////////////////////////////////////////////////////////////
909
// binary counter
910 40 unneback
module vl_cnt_bin_ce (
911
 cke, q, rst, clk);
912 22 unneback
   parameter length = 4;
913 6 unneback
   input cke;
914
   output [length:1] q;
915
   input rst;
916
   input clk;
917
   parameter clear_value = 0;
918
   parameter set_value = 1;
919
   parameter wrap_value = 0;
920
   parameter level1_value = 15;
921
   reg  [length:1] qi;
922
   wire [length:1] q_next;
923
   assign q_next = qi + {{length-1{1'b0}},1'b1};
924
   always @ (posedge clk or posedge rst)
925
     if (rst)
926
       qi <= {length{1'b0}};
927
     else
928
     if (cke)
929
       qi <= q_next;
930
   assign q = qi;
931
endmodule
932
//////////////////////////////////////////////////////////////////////
933
////                                                              ////
934
////  Versatile counter                                           ////
935
////                                                              ////
936
////  Description                                                 ////
937
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
938
////  counter                                                     ////
939
////                                                              ////
940
////  To Do:                                                      ////
941
////   - add LFSR with more taps                                  ////
942
////                                                              ////
943
////  Author(s):                                                  ////
944
////      - Michael Unneback, unneback@opencores.org              ////
945
////        ORSoC AB                                              ////
946
////                                                              ////
947
//////////////////////////////////////////////////////////////////////
948
////                                                              ////
949
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
950
////                                                              ////
951
//// This source file may be used and distributed without         ////
952
//// restriction provided that this copyright statement is not    ////
953
//// removed from the file and that any derivative work contains  ////
954
//// the original copyright notice and the associated disclaimer. ////
955
////                                                              ////
956
//// This source file is free software; you can redistribute it   ////
957
//// and/or modify it under the terms of the GNU Lesser General   ////
958
//// Public License as published by the Free Software Foundation; ////
959
//// either version 2.1 of the License, or (at your option) any   ////
960
//// later version.                                               ////
961
////                                                              ////
962
//// This source is distributed in the hope that it will be       ////
963
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
964
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
965
//// PURPOSE.  See the GNU Lesser General Public License for more ////
966
//// details.                                                     ////
967
////                                                              ////
968
//// You should have received a copy of the GNU Lesser General    ////
969
//// Public License along with this source; if not, download it   ////
970
//// from http://www.opencores.org/lgpl.shtml                     ////
971
////                                                              ////
972
//////////////////////////////////////////////////////////////////////
973
// binary counter
974 139 unneback
module vl_cnt_bin_ce_clear (
975
 clear, cke, q, rst, clk);
976
   parameter length = 4;
977
   input clear;
978
   input cke;
979
   output [length:1] q;
980
   input rst;
981
   input clk;
982
   parameter clear_value = 0;
983
   parameter set_value = 1;
984
   parameter wrap_value = 0;
985
   parameter level1_value = 15;
986
   reg  [length:1] qi;
987
   wire [length:1] q_next;
988
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
989
   always @ (posedge clk or posedge rst)
990
     if (rst)
991
       qi <= {length{1'b0}};
992
     else
993
     if (cke)
994
       qi <= q_next;
995
   assign q = qi;
996
endmodule
997
//////////////////////////////////////////////////////////////////////
998
////                                                              ////
999
////  Versatile counter                                           ////
1000
////                                                              ////
1001
////  Description                                                 ////
1002
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1003
////  counter                                                     ////
1004
////                                                              ////
1005
////  To Do:                                                      ////
1006
////   - add LFSR with more taps                                  ////
1007
////                                                              ////
1008
////  Author(s):                                                  ////
1009
////      - Michael Unneback, unneback@opencores.org              ////
1010
////        ORSoC AB                                              ////
1011
////                                                              ////
1012
//////////////////////////////////////////////////////////////////////
1013
////                                                              ////
1014
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1015
////                                                              ////
1016
//// This source file may be used and distributed without         ////
1017
//// restriction provided that this copyright statement is not    ////
1018
//// removed from the file and that any derivative work contains  ////
1019
//// the original copyright notice and the associated disclaimer. ////
1020
////                                                              ////
1021
//// This source file is free software; you can redistribute it   ////
1022
//// and/or modify it under the terms of the GNU Lesser General   ////
1023
//// Public License as published by the Free Software Foundation; ////
1024
//// either version 2.1 of the License, or (at your option) any   ////
1025
//// later version.                                               ////
1026
////                                                              ////
1027
//// This source is distributed in the hope that it will be       ////
1028
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1029
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1030
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1031
//// details.                                                     ////
1032
////                                                              ////
1033
//// You should have received a copy of the GNU Lesser General    ////
1034
//// Public License along with this source; if not, download it   ////
1035
//// from http://www.opencores.org/lgpl.shtml                     ////
1036
////                                                              ////
1037
//////////////////////////////////////////////////////////////////////
1038
// binary counter
1039
module vl_cnt_bin_ce_clear_l1_l2 (
1040
 clear, cke, q, level1, level2, rst, clk);
1041
   parameter length = 4;
1042
   input clear;
1043
   input cke;
1044
   output [length:1] q;
1045
   output reg level1;
1046
   output reg level2;
1047
   input rst;
1048
   input clk;
1049
   parameter clear_value = 0;
1050
   parameter set_value = 1;
1051
   parameter wrap_value = 15;
1052
   parameter level1_value = 8;
1053
   parameter level2_value = 15;
1054
   wire rew;
1055
   assign rew = 1'b0;
1056
   reg  [length:1] qi;
1057
   wire [length:1] q_next;
1058
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1059
   always @ (posedge clk or posedge rst)
1060
     if (rst)
1061
       qi <= {length{1'b0}};
1062
     else
1063
     if (cke)
1064
       qi <= q_next;
1065
   assign q = qi;
1066
    always @ (posedge clk or posedge rst)
1067
    if (rst)
1068
        level1 <= 1'b0;
1069
    else
1070
    if (cke)
1071
    if (clear)
1072
        level1 <= 1'b0;
1073
    else if (q_next == level1_value)
1074
        level1 <= 1'b1;
1075
    else if (qi == level1_value & rew)
1076
        level1 <= 1'b0;
1077
    always @ (posedge clk or posedge rst)
1078
    if (rst)
1079
        level2 <= 1'b0;
1080
    else
1081
    if (cke)
1082
    if (clear)
1083
        level2 <= 1'b0;
1084
    else if (q_next == level2_value)
1085
        level2 <= 1'b1;
1086
    else if (qi == level2_value & rew)
1087
        level2 <= 1'b0;
1088
endmodule
1089
//////////////////////////////////////////////////////////////////////
1090
////                                                              ////
1091
////  Versatile counter                                           ////
1092
////                                                              ////
1093
////  Description                                                 ////
1094
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1095
////  counter                                                     ////
1096
////                                                              ////
1097
////  To Do:                                                      ////
1098
////   - add LFSR with more taps                                  ////
1099
////                                                              ////
1100
////  Author(s):                                                  ////
1101
////      - Michael Unneback, unneback@opencores.org              ////
1102
////        ORSoC AB                                              ////
1103
////                                                              ////
1104
//////////////////////////////////////////////////////////////////////
1105
////                                                              ////
1106
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1107
////                                                              ////
1108
//// This source file may be used and distributed without         ////
1109
//// restriction provided that this copyright statement is not    ////
1110
//// removed from the file and that any derivative work contains  ////
1111
//// the original copyright notice and the associated disclaimer. ////
1112
////                                                              ////
1113
//// This source file is free software; you can redistribute it   ////
1114
//// and/or modify it under the terms of the GNU Lesser General   ////
1115
//// Public License as published by the Free Software Foundation; ////
1116
//// either version 2.1 of the License, or (at your option) any   ////
1117
//// later version.                                               ////
1118
////                                                              ////
1119
//// This source is distributed in the hope that it will be       ////
1120
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1121
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1122
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1123
//// details.                                                     ////
1124
////                                                              ////
1125
//// You should have received a copy of the GNU Lesser General    ////
1126
//// Public License along with this source; if not, download it   ////
1127
//// from http://www.opencores.org/lgpl.shtml                     ////
1128
////                                                              ////
1129
//////////////////////////////////////////////////////////////////////
1130
// binary counter
1131
module vl_cnt_bin_ce_clear_set_rew (
1132
 clear, set, cke, rew, q, rst, clk);
1133
   parameter length = 4;
1134
   input clear;
1135
   input set;
1136
   input cke;
1137
   input rew;
1138
   output [length:1] q;
1139
   input rst;
1140
   input clk;
1141
   parameter clear_value = 0;
1142
   parameter set_value = 1;
1143
   parameter wrap_value = 0;
1144
   parameter level1_value = 15;
1145
   reg  [length:1] qi;
1146
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1147
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
1148
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
1149
   assign q_next = rew ? q_next_rew : q_next_fw;
1150
   always @ (posedge clk or posedge rst)
1151
     if (rst)
1152
       qi <= {length{1'b0}};
1153
     else
1154
     if (cke)
1155
       qi <= q_next;
1156
   assign q = qi;
1157
endmodule
1158
//////////////////////////////////////////////////////////////////////
1159
////                                                              ////
1160
////  Versatile counter                                           ////
1161
////                                                              ////
1162
////  Description                                                 ////
1163
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1164
////  counter                                                     ////
1165
////                                                              ////
1166
////  To Do:                                                      ////
1167
////   - add LFSR with more taps                                  ////
1168
////                                                              ////
1169
////  Author(s):                                                  ////
1170
////      - Michael Unneback, unneback@opencores.org              ////
1171
////        ORSoC AB                                              ////
1172
////                                                              ////
1173
//////////////////////////////////////////////////////////////////////
1174
////                                                              ////
1175
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1176
////                                                              ////
1177
//// This source file may be used and distributed without         ////
1178
//// restriction provided that this copyright statement is not    ////
1179
//// removed from the file and that any derivative work contains  ////
1180
//// the original copyright notice and the associated disclaimer. ////
1181
////                                                              ////
1182
//// This source file is free software; you can redistribute it   ////
1183
//// and/or modify it under the terms of the GNU Lesser General   ////
1184
//// Public License as published by the Free Software Foundation; ////
1185
//// either version 2.1 of the License, or (at your option) any   ////
1186
//// later version.                                               ////
1187
////                                                              ////
1188
//// This source is distributed in the hope that it will be       ////
1189
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1190
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1191
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1192
//// details.                                                     ////
1193
////                                                              ////
1194
//// You should have received a copy of the GNU Lesser General    ////
1195
//// Public License along with this source; if not, download it   ////
1196
//// from http://www.opencores.org/lgpl.shtml                     ////
1197
////                                                              ////
1198
//////////////////////////////////////////////////////////////////////
1199
// binary counter
1200
module vl_cnt_bin_ce_rew_l1 (
1201
 cke, rew, level1, rst, clk);
1202
   parameter length = 4;
1203
   input cke;
1204
   input rew;
1205
   output reg level1;
1206
   input rst;
1207
   input clk;
1208
   parameter clear_value = 0;
1209
   parameter set_value = 1;
1210
   parameter wrap_value = 1;
1211
   parameter level1_value = 15;
1212
   wire clear;
1213
   assign clear = 1'b0;
1214
   reg  [length:1] qi;
1215
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1216
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1217
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1218
   assign q_next = rew ? q_next_rew : q_next_fw;
1219
   always @ (posedge clk or posedge rst)
1220
     if (rst)
1221
       qi <= {length{1'b0}};
1222
     else
1223
     if (cke)
1224
       qi <= q_next;
1225
    always @ (posedge clk or posedge rst)
1226
    if (rst)
1227
        level1 <= 1'b0;
1228
    else
1229
    if (cke)
1230
    if (clear)
1231
        level1 <= 1'b0;
1232
    else if (q_next == level1_value)
1233
        level1 <= 1'b1;
1234
    else if (qi == level1_value & rew)
1235
        level1 <= 1'b0;
1236
endmodule
1237
//////////////////////////////////////////////////////////////////////
1238
////                                                              ////
1239
////  Versatile counter                                           ////
1240
////                                                              ////
1241
////  Description                                                 ////
1242
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1243
////  counter                                                     ////
1244
////                                                              ////
1245
////  To Do:                                                      ////
1246
////   - add LFSR with more taps                                  ////
1247
////                                                              ////
1248
////  Author(s):                                                  ////
1249
////      - Michael Unneback, unneback@opencores.org              ////
1250
////        ORSoC AB                                              ////
1251
////                                                              ////
1252
//////////////////////////////////////////////////////////////////////
1253
////                                                              ////
1254
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1255
////                                                              ////
1256
//// This source file may be used and distributed without         ////
1257
//// restriction provided that this copyright statement is not    ////
1258
//// removed from the file and that any derivative work contains  ////
1259
//// the original copyright notice and the associated disclaimer. ////
1260
////                                                              ////
1261
//// This source file is free software; you can redistribute it   ////
1262
//// and/or modify it under the terms of the GNU Lesser General   ////
1263
//// Public License as published by the Free Software Foundation; ////
1264
//// either version 2.1 of the License, or (at your option) any   ////
1265
//// later version.                                               ////
1266
////                                                              ////
1267
//// This source is distributed in the hope that it will be       ////
1268
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1269
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1270
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1271
//// details.                                                     ////
1272
////                                                              ////
1273
//// You should have received a copy of the GNU Lesser General    ////
1274
//// Public License along with this source; if not, download it   ////
1275
//// from http://www.opencores.org/lgpl.shtml                     ////
1276
////                                                              ////
1277
//////////////////////////////////////////////////////////////////////
1278
// binary counter
1279 40 unneback
module vl_cnt_bin_ce_rew_zq_l1 (
1280
 cke, rew, zq, level1, rst, clk);
1281 6 unneback
   parameter length = 4;
1282
   input cke;
1283
   input rew;
1284 25 unneback
   output reg zq;
1285
   output reg level1;
1286
   input rst;
1287
   input clk;
1288
   parameter clear_value = 0;
1289
   parameter set_value = 1;
1290
   parameter wrap_value = 1;
1291
   parameter level1_value = 15;
1292 29 unneback
   wire clear;
1293 30 unneback
   assign clear = 1'b0;
1294 25 unneback
   reg  [length:1] qi;
1295
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1296
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1297
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1298
   assign q_next = rew ? q_next_rew : q_next_fw;
1299
   always @ (posedge clk or posedge rst)
1300
     if (rst)
1301
       qi <= {length{1'b0}};
1302
     else
1303
     if (cke)
1304
       qi <= q_next;
1305
   always @ (posedge clk or posedge rst)
1306
     if (rst)
1307
       zq <= 1'b1;
1308
     else
1309
     if (cke)
1310
       zq <= q_next == {length{1'b0}};
1311
    always @ (posedge clk or posedge rst)
1312
    if (rst)
1313
        level1 <= 1'b0;
1314
    else
1315
    if (cke)
1316 29 unneback
    if (clear)
1317
        level1 <= 1'b0;
1318
    else if (q_next == level1_value)
1319 25 unneback
        level1 <= 1'b1;
1320
    else if (qi == level1_value & rew)
1321
        level1 <= 1'b0;
1322
endmodule
1323
//////////////////////////////////////////////////////////////////////
1324
////                                                              ////
1325
////  Versatile counter                                           ////
1326
////                                                              ////
1327
////  Description                                                 ////
1328
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1329
////  counter                                                     ////
1330
////                                                              ////
1331
////  To Do:                                                      ////
1332
////   - add LFSR with more taps                                  ////
1333
////                                                              ////
1334
////  Author(s):                                                  ////
1335
////      - Michael Unneback, unneback@opencores.org              ////
1336
////        ORSoC AB                                              ////
1337
////                                                              ////
1338
//////////////////////////////////////////////////////////////////////
1339
////                                                              ////
1340
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1341
////                                                              ////
1342
//// This source file may be used and distributed without         ////
1343
//// restriction provided that this copyright statement is not    ////
1344
//// removed from the file and that any derivative work contains  ////
1345
//// the original copyright notice and the associated disclaimer. ////
1346
////                                                              ////
1347
//// This source file is free software; you can redistribute it   ////
1348
//// and/or modify it under the terms of the GNU Lesser General   ////
1349
//// Public License as published by the Free Software Foundation; ////
1350
//// either version 2.1 of the License, or (at your option) any   ////
1351
//// later version.                                               ////
1352
////                                                              ////
1353
//// This source is distributed in the hope that it will be       ////
1354
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1355
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1356
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1357
//// details.                                                     ////
1358
////                                                              ////
1359
//// You should have received a copy of the GNU Lesser General    ////
1360
//// Public License along with this source; if not, download it   ////
1361
//// from http://www.opencores.org/lgpl.shtml                     ////
1362
////                                                              ////
1363
//////////////////////////////////////////////////////////////////////
1364
// binary counter
1365 40 unneback
module vl_cnt_bin_ce_rew_q_zq_l1 (
1366
 cke, rew, q, zq, level1, rst, clk);
1367 25 unneback
   parameter length = 4;
1368
   input cke;
1369
   input rew;
1370
   output [length:1] q;
1371
   output reg zq;
1372
   output reg level1;
1373
   input rst;
1374
   input clk;
1375
   parameter clear_value = 0;
1376
   parameter set_value = 1;
1377
   parameter wrap_value = 1;
1378
   parameter level1_value = 15;
1379 29 unneback
   wire clear;
1380 30 unneback
   assign clear = 1'b0;
1381 25 unneback
   reg  [length:1] qi;
1382
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1383
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1384
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1385
   assign q_next = rew ? q_next_rew : q_next_fw;
1386
   always @ (posedge clk or posedge rst)
1387
     if (rst)
1388
       qi <= {length{1'b0}};
1389
     else
1390
     if (cke)
1391
       qi <= q_next;
1392
   assign q = qi;
1393
   always @ (posedge clk or posedge rst)
1394
     if (rst)
1395
       zq <= 1'b1;
1396
     else
1397
     if (cke)
1398
       zq <= q_next == {length{1'b0}};
1399
    always @ (posedge clk or posedge rst)
1400
    if (rst)
1401
        level1 <= 1'b0;
1402
    else
1403
    if (cke)
1404 29 unneback
    if (clear)
1405
        level1 <= 1'b0;
1406
    else if (q_next == level1_value)
1407 25 unneback
        level1 <= 1'b1;
1408
    else if (qi == level1_value & rew)
1409
        level1 <= 1'b0;
1410
endmodule
1411
//////////////////////////////////////////////////////////////////////
1412
////                                                              ////
1413
////  Versatile counter                                           ////
1414
////                                                              ////
1415
////  Description                                                 ////
1416
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1417
////  counter                                                     ////
1418
////                                                              ////
1419
////  To Do:                                                      ////
1420
////   - add LFSR with more taps                                  ////
1421
////                                                              ////
1422
////  Author(s):                                                  ////
1423
////      - Michael Unneback, unneback@opencores.org              ////
1424
////        ORSoC AB                                              ////
1425
////                                                              ////
1426
//////////////////////////////////////////////////////////////////////
1427
////                                                              ////
1428
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1429
////                                                              ////
1430
//// This source file may be used and distributed without         ////
1431
//// restriction provided that this copyright statement is not    ////
1432
//// removed from the file and that any derivative work contains  ////
1433
//// the original copyright notice and the associated disclaimer. ////
1434
////                                                              ////
1435
//// This source file is free software; you can redistribute it   ////
1436
//// and/or modify it under the terms of the GNU Lesser General   ////
1437
//// Public License as published by the Free Software Foundation; ////
1438
//// either version 2.1 of the License, or (at your option) any   ////
1439
//// later version.                                               ////
1440
////                                                              ////
1441
//// This source is distributed in the hope that it will be       ////
1442
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1443
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1444
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1445
//// details.                                                     ////
1446
////                                                              ////
1447
//// You should have received a copy of the GNU Lesser General    ////
1448
//// Public License along with this source; if not, download it   ////
1449
//// from http://www.opencores.org/lgpl.shtml                     ////
1450
////                                                              ////
1451
//////////////////////////////////////////////////////////////////////
1452 75 unneback
// LFSR counter
1453 136 unneback
module vl_cnt_lfsr_zq (
1454
 zq, rst, clk);
1455
   parameter length = 4;
1456
   output reg zq;
1457
   input rst;
1458
   input clk;
1459
   parameter clear_value = 0;
1460
   parameter set_value = 1;
1461
   parameter wrap_value = 8;
1462
   parameter level1_value = 15;
1463
   reg  [length:1] qi;
1464
   reg lfsr_fb;
1465
   wire [length:1] q_next;
1466
   reg [32:1] polynom;
1467
   integer i;
1468
   always @ (qi)
1469
   begin
1470
        case (length)
1471
         2: polynom = 32'b11;                               // 0x3
1472
         3: polynom = 32'b110;                              // 0x6
1473
         4: polynom = 32'b1100;                             // 0xC
1474
         5: polynom = 32'b10100;                            // 0x14
1475
         6: polynom = 32'b110000;                           // 0x30
1476
         7: polynom = 32'b1100000;                          // 0x60
1477
         8: polynom = 32'b10111000;                         // 0xb8
1478
         9: polynom = 32'b100010000;                        // 0x110
1479
        10: polynom = 32'b1001000000;                       // 0x240
1480
        11: polynom = 32'b10100000000;                      // 0x500
1481
        12: polynom = 32'b100000101001;                     // 0x829
1482
        13: polynom = 32'b1000000001100;                    // 0x100C
1483
        14: polynom = 32'b10000000010101;                   // 0x2015
1484
        15: polynom = 32'b110000000000000;                  // 0x6000
1485
        16: polynom = 32'b1101000000001000;                 // 0xD008
1486
        17: polynom = 32'b10010000000000000;                // 0x12000
1487
        18: polynom = 32'b100000010000000000;               // 0x20400
1488
        19: polynom = 32'b1000000000000100011;              // 0x40023
1489
        20: polynom = 32'b10010000000000000000;             // 0x90000
1490
        21: polynom = 32'b101000000000000000000;            // 0x140000
1491
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1492
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1493
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1494
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1495
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1496
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1497
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1498
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1499
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1500
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1501
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1502
        default: polynom = 32'b0;
1503
        endcase
1504
        lfsr_fb = qi[length];
1505
        for (i=length-1; i>=1; i=i-1) begin
1506
            if (polynom[i])
1507
                lfsr_fb = lfsr_fb  ~^ qi[i];
1508
        end
1509
    end
1510
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1511
   always @ (posedge clk or posedge rst)
1512
     if (rst)
1513
       qi <= {length{1'b0}};
1514
     else
1515
       qi <= q_next;
1516
   always @ (posedge clk or posedge rst)
1517
     if (rst)
1518
       zq <= 1'b1;
1519
     else
1520
       zq <= q_next == {length{1'b0}};
1521
endmodule
1522
//////////////////////////////////////////////////////////////////////
1523
////                                                              ////
1524
////  Versatile counter                                           ////
1525
////                                                              ////
1526
////  Description                                                 ////
1527
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1528
////  counter                                                     ////
1529
////                                                              ////
1530
////  To Do:                                                      ////
1531
////   - add LFSR with more taps                                  ////
1532
////                                                              ////
1533
////  Author(s):                                                  ////
1534
////      - Michael Unneback, unneback@opencores.org              ////
1535
////        ORSoC AB                                              ////
1536
////                                                              ////
1537
//////////////////////////////////////////////////////////////////////
1538
////                                                              ////
1539
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1540
////                                                              ////
1541
//// This source file may be used and distributed without         ////
1542
//// restriction provided that this copyright statement is not    ////
1543
//// removed from the file and that any derivative work contains  ////
1544
//// the original copyright notice and the associated disclaimer. ////
1545
////                                                              ////
1546
//// This source file is free software; you can redistribute it   ////
1547
//// and/or modify it under the terms of the GNU Lesser General   ////
1548
//// Public License as published by the Free Software Foundation; ////
1549
//// either version 2.1 of the License, or (at your option) any   ////
1550
//// later version.                                               ////
1551
////                                                              ////
1552
//// This source is distributed in the hope that it will be       ////
1553
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1554
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1555
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1556
//// details.                                                     ////
1557
////                                                              ////
1558
//// You should have received a copy of the GNU Lesser General    ////
1559
//// Public License along with this source; if not, download it   ////
1560
//// from http://www.opencores.org/lgpl.shtml                     ////
1561
////                                                              ////
1562
//////////////////////////////////////////////////////////////////////
1563
// LFSR counter
1564 75 unneback
module vl_cnt_lfsr_ce (
1565
 cke, zq, rst, clk);
1566
   parameter length = 4;
1567
   input cke;
1568
   output reg zq;
1569
   input rst;
1570
   input clk;
1571
   parameter clear_value = 0;
1572
   parameter set_value = 1;
1573
   parameter wrap_value = 0;
1574
   parameter level1_value = 15;
1575
   reg  [length:1] qi;
1576
   reg lfsr_fb;
1577
   wire [length:1] q_next;
1578
   reg [32:1] polynom;
1579
   integer i;
1580
   always @ (qi)
1581
   begin
1582
        case (length)
1583
         2: polynom = 32'b11;                               // 0x3
1584
         3: polynom = 32'b110;                              // 0x6
1585
         4: polynom = 32'b1100;                             // 0xC
1586
         5: polynom = 32'b10100;                            // 0x14
1587
         6: polynom = 32'b110000;                           // 0x30
1588
         7: polynom = 32'b1100000;                          // 0x60
1589
         8: polynom = 32'b10111000;                         // 0xb8
1590
         9: polynom = 32'b100010000;                        // 0x110
1591
        10: polynom = 32'b1001000000;                       // 0x240
1592
        11: polynom = 32'b10100000000;                      // 0x500
1593
        12: polynom = 32'b100000101001;                     // 0x829
1594
        13: polynom = 32'b1000000001100;                    // 0x100C
1595
        14: polynom = 32'b10000000010101;                   // 0x2015
1596
        15: polynom = 32'b110000000000000;                  // 0x6000
1597
        16: polynom = 32'b1101000000001000;                 // 0xD008
1598
        17: polynom = 32'b10010000000000000;                // 0x12000
1599
        18: polynom = 32'b100000010000000000;               // 0x20400
1600
        19: polynom = 32'b1000000000000100011;              // 0x40023
1601
        20: polynom = 32'b10010000000000000000;             // 0x90000
1602
        21: polynom = 32'b101000000000000000000;            // 0x140000
1603
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1604
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1605
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1606
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1607
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1608
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1609
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1610
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1611
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1612
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1613
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1614
        default: polynom = 32'b0;
1615
        endcase
1616
        lfsr_fb = qi[length];
1617
        for (i=length-1; i>=1; i=i-1) begin
1618
            if (polynom[i])
1619
                lfsr_fb = lfsr_fb  ~^ qi[i];
1620
        end
1621
    end
1622
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1623
   always @ (posedge clk or posedge rst)
1624
     if (rst)
1625
       qi <= {length{1'b0}};
1626
     else
1627
     if (cke)
1628
       qi <= q_next;
1629
   always @ (posedge clk or posedge rst)
1630
     if (rst)
1631
       zq <= 1'b1;
1632
     else
1633
     if (cke)
1634
       zq <= q_next == {length{1'b0}};
1635
endmodule
1636
//////////////////////////////////////////////////////////////////////
1637
////                                                              ////
1638
////  Versatile counter                                           ////
1639
////                                                              ////
1640
////  Description                                                 ////
1641
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1642
////  counter                                                     ////
1643
////                                                              ////
1644
////  To Do:                                                      ////
1645
////   - add LFSR with more taps                                  ////
1646
////                                                              ////
1647
////  Author(s):                                                  ////
1648
////      - Michael Unneback, unneback@opencores.org              ////
1649
////        ORSoC AB                                              ////
1650
////                                                              ////
1651
//////////////////////////////////////////////////////////////////////
1652
////                                                              ////
1653
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1654
////                                                              ////
1655
//// This source file may be used and distributed without         ////
1656
//// restriction provided that this copyright statement is not    ////
1657
//// removed from the file and that any derivative work contains  ////
1658
//// the original copyright notice and the associated disclaimer. ////
1659
////                                                              ////
1660
//// This source file is free software; you can redistribute it   ////
1661
//// and/or modify it under the terms of the GNU Lesser General   ////
1662
//// Public License as published by the Free Software Foundation; ////
1663
//// either version 2.1 of the License, or (at your option) any   ////
1664
//// later version.                                               ////
1665
////                                                              ////
1666
//// This source is distributed in the hope that it will be       ////
1667
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1668
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1669
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1670
//// details.                                                     ////
1671
////                                                              ////
1672
//// You should have received a copy of the GNU Lesser General    ////
1673
//// Public License along with this source; if not, download it   ////
1674
//// from http://www.opencores.org/lgpl.shtml                     ////
1675
////                                                              ////
1676
//////////////////////////////////////////////////////////////////////
1677 139 unneback
// LFSR counter
1678
module vl_cnt_lfsr_ce_zq (
1679
 cke, zq, rst, clk);
1680
   parameter length = 4;
1681
   input cke;
1682
   output reg zq;
1683
   input rst;
1684
   input clk;
1685
   parameter clear_value = 0;
1686
   parameter set_value = 1;
1687
   parameter wrap_value = 8;
1688
   parameter level1_value = 15;
1689
   reg  [length:1] qi;
1690
   reg lfsr_fb;
1691
   wire [length:1] q_next;
1692
   reg [32:1] polynom;
1693
   integer i;
1694
   always @ (qi)
1695
   begin
1696
        case (length)
1697
         2: polynom = 32'b11;                               // 0x3
1698
         3: polynom = 32'b110;                              // 0x6
1699
         4: polynom = 32'b1100;                             // 0xC
1700
         5: polynom = 32'b10100;                            // 0x14
1701
         6: polynom = 32'b110000;                           // 0x30
1702
         7: polynom = 32'b1100000;                          // 0x60
1703
         8: polynom = 32'b10111000;                         // 0xb8
1704
         9: polynom = 32'b100010000;                        // 0x110
1705
        10: polynom = 32'b1001000000;                       // 0x240
1706
        11: polynom = 32'b10100000000;                      // 0x500
1707
        12: polynom = 32'b100000101001;                     // 0x829
1708
        13: polynom = 32'b1000000001100;                    // 0x100C
1709
        14: polynom = 32'b10000000010101;                   // 0x2015
1710
        15: polynom = 32'b110000000000000;                  // 0x6000
1711
        16: polynom = 32'b1101000000001000;                 // 0xD008
1712
        17: polynom = 32'b10010000000000000;                // 0x12000
1713
        18: polynom = 32'b100000010000000000;               // 0x20400
1714
        19: polynom = 32'b1000000000000100011;              // 0x40023
1715
        20: polynom = 32'b10010000000000000000;             // 0x90000
1716
        21: polynom = 32'b101000000000000000000;            // 0x140000
1717
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1718
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1719
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1720
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1721
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1722
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1723
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1724
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1725
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1726
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1727
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1728
        default: polynom = 32'b0;
1729
        endcase
1730
        lfsr_fb = qi[length];
1731
        for (i=length-1; i>=1; i=i-1) begin
1732
            if (polynom[i])
1733
                lfsr_fb = lfsr_fb  ~^ qi[i];
1734
        end
1735
    end
1736
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1737
   always @ (posedge clk or posedge rst)
1738
     if (rst)
1739
       qi <= {length{1'b0}};
1740
     else
1741
     if (cke)
1742
       qi <= q_next;
1743
   always @ (posedge clk or posedge rst)
1744
     if (rst)
1745
       zq <= 1'b1;
1746
     else
1747
     if (cke)
1748
       zq <= q_next == {length{1'b0}};
1749
endmodule
1750
//////////////////////////////////////////////////////////////////////
1751
////                                                              ////
1752
////  Versatile counter                                           ////
1753
////                                                              ////
1754
////  Description                                                 ////
1755
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1756
////  counter                                                     ////
1757
////                                                              ////
1758
////  To Do:                                                      ////
1759
////   - add LFSR with more taps                                  ////
1760
////                                                              ////
1761
////  Author(s):                                                  ////
1762
////      - Michael Unneback, unneback@opencores.org              ////
1763
////        ORSoC AB                                              ////
1764
////                                                              ////
1765
//////////////////////////////////////////////////////////////////////
1766
////                                                              ////
1767
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1768
////                                                              ////
1769
//// This source file may be used and distributed without         ////
1770
//// restriction provided that this copyright statement is not    ////
1771
//// removed from the file and that any derivative work contains  ////
1772
//// the original copyright notice and the associated disclaimer. ////
1773
////                                                              ////
1774
//// This source file is free software; you can redistribute it   ////
1775
//// and/or modify it under the terms of the GNU Lesser General   ////
1776
//// Public License as published by the Free Software Foundation; ////
1777
//// either version 2.1 of the License, or (at your option) any   ////
1778
//// later version.                                               ////
1779
////                                                              ////
1780
//// This source is distributed in the hope that it will be       ////
1781
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1782
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1783
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1784
//// details.                                                     ////
1785
////                                                              ////
1786
//// You should have received a copy of the GNU Lesser General    ////
1787
//// Public License along with this source; if not, download it   ////
1788
//// from http://www.opencores.org/lgpl.shtml                     ////
1789
////                                                              ////
1790
//////////////////////////////////////////////////////////////////////
1791
// LFSR counter
1792
module vl_cnt_lfsr_ce_q (
1793
 cke, q, rst, clk);
1794
   parameter length = 4;
1795
   input cke;
1796
   output [length:1] q;
1797
   input rst;
1798
   input clk;
1799
   parameter clear_value = 0;
1800
   parameter set_value = 1;
1801
   parameter wrap_value = 8;
1802
   parameter level1_value = 15;
1803
   reg  [length:1] qi;
1804
   reg lfsr_fb;
1805
   wire [length:1] q_next;
1806
   reg [32:1] polynom;
1807
   integer i;
1808
   always @ (qi)
1809
   begin
1810
        case (length)
1811
         2: polynom = 32'b11;                               // 0x3
1812
         3: polynom = 32'b110;                              // 0x6
1813
         4: polynom = 32'b1100;                             // 0xC
1814
         5: polynom = 32'b10100;                            // 0x14
1815
         6: polynom = 32'b110000;                           // 0x30
1816
         7: polynom = 32'b1100000;                          // 0x60
1817
         8: polynom = 32'b10111000;                         // 0xb8
1818
         9: polynom = 32'b100010000;                        // 0x110
1819
        10: polynom = 32'b1001000000;                       // 0x240
1820
        11: polynom = 32'b10100000000;                      // 0x500
1821
        12: polynom = 32'b100000101001;                     // 0x829
1822
        13: polynom = 32'b1000000001100;                    // 0x100C
1823
        14: polynom = 32'b10000000010101;                   // 0x2015
1824
        15: polynom = 32'b110000000000000;                  // 0x6000
1825
        16: polynom = 32'b1101000000001000;                 // 0xD008
1826
        17: polynom = 32'b10010000000000000;                // 0x12000
1827
        18: polynom = 32'b100000010000000000;               // 0x20400
1828
        19: polynom = 32'b1000000000000100011;              // 0x40023
1829
        20: polynom = 32'b10010000000000000000;             // 0x90000
1830
        21: polynom = 32'b101000000000000000000;            // 0x140000
1831
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1832
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1833
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1834
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1835
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1836
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1837
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1838
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1839
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1840
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1841
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1842
        default: polynom = 32'b0;
1843
        endcase
1844
        lfsr_fb = qi[length];
1845
        for (i=length-1; i>=1; i=i-1) begin
1846
            if (polynom[i])
1847
                lfsr_fb = lfsr_fb  ~^ qi[i];
1848
        end
1849
    end
1850
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1851
   always @ (posedge clk or posedge rst)
1852
     if (rst)
1853
       qi <= {length{1'b0}};
1854
     else
1855
     if (cke)
1856
       qi <= q_next;
1857
   assign q = qi;
1858
endmodule
1859
//////////////////////////////////////////////////////////////////////
1860
////                                                              ////
1861
////  Versatile counter                                           ////
1862
////                                                              ////
1863
////  Description                                                 ////
1864
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1865
////  counter                                                     ////
1866
////                                                              ////
1867
////  To Do:                                                      ////
1868
////   - add LFSR with more taps                                  ////
1869
////                                                              ////
1870
////  Author(s):                                                  ////
1871
////      - Michael Unneback, unneback@opencores.org              ////
1872
////        ORSoC AB                                              ////
1873
////                                                              ////
1874
//////////////////////////////////////////////////////////////////////
1875
////                                                              ////
1876
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1877
////                                                              ////
1878
//// This source file may be used and distributed without         ////
1879
//// restriction provided that this copyright statement is not    ////
1880
//// removed from the file and that any derivative work contains  ////
1881
//// the original copyright notice and the associated disclaimer. ////
1882
////                                                              ////
1883
//// This source file is free software; you can redistribute it   ////
1884
//// and/or modify it under the terms of the GNU Lesser General   ////
1885
//// Public License as published by the Free Software Foundation; ////
1886
//// either version 2.1 of the License, or (at your option) any   ////
1887
//// later version.                                               ////
1888
////                                                              ////
1889
//// This source is distributed in the hope that it will be       ////
1890
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1891
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1892
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1893
//// details.                                                     ////
1894
////                                                              ////
1895
//// You should have received a copy of the GNU Lesser General    ////
1896
//// Public License along with this source; if not, download it   ////
1897
//// from http://www.opencores.org/lgpl.shtml                     ////
1898
////                                                              ////
1899
//////////////////////////////////////////////////////////////////////
1900
// LFSR counter
1901
module vl_cnt_lfsr_ce_clear_q (
1902
 clear, cke, q, rst, clk);
1903
   parameter length = 4;
1904
   input clear;
1905
   input cke;
1906
   output [length:1] q;
1907
   input rst;
1908
   input clk;
1909
   parameter clear_value = 0;
1910
   parameter set_value = 1;
1911
   parameter wrap_value = 8;
1912
   parameter level1_value = 15;
1913
   reg  [length:1] qi;
1914
   reg lfsr_fb;
1915
   wire [length:1] q_next;
1916
   reg [32:1] polynom;
1917
   integer i;
1918
   always @ (qi)
1919
   begin
1920
        case (length)
1921
         2: polynom = 32'b11;                               // 0x3
1922
         3: polynom = 32'b110;                              // 0x6
1923
         4: polynom = 32'b1100;                             // 0xC
1924
         5: polynom = 32'b10100;                            // 0x14
1925
         6: polynom = 32'b110000;                           // 0x30
1926
         7: polynom = 32'b1100000;                          // 0x60
1927
         8: polynom = 32'b10111000;                         // 0xb8
1928
         9: polynom = 32'b100010000;                        // 0x110
1929
        10: polynom = 32'b1001000000;                       // 0x240
1930
        11: polynom = 32'b10100000000;                      // 0x500
1931
        12: polynom = 32'b100000101001;                     // 0x829
1932
        13: polynom = 32'b1000000001100;                    // 0x100C
1933
        14: polynom = 32'b10000000010101;                   // 0x2015
1934
        15: polynom = 32'b110000000000000;                  // 0x6000
1935
        16: polynom = 32'b1101000000001000;                 // 0xD008
1936
        17: polynom = 32'b10010000000000000;                // 0x12000
1937
        18: polynom = 32'b100000010000000000;               // 0x20400
1938
        19: polynom = 32'b1000000000000100011;              // 0x40023
1939
        20: polynom = 32'b10010000000000000000;             // 0x90000
1940
        21: polynom = 32'b101000000000000000000;            // 0x140000
1941
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1942
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1943
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1944
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1945
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1946
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1947
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1948
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1949
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1950
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1951
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1952
        default: polynom = 32'b0;
1953
        endcase
1954
        lfsr_fb = qi[length];
1955
        for (i=length-1; i>=1; i=i-1) begin
1956
            if (polynom[i])
1957
                lfsr_fb = lfsr_fb  ~^ qi[i];
1958
        end
1959
    end
1960
   assign q_next =  clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1961
   always @ (posedge clk or posedge rst)
1962
     if (rst)
1963
       qi <= {length{1'b0}};
1964
     else
1965
     if (cke)
1966
       qi <= q_next;
1967
   assign q = qi;
1968
endmodule
1969
//////////////////////////////////////////////////////////////////////
1970
////                                                              ////
1971
////  Versatile counter                                           ////
1972
////                                                              ////
1973
////  Description                                                 ////
1974
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1975
////  counter                                                     ////
1976
////                                                              ////
1977
////  To Do:                                                      ////
1978
////   - add LFSR with more taps                                  ////
1979
////                                                              ////
1980
////  Author(s):                                                  ////
1981
////      - Michael Unneback, unneback@opencores.org              ////
1982
////        ORSoC AB                                              ////
1983
////                                                              ////
1984
//////////////////////////////////////////////////////////////////////
1985
////                                                              ////
1986
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1987
////                                                              ////
1988
//// This source file may be used and distributed without         ////
1989
//// restriction provided that this copyright statement is not    ////
1990
//// removed from the file and that any derivative work contains  ////
1991
//// the original copyright notice and the associated disclaimer. ////
1992
////                                                              ////
1993
//// This source file is free software; you can redistribute it   ////
1994
//// and/or modify it under the terms of the GNU Lesser General   ////
1995
//// Public License as published by the Free Software Foundation; ////
1996
//// either version 2.1 of the License, or (at your option) any   ////
1997
//// later version.                                               ////
1998
////                                                              ////
1999
//// This source is distributed in the hope that it will be       ////
2000
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2001
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2002
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2003
//// details.                                                     ////
2004
////                                                              ////
2005
//// You should have received a copy of the GNU Lesser General    ////
2006
//// Public License along with this source; if not, download it   ////
2007
//// from http://www.opencores.org/lgpl.shtml                     ////
2008
////                                                              ////
2009
//////////////////////////////////////////////////////////////////////
2010
// LFSR counter
2011
module vl_cnt_lfsr_ce_q_zq (
2012
 cke, q, zq, rst, clk);
2013
   parameter length = 4;
2014
   input cke;
2015
   output [length:1] q;
2016
   output reg zq;
2017
   input rst;
2018
   input clk;
2019
   parameter clear_value = 0;
2020
   parameter set_value = 1;
2021
   parameter wrap_value = 8;
2022
   parameter level1_value = 15;
2023
   reg  [length:1] qi;
2024
   reg lfsr_fb;
2025
   wire [length:1] q_next;
2026
   reg [32:1] polynom;
2027
   integer i;
2028
   always @ (qi)
2029
   begin
2030
        case (length)
2031
         2: polynom = 32'b11;                               // 0x3
2032
         3: polynom = 32'b110;                              // 0x6
2033
         4: polynom = 32'b1100;                             // 0xC
2034
         5: polynom = 32'b10100;                            // 0x14
2035
         6: polynom = 32'b110000;                           // 0x30
2036
         7: polynom = 32'b1100000;                          // 0x60
2037
         8: polynom = 32'b10111000;                         // 0xb8
2038
         9: polynom = 32'b100010000;                        // 0x110
2039
        10: polynom = 32'b1001000000;                       // 0x240
2040
        11: polynom = 32'b10100000000;                      // 0x500
2041
        12: polynom = 32'b100000101001;                     // 0x829
2042
        13: polynom = 32'b1000000001100;                    // 0x100C
2043
        14: polynom = 32'b10000000010101;                   // 0x2015
2044
        15: polynom = 32'b110000000000000;                  // 0x6000
2045
        16: polynom = 32'b1101000000001000;                 // 0xD008
2046
        17: polynom = 32'b10010000000000000;                // 0x12000
2047
        18: polynom = 32'b100000010000000000;               // 0x20400
2048
        19: polynom = 32'b1000000000000100011;              // 0x40023
2049
        20: polynom = 32'b10010000000000000000;             // 0x90000
2050
        21: polynom = 32'b101000000000000000000;            // 0x140000
2051
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2052
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2053
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2054
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2055
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2056
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2057
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2058
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2059
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2060
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2061
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2062
        default: polynom = 32'b0;
2063
        endcase
2064
        lfsr_fb = qi[length];
2065
        for (i=length-1; i>=1; i=i-1) begin
2066
            if (polynom[i])
2067
                lfsr_fb = lfsr_fb  ~^ qi[i];
2068
        end
2069
    end
2070
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2071
   always @ (posedge clk or posedge rst)
2072
     if (rst)
2073
       qi <= {length{1'b0}};
2074
     else
2075
     if (cke)
2076
       qi <= q_next;
2077
   assign q = qi;
2078
   always @ (posedge clk or posedge rst)
2079
     if (rst)
2080
       zq <= 1'b1;
2081
     else
2082
     if (cke)
2083
       zq <= q_next == {length{1'b0}};
2084
endmodule
2085
//////////////////////////////////////////////////////////////////////
2086
////                                                              ////
2087
////  Versatile counter                                           ////
2088
////                                                              ////
2089
////  Description                                                 ////
2090
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2091
////  counter                                                     ////
2092
////                                                              ////
2093
////  To Do:                                                      ////
2094
////   - add LFSR with more taps                                  ////
2095
////                                                              ////
2096
////  Author(s):                                                  ////
2097
////      - Michael Unneback, unneback@opencores.org              ////
2098
////        ORSoC AB                                              ////
2099
////                                                              ////
2100
//////////////////////////////////////////////////////////////////////
2101
////                                                              ////
2102
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2103
////                                                              ////
2104
//// This source file may be used and distributed without         ////
2105
//// restriction provided that this copyright statement is not    ////
2106
//// removed from the file and that any derivative work contains  ////
2107
//// the original copyright notice and the associated disclaimer. ////
2108
////                                                              ////
2109
//// This source file is free software; you can redistribute it   ////
2110
//// and/or modify it under the terms of the GNU Lesser General   ////
2111
//// Public License as published by the Free Software Foundation; ////
2112
//// either version 2.1 of the License, or (at your option) any   ////
2113
//// later version.                                               ////
2114
////                                                              ////
2115
//// This source is distributed in the hope that it will be       ////
2116
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2117
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2118
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2119
//// details.                                                     ////
2120
////                                                              ////
2121
//// You should have received a copy of the GNU Lesser General    ////
2122
//// Public License along with this source; if not, download it   ////
2123
//// from http://www.opencores.org/lgpl.shtml                     ////
2124
////                                                              ////
2125
//////////////////////////////////////////////////////////////////////
2126
// LFSR counter
2127
module vl_cnt_lfsr_ce_rew_l1 (
2128
 cke, rew, level1, rst, clk);
2129
   parameter length = 4;
2130
   input cke;
2131
   input rew;
2132
   output reg level1;
2133
   input rst;
2134
   input clk;
2135
   parameter clear_value = 0;
2136
   parameter set_value = 1;
2137
   parameter wrap_value = 8;
2138
   parameter level1_value = 15;
2139
   wire clear;
2140
   assign clear = 1'b0;
2141
   reg  [length:1] qi;
2142
   reg lfsr_fb, lfsr_fb_rew;
2143
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2144
   reg [32:1] polynom_rew;
2145
   integer j;
2146
   reg [32:1] polynom;
2147
   integer i;
2148
   always @ (qi)
2149
   begin
2150
        case (length)
2151
         2: polynom = 32'b11;                               // 0x3
2152
         3: polynom = 32'b110;                              // 0x6
2153
         4: polynom = 32'b1100;                             // 0xC
2154
         5: polynom = 32'b10100;                            // 0x14
2155
         6: polynom = 32'b110000;                           // 0x30
2156
         7: polynom = 32'b1100000;                          // 0x60
2157
         8: polynom = 32'b10111000;                         // 0xb8
2158
         9: polynom = 32'b100010000;                        // 0x110
2159
        10: polynom = 32'b1001000000;                       // 0x240
2160
        11: polynom = 32'b10100000000;                      // 0x500
2161
        12: polynom = 32'b100000101001;                     // 0x829
2162
        13: polynom = 32'b1000000001100;                    // 0x100C
2163
        14: polynom = 32'b10000000010101;                   // 0x2015
2164
        15: polynom = 32'b110000000000000;                  // 0x6000
2165
        16: polynom = 32'b1101000000001000;                 // 0xD008
2166
        17: polynom = 32'b10010000000000000;                // 0x12000
2167
        18: polynom = 32'b100000010000000000;               // 0x20400
2168
        19: polynom = 32'b1000000000000100011;              // 0x40023
2169
        20: polynom = 32'b10010000000000000000;             // 0x90000
2170
        21: polynom = 32'b101000000000000000000;            // 0x140000
2171
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2172
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2173
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2174
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2175
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2176
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2177
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2178
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2179
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2180
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2181
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2182
        default: polynom = 32'b0;
2183
        endcase
2184
        lfsr_fb = qi[length];
2185
        for (i=length-1; i>=1; i=i-1) begin
2186
            if (polynom[i])
2187
                lfsr_fb = lfsr_fb  ~^ qi[i];
2188
        end
2189
    end
2190
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2191
   always @ (qi)
2192
   begin
2193
        case (length)
2194
         2: polynom_rew = 32'b11;
2195
         3: polynom_rew = 32'b110;
2196
         4: polynom_rew = 32'b1100;
2197
         5: polynom_rew = 32'b10100;
2198
         6: polynom_rew = 32'b110000;
2199
         7: polynom_rew = 32'b1100000;
2200
         8: polynom_rew = 32'b10111000;
2201
         9: polynom_rew = 32'b100010000;
2202
        10: polynom_rew = 32'b1001000000;
2203
        11: polynom_rew = 32'b10100000000;
2204
        12: polynom_rew = 32'b100000101001;
2205
        13: polynom_rew = 32'b1000000001100;
2206
        14: polynom_rew = 32'b10000000010101;
2207
        15: polynom_rew = 32'b110000000000000;
2208
        16: polynom_rew = 32'b1101000000001000;
2209
        17: polynom_rew = 32'b10010000000000000;
2210
        18: polynom_rew = 32'b100000010000000000;
2211
        19: polynom_rew = 32'b1000000000000100011;
2212
        20: polynom_rew = 32'b10000010000000000000;
2213
        21: polynom_rew = 32'b101000000000000000000;
2214
        22: polynom_rew = 32'b1100000000000000000000;
2215
        23: polynom_rew = 32'b10000100000000000000000;
2216
        24: polynom_rew = 32'b111000010000000000000000;
2217
        25: polynom_rew = 32'b1001000000000000000000000;
2218
        26: polynom_rew = 32'b10000000000000000000100011;
2219
        27: polynom_rew = 32'b100000000000000000000010011;
2220
        28: polynom_rew = 32'b1100100000000000000000000000;
2221
        29: polynom_rew = 32'b10100000000000000000000000000;
2222
        30: polynom_rew = 32'b100000000000000000000000101001;
2223
        31: polynom_rew = 32'b1001000000000000000000000000000;
2224
        32: polynom_rew = 32'b10000000001000000000000000000011;
2225
        default: polynom_rew = 32'b0;
2226
        endcase
2227
        // rotate left
2228
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
2229
        lfsr_fb_rew = qi[length];
2230
        for (i=length-1; i>=1; i=i-1) begin
2231
            if (polynom_rew[i])
2232
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
2233
        end
2234
    end
2235
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
2236
   assign q_next = rew ? q_next_rew : q_next_fw;
2237
   always @ (posedge clk or posedge rst)
2238
     if (rst)
2239
       qi <= {length{1'b0}};
2240
     else
2241
     if (cke)
2242
       qi <= q_next;
2243
    always @ (posedge clk or posedge rst)
2244
    if (rst)
2245
        level1 <= 1'b0;
2246
    else
2247
    if (cke)
2248
    if (clear)
2249
        level1 <= 1'b0;
2250
    else if (q_next == level1_value)
2251
        level1 <= 1'b1;
2252
    else if (qi == level1_value & rew)
2253
        level1 <= 1'b0;
2254
endmodule
2255
//////////////////////////////////////////////////////////////////////
2256
////                                                              ////
2257
////  Versatile counter                                           ////
2258
////                                                              ////
2259
////  Description                                                 ////
2260
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2261
////  counter                                                     ////
2262
////                                                              ////
2263
////  To Do:                                                      ////
2264
////   - add LFSR with more taps                                  ////
2265
////                                                              ////
2266
////  Author(s):                                                  ////
2267
////      - Michael Unneback, unneback@opencores.org              ////
2268
////        ORSoC AB                                              ////
2269
////                                                              ////
2270
//////////////////////////////////////////////////////////////////////
2271
////                                                              ////
2272
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2273
////                                                              ////
2274
//// This source file may be used and distributed without         ////
2275
//// restriction provided that this copyright statement is not    ////
2276
//// removed from the file and that any derivative work contains  ////
2277
//// the original copyright notice and the associated disclaimer. ////
2278
////                                                              ////
2279
//// This source file is free software; you can redistribute it   ////
2280
//// and/or modify it under the terms of the GNU Lesser General   ////
2281
//// Public License as published by the Free Software Foundation; ////
2282
//// either version 2.1 of the License, or (at your option) any   ////
2283
//// later version.                                               ////
2284
////                                                              ////
2285
//// This source is distributed in the hope that it will be       ////
2286
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2287
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2288
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2289
//// details.                                                     ////
2290
////                                                              ////
2291
//// You should have received a copy of the GNU Lesser General    ////
2292
//// Public License along with this source; if not, download it   ////
2293
//// from http://www.opencores.org/lgpl.shtml                     ////
2294
////                                                              ////
2295
//////////////////////////////////////////////////////////////////////
2296 6 unneback
// GRAY counter
2297 139 unneback
module vl_cnt_gray (
2298
 q, rst, clk);
2299
   parameter length = 4;
2300
   output reg [length:1] q;
2301
   input rst;
2302
   input clk;
2303
   parameter clear_value = 0;
2304
   parameter set_value = 1;
2305
   parameter wrap_value = 8;
2306
   parameter level1_value = 15;
2307
   reg  [length:1] qi;
2308
   wire [length:1] q_next;
2309
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2310
   always @ (posedge clk or posedge rst)
2311
     if (rst)
2312
       qi <= {length{1'b0}};
2313
     else
2314
       qi <= q_next;
2315
   always @ (posedge clk or posedge rst)
2316
     if (rst)
2317
       q <= {length{1'b0}};
2318
     else
2319
         q <= (q_next>>1) ^ q_next;
2320
endmodule
2321
//////////////////////////////////////////////////////////////////////
2322
////                                                              ////
2323
////  Versatile counter                                           ////
2324
////                                                              ////
2325
////  Description                                                 ////
2326
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2327
////  counter                                                     ////
2328
////                                                              ////
2329
////  To Do:                                                      ////
2330
////   - add LFSR with more taps                                  ////
2331
////                                                              ////
2332
////  Author(s):                                                  ////
2333
////      - Michael Unneback, unneback@opencores.org              ////
2334
////        ORSoC AB                                              ////
2335
////                                                              ////
2336
//////////////////////////////////////////////////////////////////////
2337
////                                                              ////
2338
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2339
////                                                              ////
2340
//// This source file may be used and distributed without         ////
2341
//// restriction provided that this copyright statement is not    ////
2342
//// removed from the file and that any derivative work contains  ////
2343
//// the original copyright notice and the associated disclaimer. ////
2344
////                                                              ////
2345
//// This source file is free software; you can redistribute it   ////
2346
//// and/or modify it under the terms of the GNU Lesser General   ////
2347
//// Public License as published by the Free Software Foundation; ////
2348
//// either version 2.1 of the License, or (at your option) any   ////
2349
//// later version.                                               ////
2350
////                                                              ////
2351
//// This source is distributed in the hope that it will be       ////
2352
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2353
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2354
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2355
//// details.                                                     ////
2356
////                                                              ////
2357
//// You should have received a copy of the GNU Lesser General    ////
2358
//// Public License along with this source; if not, download it   ////
2359
//// from http://www.opencores.org/lgpl.shtml                     ////
2360
////                                                              ////
2361
//////////////////////////////////////////////////////////////////////
2362
// GRAY counter
2363
module vl_cnt_gray_ce (
2364
 cke, q, rst, clk);
2365
   parameter length = 4;
2366
   input cke;
2367
   output reg [length:1] q;
2368
   input rst;
2369
   input clk;
2370
   parameter clear_value = 0;
2371
   parameter set_value = 1;
2372
   parameter wrap_value = 8;
2373
   parameter level1_value = 15;
2374
   reg  [length:1] qi;
2375
   wire [length:1] q_next;
2376
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2377
   always @ (posedge clk or posedge rst)
2378
     if (rst)
2379
       qi <= {length{1'b0}};
2380
     else
2381
     if (cke)
2382
       qi <= q_next;
2383
   always @ (posedge clk or posedge rst)
2384
     if (rst)
2385
       q <= {length{1'b0}};
2386
     else
2387
       if (cke)
2388
         q <= (q_next>>1) ^ q_next;
2389
endmodule
2390
//////////////////////////////////////////////////////////////////////
2391
////                                                              ////
2392
////  Versatile counter                                           ////
2393
////                                                              ////
2394
////  Description                                                 ////
2395
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2396
////  counter                                                     ////
2397
////                                                              ////
2398
////  To Do:                                                      ////
2399
////   - add LFSR with more taps                                  ////
2400
////                                                              ////
2401
////  Author(s):                                                  ////
2402
////      - Michael Unneback, unneback@opencores.org              ////
2403
////        ORSoC AB                                              ////
2404
////                                                              ////
2405
//////////////////////////////////////////////////////////////////////
2406
////                                                              ////
2407
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2408
////                                                              ////
2409
//// This source file may be used and distributed without         ////
2410
//// restriction provided that this copyright statement is not    ////
2411
//// removed from the file and that any derivative work contains  ////
2412
//// the original copyright notice and the associated disclaimer. ////
2413
////                                                              ////
2414
//// This source file is free software; you can redistribute it   ////
2415
//// and/or modify it under the terms of the GNU Lesser General   ////
2416
//// Public License as published by the Free Software Foundation; ////
2417
//// either version 2.1 of the License, or (at your option) any   ////
2418
//// later version.                                               ////
2419
////                                                              ////
2420
//// This source is distributed in the hope that it will be       ////
2421
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2422
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2423
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2424
//// details.                                                     ////
2425
////                                                              ////
2426
//// You should have received a copy of the GNU Lesser General    ////
2427
//// Public License along with this source; if not, download it   ////
2428
//// from http://www.opencores.org/lgpl.shtml                     ////
2429
////                                                              ////
2430
//////////////////////////////////////////////////////////////////////
2431
// GRAY counter
2432 40 unneback
module vl_cnt_gray_ce_bin (
2433
 cke, q, q_bin, rst, clk);
2434 6 unneback
   parameter length = 4;
2435
   input cke;
2436
   output reg [length:1] q;
2437
   output [length:1] q_bin;
2438
   input rst;
2439
   input clk;
2440
   parameter clear_value = 0;
2441
   parameter set_value = 1;
2442
   parameter wrap_value = 8;
2443
   parameter level1_value = 15;
2444
   reg  [length:1] qi;
2445
   wire [length:1] q_next;
2446
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2447
   always @ (posedge clk or posedge rst)
2448
     if (rst)
2449
       qi <= {length{1'b0}};
2450
     else
2451
     if (cke)
2452
       qi <= q_next;
2453
   always @ (posedge clk or posedge rst)
2454
     if (rst)
2455
       q <= {length{1'b0}};
2456
     else
2457
       if (cke)
2458
         q <= (q_next>>1) ^ q_next;
2459
   assign q_bin = qi;
2460
endmodule
2461
//////////////////////////////////////////////////////////////////////
2462
////                                                              ////
2463
////  Versatile library, counters                                 ////
2464
////                                                              ////
2465
////  Description                                                 ////
2466
////  counters                                                    ////
2467
////                                                              ////
2468
////                                                              ////
2469
////  To Do:                                                      ////
2470
////   - add more counters                                        ////
2471
////                                                              ////
2472
////  Author(s):                                                  ////
2473
////      - Michael Unneback, unneback@opencores.org              ////
2474
////        ORSoC AB                                              ////
2475
////                                                              ////
2476
//////////////////////////////////////////////////////////////////////
2477
////                                                              ////
2478
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2479
////                                                              ////
2480
//// This source file may be used and distributed without         ////
2481
//// restriction provided that this copyright statement is not    ////
2482
//// removed from the file and that any derivative work contains  ////
2483
//// the original copyright notice and the associated disclaimer. ////
2484
////                                                              ////
2485
//// This source file is free software; you can redistribute it   ////
2486
//// and/or modify it under the terms of the GNU Lesser General   ////
2487
//// Public License as published by the Free Software Foundation; ////
2488
//// either version 2.1 of the License, or (at your option) any   ////
2489
//// later version.                                               ////
2490
////                                                              ////
2491
//// This source is distributed in the hope that it will be       ////
2492
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2493
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2494
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2495
//// details.                                                     ////
2496
////                                                              ////
2497
//// You should have received a copy of the GNU Lesser General    ////
2498
//// Public License along with this source; if not, download it   ////
2499
//// from http://www.opencores.org/lgpl.shtml                     ////
2500
////                                                              ////
2501
//////////////////////////////////////////////////////////////////////
2502 18 unneback
module vl_cnt_shreg_wrap ( q, rst, clk);
2503 6 unneback
   parameter length = 4;
2504
   output reg [0:length-1] q;
2505
   input rst;
2506
   input clk;
2507
    always @ (posedge clk or posedge rst)
2508
    if (rst)
2509
        q <= {1'b1,{length-1{1'b0}}};
2510
    else
2511
        q <= {q[length-1],q[0:length-2]};
2512
endmodule
2513 18 unneback
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
2514 6 unneback
   parameter length = 4;
2515
   input cke;
2516
   output reg [0:length-1] q;
2517
   input rst;
2518
   input clk;
2519
    always @ (posedge clk or posedge rst)
2520
    if (rst)
2521
        q <= {1'b1,{length-1{1'b0}}};
2522
    else
2523
        if (cke)
2524
            q <= {q[length-1],q[0:length-2]};
2525
endmodule
2526 105 unneback
module vl_cnt_shreg_clear ( clear, q, rst, clk);
2527
   parameter length = 4;
2528
   input clear;
2529
   output reg [0:length-1] q;
2530
   input rst;
2531
   input clk;
2532
    always @ (posedge clk or posedge rst)
2533
    if (rst)
2534
        q <= {1'b1,{length-1{1'b0}}};
2535
    else
2536
        if (clear)
2537
            q <= {1'b1,{length-1{1'b0}}};
2538
        else
2539
            q <= q >> 1;
2540
endmodule
2541 18 unneback
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
2542 6 unneback
   parameter length = 4;
2543
   input cke, clear;
2544
   output reg [0:length-1] q;
2545
   input rst;
2546
   input clk;
2547
    always @ (posedge clk or posedge rst)
2548
    if (rst)
2549
        q <= {1'b1,{length-1{1'b0}}};
2550
    else
2551
        if (cke)
2552
            if (clear)
2553
                q <= {1'b1,{length-1{1'b0}}};
2554
            else
2555
                q <= q >> 1;
2556
endmodule
2557 18 unneback
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
2558 6 unneback
   parameter length = 4;
2559
   input cke, clear;
2560
   output reg [0:length-1] q;
2561
   input rst;
2562
   input clk;
2563
    always @ (posedge clk or posedge rst)
2564
    if (rst)
2565
        q <= {1'b1,{length-1{1'b0}}};
2566
    else
2567
        if (cke)
2568
            if (clear)
2569
                q <= {1'b1,{length-1{1'b0}}};
2570
            else
2571
            q <= {q[length-1],q[0:length-2]};
2572
endmodule
2573
//////////////////////////////////////////////////////////////////////
2574
////                                                              ////
2575
////  Versatile library, memories                                 ////
2576
////                                                              ////
2577
////  Description                                                 ////
2578
////  memories                                                    ////
2579
////                                                              ////
2580
////                                                              ////
2581
////  To Do:                                                      ////
2582
////   - add more memory types                                    ////
2583
////                                                              ////
2584
////  Author(s):                                                  ////
2585
////      - Michael Unneback, unneback@opencores.org              ////
2586
////        ORSoC AB                                              ////
2587
////                                                              ////
2588
//////////////////////////////////////////////////////////////////////
2589
////                                                              ////
2590
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2591
////                                                              ////
2592
//// This source file may be used and distributed without         ////
2593
//// restriction provided that this copyright statement is not    ////
2594
//// removed from the file and that any derivative work contains  ////
2595
//// the original copyright notice and the associated disclaimer. ////
2596
////                                                              ////
2597
//// This source file is free software; you can redistribute it   ////
2598
//// and/or modify it under the terms of the GNU Lesser General   ////
2599
//// Public License as published by the Free Software Foundation; ////
2600
//// either version 2.1 of the License, or (at your option) any   ////
2601
//// later version.                                               ////
2602
////                                                              ////
2603