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1 6 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
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////  Versatile library, clock and reset                          ////
4
////                                                              ////
5
////  Description                                                 ////
6
////  Logic related to clock and reset                            ////
7
////                                                              ////
8
////                                                              ////
9
////  To Do:                                                      ////
10
////   - add more different registers                             ////
11
////                                                              ////
12
////  Author(s):                                                  ////
13
////      - Michael Unneback, unneback@opencores.org              ////
14
////        ORSoC AB                                              ////
15
////                                                              ////
16
//////////////////////////////////////////////////////////////////////
17
////                                                              ////
18
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
19
////                                                              ////
20
//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
36
////                                                              ////
37
//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
// Global buffer
43
// usage:
44
// use to enable global buffers for high fan out signals such as clock and reset
45
`timescale 1 ns/100 ps
46
// Version: 8.4 8.4.0.33
47
module gbuf(GL,CLK);
48
output GL;
49
input  CLK;
50
    wire GND;
51
    GND GND_1_net(.Y(GND));
52
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
53
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
54
endmodule
55
`timescale 1 ns/1 ns
56
module vl_gbuf ( i, o);
57
input i;
58
output o;
59
`ifdef SIM_GBUF
60
assign o=i;
61
`else
62
gbuf gbuf_i0 ( .CLK(i), .GL(o));
63
`endif
64
endmodule
65
 //ACTEL
66
// sync reset
67 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
68 6 unneback
// output active high global reset sync with two DFFs 
69
`timescale 1 ns/100 ps
70
module vl_sync_rst ( rst_n_i, rst_o, clk);
71
input rst_n_i, clk;
72
output rst_o;
73 18 unneback
reg [1:0] tmp;
74 6 unneback
always @ (posedge clk or negedge rst_n_i)
75
if (!rst_n_i)
76 17 unneback
        tmp <= 2'b11;
77 6 unneback
else
78 17 unneback
        tmp <= {1'b0,tmp[0]};
79
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
80 6 unneback
endmodule
81
// vl_pll
82 17 unneback
`timescale 1 ps/1 ps
83 6 unneback
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
84
parameter index = 0;
85
parameter number_of_clk = 1;
86 17 unneback
parameter period_time_0 = 20000;
87
parameter period_time_1 = 20000;
88
parameter period_time_2 = 20000;
89
parameter lock_delay = 2000000;
90 6 unneback
input clk_i, rst_n_i;
91
output lock;
92
output reg [0:number_of_clk-1] clk_o;
93
output [0:number_of_clk-1] rst_o;
94
`ifdef SIM_PLL
95
always
96
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
97
generate if (number_of_clk > 1)
98
always
99
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
100
endgenerate
101
generate if (number_of_clk > 2)
102
always
103
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
104
endgenerate
105
genvar i;
106
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
107
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
108
end
109
endgenerate
110
assign #lock_delay lock = rst_n_i;
111
endmodule
112
`else
113
generate if (number_of_clk==1 & index==0) begin
114
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
115
end
116
endgenerate // index==0
117
generate if (number_of_clk==1 & index==1) begin
118
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
119
end
120
endgenerate // index==1
121
generate if (number_of_clk==1 & index==2) begin
122
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
123
end
124
endgenerate // index==2
125
generate if (number_of_clk==1 & index==3) begin
126
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
127
end
128
endgenerate // index==0
129
generate if (number_of_clk==2 & index==0) begin
130
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
131
end
132
endgenerate // index==0
133
generate if (number_of_clk==2 & index==1) begin
134
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
135
end
136
endgenerate // index==1
137
generate if (number_of_clk==2 & index==2) begin
138
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
139
end
140
endgenerate // index==2
141
generate if (number_of_clk==2 & index==3) begin
142
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
143
end
144
endgenerate // index==0
145
generate if (number_of_clk==3 & index==0) begin
146
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
147
end
148
endgenerate // index==0
149
generate if (number_of_clk==3 & index==1) begin
150
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
151
end
152
endgenerate // index==1
153
generate if (number_of_clk==3 & index==2) begin
154
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
155
end
156
endgenerate // index==2
157
generate if (number_of_clk==3 & index==3) begin
158
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
159
end
160
endgenerate // index==0
161
genvar i;
162
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
163
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
164
end
165
endgenerate
166
endmodule
167
`endif
168
 //actel
169
//////////////////////////////////////////////////////////////////////
170
////                                                              ////
171
////  Versatile library, registers                                ////
172
////                                                              ////
173
////  Description                                                 ////
174
////  Different type of registers                                 ////
175
////                                                              ////
176
////                                                              ////
177
////  To Do:                                                      ////
178
////   - add more different registers                             ////
179
////                                                              ////
180
////  Author(s):                                                  ////
181
////      - Michael Unneback, unneback@opencores.org              ////
182
////        ORSoC AB                                              ////
183
////                                                              ////
184
//////////////////////////////////////////////////////////////////////
185
////                                                              ////
186
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
187
////                                                              ////
188
//// This source file may be used and distributed without         ////
189
//// restriction provided that this copyright statement is not    ////
190
//// removed from the file and that any derivative work contains  ////
191
//// the original copyright notice and the associated disclaimer. ////
192
////                                                              ////
193
//// This source file is free software; you can redistribute it   ////
194
//// and/or modify it under the terms of the GNU Lesser General   ////
195
//// Public License as published by the Free Software Foundation; ////
196
//// either version 2.1 of the License, or (at your option) any   ////
197
//// later version.                                               ////
198
////                                                              ////
199
//// This source is distributed in the hope that it will be       ////
200
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
201
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
202
//// PURPOSE.  See the GNU Lesser General Public License for more ////
203
//// details.                                                     ////
204
////                                                              ////
205
//// You should have received a copy of the GNU Lesser General    ////
206
//// Public License along with this source; if not, download it   ////
207
//// from http://www.opencores.org/lgpl.shtml                     ////
208
////                                                              ////
209
//////////////////////////////////////////////////////////////////////
210 18 unneback
module vl_dff ( d, q, clk, rst);
211 6 unneback
        parameter width = 1;
212
        parameter reset_value = 0;
213
        input [width-1:0] d;
214
        input clk, rst;
215
        output reg [width-1:0] q;
216
        always @ (posedge clk or posedge rst)
217
        if (rst)
218
                q <= reset_value;
219
        else
220
                q <= d;
221
endmodule
222 18 unneback
module vl_dff_array ( d, q, clk, rst);
223 6 unneback
        parameter width = 1;
224
        parameter depth = 2;
225
        parameter reset_value = 1'b0;
226
        input [width-1:0] d;
227
        input clk, rst;
228
        output [width-1:0] q;
229
        reg  [0:depth-1] q_tmp [width-1:0];
230
        integer i;
231
        always @ (posedge clk or posedge rst)
232
        if (rst) begin
233
            for (i=0;i<depth;i=i+1)
234
                q_tmp[i] <= {width{reset_value}};
235
        end else begin
236
            q_tmp[0] <= d;
237
            for (i=1;i<depth;i=i+1)
238
                q_tmp[i] <= q_tmp[i-1];
239
        end
240
    assign q = q_tmp[depth-1];
241
endmodule
242 18 unneback
module vl_dff_ce ( d, ce, q, clk, rst);
243 6 unneback
        parameter width = 1;
244
        parameter reset_value = 0;
245
        input [width-1:0] d;
246
        input ce, clk, rst;
247
        output reg [width-1:0] q;
248
        always @ (posedge clk or posedge rst)
249
        if (rst)
250
                q <= reset_value;
251
        else
252
                if (ce)
253
                        q <= d;
254
endmodule
255 18 unneback
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
256 8 unneback
        parameter width = 1;
257
        parameter reset_value = 0;
258
        input [width-1:0] d;
259 10 unneback
        input ce, clear, clk, rst;
260 8 unneback
        output reg [width-1:0] q;
261
        always @ (posedge clk or posedge rst)
262
        if (rst)
263
            q <= reset_value;
264
        else
265
            if (ce)
266
                if (clear)
267
                    q <= {width{1'b0}};
268
                else
269
                    q <= d;
270
endmodule
271 18 unneback
module vl_dff_sr ( aclr, aset, clock, data, q);
272 6 unneback
    input         aclr;
273
    input         aset;
274
    input         clock;
275
    input         data;
276
    output reg    q;
277
   always @ (posedge clock or posedge aclr or posedge aset)
278
     if (aclr)
279
       q <= 1'b0;
280
     else if (aset)
281
       q <= 1'b1;
282
     else
283
       q <= data;
284
endmodule
285
// LATCH
286
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
287
module latch ( d, le, q, clk);
288
input d, le;
289
output q;
290
input clk;/*
291
   always @ (posedge direction_set or posedge direction_clr)
292
     if (direction_clr)
293
       direction <= going_empty;
294
     else
295
       direction <= going_full;*/
296
endmodule
297 18 unneback
module vl_shreg ( d, q, clk, rst);
298 17 unneback
parameter depth = 10;
299
input d;
300
output q;
301
input clk, rst;
302
reg [1:depth] dffs;
303
always @ (posedge clk or posedge rst)
304
if (rst)
305
    dffs <= {depth{1'b0}};
306
else
307
    dffs <= {d,dffs[1:depth-1]};
308
assign q = dffs[depth];
309
endmodule
310 18 unneback
module vl_shreg_ce ( d, ce, q, clk, rst);
311 17 unneback
parameter depth = 10;
312
input d, ce;
313
output q;
314
input clk, rst;
315
reg [1:depth] dffs;
316
always @ (posedge clk or posedge rst)
317
if (rst)
318
    dffs <= {depth{1'b0}};
319
else
320
    if (ce)
321
        dffs <= {d,dffs[1:depth-1]};
322
assign q = dffs[depth];
323
endmodule
324 18 unneback
module vl_delay ( d, q, clk, rst);
325 15 unneback
parameter depth = 10;
326
input d;
327
output q;
328
input clk, rst;
329
reg [1:depth] dffs;
330
always @ (posedge clk or posedge rst)
331
if (rst)
332
    dffs <= {depth{1'b0}};
333
else
334
    dffs <= {d,dffs[1:depth-1]};
335
assign q = dffs[depth];
336
endmodule
337 18 unneback
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
338 17 unneback
parameter depth = 10;
339
input d;
340
output q, emptyflag;
341
input clk, rst;
342
reg [1:depth] dffs;
343
always @ (posedge clk or posedge rst)
344
if (rst)
345
    dffs <= {depth{1'b0}};
346
else
347
    dffs <= {d,dffs[1:depth-1]};
348
assign q = dffs[depth];
349
assign emptyflag = !(|dffs);
350
endmodule
351 6 unneback
//////////////////////////////////////////////////////////////////////
352
////                                                              ////
353 18 unneback
////  Logic functions                                             ////
354
////                                                              ////
355
////  Description                                                 ////
356
////  Logic functions such as multiplexers                        ////
357
////                                                              ////
358
////                                                              ////
359
////  To Do:                                                      ////
360
////   -                                                          ////
361
////                                                              ////
362
////  Author(s):                                                  ////
363
////      - Michael Unneback, unneback@opencores.org              ////
364
////        ORSoC AB                                              ////
365
////                                                              ////
366
//////////////////////////////////////////////////////////////////////
367
////                                                              ////
368
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
369
////                                                              ////
370
//// This source file may be used and distributed without         ////
371
//// restriction provided that this copyright statement is not    ////
372
//// removed from the file and that any derivative work contains  ////
373
//// the original copyright notice and the associated disclaimer. ////
374
////                                                              ////
375
//// This source file is free software; you can redistribute it   ////
376
//// and/or modify it under the terms of the GNU Lesser General   ////
377
//// Public License as published by the Free Software Foundation; ////
378
//// either version 2.1 of the License, or (at your option) any   ////
379
//// later version.                                               ////
380
////                                                              ////
381
//// This source is distributed in the hope that it will be       ////
382
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
383
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
384
//// PURPOSE.  See the GNU Lesser General Public License for more ////
385
//// details.                                                     ////
386
////                                                              ////
387
//// You should have received a copy of the GNU Lesser General    ////
388
//// Public License along with this source; if not, download it   ////
389
//// from http://www.opencores.org/lgpl.shtml                     ////
390
////                                                              ////
391
//////////////////////////////////////////////////////////////////////
392
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
393
parameter width = 32;
394
parameter nr_of_ports = 4;
395
input [width-1:0] a3, a2, a1, a0;
396
input [nr_of_ports-1:0] sel;
397
output reg [width-1:0] dout;
398 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
399 18 unneback
integer i;
400
// and
401
assign tmp[0] = {width{sel[0]}} & a0;
402
assign tmp[1] = {width{sel[1]}} & a1;
403
assign tmp[2] = {width{sel[2]}} & a2;
404
assign tmp[3] = {width{sel[3]}} & a3;
405
// or
406
assign dout = tmp[3] | tmp[2] | tmp[1] | tmp[0];
407
endmodule
408
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
409
parameter width = 32;
410
parameter nr_of_ports = 5;
411
input [width-1:0] a4, a3, a2, a1, a0;
412
input [nr_of_ports-1:0] sel;
413
output reg [width-1:0] dout;
414 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
415 18 unneback
integer i;
416
// and
417
assign tmp[0] = {width{sel[0]}} & a0;
418
assign tmp[1] = {width{sel[1]}} & a1;
419
assign tmp[2] = {width{sel[2]}} & a2;
420
assign tmp[3] = {width{sel[3]}} & a3;
421
assign tmp[4] = {width{sel[4]}} & a4;
422
// or
423
assign dout = tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
424
endmodule
425
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
426
parameter width = 32;
427
parameter nr_of_ports = 6;
428
input [width-1:0] a5, a4, a3, a2, a1, a0;
429
input [nr_of_ports-1:0] sel;
430
output reg [width-1:0] dout;
431 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
432 18 unneback
integer i;
433
// and
434
assign tmp[0] = {width{sel[0]}} & a0;
435
assign tmp[1] = {width{sel[1]}} & a1;
436
assign tmp[2] = {width{sel[2]}} & a2;
437
assign tmp[3] = {width{sel[3]}} & a3;
438
assign tmp[4] = {width{sel[4]}} & a4;
439
assign tmp[5] = {width{sel[5]}} & a5;
440
// or
441
assign dout = tmp[5] | tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
442
endmodule
443
//////////////////////////////////////////////////////////////////////
444
////                                                              ////
445 6 unneback
////  Versatile counter                                           ////
446
////                                                              ////
447
////  Description                                                 ////
448
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
449
////  counter                                                     ////
450
////                                                              ////
451
////  To Do:                                                      ////
452
////   - add LFSR with more taps                                  ////
453
////                                                              ////
454
////  Author(s):                                                  ////
455
////      - Michael Unneback, unneback@opencores.org              ////
456
////        ORSoC AB                                              ////
457
////                                                              ////
458
//////////////////////////////////////////////////////////////////////
459
////                                                              ////
460
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
461
////                                                              ////
462
//// This source file may be used and distributed without         ////
463
//// restriction provided that this copyright statement is not    ////
464
//// removed from the file and that any derivative work contains  ////
465
//// the original copyright notice and the associated disclaimer. ////
466
////                                                              ////
467
//// This source file is free software; you can redistribute it   ////
468
//// and/or modify it under the terms of the GNU Lesser General   ////
469
//// Public License as published by the Free Software Foundation; ////
470
//// either version 2.1 of the License, or (at your option) any   ////
471
//// later version.                                               ////
472
////                                                              ////
473
//// This source is distributed in the hope that it will be       ////
474
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
475
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
476
//// PURPOSE.  See the GNU Lesser General Public License for more ////
477
//// details.                                                     ////
478
////                                                              ////
479
//// You should have received a copy of the GNU Lesser General    ////
480
//// Public License along with this source; if not, download it   ////
481
//// from http://www.opencores.org/lgpl.shtml                     ////
482
////                                                              ////
483
//////////////////////////////////////////////////////////////////////
484
// binary counter
485 18 unneback
module vl_cnt_bin_ce ( cke, q, rst, clk);
486 6 unneback
   parameter length = 4;
487
   input cke;
488
   output [length:1] q;
489
   input rst;
490
   input clk;
491
   parameter clear_value = 0;
492
   parameter set_value = 1;
493
   parameter wrap_value = 0;
494
   parameter level1_value = 15;
495
   reg  [length:1] qi;
496
   wire [length:1] q_next;
497
   assign q_next = qi + {{length-1{1'b0}},1'b1};
498
   always @ (posedge clk or posedge rst)
499
     if (rst)
500
       qi <= {length{1'b0}};
501
     else
502
     if (cke)
503
       qi <= q_next;
504
   assign q = qi;
505
endmodule
506
//////////////////////////////////////////////////////////////////////
507
////                                                              ////
508
////  Versatile counter                                           ////
509
////                                                              ////
510
////  Description                                                 ////
511
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
512
////  counter                                                     ////
513
////                                                              ////
514
////  To Do:                                                      ////
515
////   - add LFSR with more taps                                  ////
516
////                                                              ////
517
////  Author(s):                                                  ////
518
////      - Michael Unneback, unneback@opencores.org              ////
519
////        ORSoC AB                                              ////
520
////                                                              ////
521
//////////////////////////////////////////////////////////////////////
522
////                                                              ////
523
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
524
////                                                              ////
525
//// This source file may be used and distributed without         ////
526
//// restriction provided that this copyright statement is not    ////
527
//// removed from the file and that any derivative work contains  ////
528
//// the original copyright notice and the associated disclaimer. ////
529
////                                                              ////
530
//// This source file is free software; you can redistribute it   ////
531
//// and/or modify it under the terms of the GNU Lesser General   ////
532
//// Public License as published by the Free Software Foundation; ////
533
//// either version 2.1 of the License, or (at your option) any   ////
534
//// later version.                                               ////
535
////                                                              ////
536
//// This source is distributed in the hope that it will be       ////
537
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
538
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
539
//// PURPOSE.  See the GNU Lesser General Public License for more ////
540
//// details.                                                     ////
541
////                                                              ////
542
//// You should have received a copy of the GNU Lesser General    ////
543
//// Public License along with this source; if not, download it   ////
544
//// from http://www.opencores.org/lgpl.shtml                     ////
545
////                                                              ////
546
//////////////////////////////////////////////////////////////////////
547
// binary counter
548 18 unneback
module vl_cnt_bin_ce_clear ( clear, cke, q, rst, clk);
549 6 unneback
   parameter length = 4;
550
   input clear;
551
   input cke;
552
   output [length:1] q;
553
   input rst;
554
   input clk;
555
   parameter clear_value = 0;
556
   parameter set_value = 1;
557
   parameter wrap_value = 0;
558
   parameter level1_value = 15;
559
   reg  [length:1] qi;
560
   wire [length:1] q_next;
561
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
562
   always @ (posedge clk or posedge rst)
563
     if (rst)
564
       qi <= {length{1'b0}};
565
     else
566
     if (cke)
567
       qi <= q_next;
568
   assign q = qi;
569
endmodule
570
//////////////////////////////////////////////////////////////////////
571
////                                                              ////
572
////  Versatile counter                                           ////
573
////                                                              ////
574
////  Description                                                 ////
575
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
576
////  counter                                                     ////
577
////                                                              ////
578
////  To Do:                                                      ////
579
////   - add LFSR with more taps                                  ////
580
////                                                              ////
581
////  Author(s):                                                  ////
582
////      - Michael Unneback, unneback@opencores.org              ////
583
////        ORSoC AB                                              ////
584
////                                                              ////
585
//////////////////////////////////////////////////////////////////////
586
////                                                              ////
587
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
588
////                                                              ////
589
//// This source file may be used and distributed without         ////
590
//// restriction provided that this copyright statement is not    ////
591
//// removed from the file and that any derivative work contains  ////
592
//// the original copyright notice and the associated disclaimer. ////
593
////                                                              ////
594
//// This source file is free software; you can redistribute it   ////
595
//// and/or modify it under the terms of the GNU Lesser General   ////
596
//// Public License as published by the Free Software Foundation; ////
597
//// either version 2.1 of the License, or (at your option) any   ////
598
//// later version.                                               ////
599
////                                                              ////
600
//// This source is distributed in the hope that it will be       ////
601
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
602
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
603
//// PURPOSE.  See the GNU Lesser General Public License for more ////
604
//// details.                                                     ////
605
////                                                              ////
606
//// You should have received a copy of the GNU Lesser General    ////
607
//// Public License along with this source; if not, download it   ////
608
//// from http://www.opencores.org/lgpl.shtml                     ////
609
////                                                              ////
610
//////////////////////////////////////////////////////////////////////
611
// binary counter
612 18 unneback
module vl_cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk);
613 6 unneback
   parameter length = 4;
614
   input clear;
615
   input set;
616
   input cke;
617
   input rew;
618
   output [length:1] q;
619
   input rst;
620
   input clk;
621
   parameter clear_value = 0;
622
   parameter set_value = 1;
623
   parameter wrap_value = 0;
624
   parameter level1_value = 15;
625
   reg  [length:1] qi;
626
   wire  [length:1] q_next, q_next_fw, q_next_rew;
627
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
628
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
629
   assign q_next = rew ? q_next_rew : q_next_fw;
630
   always @ (posedge clk or posedge rst)
631
     if (rst)
632
       qi <= {length{1'b0}};
633
     else
634
     if (cke)
635
       qi <= q_next;
636
   assign q = qi;
637
endmodule
638
//////////////////////////////////////////////////////////////////////
639
////                                                              ////
640
////  Versatile counter                                           ////
641
////                                                              ////
642
////  Description                                                 ////
643
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
644
////  counter                                                     ////
645
////                                                              ////
646
////  To Do:                                                      ////
647
////   - add LFSR with more taps                                  ////
648
////                                                              ////
649
////  Author(s):                                                  ////
650
////      - Michael Unneback, unneback@opencores.org              ////
651
////        ORSoC AB                                              ////
652
////                                                              ////
653
//////////////////////////////////////////////////////////////////////
654
////                                                              ////
655
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
656
////                                                              ////
657
//// This source file may be used and distributed without         ////
658
//// restriction provided that this copyright statement is not    ////
659
//// removed from the file and that any derivative work contains  ////
660
//// the original copyright notice and the associated disclaimer. ////
661
////                                                              ////
662
//// This source file is free software; you can redistribute it   ////
663
//// and/or modify it under the terms of the GNU Lesser General   ////
664
//// Public License as published by the Free Software Foundation; ////
665
//// either version 2.1 of the License, or (at your option) any   ////
666
//// later version.                                               ////
667
////                                                              ////
668
//// This source is distributed in the hope that it will be       ////
669
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
670
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
671
//// PURPOSE.  See the GNU Lesser General Public License for more ////
672
//// details.                                                     ////
673
////                                                              ////
674
//// You should have received a copy of the GNU Lesser General    ////
675
//// Public License along with this source; if not, download it   ////
676
//// from http://www.opencores.org/lgpl.shtml                     ////
677
////                                                              ////
678
//////////////////////////////////////////////////////////////////////
679
// binary counter
680 18 unneback
module vl_cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk);
681 6 unneback
   parameter length = 4;
682
   input cke;
683
   input rew;
684
   output reg level1;
685
   input rst;
686
   input clk;
687
   parameter clear_value = 0;
688
   parameter set_value = 1;
689
   parameter wrap_value = 1;
690
   parameter level1_value = 15;
691
   reg  [length:1] qi;
692
   wire  [length:1] q_next, q_next_fw, q_next_rew;
693
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
694
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
695
   assign q_next = rew ? q_next_rew : q_next_fw;
696
   always @ (posedge clk or posedge rst)
697
     if (rst)
698
       qi <= {length{1'b0}};
699
     else
700
     if (cke)
701
       qi <= q_next;
702
    always @ (posedge clk or posedge rst)
703
    if (rst)
704
        level1 <= 1'b0;
705
    else
706
    if (cke)
707
    if (q_next == level1_value)
708
        level1 <= 1'b1;
709
    else if (qi == level1_value & rew)
710
        level1 <= 1'b0;
711
endmodule
712
//////////////////////////////////////////////////////////////////////
713
////                                                              ////
714
////  Versatile counter                                           ////
715
////                                                              ////
716
////  Description                                                 ////
717
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
718
////  counter                                                     ////
719
////                                                              ////
720
////  To Do:                                                      ////
721
////   - add LFSR with more taps                                  ////
722
////                                                              ////
723
////  Author(s):                                                  ////
724
////      - Michael Unneback, unneback@opencores.org              ////
725
////        ORSoC AB                                              ////
726
////                                                              ////
727
//////////////////////////////////////////////////////////////////////
728
////                                                              ////
729
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
730
////                                                              ////
731
//// This source file may be used and distributed without         ////
732
//// restriction provided that this copyright statement is not    ////
733
//// removed from the file and that any derivative work contains  ////
734
//// the original copyright notice and the associated disclaimer. ////
735
////                                                              ////
736
//// This source file is free software; you can redistribute it   ////
737
//// and/or modify it under the terms of the GNU Lesser General   ////
738
//// Public License as published by the Free Software Foundation; ////
739
//// either version 2.1 of the License, or (at your option) any   ////
740
//// later version.                                               ////
741
////                                                              ////
742
//// This source is distributed in the hope that it will be       ////
743
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
744
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
745
//// PURPOSE.  See the GNU Lesser General Public License for more ////
746
//// details.                                                     ////
747
////                                                              ////
748
//// You should have received a copy of the GNU Lesser General    ////
749
//// Public License along with this source; if not, download it   ////
750
//// from http://www.opencores.org/lgpl.shtml                     ////
751
////                                                              ////
752
//////////////////////////////////////////////////////////////////////
753
// LFSR counter
754 18 unneback
module vl_cnt_lfsr_zq ( zq, rst, clk);
755 6 unneback
   parameter length = 4;
756
   output reg zq;
757
   input rst;
758
   input clk;
759
   parameter clear_value = 0;
760
   parameter set_value = 1;
761
   parameter wrap_value = 8;
762
   parameter level1_value = 15;
763
   reg  [length:1] qi;
764
   reg lfsr_fb;
765
   wire [length:1] q_next;
766
   reg [32:1] polynom;
767
   integer i;
768
   always @ (qi)
769
   begin
770
        case (length)
771
         2: polynom = 32'b11;                               // 0x3
772
         3: polynom = 32'b110;                              // 0x6
773
         4: polynom = 32'b1100;                             // 0xC
774
         5: polynom = 32'b10100;                            // 0x14
775
         6: polynom = 32'b110000;                           // 0x30
776
         7: polynom = 32'b1100000;                          // 0x60
777
         8: polynom = 32'b10111000;                         // 0xb8
778
         9: polynom = 32'b100010000;                        // 0x110
779
        10: polynom = 32'b1001000000;                       // 0x240
780
        11: polynom = 32'b10100000000;                      // 0x500
781
        12: polynom = 32'b100000101001;                     // 0x829
782
        13: polynom = 32'b1000000001100;                    // 0x100C
783
        14: polynom = 32'b10000000010101;                   // 0x2015
784
        15: polynom = 32'b110000000000000;                  // 0x6000
785
        16: polynom = 32'b1101000000001000;                 // 0xD008
786
        17: polynom = 32'b10010000000000000;                // 0x12000
787
        18: polynom = 32'b100000010000000000;               // 0x20400
788
        19: polynom = 32'b1000000000000100011;              // 0x40023
789
        20: polynom = 32'b10000010000000000000;             // 0x82000
790
        21: polynom = 32'b101000000000000000000;            // 0x140000
791
        22: polynom = 32'b1100000000000000000000;           // 0x300000
792
        23: polynom = 32'b10000100000000000000000;          // 0x420000
793
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
794
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
795
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
796
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
797
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
798
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
799
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
800
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
801
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
802
        default: polynom = 32'b0;
803
        endcase
804
        lfsr_fb = qi[length];
805
        for (i=length-1; i>=1; i=i-1) begin
806
            if (polynom[i])
807
                lfsr_fb = lfsr_fb  ~^ qi[i];
808
        end
809
    end
810
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
811
   always @ (posedge clk or posedge rst)
812
     if (rst)
813
       qi <= {length{1'b0}};
814
     else
815
       qi <= q_next;
816
   always @ (posedge clk or posedge rst)
817
     if (rst)
818
       zq <= 1'b1;
819
     else
820
       zq <= q_next == {length{1'b0}};
821
endmodule
822
//////////////////////////////////////////////////////////////////////
823
////                                                              ////
824
////  Versatile counter                                           ////
825
////                                                              ////
826
////  Description                                                 ////
827
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
828
////  counter                                                     ////
829
////                                                              ////
830
////  To Do:                                                      ////
831
////   - add LFSR with more taps                                  ////
832
////                                                              ////
833
////  Author(s):                                                  ////
834
////      - Michael Unneback, unneback@opencores.org              ////
835
////        ORSoC AB                                              ////
836
////                                                              ////
837
//////////////////////////////////////////////////////////////////////
838
////                                                              ////
839
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
840
////                                                              ////
841
//// This source file may be used and distributed without         ////
842
//// restriction provided that this copyright statement is not    ////
843
//// removed from the file and that any derivative work contains  ////
844
//// the original copyright notice and the associated disclaimer. ////
845
////                                                              ////
846
//// This source file is free software; you can redistribute it   ////
847
//// and/or modify it under the terms of the GNU Lesser General   ////
848
//// Public License as published by the Free Software Foundation; ////
849
//// either version 2.1 of the License, or (at your option) any   ////
850
//// later version.                                               ////
851
////                                                              ////
852
//// This source is distributed in the hope that it will be       ////
853
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
854
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
855
//// PURPOSE.  See the GNU Lesser General Public License for more ////
856
//// details.                                                     ////
857
////                                                              ////
858
//// You should have received a copy of the GNU Lesser General    ////
859
//// Public License along with this source; if not, download it   ////
860
//// from http://www.opencores.org/lgpl.shtml                     ////
861
////                                                              ////
862
//////////////////////////////////////////////////////////////////////
863
// LFSR counter
864 18 unneback
module vl_cnt_lfsr_ce_zq ( cke, zq, rst, clk);
865 6 unneback
   parameter length = 4;
866
   input cke;
867
   output reg zq;
868
   input rst;
869
   input clk;
870
   parameter clear_value = 0;
871
   parameter set_value = 1;
872
   parameter wrap_value = 8;
873
   parameter level1_value = 15;
874
   reg  [length:1] qi;
875
   reg lfsr_fb;
876
   wire [length:1] q_next;
877
   reg [32:1] polynom;
878
   integer i;
879
   always @ (qi)
880
   begin
881
        case (length)
882
         2: polynom = 32'b11;                               // 0x3
883
         3: polynom = 32'b110;                              // 0x6
884
         4: polynom = 32'b1100;                             // 0xC
885
         5: polynom = 32'b10100;                            // 0x14
886
         6: polynom = 32'b110000;                           // 0x30
887
         7: polynom = 32'b1100000;                          // 0x60
888
         8: polynom = 32'b10111000;                         // 0xb8
889
         9: polynom = 32'b100010000;                        // 0x110
890
        10: polynom = 32'b1001000000;                       // 0x240
891
        11: polynom = 32'b10100000000;                      // 0x500
892
        12: polynom = 32'b100000101001;                     // 0x829
893
        13: polynom = 32'b1000000001100;                    // 0x100C
894
        14: polynom = 32'b10000000010101;                   // 0x2015
895
        15: polynom = 32'b110000000000000;                  // 0x6000
896
        16: polynom = 32'b1101000000001000;                 // 0xD008
897
        17: polynom = 32'b10010000000000000;                // 0x12000
898
        18: polynom = 32'b100000010000000000;               // 0x20400
899
        19: polynom = 32'b1000000000000100011;              // 0x40023
900
        20: polynom = 32'b10000010000000000000;             // 0x82000
901
        21: polynom = 32'b101000000000000000000;            // 0x140000
902
        22: polynom = 32'b1100000000000000000000;           // 0x300000
903
        23: polynom = 32'b10000100000000000000000;          // 0x420000
904
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
905
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
906
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
907
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
908
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
909
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
910
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
911
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
912
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
913
        default: polynom = 32'b0;
914
        endcase
915
        lfsr_fb = qi[length];
916
        for (i=length-1; i>=1; i=i-1) begin
917
            if (polynom[i])
918
                lfsr_fb = lfsr_fb  ~^ qi[i];
919
        end
920
    end
921
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
922
   always @ (posedge clk or posedge rst)
923
     if (rst)
924
       qi <= {length{1'b0}};
925
     else
926
     if (cke)
927
       qi <= q_next;
928
   always @ (posedge clk or posedge rst)
929
     if (rst)
930
       zq <= 1'b1;
931
     else
932
     if (cke)
933
       zq <= q_next == {length{1'b0}};
934
endmodule
935
//////////////////////////////////////////////////////////////////////
936
////                                                              ////
937
////  Versatile counter                                           ////
938
////                                                              ////
939
////  Description                                                 ////
940
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
941
////  counter                                                     ////
942
////                                                              ////
943
////  To Do:                                                      ////
944
////   - add LFSR with more taps                                  ////
945
////                                                              ////
946
////  Author(s):                                                  ////
947
////      - Michael Unneback, unneback@opencores.org              ////
948
////        ORSoC AB                                              ////
949
////                                                              ////
950
//////////////////////////////////////////////////////////////////////
951
////                                                              ////
952
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
953
////                                                              ////
954
//// This source file may be used and distributed without         ////
955
//// restriction provided that this copyright statement is not    ////
956
//// removed from the file and that any derivative work contains  ////
957
//// the original copyright notice and the associated disclaimer. ////
958
////                                                              ////
959
//// This source file is free software; you can redistribute it   ////
960
//// and/or modify it under the terms of the GNU Lesser General   ////
961
//// Public License as published by the Free Software Foundation; ////
962
//// either version 2.1 of the License, or (at your option) any   ////
963
//// later version.                                               ////
964
////                                                              ////
965
//// This source is distributed in the hope that it will be       ////
966
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
967
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
968
//// PURPOSE.  See the GNU Lesser General Public License for more ////
969
//// details.                                                     ////
970
////                                                              ////
971
//// You should have received a copy of the GNU Lesser General    ////
972
//// Public License along with this source; if not, download it   ////
973
//// from http://www.opencores.org/lgpl.shtml                     ////
974
////                                                              ////
975
//////////////////////////////////////////////////////////////////////
976
// LFSR counter
977 18 unneback
module vl_cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk);
978 6 unneback
   parameter length = 4;
979
   input cke;
980
   input rew;
981
   output reg level1;
982
   input rst;
983
   input clk;
984
   parameter clear_value = 0;
985
   parameter set_value = 1;
986
   parameter wrap_value = 8;
987
   parameter level1_value = 15;
988
   reg  [length:1] qi;
989
   reg lfsr_fb, lfsr_fb_rew;
990
   wire  [length:1] q_next, q_next_fw, q_next_rew;
991
   reg [32:1] polynom_rew;
992
   integer j;
993
   reg [32:1] polynom;
994
   integer i;
995
   always @ (qi)
996
   begin
997
        case (length)
998
         2: polynom = 32'b11;                               // 0x3
999
         3: polynom = 32'b110;                              // 0x6
1000
         4: polynom = 32'b1100;                             // 0xC
1001
         5: polynom = 32'b10100;                            // 0x14
1002
         6: polynom = 32'b110000;                           // 0x30
1003
         7: polynom = 32'b1100000;                          // 0x60
1004
         8: polynom = 32'b10111000;                         // 0xb8
1005
         9: polynom = 32'b100010000;                        // 0x110
1006
        10: polynom = 32'b1001000000;                       // 0x240
1007
        11: polynom = 32'b10100000000;                      // 0x500
1008
        12: polynom = 32'b100000101001;                     // 0x829
1009
        13: polynom = 32'b1000000001100;                    // 0x100C
1010
        14: polynom = 32'b10000000010101;                   // 0x2015
1011
        15: polynom = 32'b110000000000000;                  // 0x6000
1012
        16: polynom = 32'b1101000000001000;                 // 0xD008
1013
        17: polynom = 32'b10010000000000000;                // 0x12000
1014
        18: polynom = 32'b100000010000000000;               // 0x20400
1015
        19: polynom = 32'b1000000000000100011;              // 0x40023
1016
        20: polynom = 32'b10000010000000000000;             // 0x82000
1017
        21: polynom = 32'b101000000000000000000;            // 0x140000
1018
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1019
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1020
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1021
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1022
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1023
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1024
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1025
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1026
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1027
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1028
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1029
        default: polynom = 32'b0;
1030
        endcase
1031
        lfsr_fb = qi[length];
1032
        for (i=length-1; i>=1; i=i-1) begin
1033
            if (polynom[i])
1034
                lfsr_fb = lfsr_fb  ~^ qi[i];
1035
        end
1036
    end
1037
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1038
   always @ (qi)
1039
   begin
1040
        case (length)
1041
         2: polynom_rew = 32'b11;
1042
         3: polynom_rew = 32'b110;
1043
         4: polynom_rew = 32'b1100;
1044
         5: polynom_rew = 32'b10100;
1045
         6: polynom_rew = 32'b110000;
1046
         7: polynom_rew = 32'b1100000;
1047
         8: polynom_rew = 32'b10111000;
1048
         9: polynom_rew = 32'b100010000;
1049
        10: polynom_rew = 32'b1001000000;
1050
        11: polynom_rew = 32'b10100000000;
1051
        12: polynom_rew = 32'b100000101001;
1052
        13: polynom_rew = 32'b1000000001100;
1053
        14: polynom_rew = 32'b10000000010101;
1054
        15: polynom_rew = 32'b110000000000000;
1055
        16: polynom_rew = 32'b1101000000001000;
1056
        17: polynom_rew = 32'b10010000000000000;
1057
        18: polynom_rew = 32'b100000010000000000;
1058
        19: polynom_rew = 32'b1000000000000100011;
1059
        20: polynom_rew = 32'b10000010000000000000;
1060
        21: polynom_rew = 32'b101000000000000000000;
1061
        22: polynom_rew = 32'b1100000000000000000000;
1062
        23: polynom_rew = 32'b10000100000000000000000;
1063
        24: polynom_rew = 32'b111000010000000000000000;
1064
        25: polynom_rew = 32'b1001000000000000000000000;
1065
        26: polynom_rew = 32'b10000000000000000000100011;
1066
        27: polynom_rew = 32'b100000000000000000000010011;
1067
        28: polynom_rew = 32'b1100100000000000000000000000;
1068
        29: polynom_rew = 32'b10100000000000000000000000000;
1069
        30: polynom_rew = 32'b100000000000000000000000101001;
1070
        31: polynom_rew = 32'b1001000000000000000000000000000;
1071
        32: polynom_rew = 32'b10000000001000000000000000000011;
1072
        default: polynom_rew = 32'b0;
1073
        endcase
1074
        // rotate left
1075
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
1076
        lfsr_fb_rew = qi[length];
1077
        for (i=length-1; i>=1; i=i-1) begin
1078
            if (polynom_rew[i])
1079
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
1080
        end
1081
    end
1082
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
1083
   assign q_next = rew ? q_next_rew : q_next_fw;
1084
   always @ (posedge clk or posedge rst)
1085
     if (rst)
1086
       qi <= {length{1'b0}};
1087
     else
1088
     if (cke)
1089
       qi <= q_next;
1090
    always @ (posedge clk or posedge rst)
1091
    if (rst)
1092
        level1 <= 1'b0;
1093
    else
1094
    if (cke)
1095
    if (q_next == level1_value)
1096
        level1 <= 1'b1;
1097
    else if (qi == level1_value & rew)
1098
        level1 <= 1'b0;
1099
endmodule
1100
//////////////////////////////////////////////////////////////////////
1101
////                                                              ////
1102
////  Versatile counter                                           ////
1103
////                                                              ////
1104
////  Description                                                 ////
1105
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1106
////  counter                                                     ////
1107
////                                                              ////
1108
////  To Do:                                                      ////
1109
////   - add LFSR with more taps                                  ////
1110
////                                                              ////
1111
////  Author(s):                                                  ////
1112
////      - Michael Unneback, unneback@opencores.org              ////
1113
////        ORSoC AB                                              ////
1114
////                                                              ////
1115
//////////////////////////////////////////////////////////////////////
1116
////                                                              ////
1117
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1118
////                                                              ////
1119
//// This source file may be used and distributed without         ////
1120
//// restriction provided that this copyright statement is not    ////
1121
//// removed from the file and that any derivative work contains  ////
1122
//// the original copyright notice and the associated disclaimer. ////
1123
////                                                              ////
1124
//// This source file is free software; you can redistribute it   ////
1125
//// and/or modify it under the terms of the GNU Lesser General   ////
1126
//// Public License as published by the Free Software Foundation; ////
1127
//// either version 2.1 of the License, or (at your option) any   ////
1128
//// later version.                                               ////
1129
////                                                              ////
1130
//// This source is distributed in the hope that it will be       ////
1131
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1132
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1133
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1134
//// details.                                                     ////
1135
////                                                              ////
1136
//// You should have received a copy of the GNU Lesser General    ////
1137
//// Public License along with this source; if not, download it   ////
1138
//// from http://www.opencores.org/lgpl.shtml                     ////
1139
////                                                              ////
1140
//////////////////////////////////////////////////////////////////////
1141
// GRAY counter
1142 18 unneback
module vl_cnt_gray ( q, rst, clk);
1143 6 unneback
   parameter length = 4;
1144
   output reg [length:1] q;
1145
   input rst;
1146
   input clk;
1147
   parameter clear_value = 0;
1148
   parameter set_value = 1;
1149
   parameter wrap_value = 8;
1150
   parameter level1_value = 15;
1151
   reg  [length:1] qi;
1152
   wire [length:1] q_next;
1153
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1154
   always @ (posedge clk or posedge rst)
1155
     if (rst)
1156
       qi <= {length{1'b0}};
1157
     else
1158
       qi <= q_next;
1159
   always @ (posedge clk or posedge rst)
1160
     if (rst)
1161
       q <= {length{1'b0}};
1162
     else
1163
         q <= (q_next>>1) ^ q_next;
1164
endmodule
1165
//////////////////////////////////////////////////////////////////////
1166
////                                                              ////
1167
////  Versatile counter                                           ////
1168
////                                                              ////
1169
////  Description                                                 ////
1170
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1171
////  counter                                                     ////
1172
////                                                              ////
1173
////  To Do:                                                      ////
1174
////   - add LFSR with more taps                                  ////
1175
////                                                              ////
1176
////  Author(s):                                                  ////
1177
////      - Michael Unneback, unneback@opencores.org              ////
1178
////        ORSoC AB                                              ////
1179
////                                                              ////
1180
//////////////////////////////////////////////////////////////////////
1181
////                                                              ////
1182
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1183
////                                                              ////
1184
//// This source file may be used and distributed without         ////
1185
//// restriction provided that this copyright statement is not    ////
1186
//// removed from the file and that any derivative work contains  ////
1187
//// the original copyright notice and the associated disclaimer. ////
1188
////                                                              ////
1189
//// This source file is free software; you can redistribute it   ////
1190
//// and/or modify it under the terms of the GNU Lesser General   ////
1191
//// Public License as published by the Free Software Foundation; ////
1192
//// either version 2.1 of the License, or (at your option) any   ////
1193
//// later version.                                               ////
1194
////                                                              ////
1195
//// This source is distributed in the hope that it will be       ////
1196
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1197
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1198
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1199
//// details.                                                     ////
1200
////                                                              ////
1201
//// You should have received a copy of the GNU Lesser General    ////
1202
//// Public License along with this source; if not, download it   ////
1203
//// from http://www.opencores.org/lgpl.shtml                     ////
1204
////                                                              ////
1205
//////////////////////////////////////////////////////////////////////
1206
// GRAY counter
1207 18 unneback
module vl_cnt_gray_ce ( cke, q, rst, clk);
1208 6 unneback
   parameter length = 4;
1209
   input cke;
1210
   output reg [length:1] q;
1211
   input rst;
1212
   input clk;
1213
   parameter clear_value = 0;
1214
   parameter set_value = 1;
1215
   parameter wrap_value = 8;
1216
   parameter level1_value = 15;
1217
   reg  [length:1] qi;
1218
   wire [length:1] q_next;
1219
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1220
   always @ (posedge clk or posedge rst)
1221
     if (rst)
1222
       qi <= {length{1'b0}};
1223
     else
1224
     if (cke)
1225
       qi <= q_next;
1226
   always @ (posedge clk or posedge rst)
1227
     if (rst)
1228
       q <= {length{1'b0}};
1229
     else
1230
       if (cke)
1231
         q <= (q_next>>1) ^ q_next;
1232
endmodule
1233
//////////////////////////////////////////////////////////////////////
1234
////                                                              ////
1235
////  Versatile counter                                           ////
1236
////                                                              ////
1237
////  Description                                                 ////
1238
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1239
////  counter                                                     ////
1240
////                                                              ////
1241
////  To Do:                                                      ////
1242
////   - add LFSR with more taps                                  ////
1243
////                                                              ////
1244
////  Author(s):                                                  ////
1245
////      - Michael Unneback, unneback@opencores.org              ////
1246
////        ORSoC AB                                              ////
1247
////                                                              ////
1248
//////////////////////////////////////////////////////////////////////
1249
////                                                              ////
1250
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1251
////                                                              ////
1252
//// This source file may be used and distributed without         ////
1253
//// restriction provided that this copyright statement is not    ////
1254
//// removed from the file and that any derivative work contains  ////
1255
//// the original copyright notice and the associated disclaimer. ////
1256
////                                                              ////
1257
//// This source file is free software; you can redistribute it   ////
1258
//// and/or modify it under the terms of the GNU Lesser General   ////
1259
//// Public License as published by the Free Software Foundation; ////
1260
//// either version 2.1 of the License, or (at your option) any   ////
1261
//// later version.                                               ////
1262
////                                                              ////
1263
//// This source is distributed in the hope that it will be       ////
1264
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1265
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1266
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1267
//// details.                                                     ////
1268
////                                                              ////
1269
//// You should have received a copy of the GNU Lesser General    ////
1270
//// Public License along with this source; if not, download it   ////
1271
//// from http://www.opencores.org/lgpl.shtml                     ////
1272
////                                                              ////
1273
//////////////////////////////////////////////////////////////////////
1274
// GRAY counter
1275 18 unneback
module vl_cnt_gray_ce_bin ( cke, q, q_bin, rst, clk);
1276 6 unneback
   parameter length = 4;
1277
   input cke;
1278
   output reg [length:1] q;
1279
   output [length:1] q_bin;
1280
   input rst;
1281
   input clk;
1282
   parameter clear_value = 0;
1283
   parameter set_value = 1;
1284
   parameter wrap_value = 8;
1285
   parameter level1_value = 15;
1286
   reg  [length:1] qi;
1287
   wire [length:1] q_next;
1288
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1289
   always @ (posedge clk or posedge rst)
1290
     if (rst)
1291
       qi <= {length{1'b0}};
1292
     else
1293
     if (cke)
1294
       qi <= q_next;
1295
   always @ (posedge clk or posedge rst)
1296
     if (rst)
1297
       q <= {length{1'b0}};
1298
     else
1299
       if (cke)
1300
         q <= (q_next>>1) ^ q_next;
1301
   assign q_bin = qi;
1302
endmodule
1303
//////////////////////////////////////////////////////////////////////
1304
////                                                              ////
1305
////  Versatile library, counters                                 ////
1306
////                                                              ////
1307
////  Description                                                 ////
1308
////  counters                                                    ////
1309
////                                                              ////
1310
////                                                              ////
1311
////  To Do:                                                      ////
1312
////   - add more counters                                        ////
1313
////                                                              ////
1314
////  Author(s):                                                  ////
1315
////      - Michael Unneback, unneback@opencores.org              ////
1316
////        ORSoC AB                                              ////
1317
////                                                              ////
1318
//////////////////////////////////////////////////////////////////////
1319
////                                                              ////
1320
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1321
////                                                              ////
1322
//// This source file may be used and distributed without         ////
1323
//// restriction provided that this copyright statement is not    ////
1324
//// removed from the file and that any derivative work contains  ////
1325
//// the original copyright notice and the associated disclaimer. ////
1326
////                                                              ////
1327
//// This source file is free software; you can redistribute it   ////
1328
//// and/or modify it under the terms of the GNU Lesser General   ////
1329
//// Public License as published by the Free Software Foundation; ////
1330
//// either version 2.1 of the License, or (at your option) any   ////
1331
//// later version.                                               ////
1332
////                                                              ////
1333
//// This source is distributed in the hope that it will be       ////
1334
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1335
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1336
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1337
//// details.                                                     ////
1338
////                                                              ////
1339
//// You should have received a copy of the GNU Lesser General    ////
1340
//// Public License along with this source; if not, download it   ////
1341
//// from http://www.opencores.org/lgpl.shtml                     ////
1342
////                                                              ////
1343
//////////////////////////////////////////////////////////////////////
1344 18 unneback
module vl_cnt_shreg_wrap ( q, rst, clk);
1345 6 unneback
   parameter length = 4;
1346
   output reg [0:length-1] q;
1347
   input rst;
1348
   input clk;
1349
    always @ (posedge clk or posedge rst)
1350
    if (rst)
1351
        q <= {1'b1,{length-1{1'b0}}};
1352
    else
1353
        q <= {q[length-1],q[0:length-2]};
1354
endmodule
1355 18 unneback
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
1356 6 unneback
   parameter length = 4;
1357
   input cke;
1358
   output reg [0:length-1] q;
1359
   input rst;
1360
   input clk;
1361
    always @ (posedge clk or posedge rst)
1362
    if (rst)
1363
        q <= {1'b1,{length-1{1'b0}}};
1364
    else
1365
        if (cke)
1366
            q <= {q[length-1],q[0:length-2]};
1367
endmodule
1368 18 unneback
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
1369 6 unneback
   parameter length = 4;
1370
   input cke, clear;
1371
   output reg [0:length-1] q;
1372
   input rst;
1373
   input clk;
1374
    always @ (posedge clk or posedge rst)
1375
    if (rst)
1376
        q <= {1'b1,{length-1{1'b0}}};
1377
    else
1378
        if (cke)
1379
            if (clear)
1380
                q <= {1'b1,{length-1{1'b0}}};
1381
            else
1382
                q <= q >> 1;
1383
endmodule
1384 18 unneback
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
1385 6 unneback
   parameter length = 4;
1386
   input cke, clear;
1387
   output reg [0:length-1] q;
1388
   input rst;
1389
   input clk;
1390
    always @ (posedge clk or posedge rst)
1391
    if (rst)
1392
        q <= {1'b1,{length-1{1'b0}}};
1393
    else
1394
        if (cke)
1395
            if (clear)
1396
                q <= {1'b1,{length-1{1'b0}}};
1397
            else
1398
            q <= {q[length-1],q[0:length-2]};
1399
endmodule
1400
//////////////////////////////////////////////////////////////////////
1401
////                                                              ////
1402
////  Versatile library, memories                                 ////
1403
////                                                              ////
1404
////  Description                                                 ////
1405
////  memories                                                    ////
1406
////                                                              ////
1407
////                                                              ////
1408
////  To Do:                                                      ////
1409
////   - add more memory types                                    ////
1410
////                                                              ////
1411
////  Author(s):                                                  ////
1412
////      - Michael Unneback, unneback@opencores.org              ////
1413
////        ORSoC AB                                              ////
1414
////                                                              ////
1415
//////////////////////////////////////////////////////////////////////
1416
////                                                              ////
1417
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1418
////                                                              ////
1419
//// This source file may be used and distributed without         ////
1420
//// restriction provided that this copyright statement is not    ////
1421
//// removed from the file and that any derivative work contains  ////
1422
//// the original copyright notice and the associated disclaimer. ////
1423
////                                                              ////
1424
//// This source file is free software; you can redistribute it   ////
1425
//// and/or modify it under the terms of the GNU Lesser General   ////
1426
//// Public License as published by the Free Software Foundation; ////
1427
//// either version 2.1 of the License, or (at your option) any   ////
1428
//// later version.                                               ////
1429
////                                                              ////
1430
//// This source is distributed in the hope that it will be       ////
1431
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1432
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1433
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1434
//// details.                                                     ////
1435
////                                                              ////
1436
//// You should have received a copy of the GNU Lesser General    ////
1437
//// Public License along with this source; if not, download it   ////
1438
//// from http://www.opencores.org/lgpl.shtml                     ////
1439
////                                                              ////
1440
//////////////////////////////////////////////////////////////////////
1441
/// ROM
1442 7 unneback
module vl_rom_init ( adr, q, clk);
1443
   parameter data_width = 32;
1444
   parameter addr_width = 8;
1445
   input [(addr_width-1):0]       adr;
1446
   output reg [(data_width-1):0] q;
1447
   input                         clk;
1448
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
1449
   parameter memory_file = "vl_rom.vmem";
1450
   initial
1451
     begin
1452
        $readmemh(memory_file, rom);
1453
     end
1454
   always @ (posedge clk)
1455
     q <= rom[adr];
1456
endmodule
1457 14 unneback
/*
1458 7 unneback
module vl_rom ( adr, q, clk);
1459 6 unneback
parameter data_width = 32;
1460
parameter addr_width = 4;
1461
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
1462
    {32'h18000000},
1463
    {32'hA8200000},
1464
    {32'hA8200000},
1465
    {32'hA8200000},
1466
    {32'h44003000},
1467
    {32'h15000000},
1468
    {32'h15000000},
1469
    {32'h15000000},
1470
    {32'h15000000},
1471
    {32'h15000000},
1472
    {32'h15000000},
1473
    {32'h15000000},
1474
    {32'h15000000},
1475
    {32'h15000000},
1476
    {32'h15000000},
1477
    {32'h15000000}};
1478 7 unneback
input [addr_width-1:0] adr;
1479 6 unneback
output reg [data_width-1:0] q;
1480
input clk;
1481
always @ (posedge clk)
1482 7 unneback
    q <= data[adr];
1483 6 unneback
endmodule
1484 14 unneback
*/
1485 6 unneback
// Single port RAM
1486
module vl_ram ( d, adr, we, q, clk);
1487
   parameter data_width = 32;
1488
   parameter addr_width = 8;
1489
   input [(data_width-1):0]      d;
1490
   input [(addr_width-1):0]       adr;
1491
   input                         we;
1492 7 unneback
   output reg [(data_width-1):0] q;
1493 6 unneback
   input                         clk;
1494
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
1495 7 unneback
   parameter init = 0;
1496
   parameter memory_file = "vl_ram.vmem";
1497
   generate if (init) begin : init_mem
1498
   initial
1499
     begin
1500
        $readmemh(memory_file, ram);
1501
     end
1502
   end
1503
   endgenerate
1504 6 unneback
   always @ (posedge clk)
1505
   begin
1506
   if (we)
1507
     ram[adr] <= d;
1508
   q <= ram[adr];
1509
   end
1510
endmodule
1511 7 unneback
module vl_ram_be ( d, adr, be, we, q, clk);
1512
   parameter data_width = 32;
1513
   parameter addr_width = 8;
1514
   input [(data_width-1):0]      d;
1515
   input [(addr_width-1):0]       adr;
1516
   input [(addr_width/4)-1:0]    be;
1517
   input                         we;
1518
   output reg [(data_width-1):0] q;
1519
   input                         clk;
1520
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
1521
   parameter init = 0;
1522
   parameter memory_file = "vl_ram.vmem";
1523
   generate if (init) begin : init_mem
1524
   initial
1525
     begin
1526
        $readmemh(memory_file, ram);
1527
     end
1528
   end
1529
   endgenerate
1530
   genvar i;
1531
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
1532
      always @ (posedge clk)
1533
      if (we & be[i])
1534
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
1535
   end
1536
   endgenerate
1537
   always @ (posedge clk)
1538
      q <= ram[adr];
1539
endmodule
1540 6 unneback
// Dual port RAM
1541
// ACTEL FPGA should not use logic to handle rw collision
1542 7 unneback
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1543 6 unneback
   parameter data_width = 32;
1544
   parameter addr_width = 8;
1545
   input [(data_width-1):0]      d_a;
1546
   input [(addr_width-1):0]       adr_a;
1547
   input [(addr_width-1):0]       adr_b;
1548
   input                         we_a;
1549
   output [(data_width-1):0]      q_b;
1550
   input                         clk_a, clk_b;
1551
   reg [(addr_width-1):0]         adr_b_reg;
1552
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
1553 7 unneback
   parameter init = 0;
1554
   parameter memory_file = "vl_ram.vmem";
1555
   generate if (init) begin : init_mem
1556
   initial
1557
     begin
1558
        $readmemh(memory_file, ram);
1559
     end
1560
   end
1561
   endgenerate
1562 6 unneback
   always @ (posedge clk_a)
1563
   if (we_a)
1564
     ram[adr_a] <= d_a;
1565
   always @ (posedge clk_b)
1566
   adr_b_reg <= adr_b;
1567
   assign q_b = ram[adr_b_reg];
1568
endmodule
1569 7 unneback
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1570 6 unneback
   parameter data_width = 32;
1571
   parameter addr_width = 8;
1572
   input [(data_width-1):0]      d_a;
1573
   input [(addr_width-1):0]       adr_a;
1574
   input [(addr_width-1):0]       adr_b;
1575
   input                         we_a;
1576
   output [(data_width-1):0]      q_b;
1577
   output reg [(data_width-1):0] q_a;
1578
   input                         clk_a, clk_b;
1579
   reg [(data_width-1):0]         q_b;
1580
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
1581 7 unneback
   parameter init = 0;
1582
   parameter memory_file = "vl_ram.vmem";
1583
   generate if (init) begin : init_mem
1584
   initial
1585
     begin
1586
        $readmemh(memory_file, ram);
1587
     end
1588
   end
1589
   endgenerate
1590 6 unneback
   always @ (posedge clk_a)
1591
     begin
1592
        q_a <= ram[adr_a];
1593
        if (we_a)
1594
             ram[adr_a] <= d_a;
1595
     end
1596
   always @ (posedge clk_b)
1597
          q_b <= ram[adr_b];
1598
endmodule
1599 7 unneback
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
1600 6 unneback
   parameter data_width = 32;
1601
   parameter addr_width = 8;
1602
   input [(data_width-1):0]      d_a;
1603
   input [(addr_width-1):0]       adr_a;
1604
   input [(addr_width-1):0]       adr_b;
1605
   input                         we_a;
1606
   output [(data_width-1):0]      q_b;
1607
   input [(data_width-1):0]       d_b;
1608
   output reg [(data_width-1):0] q_a;
1609
   input                         we_b;
1610
   input                         clk_a, clk_b;
1611
   reg [(data_width-1):0]         q_b;
1612
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
1613 7 unneback
   parameter init = 0;
1614
   parameter memory_file = "vl_ram.vmem";
1615
   generate if (init) begin : init_mem
1616
   initial
1617
     begin
1618
        $readmemh(memory_file, ram);
1619
     end
1620
   end
1621
   endgenerate
1622 6 unneback
   always @ (posedge clk_a)
1623
     begin
1624
        q_a <= ram[adr_a];
1625
        if (we_a)
1626
             ram[adr_a] <= d_a;
1627
     end
1628
   always @ (posedge clk_b)
1629
     begin
1630
        q_b <= ram[adr_b];
1631
        if (we_b)
1632
          ram[adr_b] <= d_b;
1633
     end
1634
endmodule
1635
// Content addresable memory, CAM
1636
// FIFO
1637
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
1638 11 unneback
   parameter addr_width = 4;
1639
   parameter N = addr_width-1;
1640 6 unneback
   parameter Q1 = 2'b00;
1641
   parameter Q2 = 2'b01;
1642
   parameter Q3 = 2'b11;
1643
   parameter Q4 = 2'b10;
1644
   parameter going_empty = 1'b0;
1645
   parameter going_full  = 1'b1;
1646
   input [N:0]  wptr, rptr;
1647 14 unneback
   output       fifo_empty;
1648 6 unneback
   output       fifo_full;
1649
   input        wclk, rclk, rst;
1650
   wire direction;
1651
   reg  direction_set, direction_clr;
1652
   wire async_empty, async_full;
1653
   wire fifo_full2;
1654 14 unneback
   wire fifo_empty2;
1655 6 unneback
   // direction_set
1656
   always @ (wptr[N:N-1] or rptr[N:N-1])
1657
     case ({wptr[N:N-1],rptr[N:N-1]})
1658
       {Q1,Q2} : direction_set <= 1'b1;
1659
       {Q2,Q3} : direction_set <= 1'b1;
1660
       {Q3,Q4} : direction_set <= 1'b1;
1661
       {Q4,Q1} : direction_set <= 1'b1;
1662
       default : direction_set <= 1'b0;
1663
     endcase
1664
   // direction_clear
1665
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
1666
     if (rst)
1667
       direction_clr <= 1'b1;
1668
     else
1669
       case ({wptr[N:N-1],rptr[N:N-1]})
1670
         {Q2,Q1} : direction_clr <= 1'b1;
1671
         {Q3,Q2} : direction_clr <= 1'b1;
1672
         {Q4,Q3} : direction_clr <= 1'b1;
1673
         {Q1,Q4} : direction_clr <= 1'b1;
1674
         default : direction_clr <= 1'b0;
1675
       endcase
1676 18 unneback
    vl_dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
1677 6 unneback
   assign async_empty = (wptr == rptr) && (direction==going_empty);
1678
   assign async_full  = (wptr == rptr) && (direction==going_full);
1679 18 unneback
    vl_dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
1680
    vl_dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
1681 6 unneback
/*
1682
   always @ (posedge wclk or posedge rst or posedge async_full)
1683
     if (rst)
1684
       {fifo_full, fifo_full2} <= 2'b00;
1685
     else if (async_full)
1686
       {fifo_full, fifo_full2} <= 2'b11;
1687
     else
1688
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
1689
*/
1690 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
1691 6 unneback
     if (async_empty)
1692
       {fifo_empty, fifo_empty2} <= 2'b11;
1693
     else
1694 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
1695 18 unneback
    vl_dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
1696
    vl_dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
1697 6 unneback
endmodule // async_comp
1698
module vl_fifo_1r1w_async (
1699
    d, wr, fifo_full, wr_clk, wr_rst,
1700
    q, rd, fifo_empty, rd_clk, rd_rst
1701
    );
1702
parameter data_width = 18;
1703
parameter addr_width = 4;
1704
// write side
1705
input  [data_width-1:0] d;
1706
input                   wr;
1707
output                  fifo_full;
1708
input                   wr_clk;
1709
input                   wr_rst;
1710
// read side
1711
output [data_width-1:0] q;
1712
input                   rd;
1713
output                  fifo_empty;
1714
input                   rd_clk;
1715
input                   rd_rst;
1716
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
1717 21 unneback
/*
1718 6 unneback
vl_fifo_1r1w_async (
1719
    d, wr, fifo_full, wr_clk, wr_rst,
1720
    q, rd, fifo_empty, rd_clk, rd_rst
1721
    );
1722 21 unneback
*/
1723 18 unneback
vl_cnt_gray_ce_bin
1724 6 unneback
    # ( .length(addr_width))
1725
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
1726 18 unneback
vl_cnt_gray_ce_bin
1727 6 unneback
    # (.length(addr_width))
1728
    fifo_rd_adr( .cke(wr), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_rst));
1729 7 unneback
vl_dpram_1r1w
1730 6 unneback
    # (.data_width(data_width), .addr_width(addr_width))
1731
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
1732
vl_fifo_cmp_async
1733
    # (.addr_width(addr_width))
1734
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
1735
endmodule
1736 8 unneback
module vl_fifo_2r2w_async (
1737 6 unneback
    // a side
1738
    a_d, a_wr, a_fifo_full,
1739
    a_q, a_rd, a_fifo_empty,
1740
    a_clk, a_rst,
1741
    // b side
1742
    b_d, b_wr, b_fifo_full,
1743
    b_q, b_rd, b_fifo_empty,
1744
    b_clk, b_rst
1745
    );
1746
parameter data_width = 18;
1747
parameter addr_width = 4;
1748
// a side
1749
input  [data_width-1:0] a_d;
1750
input                   a_wr;
1751
output                  a_fifo_full;
1752
output [data_width-1:0] a_q;
1753
input                   a_rd;
1754
output                  a_fifo_empty;
1755
input                   a_clk;
1756
input                   a_rst;
1757
// b side
1758
input  [data_width-1:0] b_d;
1759
input                   b_wr;
1760
output                  b_fifo_full;
1761
output [data_width-1:0] b_q;
1762
input                   b_rd;
1763
output                  b_fifo_empty;
1764
input                   b_clk;
1765
input                   b_rst;
1766
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
1767
vl_fifo_1r1w_async_a (
1768
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
1769
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
1770
    );
1771
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
1772
vl_fifo_1r1w_async_b (
1773
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
1774
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
1775
    );
1776
endmodule
1777 8 unneback
module vl_fifo_2r2w_async_simplex (
1778 6 unneback
    // a side
1779
    a_d, a_wr, a_fifo_full,
1780
    a_q, a_rd, a_fifo_empty,
1781
    a_clk, a_rst,
1782
    // b side
1783
    b_d, b_wr, b_fifo_full,
1784
    b_q, b_rd, b_fifo_empty,
1785
    b_clk, b_rst
1786
    );
1787
parameter data_width = 18;
1788
parameter addr_width = 4;
1789
// a side
1790
input  [data_width-1:0] a_d;
1791
input                   a_wr;
1792
output                  a_fifo_full;
1793
output [data_width-1:0] a_q;
1794
input                   a_rd;
1795
output                  a_fifo_empty;
1796
input                   a_clk;
1797
input                   a_rst;
1798
// b side
1799
input  [data_width-1:0] b_d;
1800
input                   b_wr;
1801
output                  b_fifo_full;
1802
output [data_width-1:0] b_q;
1803
input                   b_rd;
1804
output                  b_fifo_empty;
1805
input                   b_clk;
1806
input                   b_rst;
1807
// adr_gen
1808
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
1809
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
1810
// dpram
1811
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
1812 18 unneback
vl_cnt_gray_ce_bin
1813 6 unneback
    # ( .length(addr_width))
1814
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
1815 18 unneback
vl_cnt_gray_ce_bin
1816 6 unneback
    # (.length(addr_width))
1817
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
1818 18 unneback
vl_cnt_gray_ce_bin
1819 6 unneback
    # ( .length(addr_width))
1820
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
1821 18 unneback
vl_cnt_gray_ce_bin
1822 6 unneback
    # (.length(addr_width))
1823
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
1824
// mux read or write adr to DPRAM
1825
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
1826
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
1827 11 unneback
vl_dpram_2r2w
1828 6 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
1829
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
1830
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
1831 11 unneback
vl_fifo_cmp_async
1832 6 unneback
    # (.addr_width(addr_width))
1833
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
1834 11 unneback
vl_fifo_cmp_async
1835 6 unneback
    # (.addr_width(addr_width))
1836
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
1837
endmodule
1838 12 unneback
//////////////////////////////////////////////////////////////////////
1839
////                                                              ////
1840
////  Versatile library, wishbone stuff                           ////
1841
////                                                              ////
1842
////  Description                                                 ////
1843
////  Wishbone compliant modules                                  ////
1844
////                                                              ////
1845
////                                                              ////
1846
////  To Do:                                                      ////
1847
////   -                                                          ////
1848
////                                                              ////
1849
////  Author(s):                                                  ////
1850
////      - Michael Unneback, unneback@opencores.org              ////
1851
////        ORSoC AB                                              ////
1852
////                                                              ////
1853
//////////////////////////////////////////////////////////////////////
1854
////                                                              ////
1855
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1856
////                                                              ////
1857
//// This source file may be used and distributed without         ////
1858
//// restriction provided that this copyright statement is not    ////
1859
//// removed from the file and that any derivative work contains  ////
1860
//// the original copyright notice and the associated disclaimer. ////
1861
////                                                              ////
1862
//// This source file is free software; you can redistribute it   ////
1863
//// and/or modify it under the terms of the GNU Lesser General   ////
1864
//// Public License as published by the Free Software Foundation; ////
1865
//// either version 2.1 of the License, or (at your option) any   ////
1866
//// later version.                                               ////
1867
////                                                              ////
1868
//// This source is distributed in the hope that it will be       ////
1869
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1870
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1871
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1872
//// details.                                                     ////
1873
////                                                              ////
1874
//// You should have received a copy of the GNU Lesser General    ////
1875
//// Public License along with this source; if not, download it   ////
1876
//// from http://www.opencores.org/lgpl.shtml                     ////
1877
////                                                              ////
1878
//////////////////////////////////////////////////////////////////////
1879
// async wb3 - wb3 bridge
1880
`timescale 1ns/1ns
1881 18 unneback
module vl_wb3wb3_bridge (
1882 12 unneback
        // wishbone slave side
1883
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
1884
        // wishbone master side
1885
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
1886
input [31:0] wbs_dat_i;
1887
input [31:2] wbs_adr_i;
1888
input [3:0]  wbs_sel_i;
1889
input [1:0]  wbs_bte_i;
1890
input [2:0]  wbs_cti_i;
1891
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
1892
output [31:0] wbs_dat_o;
1893 14 unneback
output wbs_ack_o;
1894 12 unneback
input wbs_clk, wbs_rst;
1895
output [31:0] wbm_dat_o;
1896
output reg [31:2] wbm_adr_o;
1897
output [3:0]  wbm_sel_o;
1898
output reg [1:0]  wbm_bte_o;
1899
output reg [2:0]  wbm_cti_o;
1900 14 unneback
output reg wbm_we_o;
1901
output wbm_cyc_o;
1902 12 unneback
output wbm_stb_o;
1903
input [31:0]  wbm_dat_i;
1904
input wbm_ack_i;
1905
input wbm_clk, wbm_rst;
1906
parameter addr_width = 4;
1907
// bte
1908
parameter linear       = 2'b00;
1909
parameter wrap4        = 2'b01;
1910
parameter wrap8        = 2'b10;
1911
parameter wrap16       = 2'b11;
1912
// cti
1913
parameter classic      = 3'b000;
1914
parameter incburst     = 3'b010;
1915
parameter endofburst   = 3'b111;
1916
parameter wbs_adr  = 1'b0;
1917
parameter wbs_data = 1'b1;
1918
parameter wbm_adr0 = 2'b00;
1919
parameter wbm_adr1 = 2'b01;
1920
parameter wbm_data = 2'b10;
1921
reg [1:0] wbs_bte_reg;
1922
reg wbs;
1923
wire wbs_eoc_alert, wbm_eoc_alert;
1924
reg wbs_eoc, wbm_eoc;
1925
reg [1:0] wbm;
1926 14 unneback
wire [1:16] wbs_count, wbm_count;
1927 12 unneback
wire [35:0] a_d, a_q, b_d, b_q;
1928
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
1929
reg a_rd_reg;
1930
wire b_rd_adr, b_rd_data;
1931 14 unneback
wire b_rd_data_reg;
1932
wire [35:0] temp;
1933 12 unneback
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
1934
always @ (posedge wbs_clk or posedge wbs_rst)
1935
if (wbs_rst)
1936
        wbs_eoc <= 1'b0;
1937
else
1938
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
1939
                wbs_eoc <= wbs_bte_i==linear;
1940
        else if (wbs_eoc_alert & (a_rd | a_wr))
1941
                wbs_eoc <= 1'b1;
1942 18 unneback
vl_cnt_shreg_ce_clear # ( .length(16))
1943 12 unneback
    cnt0 (
1944
        .cke(wbs_ack_o),
1945
        .clear(wbs_eoc),
1946
        .q(wbs_count),
1947
        .rst(wbs_rst),
1948
        .clk(wbs_clk));
1949
always @ (posedge wbs_clk or posedge wbs_rst)
1950
if (wbs_rst)
1951
        wbs <= wbs_adr;
1952
else
1953
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & !a_fifo_full)
1954
                wbs <= wbs_data;
1955
        else if (wbs_eoc & wbs_ack_o)
1956
                wbs <= wbs_adr;
1957
// wbs FIFO
1958
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,wbs_bte_i,wbs_cti_i} : {wbs_dat_i,wbs_sel_i};
1959
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & !a_fifo_full :
1960
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
1961
              1'b0;
1962
assign a_rd = !a_fifo_empty;
1963
always @ (posedge wbs_clk or posedge wbs_rst)
1964
if (wbs_rst)
1965
        a_rd_reg <= 1'b0;
1966
else
1967
        a_rd_reg <= a_rd;
1968
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
1969
assign wbs_dat_o = a_q[35:4];
1970
always @ (posedge wbs_clk or posedge wbs_rst)
1971
if (wbs_rst)
1972 13 unneback
        wbs_bte_reg <= 2'b00;
1973 12 unneback
else
1974 13 unneback
        wbs_bte_reg <= wbs_bte_i;
1975 12 unneback
// wbm FIFO
1976
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
1977
always @ (posedge wbm_clk or posedge wbm_rst)
1978
if (wbm_rst)
1979
        wbm_eoc <= 1'b0;
1980
else
1981
        if (wbm==wbm_adr0 & !b_fifo_empty)
1982
                wbm_eoc <= b_q[4:3] == linear;
1983
        else if (wbm_eoc_alert & wbm_ack_i)
1984
                wbm_eoc <= 1'b1;
1985
always @ (posedge wbm_clk or posedge wbm_rst)
1986
if (wbm_rst)
1987
        wbm <= wbm_adr0;
1988
else
1989
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
1990
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
1991
        (wbm==wbm_adr1 & !wbm_we_o) |
1992
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
1993
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
1994
assign b_d = {wbm_dat_i,4'b1111};
1995
assign b_wr = !wbm_we_o & wbm_ack_i;
1996
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
1997
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
1998
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
1999
                   1'b0;
2000
assign b_rd = b_rd_adr | b_rd_data;
2001 18 unneback
vl_dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
2002
vl_dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
2003 12 unneback
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
2004 18 unneback
vl_cnt_shreg_ce_clear # ( .length(16))
2005 12 unneback
    cnt1 (
2006
        .cke(wbm_ack_i),
2007
        .clear(wbm_eoc),
2008
        .q(wbm_count),
2009
        .rst(wbm_rst),
2010
        .clk(wbm_clk));
2011
assign wbm_cyc_o = wbm==wbm_data;
2012
assign wbm_stb_o = (wbm==wbm_data & wbm_we_o) ? !b_fifo_empty :
2013
                   (wbm==wbm_data) ? 1'b1 :
2014
                   1'b0;
2015
always @ (posedge wbm_clk or posedge wbm_rst)
2016
if (wbm_rst)
2017
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
2018
else begin
2019
        if (wbm==wbm_adr0 & !b_fifo_empty)
2020
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
2021
        else if (wbm_eoc_alert & wbm_ack_i)
2022
                wbm_cti_o <= endofburst;
2023
end
2024
//async_fifo_dw_simplex_top
2025
vl_fifo_2r2w_async_simplex
2026
# ( .data_width(36), .addr_width(addr_width))
2027
fifo (
2028
    // a side
2029
    .a_d(a_d),
2030
    .a_wr(a_wr),
2031
    .a_fifo_full(a_fifo_full),
2032
    .a_q(a_q),
2033
    .a_rd(a_rd),
2034
    .a_fifo_empty(a_fifo_empty),
2035
    .a_clk(wbs_clk),
2036
    .a_rst(wbs_rst),
2037
    // b side
2038
    .b_d(b_d),
2039
    .b_wr(b_wr),
2040
    .b_fifo_full(b_fifo_full),
2041
    .b_q(b_q),
2042
    .b_rd(b_rd),
2043
    .b_fifo_empty(b_fifo_empty),
2044
    .b_clk(wbm_clk),
2045
    .b_rst(wbm_rst)
2046
    );
2047
endmodule
2048 17 unneback
// WB ROM
2049 18 unneback
module vl_wb_boot_rom (
2050 17 unneback
    wb_adr_i, wb_stb_i, wb_cyc_i,
2051 18 unneback
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
2052
    parameter adr_hi = 31;
2053
    parameter adr_lo = 28;
2054
    parameter adr_sel = 4'hf;
2055
    parameter addr_width = 5;
2056 17 unneback
`ifndef BOOT_ROM
2057
`define BOOT_ROM "boot_rom.v"
2058
`endif
2059 18 unneback
    input [adr_hi:2]    wb_adr_i;
2060
    input               wb_stb_i;
2061
    input               wb_cyc_i;
2062
    output [31:0]        wb_dat_o;
2063
    output              wb_ack_o;
2064
    output              hit_o;
2065
    input               wb_clk;
2066
    input               wb_rst;
2067
    wire hit;
2068
    reg [31:0] wb_dat;
2069
    reg wb_ack;
2070
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
2071 17 unneback
always @ (posedge wb_clk or posedge wb_rst)
2072
    if (wb_rst)
2073 18 unneback
        wb_dat <= 32'h15000000;
2074 17 unneback
    else
2075 18 unneback
         case (wb_adr_i[addr_width-1:2])
2076 17 unneback
`include `BOOT_ROM
2077
           /*
2078
            // Zero r0 and jump to 0x00000100
2079 18 unneback
 
2080
            1 : wb_dat <= 32'hA8200000;
2081
            2 : wb_dat <= 32'hA8C00100;
2082
            3 : wb_dat <= 32'h44003000;
2083
            4 : wb_dat <= 32'h15000000;
2084 17 unneback
            */
2085
           default:
2086 18 unneback
             wb_dat <= 32'h00000000;
2087 17 unneback
         endcase // case (wb_adr_i)
2088
always @ (posedge wb_clk or posedge wb_rst)
2089
    if (wb_rst)
2090 18 unneback
        wb_ack <= 1'b0;
2091 17 unneback
    else
2092 18 unneback
        wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
2093
assign hit_o = hit;
2094
assign wb_dat_o = wb_dat & {32{wb_ack}};
2095
assign wb_ack_o = wb_ack;
2096 17 unneback
endmodule
2097 18 unneback
//////////////////////////////////////////////////////////////////////
2098
////                                                              ////
2099
////  Arithmetic functions                                        ////
2100
////                                                              ////
2101
////  Description                                                 ////
2102
////  Arithmetic functions for ALU and DSP                        ////
2103
////                                                              ////
2104
////                                                              ////
2105
////  To Do:                                                      ////
2106
////   -                                                          ////
2107
////                                                              ////
2108
////  Author(s):                                                  ////
2109
////      - Michael Unneback, unneback@opencores.org              ////
2110
////        ORSoC AB                                              ////
2111
////                                                              ////
2112
//////////////////////////////////////////////////////////////////////
2113
////                                                              ////
2114
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2115
////                                                              ////
2116
//// This source file may be used and distributed without         ////
2117
//// restriction provided that this copyright statement is not    ////
2118
//// removed from the file and that any derivative work contains  ////
2119
//// the original copyright notice and the associated disclaimer. ////
2120
////                                                              ////
2121
//// This source file is free software; you can redistribute it   ////
2122
//// and/or modify it under the terms of the GNU Lesser General   ////
2123
//// Public License as published by the Free Software Foundation; ////
2124
//// either version 2.1 of the License, or (at your option) any   ////
2125
//// later version.                                               ////
2126
////                                                              ////
2127
//// This source is distributed in the hope that it will be       ////
2128
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2129
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2130
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2131
//// details.                                                     ////
2132
////                                                              ////
2133
//// You should have received a copy of the GNU Lesser General    ////
2134
//// Public License along with this source; if not, download it   ////
2135
//// from http://www.opencores.org/lgpl.shtml                     ////
2136
////                                                              ////
2137
//////////////////////////////////////////////////////////////////////
2138
// signed multiplication
2139
module vl_mults (a,b,p);
2140
parameter operand_a_width = 18;
2141
parameter operand_b_width = 18;
2142
parameter result_hi = 35;
2143
parameter result_lo = 0;
2144
input [operand_a_width-1:0] a;
2145
input [operand_b_width-1:0] b;
2146
output [result_hi:result_lo] p;
2147
wire signed [operand_a_width-1:0] ai;
2148
wire signed [operand_b_width-1:0] bi;
2149
wire signed [operand_a_width+operand_b_width-1:0] result;
2150
    assign ai = a;
2151
    assign bi = b;
2152
    assign result = ai * bi;
2153
    assign p = result[result_hi:result_lo];
2154
endmodule
2155
module vl_mults18x18 (a,b,p);
2156
input [17:0] a,b;
2157
output [35:0] p;
2158
vl_mult
2159
    # (.operand_a_width(18), .operand_b_width(18))
2160
    mult0 (.a(a), .b(b), .p(p));
2161
endmodule
2162
// unsigned multiplication
2163
module vl_mult (a,b,p);
2164
parameter operand_a_width = 18;
2165
parameter operand_b_width = 18;
2166
parameter result_hi = 35;
2167
parameter result_lo = 0;
2168
input [operand_a_width-1:0] a;
2169
input [operand_b_width-1:0] b;
2170
output [result_hi:result_hi] p;
2171
wire [operand_a_width+operand_b_width-1:0] result;
2172
    assign result = a * b;
2173
    assign p = result[result_hi:result_lo];
2174
endmodule
2175
// shift unit
2176
// supporting the following shift functions
2177
//   SLL
2178
//   SRL
2179
//   SRA
2180
module vl_shift_unit_32( din, s, dout, opcode);
2181
input [31:0] din; // data in operand
2182
input [4:0] s; // shift operand
2183
input [1:0] opcode;
2184
output [31:0] dout;
2185
parameter opcode_sll = 2'b00;
2186
//parameter opcode_srl = 2'b01;
2187
parameter opcode_sra = 2'b10;
2188
//parameter opcode_ror = 2'b11;
2189
wire sll, sra;
2190
assign sll = opcode == opcode_sll;
2191
assign sra = opcode == opcode_sra;
2192
wire [15:1] s1;
2193
wire [3:0] sign;
2194
wire [7:0] tmp [0:3];
2195
// first stage is multiplier based
2196
// shift operand as fractional 8.7
2197
assign s1[15] = sll & s[2:0]==3'd7;
2198
assign s1[14] = sll & s[2:0]==3'd6;
2199
assign s1[13] = sll & s[2:0]==3'd5;
2200
assign s1[12] = sll & s[2:0]==3'd4;
2201
assign s1[11] = sll & s[2:0]==3'd3;
2202
assign s1[10] = sll & s[2:0]==3'd2;
2203
assign s1[ 9] = sll & s[2:0]==3'd1;
2204
assign s1[ 8] = s[2:0]==3'd0;
2205
assign s1[ 7] = !sll & s[2:0]==3'd1;
2206
assign s1[ 6] = !sll & s[2:0]==3'd2;
2207
assign s1[ 5] = !sll & s[2:0]==3'd3;
2208
assign s1[ 4] = !sll & s[2:0]==3'd4;
2209
assign s1[ 3] = !sll & s[2:0]==3'd5;
2210
assign s1[ 2] = !sll & s[2:0]==3'd6;
2211
assign s1[ 1] = !sll & s[2:0]==3'd7;
2212
assign sign[3] = din[31] & sra;
2213
assign sign[2] = sign[3] & (&din[31:24]);
2214
assign sign[1] = sign[2] & (&din[23:16]);
2215
assign sign[0] = sign[1] & (&din[15:8]);
2216
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte3 ( .a({sign[3], {8{sign[3]}},din[31:24], din[23:16]}), .b({1'b0,s1}), .p(tmp[3]));
2217
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte2 ( .a({sign[2], din[31:24]  ,din[23:16],  din[15:8]}), .b({1'b0,s1}), .p(tmp[2]));
2218
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte1 ( .a({sign[1], din[23:16]  ,din[15:8],   din[7:0]}), .b({1'b0,s1}), .p(tmp[1]));
2219
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte0 ( .a({sign[0], din[15:8]   ,din[7:0],    8'h00}),      .b({1'b0,s1}), .p(tmp[0]));
2220
// second stage is multiplexer based
2221
// shift on byte level
2222
// mux byte 3
2223
assign dout[31:24] = (s[4:3]==2'b00) ? tmp[3] :
2224
                     (sll & s[4:3]==2'b01) ? tmp[2] :
2225
                     (sll & s[4:3]==2'b10) ? tmp[1] :
2226
                     (sll & s[4:3]==2'b11) ? tmp[0] :
2227
                     {8{sign[3]}};
2228
// mux byte 2
2229
assign dout[23:16] = (s[4:3]==2'b00) ? tmp[2] :
2230
                     (sll & s[4:3]==2'b01) ? tmp[1] :
2231
                     (sll & s[4:3]==2'b10) ? tmp[0] :
2232
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
2233
                     (s[4:3]==2'b01) ? tmp[3] :
2234
                     {8{sign[3]}};
2235
// mux byte 1
2236
assign dout[15:8]  = (s[4:3]==2'b00) ? tmp[1] :
2237
                     (sll & s[4:3]==2'b01) ? tmp[0] :
2238
                     (sll & s[4:3]==2'b10) ? {8{1'b0}} :
2239
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
2240
                     (s[4:3]==2'b01) ? tmp[2] :
2241
                     (s[4:3]==2'b10) ? tmp[3] :
2242
                     {8{sign[3]}};
2243
// mux byte 0
2244
assign dout[7:0]   = (s[4:3]==2'b00) ? tmp[0] :
2245
                     (sll) ?  {8{1'b0}}:
2246
                     (s[4:3]==2'b01) ? tmp[1] :
2247
                     (s[4:3]==2'b10) ? tmp[2] :
2248
                     tmp[3];
2249
endmodule
2250
// logic unit
2251
// supporting the following logic functions
2252
//    a and b
2253
//    a or  b
2254
//    a xor b
2255
//    not b
2256
module vl_logic_unit( a, b, result, opcode);
2257
parameter width = 32;
2258
parameter opcode_and = 2'b00;
2259
parameter opcode_or  = 2'b01;
2260
parameter opcode_xor = 2'b10;
2261
input [width-1:0] a,b;
2262
output [width-1:0] result;
2263
input [1:0] opcode;
2264
assign result = (opcode==opcode_and) ? a & b :
2265
                (opcode==opcode_or)  ? a | b :
2266
                (opcode==opcode_xor) ? a ^ b :
2267
                b;
2268
endmodule
2269
module vl_arith_unit ( a, b, c_in, add_sub, sign, result, c_out, z, ovfl);
2270
parameter width = 32;
2271
parameter opcode_add = 1'b0;
2272
parameter opcode_sub = 1'b1;
2273
input [width-1:0] a,b;
2274
input c_in, add_sub, sign;
2275
output [width-1:0] result;
2276
output c_out, z, ovfl;
2277
assign {c_out,result} = {(a[width-1] & sign),a} + ({a[width-1] & sign,b} ^ {(width+1){(add_sub==opcode_sub)}}) + {{(width-1){1'b0}},(c_in | (add_sub==opcode_sub))};
2278
assign z = (result=={width{1'b0}});
2279
assign ovfl = ( a[width-1] &  b[width-1] & ~result[width-1]) |
2280
               (~a[width-1] & ~b[width-1] &  result[width-1]);
2281
endmodule

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