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1 6 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
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////  Versatile library, clock and reset                          ////
4
////                                                              ////
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////  Description                                                 ////
6
////  Logic related to clock and reset                            ////
7
////                                                              ////
8
////                                                              ////
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////  To Do:                                                      ////
10
////   - add more different registers                             ////
11
////                                                              ////
12
////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
14
////        ORSoC AB                                              ////
15
////                                                              ////
16
//////////////////////////////////////////////////////////////////////
17
////                                                              ////
18
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
19
////                                                              ////
20
//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
36
////                                                              ////
37
//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
// Global buffer
43
// usage:
44
// use to enable global buffers for high fan out signals such as clock and reset
45
`timescale 1 ns/100 ps
46
// Version: 8.4 8.4.0.33
47
module gbuf(GL,CLK);
48
output GL;
49
input  CLK;
50
    wire GND;
51
    GND GND_1_net(.Y(GND));
52
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
53
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
54
endmodule
55
`timescale 1 ns/1 ns
56
module vl_gbuf ( i, o);
57
input i;
58
output o;
59
`ifdef SIM_GBUF
60
assign o=i;
61
`else
62
gbuf gbuf_i0 ( .CLK(i), .GL(o));
63
`endif
64
endmodule
65
 //ACTEL
66
// sync reset
67 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
68 6 unneback
// output active high global reset sync with two DFFs 
69
`timescale 1 ns/100 ps
70
module vl_sync_rst ( rst_n_i, rst_o, clk);
71
input rst_n_i, clk;
72
output rst_o;
73 18 unneback
reg [1:0] tmp;
74 6 unneback
always @ (posedge clk or negedge rst_n_i)
75
if (!rst_n_i)
76 17 unneback
        tmp <= 2'b11;
77 6 unneback
else
78 17 unneback
        tmp <= {1'b0,tmp[0]};
79
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
80 6 unneback
endmodule
81
// vl_pll
82 17 unneback
`timescale 1 ps/1 ps
83 6 unneback
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
84
parameter index = 0;
85
parameter number_of_clk = 1;
86 17 unneback
parameter period_time_0 = 20000;
87
parameter period_time_1 = 20000;
88
parameter period_time_2 = 20000;
89
parameter lock_delay = 2000000;
90 6 unneback
input clk_i, rst_n_i;
91
output lock;
92
output reg [0:number_of_clk-1] clk_o;
93
output [0:number_of_clk-1] rst_o;
94
`ifdef SIM_PLL
95
always
96
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
97
generate if (number_of_clk > 1)
98
always
99
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
100
endgenerate
101
generate if (number_of_clk > 2)
102
always
103
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
104
endgenerate
105
genvar i;
106
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
107
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
108
end
109
endgenerate
110
assign #lock_delay lock = rst_n_i;
111
endmodule
112
`else
113
generate if (number_of_clk==1 & index==0) begin
114
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
115
end
116
endgenerate // index==0
117
generate if (number_of_clk==1 & index==1) begin
118
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
119
end
120
endgenerate // index==1
121
generate if (number_of_clk==1 & index==2) begin
122
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
123
end
124
endgenerate // index==2
125
generate if (number_of_clk==1 & index==3) begin
126
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
127
end
128
endgenerate // index==0
129
generate if (number_of_clk==2 & index==0) begin
130
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
131
end
132
endgenerate // index==0
133
generate if (number_of_clk==2 & index==1) begin
134
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
135
end
136
endgenerate // index==1
137
generate if (number_of_clk==2 & index==2) begin
138
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
139
end
140
endgenerate // index==2
141
generate if (number_of_clk==2 & index==3) begin
142
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
143
end
144
endgenerate // index==0
145
generate if (number_of_clk==3 & index==0) begin
146
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
147
end
148
endgenerate // index==0
149
generate if (number_of_clk==3 & index==1) begin
150
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
151
end
152
endgenerate // index==1
153
generate if (number_of_clk==3 & index==2) begin
154
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
155
end
156
endgenerate // index==2
157
generate if (number_of_clk==3 & index==3) begin
158
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
159
end
160
endgenerate // index==0
161
genvar i;
162
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
163
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
164
end
165
endgenerate
166
endmodule
167
`endif
168
 //actel
169
//////////////////////////////////////////////////////////////////////
170
////                                                              ////
171
////  Versatile library, registers                                ////
172
////                                                              ////
173
////  Description                                                 ////
174
////  Different type of registers                                 ////
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////                                                              ////
176
////                                                              ////
177
////  To Do:                                                      ////
178
////   - add more different registers                             ////
179
////                                                              ////
180
////  Author(s):                                                  ////
181
////      - Michael Unneback, unneback@opencores.org              ////
182
////        ORSoC AB                                              ////
183
////                                                              ////
184
//////////////////////////////////////////////////////////////////////
185
////                                                              ////
186
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
187
////                                                              ////
188
//// This source file may be used and distributed without         ////
189
//// restriction provided that this copyright statement is not    ////
190
//// removed from the file and that any derivative work contains  ////
191
//// the original copyright notice and the associated disclaimer. ////
192
////                                                              ////
193
//// This source file is free software; you can redistribute it   ////
194
//// and/or modify it under the terms of the GNU Lesser General   ////
195
//// Public License as published by the Free Software Foundation; ////
196
//// either version 2.1 of the License, or (at your option) any   ////
197
//// later version.                                               ////
198
////                                                              ////
199
//// This source is distributed in the hope that it will be       ////
200
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
201
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
202
//// PURPOSE.  See the GNU Lesser General Public License for more ////
203
//// details.                                                     ////
204
////                                                              ////
205
//// You should have received a copy of the GNU Lesser General    ////
206
//// Public License along with this source; if not, download it   ////
207
//// from http://www.opencores.org/lgpl.shtml                     ////
208
////                                                              ////
209
//////////////////////////////////////////////////////////////////////
210 18 unneback
module vl_dff ( d, q, clk, rst);
211 6 unneback
        parameter width = 1;
212
        parameter reset_value = 0;
213
        input [width-1:0] d;
214
        input clk, rst;
215
        output reg [width-1:0] q;
216
        always @ (posedge clk or posedge rst)
217
        if (rst)
218
                q <= reset_value;
219
        else
220
                q <= d;
221
endmodule
222 18 unneback
module vl_dff_array ( d, q, clk, rst);
223 6 unneback
        parameter width = 1;
224
        parameter depth = 2;
225
        parameter reset_value = 1'b0;
226
        input [width-1:0] d;
227
        input clk, rst;
228
        output [width-1:0] q;
229
        reg  [0:depth-1] q_tmp [width-1:0];
230
        integer i;
231
        always @ (posedge clk or posedge rst)
232
        if (rst) begin
233
            for (i=0;i<depth;i=i+1)
234
                q_tmp[i] <= {width{reset_value}};
235
        end else begin
236
            q_tmp[0] <= d;
237
            for (i=1;i<depth;i=i+1)
238
                q_tmp[i] <= q_tmp[i-1];
239
        end
240
    assign q = q_tmp[depth-1];
241
endmodule
242 18 unneback
module vl_dff_ce ( d, ce, q, clk, rst);
243 6 unneback
        parameter width = 1;
244
        parameter reset_value = 0;
245
        input [width-1:0] d;
246
        input ce, clk, rst;
247
        output reg [width-1:0] q;
248
        always @ (posedge clk or posedge rst)
249
        if (rst)
250
                q <= reset_value;
251
        else
252
                if (ce)
253
                        q <= d;
254
endmodule
255 18 unneback
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
256 8 unneback
        parameter width = 1;
257
        parameter reset_value = 0;
258
        input [width-1:0] d;
259 10 unneback
        input ce, clear, clk, rst;
260 8 unneback
        output reg [width-1:0] q;
261
        always @ (posedge clk or posedge rst)
262
        if (rst)
263
            q <= reset_value;
264
        else
265
            if (ce)
266
                if (clear)
267
                    q <= {width{1'b0}};
268
                else
269
                    q <= d;
270
endmodule
271 24 unneback
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
272
        parameter width = 1;
273
        parameter reset_value = 0;
274
        input [width-1:0] d;
275
        input ce, set, clk, rst;
276
        output reg [width-1:0] q;
277
        always @ (posedge clk or posedge rst)
278
        if (rst)
279
            q <= reset_value;
280
        else
281
            if (ce)
282
                if (set)
283
                    q <= {width{1'b1}};
284
                else
285
                    q <= d;
286
endmodule
287 18 unneback
module vl_dff_sr ( aclr, aset, clock, data, q);
288 6 unneback
    input         aclr;
289
    input         aset;
290
    input         clock;
291
    input         data;
292
    output reg    q;
293
   always @ (posedge clock or posedge aclr or posedge aset)
294
     if (aclr)
295
       q <= 1'b0;
296
     else if (aset)
297
       q <= 1'b1;
298
     else
299
       q <= data;
300
endmodule
301
// LATCH
302
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
303
module latch ( d, le, q, clk);
304
input d, le;
305
output q;
306
input clk;/*
307
   always @ (posedge direction_set or posedge direction_clr)
308
     if (direction_clr)
309
       direction <= going_empty;
310
     else
311
       direction <= going_full;*/
312
endmodule
313 18 unneback
module vl_shreg ( d, q, clk, rst);
314 17 unneback
parameter depth = 10;
315
input d;
316
output q;
317
input clk, rst;
318
reg [1:depth] dffs;
319
always @ (posedge clk or posedge rst)
320
if (rst)
321
    dffs <= {depth{1'b0}};
322
else
323
    dffs <= {d,dffs[1:depth-1]};
324
assign q = dffs[depth];
325
endmodule
326 18 unneback
module vl_shreg_ce ( d, ce, q, clk, rst);
327 17 unneback
parameter depth = 10;
328
input d, ce;
329
output q;
330
input clk, rst;
331
reg [1:depth] dffs;
332
always @ (posedge clk or posedge rst)
333
if (rst)
334
    dffs <= {depth{1'b0}};
335
else
336
    if (ce)
337
        dffs <= {d,dffs[1:depth-1]};
338
assign q = dffs[depth];
339
endmodule
340 18 unneback
module vl_delay ( d, q, clk, rst);
341 15 unneback
parameter depth = 10;
342
input d;
343
output q;
344
input clk, rst;
345
reg [1:depth] dffs;
346
always @ (posedge clk or posedge rst)
347
if (rst)
348
    dffs <= {depth{1'b0}};
349
else
350
    dffs <= {d,dffs[1:depth-1]};
351
assign q = dffs[depth];
352
endmodule
353 18 unneback
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
354 17 unneback
parameter depth = 10;
355
input d;
356
output q, emptyflag;
357
input clk, rst;
358
reg [1:depth] dffs;
359
always @ (posedge clk or posedge rst)
360
if (rst)
361
    dffs <= {depth{1'b0}};
362
else
363
    dffs <= {d,dffs[1:depth-1]};
364
assign q = dffs[depth];
365
assign emptyflag = !(|dffs);
366
endmodule
367 6 unneback
//////////////////////////////////////////////////////////////////////
368
////                                                              ////
369 18 unneback
////  Logic functions                                             ////
370
////                                                              ////
371
////  Description                                                 ////
372
////  Logic functions such as multiplexers                        ////
373
////                                                              ////
374
////                                                              ////
375
////  To Do:                                                      ////
376
////   -                                                          ////
377
////                                                              ////
378
////  Author(s):                                                  ////
379
////      - Michael Unneback, unneback@opencores.org              ////
380
////        ORSoC AB                                              ////
381
////                                                              ////
382
//////////////////////////////////////////////////////////////////////
383
////                                                              ////
384
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
385
////                                                              ////
386
//// This source file may be used and distributed without         ////
387
//// restriction provided that this copyright statement is not    ////
388
//// removed from the file and that any derivative work contains  ////
389
//// the original copyright notice and the associated disclaimer. ////
390
////                                                              ////
391
//// This source file is free software; you can redistribute it   ////
392
//// and/or modify it under the terms of the GNU Lesser General   ////
393
//// Public License as published by the Free Software Foundation; ////
394
//// either version 2.1 of the License, or (at your option) any   ////
395
//// later version.                                               ////
396
////                                                              ////
397
//// This source is distributed in the hope that it will be       ////
398
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
399
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
400
//// PURPOSE.  See the GNU Lesser General Public License for more ////
401
//// details.                                                     ////
402
////                                                              ////
403
//// You should have received a copy of the GNU Lesser General    ////
404
//// Public License along with this source; if not, download it   ////
405
//// from http://www.opencores.org/lgpl.shtml                     ////
406
////                                                              ////
407
//////////////////////////////////////////////////////////////////////
408
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
409
parameter width = 32;
410
parameter nr_of_ports = 4;
411
input [width-1:0] a3, a2, a1, a0;
412
input [nr_of_ports-1:0] sel;
413 22 unneback
output [width-1:0] dout;
414 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
415 18 unneback
integer i;
416
// and
417
assign tmp[0] = {width{sel[0]}} & a0;
418
assign tmp[1] = {width{sel[1]}} & a1;
419
assign tmp[2] = {width{sel[2]}} & a2;
420
assign tmp[3] = {width{sel[3]}} & a3;
421
// or
422
assign dout = tmp[3] | tmp[2] | tmp[1] | tmp[0];
423
endmodule
424
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
425
parameter width = 32;
426
parameter nr_of_ports = 5;
427
input [width-1:0] a4, a3, a2, a1, a0;
428
input [nr_of_ports-1:0] sel;
429 22 unneback
output [width-1:0] dout;
430 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
431 18 unneback
integer i;
432
// and
433
assign tmp[0] = {width{sel[0]}} & a0;
434
assign tmp[1] = {width{sel[1]}} & a1;
435
assign tmp[2] = {width{sel[2]}} & a2;
436
assign tmp[3] = {width{sel[3]}} & a3;
437
assign tmp[4] = {width{sel[4]}} & a4;
438
// or
439
assign dout = tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
440
endmodule
441
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
442
parameter width = 32;
443
parameter nr_of_ports = 6;
444
input [width-1:0] a5, a4, a3, a2, a1, a0;
445
input [nr_of_ports-1:0] sel;
446 22 unneback
output [width-1:0] dout;
447 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
448 18 unneback
integer i;
449
// and
450
assign tmp[0] = {width{sel[0]}} & a0;
451
assign tmp[1] = {width{sel[1]}} & a1;
452
assign tmp[2] = {width{sel[2]}} & a2;
453
assign tmp[3] = {width{sel[3]}} & a3;
454
assign tmp[4] = {width{sel[4]}} & a4;
455
assign tmp[5] = {width{sel[5]}} & a5;
456
// or
457
assign dout = tmp[5] | tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
458
endmodule
459
//////////////////////////////////////////////////////////////////////
460
////                                                              ////
461 6 unneback
////  Versatile counter                                           ////
462
////                                                              ////
463
////  Description                                                 ////
464
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
465
////  counter                                                     ////
466
////                                                              ////
467
////  To Do:                                                      ////
468
////   - add LFSR with more taps                                  ////
469
////                                                              ////
470
////  Author(s):                                                  ////
471
////      - Michael Unneback, unneback@opencores.org              ////
472
////        ORSoC AB                                              ////
473
////                                                              ////
474
//////////////////////////////////////////////////////////////////////
475
////                                                              ////
476
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
477
////                                                              ////
478
//// This source file may be used and distributed without         ////
479
//// restriction provided that this copyright statement is not    ////
480
//// removed from the file and that any derivative work contains  ////
481
//// the original copyright notice and the associated disclaimer. ////
482
////                                                              ////
483
//// This source file is free software; you can redistribute it   ////
484
//// and/or modify it under the terms of the GNU Lesser General   ////
485
//// Public License as published by the Free Software Foundation; ////
486
//// either version 2.1 of the License, or (at your option) any   ////
487
//// later version.                                               ////
488
////                                                              ////
489
//// This source is distributed in the hope that it will be       ////
490
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
491
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
492
//// PURPOSE.  See the GNU Lesser General Public License for more ////
493
//// details.                                                     ////
494
////                                                              ////
495
//// You should have received a copy of the GNU Lesser General    ////
496
//// Public License along with this source; if not, download it   ////
497
//// from http://www.opencores.org/lgpl.shtml                     ////
498
////                                                              ////
499
//////////////////////////////////////////////////////////////////////
500
// binary counter
501 22 unneback
module vl_cnt_bin ( q, rst, clk);
502
   parameter length = 4;
503
   output [length:1] q;
504
   input rst;
505
   input clk;
506
   parameter clear_value = 0;
507
   parameter set_value = 1;
508
   parameter wrap_value = 0;
509
   parameter level1_value = 15;
510
   reg  [length:1] qi;
511
   wire [length:1] q_next;
512
   assign q_next = qi + {{length-1{1'b0}},1'b1};
513
   always @ (posedge clk or posedge rst)
514
     if (rst)
515
       qi <= {length{1'b0}};
516
     else
517
       qi <= q_next;
518
   assign q = qi;
519
endmodule
520
//////////////////////////////////////////////////////////////////////
521
////                                                              ////
522
////  Versatile counter                                           ////
523
////                                                              ////
524
////  Description                                                 ////
525
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
526
////  counter                                                     ////
527
////                                                              ////
528
////  To Do:                                                      ////
529
////   - add LFSR with more taps                                  ////
530
////                                                              ////
531
////  Author(s):                                                  ////
532
////      - Michael Unneback, unneback@opencores.org              ////
533
////        ORSoC AB                                              ////
534
////                                                              ////
535
//////////////////////////////////////////////////////////////////////
536
////                                                              ////
537
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
538
////                                                              ////
539
//// This source file may be used and distributed without         ////
540
//// restriction provided that this copyright statement is not    ////
541
//// removed from the file and that any derivative work contains  ////
542
//// the original copyright notice and the associated disclaimer. ////
543
////                                                              ////
544
//// This source file is free software; you can redistribute it   ////
545
//// and/or modify it under the terms of the GNU Lesser General   ////
546
//// Public License as published by the Free Software Foundation; ////
547
//// either version 2.1 of the License, or (at your option) any   ////
548
//// later version.                                               ////
549
////                                                              ////
550
//// This source is distributed in the hope that it will be       ////
551
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
552
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
553
//// PURPOSE.  See the GNU Lesser General Public License for more ////
554
//// details.                                                     ////
555
////                                                              ////
556
//// You should have received a copy of the GNU Lesser General    ////
557
//// Public License along with this source; if not, download it   ////
558
//// from http://www.opencores.org/lgpl.shtml                     ////
559
////                                                              ////
560
//////////////////////////////////////////////////////////////////////
561
// binary counter
562
module vl_cnt_bin_clear ( clear, q, rst, clk);
563
   parameter length = 4;
564
   input clear;
565
   output [length:1] q;
566
   input rst;
567
   input clk;
568
   parameter clear_value = 0;
569
   parameter set_value = 1;
570
   parameter wrap_value = 0;
571
   parameter level1_value = 15;
572
   reg  [length:1] qi;
573
   wire [length:1] q_next;
574
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
575
   always @ (posedge clk or posedge rst)
576
     if (rst)
577
       qi <= {length{1'b0}};
578
     else
579
       qi <= q_next;
580
   assign q = qi;
581
endmodule
582
//////////////////////////////////////////////////////////////////////
583
////                                                              ////
584
////  Versatile counter                                           ////
585
////                                                              ////
586
////  Description                                                 ////
587
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
588
////  counter                                                     ////
589
////                                                              ////
590
////  To Do:                                                      ////
591
////   - add LFSR with more taps                                  ////
592
////                                                              ////
593
////  Author(s):                                                  ////
594
////      - Michael Unneback, unneback@opencores.org              ////
595
////        ORSoC AB                                              ////
596
////                                                              ////
597
//////////////////////////////////////////////////////////////////////
598
////                                                              ////
599
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
600
////                                                              ////
601
//// This source file may be used and distributed without         ////
602
//// restriction provided that this copyright statement is not    ////
603
//// removed from the file and that any derivative work contains  ////
604
//// the original copyright notice and the associated disclaimer. ////
605
////                                                              ////
606
//// This source file is free software; you can redistribute it   ////
607
//// and/or modify it under the terms of the GNU Lesser General   ////
608
//// Public License as published by the Free Software Foundation; ////
609
//// either version 2.1 of the License, or (at your option) any   ////
610
//// later version.                                               ////
611
////                                                              ////
612
//// This source is distributed in the hope that it will be       ////
613
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
614
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
615
//// PURPOSE.  See the GNU Lesser General Public License for more ////
616
//// details.                                                     ////
617
////                                                              ////
618
//// You should have received a copy of the GNU Lesser General    ////
619
//// Public License along with this source; if not, download it   ////
620
//// from http://www.opencores.org/lgpl.shtml                     ////
621
////                                                              ////
622
//////////////////////////////////////////////////////////////////////
623
// binary counter
624 18 unneback
module vl_cnt_bin_ce ( cke, q, rst, clk);
625 6 unneback
   parameter length = 4;
626
   input cke;
627
   output [length:1] q;
628
   input rst;
629
   input clk;
630
   parameter clear_value = 0;
631
   parameter set_value = 1;
632
   parameter wrap_value = 0;
633
   parameter level1_value = 15;
634
   reg  [length:1] qi;
635
   wire [length:1] q_next;
636
   assign q_next = qi + {{length-1{1'b0}},1'b1};
637
   always @ (posedge clk or posedge rst)
638
     if (rst)
639
       qi <= {length{1'b0}};
640
     else
641
     if (cke)
642
       qi <= q_next;
643
   assign q = qi;
644
endmodule
645
//////////////////////////////////////////////////////////////////////
646
////                                                              ////
647
////  Versatile counter                                           ////
648
////                                                              ////
649
////  Description                                                 ////
650
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
651
////  counter                                                     ////
652
////                                                              ////
653
////  To Do:                                                      ////
654
////   - add LFSR with more taps                                  ////
655
////                                                              ////
656
////  Author(s):                                                  ////
657
////      - Michael Unneback, unneback@opencores.org              ////
658
////        ORSoC AB                                              ////
659
////                                                              ////
660
//////////////////////////////////////////////////////////////////////
661
////                                                              ////
662
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
663
////                                                              ////
664
//// This source file may be used and distributed without         ////
665
//// restriction provided that this copyright statement is not    ////
666
//// removed from the file and that any derivative work contains  ////
667
//// the original copyright notice and the associated disclaimer. ////
668
////                                                              ////
669
//// This source file is free software; you can redistribute it   ////
670
//// and/or modify it under the terms of the GNU Lesser General   ////
671
//// Public License as published by the Free Software Foundation; ////
672
//// either version 2.1 of the License, or (at your option) any   ////
673
//// later version.                                               ////
674
////                                                              ////
675
//// This source is distributed in the hope that it will be       ////
676
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
677
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
678
//// PURPOSE.  See the GNU Lesser General Public License for more ////
679
//// details.                                                     ////
680
////                                                              ////
681
//// You should have received a copy of the GNU Lesser General    ////
682
//// Public License along with this source; if not, download it   ////
683
//// from http://www.opencores.org/lgpl.shtml                     ////
684
////                                                              ////
685
//////////////////////////////////////////////////////////////////////
686
// binary counter
687 18 unneback
module vl_cnt_bin_ce_clear ( clear, cke, q, rst, clk);
688 6 unneback
   parameter length = 4;
689
   input clear;
690
   input cke;
691
   output [length:1] q;
692
   input rst;
693
   input clk;
694
   parameter clear_value = 0;
695
   parameter set_value = 1;
696
   parameter wrap_value = 0;
697
   parameter level1_value = 15;
698
   reg  [length:1] qi;
699
   wire [length:1] q_next;
700
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
701
   always @ (posedge clk or posedge rst)
702
     if (rst)
703
       qi <= {length{1'b0}};
704
     else
705
     if (cke)
706
       qi <= q_next;
707
   assign q = qi;
708
endmodule
709
//////////////////////////////////////////////////////////////////////
710
////                                                              ////
711
////  Versatile counter                                           ////
712
////                                                              ////
713
////  Description                                                 ////
714
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
715
////  counter                                                     ////
716
////                                                              ////
717
////  To Do:                                                      ////
718
////   - add LFSR with more taps                                  ////
719
////                                                              ////
720
////  Author(s):                                                  ////
721
////      - Michael Unneback, unneback@opencores.org              ////
722
////        ORSoC AB                                              ////
723
////                                                              ////
724
//////////////////////////////////////////////////////////////////////
725
////                                                              ////
726
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
727
////                                                              ////
728
//// This source file may be used and distributed without         ////
729
//// restriction provided that this copyright statement is not    ////
730
//// removed from the file and that any derivative work contains  ////
731
//// the original copyright notice and the associated disclaimer. ////
732
////                                                              ////
733
//// This source file is free software; you can redistribute it   ////
734
//// and/or modify it under the terms of the GNU Lesser General   ////
735
//// Public License as published by the Free Software Foundation; ////
736
//// either version 2.1 of the License, or (at your option) any   ////
737
//// later version.                                               ////
738
////                                                              ////
739
//// This source is distributed in the hope that it will be       ////
740
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
741
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
742
//// PURPOSE.  See the GNU Lesser General Public License for more ////
743
//// details.                                                     ////
744
////                                                              ////
745
//// You should have received a copy of the GNU Lesser General    ////
746
//// Public License along with this source; if not, download it   ////
747
//// from http://www.opencores.org/lgpl.shtml                     ////
748
////                                                              ////
749
//////////////////////////////////////////////////////////////////////
750
// binary counter
751 18 unneback
module vl_cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk);
752 6 unneback
   parameter length = 4;
753
   input clear;
754
   input set;
755
   input cke;
756
   input rew;
757
   output [length:1] q;
758
   input rst;
759
   input clk;
760
   parameter clear_value = 0;
761
   parameter set_value = 1;
762
   parameter wrap_value = 0;
763
   parameter level1_value = 15;
764
   reg  [length:1] qi;
765
   wire  [length:1] q_next, q_next_fw, q_next_rew;
766
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
767
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
768
   assign q_next = rew ? q_next_rew : q_next_fw;
769
   always @ (posedge clk or posedge rst)
770
     if (rst)
771
       qi <= {length{1'b0}};
772
     else
773
     if (cke)
774
       qi <= q_next;
775
   assign q = qi;
776
endmodule
777
//////////////////////////////////////////////////////////////////////
778
////                                                              ////
779
////  Versatile counter                                           ////
780
////                                                              ////
781
////  Description                                                 ////
782
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
783
////  counter                                                     ////
784
////                                                              ////
785
////  To Do:                                                      ////
786
////   - add LFSR with more taps                                  ////
787
////                                                              ////
788
////  Author(s):                                                  ////
789
////      - Michael Unneback, unneback@opencores.org              ////
790
////        ORSoC AB                                              ////
791
////                                                              ////
792
//////////////////////////////////////////////////////////////////////
793
////                                                              ////
794
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
795
////                                                              ////
796
//// This source file may be used and distributed without         ////
797
//// restriction provided that this copyright statement is not    ////
798
//// removed from the file and that any derivative work contains  ////
799
//// the original copyright notice and the associated disclaimer. ////
800
////                                                              ////
801
//// This source file is free software; you can redistribute it   ////
802
//// and/or modify it under the terms of the GNU Lesser General   ////
803
//// Public License as published by the Free Software Foundation; ////
804
//// either version 2.1 of the License, or (at your option) any   ////
805
//// later version.                                               ////
806
////                                                              ////
807
//// This source is distributed in the hope that it will be       ////
808
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
809
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
810
//// PURPOSE.  See the GNU Lesser General Public License for more ////
811
//// details.                                                     ////
812
////                                                              ////
813
//// You should have received a copy of the GNU Lesser General    ////
814
//// Public License along with this source; if not, download it   ////
815
//// from http://www.opencores.org/lgpl.shtml                     ////
816
////                                                              ////
817
//////////////////////////////////////////////////////////////////////
818
// binary counter
819 18 unneback
module vl_cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk);
820 6 unneback
   parameter length = 4;
821
   input cke;
822
   input rew;
823
   output reg level1;
824
   input rst;
825
   input clk;
826
   parameter clear_value = 0;
827
   parameter set_value = 1;
828
   parameter wrap_value = 1;
829
   parameter level1_value = 15;
830
   reg  [length:1] qi;
831
   wire  [length:1] q_next, q_next_fw, q_next_rew;
832
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
833
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
834
   assign q_next = rew ? q_next_rew : q_next_fw;
835
   always @ (posedge clk or posedge rst)
836
     if (rst)
837
       qi <= {length{1'b0}};
838
     else
839
     if (cke)
840
       qi <= q_next;
841
    always @ (posedge clk or posedge rst)
842
    if (rst)
843
        level1 <= 1'b0;
844
    else
845
    if (cke)
846
    if (q_next == level1_value)
847
        level1 <= 1'b1;
848
    else if (qi == level1_value & rew)
849
        level1 <= 1'b0;
850
endmodule
851
//////////////////////////////////////////////////////////////////////
852
////                                                              ////
853
////  Versatile counter                                           ////
854
////                                                              ////
855
////  Description                                                 ////
856
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
857
////  counter                                                     ////
858
////                                                              ////
859
////  To Do:                                                      ////
860
////   - add LFSR with more taps                                  ////
861
////                                                              ////
862
////  Author(s):                                                  ////
863
////      - Michael Unneback, unneback@opencores.org              ////
864
////        ORSoC AB                                              ////
865
////                                                              ////
866
//////////////////////////////////////////////////////////////////////
867
////                                                              ////
868
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
869
////                                                              ////
870
//// This source file may be used and distributed without         ////
871
//// restriction provided that this copyright statement is not    ////
872
//// removed from the file and that any derivative work contains  ////
873
//// the original copyright notice and the associated disclaimer. ////
874
////                                                              ////
875
//// This source file is free software; you can redistribute it   ////
876
//// and/or modify it under the terms of the GNU Lesser General   ////
877
//// Public License as published by the Free Software Foundation; ////
878
//// either version 2.1 of the License, or (at your option) any   ////
879
//// later version.                                               ////
880
////                                                              ////
881
//// This source is distributed in the hope that it will be       ////
882
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
883
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
884
//// PURPOSE.  See the GNU Lesser General Public License for more ////
885
//// details.                                                     ////
886
////                                                              ////
887
//// You should have received a copy of the GNU Lesser General    ////
888
//// Public License along with this source; if not, download it   ////
889
//// from http://www.opencores.org/lgpl.shtml                     ////
890
////                                                              ////
891
//////////////////////////////////////////////////////////////////////
892
// LFSR counter
893 18 unneback
module vl_cnt_lfsr_zq ( zq, rst, clk);
894 6 unneback
   parameter length = 4;
895
   output reg zq;
896
   input rst;
897
   input clk;
898
   parameter clear_value = 0;
899
   parameter set_value = 1;
900
   parameter wrap_value = 8;
901
   parameter level1_value = 15;
902
   reg  [length:1] qi;
903
   reg lfsr_fb;
904
   wire [length:1] q_next;
905
   reg [32:1] polynom;
906
   integer i;
907
   always @ (qi)
908
   begin
909
        case (length)
910
         2: polynom = 32'b11;                               // 0x3
911
         3: polynom = 32'b110;                              // 0x6
912
         4: polynom = 32'b1100;                             // 0xC
913
         5: polynom = 32'b10100;                            // 0x14
914
         6: polynom = 32'b110000;                           // 0x30
915
         7: polynom = 32'b1100000;                          // 0x60
916
         8: polynom = 32'b10111000;                         // 0xb8
917
         9: polynom = 32'b100010000;                        // 0x110
918
        10: polynom = 32'b1001000000;                       // 0x240
919
        11: polynom = 32'b10100000000;                      // 0x500
920
        12: polynom = 32'b100000101001;                     // 0x829
921
        13: polynom = 32'b1000000001100;                    // 0x100C
922
        14: polynom = 32'b10000000010101;                   // 0x2015
923
        15: polynom = 32'b110000000000000;                  // 0x6000
924
        16: polynom = 32'b1101000000001000;                 // 0xD008
925
        17: polynom = 32'b10010000000000000;                // 0x12000
926
        18: polynom = 32'b100000010000000000;               // 0x20400
927
        19: polynom = 32'b1000000000000100011;              // 0x40023
928
        20: polynom = 32'b10000010000000000000;             // 0x82000
929
        21: polynom = 32'b101000000000000000000;            // 0x140000
930
        22: polynom = 32'b1100000000000000000000;           // 0x300000
931
        23: polynom = 32'b10000100000000000000000;          // 0x420000
932
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
933
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
934
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
935
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
936
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
937
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
938
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
939
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
940
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
941
        default: polynom = 32'b0;
942
        endcase
943
        lfsr_fb = qi[length];
944
        for (i=length-1; i>=1; i=i-1) begin
945
            if (polynom[i])
946
                lfsr_fb = lfsr_fb  ~^ qi[i];
947
        end
948
    end
949
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
950
   always @ (posedge clk or posedge rst)
951
     if (rst)
952
       qi <= {length{1'b0}};
953
     else
954
       qi <= q_next;
955
   always @ (posedge clk or posedge rst)
956
     if (rst)
957
       zq <= 1'b1;
958
     else
959
       zq <= q_next == {length{1'b0}};
960
endmodule
961
//////////////////////////////////////////////////////////////////////
962
////                                                              ////
963
////  Versatile counter                                           ////
964
////                                                              ////
965
////  Description                                                 ////
966
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
967
////  counter                                                     ////
968
////                                                              ////
969
////  To Do:                                                      ////
970
////   - add LFSR with more taps                                  ////
971
////                                                              ////
972
////  Author(s):                                                  ////
973
////      - Michael Unneback, unneback@opencores.org              ////
974
////        ORSoC AB                                              ////
975
////                                                              ////
976
//////////////////////////////////////////////////////////////////////
977
////                                                              ////
978
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
979
////                                                              ////
980
//// This source file may be used and distributed without         ////
981
//// restriction provided that this copyright statement is not    ////
982
//// removed from the file and that any derivative work contains  ////
983
//// the original copyright notice and the associated disclaimer. ////
984
////                                                              ////
985
//// This source file is free software; you can redistribute it   ////
986
//// and/or modify it under the terms of the GNU Lesser General   ////
987
//// Public License as published by the Free Software Foundation; ////
988
//// either version 2.1 of the License, or (at your option) any   ////
989
//// later version.                                               ////
990
////                                                              ////
991
//// This source is distributed in the hope that it will be       ////
992
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
993
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
994
//// PURPOSE.  See the GNU Lesser General Public License for more ////
995
//// details.                                                     ////
996
////                                                              ////
997
//// You should have received a copy of the GNU Lesser General    ////
998
//// Public License along with this source; if not, download it   ////
999
//// from http://www.opencores.org/lgpl.shtml                     ////
1000
////                                                              ////
1001
//////////////////////////////////////////////////////////////////////
1002
// LFSR counter
1003 18 unneback
module vl_cnt_lfsr_ce_zq ( cke, zq, rst, clk);
1004 6 unneback
   parameter length = 4;
1005
   input cke;
1006
   output reg zq;
1007
   input rst;
1008
   input clk;
1009
   parameter clear_value = 0;
1010
   parameter set_value = 1;
1011
   parameter wrap_value = 8;
1012
   parameter level1_value = 15;
1013
   reg  [length:1] qi;
1014
   reg lfsr_fb;
1015
   wire [length:1] q_next;
1016
   reg [32:1] polynom;
1017
   integer i;
1018
   always @ (qi)
1019
   begin
1020
        case (length)
1021
         2: polynom = 32'b11;                               // 0x3
1022
         3: polynom = 32'b110;                              // 0x6
1023
         4: polynom = 32'b1100;                             // 0xC
1024
         5: polynom = 32'b10100;                            // 0x14
1025
         6: polynom = 32'b110000;                           // 0x30
1026
         7: polynom = 32'b1100000;                          // 0x60
1027
         8: polynom = 32'b10111000;                         // 0xb8
1028
         9: polynom = 32'b100010000;                        // 0x110
1029
        10: polynom = 32'b1001000000;                       // 0x240
1030
        11: polynom = 32'b10100000000;                      // 0x500
1031
        12: polynom = 32'b100000101001;                     // 0x829
1032
        13: polynom = 32'b1000000001100;                    // 0x100C
1033
        14: polynom = 32'b10000000010101;                   // 0x2015
1034
        15: polynom = 32'b110000000000000;                  // 0x6000
1035
        16: polynom = 32'b1101000000001000;                 // 0xD008
1036
        17: polynom = 32'b10010000000000000;                // 0x12000
1037
        18: polynom = 32'b100000010000000000;               // 0x20400
1038
        19: polynom = 32'b1000000000000100011;              // 0x40023
1039
        20: polynom = 32'b10000010000000000000;             // 0x82000
1040
        21: polynom = 32'b101000000000000000000;            // 0x140000
1041
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1042
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1043
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1044
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1045
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1046
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1047
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1048
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1049
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1050
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1051
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1052
        default: polynom = 32'b0;
1053
        endcase
1054
        lfsr_fb = qi[length];
1055
        for (i=length-1; i>=1; i=i-1) begin
1056
            if (polynom[i])
1057
                lfsr_fb = lfsr_fb  ~^ qi[i];
1058
        end
1059
    end
1060
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1061
   always @ (posedge clk or posedge rst)
1062
     if (rst)
1063
       qi <= {length{1'b0}};
1064
     else
1065
     if (cke)
1066
       qi <= q_next;
1067
   always @ (posedge clk or posedge rst)
1068
     if (rst)
1069
       zq <= 1'b1;
1070
     else
1071
     if (cke)
1072
       zq <= q_next == {length{1'b0}};
1073
endmodule
1074
//////////////////////////////////////////////////////////////////////
1075
////                                                              ////
1076
////  Versatile counter                                           ////
1077
////                                                              ////
1078
////  Description                                                 ////
1079
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1080
////  counter                                                     ////
1081
////                                                              ////
1082
////  To Do:                                                      ////
1083
////   - add LFSR with more taps                                  ////
1084
////                                                              ////
1085
////  Author(s):                                                  ////
1086
////      - Michael Unneback, unneback@opencores.org              ////
1087
////        ORSoC AB                                              ////
1088
////                                                              ////
1089
//////////////////////////////////////////////////////////////////////
1090
////                                                              ////
1091
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1092
////                                                              ////
1093
//// This source file may be used and distributed without         ////
1094
//// restriction provided that this copyright statement is not    ////
1095
//// removed from the file and that any derivative work contains  ////
1096
//// the original copyright notice and the associated disclaimer. ////
1097
////                                                              ////
1098
//// This source file is free software; you can redistribute it   ////
1099
//// and/or modify it under the terms of the GNU Lesser General   ////
1100
//// Public License as published by the Free Software Foundation; ////
1101
//// either version 2.1 of the License, or (at your option) any   ////
1102
//// later version.                                               ////
1103
////                                                              ////
1104
//// This source is distributed in the hope that it will be       ////
1105
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1106
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1107
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1108
//// details.                                                     ////
1109
////                                                              ////
1110
//// You should have received a copy of the GNU Lesser General    ////
1111
//// Public License along with this source; if not, download it   ////
1112
//// from http://www.opencores.org/lgpl.shtml                     ////
1113
////                                                              ////
1114
//////////////////////////////////////////////////////////////////////
1115
// LFSR counter
1116 22 unneback
module vl_cnt_lfsr_ce_q_zq ( cke, q, zq, rst, clk);
1117
   parameter length = 4;
1118
   input cke;
1119
   output [length:1] q;
1120
   output reg zq;
1121
   input rst;
1122
   input clk;
1123
   parameter clear_value = 0;
1124
   parameter set_value = 1;
1125
   parameter wrap_value = 8;
1126
   parameter level1_value = 15;
1127
   reg  [length:1] qi;
1128
   reg lfsr_fb;
1129
   wire [length:1] q_next;
1130
   reg [32:1] polynom;
1131
   integer i;
1132
   always @ (qi)
1133
   begin
1134
        case (length)
1135
         2: polynom = 32'b11;                               // 0x3
1136
         3: polynom = 32'b110;                              // 0x6
1137
         4: polynom = 32'b1100;                             // 0xC
1138
         5: polynom = 32'b10100;                            // 0x14
1139
         6: polynom = 32'b110000;                           // 0x30
1140
         7: polynom = 32'b1100000;                          // 0x60
1141
         8: polynom = 32'b10111000;                         // 0xb8
1142
         9: polynom = 32'b100010000;                        // 0x110
1143
        10: polynom = 32'b1001000000;                       // 0x240
1144
        11: polynom = 32'b10100000000;                      // 0x500
1145
        12: polynom = 32'b100000101001;                     // 0x829
1146
        13: polynom = 32'b1000000001100;                    // 0x100C
1147
        14: polynom = 32'b10000000010101;                   // 0x2015
1148
        15: polynom = 32'b110000000000000;                  // 0x6000
1149
        16: polynom = 32'b1101000000001000;                 // 0xD008
1150
        17: polynom = 32'b10010000000000000;                // 0x12000
1151
        18: polynom = 32'b100000010000000000;               // 0x20400
1152
        19: polynom = 32'b1000000000000100011;              // 0x40023
1153
        20: polynom = 32'b10000010000000000000;             // 0x82000
1154
        21: polynom = 32'b101000000000000000000;            // 0x140000
1155
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1156
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1157
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1158
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1159
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1160
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1161
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1162
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1163
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1164
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1165
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1166
        default: polynom = 32'b0;
1167
        endcase
1168
        lfsr_fb = qi[length];
1169
        for (i=length-1; i>=1; i=i-1) begin
1170
            if (polynom[i])
1171
                lfsr_fb = lfsr_fb  ~^ qi[i];
1172
        end
1173
    end
1174
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1175
   always @ (posedge clk or posedge rst)
1176
     if (rst)
1177
       qi <= {length{1'b0}};
1178
     else
1179
     if (cke)
1180
       qi <= q_next;
1181
   assign q = qi;
1182
   always @ (posedge clk or posedge rst)
1183
     if (rst)
1184
       zq <= 1'b1;
1185
     else
1186
     if (cke)
1187
       zq <= q_next == {length{1'b0}};
1188
endmodule
1189
//////////////////////////////////////////////////////////////////////
1190
////                                                              ////
1191
////  Versatile counter                                           ////
1192
////                                                              ////
1193
////  Description                                                 ////
1194
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1195
////  counter                                                     ////
1196
////                                                              ////
1197
////  To Do:                                                      ////
1198
////   - add LFSR with more taps                                  ////
1199
////                                                              ////
1200
////  Author(s):                                                  ////
1201
////      - Michael Unneback, unneback@opencores.org              ////
1202
////        ORSoC AB                                              ////
1203
////                                                              ////
1204
//////////////////////////////////////////////////////////////////////
1205
////                                                              ////
1206
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1207
////                                                              ////
1208
//// This source file may be used and distributed without         ////
1209
//// restriction provided that this copyright statement is not    ////
1210
//// removed from the file and that any derivative work contains  ////
1211
//// the original copyright notice and the associated disclaimer. ////
1212
////                                                              ////
1213
//// This source file is free software; you can redistribute it   ////
1214
//// and/or modify it under the terms of the GNU Lesser General   ////
1215
//// Public License as published by the Free Software Foundation; ////
1216
//// either version 2.1 of the License, or (at your option) any   ////
1217
//// later version.                                               ////
1218
////                                                              ////
1219
//// This source is distributed in the hope that it will be       ////
1220
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1221
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1222
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1223
//// details.                                                     ////
1224
////                                                              ////
1225
//// You should have received a copy of the GNU Lesser General    ////
1226
//// Public License along with this source; if not, download it   ////
1227
//// from http://www.opencores.org/lgpl.shtml                     ////
1228
////                                                              ////
1229
//////////////////////////////////////////////////////////////////////
1230
// LFSR counter
1231 18 unneback
module vl_cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk);
1232 6 unneback
   parameter length = 4;
1233
   input cke;
1234
   input rew;
1235
   output reg level1;
1236
   input rst;
1237
   input clk;
1238
   parameter clear_value = 0;
1239
   parameter set_value = 1;
1240
   parameter wrap_value = 8;
1241
   parameter level1_value = 15;
1242
   reg  [length:1] qi;
1243
   reg lfsr_fb, lfsr_fb_rew;
1244
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1245
   reg [32:1] polynom_rew;
1246
   integer j;
1247
   reg [32:1] polynom;
1248
   integer i;
1249
   always @ (qi)
1250
   begin
1251
        case (length)
1252
         2: polynom = 32'b11;                               // 0x3
1253
         3: polynom = 32'b110;                              // 0x6
1254
         4: polynom = 32'b1100;                             // 0xC
1255
         5: polynom = 32'b10100;                            // 0x14
1256
         6: polynom = 32'b110000;                           // 0x30
1257
         7: polynom = 32'b1100000;                          // 0x60
1258
         8: polynom = 32'b10111000;                         // 0xb8
1259
         9: polynom = 32'b100010000;                        // 0x110
1260
        10: polynom = 32'b1001000000;                       // 0x240
1261
        11: polynom = 32'b10100000000;                      // 0x500
1262
        12: polynom = 32'b100000101001;                     // 0x829
1263
        13: polynom = 32'b1000000001100;                    // 0x100C
1264
        14: polynom = 32'b10000000010101;                   // 0x2015
1265
        15: polynom = 32'b110000000000000;                  // 0x6000
1266
        16: polynom = 32'b1101000000001000;                 // 0xD008
1267
        17: polynom = 32'b10010000000000000;                // 0x12000
1268
        18: polynom = 32'b100000010000000000;               // 0x20400
1269
        19: polynom = 32'b1000000000000100011;              // 0x40023
1270
        20: polynom = 32'b10000010000000000000;             // 0x82000
1271
        21: polynom = 32'b101000000000000000000;            // 0x140000
1272
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1273
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1274
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1275
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1276
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1277
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1278
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1279
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1280
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1281
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1282
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1283
        default: polynom = 32'b0;
1284
        endcase
1285
        lfsr_fb = qi[length];
1286
        for (i=length-1; i>=1; i=i-1) begin
1287
            if (polynom[i])
1288
                lfsr_fb = lfsr_fb  ~^ qi[i];
1289
        end
1290
    end
1291
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1292
   always @ (qi)
1293
   begin
1294
        case (length)
1295
         2: polynom_rew = 32'b11;
1296
         3: polynom_rew = 32'b110;
1297
         4: polynom_rew = 32'b1100;
1298
         5: polynom_rew = 32'b10100;
1299
         6: polynom_rew = 32'b110000;
1300
         7: polynom_rew = 32'b1100000;
1301
         8: polynom_rew = 32'b10111000;
1302
         9: polynom_rew = 32'b100010000;
1303
        10: polynom_rew = 32'b1001000000;
1304
        11: polynom_rew = 32'b10100000000;
1305
        12: polynom_rew = 32'b100000101001;
1306
        13: polynom_rew = 32'b1000000001100;
1307
        14: polynom_rew = 32'b10000000010101;
1308
        15: polynom_rew = 32'b110000000000000;
1309
        16: polynom_rew = 32'b1101000000001000;
1310
        17: polynom_rew = 32'b10010000000000000;
1311
        18: polynom_rew = 32'b100000010000000000;
1312
        19: polynom_rew = 32'b1000000000000100011;
1313
        20: polynom_rew = 32'b10000010000000000000;
1314
        21: polynom_rew = 32'b101000000000000000000;
1315
        22: polynom_rew = 32'b1100000000000000000000;
1316
        23: polynom_rew = 32'b10000100000000000000000;
1317
        24: polynom_rew = 32'b111000010000000000000000;
1318
        25: polynom_rew = 32'b1001000000000000000000000;
1319
        26: polynom_rew = 32'b10000000000000000000100011;
1320
        27: polynom_rew = 32'b100000000000000000000010011;
1321
        28: polynom_rew = 32'b1100100000000000000000000000;
1322
        29: polynom_rew = 32'b10100000000000000000000000000;
1323
        30: polynom_rew = 32'b100000000000000000000000101001;
1324
        31: polynom_rew = 32'b1001000000000000000000000000000;
1325
        32: polynom_rew = 32'b10000000001000000000000000000011;
1326
        default: polynom_rew = 32'b0;
1327
        endcase
1328
        // rotate left
1329
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
1330
        lfsr_fb_rew = qi[length];
1331
        for (i=length-1; i>=1; i=i-1) begin
1332
            if (polynom_rew[i])
1333
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
1334
        end
1335
    end
1336
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
1337
   assign q_next = rew ? q_next_rew : q_next_fw;
1338
   always @ (posedge clk or posedge rst)
1339
     if (rst)
1340
       qi <= {length{1'b0}};
1341
     else
1342
     if (cke)
1343
       qi <= q_next;
1344
    always @ (posedge clk or posedge rst)
1345
    if (rst)
1346
        level1 <= 1'b0;
1347
    else
1348
    if (cke)
1349
    if (q_next == level1_value)
1350
        level1 <= 1'b1;
1351
    else if (qi == level1_value & rew)
1352
        level1 <= 1'b0;
1353
endmodule
1354
//////////////////////////////////////////////////////////////////////
1355
////                                                              ////
1356
////  Versatile counter                                           ////
1357
////                                                              ////
1358
////  Description                                                 ////
1359
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1360
////  counter                                                     ////
1361
////                                                              ////
1362
////  To Do:                                                      ////
1363
////   - add LFSR with more taps                                  ////
1364
////                                                              ////
1365
////  Author(s):                                                  ////
1366
////      - Michael Unneback, unneback@opencores.org              ////
1367
////        ORSoC AB                                              ////
1368
////                                                              ////
1369
//////////////////////////////////////////////////////////////////////
1370
////                                                              ////
1371
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1372
////                                                              ////
1373
//// This source file may be used and distributed without         ////
1374
//// restriction provided that this copyright statement is not    ////
1375
//// removed from the file and that any derivative work contains  ////
1376
//// the original copyright notice and the associated disclaimer. ////
1377
////                                                              ////
1378
//// This source file is free software; you can redistribute it   ////
1379
//// and/or modify it under the terms of the GNU Lesser General   ////
1380
//// Public License as published by the Free Software Foundation; ////
1381
//// either version 2.1 of the License, or (at your option) any   ////
1382
//// later version.                                               ////
1383
////                                                              ////
1384
//// This source is distributed in the hope that it will be       ////
1385
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1386
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1387
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1388
//// details.                                                     ////
1389
////                                                              ////
1390
//// You should have received a copy of the GNU Lesser General    ////
1391
//// Public License along with this source; if not, download it   ////
1392
//// from http://www.opencores.org/lgpl.shtml                     ////
1393
////                                                              ////
1394
//////////////////////////////////////////////////////////////////////
1395
// GRAY counter
1396 18 unneback
module vl_cnt_gray ( q, rst, clk);
1397 6 unneback
   parameter length = 4;
1398
   output reg [length:1] q;
1399
   input rst;
1400
   input clk;
1401
   parameter clear_value = 0;
1402
   parameter set_value = 1;
1403
   parameter wrap_value = 8;
1404
   parameter level1_value = 15;
1405
   reg  [length:1] qi;
1406
   wire [length:1] q_next;
1407
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1408
   always @ (posedge clk or posedge rst)
1409
     if (rst)
1410
       qi <= {length{1'b0}};
1411
     else
1412
       qi <= q_next;
1413
   always @ (posedge clk or posedge rst)
1414
     if (rst)
1415
       q <= {length{1'b0}};
1416
     else
1417
         q <= (q_next>>1) ^ q_next;
1418
endmodule
1419
//////////////////////////////////////////////////////////////////////
1420
////                                                              ////
1421
////  Versatile counter                                           ////
1422
////                                                              ////
1423
////  Description                                                 ////
1424
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1425
////  counter                                                     ////
1426
////                                                              ////
1427
////  To Do:                                                      ////
1428
////   - add LFSR with more taps                                  ////
1429
////                                                              ////
1430
////  Author(s):                                                  ////
1431
////      - Michael Unneback, unneback@opencores.org              ////
1432
////        ORSoC AB                                              ////
1433
////                                                              ////
1434
//////////////////////////////////////////////////////////////////////
1435
////                                                              ////
1436
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1437
////                                                              ////
1438
//// This source file may be used and distributed without         ////
1439
//// restriction provided that this copyright statement is not    ////
1440
//// removed from the file and that any derivative work contains  ////
1441
//// the original copyright notice and the associated disclaimer. ////
1442
////                                                              ////
1443
//// This source file is free software; you can redistribute it   ////
1444
//// and/or modify it under the terms of the GNU Lesser General   ////
1445
//// Public License as published by the Free Software Foundation; ////
1446
//// either version 2.1 of the License, or (at your option) any   ////
1447
//// later version.                                               ////
1448
////                                                              ////
1449
//// This source is distributed in the hope that it will be       ////
1450
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1451
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1452
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1453
//// details.                                                     ////
1454
////                                                              ////
1455
//// You should have received a copy of the GNU Lesser General    ////
1456
//// Public License along with this source; if not, download it   ////
1457
//// from http://www.opencores.org/lgpl.shtml                     ////
1458
////                                                              ////
1459
//////////////////////////////////////////////////////////////////////
1460
// GRAY counter
1461 18 unneback
module vl_cnt_gray_ce ( cke, q, rst, clk);
1462 6 unneback
   parameter length = 4;
1463
   input cke;
1464
   output reg [length:1] q;
1465
   input rst;
1466
   input clk;
1467
   parameter clear_value = 0;
1468
   parameter set_value = 1;
1469
   parameter wrap_value = 8;
1470
   parameter level1_value = 15;
1471
   reg  [length:1] qi;
1472
   wire [length:1] q_next;
1473
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1474
   always @ (posedge clk or posedge rst)
1475
     if (rst)
1476
       qi <= {length{1'b0}};
1477
     else
1478
     if (cke)
1479
       qi <= q_next;
1480
   always @ (posedge clk or posedge rst)
1481
     if (rst)
1482
       q <= {length{1'b0}};
1483
     else
1484
       if (cke)
1485
         q <= (q_next>>1) ^ q_next;
1486
endmodule
1487
//////////////////////////////////////////////////////////////////////
1488
////                                                              ////
1489
////  Versatile counter                                           ////
1490
////                                                              ////
1491
////  Description                                                 ////
1492
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1493
////  counter                                                     ////
1494
////                                                              ////
1495
////  To Do:                                                      ////
1496
////   - add LFSR with more taps                                  ////
1497
////                                                              ////
1498
////  Author(s):                                                  ////
1499
////      - Michael Unneback, unneback@opencores.org              ////
1500
////        ORSoC AB                                              ////
1501
////                                                              ////
1502
//////////////////////////////////////////////////////////////////////
1503
////                                                              ////
1504
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1505
////                                                              ////
1506
//// This source file may be used and distributed without         ////
1507
//// restriction provided that this copyright statement is not    ////
1508
//// removed from the file and that any derivative work contains  ////
1509
//// the original copyright notice and the associated disclaimer. ////
1510
////                                                              ////
1511
//// This source file is free software; you can redistribute it   ////
1512
//// and/or modify it under the terms of the GNU Lesser General   ////
1513
//// Public License as published by the Free Software Foundation; ////
1514
//// either version 2.1 of the License, or (at your option) any   ////
1515
//// later version.                                               ////
1516
////                                                              ////
1517
//// This source is distributed in the hope that it will be       ////
1518
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1519
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1520
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1521
//// details.                                                     ////
1522
////                                                              ////
1523
//// You should have received a copy of the GNU Lesser General    ////
1524
//// Public License along with this source; if not, download it   ////
1525
//// from http://www.opencores.org/lgpl.shtml                     ////
1526
////                                                              ////
1527
//////////////////////////////////////////////////////////////////////
1528
// GRAY counter
1529 18 unneback
module vl_cnt_gray_ce_bin ( cke, q, q_bin, rst, clk);
1530 6 unneback
   parameter length = 4;
1531
   input cke;
1532
   output reg [length:1] q;
1533
   output [length:1] q_bin;
1534
   input rst;
1535
   input clk;
1536
   parameter clear_value = 0;
1537
   parameter set_value = 1;
1538
   parameter wrap_value = 8;
1539
   parameter level1_value = 15;
1540
   reg  [length:1] qi;
1541
   wire [length:1] q_next;
1542
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1543
   always @ (posedge clk or posedge rst)
1544
     if (rst)
1545
       qi <= {length{1'b0}};
1546
     else
1547
     if (cke)
1548
       qi <= q_next;
1549
   always @ (posedge clk or posedge rst)
1550
     if (rst)
1551
       q <= {length{1'b0}};
1552
     else
1553
       if (cke)
1554
         q <= (q_next>>1) ^ q_next;
1555
   assign q_bin = qi;
1556
endmodule
1557
//////////////////////////////////////////////////////////////////////
1558
////                                                              ////
1559
////  Versatile library, counters                                 ////
1560
////                                                              ////
1561
////  Description                                                 ////
1562
////  counters                                                    ////
1563
////                                                              ////
1564
////                                                              ////
1565
////  To Do:                                                      ////
1566
////   - add more counters                                        ////
1567
////                                                              ////
1568
////  Author(s):                                                  ////
1569
////      - Michael Unneback, unneback@opencores.org              ////
1570
////        ORSoC AB                                              ////
1571
////                                                              ////
1572
//////////////////////////////////////////////////////////////////////
1573
////                                                              ////
1574
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1575
////                                                              ////
1576
//// This source file may be used and distributed without         ////
1577
//// restriction provided that this copyright statement is not    ////
1578
//// removed from the file and that any derivative work contains  ////
1579
//// the original copyright notice and the associated disclaimer. ////
1580
////                                                              ////
1581
//// This source file is free software; you can redistribute it   ////
1582
//// and/or modify it under the terms of the GNU Lesser General   ////
1583
//// Public License as published by the Free Software Foundation; ////
1584
//// either version 2.1 of the License, or (at your option) any   ////
1585
//// later version.                                               ////
1586
////                                                              ////
1587
//// This source is distributed in the hope that it will be       ////
1588
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1589
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1590
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1591
//// details.                                                     ////
1592
////                                                              ////
1593
//// You should have received a copy of the GNU Lesser General    ////
1594
//// Public License along with this source; if not, download it   ////
1595
//// from http://www.opencores.org/lgpl.shtml                     ////
1596
////                                                              ////
1597
//////////////////////////////////////////////////////////////////////
1598 18 unneback
module vl_cnt_shreg_wrap ( q, rst, clk);
1599 6 unneback
   parameter length = 4;
1600
   output reg [0:length-1] q;
1601
   input rst;
1602
   input clk;
1603
    always @ (posedge clk or posedge rst)
1604
    if (rst)
1605
        q <= {1'b1,{length-1{1'b0}}};
1606
    else
1607
        q <= {q[length-1],q[0:length-2]};
1608
endmodule
1609 18 unneback
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
1610 6 unneback
   parameter length = 4;
1611
   input cke;
1612
   output reg [0:length-1] q;
1613
   input rst;
1614
   input clk;
1615
    always @ (posedge clk or posedge rst)
1616
    if (rst)
1617
        q <= {1'b1,{length-1{1'b0}}};
1618
    else
1619
        if (cke)
1620
            q <= {q[length-1],q[0:length-2]};
1621
endmodule
1622 18 unneback
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
1623 6 unneback
   parameter length = 4;
1624
   input cke, clear;
1625
   output reg [0:length-1] q;
1626
   input rst;
1627
   input clk;
1628
    always @ (posedge clk or posedge rst)
1629
    if (rst)
1630
        q <= {1'b1,{length-1{1'b0}}};
1631
    else
1632
        if (cke)
1633
            if (clear)
1634
                q <= {1'b1,{length-1{1'b0}}};
1635
            else
1636
                q <= q >> 1;
1637
endmodule
1638 18 unneback
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
1639 6 unneback
   parameter length = 4;
1640
   input cke, clear;
1641
   output reg [0:length-1] q;
1642
   input rst;
1643
   input clk;
1644
    always @ (posedge clk or posedge rst)
1645
    if (rst)
1646
        q <= {1'b1,{length-1{1'b0}}};
1647
    else
1648
        if (cke)
1649
            if (clear)
1650
                q <= {1'b1,{length-1{1'b0}}};
1651
            else
1652
            q <= {q[length-1],q[0:length-2]};
1653
endmodule
1654
//////////////////////////////////////////////////////////////////////
1655
////                                                              ////
1656
////  Versatile library, memories                                 ////
1657
////                                                              ////
1658
////  Description                                                 ////
1659
////  memories                                                    ////
1660
////                                                              ////
1661
////                                                              ////
1662
////  To Do:                                                      ////
1663
////   - add more memory types                                    ////
1664
////                                                              ////
1665
////  Author(s):                                                  ////
1666
////      - Michael Unneback, unneback@opencores.org              ////
1667
////        ORSoC AB                                              ////
1668
////                                                              ////
1669
//////////////////////////////////////////////////////////////////////
1670
////                                                              ////
1671
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1672
////                                                              ////
1673
//// This source file may be used and distributed without         ////
1674
//// restriction provided that this copyright statement is not    ////
1675
//// removed from the file and that any derivative work contains  ////
1676
//// the original copyright notice and the associated disclaimer. ////
1677
////                                                              ////
1678
//// This source file is free software; you can redistribute it   ////
1679
//// and/or modify it under the terms of the GNU Lesser General   ////
1680
//// Public License as published by the Free Software Foundation; ////
1681
//// either version 2.1 of the License, or (at your option) any   ////
1682
//// later version.                                               ////
1683
////                                                              ////
1684
//// This source is distributed in the hope that it will be       ////
1685
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1686
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1687
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1688
//// details.                                                     ////
1689
////                                                              ////
1690
//// You should have received a copy of the GNU Lesser General    ////
1691
//// Public License along with this source; if not, download it   ////
1692
//// from http://www.opencores.org/lgpl.shtml                     ////
1693
////                                                              ////
1694
//////////////////////////////////////////////////////////////////////
1695
/// ROM
1696 7 unneback
module vl_rom_init ( adr, q, clk);
1697
   parameter data_width = 32;
1698
   parameter addr_width = 8;
1699
   input [(addr_width-1):0]       adr;
1700
   output reg [(data_width-1):0] q;
1701
   input                         clk;
1702
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
1703
   parameter memory_file = "vl_rom.vmem";
1704
   initial
1705
     begin
1706
        $readmemh(memory_file, rom);
1707
     end
1708
   always @ (posedge clk)
1709
     q <= rom[adr];
1710
endmodule
1711 14 unneback
/*
1712 7 unneback
module vl_rom ( adr, q, clk);
1713 6 unneback
parameter data_width = 32;
1714
parameter addr_width = 4;
1715
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
1716
    {32'h18000000},
1717
    {32'hA8200000},
1718
    {32'hA8200000},
1719
    {32'hA8200000},
1720
    {32'h44003000},
1721
    {32'h15000000},
1722
    {32'h15000000},
1723
    {32'h15000000},
1724
    {32'h15000000},
1725
    {32'h15000000},
1726
    {32'h15000000},
1727
    {32'h15000000},
1728
    {32'h15000000},
1729
    {32'h15000000},
1730
    {32'h15000000},
1731
    {32'h15000000}};
1732 7 unneback
input [addr_width-1:0] adr;
1733 6 unneback
output reg [data_width-1:0] q;
1734
input clk;
1735
always @ (posedge clk)
1736 7 unneback
    q <= data[adr];
1737 6 unneback
endmodule
1738 14 unneback
*/
1739 6 unneback
// Single port RAM
1740
module vl_ram ( d, adr, we, q, clk);
1741
   parameter data_width = 32;
1742
   parameter addr_width = 8;
1743
   input [(data_width-1):0]      d;
1744
   input [(addr_width-1):0]       adr;
1745
   input                         we;
1746 7 unneback
   output reg [(data_width-1):0] q;
1747 6 unneback
   input                         clk;
1748
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
1749 7 unneback
   parameter init = 0;
1750
   parameter memory_file = "vl_ram.vmem";
1751
   generate if (init) begin : init_mem
1752
   initial
1753
     begin
1754
        $readmemh(memory_file, ram);
1755
     end
1756
   end
1757
   endgenerate
1758 6 unneback
   always @ (posedge clk)
1759
   begin
1760
   if (we)
1761
     ram[adr] <= d;
1762
   q <= ram[adr];
1763
   end
1764
endmodule
1765 7 unneback
module vl_ram_be ( d, adr, be, we, q, clk);
1766
   parameter data_width = 32;
1767
   parameter addr_width = 8;
1768
   input [(data_width-1):0]      d;
1769
   input [(addr_width-1):0]       adr;
1770
   input [(addr_width/4)-1:0]    be;
1771
   input                         we;
1772
   output reg [(data_width-1):0] q;
1773
   input                         clk;
1774
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
1775
   parameter init = 0;
1776
   parameter memory_file = "vl_ram.vmem";
1777
   generate if (init) begin : init_mem
1778
   initial
1779
     begin
1780
        $readmemh(memory_file, ram);
1781
     end
1782
   end
1783
   endgenerate
1784
   genvar i;
1785
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
1786
      always @ (posedge clk)
1787
      if (we & be[i])
1788
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
1789
   end
1790
   endgenerate
1791
   always @ (posedge clk)
1792
      q <= ram[adr];
1793
endmodule
1794 6 unneback
// Dual port RAM
1795
// ACTEL FPGA should not use logic to handle rw collision
1796 7 unneback
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1797 6 unneback
   parameter data_width = 32;
1798
   parameter addr_width = 8;
1799
   input [(data_width-1):0]      d_a;
1800
   input [(addr_width-1):0]       adr_a;
1801
   input [(addr_width-1):0]       adr_b;
1802
   input                         we_a;
1803
   output [(data_width-1):0]      q_b;
1804
   input                         clk_a, clk_b;
1805
   reg [(addr_width-1):0]         adr_b_reg;
1806
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
1807 7 unneback
   parameter init = 0;
1808
   parameter memory_file = "vl_ram.vmem";
1809
   generate if (init) begin : init_mem
1810
   initial
1811
     begin
1812
        $readmemh(memory_file, ram);
1813
     end
1814
   end
1815
   endgenerate
1816 6 unneback
   always @ (posedge clk_a)
1817
   if (we_a)
1818
     ram[adr_a] <= d_a;
1819
   always @ (posedge clk_b)
1820
   adr_b_reg <= adr_b;
1821
   assign q_b = ram[adr_b_reg];
1822
endmodule
1823 7 unneback
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1824 6 unneback
   parameter data_width = 32;
1825
   parameter addr_width = 8;
1826
   input [(data_width-1):0]      d_a;
1827
   input [(addr_width-1):0]       adr_a;
1828
   input [(addr_width-1):0]       adr_b;
1829
   input                         we_a;
1830
   output [(data_width-1):0]      q_b;
1831
   output reg [(data_width-1):0] q_a;
1832
   input                         clk_a, clk_b;
1833
   reg [(data_width-1):0]         q_b;
1834
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
1835 7 unneback
   parameter init = 0;
1836
   parameter memory_file = "vl_ram.vmem";
1837
   generate if (init) begin : init_mem
1838
   initial
1839
     begin
1840
        $readmemh(memory_file, ram);
1841
     end
1842
   end
1843
   endgenerate
1844 6 unneback
   always @ (posedge clk_a)
1845
     begin
1846
        q_a <= ram[adr_a];
1847
        if (we_a)
1848
             ram[adr_a] <= d_a;
1849
     end
1850
   always @ (posedge clk_b)
1851
          q_b <= ram[adr_b];
1852
endmodule
1853 7 unneback
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
1854 6 unneback
   parameter data_width = 32;
1855
   parameter addr_width = 8;
1856
   input [(data_width-1):0]      d_a;
1857
   input [(addr_width-1):0]       adr_a;
1858
   input [(addr_width-1):0]       adr_b;
1859
   input                         we_a;
1860
   output [(data_width-1):0]      q_b;
1861
   input [(data_width-1):0]       d_b;
1862
   output reg [(data_width-1):0] q_a;
1863
   input                         we_b;
1864
   input                         clk_a, clk_b;
1865
   reg [(data_width-1):0]         q_b;
1866
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
1867 7 unneback
   parameter init = 0;
1868
   parameter memory_file = "vl_ram.vmem";
1869
   generate if (init) begin : init_mem
1870
   initial
1871
     begin
1872
        $readmemh(memory_file, ram);
1873
     end
1874
   end
1875
   endgenerate
1876 6 unneback
   always @ (posedge clk_a)
1877
     begin
1878
        q_a <= ram[adr_a];
1879
        if (we_a)
1880
             ram[adr_a] <= d_a;
1881
     end
1882
   always @ (posedge clk_b)
1883
     begin
1884
        q_b <= ram[adr_b];
1885
        if (we_b)
1886
          ram[adr_b] <= d_b;
1887
     end
1888
endmodule
1889
// Content addresable memory, CAM
1890
// FIFO
1891
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
1892 11 unneback
   parameter addr_width = 4;
1893
   parameter N = addr_width-1;
1894 6 unneback
   parameter Q1 = 2'b00;
1895
   parameter Q2 = 2'b01;
1896
   parameter Q3 = 2'b11;
1897
   parameter Q4 = 2'b10;
1898
   parameter going_empty = 1'b0;
1899
   parameter going_full  = 1'b1;
1900
   input [N:0]  wptr, rptr;
1901 14 unneback
   output       fifo_empty;
1902 6 unneback
   output       fifo_full;
1903
   input        wclk, rclk, rst;
1904
   wire direction;
1905
   reg  direction_set, direction_clr;
1906
   wire async_empty, async_full;
1907
   wire fifo_full2;
1908 14 unneback
   wire fifo_empty2;
1909 6 unneback
   // direction_set
1910
   always @ (wptr[N:N-1] or rptr[N:N-1])
1911
     case ({wptr[N:N-1],rptr[N:N-1]})
1912
       {Q1,Q2} : direction_set <= 1'b1;
1913
       {Q2,Q3} : direction_set <= 1'b1;
1914
       {Q3,Q4} : direction_set <= 1'b1;
1915
       {Q4,Q1} : direction_set <= 1'b1;
1916
       default : direction_set <= 1'b0;
1917
     endcase
1918
   // direction_clear
1919
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
1920
     if (rst)
1921
       direction_clr <= 1'b1;
1922
     else
1923
       case ({wptr[N:N-1],rptr[N:N-1]})
1924
         {Q2,Q1} : direction_clr <= 1'b1;
1925
         {Q3,Q2} : direction_clr <= 1'b1;
1926
         {Q4,Q3} : direction_clr <= 1'b1;
1927
         {Q1,Q4} : direction_clr <= 1'b1;
1928
         default : direction_clr <= 1'b0;
1929
       endcase
1930 18 unneback
    vl_dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
1931 6 unneback
   assign async_empty = (wptr == rptr) && (direction==going_empty);
1932
   assign async_full  = (wptr == rptr) && (direction==going_full);
1933 18 unneback
    vl_dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
1934
    vl_dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
1935 6 unneback
/*
1936
   always @ (posedge wclk or posedge rst or posedge async_full)
1937
     if (rst)
1938
       {fifo_full, fifo_full2} <= 2'b00;
1939
     else if (async_full)
1940
       {fifo_full, fifo_full2} <= 2'b11;
1941
     else
1942
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
1943
*/
1944 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
1945 6 unneback
     if (async_empty)
1946
       {fifo_empty, fifo_empty2} <= 2'b11;
1947
     else
1948 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
1949 18 unneback
    vl_dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
1950
    vl_dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
1951 6 unneback
endmodule // async_comp
1952
module vl_fifo_1r1w_async (
1953
    d, wr, fifo_full, wr_clk, wr_rst,
1954
    q, rd, fifo_empty, rd_clk, rd_rst
1955
    );
1956
parameter data_width = 18;
1957
parameter addr_width = 4;
1958
// write side
1959
input  [data_width-1:0] d;
1960
input                   wr;
1961
output                  fifo_full;
1962
input                   wr_clk;
1963
input                   wr_rst;
1964
// read side
1965
output [data_width-1:0] q;
1966
input                   rd;
1967
output                  fifo_empty;
1968
input                   rd_clk;
1969
input                   rd_rst;
1970
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
1971 18 unneback
vl_cnt_gray_ce_bin
1972 6 unneback
    # ( .length(addr_width))
1973
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
1974 18 unneback
vl_cnt_gray_ce_bin
1975 6 unneback
    # (.length(addr_width))
1976 23 unneback
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
1977 7 unneback
vl_dpram_1r1w
1978 6 unneback
    # (.data_width(data_width), .addr_width(addr_width))
1979
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
1980
vl_fifo_cmp_async
1981
    # (.addr_width(addr_width))
1982
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
1983
endmodule
1984 8 unneback
module vl_fifo_2r2w_async (
1985 6 unneback
    // a side
1986
    a_d, a_wr, a_fifo_full,
1987
    a_q, a_rd, a_fifo_empty,
1988
    a_clk, a_rst,
1989
    // b side
1990
    b_d, b_wr, b_fifo_full,
1991
    b_q, b_rd, b_fifo_empty,
1992
    b_clk, b_rst
1993
    );
1994
parameter data_width = 18;
1995
parameter addr_width = 4;
1996
// a side
1997
input  [data_width-1:0] a_d;
1998
input                   a_wr;
1999
output                  a_fifo_full;
2000
output [data_width-1:0] a_q;
2001
input                   a_rd;
2002
output                  a_fifo_empty;
2003
input                   a_clk;
2004
input                   a_rst;
2005
// b side
2006
input  [data_width-1:0] b_d;
2007
input                   b_wr;
2008
output                  b_fifo_full;
2009
output [data_width-1:0] b_q;
2010
input                   b_rd;
2011
output                  b_fifo_empty;
2012
input                   b_clk;
2013
input                   b_rst;
2014
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
2015
vl_fifo_1r1w_async_a (
2016
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
2017
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
2018
    );
2019
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
2020
vl_fifo_1r1w_async_b (
2021
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
2022
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
2023
    );
2024
endmodule
2025 8 unneback
module vl_fifo_2r2w_async_simplex (
2026 6 unneback
    // a side
2027
    a_d, a_wr, a_fifo_full,
2028
    a_q, a_rd, a_fifo_empty,
2029
    a_clk, a_rst,
2030
    // b side
2031
    b_d, b_wr, b_fifo_full,
2032
    b_q, b_rd, b_fifo_empty,
2033
    b_clk, b_rst
2034
    );
2035
parameter data_width = 18;
2036
parameter addr_width = 4;
2037
// a side
2038
input  [data_width-1:0] a_d;
2039
input                   a_wr;
2040
output                  a_fifo_full;
2041
output [data_width-1:0] a_q;
2042
input                   a_rd;
2043
output                  a_fifo_empty;
2044
input                   a_clk;
2045
input                   a_rst;
2046
// b side
2047
input  [data_width-1:0] b_d;
2048
input                   b_wr;
2049
output                  b_fifo_full;
2050
output [data_width-1:0] b_q;
2051
input                   b_rd;
2052
output                  b_fifo_empty;
2053
input                   b_clk;
2054
input                   b_rst;
2055
// adr_gen
2056
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
2057
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
2058
// dpram
2059
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
2060 18 unneback
vl_cnt_gray_ce_bin
2061 6 unneback
    # ( .length(addr_width))
2062
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
2063 18 unneback
vl_cnt_gray_ce_bin
2064 6 unneback
    # (.length(addr_width))
2065
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
2066 18 unneback
vl_cnt_gray_ce_bin
2067 6 unneback
    # ( .length(addr_width))
2068
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
2069 18 unneback
vl_cnt_gray_ce_bin
2070 6 unneback
    # (.length(addr_width))
2071
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
2072
// mux read or write adr to DPRAM
2073
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
2074
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
2075 11 unneback
vl_dpram_2r2w
2076 6 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
2077
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
2078
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
2079 11 unneback
vl_fifo_cmp_async
2080 6 unneback
    # (.addr_width(addr_width))
2081
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
2082 11 unneback
vl_fifo_cmp_async
2083 6 unneback
    # (.addr_width(addr_width))
2084
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
2085
endmodule
2086 12 unneback
//////////////////////////////////////////////////////////////////////
2087
////                                                              ////
2088
////  Versatile library, wishbone stuff                           ////
2089
////                                                              ////
2090
////  Description                                                 ////
2091
////  Wishbone compliant modules                                  ////
2092
////                                                              ////
2093
////                                                              ////
2094
////  To Do:                                                      ////
2095
////   -                                                          ////
2096
////                                                              ////
2097
////  Author(s):                                                  ////
2098
////      - Michael Unneback, unneback@opencores.org              ////
2099
////        ORSoC AB                                              ////
2100
////                                                              ////
2101
//////////////////////////////////////////////////////////////////////
2102
////                                                              ////
2103
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2104
////                                                              ////
2105
//// This source file may be used and distributed without         ////
2106
//// restriction provided that this copyright statement is not    ////
2107
//// removed from the file and that any derivative work contains  ////
2108
//// the original copyright notice and the associated disclaimer. ////
2109
////                                                              ////
2110
//// This source file is free software; you can redistribute it   ////
2111
//// and/or modify it under the terms of the GNU Lesser General   ////
2112
//// Public License as published by the Free Software Foundation; ////
2113
//// either version 2.1 of the License, or (at your option) any   ////
2114
//// later version.                                               ////
2115
////                                                              ////
2116
//// This source is distributed in the hope that it will be       ////
2117
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2118
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2119
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2120
//// details.                                                     ////
2121
////                                                              ////
2122
//// You should have received a copy of the GNU Lesser General    ////
2123
//// Public License along with this source; if not, download it   ////
2124
//// from http://www.opencores.org/lgpl.shtml                     ////
2125
////                                                              ////
2126
//////////////////////////////////////////////////////////////////////
2127
// async wb3 - wb3 bridge
2128
`timescale 1ns/1ns
2129 18 unneback
module vl_wb3wb3_bridge (
2130 12 unneback
        // wishbone slave side
2131
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
2132
        // wishbone master side
2133
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
2134
input [31:0] wbs_dat_i;
2135
input [31:2] wbs_adr_i;
2136
input [3:0]  wbs_sel_i;
2137
input [1:0]  wbs_bte_i;
2138
input [2:0]  wbs_cti_i;
2139
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
2140
output [31:0] wbs_dat_o;
2141 14 unneback
output wbs_ack_o;
2142 12 unneback
input wbs_clk, wbs_rst;
2143
output [31:0] wbm_dat_o;
2144
output reg [31:2] wbm_adr_o;
2145
output [3:0]  wbm_sel_o;
2146
output reg [1:0]  wbm_bte_o;
2147
output reg [2:0]  wbm_cti_o;
2148 14 unneback
output reg wbm_we_o;
2149
output wbm_cyc_o;
2150 12 unneback
output wbm_stb_o;
2151
input [31:0]  wbm_dat_i;
2152
input wbm_ack_i;
2153
input wbm_clk, wbm_rst;
2154
parameter addr_width = 4;
2155
// bte
2156
parameter linear       = 2'b00;
2157
parameter wrap4        = 2'b01;
2158
parameter wrap8        = 2'b10;
2159
parameter wrap16       = 2'b11;
2160
// cti
2161
parameter classic      = 3'b000;
2162
parameter incburst     = 3'b010;
2163
parameter endofburst   = 3'b111;
2164
parameter wbs_adr  = 1'b0;
2165
parameter wbs_data = 1'b1;
2166
parameter wbm_adr0 = 2'b00;
2167
parameter wbm_adr1 = 2'b01;
2168
parameter wbm_data = 2'b10;
2169
reg [1:0] wbs_bte_reg;
2170
reg wbs;
2171
wire wbs_eoc_alert, wbm_eoc_alert;
2172
reg wbs_eoc, wbm_eoc;
2173
reg [1:0] wbm;
2174 14 unneback
wire [1:16] wbs_count, wbm_count;
2175 12 unneback
wire [35:0] a_d, a_q, b_d, b_q;
2176
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
2177
reg a_rd_reg;
2178
wire b_rd_adr, b_rd_data;
2179 14 unneback
wire b_rd_data_reg;
2180
wire [35:0] temp;
2181 12 unneback
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
2182
always @ (posedge wbs_clk or posedge wbs_rst)
2183
if (wbs_rst)
2184
        wbs_eoc <= 1'b0;
2185
else
2186
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
2187
                wbs_eoc <= wbs_bte_i==linear;
2188
        else if (wbs_eoc_alert & (a_rd | a_wr))
2189
                wbs_eoc <= 1'b1;
2190 18 unneback
vl_cnt_shreg_ce_clear # ( .length(16))
2191 12 unneback
    cnt0 (
2192
        .cke(wbs_ack_o),
2193
        .clear(wbs_eoc),
2194
        .q(wbs_count),
2195
        .rst(wbs_rst),
2196
        .clk(wbs_clk));
2197
always @ (posedge wbs_clk or posedge wbs_rst)
2198
if (wbs_rst)
2199
        wbs <= wbs_adr;
2200
else
2201
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & !a_fifo_full)
2202
                wbs <= wbs_data;
2203
        else if (wbs_eoc & wbs_ack_o)
2204
                wbs <= wbs_adr;
2205
// wbs FIFO
2206
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,wbs_bte_i,wbs_cti_i} : {wbs_dat_i,wbs_sel_i};
2207
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & !a_fifo_full :
2208
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
2209
              1'b0;
2210
assign a_rd = !a_fifo_empty;
2211
always @ (posedge wbs_clk or posedge wbs_rst)
2212
if (wbs_rst)
2213
        a_rd_reg <= 1'b0;
2214
else
2215
        a_rd_reg <= a_rd;
2216
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
2217
assign wbs_dat_o = a_q[35:4];
2218
always @ (posedge wbs_clk or posedge wbs_rst)
2219
if (wbs_rst)
2220 13 unneback
        wbs_bte_reg <= 2'b00;
2221 12 unneback
else
2222 13 unneback
        wbs_bte_reg <= wbs_bte_i;
2223 12 unneback
// wbm FIFO
2224
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
2225
always @ (posedge wbm_clk or posedge wbm_rst)
2226
if (wbm_rst)
2227
        wbm_eoc <= 1'b0;
2228
else
2229
        if (wbm==wbm_adr0 & !b_fifo_empty)
2230
                wbm_eoc <= b_q[4:3] == linear;
2231
        else if (wbm_eoc_alert & wbm_ack_i)
2232
                wbm_eoc <= 1'b1;
2233
always @ (posedge wbm_clk or posedge wbm_rst)
2234
if (wbm_rst)
2235
        wbm <= wbm_adr0;
2236
else
2237
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
2238
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
2239
        (wbm==wbm_adr1 & !wbm_we_o) |
2240
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
2241
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
2242
assign b_d = {wbm_dat_i,4'b1111};
2243
assign b_wr = !wbm_we_o & wbm_ack_i;
2244
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
2245
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
2246
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
2247
                   1'b0;
2248
assign b_rd = b_rd_adr | b_rd_data;
2249 18 unneback
vl_dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
2250
vl_dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
2251 12 unneback
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
2252 18 unneback
vl_cnt_shreg_ce_clear # ( .length(16))
2253 12 unneback
    cnt1 (
2254
        .cke(wbm_ack_i),
2255
        .clear(wbm_eoc),
2256
        .q(wbm_count),
2257
        .rst(wbm_rst),
2258
        .clk(wbm_clk));
2259
assign wbm_cyc_o = wbm==wbm_data;
2260
assign wbm_stb_o = (wbm==wbm_data & wbm_we_o) ? !b_fifo_empty :
2261
                   (wbm==wbm_data) ? 1'b1 :
2262
                   1'b0;
2263
always @ (posedge wbm_clk or posedge wbm_rst)
2264
if (wbm_rst)
2265
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
2266
else begin
2267
        if (wbm==wbm_adr0 & !b_fifo_empty)
2268
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
2269
        else if (wbm_eoc_alert & wbm_ack_i)
2270
                wbm_cti_o <= endofburst;
2271
end
2272
//async_fifo_dw_simplex_top
2273
vl_fifo_2r2w_async_simplex
2274
# ( .data_width(36), .addr_width(addr_width))
2275
fifo (
2276
    // a side
2277
    .a_d(a_d),
2278
    .a_wr(a_wr),
2279
    .a_fifo_full(a_fifo_full),
2280
    .a_q(a_q),
2281
    .a_rd(a_rd),
2282
    .a_fifo_empty(a_fifo_empty),
2283
    .a_clk(wbs_clk),
2284
    .a_rst(wbs_rst),
2285
    // b side
2286
    .b_d(b_d),
2287
    .b_wr(b_wr),
2288
    .b_fifo_full(b_fifo_full),
2289
    .b_q(b_q),
2290
    .b_rd(b_rd),
2291
    .b_fifo_empty(b_fifo_empty),
2292
    .b_clk(wbm_clk),
2293
    .b_rst(wbm_rst)
2294
    );
2295
endmodule
2296 17 unneback
// WB ROM
2297 18 unneback
module vl_wb_boot_rom (
2298 17 unneback
    wb_adr_i, wb_stb_i, wb_cyc_i,
2299 18 unneback
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
2300
    parameter adr_hi = 31;
2301
    parameter adr_lo = 28;
2302
    parameter adr_sel = 4'hf;
2303
    parameter addr_width = 5;
2304 17 unneback
`ifndef BOOT_ROM
2305
`define BOOT_ROM "boot_rom.v"
2306
`endif
2307 18 unneback
    input [adr_hi:2]    wb_adr_i;
2308
    input               wb_stb_i;
2309
    input               wb_cyc_i;
2310
    output [31:0]        wb_dat_o;
2311
    output              wb_ack_o;
2312
    output              hit_o;
2313
    input               wb_clk;
2314
    input               wb_rst;
2315
    wire hit;
2316
    reg [31:0] wb_dat;
2317
    reg wb_ack;
2318
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
2319 17 unneback
always @ (posedge wb_clk or posedge wb_rst)
2320
    if (wb_rst)
2321 18 unneback
        wb_dat <= 32'h15000000;
2322 17 unneback
    else
2323 18 unneback
         case (wb_adr_i[addr_width-1:2])
2324 17 unneback
`include `BOOT_ROM
2325
           /*
2326
            // Zero r0 and jump to 0x00000100
2327 18 unneback
 
2328
            1 : wb_dat <= 32'hA8200000;
2329
            2 : wb_dat <= 32'hA8C00100;
2330
            3 : wb_dat <= 32'h44003000;
2331
            4 : wb_dat <= 32'h15000000;
2332 17 unneback
            */
2333
           default:
2334 18 unneback
             wb_dat <= 32'h00000000;
2335 17 unneback
         endcase // case (wb_adr_i)
2336
always @ (posedge wb_clk or posedge wb_rst)
2337
    if (wb_rst)
2338 18 unneback
        wb_ack <= 1'b0;
2339 17 unneback
    else
2340 18 unneback
        wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
2341
assign hit_o = hit;
2342
assign wb_dat_o = wb_dat & {32{wb_ack}};
2343
assign wb_ack_o = wb_ack;
2344 17 unneback
endmodule
2345 18 unneback
//////////////////////////////////////////////////////////////////////
2346
////                                                              ////
2347
////  Arithmetic functions                                        ////
2348
////                                                              ////
2349
////  Description                                                 ////
2350
////  Arithmetic functions for ALU and DSP                        ////
2351
////                                                              ////
2352
////                                                              ////
2353
////  To Do:                                                      ////
2354
////   -                                                          ////
2355
////                                                              ////
2356
////  Author(s):                                                  ////
2357
////      - Michael Unneback, unneback@opencores.org              ////
2358
////        ORSoC AB                                              ////
2359
////                                                              ////
2360
//////////////////////////////////////////////////////////////////////
2361
////                                                              ////
2362
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2363
////                                                              ////
2364
//// This source file may be used and distributed without         ////
2365
//// restriction provided that this copyright statement is not    ////
2366
//// removed from the file and that any derivative work contains  ////
2367
//// the original copyright notice and the associated disclaimer. ////
2368
////                                                              ////
2369
//// This source file is free software; you can redistribute it   ////
2370
//// and/or modify it under the terms of the GNU Lesser General   ////
2371
//// Public License as published by the Free Software Foundation; ////
2372
//// either version 2.1 of the License, or (at your option) any   ////
2373
//// later version.                                               ////
2374
////                                                              ////
2375
//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
2386
// signed multiplication
2387
module vl_mults (a,b,p);
2388
parameter operand_a_width = 18;
2389
parameter operand_b_width = 18;
2390
parameter result_hi = 35;
2391
parameter result_lo = 0;
2392
input [operand_a_width-1:0] a;
2393
input [operand_b_width-1:0] b;
2394
output [result_hi:result_lo] p;
2395
wire signed [operand_a_width-1:0] ai;
2396
wire signed [operand_b_width-1:0] bi;
2397
wire signed [operand_a_width+operand_b_width-1:0] result;
2398
    assign ai = a;
2399
    assign bi = b;
2400
    assign result = ai * bi;
2401
    assign p = result[result_hi:result_lo];
2402
endmodule
2403
module vl_mults18x18 (a,b,p);
2404
input [17:0] a,b;
2405
output [35:0] p;
2406
vl_mult
2407
    # (.operand_a_width(18), .operand_b_width(18))
2408
    mult0 (.a(a), .b(b), .p(p));
2409
endmodule
2410
// unsigned multiplication
2411
module vl_mult (a,b,p);
2412
parameter operand_a_width = 18;
2413
parameter operand_b_width = 18;
2414
parameter result_hi = 35;
2415
parameter result_lo = 0;
2416
input [operand_a_width-1:0] a;
2417
input [operand_b_width-1:0] b;
2418
output [result_hi:result_hi] p;
2419
wire [operand_a_width+operand_b_width-1:0] result;
2420
    assign result = a * b;
2421
    assign p = result[result_hi:result_lo];
2422
endmodule
2423
// shift unit
2424
// supporting the following shift functions
2425
//   SLL
2426
//   SRL
2427
//   SRA
2428
module vl_shift_unit_32( din, s, dout, opcode);
2429
input [31:0] din; // data in operand
2430
input [4:0] s; // shift operand
2431
input [1:0] opcode;
2432
output [31:0] dout;
2433
parameter opcode_sll = 2'b00;
2434
//parameter opcode_srl = 2'b01;
2435
parameter opcode_sra = 2'b10;
2436
//parameter opcode_ror = 2'b11;
2437
wire sll, sra;
2438
assign sll = opcode == opcode_sll;
2439
assign sra = opcode == opcode_sra;
2440
wire [15:1] s1;
2441
wire [3:0] sign;
2442
wire [7:0] tmp [0:3];
2443
// first stage is multiplier based
2444
// shift operand as fractional 8.7
2445
assign s1[15] = sll & s[2:0]==3'd7;
2446
assign s1[14] = sll & s[2:0]==3'd6;
2447
assign s1[13] = sll & s[2:0]==3'd5;
2448
assign s1[12] = sll & s[2:0]==3'd4;
2449
assign s1[11] = sll & s[2:0]==3'd3;
2450
assign s1[10] = sll & s[2:0]==3'd2;
2451
assign s1[ 9] = sll & s[2:0]==3'd1;
2452
assign s1[ 8] = s[2:0]==3'd0;
2453
assign s1[ 7] = !sll & s[2:0]==3'd1;
2454
assign s1[ 6] = !sll & s[2:0]==3'd2;
2455
assign s1[ 5] = !sll & s[2:0]==3'd3;
2456
assign s1[ 4] = !sll & s[2:0]==3'd4;
2457
assign s1[ 3] = !sll & s[2:0]==3'd5;
2458
assign s1[ 2] = !sll & s[2:0]==3'd6;
2459
assign s1[ 1] = !sll & s[2:0]==3'd7;
2460
assign sign[3] = din[31] & sra;
2461
assign sign[2] = sign[3] & (&din[31:24]);
2462
assign sign[1] = sign[2] & (&din[23:16]);
2463
assign sign[0] = sign[1] & (&din[15:8]);
2464
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte3 ( .a({sign[3], {8{sign[3]}},din[31:24], din[23:16]}), .b({1'b0,s1}), .p(tmp[3]));
2465
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte2 ( .a({sign[2], din[31:24]  ,din[23:16],  din[15:8]}), .b({1'b0,s1}), .p(tmp[2]));
2466
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte1 ( .a({sign[1], din[23:16]  ,din[15:8],   din[7:0]}), .b({1'b0,s1}), .p(tmp[1]));
2467
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte0 ( .a({sign[0], din[15:8]   ,din[7:0],    8'h00}),      .b({1'b0,s1}), .p(tmp[0]));
2468
// second stage is multiplexer based
2469
// shift on byte level
2470
// mux byte 3
2471
assign dout[31:24] = (s[4:3]==2'b00) ? tmp[3] :
2472
                     (sll & s[4:3]==2'b01) ? tmp[2] :
2473
                     (sll & s[4:3]==2'b10) ? tmp[1] :
2474
                     (sll & s[4:3]==2'b11) ? tmp[0] :
2475
                     {8{sign[3]}};
2476
// mux byte 2
2477
assign dout[23:16] = (s[4:3]==2'b00) ? tmp[2] :
2478
                     (sll & s[4:3]==2'b01) ? tmp[1] :
2479
                     (sll & s[4:3]==2'b10) ? tmp[0] :
2480
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
2481
                     (s[4:3]==2'b01) ? tmp[3] :
2482
                     {8{sign[3]}};
2483
// mux byte 1
2484
assign dout[15:8]  = (s[4:3]==2'b00) ? tmp[1] :
2485
                     (sll & s[4:3]==2'b01) ? tmp[0] :
2486
                     (sll & s[4:3]==2'b10) ? {8{1'b0}} :
2487
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
2488
                     (s[4:3]==2'b01) ? tmp[2] :
2489
                     (s[4:3]==2'b10) ? tmp[3] :
2490
                     {8{sign[3