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1 6 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
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////  Versatile library, clock and reset                          ////
4
////                                                              ////
5
////  Description                                                 ////
6
////  Logic related to clock and reset                            ////
7
////                                                              ////
8
////                                                              ////
9
////  To Do:                                                      ////
10
////   - add more different registers                             ////
11
////                                                              ////
12
////  Author(s):                                                  ////
13
////      - Michael Unneback, unneback@opencores.org              ////
14
////        ORSoC AB                                              ////
15
////                                                              ////
16
//////////////////////////////////////////////////////////////////////
17
////                                                              ////
18
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
19
////                                                              ////
20
//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
36
////                                                              ////
37
//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
// Global buffer
43
// usage:
44
// use to enable global buffers for high fan out signals such as clock and reset
45
`timescale 1 ns/100 ps
46
// Version: 8.4 8.4.0.33
47
module gbuf(GL,CLK);
48
output GL;
49
input  CLK;
50
    wire GND;
51
    GND GND_1_net(.Y(GND));
52
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
53
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
54
endmodule
55
`timescale 1 ns/1 ns
56
module vl_gbuf ( i, o);
57
input i;
58
output o;
59
`ifdef SIM_GBUF
60
assign o=i;
61
`else
62
gbuf gbuf_i0 ( .CLK(i), .GL(o));
63
`endif
64
endmodule
65
 //ACTEL
66
// sync reset
67 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
68 6 unneback
// output active high global reset sync with two DFFs 
69
`timescale 1 ns/100 ps
70
module vl_sync_rst ( rst_n_i, rst_o, clk);
71
input rst_n_i, clk;
72
output rst_o;
73 18 unneback
reg [1:0] tmp;
74 6 unneback
always @ (posedge clk or negedge rst_n_i)
75
if (!rst_n_i)
76 17 unneback
        tmp <= 2'b11;
77 6 unneback
else
78 17 unneback
        tmp <= {1'b0,tmp[0]};
79
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
80 6 unneback
endmodule
81
// vl_pll
82 17 unneback
`timescale 1 ps/1 ps
83 6 unneback
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
84
parameter index = 0;
85
parameter number_of_clk = 1;
86 17 unneback
parameter period_time_0 = 20000;
87
parameter period_time_1 = 20000;
88
parameter period_time_2 = 20000;
89
parameter lock_delay = 2000000;
90 6 unneback
input clk_i, rst_n_i;
91
output lock;
92
output reg [0:number_of_clk-1] clk_o;
93
output [0:number_of_clk-1] rst_o;
94
`ifdef SIM_PLL
95
always
96
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
97
generate if (number_of_clk > 1)
98
always
99
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
100
endgenerate
101
generate if (number_of_clk > 2)
102
always
103
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
104
endgenerate
105
genvar i;
106
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
107
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
108
end
109
endgenerate
110
assign #lock_delay lock = rst_n_i;
111
endmodule
112
`else
113
generate if (number_of_clk==1 & index==0) begin
114
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
115
end
116
endgenerate // index==0
117
generate if (number_of_clk==1 & index==1) begin
118
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
119
end
120
endgenerate // index==1
121
generate if (number_of_clk==1 & index==2) begin
122
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
123
end
124
endgenerate // index==2
125
generate if (number_of_clk==1 & index==3) begin
126
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
127
end
128
endgenerate // index==0
129
generate if (number_of_clk==2 & index==0) begin
130
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
131
end
132
endgenerate // index==0
133
generate if (number_of_clk==2 & index==1) begin
134
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
135
end
136
endgenerate // index==1
137
generate if (number_of_clk==2 & index==2) begin
138
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
139
end
140
endgenerate // index==2
141
generate if (number_of_clk==2 & index==3) begin
142
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
143
end
144
endgenerate // index==0
145
generate if (number_of_clk==3 & index==0) begin
146
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
147
end
148
endgenerate // index==0
149
generate if (number_of_clk==3 & index==1) begin
150
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
151
end
152
endgenerate // index==1
153
generate if (number_of_clk==3 & index==2) begin
154
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
155
end
156
endgenerate // index==2
157
generate if (number_of_clk==3 & index==3) begin
158
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
159
end
160
endgenerate // index==0
161
genvar i;
162
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
163
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
164
end
165
endgenerate
166
endmodule
167
`endif
168
 //actel
169
//////////////////////////////////////////////////////////////////////
170
////                                                              ////
171
////  Versatile library, registers                                ////
172
////                                                              ////
173
////  Description                                                 ////
174
////  Different type of registers                                 ////
175
////                                                              ////
176
////                                                              ////
177
////  To Do:                                                      ////
178
////   - add more different registers                             ////
179
////                                                              ////
180
////  Author(s):                                                  ////
181
////      - Michael Unneback, unneback@opencores.org              ////
182
////        ORSoC AB                                              ////
183
////                                                              ////
184
//////////////////////////////////////////////////////////////////////
185
////                                                              ////
186
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
187
////                                                              ////
188
//// This source file may be used and distributed without         ////
189
//// restriction provided that this copyright statement is not    ////
190
//// removed from the file and that any derivative work contains  ////
191
//// the original copyright notice and the associated disclaimer. ////
192
////                                                              ////
193
//// This source file is free software; you can redistribute it   ////
194
//// and/or modify it under the terms of the GNU Lesser General   ////
195
//// Public License as published by the Free Software Foundation; ////
196
//// either version 2.1 of the License, or (at your option) any   ////
197
//// later version.                                               ////
198
////                                                              ////
199
//// This source is distributed in the hope that it will be       ////
200
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
201
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
202
//// PURPOSE.  See the GNU Lesser General Public License for more ////
203
//// details.                                                     ////
204
////                                                              ////
205
//// You should have received a copy of the GNU Lesser General    ////
206
//// Public License along with this source; if not, download it   ////
207
//// from http://www.opencores.org/lgpl.shtml                     ////
208
////                                                              ////
209
//////////////////////////////////////////////////////////////////////
210 18 unneback
module vl_dff ( d, q, clk, rst);
211 6 unneback
        parameter width = 1;
212
        parameter reset_value = 0;
213
        input [width-1:0] d;
214
        input clk, rst;
215
        output reg [width-1:0] q;
216
        always @ (posedge clk or posedge rst)
217
        if (rst)
218
                q <= reset_value;
219
        else
220
                q <= d;
221
endmodule
222 18 unneback
module vl_dff_array ( d, q, clk, rst);
223 6 unneback
        parameter width = 1;
224
        parameter depth = 2;
225
        parameter reset_value = 1'b0;
226
        input [width-1:0] d;
227
        input clk, rst;
228
        output [width-1:0] q;
229
        reg  [0:depth-1] q_tmp [width-1:0];
230
        integer i;
231
        always @ (posedge clk or posedge rst)
232
        if (rst) begin
233
            for (i=0;i<depth;i=i+1)
234
                q_tmp[i] <= {width{reset_value}};
235
        end else begin
236
            q_tmp[0] <= d;
237
            for (i=1;i<depth;i=i+1)
238
                q_tmp[i] <= q_tmp[i-1];
239
        end
240
    assign q = q_tmp[depth-1];
241
endmodule
242 18 unneback
module vl_dff_ce ( d, ce, q, clk, rst);
243 6 unneback
        parameter width = 1;
244
        parameter reset_value = 0;
245
        input [width-1:0] d;
246
        input ce, clk, rst;
247
        output reg [width-1:0] q;
248
        always @ (posedge clk or posedge rst)
249
        if (rst)
250
                q <= reset_value;
251
        else
252
                if (ce)
253
                        q <= d;
254
endmodule
255 18 unneback
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
256 8 unneback
        parameter width = 1;
257
        parameter reset_value = 0;
258
        input [width-1:0] d;
259 10 unneback
        input ce, clear, clk, rst;
260 8 unneback
        output reg [width-1:0] q;
261
        always @ (posedge clk or posedge rst)
262
        if (rst)
263
            q <= reset_value;
264
        else
265
            if (ce)
266
                if (clear)
267
                    q <= {width{1'b0}};
268
                else
269
                    q <= d;
270
endmodule
271 24 unneback
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
272
        parameter width = 1;
273
        parameter reset_value = 0;
274
        input [width-1:0] d;
275
        input ce, set, clk, rst;
276
        output reg [width-1:0] q;
277
        always @ (posedge clk or posedge rst)
278
        if (rst)
279
            q <= reset_value;
280
        else
281
            if (ce)
282
                if (set)
283
                    q <= {width{1'b1}};
284
                else
285
                    q <= d;
286
endmodule
287 18 unneback
module vl_dff_sr ( aclr, aset, clock, data, q);
288 6 unneback
    input         aclr;
289
    input         aset;
290
    input         clock;
291
    input         data;
292
    output reg    q;
293
   always @ (posedge clock or posedge aclr or posedge aset)
294
     if (aclr)
295
       q <= 1'b0;
296
     else if (aset)
297
       q <= 1'b1;
298
     else
299
       q <= data;
300
endmodule
301
// LATCH
302
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
303
module latch ( d, le, q, clk);
304
input d, le;
305
output q;
306
input clk;/*
307
   always @ (posedge direction_set or posedge direction_clr)
308
     if (direction_clr)
309
       direction <= going_empty;
310
     else
311
       direction <= going_full;*/
312
endmodule
313 18 unneback
module vl_shreg ( d, q, clk, rst);
314 17 unneback
parameter depth = 10;
315
input d;
316
output q;
317
input clk, rst;
318
reg [1:depth] dffs;
319
always @ (posedge clk or posedge rst)
320
if (rst)
321
    dffs <= {depth{1'b0}};
322
else
323
    dffs <= {d,dffs[1:depth-1]};
324
assign q = dffs[depth];
325
endmodule
326 18 unneback
module vl_shreg_ce ( d, ce, q, clk, rst);
327 17 unneback
parameter depth = 10;
328
input d, ce;
329
output q;
330
input clk, rst;
331
reg [1:depth] dffs;
332
always @ (posedge clk or posedge rst)
333
if (rst)
334
    dffs <= {depth{1'b0}};
335
else
336
    if (ce)
337
        dffs <= {d,dffs[1:depth-1]};
338
assign q = dffs[depth];
339
endmodule
340 18 unneback
module vl_delay ( d, q, clk, rst);
341 15 unneback
parameter depth = 10;
342
input d;
343
output q;
344
input clk, rst;
345
reg [1:depth] dffs;
346
always @ (posedge clk or posedge rst)
347
if (rst)
348
    dffs <= {depth{1'b0}};
349
else
350
    dffs <= {d,dffs[1:depth-1]};
351
assign q = dffs[depth];
352
endmodule
353 18 unneback
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
354 17 unneback
parameter depth = 10;
355
input d;
356
output q, emptyflag;
357
input clk, rst;
358
reg [1:depth] dffs;
359
always @ (posedge clk or posedge rst)
360
if (rst)
361
    dffs <= {depth{1'b0}};
362
else
363
    dffs <= {d,dffs[1:depth-1]};
364
assign q = dffs[depth];
365
assign emptyflag = !(|dffs);
366
endmodule
367 6 unneback
//////////////////////////////////////////////////////////////////////
368
////                                                              ////
369 18 unneback
////  Logic functions                                             ////
370
////                                                              ////
371
////  Description                                                 ////
372
////  Logic functions such as multiplexers                        ////
373
////                                                              ////
374
////                                                              ////
375
////  To Do:                                                      ////
376
////   -                                                          ////
377
////                                                              ////
378
////  Author(s):                                                  ////
379
////      - Michael Unneback, unneback@opencores.org              ////
380
////        ORSoC AB                                              ////
381
////                                                              ////
382
//////////////////////////////////////////////////////////////////////
383
////                                                              ////
384
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
385
////                                                              ////
386
//// This source file may be used and distributed without         ////
387
//// restriction provided that this copyright statement is not    ////
388
//// removed from the file and that any derivative work contains  ////
389
//// the original copyright notice and the associated disclaimer. ////
390
////                                                              ////
391
//// This source file is free software; you can redistribute it   ////
392
//// and/or modify it under the terms of the GNU Lesser General   ////
393
//// Public License as published by the Free Software Foundation; ////
394
//// either version 2.1 of the License, or (at your option) any   ////
395
//// later version.                                               ////
396
////                                                              ////
397
//// This source is distributed in the hope that it will be       ////
398
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
399
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
400
//// PURPOSE.  See the GNU Lesser General Public License for more ////
401
//// details.                                                     ////
402
////                                                              ////
403
//// You should have received a copy of the GNU Lesser General    ////
404
//// Public License along with this source; if not, download it   ////
405
//// from http://www.opencores.org/lgpl.shtml                     ////
406
////                                                              ////
407
//////////////////////////////////////////////////////////////////////
408
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
409
parameter width = 32;
410
parameter nr_of_ports = 4;
411
input [width-1:0] a3, a2, a1, a0;
412
input [nr_of_ports-1:0] sel;
413 22 unneback
output [width-1:0] dout;
414 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
415 18 unneback
integer i;
416
// and
417
assign tmp[0] = {width{sel[0]}} & a0;
418
assign tmp[1] = {width{sel[1]}} & a1;
419
assign tmp[2] = {width{sel[2]}} & a2;
420
assign tmp[3] = {width{sel[3]}} & a3;
421
// or
422
assign dout = tmp[3] | tmp[2] | tmp[1] | tmp[0];
423
endmodule
424
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
425
parameter width = 32;
426
parameter nr_of_ports = 5;
427
input [width-1:0] a4, a3, a2, a1, a0;
428
input [nr_of_ports-1:0] sel;
429 22 unneback
output [width-1:0] dout;
430 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
431 18 unneback
integer i;
432
// and
433
assign tmp[0] = {width{sel[0]}} & a0;
434
assign tmp[1] = {width{sel[1]}} & a1;
435
assign tmp[2] = {width{sel[2]}} & a2;
436
assign tmp[3] = {width{sel[3]}} & a3;
437
assign tmp[4] = {width{sel[4]}} & a4;
438
// or
439
assign dout = tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
440
endmodule
441
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
442
parameter width = 32;
443
parameter nr_of_ports = 6;
444
input [width-1:0] a5, a4, a3, a2, a1, a0;
445
input [nr_of_ports-1:0] sel;
446 22 unneback
output [width-1:0] dout;
447 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
448 18 unneback
integer i;
449
// and
450
assign tmp[0] = {width{sel[0]}} & a0;
451
assign tmp[1] = {width{sel[1]}} & a1;
452
assign tmp[2] = {width{sel[2]}} & a2;
453
assign tmp[3] = {width{sel[3]}} & a3;
454
assign tmp[4] = {width{sel[4]}} & a4;
455
assign tmp[5] = {width{sel[5]}} & a5;
456
// or
457
assign dout = tmp[5] | tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
458
endmodule
459
//////////////////////////////////////////////////////////////////////
460
////                                                              ////
461 6 unneback
////  Versatile counter                                           ////
462
////                                                              ////
463
////  Description                                                 ////
464
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
465
////  counter                                                     ////
466
////                                                              ////
467
////  To Do:                                                      ////
468
////   - add LFSR with more taps                                  ////
469
////                                                              ////
470
////  Author(s):                                                  ////
471
////      - Michael Unneback, unneback@opencores.org              ////
472
////        ORSoC AB                                              ////
473
////                                                              ////
474
//////////////////////////////////////////////////////////////////////
475
////                                                              ////
476
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
477
////                                                              ////
478
//// This source file may be used and distributed without         ////
479
//// restriction provided that this copyright statement is not    ////
480
//// removed from the file and that any derivative work contains  ////
481
//// the original copyright notice and the associated disclaimer. ////
482
////                                                              ////
483
//// This source file is free software; you can redistribute it   ////
484
//// and/or modify it under the terms of the GNU Lesser General   ////
485
//// Public License as published by the Free Software Foundation; ////
486
//// either version 2.1 of the License, or (at your option) any   ////
487
//// later version.                                               ////
488
////                                                              ////
489
//// This source is distributed in the hope that it will be       ////
490
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
491
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
492
//// PURPOSE.  See the GNU Lesser General Public License for more ////
493
//// details.                                                     ////
494
////                                                              ////
495
//// You should have received a copy of the GNU Lesser General    ////
496
//// Public License along with this source; if not, download it   ////
497
//// from http://www.opencores.org/lgpl.shtml                     ////
498
////                                                              ////
499
//////////////////////////////////////////////////////////////////////
500
// binary counter
501 22 unneback
module vl_cnt_bin ( q, rst, clk);
502
   parameter length = 4;
503
   output [length:1] q;
504
   input rst;
505
   input clk;
506
   parameter clear_value = 0;
507
   parameter set_value = 1;
508
   parameter wrap_value = 0;
509
   parameter level1_value = 15;
510
   reg  [length:1] qi;
511
   wire [length:1] q_next;
512
   assign q_next = qi + {{length-1{1'b0}},1'b1};
513
   always @ (posedge clk or posedge rst)
514
     if (rst)
515
       qi <= {length{1'b0}};
516
     else
517
       qi <= q_next;
518
   assign q = qi;
519
endmodule
520
//////////////////////////////////////////////////////////////////////
521
////                                                              ////
522
////  Versatile counter                                           ////
523
////                                                              ////
524
////  Description                                                 ////
525
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
526
////  counter                                                     ////
527
////                                                              ////
528
////  To Do:                                                      ////
529
////   - add LFSR with more taps                                  ////
530
////                                                              ////
531
////  Author(s):                                                  ////
532
////      - Michael Unneback, unneback@opencores.org              ////
533
////        ORSoC AB                                              ////
534
////                                                              ////
535
//////////////////////////////////////////////////////////////////////
536
////                                                              ////
537
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
538
////                                                              ////
539
//// This source file may be used and distributed without         ////
540
//// restriction provided that this copyright statement is not    ////
541
//// removed from the file and that any derivative work contains  ////
542
//// the original copyright notice and the associated disclaimer. ////
543
////                                                              ////
544
//// This source file is free software; you can redistribute it   ////
545
//// and/or modify it under the terms of the GNU Lesser General   ////
546
//// Public License as published by the Free Software Foundation; ////
547
//// either version 2.1 of the License, or (at your option) any   ////
548
//// later version.                                               ////
549
////                                                              ////
550
//// This source is distributed in the hope that it will be       ////
551
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
552
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
553
//// PURPOSE.  See the GNU Lesser General Public License for more ////
554
//// details.                                                     ////
555
////                                                              ////
556
//// You should have received a copy of the GNU Lesser General    ////
557
//// Public License along with this source; if not, download it   ////
558
//// from http://www.opencores.org/lgpl.shtml                     ////
559
////                                                              ////
560
//////////////////////////////////////////////////////////////////////
561
// binary counter
562
module vl_cnt_bin_clear ( clear, q, rst, clk);
563
   parameter length = 4;
564
   input clear;
565
   output [length:1] q;
566
   input rst;
567
   input clk;
568
   parameter clear_value = 0;
569
   parameter set_value = 1;
570
   parameter wrap_value = 0;
571
   parameter level1_value = 15;
572
   reg  [length:1] qi;
573
   wire [length:1] q_next;
574
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
575
   always @ (posedge clk or posedge rst)
576
     if (rst)
577
       qi <= {length{1'b0}};
578
     else
579
       qi <= q_next;
580
   assign q = qi;
581
endmodule
582
//////////////////////////////////////////////////////////////////////
583
////                                                              ////
584
////  Versatile counter                                           ////
585
////                                                              ////
586
////  Description                                                 ////
587
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
588
////  counter                                                     ////
589
////                                                              ////
590
////  To Do:                                                      ////
591
////   - add LFSR with more taps                                  ////
592
////                                                              ////
593
////  Author(s):                                                  ////
594
////      - Michael Unneback, unneback@opencores.org              ////
595
////        ORSoC AB                                              ////
596
////                                                              ////
597
//////////////////////////////////////////////////////////////////////
598
////                                                              ////
599
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
600
////                                                              ////
601
//// This source file may be used and distributed without         ////
602
//// restriction provided that this copyright statement is not    ////
603
//// removed from the file and that any derivative work contains  ////
604
//// the original copyright notice and the associated disclaimer. ////
605
////                                                              ////
606
//// This source file is free software; you can redistribute it   ////
607
//// and/or modify it under the terms of the GNU Lesser General   ////
608
//// Public License as published by the Free Software Foundation; ////
609
//// either version 2.1 of the License, or (at your option) any   ////
610
//// later version.                                               ////
611
////                                                              ////
612
//// This source is distributed in the hope that it will be       ////
613
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
614
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
615
//// PURPOSE.  See the GNU Lesser General Public License for more ////
616
//// details.                                                     ////
617
////                                                              ////
618
//// You should have received a copy of the GNU Lesser General    ////
619
//// Public License along with this source; if not, download it   ////
620
//// from http://www.opencores.org/lgpl.shtml                     ////
621
////                                                              ////
622
//////////////////////////////////////////////////////////////////////
623
// binary counter
624 18 unneback
module vl_cnt_bin_ce ( cke, q, rst, clk);
625 6 unneback
   parameter length = 4;
626
   input cke;
627
   output [length:1] q;
628
   input rst;
629
   input clk;
630
   parameter clear_value = 0;
631
   parameter set_value = 1;
632
   parameter wrap_value = 0;
633
   parameter level1_value = 15;
634
   reg  [length:1] qi;
635
   wire [length:1] q_next;
636
   assign q_next = qi + {{length-1{1'b0}},1'b1};
637
   always @ (posedge clk or posedge rst)
638
     if (rst)
639
       qi <= {length{1'b0}};
640
     else
641
     if (cke)
642
       qi <= q_next;
643
   assign q = qi;
644
endmodule
645
//////////////////////////////////////////////////////////////////////
646
////                                                              ////
647
////  Versatile counter                                           ////
648
////                                                              ////
649
////  Description                                                 ////
650
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
651
////  counter                                                     ////
652
////                                                              ////
653
////  To Do:                                                      ////
654
////   - add LFSR with more taps                                  ////
655
////                                                              ////
656
////  Author(s):                                                  ////
657
////      - Michael Unneback, unneback@opencores.org              ////
658
////        ORSoC AB                                              ////
659
////                                                              ////
660
//////////////////////////////////////////////////////////////////////
661
////                                                              ////
662
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
663
////                                                              ////
664
//// This source file may be used and distributed without         ////
665
//// restriction provided that this copyright statement is not    ////
666
//// removed from the file and that any derivative work contains  ////
667
//// the original copyright notice and the associated disclaimer. ////
668
////                                                              ////
669
//// This source file is free software; you can redistribute it   ////
670
//// and/or modify it under the terms of the GNU Lesser General   ////
671
//// Public License as published by the Free Software Foundation; ////
672
//// either version 2.1 of the License, or (at your option) any   ////
673
//// later version.                                               ////
674
////                                                              ////
675
//// This source is distributed in the hope that it will be       ////
676
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
677
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
678
//// PURPOSE.  See the GNU Lesser General Public License for more ////
679
//// details.                                                     ////
680
////                                                              ////
681
//// You should have received a copy of the GNU Lesser General    ////
682
//// Public License along with this source; if not, download it   ////
683
//// from http://www.opencores.org/lgpl.shtml                     ////
684
////                                                              ////
685
//////////////////////////////////////////////////////////////////////
686
// binary counter
687 18 unneback
module vl_cnt_bin_ce_clear ( clear, cke, q, rst, clk);
688 6 unneback
   parameter length = 4;
689
   input clear;
690
   input cke;
691
   output [length:1] q;
692
   input rst;
693
   input clk;
694
   parameter clear_value = 0;
695
   parameter set_value = 1;
696
   parameter wrap_value = 0;
697
   parameter level1_value = 15;
698
   reg  [length:1] qi;
699
   wire [length:1] q_next;
700
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
701
   always @ (posedge clk or posedge rst)
702
     if (rst)
703
       qi <= {length{1'b0}};
704
     else
705
     if (cke)
706
       qi <= q_next;
707
   assign q = qi;
708
endmodule
709
//////////////////////////////////////////////////////////////////////
710
////                                                              ////
711
////  Versatile counter                                           ////
712
////                                                              ////
713
////  Description                                                 ////
714
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
715
////  counter                                                     ////
716
////                                                              ////
717
////  To Do:                                                      ////
718
////   - add LFSR with more taps                                  ////
719
////                                                              ////
720
////  Author(s):                                                  ////
721
////      - Michael Unneback, unneback@opencores.org              ////
722
////        ORSoC AB                                              ////
723
////                                                              ////
724
//////////////////////////////////////////////////////////////////////
725
////                                                              ////
726
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
727
////                                                              ////
728
//// This source file may be used and distributed without         ////
729
//// restriction provided that this copyright statement is not    ////
730
//// removed from the file and that any derivative work contains  ////
731
//// the original copyright notice and the associated disclaimer. ////
732
////                                                              ////
733
//// This source file is free software; you can redistribute it   ////
734
//// and/or modify it under the terms of the GNU Lesser General   ////
735
//// Public License as published by the Free Software Foundation; ////
736
//// either version 2.1 of the License, or (at your option) any   ////
737
//// later version.                                               ////
738
////                                                              ////
739
//// This source is distributed in the hope that it will be       ////
740
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
741
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
742
//// PURPOSE.  See the GNU Lesser General Public License for more ////
743
//// details.                                                     ////
744
////                                                              ////
745
//// You should have received a copy of the GNU Lesser General    ////
746
//// Public License along with this source; if not, download it   ////
747
//// from http://www.opencores.org/lgpl.shtml                     ////
748
////                                                              ////
749
//////////////////////////////////////////////////////////////////////
750
// binary counter
751 18 unneback
module vl_cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk);
752 6 unneback
   parameter length = 4;
753
   input clear;
754
   input set;
755
   input cke;
756
   input rew;
757
   output [length:1] q;
758
   input rst;
759
   input clk;
760
   parameter clear_value = 0;
761
   parameter set_value = 1;
762
   parameter wrap_value = 0;
763
   parameter level1_value = 15;
764
   reg  [length:1] qi;
765
   wire  [length:1] q_next, q_next_fw, q_next_rew;
766
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
767
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
768
   assign q_next = rew ? q_next_rew : q_next_fw;
769
   always @ (posedge clk or posedge rst)
770
     if (rst)
771
       qi <= {length{1'b0}};
772
     else
773
     if (cke)
774
       qi <= q_next;
775
   assign q = qi;
776
endmodule
777
//////////////////////////////////////////////////////////////////////
778
////                                                              ////
779
////  Versatile counter                                           ////
780
////                                                              ////
781
////  Description                                                 ////
782
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
783
////  counter                                                     ////
784
////                                                              ////
785
////  To Do:                                                      ////
786
////   - add LFSR with more taps                                  ////
787
////                                                              ////
788
////  Author(s):                                                  ////
789
////      - Michael Unneback, unneback@opencores.org              ////
790
////        ORSoC AB                                              ////
791
////                                                              ////
792
//////////////////////////////////////////////////////////////////////
793
////                                                              ////
794
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
795
////                                                              ////
796
//// This source file may be used and distributed without         ////
797
//// restriction provided that this copyright statement is not    ////
798
//// removed from the file and that any derivative work contains  ////
799
//// the original copyright notice and the associated disclaimer. ////
800
////                                                              ////
801
//// This source file is free software; you can redistribute it   ////
802
//// and/or modify it under the terms of the GNU Lesser General   ////
803
//// Public License as published by the Free Software Foundation; ////
804
//// either version 2.1 of the License, or (at your option) any   ////
805
//// later version.                                               ////
806
////                                                              ////
807
//// This source is distributed in the hope that it will be       ////
808
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
809
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
810
//// PURPOSE.  See the GNU Lesser General Public License for more ////
811
//// details.                                                     ////
812
////                                                              ////
813
//// You should have received a copy of the GNU Lesser General    ////
814
//// Public License along with this source; if not, download it   ////
815
//// from http://www.opencores.org/lgpl.shtml                     ////
816
////                                                              ////
817
//////////////////////////////////////////////////////////////////////
818
// binary counter
819 18 unneback
module vl_cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk);
820 6 unneback
   parameter length = 4;
821
   input cke;
822
   input rew;
823
   output reg level1;
824
   input rst;
825
   input clk;
826
   parameter clear_value = 0;
827
   parameter set_value = 1;
828
   parameter wrap_value = 1;
829
   parameter level1_value = 15;
830
   reg  [length:1] qi;
831
   wire  [length:1] q_next, q_next_fw, q_next_rew;
832
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
833
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
834
   assign q_next = rew ? q_next_rew : q_next_fw;
835
   always @ (posedge clk or posedge rst)
836
     if (rst)
837
       qi <= {length{1'b0}};
838
     else
839
     if (cke)
840
       qi <= q_next;
841
    always @ (posedge clk or posedge rst)
842
    if (rst)
843
        level1 <= 1'b0;
844
    else
845
    if (cke)
846
    if (q_next == level1_value)
847
        level1 <= 1'b1;
848
    else if (qi == level1_value & rew)
849
        level1 <= 1'b0;
850
endmodule
851
//////////////////////////////////////////////////////////////////////
852
////                                                              ////
853
////  Versatile counter                                           ////
854
////                                                              ////
855
////  Description                                                 ////
856
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
857
////  counter                                                     ////
858
////                                                              ////
859
////  To Do:                                                      ////
860
////   - add LFSR with more taps                                  ////
861
////                                                              ////
862
////  Author(s):                                                  ////
863
////      - Michael Unneback, unneback@opencores.org              ////
864
////        ORSoC AB                                              ////
865
////                                                              ////
866
//////////////////////////////////////////////////////////////////////
867
////                                                              ////
868
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
869
////                                                              ////
870
//// This source file may be used and distributed without         ////
871
//// restriction provided that this copyright statement is not    ////
872
//// removed from the file and that any derivative work contains  ////
873
//// the original copyright notice and the associated disclaimer. ////
874
////                                                              ////
875
//// This source file is free software; you can redistribute it   ////
876
//// and/or modify it under the terms of the GNU Lesser General   ////
877
//// Public License as published by the Free Software Foundation; ////
878
//// either version 2.1 of the License, or (at your option) any   ////
879
//// later version.                                               ////
880
////                                                              ////
881
//// This source is distributed in the hope that it will be       ////
882
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
883
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
884
//// PURPOSE.  See the GNU Lesser General Public License for more ////
885
//// details.                                                     ////
886
////                                                              ////
887
//// You should have received a copy of the GNU Lesser General    ////
888
//// Public License along with this source; if not, download it   ////
889
//// from http://www.opencores.org/lgpl.shtml                     ////
890
////                                                              ////
891
//////////////////////////////////////////////////////////////////////
892 25 unneback
// binary counter
893
module vl_cnt_bin_ce_rew_zq_l1 ( cke, rew, zq, level1, rst, clk);
894
   parameter length = 4;
895
   input cke;
896
   input rew;
897
   output reg zq;
898
   output reg level1;
899
   input rst;
900
   input clk;
901
   parameter clear_value = 0;
902
   parameter set_value = 1;
903
   parameter wrap_value = 1;
904
   parameter level1_value = 15;
905
   reg  [length:1] qi;
906
   wire  [length:1] q_next, q_next_fw, q_next_rew;
907
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
908
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
909
   assign q_next = rew ? q_next_rew : q_next_fw;
910
   always @ (posedge clk or posedge rst)
911
     if (rst)
912
       qi <= {length{1'b0}};
913
     else
914
     if (cke)
915
       qi <= q_next;
916
   always @ (posedge clk or posedge rst)
917
     if (rst)
918
       zq <= 1'b1;
919
     else
920
     if (cke)
921
       zq <= q_next == {length{1'b0}};
922
    always @ (posedge clk or posedge rst)
923
    if (rst)
924
        level1 <= 1'b0;
925
    else
926
    if (cke)
927
    if (q_next == level1_value)
928
        level1 <= 1'b1;
929
    else if (qi == level1_value & rew)
930
        level1 <= 1'b0;
931
endmodule
932
//////////////////////////////////////////////////////////////////////
933
////                                                              ////
934
////  Versatile counter                                           ////
935
////                                                              ////
936
////  Description                                                 ////
937
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
938
////  counter                                                     ////
939
////                                                              ////
940
////  To Do:                                                      ////
941
////   - add LFSR with more taps                                  ////
942
////                                                              ////
943
////  Author(s):                                                  ////
944
////      - Michael Unneback, unneback@opencores.org              ////
945
////        ORSoC AB                                              ////
946
////                                                              ////
947
//////////////////////////////////////////////////////////////////////
948
////                                                              ////
949
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
950
////                                                              ////
951
//// This source file may be used and distributed without         ////
952
//// restriction provided that this copyright statement is not    ////
953
//// removed from the file and that any derivative work contains  ////
954
//// the original copyright notice and the associated disclaimer. ////
955
////                                                              ////
956
//// This source file is free software; you can redistribute it   ////
957
//// and/or modify it under the terms of the GNU Lesser General   ////
958
//// Public License as published by the Free Software Foundation; ////
959
//// either version 2.1 of the License, or (at your option) any   ////
960
//// later version.                                               ////
961
////                                                              ////
962
//// This source is distributed in the hope that it will be       ////
963
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
964
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
965
//// PURPOSE.  See the GNU Lesser General Public License for more ////
966
//// details.                                                     ////
967
////                                                              ////
968
//// You should have received a copy of the GNU Lesser General    ////
969
//// Public License along with this source; if not, download it   ////
970
//// from http://www.opencores.org/lgpl.shtml                     ////
971
////                                                              ////
972
//////////////////////////////////////////////////////////////////////
973
// binary counter
974
module vl_cnt_bin_ce_rew_q_zq_l1 ( cke, rew, q, zq, level1, rst, clk);
975
   parameter length = 4;
976
   input cke;
977
   input rew;
978
   output [length:1] q;
979
   output reg zq;
980
   output reg level1;
981
   input rst;
982
   input clk;
983
   parameter clear_value = 0;
984
   parameter set_value = 1;
985
   parameter wrap_value = 1;
986
   parameter level1_value = 15;
987
   reg  [length:1] qi;
988
   wire  [length:1] q_next, q_next_fw, q_next_rew;
989
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
990
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
991
   assign q_next = rew ? q_next_rew : q_next_fw;
992
   always @ (posedge clk or posedge rst)
993
     if (rst)
994
       qi <= {length{1'b0}};
995
     else
996
     if (cke)
997
       qi <= q_next;
998
   assign q = qi;
999
   always @ (posedge clk or posedge rst)
1000
     if (rst)
1001
       zq <= 1'b1;
1002
     else
1003
     if (cke)
1004
       zq <= q_next == {length{1'b0}};
1005
    always @ (posedge clk or posedge rst)
1006
    if (rst)
1007
        level1 <= 1'b0;
1008
    else
1009
    if (cke)
1010
    if (q_next == level1_value)
1011
        level1 <= 1'b1;
1012
    else if (qi == level1_value & rew)
1013
        level1 <= 1'b0;
1014
endmodule
1015
//////////////////////////////////////////////////////////////////////
1016
////                                                              ////
1017
////  Versatile counter                                           ////
1018
////                                                              ////
1019
////  Description                                                 ////
1020
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1021
////  counter                                                     ////
1022
////                                                              ////
1023
////  To Do:                                                      ////
1024
////   - add LFSR with more taps                                  ////
1025
////                                                              ////
1026
////  Author(s):                                                  ////
1027
////      - Michael Unneback, unneback@opencores.org              ////
1028
////        ORSoC AB                                              ////
1029
////                                                              ////
1030
//////////////////////////////////////////////////////////////////////
1031
////                                                              ////
1032
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1033
////                                                              ////
1034
//// This source file may be used and distributed without         ////
1035
//// restriction provided that this copyright statement is not    ////
1036
//// removed from the file and that any derivative work contains  ////
1037
//// the original copyright notice and the associated disclaimer. ////
1038
////                                                              ////
1039
//// This source file is free software; you can redistribute it   ////
1040
//// and/or modify it under the terms of the GNU Lesser General   ////
1041
//// Public License as published by the Free Software Foundation; ////
1042
//// either version 2.1 of the License, or (at your option) any   ////
1043
//// later version.                                               ////
1044
////                                                              ////
1045
//// This source is distributed in the hope that it will be       ////
1046
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1047
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1048
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1049
//// details.                                                     ////
1050
////                                                              ////
1051
//// You should have received a copy of the GNU Lesser General    ////
1052
//// Public License along with this source; if not, download it   ////
1053
//// from http://www.opencores.org/lgpl.shtml                     ////
1054
////                                                              ////
1055
//////////////////////////////////////////////////////////////////////
1056 6 unneback
// LFSR counter
1057 18 unneback
module vl_cnt_lfsr_zq ( zq, rst, clk);
1058 6 unneback
   parameter length = 4;
1059
   output reg zq;
1060
   input rst;
1061
   input clk;
1062
   parameter clear_value = 0;
1063
   parameter set_value = 1;
1064
   parameter wrap_value = 8;
1065
   parameter level1_value = 15;
1066
   reg  [length:1] qi;
1067
   reg lfsr_fb;
1068
   wire [length:1] q_next;
1069
   reg [32:1] polynom;
1070
   integer i;
1071
   always @ (qi)
1072
   begin
1073
        case (length)
1074
         2: polynom = 32'b11;                               // 0x3
1075
         3: polynom = 32'b110;                              // 0x6
1076
         4: polynom = 32'b1100;                             // 0xC
1077
         5: polynom = 32'b10100;                            // 0x14
1078
         6: polynom = 32'b110000;                           // 0x30
1079
         7: polynom = 32'b1100000;                          // 0x60
1080
         8: polynom = 32'b10111000;                         // 0xb8
1081
         9: polynom = 32'b100010000;                        // 0x110
1082
        10: polynom = 32'b1001000000;                       // 0x240
1083
        11: polynom = 32'b10100000000;                      // 0x500
1084
        12: polynom = 32'b100000101001;                     // 0x829
1085
        13: polynom = 32'b1000000001100;                    // 0x100C
1086
        14: polynom = 32'b10000000010101;                   // 0x2015
1087
        15: polynom = 32'b110000000000000;                  // 0x6000
1088
        16: polynom = 32'b1101000000001000;                 // 0xD008
1089
        17: polynom = 32'b10010000000000000;                // 0x12000
1090
        18: polynom = 32'b100000010000000000;               // 0x20400
1091
        19: polynom = 32'b1000000000000100011;              // 0x40023
1092
        20: polynom = 32'b10000010000000000000;             // 0x82000
1093
        21: polynom = 32'b101000000000000000000;            // 0x140000
1094
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1095
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1096
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1097
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1098
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1099
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1100
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1101
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1102
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1103
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1104
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1105
        default: polynom = 32'b0;
1106
        endcase
1107
        lfsr_fb = qi[length];
1108
        for (i=length-1; i>=1; i=i-1) begin
1109
            if (polynom[i])
1110
                lfsr_fb = lfsr_fb  ~^ qi[i];
1111
        end
1112
    end
1113
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1114
   always @ (posedge clk or posedge rst)
1115
     if (rst)
1116
       qi <= {length{1'b0}};
1117
     else
1118
       qi <= q_next;
1119
   always @ (posedge clk or posedge rst)
1120
     if (rst)
1121
       zq <= 1'b1;
1122
     else
1123
       zq <= q_next == {length{1'b0}};
1124
endmodule
1125
//////////////////////////////////////////////////////////////////////
1126
////                                                              ////
1127
////  Versatile counter                                           ////
1128
////                                                              ////
1129
////  Description                                                 ////
1130
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1131
////  counter                                                     ////
1132
////                                                              ////
1133
////  To Do:                                                      ////
1134
////   - add LFSR with more taps                                  ////
1135
////                                                              ////
1136
////  Author(s):                                                  ////
1137
////      - Michael Unneback, unneback@opencores.org              ////
1138
////        ORSoC AB                                              ////
1139
////                                                              ////
1140
//////////////////////////////////////////////////////////////////////
1141
////                                                              ////
1142
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1143
////                                                              ////
1144
//// This source file may be used and distributed without         ////
1145
//// restriction provided that this copyright statement is not    ////
1146
//// removed from the file and that any derivative work contains  ////
1147
//// the original copyright notice and the associated disclaimer. ////
1148
////                                                              ////
1149
//// This source file is free software; you can redistribute it   ////
1150
//// and/or modify it under the terms of the GNU Lesser General   ////
1151
//// Public License as published by the Free Software Foundation; ////
1152
//// either version 2.1 of the License, or (at your option) any   ////
1153
//// later version.                                               ////
1154
////                                                              ////
1155
//// This source is distributed in the hope that it will be       ////
1156
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1157
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1158
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1159
//// details.                                                     ////
1160
////                                                              ////
1161
//// You should have received a copy of the GNU Lesser General    ////
1162
//// Public License along with this source; if not, download it   ////
1163
//// from http://www.opencores.org/lgpl.shtml                     ////
1164
////                                                              ////
1165
//////////////////////////////////////////////////////////////////////
1166
// LFSR counter
1167 18 unneback
module vl_cnt_lfsr_ce_zq ( cke, zq, rst, clk);
1168 6 unneback
   parameter length = 4;
1169
   input cke;
1170
   output reg zq;
1171
   input rst;
1172
   input clk;
1173
   parameter clear_value = 0;
1174
   parameter set_value = 1;
1175
   parameter wrap_value = 8;
1176
   parameter level1_value = 15;
1177
   reg  [length:1] qi;
1178
   reg lfsr_fb;
1179
   wire [length:1] q_next;
1180
   reg [32:1] polynom;
1181
   integer i;
1182
   always @ (qi)
1183
   begin
1184
        case (length)
1185
         2: polynom = 32'b11;                               // 0x3
1186
         3: polynom = 32'b110;                              // 0x6
1187
         4: polynom = 32'b1100;                             // 0xC
1188
         5: polynom = 32'b10100;                            // 0x14
1189
         6: polynom = 32'b110000;                           // 0x30
1190
         7: polynom = 32'b1100000;                          // 0x60
1191
         8: polynom = 32'b10111000;                         // 0xb8
1192
         9: polynom = 32'b100010000;                        // 0x110
1193
        10: polynom = 32'b1001000000;                       // 0x240
1194
        11: polynom = 32'b10100000000;                      // 0x500
1195
        12: polynom = 32'b100000101001;                     // 0x829
1196
        13: polynom = 32'b1000000001100;                    // 0x100C
1197
        14: polynom = 32'b10000000010101;                   // 0x2015
1198
        15: polynom = 32'b110000000000000;                  // 0x6000
1199
        16: polynom = 32'b1101000000001000;                 // 0xD008
1200
        17: polynom = 32'b10010000000000000;                // 0x12000
1201
        18: polynom = 32'b100000010000000000;               // 0x20400
1202
        19: polynom = 32'b1000000000000100011;              // 0x40023
1203
        20: polynom = 32'b10000010000000000000;             // 0x82000
1204
        21: polynom = 32'b101000000000000000000;            // 0x140000
1205
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1206
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1207
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1208
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1209
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1210
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1211
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1212
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1213
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1214
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1215
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1216
        default: polynom = 32'b0;
1217
        endcase
1218
        lfsr_fb = qi[length];
1219
        for (i=length-1; i>=1; i=i-1) begin
1220
            if (polynom[i])
1221
                lfsr_fb = lfsr_fb  ~^ qi[i];
1222
        end
1223
    end
1224
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1225
   always @ (posedge clk or posedge rst)
1226
     if (rst)
1227
       qi <= {length{1'b0}};
1228
     else
1229
     if (cke)
1230
       qi <= q_next;
1231
   always @ (posedge clk or posedge rst)
1232
     if (rst)
1233
       zq <= 1'b1;
1234
     else
1235
     if (cke)
1236
       zq <= q_next == {length{1'b0}};
1237
endmodule
1238
//////////////////////////////////////////////////////////////////////
1239
////                                                              ////
1240
////  Versatile counter                                           ////
1241
////                                                              ////
1242
////  Description                                                 ////
1243
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1244
////  counter                                                     ////
1245
////                                                              ////
1246
////  To Do:                                                      ////
1247
////   - add LFSR with more taps                                  ////
1248
////                                                              ////
1249
////  Author(s):                                                  ////
1250
////      - Michael Unneback, unneback@opencores.org              ////
1251
////        ORSoC AB                                              ////
1252
////                                                              ////
1253
//////////////////////////////////////////////////////////////////////
1254
////                                                              ////
1255
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1256
////                                                              ////
1257
//// This source file may be used and distributed without         ////
1258
//// restriction provided that this copyright statement is not    ////
1259
//// removed from the file and that any derivative work contains  ////
1260
//// the original copyright notice and the associated disclaimer. ////
1261
////                                                              ////
1262
//// This source file is free software; you can redistribute it   ////
1263
//// and/or modify it under the terms of the GNU Lesser General   ////
1264
//// Public License as published by the Free Software Foundation; ////
1265
//// either version 2.1 of the License, or (at your option) any   ////
1266
//// later version.                                               ////
1267
////                                                              ////
1268
//// This source is distributed in the hope that it will be       ////
1269
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1270
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1271
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1272
//// details.                                                     ////
1273
////                                                              ////
1274
//// You should have received a copy of the GNU Lesser General    ////
1275
//// Public License along with this source; if not, download it   ////
1276
//// from http://www.opencores.org/lgpl.shtml                     ////
1277
////                                                              ////
1278
//////////////////////////////////////////////////////////////////////
1279
// LFSR counter
1280 22 unneback
module vl_cnt_lfsr_ce_q_zq ( cke, q, zq, rst, clk);
1281
   parameter length = 4;
1282
   input cke;
1283
   output [length:1] q;
1284
   output reg zq;
1285
   input rst;
1286
   input clk;
1287
   parameter clear_value = 0;
1288
   parameter set_value = 1;
1289
   parameter wrap_value = 8;
1290
   parameter level1_value = 15;
1291
   reg  [length:1] qi;
1292
   reg lfsr_fb;
1293
   wire [length:1] q_next;
1294
   reg [32:1] polynom;
1295
   integer i;
1296
   always @ (qi)
1297
   begin
1298
        case (length)
1299
         2: polynom = 32'b11;                               // 0x3
1300
         3: polynom = 32'b110;                              // 0x6
1301
         4: polynom = 32'b1100;                             // 0xC
1302
         5: polynom = 32'b10100;                            // 0x14
1303
         6: polynom = 32'b110000;                           // 0x30
1304
         7: polynom = 32'b1100000;                          // 0x60
1305
         8: polynom = 32'b10111000;                         // 0xb8
1306
         9: polynom = 32'b100010000;                        // 0x110
1307
        10: polynom = 32'b1001000000;                       // 0x240
1308
        11: polynom = 32'b10100000000;                      // 0x500
1309
        12: polynom = 32'b100000101001;                     // 0x829
1310
        13: polynom = 32'b1000000001100;                    // 0x100C
1311
        14: polynom = 32'b10000000010101;                   // 0x2015
1312
        15: polynom = 32'b110000000000000;                  // 0x6000
1313
        16: polynom = 32'b1101000000001000;                 // 0xD008
1314
        17: polynom = 32'b10010000000000000;                // 0x12000
1315
        18: polynom = 32'b100000010000000000;               // 0x20400
1316
        19: polynom = 32'b1000000000000100011;              // 0x40023
1317
        20: polynom = 32'b10000010000000000000;             // 0x82000
1318
        21: polynom = 32'b101000000000000000000;            // 0x140000
1319
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1320
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1321
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1322
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1323
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1324
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1325
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1326
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1327
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1328
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1329
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1330
        default: polynom = 32'b0;
1331
        endcase
1332
        lfsr_fb = qi[length];
1333
        for (i=length-1; i>=1; i=i-1) begin
1334
            if (polynom[i])
1335
                lfsr_fb = lfsr_fb  ~^ qi[i];
1336
        end
1337
    end
1338
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1339
   always @ (posedge clk or posedge rst)
1340
     if (rst)
1341
       qi <= {length{1'b0}};
1342
     else
1343
     if (cke)
1344
       qi <= q_next;
1345
   assign q = qi;
1346
   always @ (posedge clk or posedge rst)
1347
     if (rst)
1348
       zq <= 1'b1;
1349
     else
1350
     if (cke)
1351
       zq <= q_next == {length{1'b0}};
1352
endmodule
1353
//////////////////////////////////////////////////////////////////////
1354
////                                                              ////
1355
////  Versatile counter                                           ////
1356
////                                                              ////
1357
////  Description                                                 ////
1358
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1359
////  counter                                                     ////
1360
////                                                              ////
1361
////  To Do:                                                      ////
1362
////   - add LFSR with more taps                                  ////
1363
////                                                              ////
1364
////  Author(s):                                                  ////
1365
////      - Michael Unneback, unneback@opencores.org              ////
1366
////        ORSoC AB                                              ////
1367
////                                                              ////
1368
//////////////////////////////////////////////////////////////////////
1369
////                                                              ////
1370
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1371
////                                                              ////
1372
//// This source file may be used and distributed without         ////
1373
//// restriction provided that this copyright statement is not    ////
1374
//// removed from the file and that any derivative work contains  ////
1375
//// the original copyright notice and the associated disclaimer. ////
1376
////                                                              ////
1377
//// This source file is free software; you can redistribute it   ////
1378
//// and/or modify it under the terms of the GNU Lesser General   ////
1379
//// Public License as published by the Free Software Foundation; ////
1380
//// either version 2.1 of the License, or (at your option) any   ////
1381
//// later version.                                               ////
1382
////                                                              ////
1383
//// This source is distributed in the hope that it will be       ////
1384
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1385
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1386
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1387
//// details.                                                     ////
1388
////                                                              ////
1389
//// You should have received a copy of the GNU Lesser General    ////
1390
//// Public License along with this source; if not, download it   ////
1391
//// from http://www.opencores.org/lgpl.shtml                     ////
1392
////                                                              ////
1393
//////////////////////////////////////////////////////////////////////
1394
// LFSR counter
1395 18 unneback
module vl_cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk);
1396 6 unneback
   parameter length = 4;
1397
   input cke;
1398
   input rew;
1399
   output reg level1;
1400
   input rst;
1401
   input clk;
1402
   parameter clear_value = 0;
1403
   parameter set_value = 1;
1404
   parameter wrap_value = 8;
1405
   parameter level1_value = 15;
1406
   reg  [length:1] qi;
1407
   reg lfsr_fb, lfsr_fb_rew;
1408
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1409
   reg [32:1] polynom_rew;
1410
   integer j;
1411
   reg [32:1] polynom;
1412
   integer i;
1413
   always @ (qi)
1414
   begin
1415
        case (length)
1416
         2: polynom = 32'b11;                               // 0x3
1417
         3: polynom = 32'b110;                              // 0x6
1418
         4: polynom = 32'b1100;                             // 0xC
1419
         5: polynom = 32'b10100;                            // 0x14
1420
         6: polynom = 32'b110000;                           // 0x30
1421
         7: polynom = 32'b1100000;                          // 0x60
1422
         8: polynom = 32'b10111000;                         // 0xb8
1423
         9: polynom = 32'b100010000;                        // 0x110
1424
        10: polynom = 32'b1001000000;                       // 0x240
1425
        11: polynom = 32'b10100000000;                      // 0x500
1426
        12: polynom = 32'b100000101001;                     // 0x829
1427
        13: polynom = 32'b1000000001100;                    // 0x100C
1428
        14: polynom = 32'b10000000010101;                   // 0x2015
1429
        15: polynom = 32'b110000000000000;                  // 0x6000
1430
        16: polynom = 32'b1101000000001000;                 // 0xD008
1431
        17: polynom = 32'b10010000000000000;                // 0x12000
1432
        18: polynom = 32'b100000010000000000;               // 0x20400
1433
        19: polynom = 32'b1000000000000100011;              // 0x40023
1434
        20: polynom = 32'b10000010000000000000;             // 0x82000
1435
        21: polynom = 32'b101000000000000000000;            // 0x140000
1436
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1437
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1438
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1439
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1440
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1441
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1442
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1443
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1444
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1445
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1446
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1447
        default: polynom = 32'b0;
1448
        endcase
1449
        lfsr_fb = qi[length];
1450
        for (i=length-1; i>=1; i=i-1) begin
1451
            if (polynom[i])
1452
                lfsr_fb = lfsr_fb  ~^ qi[i];
1453
        end
1454
    end
1455
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1456
   always @ (qi)
1457
   begin
1458
        case (length)
1459
         2: polynom_rew = 32'b11;
1460
         3: polynom_rew = 32'b110;
1461
         4: polynom_rew = 32'b1100;
1462
         5: polynom_rew = 32'b10100;
1463
         6: polynom_rew = 32'b110000;
1464
         7: polynom_rew = 32'b1100000;
1465
         8: polynom_rew = 32'b10111000;
1466
         9: polynom_rew = 32'b100010000;
1467
        10: polynom_rew = 32'b1001000000;
1468
        11: polynom_rew = 32'b10100000000;
1469
        12: polynom_rew = 32'b100000101001;
1470
        13: polynom_rew = 32'b1000000001100;
1471
        14: polynom_rew = 32'b10000000010101;
1472
        15: polynom_rew = 32'b110000000000000;
1473
        16: polynom_rew = 32'b1101000000001000;
1474
        17: polynom_rew = 32'b10010000000000000;
1475
        18: polynom_rew = 32'b100000010000000000;
1476
        19: polynom_rew = 32'b1000000000000100011;
1477
        20: polynom_rew = 32'b10000010000000000000;
1478
        21: polynom_rew = 32'b101000000000000000000;
1479
        22: polynom_rew = 32'b1100000000000000000000;
1480
        23: polynom_rew = 32'b10000100000000000000000;
1481
        24: polynom_rew = 32'b111000010000000000000000;
1482
        25: polynom_rew = 32'b1001000000000000000000000;
1483
        26: polynom_rew = 32'b10000000000000000000100011;
1484
        27: polynom_rew = 32'b100000000000000000000010011;
1485
        28: polynom_rew = 32'b1100100000000000000000000000;
1486
        29: polynom_rew = 32'b10100000000000000000000000000;
1487
        30: polynom_rew = 32'b100000000000000000000000101001;
1488
        31: polynom_rew = 32'b1001000000000000000000000000000;
1489
        32: polynom_rew = 32'b10000000001000000000000000000011;
1490
        default: polynom_rew = 32'b0;
1491
        endcase
1492
        // rotate left
1493
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
1494
        lfsr_fb_rew = qi[length];
1495
        for (i=length-1; i>=1; i=i-1) begin
1496
            if (polynom_rew[i])
1497
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
1498
        end
1499
    end
1500
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
1501
   assign q_next = rew ? q_next_rew : q_next_fw;
1502
   always @ (posedge clk or posedge rst)
1503
     if (rst)
1504
       qi <= {length{1'b0}};
1505
     else
1506
     if (cke)
1507
       qi <= q_next;
1508
    always @ (posedge clk or posedge rst)
1509
    if (rst)
1510
        level1 <= 1'b0;
1511
    else
1512
    if (cke)
1513
    if (q_next == level1_value)
1514
        level1 <= 1'b1;
1515
    else if (qi == level1_value & rew)
1516
        level1 <= 1'b0;
1517
endmodule
1518
//////////////////////////////////////////////////////////////////////
1519
////                                                              ////
1520
////  Versatile counter                                           ////
1521
////                                                              ////
1522
////  Description                                                 ////
1523
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1524
////  counter                                                     ////
1525
////                                                              ////
1526
////  To Do:                                                      ////
1527
////   - add LFSR with more taps                                  ////
1528
////                                                              ////
1529
////  Author(s):                                                  ////
1530
////      - Michael Unneback, unneback@opencores.org              ////
1531
////        ORSoC AB                                              ////
1532
////                                                              ////
1533
//////////////////////////////////////////////////////////////////////
1534
////                                                              ////
1535
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1536
////                                                              ////
1537
//// This source file may be used and distributed without         ////
1538
//// restriction provided that this copyright statement is not    ////
1539
//// removed from the file and that any derivative work contains  ////
1540
//// the original copyright notice and the associated disclaimer. ////
1541
////                                                              ////
1542
//// This source file is free software; you can redistribute it   ////
1543
//// and/or modify it under the terms of the GNU Lesser General   ////
1544
//// Public License as published by the Free Software Foundation; ////
1545
//// either version 2.1 of the License, or (at your option) any   ////
1546
//// later version.                                               ////
1547
////                                                              ////
1548
//// This source is distributed in the hope that it will be       ////
1549
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1550
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1551
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1552
//// details.                                                     ////
1553
////                                                              ////
1554
//// You should have received a copy of the GNU Lesser General    ////
1555
//// Public License along with this source; if not, download it   ////
1556
//// from http://www.opencores.org/lgpl.shtml                     ////
1557
////                                                              ////
1558
//////////////////////////////////////////////////////////////////////
1559
// GRAY counter
1560 18 unneback
module vl_cnt_gray ( q, rst, clk);
1561 6 unneback
   parameter length = 4;
1562
   output reg [length:1] q;
1563
   input rst;
1564
   input clk;
1565
   parameter clear_value = 0;
1566
   parameter set_value = 1;
1567
   parameter wrap_value = 8;
1568
   parameter level1_value = 15;
1569
   reg  [length:1] qi;
1570
   wire [length:1] q_next;
1571
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1572
   always @ (posedge clk or posedge rst)
1573
     if (rst)
1574
       qi <= {length{1'b0}};
1575
     else
1576
       qi <= q_next;
1577
   always @ (posedge clk or posedge rst)
1578
     if (rst)
1579
       q <= {length{1'b0}};
1580
     else
1581
         q <= (q_next>>1) ^ q_next;
1582
endmodule
1583
//////////////////////////////////////////////////////////////////////
1584
////                                                              ////
1585
////  Versatile counter                                           ////
1586
////                                                              ////
1587
////  Description                                                 ////
1588
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1589
////  counter                                                     ////
1590
////                                                              ////
1591
////  To Do:                                                      ////
1592
////   - add LFSR with more taps                                  ////
1593
////                                                              ////
1594
////  Author(s):                                                  ////
1595
////      - Michael Unneback, unneback@opencores.org              ////
1596
////        ORSoC AB                                              ////
1597
////                                                              ////
1598
//////////////////////////////////////////////////////////////////////
1599
////                                                              ////
1600
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1601
////                                                              ////
1602
//// This source file may be used and distributed without         ////
1603
//// restriction provided that this copyright statement is not    ////
1604
//// removed from the file and that any derivative work contains  ////
1605
//// the original copyright notice and the associated disclaimer. ////
1606
////                                                              ////
1607
//// This source file is free software; you can redistribute it   ////
1608
//// and/or modify it under the terms of the GNU Lesser General   ////
1609
//// Public License as published by the Free Software Foundation; ////
1610
//// either version 2.1 of the License, or (at your option) any   ////
1611
//// later version.                                               ////
1612
////                                                              ////
1613
//// This source is distributed in the hope that it will be       ////
1614
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1615
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1616
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1617
//// details.                                                     ////
1618
////                                                              ////
1619
//// You should have received a copy of the GNU Lesser General    ////
1620
//// Public License along with this source; if not, download it   ////
1621
//// from http://www.opencores.org/lgpl.shtml                     ////
1622
////                                                              ////
1623
//////////////////////////////////////////////////////////////////////
1624
// GRAY counter
1625 18 unneback
module vl_cnt_gray_ce ( cke, q, rst, clk);
1626 6 unneback
   parameter length = 4;
1627
   input cke;
1628
   output reg [length:1] q;
1629
   input rst;
1630
   input clk;
1631
   parameter clear_value = 0;
1632
   parameter set_value = 1;
1633
   parameter wrap_value = 8;
1634
   parameter level1_value = 15;
1635
   reg  [length:1] qi;
1636
   wire [length:1] q_next;
1637
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1638
   always @ (posedge clk or posedge rst)
1639
     if (rst)
1640
       qi <= {length{1'b0}};
1641
     else
1642
     if (cke)
1643
       qi <= q_next;
1644
   always @ (posedge clk or posedge rst)
1645
     if (rst)
1646
       q <= {length{1'b0}};
1647
     else
1648
       if (cke)
1649
         q <= (q_next>>1) ^ q_next;
1650
endmodule
1651
//////////////////////////////////////////////////////////////////////
1652
////                                                              ////
1653
////  Versatile counter                                           ////
1654
////                                                              ////
1655
////  Description                                                 ////
1656
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1657
////  counter                                                     ////
1658
////                                                              ////
1659
////  To Do:                                                      ////
1660
////   - add LFSR with more taps                                  ////
1661
////                                                              ////
1662
////  Author(s):                                                  ////
1663
////      - Michael Unneback, unneback@opencores.org              ////
1664
////        ORSoC AB                                              ////
1665
////                                                              ////
1666
//////////////////////////////////////////////////////////////////////
1667
////                                                              ////
1668
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1669
////                                                              ////
1670
//// This source file may be used and distributed without         ////
1671
//// restriction provided that this copyright statement is not    ////
1672
//// removed from the file and that any derivative work contains  ////
1673
//// the original copyright notice and the associated disclaimer. ////
1674
////                                                              ////
1675
//// This source file is free software; you can redistribute it   ////
1676
//// and/or modify it under the terms of the GNU Lesser General   ////
1677
//// Public License as published by the Free Software Foundation; ////
1678
//// either version 2.1 of the License, or (at your option) any   ////
1679
//// later version.                                               ////
1680
////                                                              ////
1681
//// This source is distributed in the hope that it will be       ////
1682
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1683
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1684
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1685
//// details.                                                     ////
1686
////                                                              ////
1687
//// You should have received a copy of the GNU Lesser General    ////
1688
//// Public License along with this source; if not, download it   ////
1689
//// from http://www.opencores.org/lgpl.shtml                     ////
1690
////                                                              ////
1691
//////////////////////////////////////////////////////////////////////
1692
// GRAY counter
1693 18 unneback
module vl_cnt_gray_ce_bin ( cke, q, q_bin, rst, clk);
1694 6 unneback
   parameter length = 4;
1695
   input cke;
1696
   output reg [length:1] q;
1697
   output [length:1] q_bin;
1698
   input rst;
1699
   input clk;
1700
   parameter clear_value = 0;
1701
   parameter set_value = 1;
1702
   parameter wrap_value = 8;
1703
   parameter level1_value = 15;
1704
   reg  [length:1] qi;
1705
   wire [length:1] q_next;
1706
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1707
   always @ (posedge clk or posedge rst)
1708
     if (rst)
1709
       qi <= {length{1'b0}};
1710
     else
1711
     if (cke)
1712
       qi <= q_next;
1713
   always @ (posedge clk or posedge rst)
1714
     if (rst)
1715
       q <= {length{1'b0}};
1716
     else
1717
       if (cke)
1718
         q <= (q_next>>1) ^ q_next;
1719
   assign q_bin = qi;
1720
endmodule
1721
//////////////////////////////////////////////////////////////////////
1722
////                                                              ////
1723
////  Versatile library, counters                                 ////
1724
////                                                              ////
1725
////  Description                                                 ////
1726
////  counters                                                    ////
1727
////                                                              ////
1728
////                                                              ////
1729
////  To Do:                                                      ////
1730
////   - add more counters                                        ////
1731
////                                                              ////
1732
////  Author(s):                                                  ////
1733
////      - Michael Unneback, unneback@opencores.org              ////
1734
////        ORSoC AB                                              ////
1735
////                                                              ////
1736
//////////////////////////////////////////////////////////////////////
1737
////                                                              ////
1738
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1739
////                                                              ////
1740
//// This source file may be used and distributed without         ////
1741
//// restriction provided that this copyright statement is not    ////
1742
//// removed from the file and that any derivative work contains  ////
1743
//// the original copyright notice and the associated disclaimer. ////
1744
////                                                              ////
1745
//// This source file is free software; you can redistribute it   ////
1746
//// and/or modify it under the terms of the GNU Lesser General   ////
1747
//// Public License as published by the Free Software Foundation; ////
1748
//// either version 2.1 of the License, or (at your option) any   ////
1749
//// later version.                                               ////
1750
////                                                              ////
1751
//// This source is distributed in the hope that it will be       ////
1752
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1753
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1754
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1755
//// details.                                                     ////
1756
////                                                              ////
1757
//// You should have received a copy of the GNU Lesser General    ////
1758
//// Public License along with this source; if not, download it   ////
1759
//// from http://www.opencores.org/lgpl.shtml                     ////
1760
////                                                              ////
1761
//////////////////////////////////////////////////////////////////////
1762 18 unneback
module vl_cnt_shreg_wrap ( q, rst, clk);
1763 6 unneback
   parameter length = 4;
1764
   output reg [0:length-1] q;
1765
   input rst;
1766
   input clk;
1767
    always @ (posedge clk or posedge rst)
1768
    if (rst)
1769
        q <= {1'b1,{length-1{1'b0}}};
1770
    else
1771
        q <= {q[length-1],q[0:length-2]};
1772
endmodule
1773 18 unneback
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
1774 6 unneback
   parameter length = 4;
1775
   input cke;
1776
   output reg [0:length-1] q;
1777
   input rst;
1778
   input clk;
1779
    always @ (posedge clk or posedge rst)
1780
    if (rst)
1781
        q <= {1'b1,{length-1{1'b0}}};
1782
    else
1783
        if (cke)
1784
            q <= {q[length-1],q[0:length-2]};
1785
endmodule
1786 18 unneback
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
1787 6 unneback
   parameter length = 4;
1788
   input cke, clear;
1789
   output reg [0:length-1] q;
1790
   input rst;
1791
   input clk;
1792
    always @ (posedge clk or posedge rst)
1793
    if (rst)
1794
        q <= {1'b1,{length-1{1'b0}}};
1795
    else
1796
        if (cke)
1797
            if (clear)
1798
                q <= {1'b1,{length-1{1'b0}}};
1799
            else
1800
                q <= q >> 1;
1801
endmodule
1802 18 unneback
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
1803 6 unneback
   parameter length = 4;
1804
   input cke, clear;
1805
   output reg [0:length-1] q;
1806
   input rst;
1807
   input clk;
1808
    always @ (posedge clk or posedge rst)
1809
    if (rst)
1810
        q <= {1'b1,{length-1{1'b0}}};
1811
    else
1812
        if (cke)
1813
            if (clear)
1814
                q <= {1'b1,{length-1{1'b0}}};
1815
            else
1816
            q <= {q[length-1],q[0:length-2]};
1817
endmodule
1818
//////////////////////////////////////////////////////////////////////
1819
////                                                              ////
1820
////  Versatile library, memories                                 ////
1821
////                                                              ////
1822
////  Description                                                 ////
1823
////  memories                                                    ////
1824
////                                                              ////
1825
////                                                              ////
1826
////  To Do:                                                      ////
1827
////   - add more memory types                                    ////
1828
////                                                              ////
1829
////  Author(s):                                                  ////
1830
////      - Michael Unneback, unneback@opencores.org              ////
1831
////        ORSoC AB                                              ////
1832
////                                                              ////
1833
//////////////////////////////////////////////////////////////////////
1834
////                                                              ////
1835
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1836
////                                                              ////
1837
//// This source file may be used and distributed without         ////
1838
//// restriction provided that this copyright statement is not    ////
1839
//// removed from the file and that any derivative work contains  ////
1840
//// the original copyright notice and the associated disclaimer. ////
1841
////                                                              ////
1842
//// This source file is free software; you can redistribute it   ////
1843
//// and/or modify it under the terms of the GNU Lesser General   ////
1844
//// Public License as published by the Free Software Foundation; ////
1845
//// either version 2.1 of the License, or (at your option) any   ////
1846
//// later version.                                               ////
1847
////                                                              ////
1848
//// This source is distributed in the hope that it will be       ////
1849
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1850
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1851
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1852
//// details.                                                     ////
1853
////                                                              ////
1854
//// You should have received a copy of the GNU Lesser General    ////
1855
//// Public License along with this source; if not, download it   ////
1856
//// from http://www.opencores.org/lgpl.shtml                     ////
1857
////                                                              ////
1858
//////////////////////////////////////////////////////////////////////
1859
/// ROM
1860 7 unneback
module vl_rom_init ( adr, q, clk);
1861
   parameter data_width = 32;
1862
   parameter addr_width = 8;
1863
   input [(addr_width-1):0]       adr;
1864
   output reg [(data_width-1):0] q;
1865
   input                         clk;
1866
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
1867
   parameter memory_file = "vl_rom.vmem";
1868
   initial
1869
     begin
1870
        $readmemh(memory_file, rom);
1871
     end
1872
   always @ (posedge clk)
1873
     q <= rom[adr];
1874
endmodule
1875 14 unneback
/*
1876 7 unneback
module vl_rom ( adr, q, clk);
1877 6 unneback
parameter data_width = 32;
1878
parameter addr_width = 4;
1879
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
1880
    {32'h18000000},
1881
    {32'hA8200000},
1882
    {32'hA8200000},
1883
    {32'hA8200000},
1884
    {32'h44003000},
1885
    {32'h15000000},
1886
    {32'h15000000},
1887
    {32'h15000000},
1888
    {32'h15000000},
1889
    {32'h15000000},
1890
    {32'h15000000},
1891
    {32'h15000000},
1892
    {32'h15000000},
1893
    {32'h15000000},
1894
    {32'h15000000},
1895
    {32'h15000000}};
1896 7 unneback
input [addr_width-1:0] adr;
1897 6 unneback
output reg [data_width-1:0] q;
1898
input clk;
1899
always @ (posedge clk)
1900 7 unneback
    q <= data[adr];
1901 6 unneback
endmodule
1902 14 unneback
*/
1903 6 unneback
// Single port RAM
1904
module vl_ram ( d, adr, we, q, clk);
1905
   parameter data_width = 32;
1906
   parameter addr_width = 8;
1907
   input [(data_width-1):0]      d;
1908
   input [(addr_width-1):0]       adr;
1909
   input                         we;
1910 7 unneback
   output reg [(data_width-1):0] q;
1911 6 unneback
   input                         clk;
1912
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
1913 7 unneback
   parameter init = 0;
1914
   parameter memory_file = "vl_ram.vmem";
1915
   generate if (init) begin : init_mem
1916
   initial
1917
     begin
1918
        $readmemh(memory_file, ram);
1919
     end
1920
   end
1921
   endgenerate
1922 6 unneback
   always @ (posedge clk)
1923
   begin
1924
   if (we)
1925
     ram[adr] <= d;
1926
   q <= ram[adr];
1927
   end
1928
endmodule
1929 7 unneback
module vl_ram_be ( d, adr, be, we, q, clk);
1930
   parameter data_width = 32;
1931
   parameter addr_width = 8;
1932
   input [(data_width-1):0]      d;
1933
   input [(addr_width-1):0]       adr;
1934
   input [(addr_width/4)-1:0]    be;
1935
   input                         we;
1936
   output reg [(data_width-1):0] q;
1937
   input                         clk;
1938
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
1939
   parameter init = 0;
1940
   parameter memory_file = "vl_ram.vmem";
1941
   generate if (init) begin : init_mem
1942
   initial
1943
     begin
1944
        $readmemh(memory_file, ram);
1945
     end
1946
   end
1947
   endgenerate
1948
   genvar i;
1949
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
1950
      always @ (posedge clk)
1951
      if (we & be[i])
1952
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
1953
   end
1954
   endgenerate
1955
   always @ (posedge clk)
1956
      q <= ram[adr];
1957
endmodule
1958 6 unneback
// Dual port RAM
1959
// ACTEL FPGA should not use logic to handle rw collision
1960 7 unneback
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1961 6 unneback
   parameter data_width = 32;
1962
   parameter addr_width = 8;
1963
   input [(data_width-1):0]      d_a;
1964
   input [(addr_width-1):0]       adr_a;
1965
   input [(addr_width-1):0]       adr_b;
1966
   input                         we_a;
1967
   output [(data_width-1):0]      q_b;
1968
   input                         clk_a, clk_b;
1969
   reg [(addr_width-1):0]         adr_b_reg;
1970
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
1971 7 unneback
   parameter init = 0;
1972
   parameter memory_file = "vl_ram.vmem";
1973
   generate if (init) begin : init_mem
1974
   initial
1975
     begin
1976
        $readmemh(memory_file, ram);
1977
     end
1978
   end
1979
   endgenerate
1980 6 unneback
   always @ (posedge clk_a)
1981
   if (we_a)
1982
     ram[adr_a] <= d_a;
1983
   always @ (posedge clk_b)
1984
   adr_b_reg <= adr_b;
1985
   assign q_b = ram[adr_b_reg];
1986
endmodule
1987 7 unneback
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1988 6 unneback
   parameter data_width = 32;
1989
   parameter addr_width = 8;
1990
   input [(data_width-1):0]      d_a;
1991
   input [(addr_width-1):0]       adr_a;
1992
   input [(addr_width-1):0]       adr_b;
1993
   input                         we_a;
1994
   output [(data_width-1):0]      q_b;
1995
   output reg [(data_width-1):0] q_a;
1996
   input                         clk_a, clk_b;
1997
   reg [(data_width-1):0]         q_b;
1998
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
1999 7 unneback
   parameter init = 0;
2000
   parameter memory_file = "vl_ram.vmem";
2001
   generate if (init) begin : init_mem
2002
   initial
2003
     begin
2004
        $readmemh(memory_file, ram);
2005
     end
2006
   end
2007
   endgenerate
2008 6 unneback
   always @ (posedge clk_a)
2009
     begin
2010
        q_a <= ram[adr_a];
2011
        if (we_a)
2012
             ram[adr_a] <= d_a;
2013
     end
2014
   always @ (posedge clk_b)
2015
          q_b <= ram[adr_b];
2016
endmodule
2017 7 unneback
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
2018 6 unneback
   parameter data_width = 32;
2019
   parameter addr_width = 8;
2020
   input [(data_width-1):0]      d_a;
2021
   input [(addr_width-1):0]       adr_a;
2022
   input [(addr_width-1):0]       adr_b;
2023
   input                         we_a;
2024
   output [(data_width-1):0]      q_b;
2025
   input [(data_width-1):0]       d_b;
2026
   output reg [(data_width-1):0] q_a;
2027
   input                         we_b;
2028
   input                         clk_a, clk_b;
2029
   reg [(data_width-1):0]         q_b;
2030
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
2031 7 unneback
   parameter init = 0;
2032
   parameter memory_file = "vl_ram.vmem";
2033
   generate if (init) begin : init_mem
2034
   initial
2035
     begin
2036
        $readmemh(memory_file, ram);
2037
     end
2038
   end
2039
   endgenerate
2040 6 unneback
   always @ (posedge clk_a)
2041
     begin
2042
        q_a <= ram[adr_a];
2043
        if (we_a)
2044
             ram[adr_a] <= d_a;
2045
     end
2046
   always @ (posedge clk_b)
2047
     begin
2048
        q_b <= ram[adr_b];
2049
        if (we_b)
2050
          ram[adr_b] <= d_b;
2051
     end
2052
endmodule
2053
// Content addresable memory, CAM
2054
// FIFO
2055 25 unneback
module vl_fifo_1r1w_fill_level_sync (
2056
    d, wr, fifo_full,
2057
    q, rd, fifo_empty,
2058
    fill_level,
2059
    clk, rst
2060
    );
2061
parameter data_width = 18;
2062
parameter addr_width = 4;
2063
// write side
2064
input  [data_width-1:0] d;
2065
input                   wr;
2066
output                  fifo_full;
2067
// read side
2068
output [data_width-1:0] q;
2069
input                   rd;
2070
output                  fifo_empty;
2071
// common
2072
output [addr_width:0]   fill_level;
2073
input rst, clk;
2074
wire [addr_width:1] wadr, radr;
2075
vl_cnt_bin_ce
2076
    # ( .length(addr_width))
2077
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
2078
vl_cnt_bin_ce
2079
    # (.length(addr_width))
2080
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
2081
vl_dpram_1r1w
2082
    # (.data_width(data_width), .addr_width(addr_width))
2083
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
2084
vl_cnt_bin_ce_rew_zq_l1
2085
    # (.length(addr_width+1), .level1(1<<add_width))
2086
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
2087
endmodule
2088 6 unneback
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
2089 11 unneback
   parameter addr_width = 4;
2090
   parameter N = addr_width-1;
2091 6 unneback
   parameter Q1 = 2'b00;
2092
   parameter Q2 = 2'b01;
2093
   parameter Q3 = 2'b11;
2094
   parameter Q4 = 2'b10;
2095
   parameter going_empty = 1'b0;
2096
   parameter going_full  = 1'b1;
2097
   input [N:0]  wptr, rptr;
2098 14 unneback
   output       fifo_empty;
2099 6 unneback
   output       fifo_full;
2100
   input        wclk, rclk, rst;
2101
   wire direction;
2102
   reg  direction_set, direction_clr;
2103
   wire async_empty, async_full;
2104
   wire fifo_full2;
2105 14 unneback
   wire fifo_empty2;
2106 6 unneback
   // direction_set
2107
   always @ (wptr[N:N-1] or rptr[N:N-1])
2108
     case ({wptr[N:N-1],rptr[N:N-1]})
2109
       {Q1,Q2} : direction_set <= 1'b1;
2110
       {Q2,Q3} : direction_set <= 1'b1;
2111
       {Q3,Q4} : direction_set <= 1'b1;
2112
       {Q4,Q1} : direction_set <= 1'b1;
2113
       default : direction_set <= 1'b0;
2114
     endcase
2115
   // direction_clear
2116
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
2117
     if (rst)
2118
       direction_clr <= 1'b1;
2119
     else
2120
       case ({wptr[N:N-1],rptr[N:N-1]})
2121
         {Q2,Q1} : direction_clr <= 1'b1;
2122
         {Q3,Q2} : direction_clr <= 1'b1;
2123
         {Q4,Q3} : direction_clr <= 1'b1;
2124
         {Q1,Q4} : direction_clr <= 1'b1;
2125
         default : direction_clr <= 1'b0;
2126
       endcase
2127 18 unneback
    vl_dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
2128 6 unneback
   assign async_empty = (wptr == rptr) && (direction==going_empty);
2129
   assign async_full  = (wptr == rptr) && (direction==going_full);
2130 18 unneback
    vl_dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
2131
    vl_dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
2132 6 unneback
/*
2133
   always @ (posedge wclk or posedge rst or posedge async_full)
2134
     if (rst)
2135
       {fifo_full, fifo_full2} <= 2'b00;
2136
     else if (async_full)
2137
       {fifo_full, fifo_full2} <= 2'b11;
2138
     else
2139
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
2140
*/
2141 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
2142 6 unneback
     if (async_empty)
2143
       {fifo_empty, fifo_empty2} <= 2'b11;
2144
     else
2145 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
2146 18 unneback
    vl_dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
2147
    vl_dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
2148 6 unneback
endmodule // async_comp
2149
module vl_fifo_1r1w_async (
2150
    d, wr, fifo_full, wr_clk, wr_rst,
2151
    q, rd, fifo_empty, rd_clk, rd_rst
2152
    );
2153
parameter data_width = 18;
2154
parameter addr_width = 4;
2155
// write side
2156
input  [data_width-1:0] d;
2157
input                   wr;
2158
output                  fifo_full;
2159
input                   wr_clk;
2160
input                   wr_rst;
2161
// read side
2162
output [data_width-1:0] q;
2163
input                   rd;
2164
output                  fifo_empty;
2165
input                   rd_clk;
2166
input                   rd_rst;
2167
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
2168 18 unneback
vl_cnt_gray_ce_bin
2169 6 unneback
    # ( .length(addr_width))
2170
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
2171 18 unneback
vl_cnt_gray_ce_bin
2172 6 unneback
    # (.length(addr_width))
2173 23 unneback
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
2174 7 unneback
vl_dpram_1r1w
2175 6 unneback
    # (.data_width(data_width), .addr_width(addr_width))
2176
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
2177
vl_fifo_cmp_async
2178
    # (.addr_width(addr_width))
2179
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
2180
endmodule
2181 8 unneback
module vl_fifo_2r2w_async (
2182 6 unneback
    // a side
2183
    a_d, a_wr, a_fifo_full,
2184
    a_q, a_rd, a_fifo_empty,
2185
    a_clk, a_rst,
2186
    // b side
2187
    b_d, b_wr, b_fifo_full,
2188
    b_q, b_rd, b_fifo_empty,
2189
    b_clk, b_rst
2190
    );
2191
parameter data_width = 18;
2192
parameter addr_width = 4;
2193
// a side
2194
input  [data_width-1:0] a_d;
2195
input                   a_wr;
2196
output                  a_fifo_full;
2197
output [data_width-1:0] a_q;
2198
input                   a_rd;
2199
output                  a_fifo_empty;
2200
input                   a_clk;
2201
input                   a_rst;
2202
// b side
2203
input  [data_width-1:0] b_d;
2204
input                   b_wr;
2205
output                  b_fifo_full;
2206
output [data_width-1:0] b_q;
2207
input                   b_rd;
2208
output                  b_fifo_empty;
2209
input                   b_clk;
2210
input                   b_rst;
2211
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
2212
vl_fifo_1r1w_async_a (
2213
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
2214
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
2215
    );
2216
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
2217
vl_fifo_1r1w_async_b (
2218
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
2219
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
2220
    );
2221
endmodule
2222 8 unneback
module vl_fifo_2r2w_async_simplex (
2223 6 unneback
    // a side
2224
    a_d, a_wr, a_fifo_full,
2225
    a_q, a_rd, a_fifo_empty,
2226
    a_clk, a_rst,
2227
    // b side
2228
    b_d, b_wr, b_fifo_full,
2229
    b_q, b_rd, b_fifo_empty,
2230
    b_clk, b_rst
2231
    );
2232
parameter data_width = 18;
2233
parameter addr_width = 4;
2234
// a side
2235
input  [data_width-1:0] a_d;
2236
input                   a_wr;
2237
output                  a_fifo_full;
2238
output [data_width-1:0] a_q;
2239
input                   a_rd;
2240
output                  a_fifo_empty;
2241
input                   a_clk;
2242
input                   a_rst;
2243
// b side
2244
input  [data_width-1:0] b_d;
2245
input                   b_wr;
2246
output                  b_fifo_full;
2247
output [data_width-1:0] b_q;
2248
input                   b_rd;
2249
output                  b_fifo_empty;
2250
input                   b_clk;
2251
input                   b_rst;
2252
// adr_gen
2253
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
2254
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
2255
// dpram
2256
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
2257 18 unneback
vl_cnt_gray_ce_bin
2258 6 unneback
    # ( .length(addr_width))
2259
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
2260 18 unneback
vl_cnt_gray_ce_bin
2261 6 unneback
    # (.length(addr_width))
2262
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
2263 18 unneback
vl_cnt_gray_ce_bin
2264 6 unneback
    # ( .length(addr_width))
2265
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
2266 18 unneback
vl_cnt_gray_ce_bin
2267 6 unneback
    # (.length(addr_width))
2268
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
2269
// mux read or write adr to DPRAM
2270
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
2271
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
2272 11 unneback
vl_dpram_2r2w
2273 6 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
2274
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
2275
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
2276 11 unneback
vl_fifo_cmp_async
2277 6 unneback
    # (.addr_width(addr_width))
2278
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
2279 11 unneback
vl_fifo_cmp_async
2280 6 unneback
    # (.addr_width(addr_width))
2281
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
2282
endmodule
2283 12 unneback
//////////////////////////////////////////////////////////////////////
2284
////                                                              ////
2285
////  Versatile library, wishbone stuff                           ////
2286
////                                                              ////
2287
////  Description                                                 ////
2288
////  Wishbone compliant modules                                  ////
2289
////                                                              ////
2290
////                                                              ////
2291
////  To Do:                                                      ////
2292
////   -                                                          ////
2293
////                                                              ////
2294
////  Author(s):                                                  ////
2295
////      - Michael Unneback, unneback@opencores.org              ////
2296
////        ORSoC AB                                              ////
2297
////                                                              ////
2298
//////////////////////////////////////////////////////////////////////
2299
////                                                              ////
2300
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2301
////                                                              ////
2302
//// This source file may be used and distributed without         ////
2303
//// restriction provided that this copyright statement is not    ////
2304
//// removed from the file and that any derivative work contains  ////
2305
//// the original copyright notice and the associated disclaimer. ////
2306
////                                                              ////
2307
//// This source file is free software; you can redistribute it   ////
2308
//// and/or modify it under the terms of the GNU Lesser General   ////
2309
//// Public License as published by the Free Software Foundation; ////
2310
//// either version 2.1 of the License, or (at your option) any   ////
2311
//// later version.                                               ////
2312
////                                                              ////
2313
//// This source is distributed in the hope that it will be       ////
2314
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2315
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2316
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2317
//// details.                                                     ////
2318
////                                                              ////
2319
//// You should have received a copy of the GNU Lesser General    ////
2320
//// Public License along with this source; if not, download it   ////
2321
//// from http://www.opencores.org/lgpl.shtml                     ////
2322
////                                                              ////
2323
//////////////////////////////////////////////////////////////////////
2324
// async wb3 - wb3 bridge
2325
`timescale 1ns/1ns
2326 18 unneback
module vl_wb3wb3_bridge (
2327 12 unneback
        // wishbone slave side
2328
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
2329
        // wishbone master side
2330
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
2331
input [31:0] wbs_dat_i;
2332
input [31:2] wbs_adr_i;
2333
input [3:0]  wbs_sel_i;
2334
input [1:0]  wbs_bte_i;
2335
input [2:0]  wbs_cti_i;
2336
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
2337
output [31:0] wbs_dat_o;
2338 14 unneback
output wbs_ack_o;
2339 12 unneback
input wbs_clk, wbs_rst;
2340
output [31:0] wbm_dat_o;
2341
output reg [31:2] wbm_adr_o;
2342
output [3:0]  wbm_sel_o;
2343
output reg [1:0]  wbm_bte_o;
2344
output reg [2:0]  wbm_cti_o;
2345 14 unneback
output reg wbm_we_o;
2346
output wbm_cyc_o;
2347 12 unneback
output wbm_stb_o;
2348
input [31:0]  wbm_dat_i;
2349
input wbm_ack_i;
2350
input wbm_clk, wbm_rst;
2351
parameter addr_width = 4;
2352
// bte
2353
parameter linear       = 2'b00;
2354
parameter wrap4        = 2'b01;
2355
parameter wrap8        = 2'b10;
2356
parameter wrap16       = 2'b11;
2357
// cti
2358
parameter classic      = 3'b000;
2359
parameter incburst     = 3'b010;
2360
parameter endofburst   = 3'b111;
2361
parameter wbs_adr  = 1'b0;
2362
parameter wbs_data = 1'b1;
2363
parameter wbm_adr0 = 2'b00;
2364
parameter wbm_adr1 = 2'b01;
2365
parameter wbm_data = 2'b10;
2366
reg [1:0] wbs_bte_reg;
2367
reg wbs;
2368
wire wbs_eoc_alert, wbm_eoc_alert;
2369
reg wbs_eoc, wbm_eoc;
2370
reg [1:0] wbm;
2371 14 unneback
wire [1:16] wbs_count, wbm_count;
2372 12 unneback
wire [35:0] a_d, a_q, b_d, b_q;
2373
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
2374
reg a_rd_reg;
2375
wire b_rd_adr, b_rd_data;
2376 14 unneback
wire b_rd_data_reg;
2377
wire [35:0] temp;
2378 12 unneback
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
2379
always @ (posedge wbs_clk or posedge wbs_rst)
2380
if (wbs_rst)
2381
        wbs_eoc <= 1'b0;
2382
else
2383
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
2384
                wbs_eoc <= wbs_bte_i==linear;
2385
        else if (wbs_eoc_alert & (a_rd | a_wr))
2386
                wbs_eoc <= 1'b1;
2387 18 unneback
vl_cnt_shreg_ce_clear # ( .length(16))
2388 12 unneback
    cnt0 (
2389
        .cke(wbs_ack_o),
2390
        .clear(wbs_eoc),
2391
        .q(wbs_count),
2392
        .rst(wbs_rst),
2393
        .clk(wbs_clk));
2394
always @ (posedge wbs_clk or posedge wbs_rst)
2395
if (wbs_rst)
2396
        wbs <= wbs_adr;
2397
else
2398
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & !a_fifo_full)
2399
                wbs <= wbs_data;
2400
        else if (wbs_eoc & wbs_ack_o)
2401
                wbs <= wbs_adr;
2402
// wbs FIFO
2403
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,wbs_bte_i,wbs_cti_i} : {wbs_dat_i,wbs_sel_i};
2404
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & !a_fifo_full :
2405
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
2406
              1'b0;
2407
assign a_rd = !a_fifo_empty;
2408
always @ (posedge wbs_clk or posedge wbs_rst)
2409
if (wbs_rst)
2410
        a_rd_reg <= 1'b0;
2411
else
2412
        a_rd_reg <= a_rd;
2413
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
2414
assign wbs_dat_o = a_q[35:4];
2415
always @ (posedge wbs_clk or posedge wbs_rst)
2416
if (wbs_rst)
2417 13 unneback
        wbs_bte_reg <= 2'b00;
2418 12 unneback
else
2419 13 unneback
        wbs_bte_reg <= wbs_bte_i;
2420 12 unneback
// wbm FIFO
2421
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
2422
always @ (posedge wbm_clk or posedge wbm_rst)
2423
if (wbm_rst)
2424
        wbm_eoc <= 1'b0;
2425
else
2426
        if (wbm==wbm_adr0 & !b_fifo_empty)
2427
                wbm_eoc <= b_q[4:3] == linear;
2428
        else if (wbm_eoc_alert & wbm_ack_i)
2429
                wbm_eoc <= 1'b1;
2430
always @ (posedge wbm_clk or posedge wbm_rst)
2431
if (wbm_rst)
2432
        wbm <= wbm_adr0;
2433
else
2434
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
2435
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
2436
        (wbm==wbm_adr1 & !wbm_we_o) |
2437
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
2438
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
2439
assign b_d = {wbm_dat_i,4'b1111};
2440
assign b_wr = !wbm_we_o & wbm_ack_i;
2441
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
2442
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
2443
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
2444
                   1'b0;
2445
assign b_rd = b_rd_adr | b_rd_data;
2446 18 unneback
vl_dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
2447
vl_dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
2448 12 unneback
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
2449 18 unneback
vl_cnt_shreg_ce_clear # ( .length(16))
2450 12 unneback
    cnt1 (
2451
        .cke(wbm_ack_i),
2452
        .clear(wbm_eoc),
2453
        .q(wbm_count),
2454
        .rst(wbm_rst),
2455
        .clk(wbm_clk));
2456
assign wbm_cyc_o = wbm==wbm_data;
2457
assign wbm_stb_o = (wbm==wbm_data & wbm_we_o) ? !b_fifo_empty :
2458
                   (wbm==wbm_data) ? 1'b1 :
2459
                   1'b0;
2460
always @ (posedge wbm_clk or posedge wbm_rst)
2461
if (wbm_rst)
2462
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
2463
else begin
2464
        if (wbm==wbm_adr0 & !b_fifo_empty)
2465
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
2466
        else if (wbm_eoc_alert & wbm_ack_i)
2467
                wbm_cti_o <= endofburst;
2468
end
2469
//async_fifo_dw_simplex_top
2470
vl_fifo_2r2w_async_simplex
2471
# ( .data_width(36), .addr_width(addr_width))
2472
fifo (
2473
    // a side
2474
    .a_d(a_d),
2475
    .a_wr(a_wr),
2476
    .a_fifo_full(a_fifo_full),
2477
    .a_q(a_q),
2478
    .a_rd(a_rd),
2479
    .a_fifo_empty(a_fifo_empty),
2480
    .a_clk(wbs_clk),
2481
    .a_rst(wbs_rst),
2482
    // b side
2483
    .b_d(b_d),
2484
    .b_wr(b_wr),
2485
    .b_fifo_full(b_fifo_full),
2486
    .b_q(b_q),
2487
    .b_rd(b_rd),
2488
    .b_fifo_empty(b_fifo_empty),
2489
    .b_clk(wbm_clk),
2490
    .b_rst(wbm_rst)
2491
    );
2492
endmodule
2493 17 unneback
// WB ROM
2494 18 unneback
module vl_wb_boot_rom (
2495 17 unneback
    wb_adr_i, wb_stb_i, wb_cyc_i,
2496 18 unneback
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
2497
    parameter adr_hi = 31;
2498
    parameter adr_lo = 28;
2499
    parameter adr_sel = 4'hf;
2500
    parameter addr_width = 5;
2501 17 unneback
`ifndef BOOT_ROM
2502
`define BOOT_ROM "boot_rom.v"
2503
`endif
2504 18 unneback
    input [adr_hi:2]    wb_adr_i;
2505
    input               wb_stb_i;
2506
    input               wb_cyc_i;
2507
    output [31:0]        wb_dat_o;
2508
    output              wb_ack_o;
2509
    output              hit_o;
2510
    input               wb_clk;
2511
    input               wb_rst;
2512
    wire hit;
2513
    reg [31:0] wb_dat;
2514
    reg wb_ack;
2515
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
2516 17 unneback
always @ (posedge wb_clk or posedge wb_rst)
2517
    if (wb_rst)
2518 18 unneback
        wb_dat <= 32'h15000000;
2519 17 unneback
    else
2520 18 unneback
         case (wb_adr_i[addr_width-1:2])
2521 17 unneback
`include `BOOT_ROM
2522
           /*
2523
            // Zero r0 and jump to 0x00000100
2524 18 unneback
 
2525
            1 : wb_dat <= 32'hA8200000;
2526
            2 : wb_dat <= 32'hA8C00100;
2527
            3 : wb_dat <= 32'h44003000;
2528
            4 : wb_dat <= 32'h15000000;
2529 17 unneback
            */
2530
           default:
2531 18 unneback
             wb_dat <= 32'h00000000;
2532 17 unneback
         endcase // case (wb_adr_i)
2533
always @ (posedge wb_clk or posedge wb_rst)
2534
    if (wb_rst)
2535 18 unneback
        wb_ack <= 1'b0;
2536 17 unneback
    else
2537 18 unneback
        wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
2538
assign hit_o = hit;
2539
assign wb_dat_o = wb_dat & {32{wb_ack}};
2540
assign wb_ack_o = wb_ack;
2541 17 unneback
endmodule
2542 18 unneback
//////////////////////////////////////////////////////////////////////
2543
////                                                              ////
2544
////  Arithmetic functions                                        ////
2545
////                                                              ////
2546
////  Description                                                 ////
2547
////  Arithmetic functions for ALU and DSP                        ////
2548
////                                                              ////
2549
////                                                              ////
2550
////  To Do:                                                      ////
2551
////   -                                                          ////
2552
////                                                              ////
2553
////  Author(s):                                                  ////
2554
////      - Michael Unneback, unneback@opencores.org              ////
2555
////        ORSoC AB                                              ////
2556
////                                                              ////
2557
//////////////////////////////////////////////////////////////////////
2558
////                                                              ////
2559
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2560
////                                                              ////
2561
//// This source file may be used and distributed without         ////
2562
//// restriction provided that this copyright statement is not    ////
2563
//// removed from the file and that any derivative work contains  ////
2564
//// the original copyright notice and the associated disclaimer. ////
2565
////                                                              ////