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1 6 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  Versatile library, clock and reset                          ////
4
////                                                              ////
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////  Description                                                 ////
6
////  Logic related to clock and reset                            ////
7
////                                                              ////
8
////                                                              ////
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////  To Do:                                                      ////
10
////   - add more different registers                             ////
11
////                                                              ////
12
////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
14
////        ORSoC AB                                              ////
15
////                                                              ////
16
//////////////////////////////////////////////////////////////////////
17
////                                                              ////
18
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
19
////                                                              ////
20
//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
36
////                                                              ////
37
//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
// Global buffer
43
// usage:
44
// use to enable global buffers for high fan out signals such as clock and reset
45
`timescale 1 ns/100 ps
46
// Version: 8.4 8.4.0.33
47
module gbuf(GL,CLK);
48
output GL;
49
input  CLK;
50
    wire GND;
51
    GND GND_1_net(.Y(GND));
52
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
53
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
54
endmodule
55
`timescale 1 ns/1 ns
56
module vl_gbuf ( i, o);
57
input i;
58
output o;
59
`ifdef SIM_GBUF
60
assign o=i;
61
`else
62
gbuf gbuf_i0 ( .CLK(i), .GL(o));
63
`endif
64
endmodule
65
 //ACTEL
66
// sync reset
67 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
68 6 unneback
// output active high global reset sync with two DFFs 
69
`timescale 1 ns/100 ps
70
module vl_sync_rst ( rst_n_i, rst_o, clk);
71
input rst_n_i, clk;
72
output rst_o;
73 18 unneback
reg [1:0] tmp;
74 6 unneback
always @ (posedge clk or negedge rst_n_i)
75
if (!rst_n_i)
76 17 unneback
        tmp <= 2'b11;
77 6 unneback
else
78 17 unneback
        tmp <= {1'b0,tmp[0]};
79
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
80 6 unneback
endmodule
81
// vl_pll
82 17 unneback
`timescale 1 ps/1 ps
83 6 unneback
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
84
parameter index = 0;
85
parameter number_of_clk = 1;
86 17 unneback
parameter period_time_0 = 20000;
87
parameter period_time_1 = 20000;
88
parameter period_time_2 = 20000;
89
parameter lock_delay = 2000000;
90 6 unneback
input clk_i, rst_n_i;
91
output lock;
92
output reg [0:number_of_clk-1] clk_o;
93
output [0:number_of_clk-1] rst_o;
94
`ifdef SIM_PLL
95
always
96
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
97
generate if (number_of_clk > 1)
98
always
99
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
100
endgenerate
101
generate if (number_of_clk > 2)
102
always
103
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
104
endgenerate
105
genvar i;
106
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
107
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
108
end
109
endgenerate
110
assign #lock_delay lock = rst_n_i;
111
endmodule
112
`else
113
generate if (number_of_clk==1 & index==0) begin
114
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
115
end
116
endgenerate // index==0
117
generate if (number_of_clk==1 & index==1) begin
118
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
119
end
120
endgenerate // index==1
121
generate if (number_of_clk==1 & index==2) begin
122
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
123
end
124
endgenerate // index==2
125
generate if (number_of_clk==1 & index==3) begin
126
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
127
end
128
endgenerate // index==0
129
generate if (number_of_clk==2 & index==0) begin
130
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
131
end
132
endgenerate // index==0
133
generate if (number_of_clk==2 & index==1) begin
134
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
135
end
136
endgenerate // index==1
137
generate if (number_of_clk==2 & index==2) begin
138
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
139
end
140
endgenerate // index==2
141
generate if (number_of_clk==2 & index==3) begin
142
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
143
end
144
endgenerate // index==0
145
generate if (number_of_clk==3 & index==0) begin
146
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
147
end
148
endgenerate // index==0
149
generate if (number_of_clk==3 & index==1) begin
150
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
151
end
152
endgenerate // index==1
153
generate if (number_of_clk==3 & index==2) begin
154
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
155
end
156
endgenerate // index==2
157
generate if (number_of_clk==3 & index==3) begin
158
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
159
end
160
endgenerate // index==0
161
genvar i;
162
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
163
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
164
end
165
endgenerate
166
endmodule
167
`endif
168
 //actel
169
//////////////////////////////////////////////////////////////////////
170
////                                                              ////
171
////  Versatile library, registers                                ////
172
////                                                              ////
173
////  Description                                                 ////
174
////  Different type of registers                                 ////
175
////                                                              ////
176
////                                                              ////
177
////  To Do:                                                      ////
178
////   - add more different registers                             ////
179
////                                                              ////
180
////  Author(s):                                                  ////
181
////      - Michael Unneback, unneback@opencores.org              ////
182
////        ORSoC AB                                              ////
183
////                                                              ////
184
//////////////////////////////////////////////////////////////////////
185
////                                                              ////
186
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
187
////                                                              ////
188
//// This source file may be used and distributed without         ////
189
//// restriction provided that this copyright statement is not    ////
190
//// removed from the file and that any derivative work contains  ////
191
//// the original copyright notice and the associated disclaimer. ////
192
////                                                              ////
193
//// This source file is free software; you can redistribute it   ////
194
//// and/or modify it under the terms of the GNU Lesser General   ////
195
//// Public License as published by the Free Software Foundation; ////
196
//// either version 2.1 of the License, or (at your option) any   ////
197
//// later version.                                               ////
198
////                                                              ////
199
//// This source is distributed in the hope that it will be       ////
200
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
201
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
202
//// PURPOSE.  See the GNU Lesser General Public License for more ////
203
//// details.                                                     ////
204
////                                                              ////
205
//// You should have received a copy of the GNU Lesser General    ////
206
//// Public License along with this source; if not, download it   ////
207
//// from http://www.opencores.org/lgpl.shtml                     ////
208
////                                                              ////
209
//////////////////////////////////////////////////////////////////////
210 18 unneback
module vl_dff ( d, q, clk, rst);
211 6 unneback
        parameter width = 1;
212
        parameter reset_value = 0;
213
        input [width-1:0] d;
214
        input clk, rst;
215
        output reg [width-1:0] q;
216
        always @ (posedge clk or posedge rst)
217
        if (rst)
218
                q <= reset_value;
219
        else
220
                q <= d;
221
endmodule
222 18 unneback
module vl_dff_array ( d, q, clk, rst);
223 6 unneback
        parameter width = 1;
224
        parameter depth = 2;
225
        parameter reset_value = 1'b0;
226
        input [width-1:0] d;
227
        input clk, rst;
228
        output [width-1:0] q;
229
        reg  [0:depth-1] q_tmp [width-1:0];
230
        integer i;
231
        always @ (posedge clk or posedge rst)
232
        if (rst) begin
233
            for (i=0;i<depth;i=i+1)
234
                q_tmp[i] <= {width{reset_value}};
235
        end else begin
236
            q_tmp[0] <= d;
237
            for (i=1;i<depth;i=i+1)
238
                q_tmp[i] <= q_tmp[i-1];
239
        end
240
    assign q = q_tmp[depth-1];
241
endmodule
242 18 unneback
module vl_dff_ce ( d, ce, q, clk, rst);
243 6 unneback
        parameter width = 1;
244
        parameter reset_value = 0;
245
        input [width-1:0] d;
246
        input ce, clk, rst;
247
        output reg [width-1:0] q;
248
        always @ (posedge clk or posedge rst)
249
        if (rst)
250
                q <= reset_value;
251
        else
252
                if (ce)
253
                        q <= d;
254
endmodule
255 18 unneback
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
256 8 unneback
        parameter width = 1;
257
        parameter reset_value = 0;
258
        input [width-1:0] d;
259 10 unneback
        input ce, clear, clk, rst;
260 8 unneback
        output reg [width-1:0] q;
261
        always @ (posedge clk or posedge rst)
262
        if (rst)
263
            q <= reset_value;
264
        else
265
            if (ce)
266
                if (clear)
267
                    q <= {width{1'b0}};
268
                else
269
                    q <= d;
270
endmodule
271 24 unneback
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
272
        parameter width = 1;
273
        parameter reset_value = 0;
274
        input [width-1:0] d;
275
        input ce, set, clk, rst;
276
        output reg [width-1:0] q;
277
        always @ (posedge clk or posedge rst)
278
        if (rst)
279
            q <= reset_value;
280
        else
281
            if (ce)
282
                if (set)
283
                    q <= {width{1'b1}};
284
                else
285
                    q <= d;
286
endmodule
287 29 unneback
module vl_spr ( sp, r, q, clk, rst);
288
        parameter width = 1;
289
        parameter reset_value = 0;
290
        input sp, r;
291
        output reg q;
292
        input clk, rst;
293
        always @ (posedge clk or posedge rst)
294
        if (rst)
295
            q <= reset_value;
296
        else
297
            if (sp)
298
                q <= 1'b1;
299
            else if (r)
300
                q <= 1'b0;
301
endmodule
302
module vl_srp ( s, rp, q, clk, rst);
303
        parameter width = 1;
304
        parameter reset_value = 0;
305
        input s, rp;
306
        output reg q;
307
        input clk, rst;
308
        always @ (posedge clk or posedge rst)
309
        if (rst)
310
            q <= reset_value;
311
        else
312
            if (rp)
313
                q <= 1'b0;
314
            else if (s)
315
                q <= 1'b1;
316
endmodule
317 18 unneback
module vl_dff_sr ( aclr, aset, clock, data, q);
318 6 unneback
    input         aclr;
319
    input         aset;
320
    input         clock;
321
    input         data;
322
    output reg    q;
323
   always @ (posedge clock or posedge aclr or posedge aset)
324
     if (aclr)
325
       q <= 1'b0;
326
     else if (aset)
327
       q <= 1'b1;
328
     else
329
       q <= data;
330
endmodule
331
// LATCH
332
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
333
module latch ( d, le, q, clk);
334
input d, le;
335
output q;
336
input clk;/*
337
   always @ (posedge direction_set or posedge direction_clr)
338
     if (direction_clr)
339
       direction <= going_empty;
340
     else
341
       direction <= going_full;*/
342
endmodule
343 18 unneback
module vl_shreg ( d, q, clk, rst);
344 17 unneback
parameter depth = 10;
345
input d;
346
output q;
347
input clk, rst;
348
reg [1:depth] dffs;
349
always @ (posedge clk or posedge rst)
350
if (rst)
351
    dffs <= {depth{1'b0}};
352
else
353
    dffs <= {d,dffs[1:depth-1]};
354
assign q = dffs[depth];
355
endmodule
356 18 unneback
module vl_shreg_ce ( d, ce, q, clk, rst);
357 17 unneback
parameter depth = 10;
358
input d, ce;
359
output q;
360
input clk, rst;
361
reg [1:depth] dffs;
362
always @ (posedge clk or posedge rst)
363
if (rst)
364
    dffs <= {depth{1'b0}};
365
else
366
    if (ce)
367
        dffs <= {d,dffs[1:depth-1]};
368
assign q = dffs[depth];
369
endmodule
370 18 unneback
module vl_delay ( d, q, clk, rst);
371 15 unneback
parameter depth = 10;
372
input d;
373
output q;
374
input clk, rst;
375
reg [1:depth] dffs;
376
always @ (posedge clk or posedge rst)
377
if (rst)
378
    dffs <= {depth{1'b0}};
379
else
380
    dffs <= {d,dffs[1:depth-1]};
381
assign q = dffs[depth];
382
endmodule
383 18 unneback
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
384 17 unneback
parameter depth = 10;
385
input d;
386
output q, emptyflag;
387
input clk, rst;
388
reg [1:depth] dffs;
389
always @ (posedge clk or posedge rst)
390
if (rst)
391
    dffs <= {depth{1'b0}};
392
else
393
    dffs <= {d,dffs[1:depth-1]};
394
assign q = dffs[depth];
395
assign emptyflag = !(|dffs);
396
endmodule
397 6 unneback
//////////////////////////////////////////////////////////////////////
398
////                                                              ////
399 18 unneback
////  Logic functions                                             ////
400
////                                                              ////
401
////  Description                                                 ////
402
////  Logic functions such as multiplexers                        ////
403
////                                                              ////
404
////                                                              ////
405
////  To Do:                                                      ////
406
////   -                                                          ////
407
////                                                              ////
408
////  Author(s):                                                  ////
409
////      - Michael Unneback, unneback@opencores.org              ////
410
////        ORSoC AB                                              ////
411
////                                                              ////
412
//////////////////////////////////////////////////////////////////////
413
////                                                              ////
414
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
415
////                                                              ////
416
//// This source file may be used and distributed without         ////
417
//// restriction provided that this copyright statement is not    ////
418
//// removed from the file and that any derivative work contains  ////
419
//// the original copyright notice and the associated disclaimer. ////
420
////                                                              ////
421
//// This source file is free software; you can redistribute it   ////
422
//// and/or modify it under the terms of the GNU Lesser General   ////
423
//// Public License as published by the Free Software Foundation; ////
424
//// either version 2.1 of the License, or (at your option) any   ////
425
//// later version.                                               ////
426
////                                                              ////
427
//// This source is distributed in the hope that it will be       ////
428
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
429
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
430
//// PURPOSE.  See the GNU Lesser General Public License for more ////
431
//// details.                                                     ////
432
////                                                              ////
433
//// You should have received a copy of the GNU Lesser General    ////
434
//// Public License along with this source; if not, download it   ////
435
//// from http://www.opencores.org/lgpl.shtml                     ////
436
////                                                              ////
437
//////////////////////////////////////////////////////////////////////
438
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
439
parameter width = 32;
440
parameter nr_of_ports = 4;
441
input [width-1:0] a3, a2, a1, a0;
442
input [nr_of_ports-1:0] sel;
443 22 unneback
output [width-1:0] dout;
444 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
445 18 unneback
integer i;
446
// and
447
assign tmp[0] = {width{sel[0]}} & a0;
448
assign tmp[1] = {width{sel[1]}} & a1;
449
assign tmp[2] = {width{sel[2]}} & a2;
450
assign tmp[3] = {width{sel[3]}} & a3;
451
// or
452
assign dout = tmp[3] | tmp[2] | tmp[1] | tmp[0];
453
endmodule
454
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
455
parameter width = 32;
456
parameter nr_of_ports = 5;
457
input [width-1:0] a4, a3, a2, a1, a0;
458
input [nr_of_ports-1:0] sel;
459 22 unneback
output [width-1:0] dout;
460 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
461 18 unneback
integer i;
462
// and
463
assign tmp[0] = {width{sel[0]}} & a0;
464
assign tmp[1] = {width{sel[1]}} & a1;
465
assign tmp[2] = {width{sel[2]}} & a2;
466
assign tmp[3] = {width{sel[3]}} & a3;
467
assign tmp[4] = {width{sel[4]}} & a4;
468
// or
469
assign dout = tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
470
endmodule
471
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
472
parameter width = 32;
473
parameter nr_of_ports = 6;
474
input [width-1:0] a5, a4, a3, a2, a1, a0;
475
input [nr_of_ports-1:0] sel;
476 22 unneback
output [width-1:0] dout;
477 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
478 18 unneback
integer i;
479
// and
480
assign tmp[0] = {width{sel[0]}} & a0;
481
assign tmp[1] = {width{sel[1]}} & a1;
482
assign tmp[2] = {width{sel[2]}} & a2;
483
assign tmp[3] = {width{sel[3]}} & a3;
484
assign tmp[4] = {width{sel[4]}} & a4;
485
assign tmp[5] = {width{sel[5]}} & a5;
486
// or
487
assign dout = tmp[5] | tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
488
endmodule
489
//////////////////////////////////////////////////////////////////////
490
////                                                              ////
491 6 unneback
////  Versatile counter                                           ////
492
////                                                              ////
493
////  Description                                                 ////
494
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
495
////  counter                                                     ////
496
////                                                              ////
497
////  To Do:                                                      ////
498
////   - add LFSR with more taps                                  ////
499
////                                                              ////
500
////  Author(s):                                                  ////
501
////      - Michael Unneback, unneback@opencores.org              ////
502
////        ORSoC AB                                              ////
503
////                                                              ////
504
//////////////////////////////////////////////////////////////////////
505
////                                                              ////
506
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
507
////                                                              ////
508
//// This source file may be used and distributed without         ////
509
//// restriction provided that this copyright statement is not    ////
510
//// removed from the file and that any derivative work contains  ////
511
//// the original copyright notice and the associated disclaimer. ////
512
////                                                              ////
513
//// This source file is free software; you can redistribute it   ////
514
//// and/or modify it under the terms of the GNU Lesser General   ////
515
//// Public License as published by the Free Software Foundation; ////
516
//// either version 2.1 of the License, or (at your option) any   ////
517
//// later version.                                               ////
518
////                                                              ////
519
//// This source is distributed in the hope that it will be       ////
520
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
521
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
522
//// PURPOSE.  See the GNU Lesser General Public License for more ////
523
//// details.                                                     ////
524
////                                                              ////
525
//// You should have received a copy of the GNU Lesser General    ////
526
//// Public License along with this source; if not, download it   ////
527
//// from http://www.opencores.org/lgpl.shtml                     ////
528
////                                                              ////
529
//////////////////////////////////////////////////////////////////////
530
// binary counter
531 22 unneback
module vl_cnt_bin ( q, rst, clk);
532
   parameter length = 4;
533
   output [length:1] q;
534
   input rst;
535
   input clk;
536
   parameter clear_value = 0;
537
   parameter set_value = 1;
538
   parameter wrap_value = 0;
539
   parameter level1_value = 15;
540
   reg  [length:1] qi;
541
   wire [length:1] q_next;
542
   assign q_next = qi + {{length-1{1'b0}},1'b1};
543
   always @ (posedge clk or posedge rst)
544
     if (rst)
545
       qi <= {length{1'b0}};
546
     else
547
       qi <= q_next;
548
   assign q = qi;
549
endmodule
550
//////////////////////////////////////////////////////////////////////
551
////                                                              ////
552
////  Versatile counter                                           ////
553
////                                                              ////
554
////  Description                                                 ////
555
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
556
////  counter                                                     ////
557
////                                                              ////
558
////  To Do:                                                      ////
559
////   - add LFSR with more taps                                  ////
560
////                                                              ////
561
////  Author(s):                                                  ////
562
////      - Michael Unneback, unneback@opencores.org              ////
563
////        ORSoC AB                                              ////
564
////                                                              ////
565
//////////////////////////////////////////////////////////////////////
566
////                                                              ////
567
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
568
////                                                              ////
569
//// This source file may be used and distributed without         ////
570
//// restriction provided that this copyright statement is not    ////
571
//// removed from the file and that any derivative work contains  ////
572
//// the original copyright notice and the associated disclaimer. ////
573
////                                                              ////
574
//// This source file is free software; you can redistribute it   ////
575
//// and/or modify it under the terms of the GNU Lesser General   ////
576
//// Public License as published by the Free Software Foundation; ////
577
//// either version 2.1 of the License, or (at your option) any   ////
578
//// later version.                                               ////
579
////                                                              ////
580
//// This source is distributed in the hope that it will be       ////
581
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
582
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
583
//// PURPOSE.  See the GNU Lesser General Public License for more ////
584
//// details.                                                     ////
585
////                                                              ////
586
//// You should have received a copy of the GNU Lesser General    ////
587
//// Public License along with this source; if not, download it   ////
588
//// from http://www.opencores.org/lgpl.shtml                     ////
589
////                                                              ////
590
//////////////////////////////////////////////////////////////////////
591
// binary counter
592
module vl_cnt_bin_clear ( clear, q, rst, clk);
593
   parameter length = 4;
594
   input clear;
595
   output [length:1] q;
596
   input rst;
597
   input clk;
598
   parameter clear_value = 0;
599
   parameter set_value = 1;
600
   parameter wrap_value = 0;
601
   parameter level1_value = 15;
602
   reg  [length:1] qi;
603
   wire [length:1] q_next;
604
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
605
   always @ (posedge clk or posedge rst)
606
     if (rst)
607
       qi <= {length{1'b0}};
608
     else
609
       qi <= q_next;
610
   assign q = qi;
611
endmodule
612
//////////////////////////////////////////////////////////////////////
613
////                                                              ////
614
////  Versatile counter                                           ////
615
////                                                              ////
616
////  Description                                                 ////
617
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
618
////  counter                                                     ////
619
////                                                              ////
620
////  To Do:                                                      ////
621
////   - add LFSR with more taps                                  ////
622
////                                                              ////
623
////  Author(s):                                                  ////
624
////      - Michael Unneback, unneback@opencores.org              ////
625
////        ORSoC AB                                              ////
626
////                                                              ////
627
//////////////////////////////////////////////////////////////////////
628
////                                                              ////
629
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
630
////                                                              ////
631
//// This source file may be used and distributed without         ////
632
//// restriction provided that this copyright statement is not    ////
633
//// removed from the file and that any derivative work contains  ////
634
//// the original copyright notice and the associated disclaimer. ////
635
////                                                              ////
636
//// This source file is free software; you can redistribute it   ////
637
//// and/or modify it under the terms of the GNU Lesser General   ////
638
//// Public License as published by the Free Software Foundation; ////
639
//// either version 2.1 of the License, or (at your option) any   ////
640
//// later version.                                               ////
641
////                                                              ////
642
//// This source is distributed in the hope that it will be       ////
643
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
644
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
645
//// PURPOSE.  See the GNU Lesser General Public License for more ////
646
//// details.                                                     ////
647
////                                                              ////
648
//// You should have received a copy of the GNU Lesser General    ////
649
//// Public License along with this source; if not, download it   ////
650
//// from http://www.opencores.org/lgpl.shtml                     ////
651
////                                                              ////
652
//////////////////////////////////////////////////////////////////////
653
// binary counter
654 18 unneback
module vl_cnt_bin_ce ( cke, q, rst, clk);
655 6 unneback
   parameter length = 4;
656
   input cke;
657
   output [length:1] q;
658
   input rst;
659
   input clk;
660
   parameter clear_value = 0;
661
   parameter set_value = 1;
662
   parameter wrap_value = 0;
663
   parameter level1_value = 15;
664
   reg  [length:1] qi;
665
   wire [length:1] q_next;
666
   assign q_next = qi + {{length-1{1'b0}},1'b1};
667
   always @ (posedge clk or posedge rst)
668
     if (rst)
669
       qi <= {length{1'b0}};
670
     else
671
     if (cke)
672
       qi <= q_next;
673
   assign q = qi;
674
endmodule
675
//////////////////////////////////////////////////////////////////////
676
////                                                              ////
677
////  Versatile counter                                           ////
678
////                                                              ////
679
////  Description                                                 ////
680
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
681
////  counter                                                     ////
682
////                                                              ////
683
////  To Do:                                                      ////
684
////   - add LFSR with more taps                                  ////
685
////                                                              ////
686
////  Author(s):                                                  ////
687
////      - Michael Unneback, unneback@opencores.org              ////
688
////        ORSoC AB                                              ////
689
////                                                              ////
690
//////////////////////////////////////////////////////////////////////
691
////                                                              ////
692
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
693
////                                                              ////
694
//// This source file may be used and distributed without         ////
695
//// restriction provided that this copyright statement is not    ////
696
//// removed from the file and that any derivative work contains  ////
697
//// the original copyright notice and the associated disclaimer. ////
698
////                                                              ////
699
//// This source file is free software; you can redistribute it   ////
700
//// and/or modify it under the terms of the GNU Lesser General   ////
701
//// Public License as published by the Free Software Foundation; ////
702
//// either version 2.1 of the License, or (at your option) any   ////
703
//// later version.                                               ////
704
////                                                              ////
705
//// This source is distributed in the hope that it will be       ////
706
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
707
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
708
//// PURPOSE.  See the GNU Lesser General Public License for more ////
709
//// details.                                                     ////
710
////                                                              ////
711
//// You should have received a copy of the GNU Lesser General    ////
712
//// Public License along with this source; if not, download it   ////
713
//// from http://www.opencores.org/lgpl.shtml                     ////
714
////                                                              ////
715
//////////////////////////////////////////////////////////////////////
716
// binary counter
717 18 unneback
module vl_cnt_bin_ce_clear ( clear, cke, q, rst, clk);
718 6 unneback
   parameter length = 4;
719
   input clear;
720
   input cke;
721
   output [length:1] q;
722
   input rst;
723
   input clk;
724
   parameter clear_value = 0;
725
   parameter set_value = 1;
726
   parameter wrap_value = 0;
727
   parameter level1_value = 15;
728
   reg  [length:1] qi;
729
   wire [length:1] q_next;
730
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
731
   always @ (posedge clk or posedge rst)
732
     if (rst)
733
       qi <= {length{1'b0}};
734
     else
735
     if (cke)
736
       qi <= q_next;
737
   assign q = qi;
738
endmodule
739
//////////////////////////////////////////////////////////////////////
740
////                                                              ////
741
////  Versatile counter                                           ////
742
////                                                              ////
743
////  Description                                                 ////
744
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
745
////  counter                                                     ////
746
////                                                              ////
747
////  To Do:                                                      ////
748
////   - add LFSR with more taps                                  ////
749
////                                                              ////
750
////  Author(s):                                                  ////
751
////      - Michael Unneback, unneback@opencores.org              ////
752
////        ORSoC AB                                              ////
753
////                                                              ////
754
//////////////////////////////////////////////////////////////////////
755
////                                                              ////
756
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
757
////                                                              ////
758
//// This source file may be used and distributed without         ////
759
//// restriction provided that this copyright statement is not    ////
760
//// removed from the file and that any derivative work contains  ////
761
//// the original copyright notice and the associated disclaimer. ////
762
////                                                              ////
763
//// This source file is free software; you can redistribute it   ////
764
//// and/or modify it under the terms of the GNU Lesser General   ////
765
//// Public License as published by the Free Software Foundation; ////
766
//// either version 2.1 of the License, or (at your option) any   ////
767
//// later version.                                               ////
768
////                                                              ////
769
//// This source is distributed in the hope that it will be       ////
770
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
771
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
772
//// PURPOSE.  See the GNU Lesser General Public License for more ////
773
//// details.                                                     ////
774
////                                                              ////
775
//// You should have received a copy of the GNU Lesser General    ////
776
//// Public License along with this source; if not, download it   ////
777
//// from http://www.opencores.org/lgpl.shtml                     ////
778
////                                                              ////
779
//////////////////////////////////////////////////////////////////////
780
// binary counter
781 29 unneback
module vl_cnt_bin_ce_clear_l1_l2 ( clear, cke, q, level1, level2, rst, clk);
782
   parameter length = 4;
783
   input clear;
784
   input cke;
785
   output [length:1] q;
786
   output reg level1;
787
   output reg level2;
788
   input rst;
789
   input clk;
790
   parameter clear_value = 0;
791
   parameter set_value = 1;
792 30 unneback
   parameter wrap_value = 15;
793
   parameter level1_value = 8;
794
   parameter level2_value = 15;
795 29 unneback
   wire rew;
796 30 unneback
   assign rew = 1'b0;
797 29 unneback
   reg  [length:1] qi;
798
   wire [length:1] q_next;
799
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
800
   always @ (posedge clk or posedge rst)
801
     if (rst)
802
       qi <= {length{1'b0}};
803
     else
804
     if (cke)
805
       qi <= q_next;
806
   assign q = qi;
807
    always @ (posedge clk or posedge rst)
808
    if (rst)
809
        level1 <= 1'b0;
810
    else
811
    if (cke)
812
    if (clear)
813
        level1 <= 1'b0;
814
    else if (q_next == level1_value)
815
        level1 <= 1'b1;
816
    else if (qi == level1_value & rew)
817
        level1 <= 1'b0;
818
    always @ (posedge clk or posedge rst)
819
    if (rst)
820
        level2 <= 1'b0;
821
    else
822
    if (cke)
823
    if (clear)
824
        level2 <= 1'b0;
825
    else if (q_next == level2_value)
826
        level2 <= 1'b1;
827
    else if (qi == level2_value & rew)
828
        level2 <= 1'b0;
829
endmodule
830
//////////////////////////////////////////////////////////////////////
831
////                                                              ////
832
////  Versatile counter                                           ////
833
////                                                              ////
834
////  Description                                                 ////
835
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
836
////  counter                                                     ////
837
////                                                              ////
838
////  To Do:                                                      ////
839
////   - add LFSR with more taps                                  ////
840
////                                                              ////
841
////  Author(s):                                                  ////
842
////      - Michael Unneback, unneback@opencores.org              ////
843
////        ORSoC AB                                              ////
844
////                                                              ////
845
//////////////////////////////////////////////////////////////////////
846
////                                                              ////
847
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
848
////                                                              ////
849
//// This source file may be used and distributed without         ////
850
//// restriction provided that this copyright statement is not    ////
851
//// removed from the file and that any derivative work contains  ////
852
//// the original copyright notice and the associated disclaimer. ////
853
////                                                              ////
854
//// This source file is free software; you can redistribute it   ////
855
//// and/or modify it under the terms of the GNU Lesser General   ////
856
//// Public License as published by the Free Software Foundation; ////
857
//// either version 2.1 of the License, or (at your option) any   ////
858
//// later version.                                               ////
859
////                                                              ////
860
//// This source is distributed in the hope that it will be       ////
861
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
862
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
863
//// PURPOSE.  See the GNU Lesser General Public License for more ////
864
//// details.                                                     ////
865
////                                                              ////
866
//// You should have received a copy of the GNU Lesser General    ////
867
//// Public License along with this source; if not, download it   ////
868
//// from http://www.opencores.org/lgpl.shtml                     ////
869
////                                                              ////
870
//////////////////////////////////////////////////////////////////////
871
// binary counter
872 18 unneback
module vl_cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk);
873 6 unneback
   parameter length = 4;
874
   input clear;
875
   input set;
876
   input cke;
877
   input rew;
878
   output [length:1] q;
879
   input rst;
880
   input clk;
881
   parameter clear_value = 0;
882
   parameter set_value = 1;
883
   parameter wrap_value = 0;
884
   parameter level1_value = 15;
885
   reg  [length:1] qi;
886
   wire  [length:1] q_next, q_next_fw, q_next_rew;
887
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
888
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
889
   assign q_next = rew ? q_next_rew : q_next_fw;
890
   always @ (posedge clk or posedge rst)
891
     if (rst)
892
       qi <= {length{1'b0}};
893
     else
894
     if (cke)
895
       qi <= q_next;
896
   assign q = qi;
897
endmodule
898
//////////////////////////////////////////////////////////////////////
899
////                                                              ////
900
////  Versatile counter                                           ////
901
////                                                              ////
902
////  Description                                                 ////
903
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
904
////  counter                                                     ////
905
////                                                              ////
906
////  To Do:                                                      ////
907
////   - add LFSR with more taps                                  ////
908
////                                                              ////
909
////  Author(s):                                                  ////
910
////      - Michael Unneback, unneback@opencores.org              ////
911
////        ORSoC AB                                              ////
912
////                                                              ////
913
//////////////////////////////////////////////////////////////////////
914
////                                                              ////
915
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
916
////                                                              ////
917
//// This source file may be used and distributed without         ////
918
//// restriction provided that this copyright statement is not    ////
919
//// removed from the file and that any derivative work contains  ////
920
//// the original copyright notice and the associated disclaimer. ////
921
////                                                              ////
922
//// This source file is free software; you can redistribute it   ////
923
//// and/or modify it under the terms of the GNU Lesser General   ////
924
//// Public License as published by the Free Software Foundation; ////
925
//// either version 2.1 of the License, or (at your option) any   ////
926
//// later version.                                               ////
927
////                                                              ////
928
//// This source is distributed in the hope that it will be       ////
929
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
930
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
931
//// PURPOSE.  See the GNU Lesser General Public License for more ////
932
//// details.                                                     ////
933
////                                                              ////
934
//// You should have received a copy of the GNU Lesser General    ////
935
//// Public License along with this source; if not, download it   ////
936
//// from http://www.opencores.org/lgpl.shtml                     ////
937
////                                                              ////
938
//////////////////////////////////////////////////////////////////////
939
// binary counter
940 18 unneback
module vl_cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk);
941 6 unneback
   parameter length = 4;
942
   input cke;
943
   input rew;
944
   output reg level1;
945
   input rst;
946
   input clk;
947
   parameter clear_value = 0;
948
   parameter set_value = 1;
949
   parameter wrap_value = 1;
950
   parameter level1_value = 15;
951 29 unneback
   wire clear;
952 30 unneback
   assign clear = 1'b0;
953 6 unneback
   reg  [length:1] qi;
954
   wire  [length:1] q_next, q_next_fw, q_next_rew;
955
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
956
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
957
   assign q_next = rew ? q_next_rew : q_next_fw;
958
   always @ (posedge clk or posedge rst)
959
     if (rst)
960
       qi <= {length{1'b0}};
961
     else
962
     if (cke)
963
       qi <= q_next;
964
    always @ (posedge clk or posedge rst)
965
    if (rst)
966
        level1 <= 1'b0;
967
    else
968
    if (cke)
969 29 unneback
    if (clear)
970
        level1 <= 1'b0;
971
    else if (q_next == level1_value)
972 6 unneback
        level1 <= 1'b1;
973
    else if (qi == level1_value & rew)
974
        level1 <= 1'b0;
975
endmodule
976
//////////////////////////////////////////////////////////////////////
977
////                                                              ////
978
////  Versatile counter                                           ////
979
////                                                              ////
980
////  Description                                                 ////
981
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
982
////  counter                                                     ////
983
////                                                              ////
984
////  To Do:                                                      ////
985
////   - add LFSR with more taps                                  ////
986
////                                                              ////
987
////  Author(s):                                                  ////
988
////      - Michael Unneback, unneback@opencores.org              ////
989
////        ORSoC AB                                              ////
990
////                                                              ////
991
//////////////////////////////////////////////////////////////////////
992
////                                                              ////
993
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
994
////                                                              ////
995
//// This source file may be used and distributed without         ////
996
//// restriction provided that this copyright statement is not    ////
997
//// removed from the file and that any derivative work contains  ////
998
//// the original copyright notice and the associated disclaimer. ////
999
////                                                              ////
1000
//// This source file is free software; you can redistribute it   ////
1001
//// and/or modify it under the terms of the GNU Lesser General   ////
1002
//// Public License as published by the Free Software Foundation; ////
1003
//// either version 2.1 of the License, or (at your option) any   ////
1004
//// later version.                                               ////
1005
////                                                              ////
1006
//// This source is distributed in the hope that it will be       ////
1007
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1008
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1009
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1010
//// details.                                                     ////
1011
////                                                              ////
1012
//// You should have received a copy of the GNU Lesser General    ////
1013
//// Public License along with this source; if not, download it   ////
1014
//// from http://www.opencores.org/lgpl.shtml                     ////
1015
////                                                              ////
1016
//////////////////////////////////////////////////////////////////////
1017 25 unneback
// binary counter
1018
module vl_cnt_bin_ce_rew_zq_l1 ( cke, rew, zq, level1, rst, clk);
1019
   parameter length = 4;
1020
   input cke;
1021
   input rew;
1022
   output reg zq;
1023
   output reg level1;
1024
   input rst;
1025
   input clk;
1026
   parameter clear_value = 0;
1027
   parameter set_value = 1;
1028
   parameter wrap_value = 1;
1029
   parameter level1_value = 15;
1030 29 unneback
   wire clear;
1031 30 unneback
   assign clear = 1'b0;
1032 25 unneback
   reg  [length:1] qi;
1033
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1034
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1035
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1036
   assign q_next = rew ? q_next_rew : q_next_fw;
1037
   always @ (posedge clk or posedge rst)
1038
     if (rst)
1039
       qi <= {length{1'b0}};
1040
     else
1041
     if (cke)
1042
       qi <= q_next;
1043
   always @ (posedge clk or posedge rst)
1044
     if (rst)
1045
       zq <= 1'b1;
1046
     else
1047
     if (cke)
1048
       zq <= q_next == {length{1'b0}};
1049
    always @ (posedge clk or posedge rst)
1050
    if (rst)
1051
        level1 <= 1'b0;
1052
    else
1053
    if (cke)
1054 29 unneback
    if (clear)
1055
        level1 <= 1'b0;
1056
    else if (q_next == level1_value)
1057 25 unneback
        level1 <= 1'b1;
1058
    else if (qi == level1_value & rew)
1059
        level1 <= 1'b0;
1060
endmodule
1061
//////////////////////////////////////////////////////////////////////
1062
////                                                              ////
1063
////  Versatile counter                                           ////
1064
////                                                              ////
1065
////  Description                                                 ////
1066
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1067
////  counter                                                     ////
1068
////                                                              ////
1069
////  To Do:                                                      ////
1070
////   - add LFSR with more taps                                  ////
1071
////                                                              ////
1072
////  Author(s):                                                  ////
1073
////      - Michael Unneback, unneback@opencores.org              ////
1074
////        ORSoC AB                                              ////
1075
////                                                              ////
1076
//////////////////////////////////////////////////////////////////////
1077
////                                                              ////
1078
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1079
////                                                              ////
1080
//// This source file may be used and distributed without         ////
1081
//// restriction provided that this copyright statement is not    ////
1082
//// removed from the file and that any derivative work contains  ////
1083
//// the original copyright notice and the associated disclaimer. ////
1084
////                                                              ////
1085
//// This source file is free software; you can redistribute it   ////
1086
//// and/or modify it under the terms of the GNU Lesser General   ////
1087
//// Public License as published by the Free Software Foundation; ////
1088
//// either version 2.1 of the License, or (at your option) any   ////
1089
//// later version.                                               ////
1090
////                                                              ////
1091
//// This source is distributed in the hope that it will be       ////
1092
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1093
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1094
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1095
//// details.                                                     ////
1096
////                                                              ////
1097
//// You should have received a copy of the GNU Lesser General    ////
1098
//// Public License along with this source; if not, download it   ////
1099
//// from http://www.opencores.org/lgpl.shtml                     ////
1100
////                                                              ////
1101
//////////////////////////////////////////////////////////////////////
1102
// binary counter
1103
module vl_cnt_bin_ce_rew_q_zq_l1 ( cke, rew, q, zq, level1, rst, clk);
1104
   parameter length = 4;
1105
   input cke;
1106
   input rew;
1107
   output [length:1] q;
1108
   output reg zq;
1109
   output reg level1;
1110
   input rst;
1111
   input clk;
1112
   parameter clear_value = 0;
1113
   parameter set_value = 1;
1114
   parameter wrap_value = 1;
1115
   parameter level1_value = 15;
1116 29 unneback
   wire clear;
1117 30 unneback
   assign clear = 1'b0;
1118 25 unneback
   reg  [length:1] qi;
1119
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1120
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1121
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1122
   assign q_next = rew ? q_next_rew : q_next_fw;
1123
   always @ (posedge clk or posedge rst)
1124
     if (rst)
1125
       qi <= {length{1'b0}};
1126
     else
1127
     if (cke)
1128
       qi <= q_next;
1129
   assign q = qi;
1130
   always @ (posedge clk or posedge rst)
1131
     if (rst)
1132
       zq <= 1'b1;
1133
     else
1134
     if (cke)
1135
       zq <= q_next == {length{1'b0}};
1136
    always @ (posedge clk or posedge rst)
1137
    if (rst)
1138
        level1 <= 1'b0;
1139
    else
1140
    if (cke)
1141 29 unneback
    if (clear)
1142
        level1 <= 1'b0;
1143
    else if (q_next == level1_value)
1144 25 unneback
        level1 <= 1'b1;
1145
    else if (qi == level1_value & rew)
1146
        level1 <= 1'b0;
1147
endmodule
1148
//////////////////////////////////////////////////////////////////////
1149
////                                                              ////
1150
////  Versatile counter                                           ////
1151
////                                                              ////
1152
////  Description                                                 ////
1153
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1154
////  counter                                                     ////
1155
////                                                              ////
1156
////  To Do:                                                      ////
1157
////   - add LFSR with more taps                                  ////
1158
////                                                              ////
1159
////  Author(s):                                                  ////
1160
////      - Michael Unneback, unneback@opencores.org              ////
1161
////        ORSoC AB                                              ////
1162
////                                                              ////
1163
//////////////////////////////////////////////////////////////////////
1164
////                                                              ////
1165
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1166
////                                                              ////
1167
//// This source file may be used and distributed without         ////
1168
//// restriction provided that this copyright statement is not    ////
1169
//// removed from the file and that any derivative work contains  ////
1170
//// the original copyright notice and the associated disclaimer. ////
1171
////                                                              ////
1172
//// This source file is free software; you can redistribute it   ////
1173
//// and/or modify it under the terms of the GNU Lesser General   ////
1174
//// Public License as published by the Free Software Foundation; ////
1175
//// either version 2.1 of the License, or (at your option) any   ////
1176
//// later version.                                               ////
1177
////                                                              ////
1178
//// This source is distributed in the hope that it will be       ////
1179
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1180
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1181
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1182
//// details.                                                     ////
1183
////                                                              ////
1184
//// You should have received a copy of the GNU Lesser General    ////
1185
//// Public License along with this source; if not, download it   ////
1186
//// from http://www.opencores.org/lgpl.shtml                     ////
1187
////                                                              ////
1188
//////////////////////////////////////////////////////////////////////
1189 6 unneback
// LFSR counter
1190 18 unneback
module vl_cnt_lfsr_zq ( zq, rst, clk);
1191 6 unneback
   parameter length = 4;
1192
   output reg zq;
1193
   input rst;
1194
   input clk;
1195
   parameter clear_value = 0;
1196
   parameter set_value = 1;
1197
   parameter wrap_value = 8;
1198
   parameter level1_value = 15;
1199
   reg  [length:1] qi;
1200
   reg lfsr_fb;
1201
   wire [length:1] q_next;
1202
   reg [32:1] polynom;
1203
   integer i;
1204
   always @ (qi)
1205
   begin
1206
        case (length)
1207
         2: polynom = 32'b11;                               // 0x3
1208
         3: polynom = 32'b110;                              // 0x6
1209
         4: polynom = 32'b1100;                             // 0xC
1210
         5: polynom = 32'b10100;                            // 0x14
1211
         6: polynom = 32'b110000;                           // 0x30
1212
         7: polynom = 32'b1100000;                          // 0x60
1213
         8: polynom = 32'b10111000;                         // 0xb8
1214
         9: polynom = 32'b100010000;                        // 0x110
1215
        10: polynom = 32'b1001000000;                       // 0x240
1216
        11: polynom = 32'b10100000000;                      // 0x500
1217
        12: polynom = 32'b100000101001;                     // 0x829
1218
        13: polynom = 32'b1000000001100;                    // 0x100C
1219
        14: polynom = 32'b10000000010101;                   // 0x2015
1220
        15: polynom = 32'b110000000000000;                  // 0x6000
1221
        16: polynom = 32'b1101000000001000;                 // 0xD008
1222
        17: polynom = 32'b10010000000000000;                // 0x12000
1223
        18: polynom = 32'b100000010000000000;               // 0x20400
1224
        19: polynom = 32'b1000000000000100011;              // 0x40023
1225
        20: polynom = 32'b10000010000000000000;             // 0x82000
1226
        21: polynom = 32'b101000000000000000000;            // 0x140000
1227
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1228
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1229
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1230
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1231
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1232
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1233
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1234
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1235
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1236
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1237
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1238
        default: polynom = 32'b0;
1239
        endcase
1240
        lfsr_fb = qi[length];
1241
        for (i=length-1; i>=1; i=i-1) begin
1242
            if (polynom[i])
1243
                lfsr_fb = lfsr_fb  ~^ qi[i];
1244
        end
1245
    end
1246
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1247
   always @ (posedge clk or posedge rst)
1248
     if (rst)
1249
       qi <= {length{1'b0}};
1250
     else
1251
       qi <= q_next;
1252
   always @ (posedge clk or posedge rst)
1253
     if (rst)
1254
       zq <= 1'b1;
1255
     else
1256
       zq <= q_next == {length{1'b0}};
1257
endmodule
1258
//////////////////////////////////////////////////////////////////////
1259
////                                                              ////
1260
////  Versatile counter                                           ////
1261
////                                                              ////
1262
////  Description                                                 ////
1263
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1264
////  counter                                                     ////
1265
////                                                              ////
1266
////  To Do:                                                      ////
1267
////   - add LFSR with more taps                                  ////
1268
////                                                              ////
1269
////  Author(s):                                                  ////
1270
////      - Michael Unneback, unneback@opencores.org              ////
1271
////        ORSoC AB                                              ////
1272
////                                                              ////
1273
//////////////////////////////////////////////////////////////////////
1274
////                                                              ////
1275
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1276
////                                                              ////
1277
//// This source file may be used and distributed without         ////
1278
//// restriction provided that this copyright statement is not    ////
1279
//// removed from the file and that any derivative work contains  ////
1280
//// the original copyright notice and the associated disclaimer. ////
1281
////                                                              ////
1282
//// This source file is free software; you can redistribute it   ////
1283
//// and/or modify it under the terms of the GNU Lesser General   ////
1284
//// Public License as published by the Free Software Foundation; ////
1285
//// either version 2.1 of the License, or (at your option) any   ////
1286
//// later version.                                               ////
1287
////                                                              ////
1288
//// This source is distributed in the hope that it will be       ////
1289
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1290
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1291
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1292
//// details.                                                     ////
1293
////                                                              ////
1294
//// You should have received a copy of the GNU Lesser General    ////
1295
//// Public License along with this source; if not, download it   ////
1296
//// from http://www.opencores.org/lgpl.shtml                     ////
1297
////                                                              ////
1298
//////////////////////////////////////////////////////////////////////
1299
// LFSR counter
1300 18 unneback
module vl_cnt_lfsr_ce_zq ( cke, zq, rst, clk);
1301 6 unneback
   parameter length = 4;
1302
   input cke;
1303
   output reg zq;
1304
   input rst;
1305
   input clk;
1306
   parameter clear_value = 0;
1307
   parameter set_value = 1;
1308
   parameter wrap_value = 8;
1309
   parameter level1_value = 15;
1310
   reg  [length:1] qi;
1311
   reg lfsr_fb;
1312
   wire [length:1] q_next;
1313
   reg [32:1] polynom;
1314
   integer i;
1315
   always @ (qi)
1316
   begin
1317
        case (length)
1318
         2: polynom = 32'b11;                               // 0x3
1319
         3: polynom = 32'b110;                              // 0x6
1320
         4: polynom = 32'b1100;                             // 0xC
1321
         5: polynom = 32'b10100;                            // 0x14
1322
         6: polynom = 32'b110000;                           // 0x30
1323
         7: polynom = 32'b1100000;                          // 0x60
1324
         8: polynom = 32'b10111000;                         // 0xb8
1325
         9: polynom = 32'b100010000;                        // 0x110
1326
        10: polynom = 32'b1001000000;                       // 0x240
1327
        11: polynom = 32'b10100000000;                      // 0x500
1328
        12: polynom = 32'b100000101001;                     // 0x829
1329
        13: polynom = 32'b1000000001100;                    // 0x100C
1330
        14: polynom = 32'b10000000010101;                   // 0x2015
1331
        15: polynom = 32'b110000000000000;                  // 0x6000
1332
        16: polynom = 32'b1101000000001000;                 // 0xD008
1333
        17: polynom = 32'b10010000000000000;                // 0x12000
1334
        18: polynom = 32'b100000010000000000;               // 0x20400
1335
        19: polynom = 32'b1000000000000100011;              // 0x40023
1336
        20: polynom = 32'b10000010000000000000;             // 0x82000
1337
        21: polynom = 32'b101000000000000000000;            // 0x140000
1338
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1339
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1340
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1341
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1342
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1343
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1344
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1345
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1346
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1347
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1348
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1349
        default: polynom = 32'b0;
1350
        endcase
1351
        lfsr_fb = qi[length];
1352
        for (i=length-1; i>=1; i=i-1) begin
1353
            if (polynom[i])
1354
                lfsr_fb = lfsr_fb  ~^ qi[i];
1355
        end
1356
    end
1357
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1358
   always @ (posedge clk or posedge rst)
1359
     if (rst)
1360
       qi <= {length{1'b0}};
1361
     else
1362
     if (cke)
1363
       qi <= q_next;
1364
   always @ (posedge clk or posedge rst)
1365
     if (rst)
1366
       zq <= 1'b1;
1367
     else
1368
     if (cke)
1369
       zq <= q_next == {length{1'b0}};
1370
endmodule
1371
//////////////////////////////////////////////////////////////////////
1372
////                                                              ////
1373
////  Versatile counter                                           ////
1374
////                                                              ////
1375
////  Description                                                 ////
1376
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1377
////  counter                                                     ////
1378
////                                                              ////
1379
////  To Do:                                                      ////
1380
////   - add LFSR with more taps                                  ////
1381
////                                                              ////
1382
////  Author(s):                                                  ////
1383
////      - Michael Unneback, unneback@opencores.org              ////
1384
////        ORSoC AB                                              ////
1385
////                                                              ////
1386
//////////////////////////////////////////////////////////////////////
1387
////                                                              ////
1388
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1389
////                                                              ////
1390
//// This source file may be used and distributed without         ////
1391
//// restriction provided that this copyright statement is not    ////
1392
//// removed from the file and that any derivative work contains  ////
1393
//// the original copyright notice and the associated disclaimer. ////
1394
////                                                              ////
1395
//// This source file is free software; you can redistribute it   ////
1396
//// and/or modify it under the terms of the GNU Lesser General   ////
1397
//// Public License as published by the Free Software Foundation; ////
1398
//// either version 2.1 of the License, or (at your option) any   ////
1399
//// later version.                                               ////
1400
////                                                              ////
1401
//// This source is distributed in the hope that it will be       ////
1402
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1403
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1404
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1405
//// details.                                                     ////
1406
////                                                              ////
1407
//// You should have received a copy of the GNU Lesser General    ////
1408
//// Public License along with this source; if not, download it   ////
1409
//// from http://www.opencores.org/lgpl.shtml                     ////
1410
////                                                              ////
1411
//////////////////////////////////////////////////////////////////////
1412
// LFSR counter
1413 27 unneback
module vl_cnt_lfsr_ce_q ( cke, q, rst, clk);
1414
   parameter length = 4;
1415
   input cke;
1416
   output [length:1] q;
1417
   input rst;
1418
   input clk;
1419
   parameter clear_value = 0;
1420
   parameter set_value = 1;
1421
   parameter wrap_value = 8;
1422
   parameter level1_value = 15;
1423
   reg  [length:1] qi;
1424
   reg lfsr_fb;
1425
   wire [length:1] q_next;
1426
   reg [32:1] polynom;
1427
   integer i;
1428
   always @ (qi)
1429
   begin
1430
        case (length)
1431
         2: polynom = 32'b11;                               // 0x3
1432
         3: polynom = 32'b110;                              // 0x6
1433
         4: polynom = 32'b1100;                             // 0xC
1434
         5: polynom = 32'b10100;                            // 0x14
1435
         6: polynom = 32'b110000;                           // 0x30
1436
         7: polynom = 32'b1100000;                          // 0x60
1437
         8: polynom = 32'b10111000;                         // 0xb8
1438
         9: polynom = 32'b100010000;                        // 0x110
1439
        10: polynom = 32'b1001000000;                       // 0x240
1440
        11: polynom = 32'b10100000000;                      // 0x500
1441
        12: polynom = 32'b100000101001;                     // 0x829
1442
        13: polynom = 32'b1000000001100;                    // 0x100C
1443
        14: polynom = 32'b10000000010101;                   // 0x2015
1444
        15: polynom = 32'b110000000000000;                  // 0x6000
1445
        16: polynom = 32'b1101000000001000;                 // 0xD008
1446
        17: polynom = 32'b10010000000000000;                // 0x12000
1447
        18: polynom = 32'b100000010000000000;               // 0x20400
1448
        19: polynom = 32'b1000000000000100011;              // 0x40023
1449
        20: polynom = 32'b10000010000000000000;             // 0x82000
1450
        21: polynom = 32'b101000000000000000000;            // 0x140000
1451
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1452
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1453
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1454
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1455
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1456
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1457
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1458
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1459
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1460
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1461
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1462
        default: polynom = 32'b0;
1463
        endcase
1464
        lfsr_fb = qi[length];
1465
        for (i=length-1; i>=1; i=i-1) begin
1466
            if (polynom[i])
1467
                lfsr_fb = lfsr_fb  ~^ qi[i];
1468
        end
1469
    end
1470
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1471
   always @ (posedge clk or posedge rst)
1472
     if (rst)
1473
       qi <= {length{1'b0}};
1474
     else
1475
     if (cke)
1476
       qi <= q_next;
1477
   assign q = qi;
1478
endmodule
1479
//////////////////////////////////////////////////////////////////////
1480
////                                                              ////
1481
////  Versatile counter                                           ////
1482
////                                                              ////
1483
////  Description                                                 ////
1484
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1485
////  counter                                                     ////
1486
////                                                              ////
1487
////  To Do:                                                      ////
1488
////   - add LFSR with more taps                                  ////
1489
////                                                              ////
1490
////  Author(s):                                                  ////
1491
////      - Michael Unneback, unneback@opencores.org              ////
1492
////        ORSoC AB                                              ////
1493
////                                                              ////
1494
//////////////////////////////////////////////////////////////////////
1495
////                                                              ////
1496
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1497
////                                                              ////
1498
//// This source file may be used and distributed without         ////
1499
//// restriction provided that this copyright statement is not    ////
1500
//// removed from the file and that any derivative work contains  ////
1501
//// the original copyright notice and the associated disclaimer. ////
1502
////                                                              ////
1503
//// This source file is free software; you can redistribute it   ////
1504
//// and/or modify it under the terms of the GNU Lesser General   ////
1505
//// Public License as published by the Free Software Foundation; ////
1506
//// either version 2.1 of the License, or (at your option) any   ////
1507
//// later version.                                               ////
1508
////                                                              ////
1509
//// This source is distributed in the hope that it will be       ////
1510
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1511
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1512
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1513
//// details.                                                     ////
1514
////                                                              ////
1515
//// You should have received a copy of the GNU Lesser General    ////
1516
//// Public License along with this source; if not, download it   ////
1517
//// from http://www.opencores.org/lgpl.shtml                     ////
1518
////                                                              ////
1519
//////////////////////////////////////////////////////////////////////
1520
// LFSR counter
1521
module vl_cnt_lfsr_ce_clear_q ( clear, cke, q, rst, clk);
1522
   parameter length = 4;
1523
   input clear;
1524
   input cke;
1525
   output [length:1] q;
1526
   input rst;
1527
   input clk;
1528
   parameter clear_value = 0;
1529
   parameter set_value = 1;
1530
   parameter wrap_value = 8;
1531
   parameter level1_value = 15;
1532
   reg  [length:1] qi;
1533
   reg lfsr_fb;
1534
   wire [length:1] q_next;
1535
   reg [32:1] polynom;
1536
   integer i;
1537
   always @ (qi)
1538
   begin
1539
        case (length)
1540
         2: polynom = 32'b11;                               // 0x3
1541
         3: polynom = 32'b110;                              // 0x6
1542
         4: polynom = 32'b1100;                             // 0xC
1543
         5: polynom = 32'b10100;                            // 0x14
1544
         6: polynom = 32'b110000;                           // 0x30
1545
         7: polynom = 32'b1100000;                          // 0x60
1546
         8: polynom = 32'b10111000;                         // 0xb8
1547
         9: polynom = 32'b100010000;                        // 0x110
1548
        10: polynom = 32'b1001000000;                       // 0x240
1549
        11: polynom = 32'b10100000000;                      // 0x500
1550
        12: polynom = 32'b100000101001;                     // 0x829
1551
        13: polynom = 32'b1000000001100;                    // 0x100C
1552
        14: polynom = 32'b10000000010101;                   // 0x2015
1553
        15: polynom = 32'b110000000000000;                  // 0x6000
1554
        16: polynom = 32'b1101000000001000;                 // 0xD008
1555
        17: polynom = 32'b10010000000000000;                // 0x12000
1556
        18: polynom = 32'b100000010000000000;               // 0x20400
1557
        19: polynom = 32'b1000000000000100011;              // 0x40023
1558
        20: polynom = 32'b10000010000000000000;             // 0x82000
1559
        21: polynom = 32'b101000000000000000000;            // 0x140000
1560
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1561
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1562
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1563
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1564
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1565
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1566
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1567
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1568
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1569
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1570
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1571
        default: polynom = 32'b0;
1572
        endcase
1573
        lfsr_fb = qi[length];
1574
        for (i=length-1; i>=1; i=i-1) begin
1575
            if (polynom[i])
1576
                lfsr_fb = lfsr_fb  ~^ qi[i];
1577
        end
1578
    end
1579
   assign q_next =  clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1580
   always @ (posedge clk or posedge rst)
1581
     if (rst)
1582
       qi <= {length{1'b0}};
1583
     else
1584
     if (cke)
1585
       qi <= q_next;
1586
   assign q = qi;
1587
endmodule
1588
//////////////////////////////////////////////////////////////////////
1589
////                                                              ////
1590
////  Versatile counter                                           ////
1591
////                                                              ////
1592
////  Description                                                 ////
1593
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1594
////  counter                                                     ////
1595
////                                                              ////
1596
////  To Do:                                                      ////
1597
////   - add LFSR with more taps                                  ////
1598
////                                                              ////
1599
////  Author(s):                                                  ////
1600
////      - Michael Unneback, unneback@opencores.org              ////
1601
////        ORSoC AB                                              ////
1602
////                                                              ////
1603
//////////////////////////////////////////////////////////////////////
1604
////                                                              ////
1605
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1606
////                                                              ////
1607
//// This source file may be used and distributed without         ////
1608
//// restriction provided that this copyright statement is not    ////
1609
//// removed from the file and that any derivative work contains  ////
1610
//// the original copyright notice and the associated disclaimer. ////
1611
////                                                              ////
1612
//// This source file is free software; you can redistribute it   ////
1613
//// and/or modify it under the terms of the GNU Lesser General   ////
1614
//// Public License as published by the Free Software Foundation; ////
1615
//// either version 2.1 of the License, or (at your option) any   ////
1616
//// later version.                                               ////
1617
////                                                              ////
1618
//// This source is distributed in the hope that it will be       ////
1619
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1620
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1621
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1622
//// details.                                                     ////
1623
////                                                              ////
1624
//// You should have received a copy of the GNU Lesser General    ////
1625
//// Public License along with this source; if not, download it   ////
1626
//// from http://www.opencores.org/lgpl.shtml                     ////
1627
////                                                              ////
1628
//////////////////////////////////////////////////////////////////////
1629
// LFSR counter
1630 22 unneback
module vl_cnt_lfsr_ce_q_zq ( cke, q, zq, rst, clk);
1631
   parameter length = 4;
1632
   input cke;
1633
   output [length:1] q;
1634
   output reg zq;
1635
   input rst;
1636
   input clk;
1637
   parameter clear_value = 0;
1638
   parameter set_value = 1;
1639
   parameter wrap_value = 8;
1640
   parameter level1_value = 15;
1641
   reg  [length:1] qi;
1642
   reg lfsr_fb;
1643
   wire [length:1] q_next;
1644
   reg [32:1] polynom;
1645
   integer i;
1646
   always @ (qi)
1647
   begin
1648
        case (length)
1649
         2: polynom = 32'b11;                               // 0x3
1650
         3: polynom = 32'b110;                              // 0x6
1651
         4: polynom = 32'b1100;                             // 0xC
1652
         5: polynom = 32'b10100;                            // 0x14
1653
         6: polynom = 32'b110000;                           // 0x30
1654
         7: polynom = 32'b1100000;                          // 0x60
1655
         8: polynom = 32'b10111000;                         // 0xb8
1656
         9: polynom = 32'b100010000;                        // 0x110
1657
        10: polynom = 32'b1001000000;                       // 0x240
1658
        11: polynom = 32'b10100000000;                      // 0x500
1659
        12: polynom = 32'b100000101001;                     // 0x829
1660
        13: polynom = 32'b1000000001100;                    // 0x100C
1661
        14: polynom = 32'b10000000010101;                   // 0x2015
1662
        15: polynom = 32'b110000000000000;                  // 0x6000
1663
        16: polynom = 32'b1101000000001000;                 // 0xD008
1664
        17: polynom = 32'b10010000000000000;                // 0x12000
1665
        18: polynom = 32'b100000010000000000;               // 0x20400
1666
        19: polynom = 32'b1000000000000100011;              // 0x40023
1667
        20: polynom = 32'b10000010000000000000;             // 0x82000
1668
        21: polynom = 32'b101000000000000000000;            // 0x140000
1669
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1670
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1671
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1672
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1673
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1674
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1675
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1676
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1677
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1678
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1679
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1680
        default: polynom = 32'b0;
1681
        endcase
1682
        lfsr_fb = qi[length];
1683
        for (i=length-1; i>=1; i=i-1) begin
1684
            if (polynom[i])
1685
                lfsr_fb = lfsr_fb  ~^ qi[i];
1686
        end
1687
    end
1688
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1689
   always @ (posedge clk or posedge rst)
1690
     if (rst)
1691
       qi <= {length{1'b0}};
1692
     else
1693
     if (cke)
1694
       qi <= q_next;
1695
   assign q = qi;
1696
   always @ (posedge clk or posedge rst)
1697
     if (rst)
1698
       zq <= 1'b1;
1699
     else
1700
     if (cke)
1701
       zq <= q_next == {length{1'b0}};
1702
endmodule
1703
//////////////////////////////////////////////////////////////////////
1704
////                                                              ////
1705
////  Versatile counter                                           ////
1706
////                                                              ////
1707
////  Description                                                 ////
1708
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1709
////  counter                                                     ////
1710
////                                                              ////
1711
////  To Do:                                                      ////
1712
////   - add LFSR with more taps                                  ////
1713
////                                                              ////
1714
////  Author(s):                                                  ////
1715
////      - Michael Unneback, unneback@opencores.org              ////
1716
////        ORSoC AB                                              ////
1717
////                                                              ////
1718
//////////////////////////////////////////////////////////////////////
1719
////                                                              ////
1720
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1721
////                                                              ////
1722
//// This source file may be used and distributed without         ////
1723
//// restriction provided that this copyright statement is not    ////
1724
//// removed from the file and that any derivative work contains  ////
1725
//// the original copyright notice and the associated disclaimer. ////
1726
////                                                              ////
1727
//// This source file is free software; you can redistribute it   ////
1728
//// and/or modify it under the terms of the GNU Lesser General   ////
1729
//// Public License as published by the Free Software Foundation; ////
1730
//// either version 2.1 of the License, or (at your option) any   ////
1731
//// later version.                                               ////
1732
////                                                              ////
1733
//// This source is distributed in the hope that it will be       ////
1734
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1735
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1736
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1737
//// details.                                                     ////
1738
////                                                              ////
1739
//// You should have received a copy of the GNU Lesser General    ////
1740
//// Public License along with this source; if not, download it   ////
1741
//// from http://www.opencores.org/lgpl.shtml                     ////
1742
////                                                              ////
1743
//////////////////////////////////////////////////////////////////////
1744
// LFSR counter
1745 18 unneback
module vl_cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk);
1746 6 unneback
   parameter length = 4;
1747
   input cke;
1748
   input rew;
1749
   output reg level1;
1750
   input rst;
1751
   input clk;
1752
   parameter clear_value = 0;
1753
   parameter set_value = 1;
1754
   parameter wrap_value = 8;
1755
   parameter level1_value = 15;
1756 29 unneback
   wire clear;
1757 30 unneback
   assign clear = 1'b0;
1758 6 unneback
   reg  [length:1] qi;
1759
   reg lfsr_fb, lfsr_fb_rew;
1760
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1761
   reg [32:1] polynom_rew;
1762
   integer j;
1763
   reg [32:1] polynom;
1764
   integer i;
1765
   always @ (qi)
1766
   begin
1767
        case (length)
1768
         2: polynom = 32'b11;                               // 0x3
1769
         3: polynom = 32'b110;                              // 0x6
1770
         4: polynom = 32'b1100;                             // 0xC
1771
         5: polynom = 32'b10100;                            // 0x14
1772
         6: polynom = 32'b110000;                           // 0x30
1773
         7: polynom = 32'b1100000;                          // 0x60
1774
         8: polynom = 32'b10111000;                         // 0xb8
1775
         9: polynom = 32'b100010000;                        // 0x110
1776
        10: polynom = 32'b1001000000;                       // 0x240
1777
        11: polynom = 32'b10100000000;                      // 0x500
1778
        12: polynom = 32'b100000101001;                     // 0x829
1779
        13: polynom = 32'b1000000001100;                    // 0x100C
1780
        14: polynom = 32'b10000000010101;                   // 0x2015
1781
        15: polynom = 32'b110000000000000;                  // 0x6000
1782
        16: polynom = 32'b1101000000001000;                 // 0xD008
1783
        17: polynom = 32'b10010000000000000;                // 0x12000
1784
        18: polynom = 32'b100000010000000000;               // 0x20400
1785
        19: polynom = 32'b1000000000000100011;              // 0x40023
1786
        20: polynom = 32'b10000010000000000000;             // 0x82000
1787
        21: polynom = 32'b101000000000000000000;            // 0x140000
1788
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1789
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1790
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1791
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1792
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1793
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1794
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1795
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1796
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1797
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1798
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1799
        default: polynom = 32'b0;
1800
        endcase
1801
        lfsr_fb = qi[length];
1802
        for (i=length-1; i>=1; i=i-1) begin
1803
            if (polynom[i])
1804
                lfsr_fb = lfsr_fb  ~^ qi[i];
1805
        end
1806
    end
1807
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1808
   always @ (qi)
1809
   begin
1810
        case (length)
1811
         2: polynom_rew = 32'b11;
1812
         3: polynom_rew = 32'b110;
1813
         4: polynom_rew = 32'b1100;
1814
         5: polynom_rew = 32'b10100;
1815
         6: polynom_rew = 32'b110000;
1816
         7: polynom_rew = 32'b1100000;
1817
         8: polynom_rew = 32'b10111000;
1818
         9: polynom_rew = 32'b100010000;
1819
        10: polynom_rew = 32'b1001000000;
1820
        11: polynom_rew = 32'b10100000000;
1821
        12: polynom_rew = 32'b100000101001;
1822
        13: polynom_rew = 32'b1000000001100;
1823
        14: polynom_rew = 32'b10000000010101;
1824
        15: polynom_rew = 32'b110000000000000;
1825
        16: polynom_rew = 32'b1101000000001000;
1826
        17: polynom_rew = 32'b10010000000000000;
1827
        18: polynom_rew = 32'b100000010000000000;
1828
        19: polynom_rew = 32'b1000000000000100011;
1829
        20: polynom_rew = 32'b10000010000000000000;
1830
        21: polynom_rew = 32'b101000000000000000000;
1831
        22: polynom_rew = 32'b1100000000000000000000;
1832
        23: polynom_rew = 32'b10000100000000000000000;
1833
        24: polynom_rew = 32'b111000010000000000000000;
1834
        25: polynom_rew = 32'b1001000000000000000000000;
1835
        26: polynom_rew = 32'b10000000000000000000100011;
1836
        27: polynom_rew = 32'b100000000000000000000010011;
1837
        28: polynom_rew = 32'b1100100000000000000000000000;
1838
        29: polynom_rew = 32'b10100000000000000000000000000;
1839
        30: polynom_rew = 32'b100000000000000000000000101001;
1840
        31: polynom_rew = 32'b1001000000000000000000000000000;
1841
        32: polynom_rew = 32'b10000000001000000000000000000011;
1842
        default: polynom_rew = 32'b0;
1843
        endcase
1844
        // rotate left
1845
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
1846
        lfsr_fb_rew = qi[length];
1847
        for (i=length-1; i>=1; i=i-1) begin
1848
            if (polynom_rew[i])
1849
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
1850
        end
1851
    end
1852
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
1853
   assign q_next = rew ? q_next_rew : q_next_fw;
1854
   always @ (posedge clk or posedge rst)
1855
     if (rst)
1856
       qi <= {length{1'b0}};
1857
     else
1858
     if (cke)
1859
       qi <= q_next;
1860
    always @ (posedge clk or posedge rst)
1861
    if (rst)
1862
        level1 <= 1'b0;
1863
    else
1864
    if (cke)
1865 29 unneback
    if (clear)
1866
        level1 <= 1'b0;
1867
    else if (q_next == level1_value)
1868 6 unneback
        level1 <= 1'b1;
1869
    else if (qi == level1_value & rew)
1870
        level1 <= 1'b0;
1871
endmodule
1872
//////////////////////////////////////////////////////////////////////
1873
////                                                              ////
1874
////  Versatile counter                                           ////
1875
////                                                              ////
1876
////  Description                                                 ////
1877
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1878
////  counter                                                     ////
1879
////                                                              ////
1880
////  To Do:                                                      ////
1881
////   - add LFSR with more taps                                  ////
1882
////                                                              ////
1883
////  Author(s):                                                  ////
1884
////      - Michael Unneback, unneback@opencores.org              ////
1885
////        ORSoC AB                                              ////
1886
////                                                              ////
1887
//////////////////////////////////////////////////////////////////////
1888
////                                                              ////
1889
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1890
////                                                              ////
1891
//// This source file may be used and distributed without         ////
1892
//// restriction provided that this copyright statement is not    ////
1893
//// removed from the file and that any derivative work contains  ////
1894
//// the original copyright notice and the associated disclaimer. ////
1895
////                                                              ////
1896
//// This source file is free software; you can redistribute it   ////
1897
//// and/or modify it under the terms of the GNU Lesser General   ////
1898
//// Public License as published by the Free Software Foundation; ////
1899
//// either version 2.1 of the License, or (at your option) any   ////
1900
//// later version.                                               ////
1901
////                                                              ////
1902
//// This source is distributed in the hope that it will be       ////
1903
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1904
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1905
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1906
//// details.                                                     ////
1907
////                                                              ////
1908
//// You should have received a copy of the GNU Lesser General    ////
1909
//// Public License along with this source; if not, download it   ////
1910
//// from http://www.opencores.org/lgpl.shtml                     ////
1911
////                                                              ////
1912
//////////////////////////////////////////////////////////////////////
1913
// GRAY counter
1914 18 unneback
module vl_cnt_gray ( q, rst, clk);
1915 6 unneback
   parameter length = 4;
1916
   output reg [length:1] q;
1917
   input rst;
1918
   input clk;
1919
   parameter clear_value = 0;
1920
   parameter set_value = 1;
1921
   parameter wrap_value = 8;
1922
   parameter level1_value = 15;
1923
   reg  [length:1] qi;
1924
   wire [length:1] q_next;
1925
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1926
   always @ (posedge clk or posedge rst)
1927
     if (rst)
1928
       qi <= {length{1'b0}};
1929
     else
1930
       qi <= q_next;
1931
   always @ (posedge clk or posedge rst)
1932
     if (rst)
1933
       q <= {length{1'b0}};
1934
     else
1935
         q <= (q_next>>1) ^ q_next;
1936
endmodule
1937
//////////////////////////////////////////////////////////////////////
1938
////                                                              ////
1939
////  Versatile counter                                           ////
1940
////                                                              ////
1941
////  Description                                                 ////
1942
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1943
////  counter                                                     ////
1944
////                                                              ////
1945
////  To Do:                                                      ////
1946
////   - add LFSR with more taps                                  ////
1947
////                                                              ////
1948
////  Author(s):                                                  ////
1949
////      - Michael Unneback, unneback@opencores.org              ////
1950
////        ORSoC AB                                              ////
1951
////                                                              ////
1952
//////////////////////////////////////////////////////////////////////
1953
////                                                              ////
1954
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1955
////                                                              ////
1956
//// This source file may be used and distributed without         ////
1957
//// restriction provided that this copyright statement is not    ////
1958
//// removed from the file and that any derivative work contains  ////
1959
//// the original copyright notice and the associated disclaimer. ////
1960
////                                                              ////
1961
//// This source file is free software; you can redistribute it   ////
1962
//// and/or modify it under the terms of the GNU Lesser General   ////
1963
//// Public License as published by the Free Software Foundation; ////
1964
//// either version 2.1 of the License, or (at your option) any   ////
1965
//// later version.                                               ////
1966
////                                                              ////
1967
//// This source is distributed in the hope that it will be       ////
1968
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1969
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1970
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1971
//// details.                                                     ////
1972
////                                                              ////
1973
//// You should have received a copy of the GNU Lesser General    ////
1974
//// Public License along with this source; if not, download it   ////
1975
//// from http://www.opencores.org/lgpl.shtml                     ////
1976
////                                                              ////
1977
//////////////////////////////////////////////////////////////////////
1978
// GRAY counter
1979 18 unneback
module vl_cnt_gray_ce ( cke, q, rst, clk);
1980 6 unneback
   parameter length = 4;
1981
   input cke;
1982
   output reg [length:1] q;
1983
   input rst;
1984
   input clk;
1985
   parameter clear_value = 0;
1986
   parameter set_value = 1;
1987
   parameter wrap_value = 8;
1988
   parameter level1_value = 15;
1989
   reg  [length:1] qi;
1990
   wire [length:1] q_next;
1991
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1992
   always @ (posedge clk or posedge rst)
1993
     if (rst)
1994
       qi <= {length{1'b0}};
1995
     else
1996
     if (cke)
1997
       qi <= q_next;
1998
   always @ (posedge clk or posedge rst)
1999
     if (rst)
2000
       q <= {length{1'b0}};
2001
     else
2002
       if (cke)
2003
         q <= (q_next>>1) ^ q_next;
2004
endmodule
2005
//////////////////////////////////////////////////////////////////////
2006
////                                                              ////
2007
////  Versatile counter                                           ////
2008
////                                                              ////
2009
////  Description                                                 ////
2010
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2011
////  counter                                                     ////
2012
////                                                              ////
2013
////  To Do:                                                      ////
2014
////   - add LFSR with more taps                                  ////
2015
////                                                              ////
2016
////  Author(s):                                                  ////
2017
////      - Michael Unneback, unneback@opencores.org              ////
2018
////        ORSoC AB                                              ////
2019
////                                                              ////
2020
//////////////////////////////////////////////////////////////////////
2021
////                                                              ////
2022
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2023
////                                                              ////
2024
//// This source file may be used and distributed without         ////
2025
//// restriction provided that this copyright statement is not    ////
2026
//// removed from the file and that any derivative work contains  ////
2027
//// the original copyright notice and the associated disclaimer. ////
2028
////                                                              ////
2029
//// This source file is free software; you can redistribute it   ////
2030
//// and/or modify it under the terms of the GNU Lesser General   ////
2031
//// Public License as published by the Free Software Foundation; ////
2032
//// either version 2.1 of the License, or (at your option) any   ////
2033
//// later version.                                               ////
2034
////                                                              ////
2035
//// This source is distributed in the hope that it will be       ////
2036
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2037
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2038
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2039
//// details.                                                     ////
2040
////                                                              ////
2041
//// You should have received a copy of the GNU Lesser General    ////
2042
//// Public License along with this source; if not, download it   ////
2043
//// from http://www.opencores.org/lgpl.shtml                     ////
2044
////                                                              ////
2045
//////////////////////////////////////////////////////////////////////
2046
// GRAY counter
2047 18 unneback
module vl_cnt_gray_ce_bin ( cke, q, q_bin, rst, clk);
2048 6 unneback
   parameter length = 4;
2049
   input cke;
2050
   output reg [length:1] q;
2051
   output [length:1] q_bin;
2052
   input rst;
2053
   input clk;
2054
   parameter clear_value = 0;
2055
   parameter set_value = 1;
2056
   parameter wrap_value = 8;
2057
   parameter level1_value = 15;
2058
   reg  [length:1] qi;
2059
   wire [length:1] q_next;
2060
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2061
   always @ (posedge clk or posedge rst)
2062
     if (rst)
2063
       qi <= {length{1'b0}};
2064
     else
2065
     if (cke)
2066
       qi <= q_next;
2067
   always @ (posedge clk or posedge rst)
2068
     if (rst)
2069
       q <= {length{1'b0}};
2070
     else
2071
       if (cke)
2072
         q <= (q_next>>1) ^ q_next;
2073
   assign q_bin = qi;
2074
endmodule
2075
//////////////////////////////////////////////////////////////////////
2076
////                                                              ////
2077
////  Versatile library, counters                                 ////
2078
////                                                              ////
2079
////  Description                                                 ////
2080
////  counters                                                    ////
2081
////                                                              ////
2082
////                                                              ////
2083
////  To Do:                                                      ////
2084
////   - add more counters                                        ////
2085
////                                                              ////
2086
////  Author(s):                                                  ////
2087
////      - Michael Unneback, unneback@opencores.org              ////
2088
////        ORSoC AB                                              ////
2089
////                                                              ////
2090
//////////////////////////////////////////////////////////////////////
2091
////                                                              ////
2092
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2093
////                                                              ////
2094
//// This source file may be used and distributed without         ////
2095
//// restriction provided that this copyright statement is not    ////
2096
//// removed from the file and that any derivative work contains  ////
2097
//// the original copyright notice and the associated disclaimer. ////
2098
////                                                              ////
2099
//// This source file is free software; you can redistribute it   ////
2100
//// and/or modify it under the terms of the GNU Lesser General   ////
2101
//// Public License as published by the Free Software Foundation; ////
2102
//// either version 2.1 of the License, or (at your option) any   ////
2103
//// later version.                                               ////
2104
////                                                              ////
2105
//// This source is distributed in the hope that it will be       ////
2106
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2107
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2108
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2109
//// details.                                                     ////
2110
////                                                              ////
2111
//// You should have received a copy of the GNU Lesser General    ////
2112
//// Public License along with this source; if not, download it   ////
2113
//// from http://www.opencores.org/lgpl.shtml                     ////
2114
////                                                              ////
2115
//////////////////////////////////////////////////////////////////////
2116 18 unneback
module vl_cnt_shreg_wrap ( q, rst, clk);
2117 6 unneback
   parameter length = 4;
2118
   output reg [0:length-1] q;
2119
   input rst;
2120
   input clk;
2121
    always @ (posedge clk or posedge rst)
2122
    if (rst)
2123
        q <= {1'b1,{length-1{1'b0}}};
2124
    else
2125
        q <= {q[length-1],q[0:length-2]};
2126
endmodule
2127 18 unneback
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
2128 6 unneback
   parameter length = 4;
2129
   input cke;
2130
   output reg [0:length-1] q;
2131
   input rst;
2132
   input clk;
2133
    always @ (posedge clk or posedge rst)
2134
    if (rst)
2135
        q <= {1'b1,{length-1{1'b0}}};
2136
    else
2137
        if (cke)
2138
            q <= {q[length-1],q[0:length-2]};
2139
endmodule
2140 18 unneback
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
2141 6 unneback
   parameter length = 4;
2142
   input cke, clear;
2143
   output reg [0:length-1] q;
2144
   input rst;
2145
   input clk;
2146
    always @ (posedge clk or posedge rst)
2147
    if (rst)
2148
        q <= {1'b1,{length-1{1'b0}}};
2149
    else
2150
        if (cke)
2151
            if (clear)
2152
                q <= {1'b1,{length-1{1'b0}}};
2153
            else
2154
                q <= q >> 1;
2155
endmodule
2156 18 unneback
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
2157 6 unneback
   parameter length = 4;
2158
   input cke, clear;
2159
   output reg [0:length-1] q;
2160
   input rst;
2161
   input clk;
2162
    always @ (posedge clk or posedge rst)
2163
    if (rst)
2164
        q <= {1'b1,{length-1{1'b0}}};
2165
    else
2166
        if (cke)
2167
            if (clear)
2168
                q <= {1'b1,{length-1{1'b0}}};
2169
            else
2170
            q <= {q[length-1],q[0:length-2]};
2171
endmodule
2172
//////////////////////////////////////////////////////////////////////
2173
////                                                              ////
2174
////  Versatile library, memories                                 ////
2175
////                                                              ////
2176
////  Description                                                 ////
2177
////  memories                                                    ////
2178
////                                                              ////
2179
////                                                              ////
2180
////  To Do:                                                      ////
2181
////   - add more memory types                                    ////
2182
////                                                              ////
2183
////  Author(s):                                                  ////
2184
////      - Michael Unneback, unneback@opencores.org              ////
2185
////        ORSoC AB                                              ////
2186
////                                                              ////
2187
//////////////////////////////////////////////////////////////////////
2188
////                                                              ////
2189
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2190
////                                                              ////
2191
//// This source file may be used and distributed without         ////
2192
//// restriction provided that this copyright statement is not    ////
2193
//// removed from the file and that any derivative work contains  ////
2194
//// the original copyright notice and the associated disclaimer. ////
2195
////                                                              ////
2196
//// This source file is free software; you can redistribute it   ////
2197
//// and/or modify it under the terms of the GNU Lesser General   ////
2198
//// Public License as published by the Free Software Foundation; ////
2199
//// either version 2.1 of the License, or (at your option) any   ////
2200
//// later version.                                               ////
2201
////                                                              ////
2202
//// This source is distributed in the hope that it will be       ////
2203
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2204
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2205
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2206
//// details.                                                     ////
2207
////                                                              ////
2208
//// You should have received a copy of the GNU Lesser General    ////
2209
//// Public License along with this source; if not, download it   ////
2210
//// from http://www.opencores.org/lgpl.shtml                     ////
2211
////                                                              ////
2212
//////////////////////////////////////////////////////////////////////
2213
/// ROM
2214 7 unneback
module vl_rom_init ( adr, q, clk);
2215
   parameter data_width = 32;
2216
   parameter addr_width = 8;
2217
   input [(addr_width-1):0]       adr;
2218
   output reg [(data_width-1):0] q;
2219
   input                         clk;
2220
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
2221
   parameter memory_file = "vl_rom.vmem";
2222
   initial
2223
     begin
2224
        $readmemh(memory_file, rom);
2225
     end
2226
   always @ (posedge clk)
2227
     q <= rom[adr];
2228
endmodule
2229 14 unneback
/*
2230 7 unneback
module vl_rom ( adr, q, clk);
2231 6 unneback
parameter data_width = 32;
2232
parameter addr_width = 4;
2233
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
2234
    {32'h18000000},
2235
    {32'hA8200000},
2236
    {32'hA8200000},
2237
    {32'hA8200000},
2238
    {32'h44003000},
2239
    {32'h15000000},
2240
    {32'h15000000},
2241
    {32'h15000000},
2242
    {32'h15000000},
2243
    {32'h15000000},
2244
    {32'h15000000},
2245
    {32'h15000000},
2246
    {32'h15000000},
2247
    {32'h15000000},
2248
    {32'h15000000},
2249
    {32'h15000000}};
2250 7 unneback
input [addr_width-1:0] adr;
2251 6 unneback
output reg [data_width-1:0] q;
2252
input clk;
2253
always @ (posedge clk)
2254 7 unneback
    q <= data[adr];
2255 6 unneback
endmodule
2256 14 unneback
*/
2257 6 unneback
// Single port RAM
2258
module vl_ram ( d, adr, we, q, clk);
2259
   parameter data_width = 32;
2260
   parameter addr_width = 8;
2261
   input [(data_width-1):0]      d;
2262
   input [(addr_width-1):0]       adr;
2263
   input                         we;
2264 7 unneback
   output reg [(data_width-1):0] q;
2265 6 unneback
   input                         clk;
2266
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
2267 7 unneback
   parameter init = 0;
2268
   parameter memory_file = "vl_ram.vmem";
2269
   generate if (init) begin : init_mem
2270
   initial
2271
     begin
2272
        $readmemh(memory_file, ram);
2273
     end
2274
   end
2275
   endgenerate
2276 6 unneback
   always @ (posedge clk)
2277
   begin
2278
   if (we)
2279
     ram[adr] <= d;
2280
   q <= ram[adr];
2281
   end
2282
endmodule
2283 7 unneback
module vl_ram_be ( d, adr, be, we, q, clk);
2284
   parameter data_width = 32;
2285
   parameter addr_width = 8;
2286
   input [(data_width-1):0]      d;
2287
   input [(addr_width-1):0]       adr;
2288
   input [(addr_width/4)-1:0]    be;
2289
   input                         we;
2290
   output reg [(data_width-1):0] q;
2291
   input                         clk;
2292
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
2293
   parameter init = 0;
2294
   parameter memory_file = "vl_ram.vmem";
2295
   generate if (init) begin : init_mem
2296
   initial
2297
     begin
2298
        $readmemh(memory_file, ram);
2299
     end
2300
   end
2301
   endgenerate
2302
   genvar i;
2303
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
2304
      always @ (posedge clk)
2305
      if (we & be[i])
2306
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
2307
   end
2308
   endgenerate
2309
   always @ (posedge clk)
2310
      q <= ram[adr];
2311
endmodule
2312 6 unneback
// Dual port RAM
2313
// ACTEL FPGA should not use logic to handle rw collision
2314 7 unneback
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
2315 6 unneback
   parameter data_width = 32;
2316
   parameter addr_width = 8;
2317
   input [(data_width-1):0]      d_a;
2318
   input [(addr_width-1):0]       adr_a;
2319
   input [(addr_width-1):0]       adr_b;
2320
   input                         we_a;
2321
   output [(data_width-1):0]      q_b;
2322
   input                         clk_a, clk_b;
2323
   reg [(addr_width-1):0]         adr_b_reg;
2324
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
2325 7 unneback
   parameter init = 0;
2326
   parameter memory_file = "vl_ram.vmem";
2327
   generate if (init) begin : init_mem
2328
   initial
2329
     begin
2330
        $readmemh(memory_file, ram);
2331
     end
2332
   end
2333
   endgenerate
2334 6 unneback
   always @ (posedge clk_a)
2335
   if (we_a)
2336
     ram[adr_a] <= d_a;
2337
   always @ (posedge clk_b)
2338
   adr_b_reg <= adr_b;
2339
   assign q_b = ram[adr_b_reg];
2340
endmodule
2341 7 unneback
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
2342 6 unneback
   parameter data_width = 32;
2343
   parameter addr_width = 8;
2344
   input [(data_width-1):0]      d_a;
2345
   input [(addr_width-1):0]       adr_a;
2346
   input [(addr_width-1):0]       adr_b;
2347
   input                         we_a;
2348
   output [(data_width-1):0]      q_b;
2349
   output reg [(data_width-1):0] q_a;
2350
   input                         clk_a, clk_b;
2351
   reg [(data_width-1):0]         q_b;
2352
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
2353 7 unneback
   parameter init = 0;
2354
   parameter memory_file = "vl_ram.vmem";
2355
   generate if (init) begin : init_mem
2356
   initial
2357
     begin
2358
        $readmemh(memory_file, ram);
2359
     end
2360
   end
2361
   endgenerate
2362 6 unneback
   always @ (posedge clk_a)
2363
     begin
2364
        q_a <= ram[adr_a];
2365
        if (we_a)
2366
             ram[adr_a] <= d_a;
2367
     end
2368
   always @ (posedge clk_b)
2369
          q_b <= ram[adr_b];
2370
endmodule
2371 7 unneback
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
2372 6 unneback
   parameter data_width = 32;
2373
   parameter addr_width = 8;
2374
   input [(data_width-1):0]      d_a;
2375
   input [(addr_width-1):0]       adr_a;
2376
   input [(addr_width-1):0]       adr_b;
2377
   input                         we_a;
2378
   output [(data_width-1):0]      q_b;
2379
   input [(data_width-1):0]       d_b;
2380
   output reg [(data_width-1):0] q_a;
2381
   input                         we_b;
2382
   input                         clk_a, clk_b;
2383
   reg [(data_width-1):0]         q_b;
2384
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
2385 7 unneback
   parameter init = 0;
2386
   parameter memory_file = "vl_ram.vmem";
2387
   generate if (init) begin : init_mem
2388
   initial
2389
     begin
2390
        $readmemh(memory_file, ram);
2391
     end
2392
   end
2393
   endgenerate
2394 6 unneback
   always @ (posedge clk_a)
2395
     begin
2396
        q_a <= ram[adr_a];
2397
        if (we_a)
2398
             ram[adr_a] <= d_a;
2399
     end
2400
   always @ (posedge clk_b)
2401
     begin
2402
        q_b <= ram[adr_b];
2403
        if (we_b)
2404
          ram[adr_b] <= d_b;
2405
     end
2406
endmodule
2407
// Content addresable memory, CAM
2408
// FIFO
2409 25 unneback
module vl_fifo_1r1w_fill_level_sync (
2410
    d, wr, fifo_full,
2411
    q, rd, fifo_empty,
2412
    fill_level,
2413
    clk, rst
2414
    );
2415
parameter data_width = 18;
2416
parameter addr_width = 4;
2417
// write side
2418
input  [data_width-1:0] d;
2419
input                   wr;
2420
output                  fifo_full;
2421
// read side
2422
output [data_width-1:0] q;
2423
input                   rd;
2424
output                  fifo_empty;
2425
// common
2426
output [addr_width:0]   fill_level;
2427
input rst, clk;
2428
wire [addr_width:1] wadr, radr;
2429
vl_cnt_bin_ce
2430
    # ( .length(addr_width))
2431
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
2432
vl_cnt_bin_ce
2433
    # (.length(addr_width))
2434
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
2435
vl_dpram_1r1w
2436
    # (.data_width(data_width), .addr_width(addr_width))
2437
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
2438
vl_cnt_bin_ce_rew_zq_l1
2439 27 unneback
    # (.length(addr_width+1), .level1_value(1<<addr_width))
2440 25 unneback
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
2441
endmodule
2442 27 unneback
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
2443
// RAM is supposed to be larger than the two FIFOs
2444
// LFSR counters used adr pointers
2445
module vl_fifo_2r2w_sync_simplex (
2446
    // a side
2447
    a_d, a_wr, a_fifo_full,
2448
    a_q, a_rd, a_fifo_empty,
2449
    a_fill_level,
2450
    // b side
2451
    b_d, b_wr, b_fifo_full,
2452
    b_q, b_rd, b_fifo_empty,
2453
    b_fill_level,
2454
    // common
2455
    clk, rst
2456
    );
2457
parameter data_width = 8;
2458
parameter addr_width = 5;
2459
parameter fifo_full_level = (1<<addr_width)-1;
2460
// a side
2461
input  [data_width-1:0] a_d;
2462
input                   a_wr;
2463
output                  a_fifo_full;
2464
output [data_width-1:0] a_q;
2465
input                   a_rd;
2466
output                  a_fifo_empty;
2467
output [addr_width-1:0] a_fill_level;
2468
// b side
2469
input  [data_width-1:0] b_d;
2470
input                   b_wr;
2471
output                  b_fifo_full;
2472
output [data_width-1:0] b_q;
2473
input                   b_rd;
2474
output                  b_fifo_empty;
2475
output [addr_width-1:0] b_fill_level;
2476
input                   clk;
2477
input                   rst;
2478
// adr_gen
2479
wire [addr_width:1] a_wadr, a_radr;
2480
wire [addr_width:1] b_wadr, b_radr;
2481
// dpram
2482
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
2483
vl_cnt_lfsr_ce
2484
    # ( .length(addr_width))
2485
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
2486
vl_cnt_lfsr_ce
2487
    # (.length(addr_width))
2488
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
2489
vl_cnt_lfsr_ce
2490
    # ( .length(addr_width))
2491
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
2492
vl_cnt_lfsr_ce
2493
    # (.length(addr_width))
2494
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
2495
// mux read or write adr to DPRAM
2496
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
2497
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
2498
vl_dpram_2r2w
2499
    # (.data_width(data_width), .addr_width(addr_width+1))
2500
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
2501
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
2502
vl_cnt_bin_ce_rew_zq_l1
2503 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
2504 27 unneback
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
2505
vl_cnt_bin_ce_rew_zq_l1
2506 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
2507 27 unneback
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
2508
endmodule
2509 6 unneback
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
2510 11 unneback
   parameter addr_width = 4;
2511
   parameter N = addr_width-1;
2512 6 unneback
   parameter Q1 = 2'b00;
2513
   parameter Q2 = 2'b01;
2514
   parameter Q3 = 2'b11;
2515
   parameter Q4 = 2'b10;
2516
   parameter going_empty = 1'b0;
2517
   parameter going_full  = 1'b1;
2518
   input [N:0]  wptr, rptr;
2519 14 unneback
   output       fifo_empty;
2520 6 unneback
   output       fifo_full;
2521
   input        wclk, rclk, rst;
2522
   wire direction;
2523
   reg  direction_set, direction_clr;
2524
   wire async_empty, async_full;
2525
   wire fifo_full2;
2526 14 unneback
   wire fifo_empty2;
2527 6 unneback
   // direction_set
2528
   always @ (wptr[N:N-1] or rptr[N:N-1])
2529
     case ({wptr[N:N-1],rptr[N:N-1]})
2530
       {Q1,Q2} : direction_set <= 1'b1;
2531
       {Q2,Q3} : direction_set <= 1'b1;
2532
       {Q3,Q4} : direction_set <= 1'b1;
2533
       {Q4,Q1} : direction_set <= 1'b1;
2534
       default : direction_set <= 1'b0;
2535
     endcase
2536
   // direction_clear
2537
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
2538
     if (rst)
2539
       direction_clr <= 1'b1;
2540
     else
2541
       case ({wptr[N:N-1],rptr[N:N-1]})
2542
         {Q2,Q1} : direction_clr <= 1'b1;
2543
         {Q3,Q2} : direction_clr <= 1'b1;
2544
         {Q4,Q3} : direction_clr <= 1'b1;
2545
         {Q1,Q4} : direction_clr <= 1'b1;
2546
         default : direction_clr <= 1'b0;
2547
       endcase
2548 18 unneback
    vl_dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
2549 6 unneback
   assign async_empty = (wptr == rptr) && (direction==going_empty);
2550
   assign async_full  = (wptr == rptr) && (direction==going_full);
2551 18 unneback
    vl_dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
2552
    vl_dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
2553 6 unneback
/*
2554
   always @ (posedge wclk or posedge rst or posedge async_full)
2555
     if (rst)
2556
       {fifo_full, fifo_full2} <= 2'b00;
2557
     else if (async_full)
2558
       {fifo_full, fifo_full2} <= 2'b11;
2559
     else
2560
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
2561
*/
2562 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
2563 6 unneback
     if (async_empty)
2564
       {fifo_empty, fifo_empty2} <= 2'b11;
2565
     else
2566 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
2567 18 unneback
    vl_dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
2568
    vl_dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
2569 27 unneback
endmodule // async_compb
2570 6 unneback
module vl_fifo_1r1w_async (
2571
    d, wr, fifo_full, wr_clk, wr_rst,
2572
    q, rd, fifo_empty, rd_clk, rd_rst
2573
    );
2574
parameter data_width = 18;
2575
parameter addr_width = 4;
2576
// write side
2577
input  [data_width-1:0] d;
2578
input                   wr;
2579
output                  fifo_full;
2580
input                   wr_clk;
2581
input                   wr_rst;
2582
// read side
2583
output [data_width-1:0] q;