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1 6 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
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////  Versatile library, clock and reset                          ////
4
////                                                              ////
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////  Description                                                 ////
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////  Logic related to clock and reset                            ////
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////                                                              ////
8
////                                                              ////
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////  To Do:                                                      ////
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////   - add more different registers                             ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
14
////        ORSoC AB                                              ////
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////                                                              ////
16
//////////////////////////////////////////////////////////////////////
17
////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
19
////                                                              ////
20
//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
36
////                                                              ////
37
//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
// Global buffer
43
// usage:
44
// use to enable global buffers for high fan out signals such as clock and reset
45
`timescale 1 ns/100 ps
46
// Version: 8.4 8.4.0.33
47
module gbuf(GL,CLK);
48
output GL;
49
input  CLK;
50
    wire GND;
51
    GND GND_1_net(.Y(GND));
52
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
53
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
54
endmodule
55
`timescale 1 ns/1 ns
56
module vl_gbuf ( i, o);
57
input i;
58
output o;
59
`ifdef SIM_GBUF
60
assign o=i;
61
`else
62
gbuf gbuf_i0 ( .CLK(i), .GL(o));
63
`endif
64
endmodule
65
 //ACTEL
66
// sync reset
67 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
68 6 unneback
// output active high global reset sync with two DFFs 
69
`timescale 1 ns/100 ps
70
module vl_sync_rst ( rst_n_i, rst_o, clk);
71
input rst_n_i, clk;
72
output rst_o;
73 18 unneback
reg [1:0] tmp;
74 6 unneback
always @ (posedge clk or negedge rst_n_i)
75
if (!rst_n_i)
76 17 unneback
        tmp <= 2'b11;
77 6 unneback
else
78 33 unneback
        tmp <= {1'b0,tmp[1]};
79 17 unneback
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
80 6 unneback
endmodule
81
// vl_pll
82 32 unneback
///////////////////////////////////////////////////////////////////////////////
83 17 unneback
`timescale 1 ps/1 ps
84 6 unneback
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
85
parameter index = 0;
86
parameter number_of_clk = 1;
87 17 unneback
parameter period_time_0 = 20000;
88
parameter period_time_1 = 20000;
89
parameter period_time_2 = 20000;
90
parameter lock_delay = 2000000;
91 6 unneback
input clk_i, rst_n_i;
92
output lock;
93
output reg [0:number_of_clk-1] clk_o;
94
output [0:number_of_clk-1] rst_o;
95
`ifdef SIM_PLL
96
always
97
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
98
generate if (number_of_clk > 1)
99
always
100
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
101
endgenerate
102
generate if (number_of_clk > 2)
103
always
104
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
105
endgenerate
106
genvar i;
107
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
108
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
109
end
110
endgenerate
111
assign #lock_delay lock = rst_n_i;
112
endmodule
113
`else
114
generate if (number_of_clk==1 & index==0) begin
115
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
116
end
117
endgenerate // index==0
118
generate if (number_of_clk==1 & index==1) begin
119
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
120
end
121
endgenerate // index==1
122
generate if (number_of_clk==1 & index==2) begin
123
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
124
end
125
endgenerate // index==2
126
generate if (number_of_clk==1 & index==3) begin
127
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
128
end
129
endgenerate // index==0
130
generate if (number_of_clk==2 & index==0) begin
131
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
132
end
133
endgenerate // index==0
134
generate if (number_of_clk==2 & index==1) begin
135
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
136
end
137
endgenerate // index==1
138
generate if (number_of_clk==2 & index==2) begin
139
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
140
end
141
endgenerate // index==2
142
generate if (number_of_clk==2 & index==3) begin
143
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
144
end
145
endgenerate // index==0
146
generate if (number_of_clk==3 & index==0) begin
147
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
148
end
149
endgenerate // index==0
150
generate if (number_of_clk==3 & index==1) begin
151
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
152
end
153
endgenerate // index==1
154
generate if (number_of_clk==3 & index==2) begin
155
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
156
end
157
endgenerate // index==2
158
generate if (number_of_clk==3 & index==3) begin
159
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
160
end
161
endgenerate // index==0
162
genvar i;
163
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
164
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
165
end
166
endgenerate
167
endmodule
168
`endif
169 32 unneback
///////////////////////////////////////////////////////////////////////////////
170 6 unneback
 //actel
171
//////////////////////////////////////////////////////////////////////
172
////                                                              ////
173
////  Versatile library, registers                                ////
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////                                                              ////
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////  Description                                                 ////
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////  Different type of registers                                 ////
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////                                                              ////
178
////                                                              ////
179
////  To Do:                                                      ////
180
////   - add more different registers                             ////
181
////                                                              ////
182
////  Author(s):                                                  ////
183
////      - Michael Unneback, unneback@opencores.org              ////
184
////        ORSoC AB                                              ////
185
////                                                              ////
186
//////////////////////////////////////////////////////////////////////
187
////                                                              ////
188
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
189
////                                                              ////
190
//// This source file may be used and distributed without         ////
191
//// restriction provided that this copyright statement is not    ////
192
//// removed from the file and that any derivative work contains  ////
193
//// the original copyright notice and the associated disclaimer. ////
194
////                                                              ////
195
//// This source file is free software; you can redistribute it   ////
196
//// and/or modify it under the terms of the GNU Lesser General   ////
197
//// Public License as published by the Free Software Foundation; ////
198
//// either version 2.1 of the License, or (at your option) any   ////
199
//// later version.                                               ////
200
////                                                              ////
201
//// This source is distributed in the hope that it will be       ////
202
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
203
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
204
//// PURPOSE.  See the GNU Lesser General Public License for more ////
205
//// details.                                                     ////
206
////                                                              ////
207
//// You should have received a copy of the GNU Lesser General    ////
208
//// Public License along with this source; if not, download it   ////
209
//// from http://www.opencores.org/lgpl.shtml                     ////
210
////                                                              ////
211
//////////////////////////////////////////////////////////////////////
212 18 unneback
module vl_dff ( d, q, clk, rst);
213 6 unneback
        parameter width = 1;
214
        parameter reset_value = 0;
215
        input [width-1:0] d;
216
        input clk, rst;
217
        output reg [width-1:0] q;
218
        always @ (posedge clk or posedge rst)
219
        if (rst)
220
                q <= reset_value;
221
        else
222
                q <= d;
223
endmodule
224 18 unneback
module vl_dff_array ( d, q, clk, rst);
225 6 unneback
        parameter width = 1;
226
        parameter depth = 2;
227
        parameter reset_value = 1'b0;
228
        input [width-1:0] d;
229
        input clk, rst;
230
        output [width-1:0] q;
231
        reg  [0:depth-1] q_tmp [width-1:0];
232
        integer i;
233
        always @ (posedge clk or posedge rst)
234
        if (rst) begin
235
            for (i=0;i<depth;i=i+1)
236
                q_tmp[i] <= {width{reset_value}};
237
        end else begin
238
            q_tmp[0] <= d;
239
            for (i=1;i<depth;i=i+1)
240
                q_tmp[i] <= q_tmp[i-1];
241
        end
242
    assign q = q_tmp[depth-1];
243
endmodule
244 18 unneback
module vl_dff_ce ( d, ce, q, clk, rst);
245 6 unneback
        parameter width = 1;
246
        parameter reset_value = 0;
247
        input [width-1:0] d;
248
        input ce, clk, rst;
249
        output reg [width-1:0] q;
250
        always @ (posedge clk or posedge rst)
251
        if (rst)
252
                q <= reset_value;
253
        else
254
                if (ce)
255
                        q <= d;
256
endmodule
257 18 unneback
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
258 8 unneback
        parameter width = 1;
259
        parameter reset_value = 0;
260
        input [width-1:0] d;
261 10 unneback
        input ce, clear, clk, rst;
262 8 unneback
        output reg [width-1:0] q;
263
        always @ (posedge clk or posedge rst)
264
        if (rst)
265
            q <= reset_value;
266
        else
267
            if (ce)
268
                if (clear)
269
                    q <= {width{1'b0}};
270
                else
271
                    q <= d;
272
endmodule
273 24 unneback
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
274
        parameter width = 1;
275
        parameter reset_value = 0;
276
        input [width-1:0] d;
277
        input ce, set, clk, rst;
278
        output reg [width-1:0] q;
279
        always @ (posedge clk or posedge rst)
280
        if (rst)
281
            q <= reset_value;
282
        else
283
            if (ce)
284
                if (set)
285
                    q <= {width{1'b1}};
286
                else
287
                    q <= d;
288
endmodule
289 29 unneback
module vl_spr ( sp, r, q, clk, rst);
290
        parameter width = 1;
291
        parameter reset_value = 0;
292
        input sp, r;
293
        output reg q;
294
        input clk, rst;
295
        always @ (posedge clk or posedge rst)
296
        if (rst)
297
            q <= reset_value;
298
        else
299
            if (sp)
300
                q <= 1'b1;
301
            else if (r)
302
                q <= 1'b0;
303
endmodule
304
module vl_srp ( s, rp, q, clk, rst);
305
        parameter width = 1;
306
        parameter reset_value = 0;
307
        input s, rp;
308
        output reg q;
309
        input clk, rst;
310
        always @ (posedge clk or posedge rst)
311
        if (rst)
312
            q <= reset_value;
313
        else
314
            if (rp)
315
                q <= 1'b0;
316
            else if (s)
317
                q <= 1'b1;
318
endmodule
319 18 unneback
module vl_dff_sr ( aclr, aset, clock, data, q);
320 6 unneback
    input         aclr;
321
    input         aset;
322
    input         clock;
323
    input         data;
324
    output reg    q;
325
   always @ (posedge clock or posedge aclr or posedge aset)
326
     if (aclr)
327
       q <= 1'b0;
328
     else if (aset)
329
       q <= 1'b1;
330
     else
331
       q <= data;
332
endmodule
333
// LATCH
334
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
335
module latch ( d, le, q, clk);
336
input d, le;
337
output q;
338
input clk;/*
339
   always @ (posedge direction_set or posedge direction_clr)
340
     if (direction_clr)
341
       direction <= going_empty;
342
     else
343
       direction <= going_full;*/
344
endmodule
345 18 unneback
module vl_shreg ( d, q, clk, rst);
346 17 unneback
parameter depth = 10;
347
input d;
348
output q;
349
input clk, rst;
350
reg [1:depth] dffs;
351
always @ (posedge clk or posedge rst)
352
if (rst)
353
    dffs <= {depth{1'b0}};
354
else
355
    dffs <= {d,dffs[1:depth-1]};
356
assign q = dffs[depth];
357
endmodule
358 18 unneback
module vl_shreg_ce ( d, ce, q, clk, rst);
359 17 unneback
parameter depth = 10;
360
input d, ce;
361
output q;
362
input clk, rst;
363
reg [1:depth] dffs;
364
always @ (posedge clk or posedge rst)
365
if (rst)
366
    dffs <= {depth{1'b0}};
367
else
368
    if (ce)
369
        dffs <= {d,dffs[1:depth-1]};
370
assign q = dffs[depth];
371
endmodule
372 18 unneback
module vl_delay ( d, q, clk, rst);
373 15 unneback
parameter depth = 10;
374
input d;
375
output q;
376
input clk, rst;
377
reg [1:depth] dffs;
378
always @ (posedge clk or posedge rst)
379
if (rst)
380
    dffs <= {depth{1'b0}};
381
else
382
    dffs <= {d,dffs[1:depth-1]};
383
assign q = dffs[depth];
384
endmodule
385 18 unneback
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
386 17 unneback
parameter depth = 10;
387
input d;
388
output q, emptyflag;
389
input clk, rst;
390
reg [1:depth] dffs;
391
always @ (posedge clk or posedge rst)
392
if (rst)
393
    dffs <= {depth{1'b0}};
394
else
395
    dffs <= {d,dffs[1:depth-1]};
396
assign q = dffs[depth];
397
assign emptyflag = !(|dffs);
398
endmodule
399 6 unneback
//////////////////////////////////////////////////////////////////////
400
////                                                              ////
401 18 unneback
////  Logic functions                                             ////
402
////                                                              ////
403
////  Description                                                 ////
404
////  Logic functions such as multiplexers                        ////
405
////                                                              ////
406
////                                                              ////
407
////  To Do:                                                      ////
408
////   -                                                          ////
409
////                                                              ////
410
////  Author(s):                                                  ////
411
////      - Michael Unneback, unneback@opencores.org              ////
412
////        ORSoC AB                                              ////
413
////                                                              ////
414
//////////////////////////////////////////////////////////////////////
415
////                                                              ////
416
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
417
////                                                              ////
418
//// This source file may be used and distributed without         ////
419
//// restriction provided that this copyright statement is not    ////
420
//// removed from the file and that any derivative work contains  ////
421
//// the original copyright notice and the associated disclaimer. ////
422
////                                                              ////
423
//// This source file is free software; you can redistribute it   ////
424
//// and/or modify it under the terms of the GNU Lesser General   ////
425
//// Public License as published by the Free Software Foundation; ////
426
//// either version 2.1 of the License, or (at your option) any   ////
427
//// later version.                                               ////
428
////                                                              ////
429
//// This source is distributed in the hope that it will be       ////
430
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
431
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
432
//// PURPOSE.  See the GNU Lesser General Public License for more ////
433
//// details.                                                     ////
434
////                                                              ////
435
//// You should have received a copy of the GNU Lesser General    ////
436
//// Public License along with this source; if not, download it   ////
437
//// from http://www.opencores.org/lgpl.shtml                     ////
438
////                                                              ////
439
//////////////////////////////////////////////////////////////////////
440
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
441
parameter width = 32;
442
parameter nr_of_ports = 4;
443
input [width-1:0] a3, a2, a1, a0;
444
input [nr_of_ports-1:0] sel;
445 22 unneback
output [width-1:0] dout;
446 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
447 18 unneback
integer i;
448
// and
449
assign tmp[0] = {width{sel[0]}} & a0;
450
assign tmp[1] = {width{sel[1]}} & a1;
451
assign tmp[2] = {width{sel[2]}} & a2;
452
assign tmp[3] = {width{sel[3]}} & a3;
453
// or
454
assign dout = tmp[3] | tmp[2] | tmp[1] | tmp[0];
455
endmodule
456
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
457
parameter width = 32;
458
parameter nr_of_ports = 5;
459
input [width-1:0] a4, a3, a2, a1, a0;
460
input [nr_of_ports-1:0] sel;
461 22 unneback
output [width-1:0] dout;
462 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
463 18 unneback
integer i;
464
// and
465
assign tmp[0] = {width{sel[0]}} & a0;
466
assign tmp[1] = {width{sel[1]}} & a1;
467
assign tmp[2] = {width{sel[2]}} & a2;
468
assign tmp[3] = {width{sel[3]}} & a3;
469
assign tmp[4] = {width{sel[4]}} & a4;
470
// or
471
assign dout = tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
472
endmodule
473
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
474
parameter width = 32;
475
parameter nr_of_ports = 6;
476
input [width-1:0] a5, a4, a3, a2, a1, a0;
477
input [nr_of_ports-1:0] sel;
478 22 unneback
output [width-1:0] dout;
479 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
480 18 unneback
integer i;
481
// and
482
assign tmp[0] = {width{sel[0]}} & a0;
483
assign tmp[1] = {width{sel[1]}} & a1;
484
assign tmp[2] = {width{sel[2]}} & a2;
485
assign tmp[3] = {width{sel[3]}} & a3;
486
assign tmp[4] = {width{sel[4]}} & a4;
487
assign tmp[5] = {width{sel[5]}} & a5;
488
// or
489
assign dout = tmp[5] | tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
490
endmodule
491
//////////////////////////////////////////////////////////////////////
492
////                                                              ////
493 6 unneback
////  Versatile counter                                           ////
494
////                                                              ////
495
////  Description                                                 ////
496
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
497
////  counter                                                     ////
498
////                                                              ////
499
////  To Do:                                                      ////
500
////   - add LFSR with more taps                                  ////
501
////                                                              ////
502
////  Author(s):                                                  ////
503
////      - Michael Unneback, unneback@opencores.org              ////
504
////        ORSoC AB                                              ////
505
////                                                              ////
506
//////////////////////////////////////////////////////////////////////
507
////                                                              ////
508
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
509
////                                                              ////
510
//// This source file may be used and distributed without         ////
511
//// restriction provided that this copyright statement is not    ////
512
//// removed from the file and that any derivative work contains  ////
513
//// the original copyright notice and the associated disclaimer. ////
514
////                                                              ////
515
//// This source file is free software; you can redistribute it   ////
516
//// and/or modify it under the terms of the GNU Lesser General   ////
517
//// Public License as published by the Free Software Foundation; ////
518
//// either version 2.1 of the License, or (at your option) any   ////
519
//// later version.                                               ////
520
////                                                              ////
521
//// This source is distributed in the hope that it will be       ////
522
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
523
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
524
//// PURPOSE.  See the GNU Lesser General Public License for more ////
525
//// details.                                                     ////
526
////                                                              ////
527
//// You should have received a copy of the GNU Lesser General    ////
528
//// Public License along with this source; if not, download it   ////
529
//// from http://www.opencores.org/lgpl.shtml                     ////
530
////                                                              ////
531
//////////////////////////////////////////////////////////////////////
532
// binary counter
533 22 unneback
module vl_cnt_bin ( q, rst, clk);
534
   parameter length = 4;
535
   output [length:1] q;
536
   input rst;
537
   input clk;
538
   parameter clear_value = 0;
539
   parameter set_value = 1;
540
   parameter wrap_value = 0;
541
   parameter level1_value = 15;
542
   reg  [length:1] qi;
543
   wire [length:1] q_next;
544
   assign q_next = qi + {{length-1{1'b0}},1'b1};
545
   always @ (posedge clk or posedge rst)
546
     if (rst)
547
       qi <= {length{1'b0}};
548
     else
549
       qi <= q_next;
550
   assign q = qi;
551
endmodule
552
//////////////////////////////////////////////////////////////////////
553
////                                                              ////
554
////  Versatile counter                                           ////
555
////                                                              ////
556
////  Description                                                 ////
557
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
558
////  counter                                                     ////
559
////                                                              ////
560
////  To Do:                                                      ////
561
////   - add LFSR with more taps                                  ////
562
////                                                              ////
563
////  Author(s):                                                  ////
564
////      - Michael Unneback, unneback@opencores.org              ////
565
////        ORSoC AB                                              ////
566
////                                                              ////
567
//////////////////////////////////////////////////////////////////////
568
////                                                              ////
569
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
570
////                                                              ////
571
//// This source file may be used and distributed without         ////
572
//// restriction provided that this copyright statement is not    ////
573
//// removed from the file and that any derivative work contains  ////
574
//// the original copyright notice and the associated disclaimer. ////
575
////                                                              ////
576
//// This source file is free software; you can redistribute it   ////
577
//// and/or modify it under the terms of the GNU Lesser General   ////
578
//// Public License as published by the Free Software Foundation; ////
579
//// either version 2.1 of the License, or (at your option) any   ////
580
//// later version.                                               ////
581
////                                                              ////
582
//// This source is distributed in the hope that it will be       ////
583
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
584
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
585
//// PURPOSE.  See the GNU Lesser General Public License for more ////
586
//// details.                                                     ////
587
////                                                              ////
588
//// You should have received a copy of the GNU Lesser General    ////
589
//// Public License along with this source; if not, download it   ////
590
//// from http://www.opencores.org/lgpl.shtml                     ////
591
////                                                              ////
592
//////////////////////////////////////////////////////////////////////
593
// binary counter
594
module vl_cnt_bin_clear ( clear, q, rst, clk);
595
   parameter length = 4;
596
   input clear;
597
   output [length:1] q;
598
   input rst;
599
   input clk;
600
   parameter clear_value = 0;
601
   parameter set_value = 1;
602
   parameter wrap_value = 0;
603
   parameter level1_value = 15;
604
   reg  [length:1] qi;
605
   wire [length:1] q_next;
606
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
607
   always @ (posedge clk or posedge rst)
608
     if (rst)
609
       qi <= {length{1'b0}};
610
     else
611
       qi <= q_next;
612
   assign q = qi;
613
endmodule
614
//////////////////////////////////////////////////////////////////////
615
////                                                              ////
616
////  Versatile counter                                           ////
617
////                                                              ////
618
////  Description                                                 ////
619
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
620
////  counter                                                     ////
621
////                                                              ////
622
////  To Do:                                                      ////
623
////   - add LFSR with more taps                                  ////
624
////                                                              ////
625
////  Author(s):                                                  ////
626
////      - Michael Unneback, unneback@opencores.org              ////
627
////        ORSoC AB                                              ////
628
////                                                              ////
629
//////////////////////////////////////////////////////////////////////
630
////                                                              ////
631
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
632
////                                                              ////
633
//// This source file may be used and distributed without         ////
634
//// restriction provided that this copyright statement is not    ////
635
//// removed from the file and that any derivative work contains  ////
636
//// the original copyright notice and the associated disclaimer. ////
637
////                                                              ////
638
//// This source file is free software; you can redistribute it   ////
639
//// and/or modify it under the terms of the GNU Lesser General   ////
640
//// Public License as published by the Free Software Foundation; ////
641
//// either version 2.1 of the License, or (at your option) any   ////
642
//// later version.                                               ////
643
////                                                              ////
644
//// This source is distributed in the hope that it will be       ////
645
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
646
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
647
//// PURPOSE.  See the GNU Lesser General Public License for more ////
648
//// details.                                                     ////
649
////                                                              ////
650
//// You should have received a copy of the GNU Lesser General    ////
651
//// Public License along with this source; if not, download it   ////
652
//// from http://www.opencores.org/lgpl.shtml                     ////
653
////                                                              ////
654
//////////////////////////////////////////////////////////////////////
655
// binary counter
656 18 unneback
module vl_cnt_bin_ce ( cke, q, rst, clk);
657 6 unneback
   parameter length = 4;
658
   input cke;
659
   output [length:1] q;
660
   input rst;
661
   input clk;
662
   parameter clear_value = 0;
663
   parameter set_value = 1;
664
   parameter wrap_value = 0;
665
   parameter level1_value = 15;
666
   reg  [length:1] qi;
667
   wire [length:1] q_next;
668
   assign q_next = qi + {{length-1{1'b0}},1'b1};
669
   always @ (posedge clk or posedge rst)
670
     if (rst)
671
       qi <= {length{1'b0}};
672
     else
673
     if (cke)
674
       qi <= q_next;
675
   assign q = qi;
676
endmodule
677
//////////////////////////////////////////////////////////////////////
678
////                                                              ////
679
////  Versatile counter                                           ////
680
////                                                              ////
681
////  Description                                                 ////
682
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
683
////  counter                                                     ////
684
////                                                              ////
685
////  To Do:                                                      ////
686
////   - add LFSR with more taps                                  ////
687
////                                                              ////
688
////  Author(s):                                                  ////
689
////      - Michael Unneback, unneback@opencores.org              ////
690
////        ORSoC AB                                              ////
691
////                                                              ////
692
//////////////////////////////////////////////////////////////////////
693
////                                                              ////
694
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
695
////                                                              ////
696
//// This source file may be used and distributed without         ////
697
//// restriction provided that this copyright statement is not    ////
698
//// removed from the file and that any derivative work contains  ////
699
//// the original copyright notice and the associated disclaimer. ////
700
////                                                              ////
701
//// This source file is free software; you can redistribute it   ////
702
//// and/or modify it under the terms of the GNU Lesser General   ////
703
//// Public License as published by the Free Software Foundation; ////
704
//// either version 2.1 of the License, or (at your option) any   ////
705
//// later version.                                               ////
706
////                                                              ////
707
//// This source is distributed in the hope that it will be       ////
708
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
709
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
710
//// PURPOSE.  See the GNU Lesser General Public License for more ////
711
//// details.                                                     ////
712
////                                                              ////
713
//// You should have received a copy of the GNU Lesser General    ////
714
//// Public License along with this source; if not, download it   ////
715
//// from http://www.opencores.org/lgpl.shtml                     ////
716
////                                                              ////
717
//////////////////////////////////////////////////////////////////////
718
// binary counter
719 18 unneback
module vl_cnt_bin_ce_clear ( clear, cke, q, rst, clk);
720 6 unneback
   parameter length = 4;
721
   input clear;
722
   input cke;
723
   output [length:1] q;
724
   input rst;
725
   input clk;
726
   parameter clear_value = 0;
727
   parameter set_value = 1;
728
   parameter wrap_value = 0;
729
   parameter level1_value = 15;
730
   reg  [length:1] qi;
731
   wire [length:1] q_next;
732
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
733
   always @ (posedge clk or posedge rst)
734
     if (rst)
735
       qi <= {length{1'b0}};
736
     else
737
     if (cke)
738
       qi <= q_next;
739
   assign q = qi;
740
endmodule
741
//////////////////////////////////////////////////////////////////////
742
////                                                              ////
743
////  Versatile counter                                           ////
744
////                                                              ////
745
////  Description                                                 ////
746
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
747
////  counter                                                     ////
748
////                                                              ////
749
////  To Do:                                                      ////
750
////   - add LFSR with more taps                                  ////
751
////                                                              ////
752
////  Author(s):                                                  ////
753
////      - Michael Unneback, unneback@opencores.org              ////
754
////        ORSoC AB                                              ////
755
////                                                              ////
756
//////////////////////////////////////////////////////////////////////
757
////                                                              ////
758
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
759
////                                                              ////
760
//// This source file may be used and distributed without         ////
761
//// restriction provided that this copyright statement is not    ////
762
//// removed from the file and that any derivative work contains  ////
763
//// the original copyright notice and the associated disclaimer. ////
764
////                                                              ////
765
//// This source file is free software; you can redistribute it   ////
766
//// and/or modify it under the terms of the GNU Lesser General   ////
767
//// Public License as published by the Free Software Foundation; ////
768
//// either version 2.1 of the License, or (at your option) any   ////
769
//// later version.                                               ////
770
////                                                              ////
771
//// This source is distributed in the hope that it will be       ////
772
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
773
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
774
//// PURPOSE.  See the GNU Lesser General Public License for more ////
775
//// details.                                                     ////
776
////                                                              ////
777
//// You should have received a copy of the GNU Lesser General    ////
778
//// Public License along with this source; if not, download it   ////
779
//// from http://www.opencores.org/lgpl.shtml                     ////
780
////                                                              ////
781
//////////////////////////////////////////////////////////////////////
782
// binary counter
783 29 unneback
module vl_cnt_bin_ce_clear_l1_l2 ( clear, cke, q, level1, level2, rst, clk);
784
   parameter length = 4;
785
   input clear;
786
   input cke;
787
   output [length:1] q;
788
   output reg level1;
789
   output reg level2;
790
   input rst;
791
   input clk;
792
   parameter clear_value = 0;
793
   parameter set_value = 1;
794 30 unneback
   parameter wrap_value = 15;
795
   parameter level1_value = 8;
796
   parameter level2_value = 15;
797 29 unneback
   wire rew;
798 30 unneback
   assign rew = 1'b0;
799 29 unneback
   reg  [length:1] qi;
800
   wire [length:1] q_next;
801
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
802
   always @ (posedge clk or posedge rst)
803
     if (rst)
804
       qi <= {length{1'b0}};
805
     else
806
     if (cke)
807
       qi <= q_next;
808
   assign q = qi;
809
    always @ (posedge clk or posedge rst)
810
    if (rst)
811
        level1 <= 1'b0;
812
    else
813
    if (cke)
814
    if (clear)
815
        level1 <= 1'b0;
816
    else if (q_next == level1_value)
817
        level1 <= 1'b1;
818
    else if (qi == level1_value & rew)
819
        level1 <= 1'b0;
820
    always @ (posedge clk or posedge rst)
821
    if (rst)
822
        level2 <= 1'b0;
823
    else
824
    if (cke)
825
    if (clear)
826
        level2 <= 1'b0;
827
    else if (q_next == level2_value)
828
        level2 <= 1'b1;
829
    else if (qi == level2_value & rew)
830
        level2 <= 1'b0;
831
endmodule
832
//////////////////////////////////////////////////////////////////////
833
////                                                              ////
834
////  Versatile counter                                           ////
835
////                                                              ////
836
////  Description                                                 ////
837
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
838
////  counter                                                     ////
839
////                                                              ////
840
////  To Do:                                                      ////
841
////   - add LFSR with more taps                                  ////
842
////                                                              ////
843
////  Author(s):                                                  ////
844
////      - Michael Unneback, unneback@opencores.org              ////
845
////        ORSoC AB                                              ////
846
////                                                              ////
847
//////////////////////////////////////////////////////////////////////
848
////                                                              ////
849
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
850
////                                                              ////
851
//// This source file may be used and distributed without         ////
852
//// restriction provided that this copyright statement is not    ////
853
//// removed from the file and that any derivative work contains  ////
854
//// the original copyright notice and the associated disclaimer. ////
855
////                                                              ////
856
//// This source file is free software; you can redistribute it   ////
857
//// and/or modify it under the terms of the GNU Lesser General   ////
858
//// Public License as published by the Free Software Foundation; ////
859
//// either version 2.1 of the License, or (at your option) any   ////
860
//// later version.                                               ////
861
////                                                              ////
862
//// This source is distributed in the hope that it will be       ////
863
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
864
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
865
//// PURPOSE.  See the GNU Lesser General Public License for more ////
866
//// details.                                                     ////
867
////                                                              ////
868
//// You should have received a copy of the GNU Lesser General    ////
869
//// Public License along with this source; if not, download it   ////
870
//// from http://www.opencores.org/lgpl.shtml                     ////
871
////                                                              ////
872
//////////////////////////////////////////////////////////////////////
873
// binary counter
874 18 unneback
module vl_cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk);
875 6 unneback
   parameter length = 4;
876
   input clear;
877
   input set;
878
   input cke;
879
   input rew;
880
   output [length:1] q;
881
   input rst;
882
   input clk;
883
   parameter clear_value = 0;
884
   parameter set_value = 1;
885
   parameter wrap_value = 0;
886
   parameter level1_value = 15;
887
   reg  [length:1] qi;
888
   wire  [length:1] q_next, q_next_fw, q_next_rew;
889
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
890
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
891
   assign q_next = rew ? q_next_rew : q_next_fw;
892
   always @ (posedge clk or posedge rst)
893
     if (rst)
894
       qi <= {length{1'b0}};
895
     else
896
     if (cke)
897
       qi <= q_next;
898
   assign q = qi;
899
endmodule
900
//////////////////////////////////////////////////////////////////////
901
////                                                              ////
902
////  Versatile counter                                           ////
903
////                                                              ////
904
////  Description                                                 ////
905
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
906
////  counter                                                     ////
907
////                                                              ////
908
////  To Do:                                                      ////
909
////   - add LFSR with more taps                                  ////
910
////                                                              ////
911
////  Author(s):                                                  ////
912
////      - Michael Unneback, unneback@opencores.org              ////
913
////        ORSoC AB                                              ////
914
////                                                              ////
915
//////////////////////////////////////////////////////////////////////
916
////                                                              ////
917
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
918
////                                                              ////
919
//// This source file may be used and distributed without         ////
920
//// restriction provided that this copyright statement is not    ////
921
//// removed from the file and that any derivative work contains  ////
922
//// the original copyright notice and the associated disclaimer. ////
923
////                                                              ////
924
//// This source file is free software; you can redistribute it   ////
925
//// and/or modify it under the terms of the GNU Lesser General   ////
926
//// Public License as published by the Free Software Foundation; ////
927
//// either version 2.1 of the License, or (at your option) any   ////
928
//// later version.                                               ////
929
////                                                              ////
930
//// This source is distributed in the hope that it will be       ////
931
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
932
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
933
//// PURPOSE.  See the GNU Lesser General Public License for more ////
934
//// details.                                                     ////
935
////                                                              ////
936
//// You should have received a copy of the GNU Lesser General    ////
937
//// Public License along with this source; if not, download it   ////
938
//// from http://www.opencores.org/lgpl.shtml                     ////
939
////                                                              ////
940
//////////////////////////////////////////////////////////////////////
941
// binary counter
942 18 unneback
module vl_cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk);
943 6 unneback
   parameter length = 4;
944
   input cke;
945
   input rew;
946
   output reg level1;
947
   input rst;
948
   input clk;
949
   parameter clear_value = 0;
950
   parameter set_value = 1;
951
   parameter wrap_value = 1;
952
   parameter level1_value = 15;
953 29 unneback
   wire clear;
954 30 unneback
   assign clear = 1'b0;
955 6 unneback
   reg  [length:1] qi;
956
   wire  [length:1] q_next, q_next_fw, q_next_rew;
957
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
958
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
959
   assign q_next = rew ? q_next_rew : q_next_fw;
960
   always @ (posedge clk or posedge rst)
961
     if (rst)
962
       qi <= {length{1'b0}};
963
     else
964
     if (cke)
965
       qi <= q_next;
966
    always @ (posedge clk or posedge rst)
967
    if (rst)
968
        level1 <= 1'b0;
969
    else
970
    if (cke)
971 29 unneback
    if (clear)
972
        level1 <= 1'b0;
973
    else if (q_next == level1_value)
974 6 unneback
        level1 <= 1'b1;
975
    else if (qi == level1_value & rew)
976
        level1 <= 1'b0;
977
endmodule
978
//////////////////////////////////////////////////////////////////////
979
////                                                              ////
980
////  Versatile counter                                           ////
981
////                                                              ////
982
////  Description                                                 ////
983
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
984
////  counter                                                     ////
985
////                                                              ////
986
////  To Do:                                                      ////
987
////   - add LFSR with more taps                                  ////
988
////                                                              ////
989
////  Author(s):                                                  ////
990
////      - Michael Unneback, unneback@opencores.org              ////
991
////        ORSoC AB                                              ////
992
////                                                              ////
993
//////////////////////////////////////////////////////////////////////
994
////                                                              ////
995
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
996
////                                                              ////
997
//// This source file may be used and distributed without         ////
998
//// restriction provided that this copyright statement is not    ////
999
//// removed from the file and that any derivative work contains  ////
1000
//// the original copyright notice and the associated disclaimer. ////
1001
////                                                              ////
1002
//// This source file is free software; you can redistribute it   ////
1003
//// and/or modify it under the terms of the GNU Lesser General   ////
1004
//// Public License as published by the Free Software Foundation; ////
1005
//// either version 2.1 of the License, or (at your option) any   ////
1006
//// later version.                                               ////
1007
////                                                              ////
1008
//// This source is distributed in the hope that it will be       ////
1009
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1010
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1011
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1012
//// details.                                                     ////
1013
////                                                              ////
1014
//// You should have received a copy of the GNU Lesser General    ////
1015
//// Public License along with this source; if not, download it   ////
1016
//// from http://www.opencores.org/lgpl.shtml                     ////
1017
////                                                              ////
1018
//////////////////////////////////////////////////////////////////////
1019 25 unneback
// binary counter
1020
module vl_cnt_bin_ce_rew_zq_l1 ( cke, rew, zq, level1, rst, clk);
1021
   parameter length = 4;
1022
   input cke;
1023
   input rew;
1024
   output reg zq;
1025
   output reg level1;
1026
   input rst;
1027
   input clk;
1028
   parameter clear_value = 0;
1029
   parameter set_value = 1;
1030
   parameter wrap_value = 1;
1031
   parameter level1_value = 15;
1032 29 unneback
   wire clear;
1033 30 unneback
   assign clear = 1'b0;
1034 25 unneback
   reg  [length:1] qi;
1035
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1036
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1037
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1038
   assign q_next = rew ? q_next_rew : q_next_fw;
1039
   always @ (posedge clk or posedge rst)
1040
     if (rst)
1041
       qi <= {length{1'b0}};
1042
     else
1043
     if (cke)
1044
       qi <= q_next;
1045
   always @ (posedge clk or posedge rst)
1046
     if (rst)
1047
       zq <= 1'b1;
1048
     else
1049
     if (cke)
1050
       zq <= q_next == {length{1'b0}};
1051
    always @ (posedge clk or posedge rst)
1052
    if (rst)
1053
        level1 <= 1'b0;
1054
    else
1055
    if (cke)
1056 29 unneback
    if (clear)
1057
        level1 <= 1'b0;
1058
    else if (q_next == level1_value)
1059 25 unneback
        level1 <= 1'b1;
1060
    else if (qi == level1_value & rew)
1061
        level1 <= 1'b0;
1062
endmodule
1063
//////////////////////////////////////////////////////////////////////
1064
////                                                              ////
1065
////  Versatile counter                                           ////
1066
////                                                              ////
1067
////  Description                                                 ////
1068
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1069
////  counter                                                     ////
1070
////                                                              ////
1071
////  To Do:                                                      ////
1072
////   - add LFSR with more taps                                  ////
1073
////                                                              ////
1074
////  Author(s):                                                  ////
1075
////      - Michael Unneback, unneback@opencores.org              ////
1076
////        ORSoC AB                                              ////
1077
////                                                              ////
1078
//////////////////////////////////////////////////////////////////////
1079
////                                                              ////
1080
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1081
////                                                              ////
1082
//// This source file may be used and distributed without         ////
1083
//// restriction provided that this copyright statement is not    ////
1084
//// removed from the file and that any derivative work contains  ////
1085
//// the original copyright notice and the associated disclaimer. ////
1086
////                                                              ////
1087
//// This source file is free software; you can redistribute it   ////
1088
//// and/or modify it under the terms of the GNU Lesser General   ////
1089
//// Public License as published by the Free Software Foundation; ////
1090
//// either version 2.1 of the License, or (at your option) any   ////
1091
//// later version.                                               ////
1092
////                                                              ////
1093
//// This source is distributed in the hope that it will be       ////
1094
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1095
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1096
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1097
//// details.                                                     ////
1098
////                                                              ////
1099
//// You should have received a copy of the GNU Lesser General    ////
1100
//// Public License along with this source; if not, download it   ////
1101
//// from http://www.opencores.org/lgpl.shtml                     ////
1102
////                                                              ////
1103
//////////////////////////////////////////////////////////////////////
1104
// binary counter
1105
module vl_cnt_bin_ce_rew_q_zq_l1 ( cke, rew, q, zq, level1, rst, clk);
1106
   parameter length = 4;
1107
   input cke;
1108
   input rew;
1109
   output [length:1] q;
1110
   output reg zq;
1111
   output reg level1;
1112
   input rst;
1113
   input clk;
1114
   parameter clear_value = 0;
1115
   parameter set_value = 1;
1116
   parameter wrap_value = 1;
1117
   parameter level1_value = 15;
1118 29 unneback
   wire clear;
1119 30 unneback
   assign clear = 1'b0;
1120 25 unneback
   reg  [length:1] qi;
1121
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1122
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1123
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1124
   assign q_next = rew ? q_next_rew : q_next_fw;
1125
   always @ (posedge clk or posedge rst)
1126
     if (rst)
1127
       qi <= {length{1'b0}};
1128
     else
1129
     if (cke)
1130
       qi <= q_next;
1131
   assign q = qi;
1132
   always @ (posedge clk or posedge rst)
1133
     if (rst)
1134
       zq <= 1'b1;
1135
     else
1136
     if (cke)
1137
       zq <= q_next == {length{1'b0}};
1138
    always @ (posedge clk or posedge rst)
1139
    if (rst)
1140
        level1 <= 1'b0;
1141
    else
1142
    if (cke)
1143 29 unneback
    if (clear)
1144
        level1 <= 1'b0;
1145
    else if (q_next == level1_value)
1146 25 unneback
        level1 <= 1'b1;
1147
    else if (qi == level1_value & rew)
1148
        level1 <= 1'b0;
1149
endmodule
1150
//////////////////////////////////////////////////////////////////////
1151
////                                                              ////
1152
////  Versatile counter                                           ////
1153
////                                                              ////
1154
////  Description                                                 ////
1155
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1156
////  counter                                                     ////
1157
////                                                              ////
1158
////  To Do:                                                      ////
1159
////   - add LFSR with more taps                                  ////
1160
////                                                              ////
1161
////  Author(s):                                                  ////
1162
////      - Michael Unneback, unneback@opencores.org              ////
1163
////        ORSoC AB                                              ////
1164
////                                                              ////
1165
//////////////////////////////////////////////////////////////////////
1166
////                                                              ////
1167
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1168
////                                                              ////
1169
//// This source file may be used and distributed without         ////
1170
//// restriction provided that this copyright statement is not    ////
1171
//// removed from the file and that any derivative work contains  ////
1172
//// the original copyright notice and the associated disclaimer. ////
1173
////                                                              ////
1174
//// This source file is free software; you can redistribute it   ////
1175
//// and/or modify it under the terms of the GNU Lesser General   ////
1176
//// Public License as published by the Free Software Foundation; ////
1177
//// either version 2.1 of the License, or (at your option) any   ////
1178
//// later version.                                               ////
1179
////                                                              ////
1180
//// This source is distributed in the hope that it will be       ////
1181
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1182
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1183
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1184
//// details.                                                     ////
1185
////                                                              ////
1186
//// You should have received a copy of the GNU Lesser General    ////
1187
//// Public License along with this source; if not, download it   ////
1188
//// from http://www.opencores.org/lgpl.shtml                     ////
1189
////                                                              ////
1190
//////////////////////////////////////////////////////////////////////
1191 6 unneback
// LFSR counter
1192 18 unneback
module vl_cnt_lfsr_zq ( zq, rst, clk);
1193 6 unneback
   parameter length = 4;
1194
   output reg zq;
1195
   input rst;
1196
   input clk;
1197
   parameter clear_value = 0;
1198
   parameter set_value = 1;
1199
   parameter wrap_value = 8;
1200
   parameter level1_value = 15;
1201
   reg  [length:1] qi;
1202
   reg lfsr_fb;
1203
   wire [length:1] q_next;
1204
   reg [32:1] polynom;
1205
   integer i;
1206
   always @ (qi)
1207
   begin
1208
        case (length)
1209
         2: polynom = 32'b11;                               // 0x3
1210
         3: polynom = 32'b110;                              // 0x6
1211
         4: polynom = 32'b1100;                             // 0xC
1212
         5: polynom = 32'b10100;                            // 0x14
1213
         6: polynom = 32'b110000;                           // 0x30
1214
         7: polynom = 32'b1100000;                          // 0x60
1215
         8: polynom = 32'b10111000;                         // 0xb8
1216
         9: polynom = 32'b100010000;                        // 0x110
1217
        10: polynom = 32'b1001000000;                       // 0x240
1218
        11: polynom = 32'b10100000000;                      // 0x500
1219
        12: polynom = 32'b100000101001;                     // 0x829
1220
        13: polynom = 32'b1000000001100;                    // 0x100C
1221
        14: polynom = 32'b10000000010101;                   // 0x2015
1222
        15: polynom = 32'b110000000000000;                  // 0x6000
1223
        16: polynom = 32'b1101000000001000;                 // 0xD008
1224
        17: polynom = 32'b10010000000000000;                // 0x12000
1225
        18: polynom = 32'b100000010000000000;               // 0x20400
1226
        19: polynom = 32'b1000000000000100011;              // 0x40023
1227
        20: polynom = 32'b10000010000000000000;             // 0x82000
1228
        21: polynom = 32'b101000000000000000000;            // 0x140000
1229
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1230
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1231
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1232
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1233
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1234
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1235
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1236
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1237
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1238
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1239
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1240
        default: polynom = 32'b0;
1241
        endcase
1242
        lfsr_fb = qi[length];
1243
        for (i=length-1; i>=1; i=i-1) begin
1244
            if (polynom[i])
1245
                lfsr_fb = lfsr_fb  ~^ qi[i];
1246
        end
1247
    end
1248
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1249
   always @ (posedge clk or posedge rst)
1250
     if (rst)
1251
       qi <= {length{1'b0}};
1252
     else
1253
       qi <= q_next;
1254
   always @ (posedge clk or posedge rst)
1255
     if (rst)
1256
       zq <= 1'b1;
1257
     else
1258
       zq <= q_next == {length{1'b0}};
1259
endmodule
1260
//////////////////////////////////////////////////////////////////////
1261
////                                                              ////
1262
////  Versatile counter                                           ////
1263
////                                                              ////
1264
////  Description                                                 ////
1265
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1266
////  counter                                                     ////
1267
////                                                              ////
1268
////  To Do:                                                      ////
1269
////   - add LFSR with more taps                                  ////
1270
////                                                              ////
1271
////  Author(s):                                                  ////
1272
////      - Michael Unneback, unneback@opencores.org              ////
1273
////        ORSoC AB                                              ////
1274
////                                                              ////
1275
//////////////////////////////////////////////////////////////////////
1276
////                                                              ////
1277
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1278
////                                                              ////
1279
//// This source file may be used and distributed without         ////
1280
//// restriction provided that this copyright statement is not    ////
1281
//// removed from the file and that any derivative work contains  ////
1282
//// the original copyright notice and the associated disclaimer. ////
1283
////                                                              ////
1284
//// This source file is free software; you can redistribute it   ////
1285
//// and/or modify it under the terms of the GNU Lesser General   ////
1286
//// Public License as published by the Free Software Foundation; ////
1287
//// either version 2.1 of the License, or (at your option) any   ////
1288
//// later version.                                               ////
1289
////                                                              ////
1290
//// This source is distributed in the hope that it will be       ////
1291
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1292
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1293
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1294
//// details.                                                     ////
1295
////                                                              ////
1296
//// You should have received a copy of the GNU Lesser General    ////
1297
//// Public License along with this source; if not, download it   ////
1298
//// from http://www.opencores.org/lgpl.shtml                     ////
1299
////                                                              ////
1300
//////////////////////////////////////////////////////////////////////
1301
// LFSR counter
1302 18 unneback
module vl_cnt_lfsr_ce_zq ( cke, zq, rst, clk);
1303 6 unneback
   parameter length = 4;
1304
   input cke;
1305
   output reg zq;
1306
   input rst;
1307
   input clk;
1308
   parameter clear_value = 0;
1309
   parameter set_value = 1;
1310
   parameter wrap_value = 8;
1311
   parameter level1_value = 15;
1312
   reg  [length:1] qi;
1313
   reg lfsr_fb;
1314
   wire [length:1] q_next;
1315
   reg [32:1] polynom;
1316
   integer i;
1317
   always @ (qi)
1318
   begin
1319
        case (length)
1320
         2: polynom = 32'b11;                               // 0x3
1321
         3: polynom = 32'b110;                              // 0x6
1322
         4: polynom = 32'b1100;                             // 0xC
1323
         5: polynom = 32'b10100;                            // 0x14
1324
         6: polynom = 32'b110000;                           // 0x30
1325
         7: polynom = 32'b1100000;                          // 0x60
1326
         8: polynom = 32'b10111000;                         // 0xb8
1327
         9: polynom = 32'b100010000;                        // 0x110
1328
        10: polynom = 32'b1001000000;                       // 0x240
1329
        11: polynom = 32'b10100000000;                      // 0x500
1330
        12: polynom = 32'b100000101001;                     // 0x829
1331
        13: polynom = 32'b1000000001100;                    // 0x100C
1332
        14: polynom = 32'b10000000010101;                   // 0x2015
1333
        15: polynom = 32'b110000000000000;                  // 0x6000
1334
        16: polynom = 32'b1101000000001000;                 // 0xD008
1335
        17: polynom = 32'b10010000000000000;                // 0x12000
1336
        18: polynom = 32'b100000010000000000;               // 0x20400
1337
        19: polynom = 32'b1000000000000100011;              // 0x40023
1338
        20: polynom = 32'b10000010000000000000;             // 0x82000
1339
        21: polynom = 32'b101000000000000000000;            // 0x140000
1340
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1341
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1342
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1343
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1344
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1345
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1346
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1347
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1348
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1349
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1350
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1351
        default: polynom = 32'b0;
1352
        endcase
1353
        lfsr_fb = qi[length];
1354
        for (i=length-1; i>=1; i=i-1) begin
1355
            if (polynom[i])
1356
                lfsr_fb = lfsr_fb  ~^ qi[i];
1357
        end
1358
    end
1359
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1360
   always @ (posedge clk or posedge rst)
1361
     if (rst)
1362
       qi <= {length{1'b0}};
1363
     else
1364
     if (cke)
1365
       qi <= q_next;
1366
   always @ (posedge clk or posedge rst)
1367
     if (rst)
1368
       zq <= 1'b1;
1369
     else
1370
     if (cke)
1371
       zq <= q_next == {length{1'b0}};
1372
endmodule
1373
//////////////////////////////////////////////////////////////////////
1374
////                                                              ////
1375
////  Versatile counter                                           ////
1376
////                                                              ////
1377
////  Description                                                 ////
1378
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1379
////  counter                                                     ////
1380
////                                                              ////
1381
////  To Do:                                                      ////
1382
////   - add LFSR with more taps                                  ////
1383
////                                                              ////
1384
////  Author(s):                                                  ////
1385
////      - Michael Unneback, unneback@opencores.org              ////
1386
////        ORSoC AB                                              ////
1387
////                                                              ////
1388
//////////////////////////////////////////////////////////////////////
1389
////                                                              ////
1390
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1391
////                                                              ////
1392
//// This source file may be used and distributed without         ////
1393
//// restriction provided that this copyright statement is not    ////
1394
//// removed from the file and that any derivative work contains  ////
1395
//// the original copyright notice and the associated disclaimer. ////
1396
////                                                              ////
1397
//// This source file is free software; you can redistribute it   ////
1398
//// and/or modify it under the terms of the GNU Lesser General   ////
1399
//// Public License as published by the Free Software Foundation; ////
1400
//// either version 2.1 of the License, or (at your option) any   ////
1401
//// later version.                                               ////
1402
////                                                              ////
1403
//// This source is distributed in the hope that it will be       ////
1404
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1405
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1406
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1407
//// details.                                                     ////
1408
////                                                              ////
1409
//// You should have received a copy of the GNU Lesser General    ////
1410
//// Public License along with this source; if not, download it   ////
1411
//// from http://www.opencores.org/lgpl.shtml                     ////
1412
////                                                              ////
1413
//////////////////////////////////////////////////////////////////////
1414
// LFSR counter
1415 27 unneback
module vl_cnt_lfsr_ce_q ( cke, q, rst, clk);
1416
   parameter length = 4;
1417
   input cke;
1418
   output [length:1] q;
1419
   input rst;
1420
   input clk;
1421
   parameter clear_value = 0;
1422
   parameter set_value = 1;
1423
   parameter wrap_value = 8;
1424
   parameter level1_value = 15;
1425
   reg  [length:1] qi;
1426
   reg lfsr_fb;
1427
   wire [length:1] q_next;
1428
   reg [32:1] polynom;
1429
   integer i;
1430
   always @ (qi)
1431
   begin
1432
        case (length)
1433
         2: polynom = 32'b11;                               // 0x3
1434
         3: polynom = 32'b110;                              // 0x6
1435
         4: polynom = 32'b1100;                             // 0xC
1436
         5: polynom = 32'b10100;                            // 0x14
1437
         6: polynom = 32'b110000;                           // 0x30
1438
         7: polynom = 32'b1100000;                          // 0x60
1439
         8: polynom = 32'b10111000;                         // 0xb8
1440
         9: polynom = 32'b100010000;                        // 0x110
1441
        10: polynom = 32'b1001000000;                       // 0x240
1442
        11: polynom = 32'b10100000000;                      // 0x500
1443
        12: polynom = 32'b100000101001;                     // 0x829
1444
        13: polynom = 32'b1000000001100;                    // 0x100C
1445
        14: polynom = 32'b10000000010101;                   // 0x2015
1446
        15: polynom = 32'b110000000000000;                  // 0x6000
1447
        16: polynom = 32'b1101000000001000;                 // 0xD008
1448
        17: polynom = 32'b10010000000000000;                // 0x12000
1449
        18: polynom = 32'b100000010000000000;               // 0x20400
1450
        19: polynom = 32'b1000000000000100011;              // 0x40023
1451
        20: polynom = 32'b10000010000000000000;             // 0x82000
1452
        21: polynom = 32'b101000000000000000000;            // 0x140000
1453
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1454
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1455
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1456
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1457
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1458
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1459
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1460
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1461
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1462
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1463
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1464
        default: polynom = 32'b0;
1465
        endcase
1466
        lfsr_fb = qi[length];
1467
        for (i=length-1; i>=1; i=i-1) begin
1468
            if (polynom[i])
1469
                lfsr_fb = lfsr_fb  ~^ qi[i];
1470
        end
1471
    end
1472
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1473
   always @ (posedge clk or posedge rst)
1474
     if (rst)
1475
       qi <= {length{1'b0}};
1476
     else
1477
     if (cke)
1478
       qi <= q_next;
1479
   assign q = qi;
1480
endmodule
1481
//////////////////////////////////////////////////////////////////////
1482
////                                                              ////
1483
////  Versatile counter                                           ////
1484
////                                                              ////
1485
////  Description                                                 ////
1486
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1487
////  counter                                                     ////
1488
////                                                              ////
1489
////  To Do:                                                      ////
1490
////   - add LFSR with more taps                                  ////
1491
////                                                              ////
1492
////  Author(s):                                                  ////
1493
////      - Michael Unneback, unneback@opencores.org              ////
1494
////        ORSoC AB                                              ////
1495
////                                                              ////
1496
//////////////////////////////////////////////////////////////////////
1497
////                                                              ////
1498
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1499
////                                                              ////
1500
//// This source file may be used and distributed without         ////
1501
//// restriction provided that this copyright statement is not    ////
1502
//// removed from the file and that any derivative work contains  ////
1503
//// the original copyright notice and the associated disclaimer. ////
1504
////                                                              ////
1505
//// This source file is free software; you can redistribute it   ////
1506
//// and/or modify it under the terms of the GNU Lesser General   ////
1507
//// Public License as published by the Free Software Foundation; ////
1508
//// either version 2.1 of the License, or (at your option) any   ////
1509
//// later version.                                               ////
1510
////                                                              ////
1511
//// This source is distributed in the hope that it will be       ////
1512
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1513
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1514
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1515
//// details.                                                     ////
1516
////                                                              ////
1517
//// You should have received a copy of the GNU Lesser General    ////
1518
//// Public License along with this source; if not, download it   ////
1519
//// from http://www.opencores.org/lgpl.shtml                     ////
1520
////                                                              ////
1521
//////////////////////////////////////////////////////////////////////
1522
// LFSR counter
1523
module vl_cnt_lfsr_ce_clear_q ( clear, cke, q, rst, clk);
1524
   parameter length = 4;
1525
   input clear;
1526
   input cke;
1527
   output [length:1] q;
1528
   input rst;
1529
   input clk;
1530
   parameter clear_value = 0;
1531
   parameter set_value = 1;
1532
   parameter wrap_value = 8;
1533
   parameter level1_value = 15;
1534
   reg  [length:1] qi;
1535
   reg lfsr_fb;
1536
   wire [length:1] q_next;
1537
   reg [32:1] polynom;
1538
   integer i;
1539
   always @ (qi)
1540
   begin
1541
        case (length)
1542
         2: polynom = 32'b11;                               // 0x3
1543
         3: polynom = 32'b110;                              // 0x6
1544
         4: polynom = 32'b1100;                             // 0xC
1545
         5: polynom = 32'b10100;                            // 0x14
1546
         6: polynom = 32'b110000;                           // 0x30
1547
         7: polynom = 32'b1100000;                          // 0x60
1548
         8: polynom = 32'b10111000;                         // 0xb8
1549
         9: polynom = 32'b100010000;                        // 0x110
1550
        10: polynom = 32'b1001000000;                       // 0x240
1551
        11: polynom = 32'b10100000000;                      // 0x500
1552
        12: polynom = 32'b100000101001;                     // 0x829
1553
        13: polynom = 32'b1000000001100;                    // 0x100C
1554
        14: polynom = 32'b10000000010101;                   // 0x2015
1555
        15: polynom = 32'b110000000000000;                  // 0x6000
1556
        16: polynom = 32'b1101000000001000;                 // 0xD008
1557
        17: polynom = 32'b10010000000000000;                // 0x12000
1558
        18: polynom = 32'b100000010000000000;               // 0x20400
1559
        19: polynom = 32'b1000000000000100011;              // 0x40023
1560
        20: polynom = 32'b10000010000000000000;             // 0x82000
1561
        21: polynom = 32'b101000000000000000000;            // 0x140000
1562
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1563
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1564
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1565
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1566
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1567
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1568
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1569
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1570
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1571
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1572
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1573
        default: polynom = 32'b0;
1574
        endcase
1575
        lfsr_fb = qi[length];
1576
        for (i=length-1; i>=1; i=i-1) begin
1577
            if (polynom[i])
1578
                lfsr_fb = lfsr_fb  ~^ qi[i];
1579
        end
1580
    end
1581
   assign q_next =  clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1582
   always @ (posedge clk or posedge rst)
1583
     if (rst)
1584
       qi <= {length{1'b0}};
1585
     else
1586
     if (cke)
1587
       qi <= q_next;
1588
   assign q = qi;
1589
endmodule
1590
//////////////////////////////////////////////////////////////////////
1591
////                                                              ////
1592
////  Versatile counter                                           ////
1593
////                                                              ////
1594
////  Description                                                 ////
1595
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1596
////  counter                                                     ////
1597
////                                                              ////
1598
////  To Do:                                                      ////
1599
////   - add LFSR with more taps                                  ////
1600
////                                                              ////
1601
////  Author(s):                                                  ////
1602
////      - Michael Unneback, unneback@opencores.org              ////
1603
////        ORSoC AB                                              ////
1604
////                                                              ////
1605
//////////////////////////////////////////////////////////////////////
1606
////                                                              ////
1607
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1608
////                                                              ////
1609
//// This source file may be used and distributed without         ////
1610
//// restriction provided that this copyright statement is not    ////
1611
//// removed from the file and that any derivative work contains  ////
1612
//// the original copyright notice and the associated disclaimer. ////
1613
////                                                              ////
1614
//// This source file is free software; you can redistribute it   ////
1615
//// and/or modify it under the terms of the GNU Lesser General   ////
1616
//// Public License as published by the Free Software Foundation; ////
1617
//// either version 2.1 of the License, or (at your option) any   ////
1618
//// later version.                                               ////
1619
////                                                              ////
1620
//// This source is distributed in the hope that it will be       ////
1621
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1622
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1623
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1624
//// details.                                                     ////
1625
////                                                              ////
1626
//// You should have received a copy of the GNU Lesser General    ////
1627
//// Public License along with this source; if not, download it   ////
1628
//// from http://www.opencores.org/lgpl.shtml                     ////
1629
////                                                              ////
1630
//////////////////////////////////////////////////////////////////////
1631
// LFSR counter
1632 22 unneback
module vl_cnt_lfsr_ce_q_zq ( cke, q, zq, rst, clk);
1633
   parameter length = 4;
1634
   input cke;
1635
   output [length:1] q;
1636
   output reg zq;
1637
   input rst;
1638
   input clk;
1639
   parameter clear_value = 0;
1640
   parameter set_value = 1;
1641
   parameter wrap_value = 8;
1642
   parameter level1_value = 15;
1643
   reg  [length:1] qi;
1644
   reg lfsr_fb;
1645
   wire [length:1] q_next;
1646
   reg [32:1] polynom;
1647
   integer i;
1648
   always @ (qi)
1649
   begin
1650
        case (length)
1651
         2: polynom = 32'b11;                               // 0x3
1652
         3: polynom = 32'b110;                              // 0x6
1653
         4: polynom = 32'b1100;                             // 0xC
1654
         5: polynom = 32'b10100;                            // 0x14
1655
         6: polynom = 32'b110000;                           // 0x30
1656
         7: polynom = 32'b1100000;                          // 0x60
1657
         8: polynom = 32'b10111000;                         // 0xb8
1658
         9: polynom = 32'b100010000;                        // 0x110
1659
        10: polynom = 32'b1001000000;                       // 0x240
1660
        11: polynom = 32'b10100000000;                      // 0x500
1661
        12: polynom = 32'b100000101001;                     // 0x829
1662
        13: polynom = 32'b1000000001100;                    // 0x100C
1663
        14: polynom = 32'b10000000010101;                   // 0x2015
1664
        15: polynom = 32'b110000000000000;                  // 0x6000
1665
        16: polynom = 32'b1101000000001000;                 // 0xD008
1666
        17: polynom = 32'b10010000000000000;                // 0x12000
1667
        18: polynom = 32'b100000010000000000;               // 0x20400
1668
        19: polynom = 32'b1000000000000100011;              // 0x40023
1669
        20: polynom = 32'b10000010000000000000;             // 0x82000
1670
        21: polynom = 32'b101000000000000000000;            // 0x140000
1671
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1672
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1673
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1674
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1675
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1676
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1677
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1678
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1679
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1680
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1681
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1682
        default: polynom = 32'b0;
1683
        endcase
1684
        lfsr_fb = qi[length];
1685
        for (i=length-1; i>=1; i=i-1) begin
1686
            if (polynom[i])
1687
                lfsr_fb = lfsr_fb  ~^ qi[i];
1688
        end
1689
    end
1690
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1691
   always @ (posedge clk or posedge rst)
1692
     if (rst)
1693
       qi <= {length{1'b0}};
1694
     else
1695
     if (cke)
1696
       qi <= q_next;
1697
   assign q = qi;
1698
   always @ (posedge clk or posedge rst)
1699
     if (rst)
1700
       zq <= 1'b1;
1701
     else
1702
     if (cke)
1703
       zq <= q_next == {length{1'b0}};
1704
endmodule
1705
//////////////////////////////////////////////////////////////////////
1706
////                                                              ////
1707
////  Versatile counter                                           ////
1708
////                                                              ////
1709
////  Description                                                 ////
1710
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1711
////  counter                                                     ////
1712
////                                                              ////
1713
////  To Do:                                                      ////
1714
////   - add LFSR with more taps                                  ////
1715
////                                                              ////
1716
////  Author(s):                                                  ////
1717
////      - Michael Unneback, unneback@opencores.org              ////
1718
////        ORSoC AB                                              ////
1719
////                                                              ////
1720
//////////////////////////////////////////////////////////////////////
1721
////                                                              ////
1722
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1723
////                                                              ////
1724
//// This source file may be used and distributed without         ////
1725
//// restriction provided that this copyright statement is not    ////
1726
//// removed from the file and that any derivative work contains  ////
1727
//// the original copyright notice and the associated disclaimer. ////
1728
////                                                              ////
1729
//// This source file is free software; you can redistribute it   ////
1730
//// and/or modify it under the terms of the GNU Lesser General   ////
1731
//// Public License as published by the Free Software Foundation; ////
1732
//// either version 2.1 of the License, or (at your option) any   ////
1733
//// later version.                                               ////
1734
////                                                              ////
1735
//// This source is distributed in the hope that it will be       ////
1736
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1737
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1738
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1739
//// details.                                                     ////
1740
////                                                              ////
1741
//// You should have received a copy of the GNU Lesser General    ////
1742
//// Public License along with this source; if not, download it   ////
1743
//// from http://www.opencores.org/lgpl.shtml                     ////
1744
////                                                              ////
1745
//////////////////////////////////////////////////////////////////////
1746
// LFSR counter
1747 18 unneback
module vl_cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk);
1748 6 unneback
   parameter length = 4;
1749
   input cke;
1750
   input rew;
1751
   output reg level1;
1752
   input rst;
1753
   input clk;
1754
   parameter clear_value = 0;
1755
   parameter set_value = 1;
1756
   parameter wrap_value = 8;
1757
   parameter level1_value = 15;
1758 29 unneback
   wire clear;
1759 30 unneback
   assign clear = 1'b0;
1760 6 unneback
   reg  [length:1] qi;
1761
   reg lfsr_fb, lfsr_fb_rew;
1762
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1763
   reg [32:1] polynom_rew;
1764
   integer j;
1765
   reg [32:1] polynom;
1766
   integer i;
1767
   always @ (qi)
1768
   begin
1769
        case (length)
1770
         2: polynom = 32'b11;                               // 0x3
1771
         3: polynom = 32'b110;                              // 0x6
1772
         4: polynom = 32'b1100;                             // 0xC
1773
         5: polynom = 32'b10100;                            // 0x14
1774
         6: polynom = 32'b110000;                           // 0x30
1775
         7: polynom = 32'b1100000;                          // 0x60
1776
         8: polynom = 32'b10111000;                         // 0xb8
1777
         9: polynom = 32'b100010000;                        // 0x110
1778
        10: polynom = 32'b1001000000;                       // 0x240
1779
        11: polynom = 32'b10100000000;                      // 0x500
1780
        12: polynom = 32'b100000101001;                     // 0x829
1781
        13: polynom = 32'b1000000001100;                    // 0x100C
1782
        14: polynom = 32'b10000000010101;                   // 0x2015
1783
        15: polynom = 32'b110000000000000;                  // 0x6000
1784
        16: polynom = 32'b1101000000001000;                 // 0xD008
1785
        17: polynom = 32'b10010000000000000;                // 0x12000
1786
        18: polynom = 32'b100000010000000000;               // 0x20400
1787
        19: polynom = 32'b1000000000000100011;              // 0x40023
1788
        20: polynom = 32'b10000010000000000000;             // 0x82000
1789
        21: polynom = 32'b101000000000000000000;            // 0x140000
1790
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1791
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1792
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1793
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1794
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1795
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1796
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1797
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1798
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1799
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1800
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1801
        default: polynom = 32'b0;
1802
        endcase
1803
        lfsr_fb = qi[length];
1804
        for (i=length-1; i>=1; i=i-1) begin
1805
            if (polynom[i])
1806
                lfsr_fb = lfsr_fb  ~^ qi[i];
1807
        end
1808
    end
1809
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1810
   always @ (qi)
1811
   begin
1812
        case (length)
1813
         2: polynom_rew = 32'b11;
1814
         3: polynom_rew = 32'b110;
1815
         4: polynom_rew = 32'b1100;
1816
         5: polynom_rew = 32'b10100;
1817
         6: polynom_rew = 32'b110000;
1818
         7: polynom_rew = 32'b1100000;
1819
         8: polynom_rew = 32'b10111000;
1820
         9: polynom_rew = 32'b100010000;
1821
        10: polynom_rew = 32'b1001000000;
1822
        11: polynom_rew = 32'b10100000000;
1823
        12: polynom_rew = 32'b100000101001;
1824
        13: polynom_rew = 32'b1000000001100;
1825
        14: polynom_rew = 32'b10000000010101;
1826
        15: polynom_rew = 32'b110000000000000;
1827
        16: polynom_rew = 32'b1101000000001000;
1828
        17: polynom_rew = 32'b10010000000000000;
1829
        18: polynom_rew = 32'b100000010000000000;
1830
        19: polynom_rew = 32'b1000000000000100011;
1831
        20: polynom_rew = 32'b10000010000000000000;
1832
        21: polynom_rew = 32'b101000000000000000000;
1833
        22: polynom_rew = 32'b1100000000000000000000;
1834
        23: polynom_rew = 32'b10000100000000000000000;
1835
        24: polynom_rew = 32'b111000010000000000000000;
1836
        25: polynom_rew = 32'b1001000000000000000000000;
1837
        26: polynom_rew = 32'b10000000000000000000100011;
1838
        27: polynom_rew = 32'b100000000000000000000010011;
1839
        28: polynom_rew = 32'b1100100000000000000000000000;
1840
        29: polynom_rew = 32'b10100000000000000000000000000;
1841
        30: polynom_rew = 32'b100000000000000000000000101001;
1842
        31: polynom_rew = 32'b1001000000000000000000000000000;
1843
        32: polynom_rew = 32'b10000000001000000000000000000011;
1844
        default: polynom_rew = 32'b0;
1845
        endcase
1846
        // rotate left
1847
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
1848
        lfsr_fb_rew = qi[length];
1849
        for (i=length-1; i>=1; i=i-1) begin
1850
            if (polynom_rew[i])
1851
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
1852
        end
1853
    end
1854
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
1855
   assign q_next = rew ? q_next_rew : q_next_fw;
1856
   always @ (posedge clk or posedge rst)
1857
     if (rst)
1858
       qi <= {length{1'b0}};
1859
     else
1860
     if (cke)
1861
       qi <= q_next;
1862
    always @ (posedge clk or posedge rst)
1863
    if (rst)
1864
        level1 <= 1'b0;
1865
    else
1866
    if (cke)
1867 29 unneback
    if (clear)
1868
        level1 <= 1'b0;
1869
    else if (q_next == level1_value)
1870 6 unneback
        level1 <= 1'b1;
1871
    else if (qi == level1_value & rew)
1872
        level1 <= 1'b0;
1873
endmodule
1874
//////////////////////////////////////////////////////////////////////
1875
////                                                              ////
1876
////  Versatile counter                                           ////
1877
////                                                              ////
1878
////  Description                                                 ////
1879
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1880
////  counter                                                     ////
1881
////                                                              ////
1882
////  To Do:                                                      ////
1883
////   - add LFSR with more taps                                  ////
1884
////                                                              ////
1885
////  Author(s):                                                  ////
1886
////      - Michael Unneback, unneback@opencores.org              ////
1887
////        ORSoC AB                                              ////
1888
////                                                              ////
1889
//////////////////////////////////////////////////////////////////////
1890
////                                                              ////
1891
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1892
////                                                              ////
1893
//// This source file may be used and distributed without         ////
1894
//// restriction provided that this copyright statement is not    ////
1895
//// removed from the file and that any derivative work contains  ////
1896
//// the original copyright notice and the associated disclaimer. ////
1897
////                                                              ////
1898
//// This source file is free software; you can redistribute it   ////
1899
//// and/or modify it under the terms of the GNU Lesser General   ////
1900
//// Public License as published by the Free Software Foundation; ////
1901
//// either version 2.1 of the License, or (at your option) any   ////
1902
//// later version.                                               ////
1903
////                                                              ////
1904
//// This source is distributed in the hope that it will be       ////
1905
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1906
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1907
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1908
//// details.                                                     ////
1909
////                                                              ////
1910
//// You should have received a copy of the GNU Lesser General    ////
1911
//// Public License along with this source; if not, download it   ////
1912
//// from http://www.opencores.org/lgpl.shtml                     ////
1913
////                                                              ////
1914
//////////////////////////////////////////////////////////////////////
1915
// GRAY counter
1916 18 unneback
module vl_cnt_gray ( q, rst, clk);
1917 6 unneback
   parameter length = 4;
1918
   output reg [length:1] q;
1919
   input rst;
1920
   input clk;
1921
   parameter clear_value = 0;
1922
   parameter set_value = 1;
1923
   parameter wrap_value = 8;
1924
   parameter level1_value = 15;
1925
   reg  [length:1] qi;
1926
   wire [length:1] q_next;
1927
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1928
   always @ (posedge clk or posedge rst)
1929
     if (rst)
1930
       qi <= {length{1'b0}};
1931
     else
1932
       qi <= q_next;
1933
   always @ (posedge clk or posedge rst)
1934
     if (rst)
1935
       q <= {length{1'b0}};
1936
     else
1937
         q <= (q_next>>1) ^ q_next;
1938
endmodule
1939
//////////////////////////////////////////////////////////////////////
1940
////                                                              ////
1941
////  Versatile counter                                           ////
1942
////                                                              ////
1943
////  Description                                                 ////
1944
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1945
////  counter                                                     ////
1946
////                                                              ////
1947
////  To Do:                                                      ////
1948
////   - add LFSR with more taps                                  ////
1949
////                                                              ////
1950
////  Author(s):                                                  ////
1951
////      - Michael Unneback, unneback@opencores.org              ////
1952
////        ORSoC AB                                              ////
1953
////                                                              ////
1954
//////////////////////////////////////////////////////////////////////
1955
////                                                              ////
1956
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1957
////                                                              ////
1958
//// This source file may be used and distributed without         ////
1959
//// restriction provided that this copyright statement is not    ////
1960
//// removed from the file and that any derivative work contains  ////
1961
//// the original copyright notice and the associated disclaimer. ////
1962
////                                                              ////
1963
//// This source file is free software; you can redistribute it   ////
1964
//// and/or modify it under the terms of the GNU Lesser General   ////
1965
//// Public License as published by the Free Software Foundation; ////
1966
//// either version 2.1 of the License, or (at your option) any   ////
1967
//// later version.                                               ////
1968
////                                                              ////
1969
//// This source is distributed in the hope that it will be       ////
1970
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1971
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1972
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1973
//// details.                                                     ////
1974
////                                                              ////
1975
//// You should have received a copy of the GNU Lesser General    ////
1976
//// Public License along with this source; if not, download it   ////
1977
//// from http://www.opencores.org/lgpl.shtml                     ////
1978
////                                                              ////
1979
//////////////////////////////////////////////////////////////////////
1980
// GRAY counter
1981 18 unneback
module vl_cnt_gray_ce ( cke, q, rst, clk);
1982 6 unneback
   parameter length = 4;
1983
   input cke;
1984
   output reg [length:1] q;
1985
   input rst;
1986
   input clk;
1987
   parameter clear_value = 0;
1988
   parameter set_value = 1;
1989
   parameter wrap_value = 8;
1990
   parameter level1_value = 15;
1991
   reg  [length:1] qi;
1992
   wire [length:1] q_next;
1993
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1994
   always @ (posedge clk or posedge rst)
1995
     if (rst)
1996
       qi <= {length{1'b0}};
1997
     else
1998
     if (cke)
1999
       qi <= q_next;
2000
   always @ (posedge clk or posedge rst)
2001
     if (rst)
2002
       q <= {length{1'b0}};
2003
     else
2004
       if (cke)
2005
         q <= (q_next>>1) ^ q_next;
2006
endmodule
2007
//////////////////////////////////////////////////////////////////////
2008
////                                                              ////
2009
////  Versatile counter                                           ////
2010
////                                                              ////
2011
////  Description                                                 ////
2012
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2013
////  counter                                                     ////
2014
////                                                              ////
2015
////  To Do:                                                      ////
2016
////   - add LFSR with more taps                                  ////
2017
////                                                              ////
2018
////  Author(s):                                                  ////
2019
////      - Michael Unneback, unneback@opencores.org              ////
2020
////        ORSoC AB                                              ////
2021
////                                                              ////
2022
//////////////////////////////////////////////////////////////////////
2023
////                                                              ////
2024
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2025
////                                                              ////
2026
//// This source file may be used and distributed without         ////
2027
//// restriction provided that this copyright statement is not    ////
2028
//// removed from the file and that any derivative work contains  ////
2029
//// the original copyright notice and the associated disclaimer. ////
2030
////                                                              ////
2031
//// This source file is free software; you can redistribute it   ////
2032
//// and/or modify it under the terms of the GNU Lesser General   ////
2033
//// Public License as published by the Free Software Foundation; ////
2034
//// either version 2.1 of the License, or (at your option) any   ////
2035
//// later version.                                               ////
2036
////                                                              ////
2037
//// This source is distributed in the hope that it will be       ////
2038
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2039
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2040
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2041
//// details.                                                     ////
2042
////                                                              ////
2043
//// You should have received a copy of the GNU Lesser General    ////
2044
//// Public License along with this source; if not, download it   ////
2045
//// from http://www.opencores.org/lgpl.shtml                     ////
2046
////                                                              ////
2047
//////////////////////////////////////////////////////////////////////
2048
// GRAY counter
2049 18 unneback
module vl_cnt_gray_ce_bin ( cke, q, q_bin, rst, clk);
2050 6 unneback
   parameter length = 4;
2051
   input cke;
2052
   output reg [length:1] q;
2053
   output [length:1] q_bin;
2054
   input rst;
2055
   input clk;
2056
   parameter clear_value = 0;
2057
   parameter set_value = 1;
2058
   parameter wrap_value = 8;
2059
   parameter level1_value = 15;
2060
   reg  [length:1] qi;
2061
   wire [length:1] q_next;
2062
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2063
   always @ (posedge clk or posedge rst)
2064
     if (rst)
2065
       qi <= {length{1'b0}};
2066
     else
2067
     if (cke)
2068
       qi <= q_next;
2069
   always @ (posedge clk or posedge rst)
2070
     if (rst)
2071
       q <= {length{1'b0}};
2072
     else
2073
       if (cke)
2074
         q <= (q_next>>1) ^ q_next;
2075
   assign q_bin = qi;
2076
endmodule
2077
//////////////////////////////////////////////////////////////////////
2078
////                                                              ////
2079
////  Versatile library, counters                                 ////
2080
////                                                              ////
2081
////  Description                                                 ////
2082
////  counters                                                    ////
2083
////                                                              ////
2084
////                                                              ////
2085
////  To Do:                                                      ////
2086
////   - add more counters                                        ////
2087
////                                                              ////
2088
////  Author(s):                                                  ////
2089
////      - Michael Unneback, unneback@opencores.org              ////
2090
////        ORSoC AB                                              ////
2091
////                                                              ////
2092
//////////////////////////////////////////////////////////////////////
2093
////                                                              ////
2094
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2095
////                                                              ////
2096
//// This source file may be used and distributed without         ////
2097
//// restriction provided that this copyright statement is not    ////
2098
//// removed from the file and that any derivative work contains  ////
2099
//// the original copyright notice and the associated disclaimer. ////
2100
////                                                              ////
2101
//// This source file is free software; you can redistribute it   ////
2102
//// and/or modify it under the terms of the GNU Lesser General   ////
2103
//// Public License as published by the Free Software Foundation; ////
2104
//// either version 2.1 of the License, or (at your option) any   ////
2105
//// later version.                                               ////
2106
////                                                              ////
2107
//// This source is distributed in the hope that it will be       ////
2108
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2109
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2110
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2111
//// details.                                                     ////
2112
////                                                              ////
2113
//// You should have received a copy of the GNU Lesser General    ////
2114
//// Public License along with this source; if not, download it   ////
2115
//// from http://www.opencores.org/lgpl.shtml                     ////
2116
////                                                              ////
2117
//////////////////////////////////////////////////////////////////////
2118 18 unneback
module vl_cnt_shreg_wrap ( q, rst, clk);
2119 6 unneback
   parameter length = 4;
2120
   output reg [0:length-1] q;
2121
   input rst;
2122
   input clk;
2123
    always @ (posedge clk or posedge rst)
2124
    if (rst)
2125
        q <= {1'b1,{length-1{1'b0}}};
2126
    else
2127
        q <= {q[length-1],q[0:length-2]};
2128
endmodule
2129 18 unneback
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
2130 6 unneback
   parameter length = 4;
2131
   input cke;
2132
   output reg [0:length-1] q;
2133
   input rst;
2134
   input clk;
2135
    always @ (posedge clk or posedge rst)
2136
    if (rst)
2137
        q <= {1'b1,{length-1{1'b0}}};
2138
    else
2139
        if (cke)
2140
            q <= {q[length-1],q[0:length-2]};
2141
endmodule
2142 18 unneback
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
2143 6 unneback
   parameter length = 4;
2144
   input cke, clear;
2145
   output reg [0:length-1] q;
2146
   input rst;
2147
   input clk;
2148
    always @ (posedge clk or posedge rst)
2149
    if (rst)
2150
        q <= {1'b1,{length-1{1'b0}}};
2151
    else
2152
        if (cke)
2153
            if (clear)
2154
                q <= {1'b1,{length-1{1'b0}}};
2155
            else
2156
                q <= q >> 1;
2157
endmodule
2158 18 unneback
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
2159 6 unneback
   parameter length = 4;
2160
   input cke, clear;
2161
   output reg [0:length-1] q;
2162
   input rst;
2163
   input clk;
2164
    always @ (posedge clk or posedge rst)
2165
    if (rst)
2166
        q <= {1'b1,{length-1{1'b0}}};
2167
    else
2168
        if (cke)
2169
            if (clear)
2170
                q <= {1'b1,{length-1{1'b0}}};
2171
            else
2172
            q <= {q[length-1],q[0:length-2]};
2173
endmodule
2174
//////////////////////////////////////////////////////////////////////
2175
////                                                              ////
2176
////  Versatile library, memories                                 ////
2177
////                                                              ////
2178
////  Description                                                 ////
2179
////  memories                                                    ////
2180
////                                                              ////
2181
////                                                              ////
2182
////  To Do:                                                      ////
2183
////   - add more memory types                                    ////
2184
////                                                              ////
2185
////  Author(s):                                                  ////
2186
////      - Michael Unneback, unneback@opencores.org              ////
2187
////        ORSoC AB                                              ////
2188
////                                                              ////
2189
//////////////////////////////////////////////////////////////////////
2190
////                                                              ////
2191
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2192
////                                                              ////
2193
//// This source file may be used and distributed without         ////
2194
//// restriction provided that this copyright statement is not    ////
2195
//// removed from the file and that any derivative work contains  ////
2196
//// the original copyright notice and the associated disclaimer. ////
2197
////                                                              ////
2198
//// This source file is free software; you can redistribute it   ////
2199
//// and/or modify it under the terms of the GNU Lesser General   ////
2200
//// Public License as published by the Free Software Foundation; ////
2201
//// either version 2.1 of the License, or (at your option) any   ////
2202
//// later version.                                               ////
2203
////                                                              ////
2204
//// This source is distributed in the hope that it will be       ////
2205
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2206
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2207
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2208
//// details.                                                     ////
2209
////                                                              ////
2210
//// You should have received a copy of the GNU Lesser General    ////
2211
//// Public License along with this source; if not, download it   ////
2212
//// from http://www.opencores.org/lgpl.shtml                     ////
2213
////                                                              ////
2214
//////////////////////////////////////////////////////////////////////
2215
/// ROM
2216 7 unneback
module vl_rom_init ( adr, q, clk);
2217
   parameter data_width = 32;
2218
   parameter addr_width = 8;
2219
   input [(addr_width-1):0]       adr;
2220
   output reg [(data_width-1):0] q;
2221
   input                         clk;
2222
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
2223
   parameter memory_file = "vl_rom.vmem";
2224
   initial
2225
     begin
2226
        $readmemh(memory_file, rom);
2227
     end
2228
   always @ (posedge clk)
2229
     q <= rom[adr];
2230
endmodule
2231 14 unneback
/*
2232 7 unneback
module vl_rom ( adr, q, clk);
2233 6 unneback
parameter data_width = 32;
2234
parameter addr_width = 4;
2235
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
2236
    {32'h18000000},
2237
    {32'hA8200000},
2238
    {32'hA8200000},
2239
    {32'hA8200000},
2240
    {32'h44003000},
2241
    {32'h15000000},
2242
    {32'h15000000},
2243
    {32'h15000000},
2244
    {32'h15000000},
2245
    {32'h15000000},
2246
    {32'h15000000},
2247
    {32'h15000000},
2248
    {32'h15000000},
2249
    {32'h15000000},
2250
    {32'h15000000},
2251
    {32'h15000000}};
2252 7 unneback
input [addr_width-1:0] adr;
2253 6 unneback
output reg [data_width-1:0] q;
2254
input clk;
2255
always @ (posedge clk)
2256 7 unneback
    q <= data[adr];
2257 6 unneback
endmodule
2258 14 unneback
*/
2259 6 unneback
// Single port RAM
2260
module vl_ram ( d, adr, we, q, clk);
2261
   parameter data_width = 32;
2262
   parameter addr_width = 8;
2263
   input [(data_width-1):0]      d;
2264
   input [(addr_width-1):0]       adr;
2265
   input                         we;
2266 7 unneback
   output reg [(data_width-1):0] q;
2267 6 unneback
   input                         clk;
2268
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
2269 7 unneback
   parameter init = 0;
2270
   parameter memory_file = "vl_ram.vmem";
2271
   generate if (init) begin : init_mem
2272
   initial
2273
     begin
2274
        $readmemh(memory_file, ram);
2275
     end
2276
   end
2277
   endgenerate
2278 6 unneback
   always @ (posedge clk)
2279
   begin
2280
   if (we)
2281
     ram[adr] <= d;
2282
   q <= ram[adr];
2283
   end
2284
endmodule
2285 7 unneback
module vl_ram_be ( d, adr, be, we, q, clk);
2286
   parameter data_width = 32;
2287
   parameter addr_width = 8;
2288
   input [(data_width-1):0]      d;
2289
   input [(addr_width-1):0]       adr;
2290
   input [(addr_width/4)-1:0]    be;
2291
   input                         we;
2292
   output reg [(data_width-1):0] q;
2293
   input                         clk;
2294
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
2295
   parameter init = 0;
2296
   parameter memory_file = "vl_ram.vmem";
2297
   generate if (init) begin : init_mem
2298
   initial
2299
     begin
2300
        $readmemh(memory_file, ram);
2301
     end
2302
   end
2303
   endgenerate
2304
   genvar i;
2305
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
2306
      always @ (posedge clk)
2307
      if (we & be[i])
2308
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
2309
   end
2310
   endgenerate
2311
   always @ (posedge clk)
2312
      q <= ram[adr];
2313
endmodule
2314 6 unneback
// Dual port RAM
2315
// ACTEL FPGA should not use logic to handle rw collision
2316 7 unneback
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
2317 6 unneback
   parameter data_width = 32;
2318
   parameter addr_width = 8;
2319
   input [(data_width-1):0]      d_a;
2320
   input [(addr_width-1):0]       adr_a;
2321
   input [(addr_width-1):0]       adr_b;
2322
   input                         we_a;
2323
   output [(data_width-1):0]      q_b;
2324
   input                         clk_a, clk_b;
2325
   reg [(addr_width-1):0]         adr_b_reg;
2326
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
2327 7 unneback
   parameter init = 0;
2328
   parameter memory_file = "vl_ram.vmem";
2329
   generate if (init) begin : init_mem
2330
   initial
2331
     begin
2332
        $readmemh(memory_file, ram);
2333
     end
2334
   end
2335
   endgenerate
2336 6 unneback
   always @ (posedge clk_a)
2337
   if (we_a)
2338
     ram[adr_a] <= d_a;
2339
   always @ (posedge clk_b)
2340
   adr_b_reg <= adr_b;
2341
   assign q_b = ram[adr_b_reg];
2342
endmodule
2343 7 unneback
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
2344 6 unneback
   parameter data_width = 32;
2345
   parameter addr_width = 8;
2346
   input [(data_width-1):0]      d_a;
2347
   input [(addr_width-1):0]       adr_a;
2348
   input [(addr_width-1):0]       adr_b;
2349
   input                         we_a;
2350
   output [(data_width-1):0]      q_b;
2351
   output reg [(data_width-1):0] q_a;
2352
   input                         clk_a, clk_b;
2353
   reg [(data_width-1):0]         q_b;
2354
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
2355 7 unneback
   parameter init = 0;
2356
   parameter memory_file = "vl_ram.vmem";
2357
   generate if (init) begin : init_mem
2358
   initial
2359
     begin
2360
        $readmemh(memory_file, ram);
2361
     end
2362
   end
2363
   endgenerate
2364 6 unneback
   always @ (posedge clk_a)
2365
     begin
2366
        q_a <= ram[adr_a];
2367
        if (we_a)
2368
             ram[adr_a] <= d_a;
2369
     end
2370
   always @ (posedge clk_b)
2371
          q_b <= ram[adr_b];
2372
endmodule
2373 7 unneback
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
2374 6 unneback
   parameter data_width = 32;
2375
   parameter addr_width = 8;
2376
   input [(data_width-1):0]      d_a;
2377
   input [(addr_width-1):0]       adr_a;
2378
   input [(addr_width-1):0]       adr_b;
2379
   input                         we_a;
2380
   output [(data_width-1):0]      q_b;
2381
   input [(data_width-1):0]       d_b;
2382
   output reg [(data_width-1):0] q_a;
2383
   input                         we_b;
2384
   input                         clk_a, clk_b;
2385
   reg [(data_width-1):0]         q_b;
2386
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
2387 7 unneback
   parameter init = 0;
2388
   parameter memory_file = "vl_ram.vmem";
2389
   generate if (init) begin : init_mem
2390
   initial
2391
     begin
2392
        $readmemh(memory_file, ram);
2393
     end
2394
   end
2395
   endgenerate
2396 6 unneback
   always @ (posedge clk_a)
2397
     begin
2398
        q_a <= ram[adr_a];
2399
        if (we_a)
2400
             ram[adr_a] <= d_a;
2401
     end
2402
   always @ (posedge clk_b)
2403
     begin
2404
        q_b <= ram[adr_b];
2405
        if (we_b)
2406
          ram[adr_b] <= d_b;
2407
     end
2408
endmodule
2409
// Content addresable memory, CAM
2410
// FIFO
2411 25 unneback
module vl_fifo_1r1w_fill_level_sync (
2412
    d, wr, fifo_full,
2413
    q, rd, fifo_empty,
2414
    fill_level,
2415
    clk, rst
2416
    );
2417
parameter data_width = 18;
2418
parameter addr_width = 4;
2419
// write side
2420
input  [data_width-1:0] d;
2421
input                   wr;
2422
output                  fifo_full;
2423
// read side
2424
output [data_width-1:0] q;
2425
input                   rd;
2426
output                  fifo_empty;
2427
// common
2428
output [addr_width:0]   fill_level;
2429
input rst, clk;
2430
wire [addr_width:1] wadr, radr;
2431
vl_cnt_bin_ce
2432
    # ( .length(addr_width))
2433
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
2434
vl_cnt_bin_ce
2435
    # (.length(addr_width))
2436
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
2437
vl_dpram_1r1w
2438
    # (.data_width(data_width), .addr_width(addr_width))
2439
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
2440 31 unneback
vl_cnt_bin_ce_rew_q_zq_l1
2441 27 unneback
    # (.length(addr_width+1), .level1_value(1<<addr_width))
2442 25 unneback
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
2443
endmodule
2444 27 unneback
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
2445
// RAM is supposed to be larger than the two FIFOs
2446
// LFSR counters used adr pointers
2447
module vl_fifo_2r2w_sync_simplex (
2448
    // a side
2449
    a_d, a_wr, a_fifo_full,
2450
    a_q, a_rd, a_fifo_empty,
2451
    a_fill_level,
2452
    // b side
2453
    b_d, b_wr, b_fifo_full,
2454
    b_q, b_rd, b_fifo_empty,
2455
    b_fill_level,
2456
    // common
2457
    clk, rst
2458
    );
2459
parameter data_width = 8;
2460
parameter addr_width = 5;
2461
parameter fifo_full_level = (1<<addr_width)-1;
2462
// a side
2463
input  [data_width-1:0] a_d;
2464
input                   a_wr;
2465
output                  a_fifo_full;
2466
output [data_width-1:0] a_q;
2467
input                   a_rd;
2468
output                  a_fifo_empty;
2469
output [addr_width-1:0] a_fill_level;
2470
// b side
2471
input  [data_width-1:0] b_d;
2472
input                   b_wr;
2473
output                  b_fifo_full;
2474
output [data_width-1:0] b_q;
2475
input                   b_rd;
2476
output                  b_fifo_empty;
2477
output [addr_width-1:0] b_fill_level;
2478
input                   clk;
2479
input                   rst;
2480
// adr_gen
2481
wire [addr_width:1] a_wadr, a_radr;
2482
wire [addr_width:1] b_wadr, b_radr;
2483
// dpram
2484
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
2485
vl_cnt_lfsr_ce
2486
    # ( .length(addr_width))
2487
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
2488
vl_cnt_lfsr_ce
2489
    # (.length(addr_width))
2490
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
2491
vl_cnt_lfsr_ce
2492
    # ( .length(addr_width))
2493
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
2494
vl_cnt_lfsr_ce
2495
    # (.length(addr_width))
2496
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
2497
// mux read or write adr to DPRAM
2498
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
2499
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
2500
vl_dpram_2r2w
2501
    # (.data_width(data_width), .addr_width(addr_width+1))
2502
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
2503
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
2504
vl_cnt_bin_ce_rew_zq_l1
2505 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
2506 27 unneback
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
2507
vl_cnt_bin_ce_rew_zq_l1
2508 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
2509 27 unneback
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
2510
endmodule
2511 6 unneback
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
2512 11 unneback
   parameter addr_width = 4;
2513
   parameter N = addr_width-1;
2514 6 unneback
   parameter Q1 = 2'b00;
2515
   parameter Q2 = 2'b01;
2516
   parameter Q3 = 2'b11;
2517
   parameter Q4 = 2'b10;
2518
   parameter going_empty = 1'b0;
2519
   parameter going_full  = 1'b1;
2520
   input [N:0]  wptr, rptr;
2521 14 unneback
   output       fifo_empty;
2522 6 unneback
   output       fifo_full;
2523
   input        wclk, rclk, rst;
2524
   wire direction;
2525
   reg  direction_set, direction_clr;
2526
   wire async_empty, async_full;
2527
   wire fifo_full2;
2528 14 unneback
   wire fifo_empty2;
2529 6 unneback
   // direction_set
2530
   always @ (wptr[N:N-1] or rptr[N:N-1])
2531
     case ({wptr[N:N-1],rptr[N:N-1]})
2532
       {Q1,Q2} : direction_set <= 1'b1;
2533
       {Q2,Q3} : direction_set <= 1'b1;
2534
       {Q3,Q4} : direction_set <= 1'b1;
2535
       {Q4,Q1} : direction_set <= 1'b1;
2536
       default : direction_set <= 1'b0;
2537
     endcase
2538
   // direction_clear
2539
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
2540
     if (rst)
2541
       direction_clr <= 1'b1;
2542
     else
2543
       case ({wptr[N:N-1],rptr[N:N-1]})
2544
         {Q2,Q1} : direction_clr <= 1'b1;
2545
         {Q3,Q2} : direction_clr <= 1'b1;
2546
         {Q4,Q3} : direction_clr <= 1'b1;
2547
         {Q1,Q4} : direction_clr <= 1'b1;
2548
         default : direction_clr <= 1'b0;
2549
       endcase
2550 18 unneback
    vl_dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
2551 6 unneback
   assign async_empty = (wptr == rptr) && (direction==going_empty);
2552
   assign async_full  = (wptr == rptr) && (direction==going_full);
2553 18 unneback
    vl_dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
2554
    vl_dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
2555 6 unneback
/*
2556
   always @ (posedge wclk or posedge rst or posedge async_full)
2557
     if (rst)
2558
       {fifo_full, fifo_full2} <= 2'b00;
2559
     else if (async_full)
2560
       {fifo_full, fifo_full2} <= 2'b11;
2561
     else
2562
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
2563
*/
2564 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
2565 6 unneback
     if (async_empty)
2566
       {fifo_empty, fifo_empty2} <= 2'b11;
2567
     else
2568 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
2569 18 unneback
    vl_dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
2570
    vl_dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
2571 27 unneback
endmodule // async_compb
2572 6 unneback
module vl_fifo_1r1w_async (
2573
    d, wr, fifo_full, wr_clk, wr_rst,
2574
    q, rd, fifo_empty, rd_clk, rd_rst
2575
    );
2576
parameter data_width = 18;
2577
parameter addr_width = 4;
2578
// write side
2579
input  [data_width-1:0] d;
2580
input                   wr;
2581
output                  fifo_full;
2582
input                   wr_clk;