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1 6 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
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////  Versatile library, clock and reset                          ////
4
////                                                              ////
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////  Description                                                 ////
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////  Logic related to clock and reset                            ////
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////                                                              ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - add more different registers                             ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
14
////        ORSoC AB                                              ////
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////                                                              ////
16
//////////////////////////////////////////////////////////////////////
17
////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
19
////                                                              ////
20
//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
36
////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
// Global buffer
43
// usage:
44
// use to enable global buffers for high fan out signals such as clock and reset
45
`timescale 1 ns/100 ps
46
// Version: 8.4 8.4.0.33
47
module gbuf(GL,CLK);
48
output GL;
49
input  CLK;
50
    wire GND;
51
    GND GND_1_net(.Y(GND));
52
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
53
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
54
endmodule
55
`timescale 1 ns/1 ns
56
module vl_gbuf ( i, o);
57
input i;
58
output o;
59
`ifdef SIM_GBUF
60
assign o=i;
61
`else
62
gbuf gbuf_i0 ( .CLK(i), .GL(o));
63
`endif
64
endmodule
65
 //ACTEL
66
// sync reset
67 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
68 6 unneback
// output active high global reset sync with two DFFs 
69
`timescale 1 ns/100 ps
70
module vl_sync_rst ( rst_n_i, rst_o, clk);
71
input rst_n_i, clk;
72
output rst_o;
73 18 unneback
reg [1:0] tmp;
74 6 unneback
always @ (posedge clk or negedge rst_n_i)
75
if (!rst_n_i)
76 17 unneback
        tmp <= 2'b11;
77 6 unneback
else
78 33 unneback
        tmp <= {1'b0,tmp[1]};
79 17 unneback
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
80 6 unneback
endmodule
81
// vl_pll
82 32 unneback
///////////////////////////////////////////////////////////////////////////////
83 17 unneback
`timescale 1 ps/1 ps
84 6 unneback
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
85
parameter index = 0;
86
parameter number_of_clk = 1;
87 17 unneback
parameter period_time_0 = 20000;
88
parameter period_time_1 = 20000;
89
parameter period_time_2 = 20000;
90
parameter lock_delay = 2000000;
91 6 unneback
input clk_i, rst_n_i;
92
output lock;
93
output reg [0:number_of_clk-1] clk_o;
94
output [0:number_of_clk-1] rst_o;
95
`ifdef SIM_PLL
96
always
97
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
98
generate if (number_of_clk > 1)
99
always
100
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
101
endgenerate
102
generate if (number_of_clk > 2)
103
always
104
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
105
endgenerate
106
genvar i;
107
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
108
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
109
end
110
endgenerate
111
assign #lock_delay lock = rst_n_i;
112
endmodule
113
`else
114
generate if (number_of_clk==1 & index==0) begin
115
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
116
end
117
endgenerate // index==0
118
generate if (number_of_clk==1 & index==1) begin
119
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
120
end
121
endgenerate // index==1
122
generate if (number_of_clk==1 & index==2) begin
123
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
124
end
125
endgenerate // index==2
126
generate if (number_of_clk==1 & index==3) begin
127
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
128
end
129
endgenerate // index==0
130
generate if (number_of_clk==2 & index==0) begin
131
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
132
end
133
endgenerate // index==0
134
generate if (number_of_clk==2 & index==1) begin
135
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
136
end
137
endgenerate // index==1
138
generate if (number_of_clk==2 & index==2) begin
139
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
140
end
141
endgenerate // index==2
142
generate if (number_of_clk==2 & index==3) begin
143
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
144
end
145
endgenerate // index==0
146
generate if (number_of_clk==3 & index==0) begin
147
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
148
end
149
endgenerate // index==0
150
generate if (number_of_clk==3 & index==1) begin
151
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
152
end
153
endgenerate // index==1
154
generate if (number_of_clk==3 & index==2) begin
155
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
156
end
157
endgenerate // index==2
158
generate if (number_of_clk==3 & index==3) begin
159
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
160
end
161
endgenerate // index==0
162
genvar i;
163
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
164
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
165
end
166
endgenerate
167
endmodule
168
`endif
169 32 unneback
///////////////////////////////////////////////////////////////////////////////
170 6 unneback
 //actel
171
//////////////////////////////////////////////////////////////////////
172
////                                                              ////
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////  Versatile library, registers                                ////
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////                                                              ////
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////  Description                                                 ////
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////  Different type of registers                                 ////
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////                                                              ////
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////                                                              ////
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////  To Do:                                                      ////
180
////   - add more different registers                             ////
181
////                                                              ////
182
////  Author(s):                                                  ////
183
////      - Michael Unneback, unneback@opencores.org              ////
184
////        ORSoC AB                                              ////
185
////                                                              ////
186
//////////////////////////////////////////////////////////////////////
187
////                                                              ////
188
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
189
////                                                              ////
190
//// This source file may be used and distributed without         ////
191
//// restriction provided that this copyright statement is not    ////
192
//// removed from the file and that any derivative work contains  ////
193
//// the original copyright notice and the associated disclaimer. ////
194
////                                                              ////
195
//// This source file is free software; you can redistribute it   ////
196
//// and/or modify it under the terms of the GNU Lesser General   ////
197
//// Public License as published by the Free Software Foundation; ////
198
//// either version 2.1 of the License, or (at your option) any   ////
199
//// later version.                                               ////
200
////                                                              ////
201
//// This source is distributed in the hope that it will be       ////
202
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
203
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
204
//// PURPOSE.  See the GNU Lesser General Public License for more ////
205
//// details.                                                     ////
206
////                                                              ////
207
//// You should have received a copy of the GNU Lesser General    ////
208
//// Public License along with this source; if not, download it   ////
209
//// from http://www.opencores.org/lgpl.shtml                     ////
210
////                                                              ////
211
//////////////////////////////////////////////////////////////////////
212 18 unneback
module vl_dff ( d, q, clk, rst);
213 6 unneback
        parameter width = 1;
214
        parameter reset_value = 0;
215
        input [width-1:0] d;
216
        input clk, rst;
217
        output reg [width-1:0] q;
218
        always @ (posedge clk or posedge rst)
219
        if (rst)
220
                q <= reset_value;
221
        else
222
                q <= d;
223
endmodule
224 18 unneback
module vl_dff_array ( d, q, clk, rst);
225 6 unneback
        parameter width = 1;
226
        parameter depth = 2;
227
        parameter reset_value = 1'b0;
228
        input [width-1:0] d;
229
        input clk, rst;
230
        output [width-1:0] q;
231
        reg  [0:depth-1] q_tmp [width-1:0];
232
        integer i;
233
        always @ (posedge clk or posedge rst)
234
        if (rst) begin
235
            for (i=0;i<depth;i=i+1)
236
                q_tmp[i] <= {width{reset_value}};
237
        end else begin
238
            q_tmp[0] <= d;
239
            for (i=1;i<depth;i=i+1)
240
                q_tmp[i] <= q_tmp[i-1];
241
        end
242
    assign q = q_tmp[depth-1];
243
endmodule
244 18 unneback
module vl_dff_ce ( d, ce, q, clk, rst);
245 6 unneback
        parameter width = 1;
246
        parameter reset_value = 0;
247
        input [width-1:0] d;
248
        input ce, clk, rst;
249
        output reg [width-1:0] q;
250
        always @ (posedge clk or posedge rst)
251
        if (rst)
252
                q <= reset_value;
253
        else
254
                if (ce)
255
                        q <= d;
256
endmodule
257 18 unneback
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
258 8 unneback
        parameter width = 1;
259
        parameter reset_value = 0;
260
        input [width-1:0] d;
261 10 unneback
        input ce, clear, clk, rst;
262 8 unneback
        output reg [width-1:0] q;
263
        always @ (posedge clk or posedge rst)
264
        if (rst)
265
            q <= reset_value;
266
        else
267
            if (ce)
268
                if (clear)
269
                    q <= {width{1'b0}};
270
                else
271
                    q <= d;
272
endmodule
273 24 unneback
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
274
        parameter width = 1;
275
        parameter reset_value = 0;
276
        input [width-1:0] d;
277
        input ce, set, clk, rst;
278
        output reg [width-1:0] q;
279
        always @ (posedge clk or posedge rst)
280
        if (rst)
281
            q <= reset_value;
282
        else
283
            if (ce)
284
                if (set)
285
                    q <= {width{1'b1}};
286
                else
287
                    q <= d;
288
endmodule
289 29 unneback
module vl_spr ( sp, r, q, clk, rst);
290
        parameter width = 1;
291
        parameter reset_value = 0;
292
        input sp, r;
293
        output reg q;
294
        input clk, rst;
295
        always @ (posedge clk or posedge rst)
296
        if (rst)
297
            q <= reset_value;
298
        else
299
            if (sp)
300
                q <= 1'b1;
301
            else if (r)
302
                q <= 1'b0;
303
endmodule
304
module vl_srp ( s, rp, q, clk, rst);
305
        parameter width = 1;
306
        parameter reset_value = 0;
307
        input s, rp;
308
        output reg q;
309
        input clk, rst;
310
        always @ (posedge clk or posedge rst)
311
        if (rst)
312
            q <= reset_value;
313
        else
314
            if (rp)
315
                q <= 1'b0;
316
            else if (s)
317
                q <= 1'b1;
318
endmodule
319 18 unneback
module vl_dff_sr ( aclr, aset, clock, data, q);
320 6 unneback
    input         aclr;
321
    input         aset;
322
    input         clock;
323
    input         data;
324
    output reg    q;
325
   always @ (posedge clock or posedge aclr or posedge aset)
326
     if (aclr)
327
       q <= 1'b0;
328
     else if (aset)
329
       q <= 1'b1;
330
     else
331
       q <= data;
332
endmodule
333
// LATCH
334
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
335
module latch ( d, le, q, clk);
336
input d, le;
337
output q;
338
input clk;/*
339
   always @ (posedge direction_set or posedge direction_clr)
340
     if (direction_clr)
341
       direction <= going_empty;
342
     else
343
       direction <= going_full;*/
344
endmodule
345 18 unneback
module vl_shreg ( d, q, clk, rst);
346 17 unneback
parameter depth = 10;
347
input d;
348
output q;
349
input clk, rst;
350
reg [1:depth] dffs;
351
always @ (posedge clk or posedge rst)
352
if (rst)
353
    dffs <= {depth{1'b0}};
354
else
355
    dffs <= {d,dffs[1:depth-1]};
356
assign q = dffs[depth];
357
endmodule
358 18 unneback
module vl_shreg_ce ( d, ce, q, clk, rst);
359 17 unneback
parameter depth = 10;
360
input d, ce;
361
output q;
362
input clk, rst;
363
reg [1:depth] dffs;
364
always @ (posedge clk or posedge rst)
365
if (rst)
366
    dffs <= {depth{1'b0}};
367
else
368
    if (ce)
369
        dffs <= {d,dffs[1:depth-1]};
370
assign q = dffs[depth];
371
endmodule
372 18 unneback
module vl_delay ( d, q, clk, rst);
373 15 unneback
parameter depth = 10;
374
input d;
375
output q;
376
input clk, rst;
377
reg [1:depth] dffs;
378
always @ (posedge clk or posedge rst)
379
if (rst)
380
    dffs <= {depth{1'b0}};
381
else
382
    dffs <= {d,dffs[1:depth-1]};
383
assign q = dffs[depth];
384
endmodule
385 18 unneback
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
386 17 unneback
parameter depth = 10;
387
input d;
388
output q, emptyflag;
389
input clk, rst;
390
reg [1:depth] dffs;
391
always @ (posedge clk or posedge rst)
392
if (rst)
393
    dffs <= {depth{1'b0}};
394
else
395
    dffs <= {d,dffs[1:depth-1]};
396
assign q = dffs[depth];
397
assign emptyflag = !(|dffs);
398
endmodule
399 6 unneback
//////////////////////////////////////////////////////////////////////
400
////                                                              ////
401 18 unneback
////  Logic functions                                             ////
402
////                                                              ////
403
////  Description                                                 ////
404
////  Logic functions such as multiplexers                        ////
405
////                                                              ////
406
////                                                              ////
407
////  To Do:                                                      ////
408
////   -                                                          ////
409
////                                                              ////
410
////  Author(s):                                                  ////
411
////      - Michael Unneback, unneback@opencores.org              ////
412
////        ORSoC AB                                              ////
413
////                                                              ////
414
//////////////////////////////////////////////////////////////////////
415
////                                                              ////
416
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
417
////                                                              ////
418
//// This source file may be used and distributed without         ////
419
//// restriction provided that this copyright statement is not    ////
420
//// removed from the file and that any derivative work contains  ////
421
//// the original copyright notice and the associated disclaimer. ////
422
////                                                              ////
423
//// This source file is free software; you can redistribute it   ////
424
//// and/or modify it under the terms of the GNU Lesser General   ////
425
//// Public License as published by the Free Software Foundation; ////
426
//// either version 2.1 of the License, or (at your option) any   ////
427
//// later version.                                               ////
428
////                                                              ////
429
//// This source is distributed in the hope that it will be       ////
430
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
431
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
432
//// PURPOSE.  See the GNU Lesser General Public License for more ////
433
//// details.                                                     ////
434
////                                                              ////
435
//// You should have received a copy of the GNU Lesser General    ////
436
//// Public License along with this source; if not, download it   ////
437
//// from http://www.opencores.org/lgpl.shtml                     ////
438
////                                                              ////
439
//////////////////////////////////////////////////////////////////////
440 34 unneback
module vl_mux2_andor ( a1, a0, sel, dout);
441
parameter width = 32;
442
parameter nr_of_ports = 2;
443
input [width-1:0] a1, a0;
444
input [nr_of_ports-1:0] sel;
445
output [width-1:0] dout;
446
wire [width-1:0] tmp [nr_of_ports-1:0];
447
integer i;
448
// and
449
assign tmp[0] = {width{sel[0]}} & a0;
450
assign tmp[1] = {width{sel[1]}} & a1;
451
// or
452
assign dout = tmp[1] | tmp[0];
453
endmodule
454
module vl_mux3_andor ( a2, a1, a0, sel, dout);
455
parameter width = 32;
456
parameter nr_of_ports = 3;
457
input [width-1:0] a2, a1, a0;
458
input [nr_of_ports-1:0] sel;
459
output [width-1:0] dout;
460
wire [width-1:0] tmp [nr_of_ports-1:0];
461
integer i;
462
// and
463
assign tmp[0] = {width{sel[0]}} & a0;
464
assign tmp[1] = {width{sel[1]}} & a1;
465
assign tmp[2] = {width{sel[2]}} & a2;
466
// or
467
assign dout = tmp[2] | tmp[1] | tmp[0];
468
endmodule
469 18 unneback
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
470
parameter width = 32;
471
parameter nr_of_ports = 4;
472
input [width-1:0] a3, a2, a1, a0;
473
input [nr_of_ports-1:0] sel;
474 22 unneback
output [width-1:0] dout;
475 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
476 18 unneback
integer i;
477
// and
478
assign tmp[0] = {width{sel[0]}} & a0;
479
assign tmp[1] = {width{sel[1]}} & a1;
480
assign tmp[2] = {width{sel[2]}} & a2;
481
assign tmp[3] = {width{sel[3]}} & a3;
482
// or
483
assign dout = tmp[3] | tmp[2] | tmp[1] | tmp[0];
484
endmodule
485
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
486
parameter width = 32;
487
parameter nr_of_ports = 5;
488
input [width-1:0] a4, a3, a2, a1, a0;
489
input [nr_of_ports-1:0] sel;
490 22 unneback
output [width-1:0] dout;
491 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
492 18 unneback
integer i;
493
// and
494
assign tmp[0] = {width{sel[0]}} & a0;
495
assign tmp[1] = {width{sel[1]}} & a1;
496
assign tmp[2] = {width{sel[2]}} & a2;
497
assign tmp[3] = {width{sel[3]}} & a3;
498
assign tmp[4] = {width{sel[4]}} & a4;
499
// or
500
assign dout = tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
501
endmodule
502
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
503
parameter width = 32;
504
parameter nr_of_ports = 6;
505
input [width-1:0] a5, a4, a3, a2, a1, a0;
506
input [nr_of_ports-1:0] sel;
507 22 unneback
output [width-1:0] dout;
508 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
509 18 unneback
integer i;
510
// and
511
assign tmp[0] = {width{sel[0]}} & a0;
512
assign tmp[1] = {width{sel[1]}} & a1;
513
assign tmp[2] = {width{sel[2]}} & a2;
514
assign tmp[3] = {width{sel[3]}} & a3;
515
assign tmp[4] = {width{sel[4]}} & a4;
516
assign tmp[5] = {width{sel[5]}} & a5;
517
// or
518
assign dout = tmp[5] | tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
519
endmodule
520
//////////////////////////////////////////////////////////////////////
521
////                                                              ////
522 6 unneback
////  Versatile counter                                           ////
523
////                                                              ////
524
////  Description                                                 ////
525
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
526
////  counter                                                     ////
527
////                                                              ////
528
////  To Do:                                                      ////
529
////   - add LFSR with more taps                                  ////
530
////                                                              ////
531
////  Author(s):                                                  ////
532
////      - Michael Unneback, unneback@opencores.org              ////
533
////        ORSoC AB                                              ////
534
////                                                              ////
535
//////////////////////////////////////////////////////////////////////
536
////                                                              ////
537
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
538
////                                                              ////
539
//// This source file may be used and distributed without         ////
540
//// restriction provided that this copyright statement is not    ////
541
//// removed from the file and that any derivative work contains  ////
542
//// the original copyright notice and the associated disclaimer. ////
543
////                                                              ////
544
//// This source file is free software; you can redistribute it   ////
545
//// and/or modify it under the terms of the GNU Lesser General   ////
546
//// Public License as published by the Free Software Foundation; ////
547
//// either version 2.1 of the License, or (at your option) any   ////
548
//// later version.                                               ////
549
////                                                              ////
550
//// This source is distributed in the hope that it will be       ////
551
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
552
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
553
//// PURPOSE.  See the GNU Lesser General Public License for more ////
554
//// details.                                                     ////
555
////                                                              ////
556
//// You should have received a copy of the GNU Lesser General    ////
557
//// Public License along with this source; if not, download it   ////
558
//// from http://www.opencores.org/lgpl.shtml                     ////
559
////                                                              ////
560
//////////////////////////////////////////////////////////////////////
561
// binary counter
562 22 unneback
module vl_cnt_bin ( q, rst, clk);
563
   parameter length = 4;
564
   output [length:1] q;
565
   input rst;
566
   input clk;
567
   parameter clear_value = 0;
568
   parameter set_value = 1;
569
   parameter wrap_value = 0;
570
   parameter level1_value = 15;
571
   reg  [length:1] qi;
572
   wire [length:1] q_next;
573
   assign q_next = qi + {{length-1{1'b0}},1'b1};
574
   always @ (posedge clk or posedge rst)
575
     if (rst)
576
       qi <= {length{1'b0}};
577
     else
578
       qi <= q_next;
579
   assign q = qi;
580
endmodule
581
//////////////////////////////////////////////////////////////////////
582
////                                                              ////
583
////  Versatile counter                                           ////
584
////                                                              ////
585
////  Description                                                 ////
586
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
587
////  counter                                                     ////
588
////                                                              ////
589
////  To Do:                                                      ////
590
////   - add LFSR with more taps                                  ////
591
////                                                              ////
592
////  Author(s):                                                  ////
593
////      - Michael Unneback, unneback@opencores.org              ////
594
////        ORSoC AB                                              ////
595
////                                                              ////
596
//////////////////////////////////////////////////////////////////////
597
////                                                              ////
598
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
599
////                                                              ////
600
//// This source file may be used and distributed without         ////
601
//// restriction provided that this copyright statement is not    ////
602
//// removed from the file and that any derivative work contains  ////
603
//// the original copyright notice and the associated disclaimer. ////
604
////                                                              ////
605
//// This source file is free software; you can redistribute it   ////
606
//// and/or modify it under the terms of the GNU Lesser General   ////
607
//// Public License as published by the Free Software Foundation; ////
608
//// either version 2.1 of the License, or (at your option) any   ////
609
//// later version.                                               ////
610
////                                                              ////
611
//// This source is distributed in the hope that it will be       ////
612
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
613
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
614
//// PURPOSE.  See the GNU Lesser General Public License for more ////
615
//// details.                                                     ////
616
////                                                              ////
617
//// You should have received a copy of the GNU Lesser General    ////
618
//// Public License along with this source; if not, download it   ////
619
//// from http://www.opencores.org/lgpl.shtml                     ////
620
////                                                              ////
621
//////////////////////////////////////////////////////////////////////
622
// binary counter
623
module vl_cnt_bin_clear ( clear, q, rst, clk);
624
   parameter length = 4;
625
   input clear;
626
   output [length:1] q;
627
   input rst;
628
   input clk;
629
   parameter clear_value = 0;
630
   parameter set_value = 1;
631
   parameter wrap_value = 0;
632
   parameter level1_value = 15;
633
   reg  [length:1] qi;
634
   wire [length:1] q_next;
635
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
636
   always @ (posedge clk or posedge rst)
637
     if (rst)
638
       qi <= {length{1'b0}};
639
     else
640
       qi <= q_next;
641
   assign q = qi;
642
endmodule
643
//////////////////////////////////////////////////////////////////////
644
////                                                              ////
645
////  Versatile counter                                           ////
646
////                                                              ////
647
////  Description                                                 ////
648
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
649
////  counter                                                     ////
650
////                                                              ////
651
////  To Do:                                                      ////
652
////   - add LFSR with more taps                                  ////
653
////                                                              ////
654
////  Author(s):                                                  ////
655
////      - Michael Unneback, unneback@opencores.org              ////
656
////        ORSoC AB                                              ////
657
////                                                              ////
658
//////////////////////////////////////////////////////////////////////
659
////                                                              ////
660
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
661
////                                                              ////
662
//// This source file may be used and distributed without         ////
663
//// restriction provided that this copyright statement is not    ////
664
//// removed from the file and that any derivative work contains  ////
665
//// the original copyright notice and the associated disclaimer. ////
666
////                                                              ////
667
//// This source file is free software; you can redistribute it   ////
668
//// and/or modify it under the terms of the GNU Lesser General   ////
669
//// Public License as published by the Free Software Foundation; ////
670
//// either version 2.1 of the License, or (at your option) any   ////
671
//// later version.                                               ////
672
////                                                              ////
673
//// This source is distributed in the hope that it will be       ////
674
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
675
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
676
//// PURPOSE.  See the GNU Lesser General Public License for more ////
677
//// details.                                                     ////
678
////                                                              ////
679
//// You should have received a copy of the GNU Lesser General    ////
680
//// Public License along with this source; if not, download it   ////
681
//// from http://www.opencores.org/lgpl.shtml                     ////
682
////                                                              ////
683
//////////////////////////////////////////////////////////////////////
684
// binary counter
685 18 unneback
module vl_cnt_bin_ce ( cke, q, rst, clk);
686 6 unneback
   parameter length = 4;
687
   input cke;
688
   output [length:1] q;
689
   input rst;
690
   input clk;
691
   parameter clear_value = 0;
692
   parameter set_value = 1;
693
   parameter wrap_value = 0;
694
   parameter level1_value = 15;
695
   reg  [length:1] qi;
696
   wire [length:1] q_next;
697
   assign q_next = qi + {{length-1{1'b0}},1'b1};
698
   always @ (posedge clk or posedge rst)
699
     if (rst)
700
       qi <= {length{1'b0}};
701
     else
702
     if (cke)
703
       qi <= q_next;
704
   assign q = qi;
705
endmodule
706
//////////////////////////////////////////////////////////////////////
707
////                                                              ////
708
////  Versatile counter                                           ////
709
////                                                              ////
710
////  Description                                                 ////
711
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
712
////  counter                                                     ////
713
////                                                              ////
714
////  To Do:                                                      ////
715
////   - add LFSR with more taps                                  ////
716
////                                                              ////
717
////  Author(s):                                                  ////
718
////      - Michael Unneback, unneback@opencores.org              ////
719
////        ORSoC AB                                              ////
720
////                                                              ////
721
//////////////////////////////////////////////////////////////////////
722
////                                                              ////
723
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
724
////                                                              ////
725
//// This source file may be used and distributed without         ////
726
//// restriction provided that this copyright statement is not    ////
727
//// removed from the file and that any derivative work contains  ////
728
//// the original copyright notice and the associated disclaimer. ////
729
////                                                              ////
730
//// This source file is free software; you can redistribute it   ////
731
//// and/or modify it under the terms of the GNU Lesser General   ////
732
//// Public License as published by the Free Software Foundation; ////
733
//// either version 2.1 of the License, or (at your option) any   ////
734
//// later version.                                               ////
735
////                                                              ////
736
//// This source is distributed in the hope that it will be       ////
737
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
738
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
739
//// PURPOSE.  See the GNU Lesser General Public License for more ////
740
//// details.                                                     ////
741
////                                                              ////
742
//// You should have received a copy of the GNU Lesser General    ////
743
//// Public License along with this source; if not, download it   ////
744
//// from http://www.opencores.org/lgpl.shtml                     ////
745
////                                                              ////
746
//////////////////////////////////////////////////////////////////////
747
// binary counter
748 18 unneback
module vl_cnt_bin_ce_clear ( clear, cke, q, rst, clk);
749 6 unneback
   parameter length = 4;
750
   input clear;
751
   input cke;
752
   output [length:1] q;
753
   input rst;
754
   input clk;
755
   parameter clear_value = 0;
756
   parameter set_value = 1;
757
   parameter wrap_value = 0;
758
   parameter level1_value = 15;
759
   reg  [length:1] qi;
760
   wire [length:1] q_next;
761
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
762
   always @ (posedge clk or posedge rst)
763
     if (rst)
764
       qi <= {length{1'b0}};
765
     else
766
     if (cke)
767
       qi <= q_next;
768
   assign q = qi;
769
endmodule
770
//////////////////////////////////////////////////////////////////////
771
////                                                              ////
772
////  Versatile counter                                           ////
773
////                                                              ////
774
////  Description                                                 ////
775
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
776
////  counter                                                     ////
777
////                                                              ////
778
////  To Do:                                                      ////
779
////   - add LFSR with more taps                                  ////
780
////                                                              ////
781
////  Author(s):                                                  ////
782
////      - Michael Unneback, unneback@opencores.org              ////
783
////        ORSoC AB                                              ////
784
////                                                              ////
785
//////////////////////////////////////////////////////////////////////
786
////                                                              ////
787
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
788
////                                                              ////
789
//// This source file may be used and distributed without         ////
790
//// restriction provided that this copyright statement is not    ////
791
//// removed from the file and that any derivative work contains  ////
792
//// the original copyright notice and the associated disclaimer. ////
793
////                                                              ////
794
//// This source file is free software; you can redistribute it   ////
795
//// and/or modify it under the terms of the GNU Lesser General   ////
796
//// Public License as published by the Free Software Foundation; ////
797
//// either version 2.1 of the License, or (at your option) any   ////
798
//// later version.                                               ////
799
////                                                              ////
800
//// This source is distributed in the hope that it will be       ////
801
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
802
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
803
//// PURPOSE.  See the GNU Lesser General Public License for more ////
804
//// details.                                                     ////
805
////                                                              ////
806
//// You should have received a copy of the GNU Lesser General    ////
807
//// Public License along with this source; if not, download it   ////
808
//// from http://www.opencores.org/lgpl.shtml                     ////
809
////                                                              ////
810
//////////////////////////////////////////////////////////////////////
811
// binary counter
812 29 unneback
module vl_cnt_bin_ce_clear_l1_l2 ( clear, cke, q, level1, level2, rst, clk);
813
   parameter length = 4;
814
   input clear;
815
   input cke;
816
   output [length:1] q;
817
   output reg level1;
818
   output reg level2;
819
   input rst;
820
   input clk;
821
   parameter clear_value = 0;
822
   parameter set_value = 1;
823 30 unneback
   parameter wrap_value = 15;
824
   parameter level1_value = 8;
825
   parameter level2_value = 15;
826 29 unneback
   wire rew;
827 30 unneback
   assign rew = 1'b0;
828 29 unneback
   reg  [length:1] qi;
829
   wire [length:1] q_next;
830
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
831
   always @ (posedge clk or posedge rst)
832
     if (rst)
833
       qi <= {length{1'b0}};
834
     else
835
     if (cke)
836
       qi <= q_next;
837
   assign q = qi;
838
    always @ (posedge clk or posedge rst)
839
    if (rst)
840
        level1 <= 1'b0;
841
    else
842
    if (cke)
843
    if (clear)
844
        level1 <= 1'b0;
845
    else if (q_next == level1_value)
846
        level1 <= 1'b1;
847
    else if (qi == level1_value & rew)
848
        level1 <= 1'b0;
849
    always @ (posedge clk or posedge rst)
850
    if (rst)
851
        level2 <= 1'b0;
852
    else
853
    if (cke)
854
    if (clear)
855
        level2 <= 1'b0;
856
    else if (q_next == level2_value)
857
        level2 <= 1'b1;
858
    else if (qi == level2_value & rew)
859
        level2 <= 1'b0;
860
endmodule
861
//////////////////////////////////////////////////////////////////////
862
////                                                              ////
863
////  Versatile counter                                           ////
864
////                                                              ////
865
////  Description                                                 ////
866
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
867
////  counter                                                     ////
868
////                                                              ////
869
////  To Do:                                                      ////
870
////   - add LFSR with more taps                                  ////
871
////                                                              ////
872
////  Author(s):                                                  ////
873
////      - Michael Unneback, unneback@opencores.org              ////
874
////        ORSoC AB                                              ////
875
////                                                              ////
876
//////////////////////////////////////////////////////////////////////
877
////                                                              ////
878
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
879
////                                                              ////
880
//// This source file may be used and distributed without         ////
881
//// restriction provided that this copyright statement is not    ////
882
//// removed from the file and that any derivative work contains  ////
883
//// the original copyright notice and the associated disclaimer. ////
884
////                                                              ////
885
//// This source file is free software; you can redistribute it   ////
886
//// and/or modify it under the terms of the GNU Lesser General   ////
887
//// Public License as published by the Free Software Foundation; ////
888
//// either version 2.1 of the License, or (at your option) any   ////
889
//// later version.                                               ////
890
////                                                              ////
891
//// This source is distributed in the hope that it will be       ////
892
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
893
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
894
//// PURPOSE.  See the GNU Lesser General Public License for more ////
895
//// details.                                                     ////
896
////                                                              ////
897
//// You should have received a copy of the GNU Lesser General    ////
898
//// Public License along with this source; if not, download it   ////
899
//// from http://www.opencores.org/lgpl.shtml                     ////
900
////                                                              ////
901
//////////////////////////////////////////////////////////////////////
902
// binary counter
903 18 unneback
module vl_cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk);
904 6 unneback
   parameter length = 4;
905
   input clear;
906
   input set;
907
   input cke;
908
   input rew;
909
   output [length:1] q;
910
   input rst;
911
   input clk;
912
   parameter clear_value = 0;
913
   parameter set_value = 1;
914
   parameter wrap_value = 0;
915
   parameter level1_value = 15;
916
   reg  [length:1] qi;
917
   wire  [length:1] q_next, q_next_fw, q_next_rew;
918
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
919
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
920
   assign q_next = rew ? q_next_rew : q_next_fw;
921
   always @ (posedge clk or posedge rst)
922
     if (rst)
923
       qi <= {length{1'b0}};
924
     else
925
     if (cke)
926
       qi <= q_next;
927
   assign q = qi;
928
endmodule
929
//////////////////////////////////////////////////////////////////////
930
////                                                              ////
931
////  Versatile counter                                           ////
932
////                                                              ////
933
////  Description                                                 ////
934
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
935
////  counter                                                     ////
936
////                                                              ////
937
////  To Do:                                                      ////
938
////   - add LFSR with more taps                                  ////
939
////                                                              ////
940
////  Author(s):                                                  ////
941
////      - Michael Unneback, unneback@opencores.org              ////
942
////        ORSoC AB                                              ////
943
////                                                              ////
944
//////////////////////////////////////////////////////////////////////
945
////                                                              ////
946
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
947
////                                                              ////
948
//// This source file may be used and distributed without         ////
949
//// restriction provided that this copyright statement is not    ////
950
//// removed from the file and that any derivative work contains  ////
951
//// the original copyright notice and the associated disclaimer. ////
952
////                                                              ////
953
//// This source file is free software; you can redistribute it   ////
954
//// and/or modify it under the terms of the GNU Lesser General   ////
955
//// Public License as published by the Free Software Foundation; ////
956
//// either version 2.1 of the License, or (at your option) any   ////
957
//// later version.                                               ////
958
////                                                              ////
959
//// This source is distributed in the hope that it will be       ////
960
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
961
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
962
//// PURPOSE.  See the GNU Lesser General Public License for more ////
963
//// details.                                                     ////
964
////                                                              ////
965
//// You should have received a copy of the GNU Lesser General    ////
966
//// Public License along with this source; if not, download it   ////
967
//// from http://www.opencores.org/lgpl.shtml                     ////
968
////                                                              ////
969
//////////////////////////////////////////////////////////////////////
970
// binary counter
971 18 unneback
module vl_cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk);
972 6 unneback
   parameter length = 4;
973
   input cke;
974
   input rew;
975
   output reg level1;
976
   input rst;
977
   input clk;
978
   parameter clear_value = 0;
979
   parameter set_value = 1;
980
   parameter wrap_value = 1;
981
   parameter level1_value = 15;
982 29 unneback
   wire clear;
983 30 unneback
   assign clear = 1'b0;
984 6 unneback
   reg  [length:1] qi;
985
   wire  [length:1] q_next, q_next_fw, q_next_rew;
986
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
987
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
988
   assign q_next = rew ? q_next_rew : q_next_fw;
989
   always @ (posedge clk or posedge rst)
990
     if (rst)
991
       qi <= {length{1'b0}};
992
     else
993
     if (cke)
994
       qi <= q_next;
995
    always @ (posedge clk or posedge rst)
996
    if (rst)
997
        level1 <= 1'b0;
998
    else
999
    if (cke)
1000 29 unneback
    if (clear)
1001
        level1 <= 1'b0;
1002
    else if (q_next == level1_value)
1003 6 unneback
        level1 <= 1'b1;
1004
    else if (qi == level1_value & rew)
1005
        level1 <= 1'b0;
1006
endmodule
1007
//////////////////////////////////////////////////////////////////////
1008
////                                                              ////
1009
////  Versatile counter                                           ////
1010
////                                                              ////
1011
////  Description                                                 ////
1012
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1013
////  counter                                                     ////
1014
////                                                              ////
1015
////  To Do:                                                      ////
1016
////   - add LFSR with more taps                                  ////
1017
////                                                              ////
1018
////  Author(s):                                                  ////
1019
////      - Michael Unneback, unneback@opencores.org              ////
1020
////        ORSoC AB                                              ////
1021
////                                                              ////
1022
//////////////////////////////////////////////////////////////////////
1023
////                                                              ////
1024
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1025
////                                                              ////
1026
//// This source file may be used and distributed without         ////
1027
//// restriction provided that this copyright statement is not    ////
1028
//// removed from the file and that any derivative work contains  ////
1029
//// the original copyright notice and the associated disclaimer. ////
1030
////                                                              ////
1031
//// This source file is free software; you can redistribute it   ////
1032
//// and/or modify it under the terms of the GNU Lesser General   ////
1033
//// Public License as published by the Free Software Foundation; ////
1034
//// either version 2.1 of the License, or (at your option) any   ////
1035
//// later version.                                               ////
1036
////                                                              ////
1037
//// This source is distributed in the hope that it will be       ////
1038
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1039
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1040
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1041
//// details.                                                     ////
1042
////                                                              ////
1043
//// You should have received a copy of the GNU Lesser General    ////
1044
//// Public License along with this source; if not, download it   ////
1045
//// from http://www.opencores.org/lgpl.shtml                     ////
1046
////                                                              ////
1047
//////////////////////////////////////////////////////////////////////
1048 25 unneback
// binary counter
1049
module vl_cnt_bin_ce_rew_zq_l1 ( cke, rew, zq, level1, rst, clk);
1050
   parameter length = 4;
1051
   input cke;
1052
   input rew;
1053
   output reg zq;
1054
   output reg level1;
1055
   input rst;
1056
   input clk;
1057
   parameter clear_value = 0;
1058
   parameter set_value = 1;
1059
   parameter wrap_value = 1;
1060
   parameter level1_value = 15;
1061 29 unneback
   wire clear;
1062 30 unneback
   assign clear = 1'b0;
1063 25 unneback
   reg  [length:1] qi;
1064
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1065
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1066
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1067
   assign q_next = rew ? q_next_rew : q_next_fw;
1068
   always @ (posedge clk or posedge rst)
1069
     if (rst)
1070
       qi <= {length{1'b0}};
1071
     else
1072
     if (cke)
1073
       qi <= q_next;
1074
   always @ (posedge clk or posedge rst)
1075
     if (rst)
1076
       zq <= 1'b1;
1077
     else
1078
     if (cke)
1079
       zq <= q_next == {length{1'b0}};
1080
    always @ (posedge clk or posedge rst)
1081
    if (rst)
1082
        level1 <= 1'b0;
1083
    else
1084
    if (cke)
1085 29 unneback
    if (clear)
1086
        level1 <= 1'b0;
1087
    else if (q_next == level1_value)
1088 25 unneback
        level1 <= 1'b1;
1089
    else if (qi == level1_value & rew)
1090
        level1 <= 1'b0;
1091
endmodule
1092
//////////////////////////////////////////////////////////////////////
1093
////                                                              ////
1094
////  Versatile counter                                           ////
1095
////                                                              ////
1096
////  Description                                                 ////
1097
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1098
////  counter                                                     ////
1099
////                                                              ////
1100
////  To Do:                                                      ////
1101
////   - add LFSR with more taps                                  ////
1102
////                                                              ////
1103
////  Author(s):                                                  ////
1104
////      - Michael Unneback, unneback@opencores.org              ////
1105
////        ORSoC AB                                              ////
1106
////                                                              ////
1107
//////////////////////////////////////////////////////////////////////
1108
////                                                              ////
1109
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1110
////                                                              ////
1111
//// This source file may be used and distributed without         ////
1112
//// restriction provided that this copyright statement is not    ////
1113
//// removed from the file and that any derivative work contains  ////
1114
//// the original copyright notice and the associated disclaimer. ////
1115
////                                                              ////
1116
//// This source file is free software; you can redistribute it   ////
1117
//// and/or modify it under the terms of the GNU Lesser General   ////
1118
//// Public License as published by the Free Software Foundation; ////
1119
//// either version 2.1 of the License, or (at your option) any   ////
1120
//// later version.                                               ////
1121
////                                                              ////
1122
//// This source is distributed in the hope that it will be       ////
1123
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1124
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1125
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1126
//// details.                                                     ////
1127
////                                                              ////
1128
//// You should have received a copy of the GNU Lesser General    ////
1129
//// Public License along with this source; if not, download it   ////
1130
//// from http://www.opencores.org/lgpl.shtml                     ////
1131
////                                                              ////
1132
//////////////////////////////////////////////////////////////////////
1133
// binary counter
1134
module vl_cnt_bin_ce_rew_q_zq_l1 ( cke, rew, q, zq, level1, rst, clk);
1135
   parameter length = 4;
1136
   input cke;
1137
   input rew;
1138
   output [length:1] q;
1139
   output reg zq;
1140
   output reg level1;
1141
   input rst;
1142
   input clk;
1143
   parameter clear_value = 0;
1144
   parameter set_value = 1;
1145
   parameter wrap_value = 1;
1146
   parameter level1_value = 15;
1147 29 unneback
   wire clear;
1148 30 unneback
   assign clear = 1'b0;
1149 25 unneback
   reg  [length:1] qi;
1150
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1151
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1152
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1153
   assign q_next = rew ? q_next_rew : q_next_fw;
1154
   always @ (posedge clk or posedge rst)
1155
     if (rst)
1156
       qi <= {length{1'b0}};
1157
     else
1158
     if (cke)
1159
       qi <= q_next;
1160
   assign q = qi;
1161
   always @ (posedge clk or posedge rst)
1162
     if (rst)
1163
       zq <= 1'b1;
1164
     else
1165
     if (cke)
1166
       zq <= q_next == {length{1'b0}};
1167
    always @ (posedge clk or posedge rst)
1168
    if (rst)
1169
        level1 <= 1'b0;
1170
    else
1171
    if (cke)
1172 29 unneback
    if (clear)
1173
        level1 <= 1'b0;
1174
    else if (q_next == level1_value)
1175 25 unneback
        level1 <= 1'b1;
1176
    else if (qi == level1_value & rew)
1177
        level1 <= 1'b0;
1178
endmodule
1179
//////////////////////////////////////////////////////////////////////
1180
////                                                              ////
1181
////  Versatile counter                                           ////
1182
////                                                              ////
1183
////  Description                                                 ////
1184
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1185
////  counter                                                     ////
1186
////                                                              ////
1187
////  To Do:                                                      ////
1188
////   - add LFSR with more taps                                  ////
1189
////                                                              ////
1190
////  Author(s):                                                  ////
1191
////      - Michael Unneback, unneback@opencores.org              ////
1192
////        ORSoC AB                                              ////
1193
////                                                              ////
1194
//////////////////////////////////////////////////////////////////////
1195
////                                                              ////
1196
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1197
////                                                              ////
1198
//// This source file may be used and distributed without         ////
1199
//// restriction provided that this copyright statement is not    ////
1200
//// removed from the file and that any derivative work contains  ////
1201
//// the original copyright notice and the associated disclaimer. ////
1202
////                                                              ////
1203
//// This source file is free software; you can redistribute it   ////
1204
//// and/or modify it under the terms of the GNU Lesser General   ////
1205
//// Public License as published by the Free Software Foundation; ////
1206
//// either version 2.1 of the License, or (at your option) any   ////
1207
//// later version.                                               ////
1208
////                                                              ////
1209
//// This source is distributed in the hope that it will be       ////
1210
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1211
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1212
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1213
//// details.                                                     ////
1214
////                                                              ////
1215
//// You should have received a copy of the GNU Lesser General    ////
1216
//// Public License along with this source; if not, download it   ////
1217
//// from http://www.opencores.org/lgpl.shtml                     ////
1218
////                                                              ////
1219
//////////////////////////////////////////////////////////////////////
1220 6 unneback
// LFSR counter
1221 18 unneback
module vl_cnt_lfsr_zq ( zq, rst, clk);
1222 6 unneback
   parameter length = 4;
1223
   output reg zq;
1224
   input rst;
1225
   input clk;
1226
   parameter clear_value = 0;
1227
   parameter set_value = 1;
1228
   parameter wrap_value = 8;
1229
   parameter level1_value = 15;
1230
   reg  [length:1] qi;
1231
   reg lfsr_fb;
1232
   wire [length:1] q_next;
1233
   reg [32:1] polynom;
1234
   integer i;
1235
   always @ (qi)
1236
   begin
1237
        case (length)
1238
         2: polynom = 32'b11;                               // 0x3
1239
         3: polynom = 32'b110;                              // 0x6
1240
         4: polynom = 32'b1100;                             // 0xC
1241
         5: polynom = 32'b10100;                            // 0x14
1242
         6: polynom = 32'b110000;                           // 0x30
1243
         7: polynom = 32'b1100000;                          // 0x60
1244
         8: polynom = 32'b10111000;                         // 0xb8
1245
         9: polynom = 32'b100010000;                        // 0x110
1246
        10: polynom = 32'b1001000000;                       // 0x240
1247
        11: polynom = 32'b10100000000;                      // 0x500
1248
        12: polynom = 32'b100000101001;                     // 0x829
1249
        13: polynom = 32'b1000000001100;                    // 0x100C
1250
        14: polynom = 32'b10000000010101;                   // 0x2015
1251
        15: polynom = 32'b110000000000000;                  // 0x6000
1252
        16: polynom = 32'b1101000000001000;                 // 0xD008
1253
        17: polynom = 32'b10010000000000000;                // 0x12000
1254
        18: polynom = 32'b100000010000000000;               // 0x20400
1255
        19: polynom = 32'b1000000000000100011;              // 0x40023
1256
        20: polynom = 32'b10000010000000000000;             // 0x82000
1257
        21: polynom = 32'b101000000000000000000;            // 0x140000
1258
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1259
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1260
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1261
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1262
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1263
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1264
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1265
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1266
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1267
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1268
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1269
        default: polynom = 32'b0;
1270
        endcase
1271
        lfsr_fb = qi[length];
1272
        for (i=length-1; i>=1; i=i-1) begin
1273
            if (polynom[i])
1274
                lfsr_fb = lfsr_fb  ~^ qi[i];
1275
        end
1276
    end
1277
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1278
   always @ (posedge clk or posedge rst)
1279
     if (rst)
1280
       qi <= {length{1'b0}};
1281
     else
1282
       qi <= q_next;
1283
   always @ (posedge clk or posedge rst)
1284
     if (rst)
1285
       zq <= 1'b1;
1286
     else
1287
       zq <= q_next == {length{1'b0}};
1288
endmodule
1289
//////////////////////////////////////////////////////////////////////
1290
////                                                              ////
1291
////  Versatile counter                                           ////
1292
////                                                              ////
1293
////  Description                                                 ////
1294
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1295
////  counter                                                     ////
1296
////                                                              ////
1297
////  To Do:                                                      ////
1298
////   - add LFSR with more taps                                  ////
1299
////                                                              ////
1300
////  Author(s):                                                  ////
1301
////      - Michael Unneback, unneback@opencores.org              ////
1302
////        ORSoC AB                                              ////
1303
////                                                              ////
1304
//////////////////////////////////////////////////////////////////////
1305
////                                                              ////
1306
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1307
////                                                              ////
1308
//// This source file may be used and distributed without         ////
1309
//// restriction provided that this copyright statement is not    ////
1310
//// removed from the file and that any derivative work contains  ////
1311
//// the original copyright notice and the associated disclaimer. ////
1312
////                                                              ////
1313
//// This source file is free software; you can redistribute it   ////
1314
//// and/or modify it under the terms of the GNU Lesser General   ////
1315
//// Public License as published by the Free Software Foundation; ////
1316
//// either version 2.1 of the License, or (at your option) any   ////
1317
//// later version.                                               ////
1318
////                                                              ////
1319
//// This source is distributed in the hope that it will be       ////
1320
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1321
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1322
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1323
//// details.                                                     ////
1324
////                                                              ////
1325
//// You should have received a copy of the GNU Lesser General    ////
1326
//// Public License along with this source; if not, download it   ////
1327
//// from http://www.opencores.org/lgpl.shtml                     ////
1328
////                                                              ////
1329
//////////////////////////////////////////////////////////////////////
1330
// LFSR counter
1331 18 unneback
module vl_cnt_lfsr_ce_zq ( cke, zq, rst, clk);
1332 6 unneback
   parameter length = 4;
1333
   input cke;
1334
   output reg zq;
1335
   input rst;
1336
   input clk;
1337
   parameter clear_value = 0;
1338
   parameter set_value = 1;
1339
   parameter wrap_value = 8;
1340
   parameter level1_value = 15;
1341
   reg  [length:1] qi;
1342
   reg lfsr_fb;
1343
   wire [length:1] q_next;
1344
   reg [32:1] polynom;
1345
   integer i;
1346
   always @ (qi)
1347
   begin
1348
        case (length)
1349
         2: polynom = 32'b11;                               // 0x3
1350
         3: polynom = 32'b110;                              // 0x6
1351
         4: polynom = 32'b1100;                             // 0xC
1352
         5: polynom = 32'b10100;                            // 0x14
1353
         6: polynom = 32'b110000;                           // 0x30
1354
         7: polynom = 32'b1100000;                          // 0x60
1355
         8: polynom = 32'b10111000;                         // 0xb8
1356
         9: polynom = 32'b100010000;                        // 0x110
1357
        10: polynom = 32'b1001000000;                       // 0x240
1358
        11: polynom = 32'b10100000000;                      // 0x500
1359
        12: polynom = 32'b100000101001;                     // 0x829
1360
        13: polynom = 32'b1000000001100;                    // 0x100C
1361
        14: polynom = 32'b10000000010101;                   // 0x2015
1362
        15: polynom = 32'b110000000000000;                  // 0x6000
1363
        16: polynom = 32'b1101000000001000;                 // 0xD008
1364
        17: polynom = 32'b10010000000000000;                // 0x12000
1365
        18: polynom = 32'b100000010000000000;               // 0x20400
1366
        19: polynom = 32'b1000000000000100011;              // 0x40023
1367
        20: polynom = 32'b10000010000000000000;             // 0x82000
1368
        21: polynom = 32'b101000000000000000000;            // 0x140000
1369
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1370
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1371
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1372
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1373
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1374
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1375
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1376
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1377
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1378
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1379
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1380
        default: polynom = 32'b0;
1381
        endcase
1382
        lfsr_fb = qi[length];
1383
        for (i=length-1; i>=1; i=i-1) begin
1384
            if (polynom[i])
1385
                lfsr_fb = lfsr_fb  ~^ qi[i];
1386
        end
1387
    end
1388
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1389
   always @ (posedge clk or posedge rst)
1390
     if (rst)
1391
       qi <= {length{1'b0}};
1392
     else
1393
     if (cke)
1394
       qi <= q_next;
1395
   always @ (posedge clk or posedge rst)
1396
     if (rst)
1397
       zq <= 1'b1;
1398
     else
1399
     if (cke)
1400
       zq <= q_next == {length{1'b0}};
1401
endmodule
1402
//////////////////////////////////////////////////////////////////////
1403
////                                                              ////
1404
////  Versatile counter                                           ////
1405
////                                                              ////
1406
////  Description                                                 ////
1407
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1408
////  counter                                                     ////
1409
////                                                              ////
1410
////  To Do:                                                      ////
1411
////   - add LFSR with more taps                                  ////
1412
////                                                              ////
1413
////  Author(s):                                                  ////
1414
////      - Michael Unneback, unneback@opencores.org              ////
1415
////        ORSoC AB                                              ////
1416
////                                                              ////
1417
//////////////////////////////////////////////////////////////////////
1418
////                                                              ////
1419
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1420
////                                                              ////
1421
//// This source file may be used and distributed without         ////
1422
//// restriction provided that this copyright statement is not    ////
1423
//// removed from the file and that any derivative work contains  ////
1424
//// the original copyright notice and the associated disclaimer. ////
1425
////                                                              ////
1426
//// This source file is free software; you can redistribute it   ////
1427
//// and/or modify it under the terms of the GNU Lesser General   ////
1428
//// Public License as published by the Free Software Foundation; ////
1429
//// either version 2.1 of the License, or (at your option) any   ////
1430
//// later version.                                               ////
1431
////                                                              ////
1432
//// This source is distributed in the hope that it will be       ////
1433
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1434
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1435
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1436
//// details.                                                     ////
1437
////                                                              ////
1438
//// You should have received a copy of the GNU Lesser General    ////
1439
//// Public License along with this source; if not, download it   ////
1440
//// from http://www.opencores.org/lgpl.shtml                     ////
1441
////                                                              ////
1442
//////////////////////////////////////////////////////////////////////
1443
// LFSR counter
1444 27 unneback
module vl_cnt_lfsr_ce_q ( cke, q, rst, clk);
1445
   parameter length = 4;
1446
   input cke;
1447
   output [length:1] q;
1448
   input rst;
1449
   input clk;
1450
   parameter clear_value = 0;
1451
   parameter set_value = 1;
1452
   parameter wrap_value = 8;
1453
   parameter level1_value = 15;
1454
   reg  [length:1] qi;
1455
   reg lfsr_fb;
1456
   wire [length:1] q_next;
1457
   reg [32:1] polynom;
1458
   integer i;
1459
   always @ (qi)
1460
   begin
1461
        case (length)
1462
         2: polynom = 32'b11;                               // 0x3
1463
         3: polynom = 32'b110;                              // 0x6
1464
         4: polynom = 32'b1100;                             // 0xC
1465
         5: polynom = 32'b10100;                            // 0x14
1466
         6: polynom = 32'b110000;                           // 0x30
1467
         7: polynom = 32'b1100000;                          // 0x60
1468
         8: polynom = 32'b10111000;                         // 0xb8
1469
         9: polynom = 32'b100010000;                        // 0x110
1470
        10: polynom = 32'b1001000000;                       // 0x240
1471
        11: polynom = 32'b10100000000;                      // 0x500
1472
        12: polynom = 32'b100000101001;                     // 0x829
1473
        13: polynom = 32'b1000000001100;                    // 0x100C
1474
        14: polynom = 32'b10000000010101;                   // 0x2015
1475
        15: polynom = 32'b110000000000000;                  // 0x6000
1476
        16: polynom = 32'b1101000000001000;                 // 0xD008
1477
        17: polynom = 32'b10010000000000000;                // 0x12000
1478
        18: polynom = 32'b100000010000000000;               // 0x20400
1479
        19: polynom = 32'b1000000000000100011;              // 0x40023
1480
        20: polynom = 32'b10000010000000000000;             // 0x82000
1481
        21: polynom = 32'b101000000000000000000;            // 0x140000
1482
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1483
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1484
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1485
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1486
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1487
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1488
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1489
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1490
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1491
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1492
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1493
        default: polynom = 32'b0;
1494
        endcase
1495
        lfsr_fb = qi[length];
1496
        for (i=length-1; i>=1; i=i-1) begin
1497
            if (polynom[i])
1498
                lfsr_fb = lfsr_fb  ~^ qi[i];
1499
        end
1500
    end
1501
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1502
   always @ (posedge clk or posedge rst)
1503
     if (rst)
1504
       qi <= {length{1'b0}};
1505
     else
1506
     if (cke)
1507
       qi <= q_next;
1508
   assign q = qi;
1509
endmodule
1510
//////////////////////////////////////////////////////////////////////
1511
////                                                              ////
1512
////  Versatile counter                                           ////
1513
////                                                              ////
1514
////  Description                                                 ////
1515
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1516
////  counter                                                     ////
1517
////                                                              ////
1518
////  To Do:                                                      ////
1519
////   - add LFSR with more taps                                  ////
1520
////                                                              ////
1521
////  Author(s):                                                  ////
1522
////      - Michael Unneback, unneback@opencores.org              ////
1523
////        ORSoC AB                                              ////
1524
////                                                              ////
1525
//////////////////////////////////////////////////////////////////////
1526
////                                                              ////
1527
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1528
////                                                              ////
1529
//// This source file may be used and distributed without         ////
1530
//// restriction provided that this copyright statement is not    ////
1531
//// removed from the file and that any derivative work contains  ////
1532
//// the original copyright notice and the associated disclaimer. ////
1533
////                                                              ////
1534
//// This source file is free software; you can redistribute it   ////
1535
//// and/or modify it under the terms of the GNU Lesser General   ////
1536
//// Public License as published by the Free Software Foundation; ////
1537
//// either version 2.1 of the License, or (at your option) any   ////
1538
//// later version.                                               ////
1539
////                                                              ////
1540
//// This source is distributed in the hope that it will be       ////
1541
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1542
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1543
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1544
//// details.                                                     ////
1545
////                                                              ////
1546
//// You should have received a copy of the GNU Lesser General    ////
1547
//// Public License along with this source; if not, download it   ////
1548
//// from http://www.opencores.org/lgpl.shtml                     ////
1549
////                                                              ////
1550
//////////////////////////////////////////////////////////////////////
1551
// LFSR counter
1552
module vl_cnt_lfsr_ce_clear_q ( clear, cke, q, rst, clk);
1553
   parameter length = 4;
1554
   input clear;
1555
   input cke;
1556
   output [length:1] q;
1557
   input rst;
1558
   input clk;
1559
   parameter clear_value = 0;
1560
   parameter set_value = 1;
1561
   parameter wrap_value = 8;
1562
   parameter level1_value = 15;
1563
   reg  [length:1] qi;
1564
   reg lfsr_fb;
1565
   wire [length:1] q_next;
1566
   reg [32:1] polynom;
1567
   integer i;
1568
   always @ (qi)
1569
   begin
1570
        case (length)
1571
         2: polynom = 32'b11;                               // 0x3
1572
         3: polynom = 32'b110;                              // 0x6
1573
         4: polynom = 32'b1100;                             // 0xC
1574
         5: polynom = 32'b10100;                            // 0x14
1575
         6: polynom = 32'b110000;                           // 0x30
1576
         7: polynom = 32'b1100000;                          // 0x60
1577
         8: polynom = 32'b10111000;                         // 0xb8
1578
         9: polynom = 32'b100010000;                        // 0x110
1579
        10: polynom = 32'b1001000000;                       // 0x240
1580
        11: polynom = 32'b10100000000;                      // 0x500
1581
        12: polynom = 32'b100000101001;                     // 0x829
1582
        13: polynom = 32'b1000000001100;                    // 0x100C
1583
        14: polynom = 32'b10000000010101;                   // 0x2015
1584
        15: polynom = 32'b110000000000000;                  // 0x6000
1585
        16: polynom = 32'b1101000000001000;                 // 0xD008
1586
        17: polynom = 32'b10010000000000000;                // 0x12000
1587
        18: polynom = 32'b100000010000000000;               // 0x20400
1588
        19: polynom = 32'b1000000000000100011;              // 0x40023
1589
        20: polynom = 32'b10000010000000000000;             // 0x82000
1590
        21: polynom = 32'b101000000000000000000;            // 0x140000
1591
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1592
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1593
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1594
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1595
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1596
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1597
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1598
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1599
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1600
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1601
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1602
        default: polynom = 32'b0;
1603
        endcase
1604
        lfsr_fb = qi[length];
1605
        for (i=length-1; i>=1; i=i-1) begin
1606
            if (polynom[i])
1607
                lfsr_fb = lfsr_fb  ~^ qi[i];
1608
        end
1609
    end
1610
   assign q_next =  clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1611
   always @ (posedge clk or posedge rst)
1612
     if (rst)
1613
       qi <= {length{1'b0}};
1614
     else
1615
     if (cke)
1616
       qi <= q_next;
1617
   assign q = qi;
1618
endmodule
1619
//////////////////////////////////////////////////////////////////////
1620
////                                                              ////
1621
////  Versatile counter                                           ////
1622
////                                                              ////
1623
////  Description                                                 ////
1624
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1625
////  counter                                                     ////
1626
////                                                              ////
1627
////  To Do:                                                      ////
1628
////   - add LFSR with more taps                                  ////
1629
////                                                              ////
1630
////  Author(s):                                                  ////
1631
////      - Michael Unneback, unneback@opencores.org              ////
1632
////        ORSoC AB                                              ////
1633
////                                                              ////
1634
//////////////////////////////////////////////////////////////////////
1635
////                                                              ////
1636
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1637
////                                                              ////
1638
//// This source file may be used and distributed without         ////
1639
//// restriction provided that this copyright statement is not    ////
1640
//// removed from the file and that any derivative work contains  ////
1641
//// the original copyright notice and the associated disclaimer. ////
1642
////                                                              ////
1643
//// This source file is free software; you can redistribute it   ////
1644
//// and/or modify it under the terms of the GNU Lesser General   ////
1645
//// Public License as published by the Free Software Foundation; ////
1646
//// either version 2.1 of the License, or (at your option) any   ////
1647
//// later version.                                               ////
1648
////                                                              ////
1649
//// This source is distributed in the hope that it will be       ////
1650
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1651
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1652
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1653
//// details.                                                     ////
1654
////                                                              ////
1655
//// You should have received a copy of the GNU Lesser General    ////
1656
//// Public License along with this source; if not, download it   ////
1657
//// from http://www.opencores.org/lgpl.shtml                     ////
1658
////                                                              ////
1659
//////////////////////////////////////////////////////////////////////
1660
// LFSR counter
1661 22 unneback
module vl_cnt_lfsr_ce_q_zq ( cke, q, zq, rst, clk);
1662
   parameter length = 4;
1663
   input cke;
1664
   output [length:1] q;
1665
   output reg zq;
1666
   input rst;
1667
   input clk;
1668
   parameter clear_value = 0;
1669
   parameter set_value = 1;
1670
   parameter wrap_value = 8;
1671
   parameter level1_value = 15;
1672
   reg  [length:1] qi;
1673
   reg lfsr_fb;
1674
   wire [length:1] q_next;
1675
   reg [32:1] polynom;
1676
   integer i;
1677
   always @ (qi)
1678
   begin
1679
        case (length)
1680
         2: polynom = 32'b11;                               // 0x3
1681
         3: polynom = 32'b110;                              // 0x6
1682
         4: polynom = 32'b1100;                             // 0xC
1683
         5: polynom = 32'b10100;                            // 0x14
1684
         6: polynom = 32'b110000;                           // 0x30
1685
         7: polynom = 32'b1100000;                          // 0x60
1686
         8: polynom = 32'b10111000;                         // 0xb8
1687
         9: polynom = 32'b100010000;                        // 0x110
1688
        10: polynom = 32'b1001000000;                       // 0x240
1689
        11: polynom = 32'b10100000000;                      // 0x500
1690
        12: polynom = 32'b100000101001;                     // 0x829
1691
        13: polynom = 32'b1000000001100;                    // 0x100C
1692
        14: polynom = 32'b10000000010101;                   // 0x2015
1693
        15: polynom = 32'b110000000000000;                  // 0x6000
1694
        16: polynom = 32'b1101000000001000;                 // 0xD008
1695
        17: polynom = 32'b10010000000000000;                // 0x12000
1696
        18: polynom = 32'b100000010000000000;               // 0x20400
1697
        19: polynom = 32'b1000000000000100011;              // 0x40023
1698
        20: polynom = 32'b10000010000000000000;             // 0x82000
1699
        21: polynom = 32'b101000000000000000000;            // 0x140000
1700
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1701
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1702
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1703
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1704
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1705
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1706
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1707
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1708
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1709
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1710
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1711
        default: polynom = 32'b0;
1712
        endcase
1713
        lfsr_fb = qi[length];
1714
        for (i=length-1; i>=1; i=i-1) begin
1715
            if (polynom[i])
1716
                lfsr_fb = lfsr_fb  ~^ qi[i];
1717
        end
1718
    end
1719
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1720
   always @ (posedge clk or posedge rst)
1721
     if (rst)
1722
       qi <= {length{1'b0}};
1723
     else
1724
     if (cke)
1725
       qi <= q_next;
1726
   assign q = qi;
1727
   always @ (posedge clk or posedge rst)
1728
     if (rst)
1729
       zq <= 1'b1;
1730
     else
1731
     if (cke)
1732
       zq <= q_next == {length{1'b0}};
1733
endmodule
1734
//////////////////////////////////////////////////////////////////////
1735
////                                                              ////
1736
////  Versatile counter                                           ////
1737
////                                                              ////
1738
////  Description                                                 ////
1739
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1740
////  counter                                                     ////
1741
////                                                              ////
1742
////  To Do:                                                      ////
1743
////   - add LFSR with more taps                                  ////
1744
////                                                              ////
1745
////  Author(s):                                                  ////
1746
////      - Michael Unneback, unneback@opencores.org              ////
1747
////        ORSoC AB                                              ////
1748
////                                                              ////
1749
//////////////////////////////////////////////////////////////////////
1750
////                                                              ////
1751
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1752
////                                                              ////
1753
//// This source file may be used and distributed without         ////
1754
//// restriction provided that this copyright statement is not    ////
1755
//// removed from the file and that any derivative work contains  ////
1756
//// the original copyright notice and the associated disclaimer. ////
1757
////                                                              ////
1758
//// This source file is free software; you can redistribute it   ////
1759
//// and/or modify it under the terms of the GNU Lesser General   ////
1760
//// Public License as published by the Free Software Foundation; ////
1761
//// either version 2.1 of the License, or (at your option) any   ////
1762
//// later version.                                               ////
1763
////                                                              ////
1764
//// This source is distributed in the hope that it will be       ////
1765
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1766
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1767
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1768
//// details.                                                     ////
1769
////                                                              ////
1770
//// You should have received a copy of the GNU Lesser General    ////
1771
//// Public License along with this source; if not, download it   ////
1772
//// from http://www.opencores.org/lgpl.shtml                     ////
1773
////                                                              ////
1774
//////////////////////////////////////////////////////////////////////
1775
// LFSR counter
1776 18 unneback
module vl_cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk);
1777 6 unneback
   parameter length = 4;
1778
   input cke;
1779
   input rew;
1780
   output reg level1;
1781
   input rst;
1782
   input clk;
1783
   parameter clear_value = 0;
1784
   parameter set_value = 1;
1785
   parameter wrap_value = 8;
1786
   parameter level1_value = 15;
1787 29 unneback
   wire clear;
1788 30 unneback
   assign clear = 1'b0;
1789 6 unneback
   reg  [length:1] qi;
1790
   reg lfsr_fb, lfsr_fb_rew;
1791
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1792
   reg [32:1] polynom_rew;
1793
   integer j;
1794
   reg [32:1] polynom;
1795
   integer i;
1796
   always @ (qi)
1797
   begin
1798
        case (length)
1799
         2: polynom = 32'b11;                               // 0x3
1800
         3: polynom = 32'b110;                              // 0x6
1801
         4: polynom = 32'b1100;                             // 0xC
1802
         5: polynom = 32'b10100;                            // 0x14
1803
         6: polynom = 32'b110000;                           // 0x30
1804
         7: polynom = 32'b1100000;                          // 0x60
1805
         8: polynom = 32'b10111000;                         // 0xb8
1806
         9: polynom = 32'b100010000;                        // 0x110
1807
        10: polynom = 32'b1001000000;                       // 0x240
1808
        11: polynom = 32'b10100000000;                      // 0x500
1809
        12: polynom = 32'b100000101001;                     // 0x829
1810
        13: polynom = 32'b1000000001100;                    // 0x100C
1811
        14: polynom = 32'b10000000010101;                   // 0x2015
1812
        15: polynom = 32'b110000000000000;                  // 0x6000
1813
        16: polynom = 32'b1101000000001000;                 // 0xD008
1814
        17: polynom = 32'b10010000000000000;                // 0x12000
1815
        18: polynom = 32'b100000010000000000;               // 0x20400
1816
        19: polynom = 32'b1000000000000100011;              // 0x40023
1817
        20: polynom = 32'b10000010000000000000;             // 0x82000
1818
        21: polynom = 32'b101000000000000000000;            // 0x140000
1819
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1820
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1821
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1822
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1823
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1824
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1825
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1826
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1827
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1828
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1829
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1830
        default: polynom = 32'b0;
1831
        endcase
1832
        lfsr_fb = qi[length];
1833
        for (i=length-1; i>=1; i=i-1) begin
1834
            if (polynom[i])
1835
                lfsr_fb = lfsr_fb  ~^ qi[i];
1836
        end
1837
    end
1838
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1839
   always @ (qi)
1840
   begin
1841
        case (length)
1842
         2: polynom_rew = 32'b11;
1843
         3: polynom_rew = 32'b110;
1844
         4: polynom_rew = 32'b1100;
1845
         5: polynom_rew = 32'b10100;
1846
         6: polynom_rew = 32'b110000;
1847
         7: polynom_rew = 32'b1100000;
1848
         8: polynom_rew = 32'b10111000;
1849
         9: polynom_rew = 32'b100010000;
1850
        10: polynom_rew = 32'b1001000000;
1851
        11: polynom_rew = 32'b10100000000;
1852
        12: polynom_rew = 32'b100000101001;
1853
        13: polynom_rew = 32'b1000000001100;
1854
        14: polynom_rew = 32'b10000000010101;
1855
        15: polynom_rew = 32'b110000000000000;
1856
        16: polynom_rew = 32'b1101000000001000;
1857
        17: polynom_rew = 32'b10010000000000000;
1858
        18: polynom_rew = 32'b100000010000000000;
1859
        19: polynom_rew = 32'b1000000000000100011;
1860
        20: polynom_rew = 32'b10000010000000000000;
1861
        21: polynom_rew = 32'b101000000000000000000;
1862
        22: polynom_rew = 32'b1100000000000000000000;
1863
        23: polynom_rew = 32'b10000100000000000000000;
1864
        24: polynom_rew = 32'b111000010000000000000000;
1865
        25: polynom_rew = 32'b1001000000000000000000000;
1866
        26: polynom_rew = 32'b10000000000000000000100011;
1867
        27: polynom_rew = 32'b100000000000000000000010011;
1868
        28: polynom_rew = 32'b1100100000000000000000000000;
1869
        29: polynom_rew = 32'b10100000000000000000000000000;
1870
        30: polynom_rew = 32'b100000000000000000000000101001;
1871
        31: polynom_rew = 32'b1001000000000000000000000000000;
1872
        32: polynom_rew = 32'b10000000001000000000000000000011;
1873
        default: polynom_rew = 32'b0;
1874
        endcase
1875
        // rotate left
1876
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
1877
        lfsr_fb_rew = qi[length];
1878
        for (i=length-1; i>=1; i=i-1) begin
1879
            if (polynom_rew[i])
1880
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
1881
        end
1882
    end
1883
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
1884
   assign q_next = rew ? q_next_rew : q_next_fw;
1885
   always @ (posedge clk or posedge rst)
1886
     if (rst)
1887
       qi <= {length{1'b0}};
1888
     else
1889
     if (cke)
1890
       qi <= q_next;
1891
    always @ (posedge clk or posedge rst)
1892
    if (rst)
1893
        level1 <= 1'b0;
1894
    else
1895
    if (cke)
1896 29 unneback
    if (clear)
1897
        level1 <= 1'b0;
1898
    else if (q_next == level1_value)
1899 6 unneback
        level1 <= 1'b1;
1900
    else if (qi == level1_value & rew)
1901
        level1 <= 1'b0;
1902
endmodule
1903
//////////////////////////////////////////////////////////////////////
1904
////                                                              ////
1905
////  Versatile counter                                           ////
1906
////                                                              ////
1907
////  Description                                                 ////
1908
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1909
////  counter                                                     ////
1910
////                                                              ////
1911
////  To Do:                                                      ////
1912
////   - add LFSR with more taps                                  ////
1913
////                                                              ////
1914
////  Author(s):                                                  ////
1915
////      - Michael Unneback, unneback@opencores.org              ////
1916
////        ORSoC AB                                              ////
1917
////                                                              ////
1918
//////////////////////////////////////////////////////////////////////
1919
////                                                              ////
1920
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1921
////                                                              ////
1922
//// This source file may be used and distributed without         ////
1923
//// restriction provided that this copyright statement is not    ////
1924
//// removed from the file and that any derivative work contains  ////
1925
//// the original copyright notice and the associated disclaimer. ////
1926
////                                                              ////
1927
//// This source file is free software; you can redistribute it   ////
1928
//// and/or modify it under the terms of the GNU Lesser General   ////
1929
//// Public License as published by the Free Software Foundation; ////
1930
//// either version 2.1 of the License, or (at your option) any   ////
1931
//// later version.                                               ////
1932
////                                                              ////
1933
//// This source is distributed in the hope that it will be       ////
1934
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1935
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1936
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1937
//// details.                                                     ////
1938
////                                                              ////
1939
//// You should have received a copy of the GNU Lesser General    ////
1940
//// Public License along with this source; if not, download it   ////
1941
//// from http://www.opencores.org/lgpl.shtml                     ////
1942
////                                                              ////
1943
//////////////////////////////////////////////////////////////////////
1944
// GRAY counter
1945 18 unneback
module vl_cnt_gray ( q, rst, clk);
1946 6 unneback
   parameter length = 4;
1947
   output reg [length:1] q;
1948
   input rst;
1949
   input clk;
1950
   parameter clear_value = 0;
1951
   parameter set_value = 1;
1952
   parameter wrap_value = 8;
1953
   parameter level1_value = 15;
1954
   reg  [length:1] qi;
1955
   wire [length:1] q_next;
1956
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1957
   always @ (posedge clk or posedge rst)
1958
     if (rst)
1959
       qi <= {length{1'b0}};
1960
     else
1961
       qi <= q_next;
1962
   always @ (posedge clk or posedge rst)
1963
     if (rst)
1964
       q <= {length{1'b0}};
1965
     else
1966
         q <= (q_next>>1) ^ q_next;
1967
endmodule
1968
//////////////////////////////////////////////////////////////////////
1969
////                                                              ////
1970
////  Versatile counter                                           ////
1971
////                                                              ////
1972
////  Description                                                 ////
1973
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1974
////  counter                                                     ////
1975
////                                                              ////
1976
////  To Do:                                                      ////
1977
////   - add LFSR with more taps                                  ////
1978
////                                                              ////
1979
////  Author(s):                                                  ////
1980
////      - Michael Unneback, unneback@opencores.org              ////
1981
////        ORSoC AB                                              ////
1982
////                                                              ////
1983
//////////////////////////////////////////////////////////////////////
1984
////                                                              ////
1985
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1986
////                                                              ////
1987
//// This source file may be used and distributed without         ////
1988
//// restriction provided that this copyright statement is not    ////
1989
//// removed from the file and that any derivative work contains  ////
1990
//// the original copyright notice and the associated disclaimer. ////
1991
////                                                              ////
1992
//// This source file is free software; you can redistribute it   ////
1993
//// and/or modify it under the terms of the GNU Lesser General   ////
1994
//// Public License as published by the Free Software Foundation; ////
1995
//// either version 2.1 of the License, or (at your option) any   ////
1996
//// later version.                                               ////
1997
////                                                              ////
1998
//// This source is distributed in the hope that it will be       ////
1999
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2000
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2001
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2002
//// details.                                                     ////
2003
////                                                              ////
2004
//// You should have received a copy of the GNU Lesser General    ////
2005
//// Public License along with this source; if not, download it   ////
2006
//// from http://www.opencores.org/lgpl.shtml                     ////
2007
////                                                              ////
2008
//////////////////////////////////////////////////////////////////////
2009
// GRAY counter
2010 18 unneback
module vl_cnt_gray_ce ( cke, q, rst, clk);
2011 6 unneback
   parameter length = 4;
2012
   input cke;
2013
   output reg [length:1] q;
2014
   input rst;
2015
   input clk;
2016
   parameter clear_value = 0;
2017
   parameter set_value = 1;
2018
   parameter wrap_value = 8;
2019
   parameter level1_value = 15;
2020
   reg  [length:1] qi;
2021
   wire [length:1] q_next;
2022
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2023
   always @ (posedge clk or posedge rst)
2024
     if (rst)
2025
       qi <= {length{1'b0}};
2026
     else
2027
     if (cke)
2028
       qi <= q_next;
2029
   always @ (posedge clk or posedge rst)
2030
     if (rst)
2031
       q <= {length{1'b0}};
2032
     else
2033
       if (cke)
2034
         q <= (q_next>>1) ^ q_next;
2035
endmodule
2036
//////////////////////////////////////////////////////////////////////
2037
////                                                              ////
2038
////  Versatile counter                                           ////
2039
////                                                              ////
2040
////  Description                                                 ////
2041
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2042
////  counter                                                     ////
2043
////                                                              ////
2044
////  To Do:                                                      ////
2045
////   - add LFSR with more taps                                  ////
2046
////                                                              ////
2047
////  Author(s):                                                  ////
2048
////      - Michael Unneback, unneback@opencores.org              ////
2049
////        ORSoC AB                                              ////
2050
////                                                              ////
2051
//////////////////////////////////////////////////////////////////////
2052
////                                                              ////
2053
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2054
////                                                              ////
2055
//// This source file may be used and distributed without         ////
2056
//// restriction provided that this copyright statement is not    ////
2057
//// removed from the file and that any derivative work contains  ////
2058
//// the original copyright notice and the associated disclaimer. ////
2059
////                                                              ////
2060
//// This source file is free software; you can redistribute it   ////
2061
//// and/or modify it under the terms of the GNU Lesser General   ////
2062
//// Public License as published by the Free Software Foundation; ////
2063
//// either version 2.1 of the License, or (at your option) any   ////
2064
//// later version.                                               ////
2065
////                                                              ////
2066
//// This source is distributed in the hope that it will be       ////
2067
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2068
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2069
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2070
//// details.                                                     ////
2071
////                                                              ////
2072
//// You should have received a copy of the GNU Lesser General    ////
2073
//// Public License along with this source; if not, download it   ////
2074
//// from http://www.opencores.org/lgpl.shtml                     ////
2075
////                                                              ////
2076
//////////////////////////////////////////////////////////////////////
2077
// GRAY counter
2078 18 unneback
module vl_cnt_gray_ce_bin ( cke, q, q_bin, rst, clk);
2079 6 unneback
   parameter length = 4;
2080
   input cke;
2081
   output reg [length:1] q;
2082
   output [length:1] q_bin;
2083
   input rst;
2084
   input clk;
2085
   parameter clear_value = 0;
2086
   parameter set_value = 1;
2087
   parameter wrap_value = 8;
2088
   parameter level1_value = 15;
2089
   reg  [length:1] qi;
2090
   wire [length:1] q_next;
2091
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2092
   always @ (posedge clk or posedge rst)
2093
     if (rst)
2094
       qi <= {length{1'b0}};
2095
     else
2096
     if (cke)
2097
       qi <= q_next;
2098
   always @ (posedge clk or posedge rst)
2099
     if (rst)
2100
       q <= {length{1'b0}};
2101
     else
2102
       if (cke)
2103
         q <= (q_next>>1) ^ q_next;
2104
   assign q_bin = qi;
2105
endmodule
2106
//////////////////////////////////////////////////////////////////////
2107
////                                                              ////
2108
////  Versatile library, counters                                 ////
2109
////                                                              ////
2110
////  Description                                                 ////
2111
////  counters                                                    ////
2112
////                                                              ////
2113
////                                                              ////
2114
////  To Do:                                                      ////
2115
////   - add more counters                                        ////
2116
////                                                              ////
2117
////  Author(s):                                                  ////
2118
////      - Michael Unneback, unneback@opencores.org              ////
2119
////        ORSoC AB                                              ////
2120
////                                                              ////
2121
//////////////////////////////////////////////////////////////////////
2122
////                                                              ////
2123
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2124
////                                                              ////
2125
//// This source file may be used and distributed without         ////
2126
//// restriction provided that this copyright statement is not    ////
2127
//// removed from the file and that any derivative work contains  ////
2128
//// the original copyright notice and the associated disclaimer. ////
2129
////                                                              ////
2130
//// This source file is free software; you can redistribute it   ////
2131
//// and/or modify it under the terms of the GNU Lesser General   ////
2132
//// Public License as published by the Free Software Foundation; ////
2133
//// either version 2.1 of the License, or (at your option) any   ////
2134
//// later version.                                               ////
2135
////                                                              ////
2136
//// This source is distributed in the hope that it will be       ////
2137
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2138
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2139
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2140
//// details.                                                     ////
2141
////                                                              ////
2142
//// You should have received a copy of the GNU Lesser General    ////
2143
//// Public License along with this source; if not, download it   ////
2144
//// from http://www.opencores.org/lgpl.shtml                     ////
2145
////                                                              ////
2146
//////////////////////////////////////////////////////////////////////
2147 18 unneback
module vl_cnt_shreg_wrap ( q, rst, clk);
2148 6 unneback
   parameter length = 4;
2149
   output reg [0:length-1] q;
2150
   input rst;
2151
   input clk;
2152
    always @ (posedge clk or posedge rst)
2153
    if (rst)
2154
        q <= {1'b1,{length-1{1'b0}}};
2155
    else
2156
        q <= {q[length-1],q[0:length-2]};
2157
endmodule
2158 18 unneback
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
2159 6 unneback
   parameter length = 4;
2160
   input cke;
2161
   output reg [0:length-1] q;
2162
   input rst;
2163
   input clk;
2164
    always @ (posedge clk or posedge rst)
2165
    if (rst)
2166
        q <= {1'b1,{length-1{1'b0}}};
2167
    else
2168
        if (cke)
2169
            q <= {q[length-1],q[0:length-2]};
2170
endmodule
2171 18 unneback
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
2172 6 unneback
   parameter length = 4;
2173
   input cke, clear;
2174
   output reg [0:length-1] q;
2175
   input rst;
2176
   input clk;
2177
    always @ (posedge clk or posedge rst)
2178
    if (rst)
2179
        q <= {1'b1,{length-1{1'b0}}};
2180
    else
2181
        if (cke)
2182
            if (clear)
2183
                q <= {1'b1,{length-1{1'b0}}};
2184
            else
2185
                q <= q >> 1;
2186
endmodule
2187 18 unneback
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
2188 6 unneback
   parameter length = 4;
2189
   input cke, clear;
2190
   output reg [0:length-1] q;
2191
   input rst;
2192
   input clk;
2193
    always @ (posedge clk or posedge rst)
2194
    if (rst)
2195
        q <= {1'b1,{length-1{1'b0}}};
2196
    else
2197
        if (cke)
2198
            if (clear)
2199
                q <= {1'b1,{length-1{1'b0}}};
2200
            else
2201
            q <= {q[length-1],q[0:length-2]};
2202
endmodule
2203
//////////////////////////////////////////////////////////////////////
2204
////                                                              ////
2205
////  Versatile library, memories                                 ////
2206
////                                                              ////
2207
////  Description                                                 ////
2208
////  memories                                                    ////
2209
////                                                              ////
2210
////                                                              ////
2211
////  To Do:                                                      ////
2212
////   - add more memory types                                    ////
2213
////                                                              ////
2214
////  Author(s):                                                  ////
2215
////      - Michael Unneback, unneback@opencores.org              ////
2216
////        ORSoC AB                                              ////
2217
////                                                              ////
2218
//////////////////////////////////////////////////////////////////////
2219
////                                                              ////
2220
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2221
////                                                              ////
2222
//// This source file may be used and distributed without         ////
2223
//// restriction provided that this copyright statement is not    ////
2224
//// removed from the file and that any derivative work contains  ////
2225
//// the original copyright notice and the associated disclaimer. ////
2226
////                                                              ////
2227
//// This source file is free software; you can redistribute it   ////
2228
//// and/or modify it under the terms of the GNU Lesser General   ////
2229
//// Public License as published by the Free Software Foundation; ////
2230
//// either version 2.1 of the License, or (at your option) any   ////
2231
//// later version.                                               ////
2232
////                                                              ////
2233
//// This source is distributed in the hope that it will be       ////
2234
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2235
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2236
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2237
//// details.                                                     ////
2238
////                                                              ////
2239
//// You should have received a copy of the GNU Lesser General    ////
2240
//// Public License along with this source; if not, download it   ////
2241
//// from http://www.opencores.org/lgpl.shtml                     ////
2242
////                                                              ////
2243
//////////////////////////////////////////////////////////////////////
2244
/// ROM
2245 7 unneback
module vl_rom_init ( adr, q, clk);
2246
   parameter data_width = 32;
2247
   parameter addr_width = 8;
2248
   input [(addr_width-1):0]       adr;
2249
   output reg [(data_width-1):0] q;
2250
   input                         clk;
2251
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
2252
   parameter memory_file = "vl_rom.vmem";
2253
   initial
2254
     begin
2255
        $readmemh(memory_file, rom);
2256
     end
2257
   always @ (posedge clk)
2258
     q <= rom[adr];
2259
endmodule
2260 14 unneback
/*
2261 7 unneback
module vl_rom ( adr, q, clk);
2262 6 unneback
parameter data_width = 32;
2263
parameter addr_width = 4;
2264
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
2265
    {32'h18000000},
2266
    {32'hA8200000},
2267
    {32'hA8200000},
2268
    {32'hA8200000},
2269
    {32'h44003000},
2270
    {32'h15000000},
2271
    {32'h15000000},
2272
    {32'h15000000},
2273
    {32'h15000000},
2274
    {32'h15000000},
2275
    {32'h15000000},
2276
    {32'h15000000},
2277
    {32'h15000000},
2278
    {32'h15000000},
2279
    {32'h15000000},
2280
    {32'h15000000}};
2281 7 unneback
input [addr_width-1:0] adr;
2282 6 unneback
output reg [data_width-1:0] q;
2283
input clk;
2284
always @ (posedge clk)
2285 7 unneback
    q <= data[adr];
2286 6 unneback
endmodule
2287 14 unneback
*/
2288 6 unneback
// Single port RAM
2289
module vl_ram ( d, adr, we, q, clk);
2290
   parameter data_width = 32;
2291
   parameter addr_width = 8;
2292
   input [(data_width-1):0]      d;
2293
   input [(addr_width-1):0]       adr;
2294
   input                         we;
2295 7 unneback
   output reg [(data_width-1):0] q;
2296 6 unneback
   input                         clk;
2297
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
2298 7 unneback
   parameter init = 0;
2299
   parameter memory_file = "vl_ram.vmem";
2300
   generate if (init) begin : init_mem
2301
   initial
2302
     begin
2303
        $readmemh(memory_file, ram);
2304
     end
2305
   end
2306
   endgenerate
2307 6 unneback
   always @ (posedge clk)
2308
   begin
2309
   if (we)
2310
     ram[adr] <= d;
2311
   q <= ram[adr];
2312
   end
2313
endmodule
2314 7 unneback
module vl_ram_be ( d, adr, be, we, q, clk);
2315
   parameter data_width = 32;
2316
   parameter addr_width = 8;
2317
   input [(data_width-1):0]      d;
2318
   input [(addr_width-1):0]       adr;
2319
   input [(addr_width/4)-1:0]    be;
2320
   input                         we;
2321
   output reg [(data_width-1):0] q;
2322
   input                         clk;
2323
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
2324
   parameter init = 0;
2325
   parameter memory_file = "vl_ram.vmem";
2326
   generate if (init) begin : init_mem
2327
   initial
2328
     begin
2329
        $readmemh(memory_file, ram);
2330
     end
2331
   end
2332
   endgenerate
2333
   genvar i;
2334
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
2335
      always @ (posedge clk)
2336
      if (we & be[i])
2337
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
2338
   end
2339
   endgenerate
2340
   always @ (posedge clk)
2341
      q <= ram[adr];
2342
endmodule
2343 6 unneback
// Dual port RAM
2344
// ACTEL FPGA should not use logic to handle rw collision
2345 7 unneback
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
2346 6 unneback
   parameter data_width = 32;
2347
   parameter addr_width = 8;
2348
   input [(data_width-1):0]      d_a;
2349
   input [(addr_width-1):0]       adr_a;
2350
   input [(addr_width-1):0]       adr_b;
2351
   input                         we_a;
2352
   output [(data_width-1):0]      q_b;
2353
   input                         clk_a, clk_b;
2354
   reg [(addr_width-1):0]         adr_b_reg;
2355
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
2356 7 unneback
   parameter init = 0;
2357
   parameter memory_file = "vl_ram.vmem";
2358
   generate if (init) begin : init_mem
2359
   initial
2360
     begin
2361
        $readmemh(memory_file, ram);
2362
     end
2363
   end
2364
   endgenerate
2365 6 unneback
   always @ (posedge clk_a)
2366
   if (we_a)
2367
     ram[adr_a] <= d_a;
2368
   always @ (posedge clk_b)
2369
   adr_b_reg <= adr_b;
2370
   assign q_b = ram[adr_b_reg];
2371
endmodule
2372 7 unneback
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
2373 6 unneback
   parameter data_width = 32;
2374
   parameter addr_width = 8;
2375
   input [(data_width-1):0]      d_a;
2376
   input [(addr_width-1):0]       adr_a;
2377
   input [(addr_width-1):0]       adr_b;
2378
   input                         we_a;
2379
   output [(data_width-1):0]      q_b;
2380
   output reg [(data_width-1):0] q_a;
2381
   input                         clk_a, clk_b;
2382
   reg [(data_width-1):0]         q_b;
2383
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
2384 7 unneback
   parameter init = 0;
2385
   parameter memory_file = "vl_ram.vmem";
2386
   generate if (init) begin : init_mem
2387
   initial
2388
     begin
2389
        $readmemh(memory_file, ram);
2390
     end
2391
   end
2392
   endgenerate
2393 6 unneback
   always @ (posedge clk_a)
2394
     begin
2395
        q_a <= ram[adr_a];
2396
        if (we_a)
2397
             ram[adr_a] <= d_a;
2398
     end
2399
   always @ (posedge clk_b)
2400
          q_b <= ram[adr_b];
2401
endmodule
2402 7 unneback
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
2403 6 unneback
   parameter data_width = 32;
2404
   parameter addr_width = 8;
2405
   input [(data_width-1):0]      d_a;
2406
   input [(addr_width-1):0]       adr_a;
2407
   input [(addr_width-1):0]       adr_b;
2408
   input                         we_a;
2409
   output [(data_width-1):0]      q_b;
2410
   input [(data_width-1):0]       d_b;
2411
   output reg [(data_width-1):0] q_a;
2412
   input                         we_b;
2413
   input                         clk_a, clk_b;
2414
   reg [(data_width-1):0]         q_b;
2415
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
2416 7 unneback
   parameter init = 0;
2417
   parameter memory_file = "vl_ram.vmem";
2418
   generate if (init) begin : init_mem
2419
   initial
2420
     begin
2421
        $readmemh(memory_file, ram);
2422
     end
2423
   end
2424
   endgenerate
2425 6 unneback
   always @ (posedge clk_a)
2426
     begin
2427
        q_a <= ram[adr_a];
2428
        if (we_a)
2429
             ram[adr_a] <= d_a;
2430
     end
2431
   always @ (posedge clk_b)
2432
     begin
2433
        q_b <= ram[adr_b];
2434
        if (we_b)
2435
          ram[adr_b] <= d_b;
2436
     end
2437
endmodule
2438
// Content addresable memory, CAM
2439
// FIFO
2440 25 unneback
module vl_fifo_1r1w_fill_level_sync (
2441
    d, wr, fifo_full,
2442
    q, rd, fifo_empty,
2443
    fill_level,
2444
    clk, rst
2445
    );
2446
parameter data_width = 18;
2447
parameter addr_width = 4;
2448
// write side
2449
input  [data_width-1:0] d;
2450
input                   wr;
2451
output                  fifo_full;
2452
// read side
2453
output [data_width-1:0] q;
2454
input                   rd;
2455
output                  fifo_empty;
2456
// common
2457
output [addr_width:0]   fill_level;
2458
input rst, clk;
2459
wire [addr_width:1] wadr, radr;
2460
vl_cnt_bin_ce
2461
    # ( .length(addr_width))
2462
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
2463
vl_cnt_bin_ce
2464
    # (.length(addr_width))
2465
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
2466
vl_dpram_1r1w
2467
    # (.data_width(data_width), .addr_width(addr_width))
2468
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
2469 31 unneback
vl_cnt_bin_ce_rew_q_zq_l1
2470 27 unneback
    # (.length(addr_width+1), .level1_value(1<<addr_width))
2471 25 unneback
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
2472
endmodule
2473 27 unneback
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
2474
// RAM is supposed to be larger than the two FIFOs
2475
// LFSR counters used adr pointers
2476
module vl_fifo_2r2w_sync_simplex (
2477
    // a side
2478
    a_d, a_wr, a_fifo_full,
2479
    a_q, a_rd, a_fifo_empty,
2480
    a_fill_level,
2481
    // b side
2482
    b_d, b_wr, b_fifo_full,
2483
    b_q, b_rd, b_fifo_empty,
2484
    b_fill_level,
2485
    // common
2486
    clk, rst
2487
    );
2488
parameter data_width = 8;
2489
parameter addr_width = 5;
2490
parameter fifo_full_level = (1<<addr_width)-1;
2491
// a side
2492
input  [data_width-1:0] a_d;
2493
input                   a_wr;
2494
output                  a_fifo_full;
2495
output [data_width-1:0] a_q;
2496
input                   a_rd;
2497
output                  a_fifo_empty;
2498
output [addr_width-1:0] a_fill_level;
2499
// b side
2500
input  [data_width-1:0] b_d;
2501
input                   b_wr;
2502
output                  b_fifo_full;
2503
output [data_width-1:0] b_q;
2504
input                   b_rd;
2505
output                  b_fifo_empty;
2506
output [addr_width-1:0] b_fill_level;
2507
input                   clk;
2508
input                   rst;
2509
// adr_gen
2510
wire [addr_width:1] a_wadr, a_radr;
2511
wire [addr_width:1] b_wadr, b_radr;
2512
// dpram
2513
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
2514
vl_cnt_lfsr_ce
2515
    # ( .length(addr_width))
2516
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
2517
vl_cnt_lfsr_ce
2518
    # (.length(addr_width))
2519
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
2520
vl_cnt_lfsr_ce
2521
    # ( .length(addr_width))
2522
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
2523
vl_cnt_lfsr_ce
2524
    # (.length(addr_width))
2525
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
2526
// mux read or write adr to DPRAM
2527
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
2528
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
2529
vl_dpram_2r2w
2530
    # (.data_width(data_width), .addr_width(addr_width+1))
2531
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
2532
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
2533
vl_cnt_bin_ce_rew_zq_l1
2534 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
2535 27 unneback
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
2536
vl_cnt_bin_ce_rew_zq_l1
2537 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
2538 27 unneback
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
2539
endmodule
2540 6 unneback
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
2541 11 unneback
   parameter addr_width = 4;
2542
   parameter N = addr_width-1;
2543 6 unneback
   parameter Q1 = 2'b00;
2544
   parameter Q2 = 2'b01;
2545
   parameter Q3 = 2'b11;
2546
   parameter Q4 = 2'b10;
2547
   parameter going_empty = 1'b0;
2548
   parameter going_full  = 1'b1;
2549
   input [N:0]  wptr, rptr;
2550 14 unneback
   output       fifo_empty;
2551 6 unneback
   output       fifo_full;
2552
   input        wclk, rclk, rst;
2553
   wire direction;
2554
   reg  direction_set, direction_clr;
2555
   wire async_empty, async_full;
2556
   wire fifo_full2;
2557 14 unneback
   wire fifo_empty2;
2558 6 unneback
   // direction_set
2559
   always @ (wptr[N:N-1] or rptr[N:N-1])
2560
     case ({wptr[N:N-1],rptr[N:N-1]})
2561
       {Q1,Q2} : direction_set <= 1'b1;
2562
       {Q2,Q3} : direction_set <= 1'b1;
2563
       {Q3,Q4} : direction_set <= 1'b1;
2564
       {Q4,Q1} : direction_set <= 1'b1;
2565
       default : direction_set <= 1'b0;
2566
     endcase
2567
   // direction_clear
2568
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
2569
     if (rst)
2570
       direction_clr <= 1'b1;
2571
     else
2572
       case ({wptr[N:N-1],rptr[N:N-1]})
2573
         {Q2,Q1} : direction_clr <= 1'b1;
2574
         {Q3,Q2} : direction_clr <= 1'b1;
2575
         {Q4,Q3} : direction_clr <= 1'b1;
2576
         {Q1,Q4} : direction_clr <= 1'b1;
2577
         default : direction_clr <= 1'b0;
2578
       endcase
2579 18 unneback
    vl_dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
2580