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1 6 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
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////  Versatile library, clock and reset                          ////
4
////                                                              ////
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////  Description                                                 ////
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////  Logic related to clock and reset                            ////
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////                                                              ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - add more different registers                             ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
14
////        ORSoC AB                                              ////
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////                                                              ////
16
//////////////////////////////////////////////////////////////////////
17
////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
19
////                                                              ////
20
//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
36
////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
// Global buffer
43
// usage:
44
// use to enable global buffers for high fan out signals such as clock and reset
45
`timescale 1 ns/100 ps
46
// Version: 8.4 8.4.0.33
47
module gbuf(GL,CLK);
48
output GL;
49
input  CLK;
50
    wire GND;
51
    GND GND_1_net(.Y(GND));
52
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
53
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
54
endmodule
55
`timescale 1 ns/1 ns
56
module vl_gbuf ( i, o);
57
input i;
58
output o;
59
`ifdef SIM_GBUF
60
assign o=i;
61
`else
62
gbuf gbuf_i0 ( .CLK(i), .GL(o));
63
`endif
64
endmodule
65
 //ACTEL
66
// sync reset
67 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
68 6 unneback
// output active high global reset sync with two DFFs 
69
`timescale 1 ns/100 ps
70
module vl_sync_rst ( rst_n_i, rst_o, clk);
71
input rst_n_i, clk;
72
output rst_o;
73 18 unneback
reg [1:0] tmp;
74 6 unneback
always @ (posedge clk or negedge rst_n_i)
75
if (!rst_n_i)
76 17 unneback
        tmp <= 2'b11;
77 6 unneback
else
78 33 unneback
        tmp <= {1'b0,tmp[1]};
79 17 unneback
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
80 6 unneback
endmodule
81
// vl_pll
82 32 unneback
///////////////////////////////////////////////////////////////////////////////
83 17 unneback
`timescale 1 ps/1 ps
84 6 unneback
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
85
parameter index = 0;
86
parameter number_of_clk = 1;
87 17 unneback
parameter period_time_0 = 20000;
88
parameter period_time_1 = 20000;
89
parameter period_time_2 = 20000;
90
parameter lock_delay = 2000000;
91 6 unneback
input clk_i, rst_n_i;
92
output lock;
93
output reg [0:number_of_clk-1] clk_o;
94
output [0:number_of_clk-1] rst_o;
95
`ifdef SIM_PLL
96
always
97
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
98
generate if (number_of_clk > 1)
99
always
100
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
101
endgenerate
102
generate if (number_of_clk > 2)
103
always
104
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
105
endgenerate
106
genvar i;
107
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
108
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
109
end
110
endgenerate
111
assign #lock_delay lock = rst_n_i;
112
endmodule
113
`else
114
generate if (number_of_clk==1 & index==0) begin
115
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
116
end
117
endgenerate // index==0
118
generate if (number_of_clk==1 & index==1) begin
119
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
120
end
121
endgenerate // index==1
122
generate if (number_of_clk==1 & index==2) begin
123
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
124
end
125
endgenerate // index==2
126
generate if (number_of_clk==1 & index==3) begin
127
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
128
end
129
endgenerate // index==0
130
generate if (number_of_clk==2 & index==0) begin
131
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
132
end
133
endgenerate // index==0
134
generate if (number_of_clk==2 & index==1) begin
135
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
136
end
137
endgenerate // index==1
138
generate if (number_of_clk==2 & index==2) begin
139
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
140
end
141
endgenerate // index==2
142
generate if (number_of_clk==2 & index==3) begin
143
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
144
end
145
endgenerate // index==0
146
generate if (number_of_clk==3 & index==0) begin
147
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
148
end
149
endgenerate // index==0
150
generate if (number_of_clk==3 & index==1) begin
151
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
152
end
153
endgenerate // index==1
154
generate if (number_of_clk==3 & index==2) begin
155
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
156
end
157
endgenerate // index==2
158
generate if (number_of_clk==3 & index==3) begin
159
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
160
end
161
endgenerate // index==0
162
genvar i;
163
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
164
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
165
end
166
endgenerate
167
endmodule
168
`endif
169 32 unneback
///////////////////////////////////////////////////////////////////////////////
170 6 unneback
 //actel
171
//////////////////////////////////////////////////////////////////////
172
////                                                              ////
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////  Versatile library, registers                                ////
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////                                                              ////
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////  Description                                                 ////
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////  Different type of registers                                 ////
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////                                                              ////
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////                                                              ////
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////  To Do:                                                      ////
180
////   - add more different registers                             ////
181
////                                                              ////
182
////  Author(s):                                                  ////
183
////      - Michael Unneback, unneback@opencores.org              ////
184
////        ORSoC AB                                              ////
185
////                                                              ////
186
//////////////////////////////////////////////////////////////////////
187
////                                                              ////
188
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
189
////                                                              ////
190
//// This source file may be used and distributed without         ////
191
//// restriction provided that this copyright statement is not    ////
192
//// removed from the file and that any derivative work contains  ////
193
//// the original copyright notice and the associated disclaimer. ////
194
////                                                              ////
195
//// This source file is free software; you can redistribute it   ////
196
//// and/or modify it under the terms of the GNU Lesser General   ////
197
//// Public License as published by the Free Software Foundation; ////
198
//// either version 2.1 of the License, or (at your option) any   ////
199
//// later version.                                               ////
200
////                                                              ////
201
//// This source is distributed in the hope that it will be       ////
202
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
203
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
204
//// PURPOSE.  See the GNU Lesser General Public License for more ////
205
//// details.                                                     ////
206
////                                                              ////
207
//// You should have received a copy of the GNU Lesser General    ////
208
//// Public License along with this source; if not, download it   ////
209
//// from http://www.opencores.org/lgpl.shtml                     ////
210
////                                                              ////
211
//////////////////////////////////////////////////////////////////////
212 18 unneback
module vl_dff ( d, q, clk, rst);
213 6 unneback
        parameter width = 1;
214
        parameter reset_value = 0;
215
        input [width-1:0] d;
216
        input clk, rst;
217
        output reg [width-1:0] q;
218
        always @ (posedge clk or posedge rst)
219
        if (rst)
220
                q <= reset_value;
221
        else
222
                q <= d;
223
endmodule
224 18 unneback
module vl_dff_array ( d, q, clk, rst);
225 6 unneback
        parameter width = 1;
226
        parameter depth = 2;
227
        parameter reset_value = 1'b0;
228
        input [width-1:0] d;
229
        input clk, rst;
230
        output [width-1:0] q;
231
        reg  [0:depth-1] q_tmp [width-1:0];
232
        integer i;
233
        always @ (posedge clk or posedge rst)
234
        if (rst) begin
235
            for (i=0;i<depth;i=i+1)
236
                q_tmp[i] <= {width{reset_value}};
237
        end else begin
238
            q_tmp[0] <= d;
239
            for (i=1;i<depth;i=i+1)
240
                q_tmp[i] <= q_tmp[i-1];
241
        end
242
    assign q = q_tmp[depth-1];
243
endmodule
244 18 unneback
module vl_dff_ce ( d, ce, q, clk, rst);
245 6 unneback
        parameter width = 1;
246
        parameter reset_value = 0;
247
        input [width-1:0] d;
248
        input ce, clk, rst;
249
        output reg [width-1:0] q;
250
        always @ (posedge clk or posedge rst)
251
        if (rst)
252
                q <= reset_value;
253
        else
254
                if (ce)
255
                        q <= d;
256
endmodule
257 18 unneback
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
258 8 unneback
        parameter width = 1;
259
        parameter reset_value = 0;
260
        input [width-1:0] d;
261 10 unneback
        input ce, clear, clk, rst;
262 8 unneback
        output reg [width-1:0] q;
263
        always @ (posedge clk or posedge rst)
264
        if (rst)
265
            q <= reset_value;
266
        else
267
            if (ce)
268
                if (clear)
269
                    q <= {width{1'b0}};
270
                else
271
                    q <= d;
272
endmodule
273 24 unneback
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
274
        parameter width = 1;
275
        parameter reset_value = 0;
276
        input [width-1:0] d;
277
        input ce, set, clk, rst;
278
        output reg [width-1:0] q;
279
        always @ (posedge clk or posedge rst)
280
        if (rst)
281
            q <= reset_value;
282
        else
283
            if (ce)
284
                if (set)
285
                    q <= {width{1'b1}};
286
                else
287
                    q <= d;
288
endmodule
289 29 unneback
module vl_spr ( sp, r, q, clk, rst);
290
        parameter width = 1;
291
        parameter reset_value = 0;
292
        input sp, r;
293
        output reg q;
294
        input clk, rst;
295
        always @ (posedge clk or posedge rst)
296
        if (rst)
297
            q <= reset_value;
298
        else
299
            if (sp)
300
                q <= 1'b1;
301
            else if (r)
302
                q <= 1'b0;
303
endmodule
304
module vl_srp ( s, rp, q, clk, rst);
305
        parameter width = 1;
306
        parameter reset_value = 0;
307
        input s, rp;
308
        output reg q;
309
        input clk, rst;
310
        always @ (posedge clk or posedge rst)
311
        if (rst)
312
            q <= reset_value;
313
        else
314
            if (rp)
315
                q <= 1'b0;
316
            else if (s)
317
                q <= 1'b1;
318
endmodule
319 18 unneback
module vl_dff_sr ( aclr, aset, clock, data, q);
320 6 unneback
    input         aclr;
321
    input         aset;
322
    input         clock;
323
    input         data;
324
    output reg    q;
325
   always @ (posedge clock or posedge aclr or posedge aset)
326
     if (aclr)
327
       q <= 1'b0;
328
     else if (aset)
329
       q <= 1'b1;
330
     else
331
       q <= data;
332
endmodule
333
// LATCH
334
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
335
module latch ( d, le, q, clk);
336
input d, le;
337
output q;
338
input clk;/*
339
   always @ (posedge direction_set or posedge direction_clr)
340
     if (direction_clr)
341
       direction <= going_empty;
342
     else
343
       direction <= going_full;*/
344
endmodule
345 18 unneback
module vl_shreg ( d, q, clk, rst);
346 17 unneback
parameter depth = 10;
347
input d;
348
output q;
349
input clk, rst;
350
reg [1:depth] dffs;
351
always @ (posedge clk or posedge rst)
352
if (rst)
353
    dffs <= {depth{1'b0}};
354
else
355
    dffs <= {d,dffs[1:depth-1]};
356
assign q = dffs[depth];
357
endmodule
358 18 unneback
module vl_shreg_ce ( d, ce, q, clk, rst);
359 17 unneback
parameter depth = 10;
360
input d, ce;
361
output q;
362
input clk, rst;
363
reg [1:depth] dffs;
364
always @ (posedge clk or posedge rst)
365
if (rst)
366
    dffs <= {depth{1'b0}};
367
else
368
    if (ce)
369
        dffs <= {d,dffs[1:depth-1]};
370
assign q = dffs[depth];
371
endmodule
372 18 unneback
module vl_delay ( d, q, clk, rst);
373 15 unneback
parameter depth = 10;
374
input d;
375
output q;
376
input clk, rst;
377
reg [1:depth] dffs;
378
always @ (posedge clk or posedge rst)
379
if (rst)
380
    dffs <= {depth{1'b0}};
381
else
382
    dffs <= {d,dffs[1:depth-1]};
383
assign q = dffs[depth];
384
endmodule
385 18 unneback
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
386 17 unneback
parameter depth = 10;
387
input d;
388
output q, emptyflag;
389
input clk, rst;
390
reg [1:depth] dffs;
391
always @ (posedge clk or posedge rst)
392
if (rst)
393
    dffs <= {depth{1'b0}};
394
else
395
    dffs <= {d,dffs[1:depth-1]};
396
assign q = dffs[depth];
397
assign emptyflag = !(|dffs);
398
endmodule
399 6 unneback
//////////////////////////////////////////////////////////////////////
400
////                                                              ////
401 18 unneback
////  Logic functions                                             ////
402
////                                                              ////
403
////  Description                                                 ////
404
////  Logic functions such as multiplexers                        ////
405
////                                                              ////
406
////                                                              ////
407
////  To Do:                                                      ////
408
////   -                                                          ////
409
////                                                              ////
410
////  Author(s):                                                  ////
411
////      - Michael Unneback, unneback@opencores.org              ////
412
////        ORSoC AB                                              ////
413
////                                                              ////
414
//////////////////////////////////////////////////////////////////////
415
////                                                              ////
416
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
417
////                                                              ////
418
//// This source file may be used and distributed without         ////
419
//// restriction provided that this copyright statement is not    ////
420
//// removed from the file and that any derivative work contains  ////
421
//// the original copyright notice and the associated disclaimer. ////
422
////                                                              ////
423
//// This source file is free software; you can redistribute it   ////
424
//// and/or modify it under the terms of the GNU Lesser General   ////
425
//// Public License as published by the Free Software Foundation; ////
426
//// either version 2.1 of the License, or (at your option) any   ////
427
//// later version.                                               ////
428
////                                                              ////
429
//// This source is distributed in the hope that it will be       ////
430
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
431
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
432
//// PURPOSE.  See the GNU Lesser General Public License for more ////
433
//// details.                                                     ////
434
////                                                              ////
435
//// You should have received a copy of the GNU Lesser General    ////
436
//// Public License along with this source; if not, download it   ////
437
//// from http://www.opencores.org/lgpl.shtml                     ////
438
////                                                              ////
439
//////////////////////////////////////////////////////////////////////
440 36 unneback
module vl_mux_andor ( a, sel, dout);
441
parameter width = 32;
442
parameter nr_of_ports = 4;
443
input [nr_of_ports*width-1:0] a;
444
input [nr_of_ports-1:0] sel;
445
output reg [width-1:0] dout;
446
always @ (a, sel)
447
begin
448
    dout = a[width-1:0] & {width{sel[0]}};
449
    for (i=nr_of_ports-2;i<nr_of_ports;i=i+1)
450
        dout = (a[i*width-1:(i-1)*width] & {width{sel[i]}}) | dout;
451
end
452
endmodule
453 34 unneback
module vl_mux2_andor ( a1, a0, sel, dout);
454
parameter width = 32;
455 35 unneback
localparam nr_of_ports = 2;
456 34 unneback
input [width-1:0] a1, a0;
457
input [nr_of_ports-1:0] sel;
458
output [width-1:0] dout;
459 36 unneback
vl_mux_andor
460
    # ( .width(width), .nr_of_ports(nr_of_ports)
461
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
462
/*
463 34 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
464
integer i;
465
// and
466
assign tmp[0] = {width{sel[0]}} & a0;
467
assign tmp[1] = {width{sel[1]}} & a1;
468
// or
469
assign dout = tmp[1] | tmp[0];
470 36 unneback
*/
471 34 unneback
endmodule
472
module vl_mux3_andor ( a2, a1, a0, sel, dout);
473
parameter width = 32;
474 35 unneback
localparam nr_of_ports = 3;
475 34 unneback
input [width-1:0] a2, a1, a0;
476
input [nr_of_ports-1:0] sel;
477
output [width-1:0] dout;
478 36 unneback
vl_mux_andor
479
    # ( .width(width), .nr_of_ports(nr_of_ports)
480
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
481
/*
482 34 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
483
integer i;
484
// and
485
assign tmp[0] = {width{sel[0]}} & a0;
486
assign tmp[1] = {width{sel[1]}} & a1;
487
assign tmp[2] = {width{sel[2]}} & a2;
488
// or
489
assign dout = tmp[2] | tmp[1] | tmp[0];
490 36 unneback
*/
491 34 unneback
endmodule
492 18 unneback
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
493
parameter width = 32;
494 35 unneback
localparam nr_of_ports = 4;
495 18 unneback
input [width-1:0] a3, a2, a1, a0;
496
input [nr_of_ports-1:0] sel;
497 22 unneback
output [width-1:0] dout;
498 36 unneback
vl_mux_andor
499
    # ( .width(width), .nr_of_ports(nr_of_ports)
500
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
501
/*
502 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
503 18 unneback
integer i;
504
// and
505
assign tmp[0] = {width{sel[0]}} & a0;
506
assign tmp[1] = {width{sel[1]}} & a1;
507
assign tmp[2] = {width{sel[2]}} & a2;
508
assign tmp[3] = {width{sel[3]}} & a3;
509
// or
510
assign dout = tmp[3] | tmp[2] | tmp[1] | tmp[0];
511 36 unneback
*/
512 18 unneback
endmodule
513
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
514
parameter width = 32;
515 35 unneback
localparam nr_of_ports = 5;
516 18 unneback
input [width-1:0] a4, a3, a2, a1, a0;
517
input [nr_of_ports-1:0] sel;
518 22 unneback
output [width-1:0] dout;
519 36 unneback
vl_mux_andor
520
    # ( .width(width), .nr_of_ports(nr_of_ports)
521
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
522
/*
523 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
524 18 unneback
integer i;
525
// and
526
assign tmp[0] = {width{sel[0]}} & a0;
527
assign tmp[1] = {width{sel[1]}} & a1;
528
assign tmp[2] = {width{sel[2]}} & a2;
529
assign tmp[3] = {width{sel[3]}} & a3;
530
assign tmp[4] = {width{sel[4]}} & a4;
531
// or
532
assign dout = tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
533 36 unneback
*/
534 18 unneback
endmodule
535
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
536
parameter width = 32;
537 35 unneback
localparam nr_of_ports = 6;
538 18 unneback
input [width-1:0] a5, a4, a3, a2, a1, a0;
539
input [nr_of_ports-1:0] sel;
540 22 unneback
output [width-1:0] dout;
541 36 unneback
vl_mux_andor
542
    # ( .width(width), .nr_of_ports(nr_of_ports)
543
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
544
/*
545 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
546 18 unneback
integer i;
547
// and
548
assign tmp[0] = {width{sel[0]}} & a0;
549
assign tmp[1] = {width{sel[1]}} & a1;
550
assign tmp[2] = {width{sel[2]}} & a2;
551
assign tmp[3] = {width{sel[3]}} & a3;
552
assign tmp[4] = {width{sel[4]}} & a4;
553
assign tmp[5] = {width{sel[5]}} & a5;
554
// or
555
assign dout = tmp[5] | tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
556 36 unneback
*/
557 18 unneback
endmodule
558
//////////////////////////////////////////////////////////////////////
559
////                                                              ////
560 6 unneback
////  Versatile counter                                           ////
561
////                                                              ////
562
////  Description                                                 ////
563
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
564
////  counter                                                     ////
565
////                                                              ////
566
////  To Do:                                                      ////
567
////   - add LFSR with more taps                                  ////
568
////                                                              ////
569
////  Author(s):                                                  ////
570
////      - Michael Unneback, unneback@opencores.org              ////
571
////        ORSoC AB                                              ////
572
////                                                              ////
573
//////////////////////////////////////////////////////////////////////
574
////                                                              ////
575
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
576
////                                                              ////
577
//// This source file may be used and distributed without         ////
578
//// restriction provided that this copyright statement is not    ////
579
//// removed from the file and that any derivative work contains  ////
580
//// the original copyright notice and the associated disclaimer. ////
581
////                                                              ////
582
//// This source file is free software; you can redistribute it   ////
583
//// and/or modify it under the terms of the GNU Lesser General   ////
584
//// Public License as published by the Free Software Foundation; ////
585
//// either version 2.1 of the License, or (at your option) any   ////
586
//// later version.                                               ////
587
////                                                              ////
588
//// This source is distributed in the hope that it will be       ////
589
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
590
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
591
//// PURPOSE.  See the GNU Lesser General Public License for more ////
592
//// details.                                                     ////
593
////                                                              ////
594
//// You should have received a copy of the GNU Lesser General    ////
595
//// Public License along with this source; if not, download it   ////
596
//// from http://www.opencores.org/lgpl.shtml                     ////
597
////                                                              ////
598
//////////////////////////////////////////////////////////////////////
599
// binary counter
600 22 unneback
module vl_cnt_bin ( q, rst, clk);
601
   parameter length = 4;
602
   output [length:1] q;
603
   input rst;
604
   input clk;
605
   parameter clear_value = 0;
606
   parameter set_value = 1;
607
   parameter wrap_value = 0;
608
   parameter level1_value = 15;
609
   reg  [length:1] qi;
610
   wire [length:1] q_next;
611
   assign q_next = qi + {{length-1{1'b0}},1'b1};
612
   always @ (posedge clk or posedge rst)
613
     if (rst)
614
       qi <= {length{1'b0}};
615
     else
616
       qi <= q_next;
617
   assign q = qi;
618
endmodule
619
//////////////////////////////////////////////////////////////////////
620
////                                                              ////
621
////  Versatile counter                                           ////
622
////                                                              ////
623
////  Description                                                 ////
624
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
625
////  counter                                                     ////
626
////                                                              ////
627
////  To Do:                                                      ////
628
////   - add LFSR with more taps                                  ////
629
////                                                              ////
630
////  Author(s):                                                  ////
631
////      - Michael Unneback, unneback@opencores.org              ////
632
////        ORSoC AB                                              ////
633
////                                                              ////
634
//////////////////////////////////////////////////////////////////////
635
////                                                              ////
636
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
637
////                                                              ////
638
//// This source file may be used and distributed without         ////
639
//// restriction provided that this copyright statement is not    ////
640
//// removed from the file and that any derivative work contains  ////
641
//// the original copyright notice and the associated disclaimer. ////
642
////                                                              ////
643
//// This source file is free software; you can redistribute it   ////
644
//// and/or modify it under the terms of the GNU Lesser General   ////
645
//// Public License as published by the Free Software Foundation; ////
646
//// either version 2.1 of the License, or (at your option) any   ////
647
//// later version.                                               ////
648
////                                                              ////
649
//// This source is distributed in the hope that it will be       ////
650
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
651
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
652
//// PURPOSE.  See the GNU Lesser General Public License for more ////
653
//// details.                                                     ////
654
////                                                              ////
655
//// You should have received a copy of the GNU Lesser General    ////
656
//// Public License along with this source; if not, download it   ////
657
//// from http://www.opencores.org/lgpl.shtml                     ////
658
////                                                              ////
659
//////////////////////////////////////////////////////////////////////
660
// binary counter
661
module vl_cnt_bin_clear ( clear, q, rst, clk);
662
   parameter length = 4;
663
   input clear;
664
   output [length:1] q;
665
   input rst;
666
   input clk;
667
   parameter clear_value = 0;
668
   parameter set_value = 1;
669
   parameter wrap_value = 0;
670
   parameter level1_value = 15;
671
   reg  [length:1] qi;
672
   wire [length:1] q_next;
673
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
674
   always @ (posedge clk or posedge rst)
675
     if (rst)
676
       qi <= {length{1'b0}};
677
     else
678
       qi <= q_next;
679
   assign q = qi;
680
endmodule
681
//////////////////////////////////////////////////////////////////////
682
////                                                              ////
683
////  Versatile counter                                           ////
684
////                                                              ////
685
////  Description                                                 ////
686
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
687
////  counter                                                     ////
688
////                                                              ////
689
////  To Do:                                                      ////
690
////   - add LFSR with more taps                                  ////
691
////                                                              ////
692
////  Author(s):                                                  ////
693
////      - Michael Unneback, unneback@opencores.org              ////
694
////        ORSoC AB                                              ////
695
////                                                              ////
696
//////////////////////////////////////////////////////////////////////
697
////                                                              ////
698
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
699
////                                                              ////
700
//// This source file may be used and distributed without         ////
701
//// restriction provided that this copyright statement is not    ////
702
//// removed from the file and that any derivative work contains  ////
703
//// the original copyright notice and the associated disclaimer. ////
704
////                                                              ////
705
//// This source file is free software; you can redistribute it   ////
706
//// and/or modify it under the terms of the GNU Lesser General   ////
707
//// Public License as published by the Free Software Foundation; ////
708
//// either version 2.1 of the License, or (at your option) any   ////
709
//// later version.                                               ////
710
////                                                              ////
711
//// This source is distributed in the hope that it will be       ////
712
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
713
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
714
//// PURPOSE.  See the GNU Lesser General Public License for more ////
715
//// details.                                                     ////
716
////                                                              ////
717
//// You should have received a copy of the GNU Lesser General    ////
718
//// Public License along with this source; if not, download it   ////
719
//// from http://www.opencores.org/lgpl.shtml                     ////
720
////                                                              ////
721
//////////////////////////////////////////////////////////////////////
722
// binary counter
723 18 unneback
module vl_cnt_bin_ce ( cke, q, rst, clk);
724 6 unneback
   parameter length = 4;
725
   input cke;
726
   output [length:1] q;
727
   input rst;
728
   input clk;
729
   parameter clear_value = 0;
730
   parameter set_value = 1;
731
   parameter wrap_value = 0;
732
   parameter level1_value = 15;
733
   reg  [length:1] qi;
734
   wire [length:1] q_next;
735
   assign q_next = qi + {{length-1{1'b0}},1'b1};
736
   always @ (posedge clk or posedge rst)
737
     if (rst)
738
       qi <= {length{1'b0}};
739
     else
740
     if (cke)
741
       qi <= q_next;
742
   assign q = qi;
743
endmodule
744
//////////////////////////////////////////////////////////////////////
745
////                                                              ////
746
////  Versatile counter                                           ////
747
////                                                              ////
748
////  Description                                                 ////
749
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
750
////  counter                                                     ////
751
////                                                              ////
752
////  To Do:                                                      ////
753
////   - add LFSR with more taps                                  ////
754
////                                                              ////
755
////  Author(s):                                                  ////
756
////      - Michael Unneback, unneback@opencores.org              ////
757
////        ORSoC AB                                              ////
758
////                                                              ////
759
//////////////////////////////////////////////////////////////////////
760
////                                                              ////
761
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
762
////                                                              ////
763
//// This source file may be used and distributed without         ////
764
//// restriction provided that this copyright statement is not    ////
765
//// removed from the file and that any derivative work contains  ////
766
//// the original copyright notice and the associated disclaimer. ////
767
////                                                              ////
768
//// This source file is free software; you can redistribute it   ////
769
//// and/or modify it under the terms of the GNU Lesser General   ////
770
//// Public License as published by the Free Software Foundation; ////
771
//// either version 2.1 of the License, or (at your option) any   ////
772
//// later version.                                               ////
773
////                                                              ////
774
//// This source is distributed in the hope that it will be       ////
775
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
776
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
777
//// PURPOSE.  See the GNU Lesser General Public License for more ////
778
//// details.                                                     ////
779
////                                                              ////
780
//// You should have received a copy of the GNU Lesser General    ////
781
//// Public License along with this source; if not, download it   ////
782
//// from http://www.opencores.org/lgpl.shtml                     ////
783
////                                                              ////
784
//////////////////////////////////////////////////////////////////////
785
// binary counter
786 18 unneback
module vl_cnt_bin_ce_clear ( clear, cke, q, rst, clk);
787 6 unneback
   parameter length = 4;
788
   input clear;
789
   input cke;
790
   output [length:1] q;
791
   input rst;
792
   input clk;
793
   parameter clear_value = 0;
794
   parameter set_value = 1;
795
   parameter wrap_value = 0;
796
   parameter level1_value = 15;
797
   reg  [length:1] qi;
798
   wire [length:1] q_next;
799
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
800
   always @ (posedge clk or posedge rst)
801
     if (rst)
802
       qi <= {length{1'b0}};
803
     else
804
     if (cke)
805
       qi <= q_next;
806
   assign q = qi;
807
endmodule
808
//////////////////////////////////////////////////////////////////////
809
////                                                              ////
810
////  Versatile counter                                           ////
811
////                                                              ////
812
////  Description                                                 ////
813
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
814
////  counter                                                     ////
815
////                                                              ////
816
////  To Do:                                                      ////
817
////   - add LFSR with more taps                                  ////
818
////                                                              ////
819
////  Author(s):                                                  ////
820
////      - Michael Unneback, unneback@opencores.org              ////
821
////        ORSoC AB                                              ////
822
////                                                              ////
823
//////////////////////////////////////////////////////////////////////
824
////                                                              ////
825
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
826
////                                                              ////
827
//// This source file may be used and distributed without         ////
828
//// restriction provided that this copyright statement is not    ////
829
//// removed from the file and that any derivative work contains  ////
830
//// the original copyright notice and the associated disclaimer. ////
831
////                                                              ////
832
//// This source file is free software; you can redistribute it   ////
833
//// and/or modify it under the terms of the GNU Lesser General   ////
834
//// Public License as published by the Free Software Foundation; ////
835
//// either version 2.1 of the License, or (at your option) any   ////
836
//// later version.                                               ////
837
////                                                              ////
838
//// This source is distributed in the hope that it will be       ////
839
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
840
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
841
//// PURPOSE.  See the GNU Lesser General Public License for more ////
842
//// details.                                                     ////
843
////                                                              ////
844
//// You should have received a copy of the GNU Lesser General    ////
845
//// Public License along with this source; if not, download it   ////
846
//// from http://www.opencores.org/lgpl.shtml                     ////
847
////                                                              ////
848
//////////////////////////////////////////////////////////////////////
849
// binary counter
850 29 unneback
module vl_cnt_bin_ce_clear_l1_l2 ( clear, cke, q, level1, level2, rst, clk);
851
   parameter length = 4;
852
   input clear;
853
   input cke;
854
   output [length:1] q;
855
   output reg level1;
856
   output reg level2;
857
   input rst;
858
   input clk;
859
   parameter clear_value = 0;
860
   parameter set_value = 1;
861 30 unneback
   parameter wrap_value = 15;
862
   parameter level1_value = 8;
863
   parameter level2_value = 15;
864 29 unneback
   wire rew;
865 30 unneback
   assign rew = 1'b0;
866 29 unneback
   reg  [length:1] qi;
867
   wire [length:1] q_next;
868
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
869
   always @ (posedge clk or posedge rst)
870
     if (rst)
871
       qi <= {length{1'b0}};
872
     else
873
     if (cke)
874
       qi <= q_next;
875
   assign q = qi;
876
    always @ (posedge clk or posedge rst)
877
    if (rst)
878
        level1 <= 1'b0;
879
    else
880
    if (cke)
881
    if (clear)
882
        level1 <= 1'b0;
883
    else if (q_next == level1_value)
884
        level1 <= 1'b1;
885
    else if (qi == level1_value & rew)
886
        level1 <= 1'b0;
887
    always @ (posedge clk or posedge rst)
888
    if (rst)
889
        level2 <= 1'b0;
890
    else
891
    if (cke)
892
    if (clear)
893
        level2 <= 1'b0;
894
    else if (q_next == level2_value)
895
        level2 <= 1'b1;
896
    else if (qi == level2_value & rew)
897
        level2 <= 1'b0;
898
endmodule
899
//////////////////////////////////////////////////////////////////////
900
////                                                              ////
901
////  Versatile counter                                           ////
902
////                                                              ////
903
////  Description                                                 ////
904
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
905
////  counter                                                     ////
906
////                                                              ////
907
////  To Do:                                                      ////
908
////   - add LFSR with more taps                                  ////
909
////                                                              ////
910
////  Author(s):                                                  ////
911
////      - Michael Unneback, unneback@opencores.org              ////
912
////        ORSoC AB                                              ////
913
////                                                              ////
914
//////////////////////////////////////////////////////////////////////
915
////                                                              ////
916
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
917
////                                                              ////
918
//// This source file may be used and distributed without         ////
919
//// restriction provided that this copyright statement is not    ////
920
//// removed from the file and that any derivative work contains  ////
921
//// the original copyright notice and the associated disclaimer. ////
922
////                                                              ////
923
//// This source file is free software; you can redistribute it   ////
924
//// and/or modify it under the terms of the GNU Lesser General   ////
925
//// Public License as published by the Free Software Foundation; ////
926
//// either version 2.1 of the License, or (at your option) any   ////
927
//// later version.                                               ////
928
////                                                              ////
929
//// This source is distributed in the hope that it will be       ////
930
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
931
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
932
//// PURPOSE.  See the GNU Lesser General Public License for more ////
933
//// details.                                                     ////
934
////                                                              ////
935
//// You should have received a copy of the GNU Lesser General    ////
936
//// Public License along with this source; if not, download it   ////
937
//// from http://www.opencores.org/lgpl.shtml                     ////
938
////                                                              ////
939
//////////////////////////////////////////////////////////////////////
940
// binary counter
941 18 unneback
module vl_cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk);
942 6 unneback
   parameter length = 4;
943
   input clear;
944
   input set;
945
   input cke;
946
   input rew;
947
   output [length:1] q;
948
   input rst;
949
   input clk;
950
   parameter clear_value = 0;
951
   parameter set_value = 1;
952
   parameter wrap_value = 0;
953
   parameter level1_value = 15;
954
   reg  [length:1] qi;
955
   wire  [length:1] q_next, q_next_fw, q_next_rew;
956
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
957
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
958
   assign q_next = rew ? q_next_rew : q_next_fw;
959
   always @ (posedge clk or posedge rst)
960
     if (rst)
961
       qi <= {length{1'b0}};
962
     else
963
     if (cke)
964
       qi <= q_next;
965
   assign q = qi;
966
endmodule
967
//////////////////////////////////////////////////////////////////////
968
////                                                              ////
969
////  Versatile counter                                           ////
970
////                                                              ////
971
////  Description                                                 ////
972
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
973
////  counter                                                     ////
974
////                                                              ////
975
////  To Do:                                                      ////
976
////   - add LFSR with more taps                                  ////
977
////                                                              ////
978
////  Author(s):                                                  ////
979
////      - Michael Unneback, unneback@opencores.org              ////
980
////        ORSoC AB                                              ////
981
////                                                              ////
982
//////////////////////////////////////////////////////////////////////
983
////                                                              ////
984
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
985
////                                                              ////
986
//// This source file may be used and distributed without         ////
987
//// restriction provided that this copyright statement is not    ////
988
//// removed from the file and that any derivative work contains  ////
989
//// the original copyright notice and the associated disclaimer. ////
990
////                                                              ////
991
//// This source file is free software; you can redistribute it   ////
992
//// and/or modify it under the terms of the GNU Lesser General   ////
993
//// Public License as published by the Free Software Foundation; ////
994
//// either version 2.1 of the License, or (at your option) any   ////
995
//// later version.                                               ////
996
////                                                              ////
997
//// This source is distributed in the hope that it will be       ////
998
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
999
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1000
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1001
//// details.                                                     ////
1002
////                                                              ////
1003
//// You should have received a copy of the GNU Lesser General    ////
1004
//// Public License along with this source; if not, download it   ////
1005
//// from http://www.opencores.org/lgpl.shtml                     ////
1006
////                                                              ////
1007
//////////////////////////////////////////////////////////////////////
1008
// binary counter
1009 18 unneback
module vl_cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk);
1010 6 unneback
   parameter length = 4;
1011
   input cke;
1012
   input rew;
1013
   output reg level1;
1014
   input rst;
1015
   input clk;
1016
   parameter clear_value = 0;
1017
   parameter set_value = 1;
1018
   parameter wrap_value = 1;
1019
   parameter level1_value = 15;
1020 29 unneback
   wire clear;
1021 30 unneback
   assign clear = 1'b0;
1022 6 unneback
   reg  [length:1] qi;
1023
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1024
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1025
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1026
   assign q_next = rew ? q_next_rew : q_next_fw;
1027
   always @ (posedge clk or posedge rst)
1028
     if (rst)
1029
       qi <= {length{1'b0}};
1030
     else
1031
     if (cke)
1032
       qi <= q_next;
1033
    always @ (posedge clk or posedge rst)
1034
    if (rst)
1035
        level1 <= 1'b0;
1036
    else
1037
    if (cke)
1038 29 unneback
    if (clear)
1039
        level1 <= 1'b0;
1040
    else if (q_next == level1_value)
1041 6 unneback
        level1 <= 1'b1;
1042
    else if (qi == level1_value & rew)
1043
        level1 <= 1'b0;
1044
endmodule
1045
//////////////////////////////////////////////////////////////////////
1046
////                                                              ////
1047
////  Versatile counter                                           ////
1048
////                                                              ////
1049
////  Description                                                 ////
1050
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1051
////  counter                                                     ////
1052
////                                                              ////
1053
////  To Do:                                                      ////
1054
////   - add LFSR with more taps                                  ////
1055
////                                                              ////
1056
////  Author(s):                                                  ////
1057
////      - Michael Unneback, unneback@opencores.org              ////
1058
////        ORSoC AB                                              ////
1059
////                                                              ////
1060
//////////////////////////////////////////////////////////////////////
1061
////                                                              ////
1062
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1063
////                                                              ////
1064
//// This source file may be used and distributed without         ////
1065
//// restriction provided that this copyright statement is not    ////
1066
//// removed from the file and that any derivative work contains  ////
1067
//// the original copyright notice and the associated disclaimer. ////
1068
////                                                              ////
1069
//// This source file is free software; you can redistribute it   ////
1070
//// and/or modify it under the terms of the GNU Lesser General   ////
1071
//// Public License as published by the Free Software Foundation; ////
1072
//// either version 2.1 of the License, or (at your option) any   ////
1073
//// later version.                                               ////
1074
////                                                              ////
1075
//// This source is distributed in the hope that it will be       ////
1076
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1077
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1078
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1079
//// details.                                                     ////
1080
////                                                              ////
1081
//// You should have received a copy of the GNU Lesser General    ////
1082
//// Public License along with this source; if not, download it   ////
1083
//// from http://www.opencores.org/lgpl.shtml                     ////
1084
////                                                              ////
1085
//////////////////////////////////////////////////////////////////////
1086 25 unneback
// binary counter
1087
module vl_cnt_bin_ce_rew_zq_l1 ( cke, rew, zq, level1, rst, clk);
1088
   parameter length = 4;
1089
   input cke;
1090
   input rew;
1091
   output reg zq;
1092
   output reg level1;
1093
   input rst;
1094
   input clk;
1095
   parameter clear_value = 0;
1096
   parameter set_value = 1;
1097
   parameter wrap_value = 1;
1098
   parameter level1_value = 15;
1099 29 unneback
   wire clear;
1100 30 unneback
   assign clear = 1'b0;
1101 25 unneback
   reg  [length:1] qi;
1102
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1103
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1104
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1105
   assign q_next = rew ? q_next_rew : q_next_fw;
1106
   always @ (posedge clk or posedge rst)
1107
     if (rst)
1108
       qi <= {length{1'b0}};
1109
     else
1110
     if (cke)
1111
       qi <= q_next;
1112
   always @ (posedge clk or posedge rst)
1113
     if (rst)
1114
       zq <= 1'b1;
1115
     else
1116
     if (cke)
1117
       zq <= q_next == {length{1'b0}};
1118
    always @ (posedge clk or posedge rst)
1119
    if (rst)
1120
        level1 <= 1'b0;
1121
    else
1122
    if (cke)
1123 29 unneback
    if (clear)
1124
        level1 <= 1'b0;
1125
    else if (q_next == level1_value)
1126 25 unneback
        level1 <= 1'b1;
1127
    else if (qi == level1_value & rew)
1128
        level1 <= 1'b0;
1129
endmodule
1130
//////////////////////////////////////////////////////////////////////
1131
////                                                              ////
1132
////  Versatile counter                                           ////
1133
////                                                              ////
1134
////  Description                                                 ////
1135
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1136
////  counter                                                     ////
1137
////                                                              ////
1138
////  To Do:                                                      ////
1139
////   - add LFSR with more taps                                  ////
1140
////                                                              ////
1141
////  Author(s):                                                  ////
1142
////      - Michael Unneback, unneback@opencores.org              ////
1143
////        ORSoC AB                                              ////
1144
////                                                              ////
1145
//////////////////////////////////////////////////////////////////////
1146
////                                                              ////
1147
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1148
////                                                              ////
1149
//// This source file may be used and distributed without         ////
1150
//// restriction provided that this copyright statement is not    ////
1151
//// removed from the file and that any derivative work contains  ////
1152
//// the original copyright notice and the associated disclaimer. ////
1153
////                                                              ////
1154
//// This source file is free software; you can redistribute it   ////
1155
//// and/or modify it under the terms of the GNU Lesser General   ////
1156
//// Public License as published by the Free Software Foundation; ////
1157
//// either version 2.1 of the License, or (at your option) any   ////
1158
//// later version.                                               ////
1159
////                                                              ////
1160
//// This source is distributed in the hope that it will be       ////
1161
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1162
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1163
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1164
//// details.                                                     ////
1165
////                                                              ////
1166
//// You should have received a copy of the GNU Lesser General    ////
1167
//// Public License along with this source; if not, download it   ////
1168
//// from http://www.opencores.org/lgpl.shtml                     ////
1169
////                                                              ////
1170
//////////////////////////////////////////////////////////////////////
1171
// binary counter
1172
module vl_cnt_bin_ce_rew_q_zq_l1 ( cke, rew, q, zq, level1, rst, clk);
1173
   parameter length = 4;
1174
   input cke;
1175
   input rew;
1176
   output [length:1] q;
1177
   output reg zq;
1178
   output reg level1;
1179
   input rst;
1180
   input clk;
1181
   parameter clear_value = 0;
1182
   parameter set_value = 1;
1183
   parameter wrap_value = 1;
1184
   parameter level1_value = 15;
1185 29 unneback
   wire clear;
1186 30 unneback
   assign clear = 1'b0;
1187 25 unneback
   reg  [length:1] qi;
1188
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1189
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1190
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1191
   assign q_next = rew ? q_next_rew : q_next_fw;
1192
   always @ (posedge clk or posedge rst)
1193
     if (rst)
1194
       qi <= {length{1'b0}};
1195
     else
1196
     if (cke)
1197
       qi <= q_next;
1198
   assign q = qi;
1199
   always @ (posedge clk or posedge rst)
1200
     if (rst)
1201
       zq <= 1'b1;
1202
     else
1203
     if (cke)
1204
       zq <= q_next == {length{1'b0}};
1205
    always @ (posedge clk or posedge rst)
1206
    if (rst)
1207
        level1 <= 1'b0;
1208
    else
1209
    if (cke)
1210 29 unneback
    if (clear)
1211
        level1 <= 1'b0;
1212
    else if (q_next == level1_value)
1213 25 unneback
        level1 <= 1'b1;
1214
    else if (qi == level1_value & rew)
1215
        level1 <= 1'b0;
1216
endmodule
1217
//////////////////////////////////////////////////////////////////////
1218
////                                                              ////
1219
////  Versatile counter                                           ////
1220
////                                                              ////
1221
////  Description                                                 ////
1222
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1223
////  counter                                                     ////
1224
////                                                              ////
1225
////  To Do:                                                      ////
1226
////   - add LFSR with more taps                                  ////
1227
////                                                              ////
1228
////  Author(s):                                                  ////
1229
////      - Michael Unneback, unneback@opencores.org              ////
1230
////        ORSoC AB                                              ////
1231
////                                                              ////
1232
//////////////////////////////////////////////////////////////////////
1233
////                                                              ////
1234
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1235
////                                                              ////
1236
//// This source file may be used and distributed without         ////
1237
//// restriction provided that this copyright statement is not    ////
1238
//// removed from the file and that any derivative work contains  ////
1239
//// the original copyright notice and the associated disclaimer. ////
1240
////                                                              ////
1241
//// This source file is free software; you can redistribute it   ////
1242
//// and/or modify it under the terms of the GNU Lesser General   ////
1243
//// Public License as published by the Free Software Foundation; ////
1244
//// either version 2.1 of the License, or (at your option) any   ////
1245
//// later version.                                               ////
1246
////                                                              ////
1247
//// This source is distributed in the hope that it will be       ////
1248
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1249
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1250
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1251
//// details.                                                     ////
1252
////                                                              ////
1253
//// You should have received a copy of the GNU Lesser General    ////
1254
//// Public License along with this source; if not, download it   ////
1255
//// from http://www.opencores.org/lgpl.shtml                     ////
1256
////                                                              ////
1257
//////////////////////////////////////////////////////////////////////
1258 6 unneback
// LFSR counter
1259 18 unneback
module vl_cnt_lfsr_zq ( zq, rst, clk);
1260 6 unneback
   parameter length = 4;
1261
   output reg zq;
1262
   input rst;
1263
   input clk;
1264
   parameter clear_value = 0;
1265
   parameter set_value = 1;
1266
   parameter wrap_value = 8;
1267
   parameter level1_value = 15;
1268
   reg  [length:1] qi;
1269
   reg lfsr_fb;
1270
   wire [length:1] q_next;
1271
   reg [32:1] polynom;
1272
   integer i;
1273
   always @ (qi)
1274
   begin
1275
        case (length)
1276
         2: polynom = 32'b11;                               // 0x3
1277
         3: polynom = 32'b110;                              // 0x6
1278
         4: polynom = 32'b1100;                             // 0xC
1279
         5: polynom = 32'b10100;                            // 0x14
1280
         6: polynom = 32'b110000;                           // 0x30
1281
         7: polynom = 32'b1100000;                          // 0x60
1282
         8: polynom = 32'b10111000;                         // 0xb8
1283
         9: polynom = 32'b100010000;                        // 0x110
1284
        10: polynom = 32'b1001000000;                       // 0x240
1285
        11: polynom = 32'b10100000000;                      // 0x500
1286
        12: polynom = 32'b100000101001;                     // 0x829
1287
        13: polynom = 32'b1000000001100;                    // 0x100C
1288
        14: polynom = 32'b10000000010101;                   // 0x2015
1289
        15: polynom = 32'b110000000000000;                  // 0x6000
1290
        16: polynom = 32'b1101000000001000;                 // 0xD008
1291
        17: polynom = 32'b10010000000000000;                // 0x12000
1292
        18: polynom = 32'b100000010000000000;               // 0x20400
1293
        19: polynom = 32'b1000000000000100011;              // 0x40023
1294
        20: polynom = 32'b10000010000000000000;             // 0x82000
1295
        21: polynom = 32'b101000000000000000000;            // 0x140000
1296
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1297
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1298
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1299
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1300
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1301
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1302
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1303
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1304
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1305
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1306
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1307
        default: polynom = 32'b0;
1308
        endcase
1309
        lfsr_fb = qi[length];
1310
        for (i=length-1; i>=1; i=i-1) begin
1311
            if (polynom[i])
1312
                lfsr_fb = lfsr_fb  ~^ qi[i];
1313
        end
1314
    end
1315
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1316
   always @ (posedge clk or posedge rst)
1317
     if (rst)
1318
       qi <= {length{1'b0}};
1319
     else
1320
       qi <= q_next;
1321
   always @ (posedge clk or posedge rst)
1322
     if (rst)
1323
       zq <= 1'b1;
1324
     else
1325
       zq <= q_next == {length{1'b0}};
1326
endmodule
1327
//////////////////////////////////////////////////////////////////////
1328
////                                                              ////
1329
////  Versatile counter                                           ////
1330
////                                                              ////
1331
////  Description                                                 ////
1332
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1333
////  counter                                                     ////
1334
////                                                              ////
1335
////  To Do:                                                      ////
1336
////   - add LFSR with more taps                                  ////
1337
////                                                              ////
1338
////  Author(s):                                                  ////
1339
////      - Michael Unneback, unneback@opencores.org              ////
1340
////        ORSoC AB                                              ////
1341
////                                                              ////
1342
//////////////////////////////////////////////////////////////////////
1343
////                                                              ////
1344
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1345
////                                                              ////
1346
//// This source file may be used and distributed without         ////
1347
//// restriction provided that this copyright statement is not    ////
1348
//// removed from the file and that any derivative work contains  ////
1349
//// the original copyright notice and the associated disclaimer. ////
1350
////                                                              ////
1351
//// This source file is free software; you can redistribute it   ////
1352
//// and/or modify it under the terms of the GNU Lesser General   ////
1353
//// Public License as published by the Free Software Foundation; ////
1354
//// either version 2.1 of the License, or (at your option) any   ////
1355
//// later version.                                               ////
1356
////                                                              ////
1357
//// This source is distributed in the hope that it will be       ////
1358
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1359
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1360
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1361
//// details.                                                     ////
1362
////                                                              ////
1363
//// You should have received a copy of the GNU Lesser General    ////
1364
//// Public License along with this source; if not, download it   ////
1365
//// from http://www.opencores.org/lgpl.shtml                     ////
1366
////                                                              ////
1367
//////////////////////////////////////////////////////////////////////
1368
// LFSR counter
1369 18 unneback
module vl_cnt_lfsr_ce_zq ( cke, zq, rst, clk);
1370 6 unneback
   parameter length = 4;
1371
   input cke;
1372
   output reg zq;
1373
   input rst;
1374
   input clk;
1375
   parameter clear_value = 0;
1376
   parameter set_value = 1;
1377
   parameter wrap_value = 8;
1378
   parameter level1_value = 15;
1379
   reg  [length:1] qi;
1380
   reg lfsr_fb;
1381
   wire [length:1] q_next;
1382
   reg [32:1] polynom;
1383
   integer i;
1384
   always @ (qi)
1385
   begin
1386
        case (length)
1387
         2: polynom = 32'b11;                               // 0x3
1388
         3: polynom = 32'b110;                              // 0x6
1389
         4: polynom = 32'b1100;                             // 0xC
1390
         5: polynom = 32'b10100;                            // 0x14
1391
         6: polynom = 32'b110000;                           // 0x30
1392
         7: polynom = 32'b1100000;                          // 0x60
1393
         8: polynom = 32'b10111000;                         // 0xb8
1394
         9: polynom = 32'b100010000;                        // 0x110
1395
        10: polynom = 32'b1001000000;                       // 0x240
1396
        11: polynom = 32'b10100000000;                      // 0x500
1397
        12: polynom = 32'b100000101001;                     // 0x829
1398
        13: polynom = 32'b1000000001100;                    // 0x100C
1399
        14: polynom = 32'b10000000010101;                   // 0x2015
1400
        15: polynom = 32'b110000000000000;                  // 0x6000
1401
        16: polynom = 32'b1101000000001000;                 // 0xD008
1402
        17: polynom = 32'b10010000000000000;                // 0x12000
1403
        18: polynom = 32'b100000010000000000;               // 0x20400
1404
        19: polynom = 32'b1000000000000100011;              // 0x40023
1405
        20: polynom = 32'b10000010000000000000;             // 0x82000
1406
        21: polynom = 32'b101000000000000000000;            // 0x140000
1407
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1408
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1409
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1410
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1411
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1412
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1413
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1414
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1415
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1416
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1417
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1418
        default: polynom = 32'b0;
1419
        endcase
1420
        lfsr_fb = qi[length];
1421
        for (i=length-1; i>=1; i=i-1) begin
1422
            if (polynom[i])
1423
                lfsr_fb = lfsr_fb  ~^ qi[i];
1424
        end
1425
    end
1426
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1427
   always @ (posedge clk or posedge rst)
1428
     if (rst)
1429
       qi <= {length{1'b0}};
1430
     else
1431
     if (cke)
1432
       qi <= q_next;
1433
   always @ (posedge clk or posedge rst)
1434
     if (rst)
1435
       zq <= 1'b1;
1436
     else
1437
     if (cke)
1438
       zq <= q_next == {length{1'b0}};
1439
endmodule
1440
//////////////////////////////////////////////////////////////////////
1441
////                                                              ////
1442
////  Versatile counter                                           ////
1443
////                                                              ////
1444
////  Description                                                 ////
1445
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1446
////  counter                                                     ////
1447
////                                                              ////
1448
////  To Do:                                                      ////
1449
////   - add LFSR with more taps                                  ////
1450
////                                                              ////
1451
////  Author(s):                                                  ////
1452
////      - Michael Unneback, unneback@opencores.org              ////
1453
////        ORSoC AB                                              ////
1454
////                                                              ////
1455
//////////////////////////////////////////////////////////////////////
1456
////                                                              ////
1457
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1458
////                                                              ////
1459
//// This source file may be used and distributed without         ////
1460
//// restriction provided that this copyright statement is not    ////
1461
//// removed from the file and that any derivative work contains  ////
1462
//// the original copyright notice and the associated disclaimer. ////
1463
////                                                              ////
1464
//// This source file is free software; you can redistribute it   ////
1465
//// and/or modify it under the terms of the GNU Lesser General   ////
1466
//// Public License as published by the Free Software Foundation; ////
1467
//// either version 2.1 of the License, or (at your option) any   ////
1468
//// later version.                                               ////
1469
////                                                              ////
1470
//// This source is distributed in the hope that it will be       ////
1471
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1472
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1473
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1474
//// details.                                                     ////
1475
////                                                              ////
1476
//// You should have received a copy of the GNU Lesser General    ////
1477
//// Public License along with this source; if not, download it   ////
1478
//// from http://www.opencores.org/lgpl.shtml                     ////
1479
////                                                              ////
1480
//////////////////////////////////////////////////////////////////////
1481
// LFSR counter
1482 27 unneback
module vl_cnt_lfsr_ce_q ( cke, q, rst, clk);
1483
   parameter length = 4;
1484
   input cke;
1485
   output [length:1] q;
1486
   input rst;
1487
   input clk;
1488
   parameter clear_value = 0;
1489
   parameter set_value = 1;
1490
   parameter wrap_value = 8;
1491
   parameter level1_value = 15;
1492
   reg  [length:1] qi;
1493
   reg lfsr_fb;
1494
   wire [length:1] q_next;
1495
   reg [32:1] polynom;
1496
   integer i;
1497
   always @ (qi)
1498
   begin
1499
        case (length)
1500
         2: polynom = 32'b11;                               // 0x3
1501
         3: polynom = 32'b110;                              // 0x6
1502
         4: polynom = 32'b1100;                             // 0xC
1503
         5: polynom = 32'b10100;                            // 0x14
1504
         6: polynom = 32'b110000;                           // 0x30
1505
         7: polynom = 32'b1100000;                          // 0x60
1506
         8: polynom = 32'b10111000;                         // 0xb8
1507
         9: polynom = 32'b100010000;                        // 0x110
1508
        10: polynom = 32'b1001000000;                       // 0x240
1509
        11: polynom = 32'b10100000000;                      // 0x500
1510
        12: polynom = 32'b100000101001;                     // 0x829
1511
        13: polynom = 32'b1000000001100;                    // 0x100C
1512
        14: polynom = 32'b10000000010101;                   // 0x2015
1513
        15: polynom = 32'b110000000000000;                  // 0x6000
1514
        16: polynom = 32'b1101000000001000;                 // 0xD008
1515
        17: polynom = 32'b10010000000000000;                // 0x12000
1516
        18: polynom = 32'b100000010000000000;               // 0x20400
1517
        19: polynom = 32'b1000000000000100011;              // 0x40023
1518
        20: polynom = 32'b10000010000000000000;             // 0x82000
1519
        21: polynom = 32'b101000000000000000000;            // 0x140000
1520
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1521
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1522
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1523
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1524
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1525
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1526
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1527
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1528
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1529
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1530
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1531
        default: polynom = 32'b0;
1532
        endcase
1533
        lfsr_fb = qi[length];
1534
        for (i=length-1; i>=1; i=i-1) begin
1535
            if (polynom[i])
1536
                lfsr_fb = lfsr_fb  ~^ qi[i];
1537
        end
1538
    end
1539
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1540
   always @ (posedge clk or posedge rst)
1541
     if (rst)
1542
       qi <= {length{1'b0}};
1543
     else
1544
     if (cke)
1545
       qi <= q_next;
1546
   assign q = qi;
1547
endmodule
1548
//////////////////////////////////////////////////////////////////////
1549
////                                                              ////
1550
////  Versatile counter                                           ////
1551
////                                                              ////
1552
////  Description                                                 ////
1553
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1554
////  counter                                                     ////
1555
////                                                              ////
1556
////  To Do:                                                      ////
1557
////   - add LFSR with more taps                                  ////
1558
////                                                              ////
1559
////  Author(s):                                                  ////
1560
////      - Michael Unneback, unneback@opencores.org              ////
1561
////        ORSoC AB                                              ////
1562
////                                                              ////
1563
//////////////////////////////////////////////////////////////////////
1564
////                                                              ////
1565
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1566
////                                                              ////
1567
//// This source file may be used and distributed without         ////
1568
//// restriction provided that this copyright statement is not    ////
1569
//// removed from the file and that any derivative work contains  ////
1570
//// the original copyright notice and the associated disclaimer. ////
1571
////                                                              ////
1572
//// This source file is free software; you can redistribute it   ////
1573
//// and/or modify it under the terms of the GNU Lesser General   ////
1574
//// Public License as published by the Free Software Foundation; ////
1575
//// either version 2.1 of the License, or (at your option) any   ////
1576
//// later version.                                               ////
1577
////                                                              ////
1578
//// This source is distributed in the hope that it will be       ////
1579
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1580
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1581
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1582
//// details.                                                     ////
1583
////                                                              ////
1584
//// You should have received a copy of the GNU Lesser General    ////
1585
//// Public License along with this source; if not, download it   ////
1586
//// from http://www.opencores.org/lgpl.shtml                     ////
1587
////                                                              ////
1588
//////////////////////////////////////////////////////////////////////
1589
// LFSR counter
1590
module vl_cnt_lfsr_ce_clear_q ( clear, cke, q, rst, clk);
1591
   parameter length = 4;
1592
   input clear;
1593
   input cke;
1594
   output [length:1] q;
1595
   input rst;
1596
   input clk;
1597
   parameter clear_value = 0;
1598
   parameter set_value = 1;
1599
   parameter wrap_value = 8;
1600
   parameter level1_value = 15;
1601
   reg  [length:1] qi;
1602
   reg lfsr_fb;
1603
   wire [length:1] q_next;
1604
   reg [32:1] polynom;
1605
   integer i;
1606
   always @ (qi)
1607
   begin
1608
        case (length)
1609
         2: polynom = 32'b11;                               // 0x3
1610
         3: polynom = 32'b110;                              // 0x6
1611
         4: polynom = 32'b1100;                             // 0xC
1612
         5: polynom = 32'b10100;                            // 0x14
1613
         6: polynom = 32'b110000;                           // 0x30
1614
         7: polynom = 32'b1100000;                          // 0x60
1615
         8: polynom = 32'b10111000;                         // 0xb8
1616
         9: polynom = 32'b100010000;                        // 0x110
1617
        10: polynom = 32'b1001000000;                       // 0x240
1618
        11: polynom = 32'b10100000000;                      // 0x500
1619
        12: polynom = 32'b100000101001;                     // 0x829
1620
        13: polynom = 32'b1000000001100;                    // 0x100C
1621
        14: polynom = 32'b10000000010101;                   // 0x2015
1622
        15: polynom = 32'b110000000000000;                  // 0x6000
1623
        16: polynom = 32'b1101000000001000;                 // 0xD008
1624
        17: polynom = 32'b10010000000000000;                // 0x12000
1625
        18: polynom = 32'b100000010000000000;               // 0x20400
1626
        19: polynom = 32'b1000000000000100011;              // 0x40023
1627
        20: polynom = 32'b10000010000000000000;             // 0x82000
1628
        21: polynom = 32'b101000000000000000000;            // 0x140000
1629
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1630
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1631
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1632
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1633
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1634
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1635
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1636
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1637
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1638
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1639
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1640
        default: polynom = 32'b0;
1641
        endcase
1642
        lfsr_fb = qi[length];
1643
        for (i=length-1; i>=1; i=i-1) begin
1644
            if (polynom[i])
1645
                lfsr_fb = lfsr_fb  ~^ qi[i];
1646
        end
1647
    end
1648
   assign q_next =  clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1649
   always @ (posedge clk or posedge rst)
1650
     if (rst)
1651
       qi <= {length{1'b0}};
1652
     else
1653
     if (cke)
1654
       qi <= q_next;
1655
   assign q = qi;
1656
endmodule
1657
//////////////////////////////////////////////////////////////////////
1658
////                                                              ////
1659
////  Versatile counter                                           ////
1660
////                                                              ////
1661
////  Description                                                 ////
1662
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1663
////  counter                                                     ////
1664
////                                                              ////
1665
////  To Do:                                                      ////
1666
////   - add LFSR with more taps                                  ////
1667
////                                                              ////
1668
////  Author(s):                                                  ////
1669
////      - Michael Unneback, unneback@opencores.org              ////
1670
////        ORSoC AB                                              ////
1671
////                                                              ////
1672
//////////////////////////////////////////////////////////////////////
1673
////                                                              ////
1674
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1675
////                                                              ////
1676
//// This source file may be used and distributed without         ////
1677
//// restriction provided that this copyright statement is not    ////
1678
//// removed from the file and that any derivative work contains  ////
1679
//// the original copyright notice and the associated disclaimer. ////
1680
////                                                              ////
1681
//// This source file is free software; you can redistribute it   ////
1682
//// and/or modify it under the terms of the GNU Lesser General   ////
1683
//// Public License as published by the Free Software Foundation; ////
1684
//// either version 2.1 of the License, or (at your option) any   ////
1685
//// later version.                                               ////
1686
////                                                              ////
1687
//// This source is distributed in the hope that it will be       ////
1688
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1689
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1690
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1691
//// details.                                                     ////
1692
////                                                              ////
1693
//// You should have received a copy of the GNU Lesser General    ////
1694
//// Public License along with this source; if not, download it   ////
1695
//// from http://www.opencores.org/lgpl.shtml                     ////
1696
////                                                              ////
1697
//////////////////////////////////////////////////////////////////////
1698
// LFSR counter
1699 22 unneback
module vl_cnt_lfsr_ce_q_zq ( cke, q, zq, rst, clk);
1700
   parameter length = 4;
1701
   input cke;
1702
   output [length:1] q;
1703
   output reg zq;
1704
   input rst;
1705
   input clk;
1706
   parameter clear_value = 0;
1707
   parameter set_value = 1;
1708
   parameter wrap_value = 8;
1709
   parameter level1_value = 15;
1710
   reg  [length:1] qi;
1711
   reg lfsr_fb;
1712
   wire [length:1] q_next;
1713
   reg [32:1] polynom;
1714
   integer i;
1715
   always @ (qi)
1716
   begin
1717
        case (length)
1718
         2: polynom = 32'b11;                               // 0x3
1719
         3: polynom = 32'b110;                              // 0x6
1720
         4: polynom = 32'b1100;                             // 0xC
1721
         5: polynom = 32'b10100;                            // 0x14
1722
         6: polynom = 32'b110000;                           // 0x30
1723
         7: polynom = 32'b1100000;                          // 0x60
1724
         8: polynom = 32'b10111000;                         // 0xb8
1725
         9: polynom = 32'b100010000;                        // 0x110
1726
        10: polynom = 32'b1001000000;                       // 0x240
1727
        11: polynom = 32'b10100000000;                      // 0x500
1728
        12: polynom = 32'b100000101001;                     // 0x829
1729
        13: polynom = 32'b1000000001100;                    // 0x100C
1730
        14: polynom = 32'b10000000010101;                   // 0x2015
1731
        15: polynom = 32'b110000000000000;                  // 0x6000
1732
        16: polynom = 32'b1101000000001000;                 // 0xD008
1733
        17: polynom = 32'b10010000000000000;                // 0x12000
1734
        18: polynom = 32'b100000010000000000;               // 0x20400
1735
        19: polynom = 32'b1000000000000100011;              // 0x40023
1736
        20: polynom = 32'b10000010000000000000;             // 0x82000
1737
        21: polynom = 32'b101000000000000000000;            // 0x140000
1738
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1739
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1740
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1741
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1742
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1743
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1744
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1745
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1746
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1747
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1748
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1749
        default: polynom = 32'b0;
1750
        endcase
1751
        lfsr_fb = qi[length];
1752
        for (i=length-1; i>=1; i=i-1) begin
1753
            if (polynom[i])
1754
                lfsr_fb = lfsr_fb  ~^ qi[i];
1755
        end
1756
    end
1757
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1758
   always @ (posedge clk or posedge rst)
1759
     if (rst)
1760
       qi <= {length{1'b0}};
1761
     else
1762
     if (cke)
1763
       qi <= q_next;
1764
   assign q = qi;
1765
   always @ (posedge clk or posedge rst)
1766
     if (rst)
1767
       zq <= 1'b1;
1768
     else
1769
     if (cke)
1770
       zq <= q_next == {length{1'b0}};
1771
endmodule
1772
//////////////////////////////////////////////////////////////////////
1773
////                                                              ////
1774
////  Versatile counter                                           ////
1775
////                                                              ////
1776
////  Description                                                 ////
1777
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1778
////  counter                                                     ////
1779
////                                                              ////
1780
////  To Do:                                                      ////
1781
////   - add LFSR with more taps                                  ////
1782
////                                                              ////
1783
////  Author(s):                                                  ////
1784
////      - Michael Unneback, unneback@opencores.org              ////
1785
////        ORSoC AB                                              ////
1786
////                                                              ////
1787
//////////////////////////////////////////////////////////////////////
1788
////                                                              ////
1789
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1790
////                                                              ////
1791
//// This source file may be used and distributed without         ////
1792
//// restriction provided that this copyright statement is not    ////
1793
//// removed from the file and that any derivative work contains  ////
1794
//// the original copyright notice and the associated disclaimer. ////
1795
////                                                              ////
1796
//// This source file is free software; you can redistribute it   ////
1797
//// and/or modify it under the terms of the GNU Lesser General   ////
1798
//// Public License as published by the Free Software Foundation; ////
1799
//// either version 2.1 of the License, or (at your option) any   ////
1800
//// later version.                                               ////
1801
////                                                              ////
1802
//// This source is distributed in the hope that it will be       ////
1803
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1804
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1805
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1806
//// details.                                                     ////
1807
////                                                              ////
1808
//// You should have received a copy of the GNU Lesser General    ////
1809
//// Public License along with this source; if not, download it   ////
1810
//// from http://www.opencores.org/lgpl.shtml                     ////
1811
////                                                              ////
1812
//////////////////////////////////////////////////////////////////////
1813
// LFSR counter
1814 18 unneback
module vl_cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk);
1815 6 unneback
   parameter length = 4;
1816
   input cke;
1817
   input rew;
1818
   output reg level1;
1819
   input rst;
1820
   input clk;
1821
   parameter clear_value = 0;
1822
   parameter set_value = 1;
1823
   parameter wrap_value = 8;
1824
   parameter level1_value = 15;
1825 29 unneback
   wire clear;
1826 30 unneback
   assign clear = 1'b0;
1827 6 unneback
   reg  [length:1] qi;
1828
   reg lfsr_fb, lfsr_fb_rew;
1829
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1830
   reg [32:1] polynom_rew;
1831
   integer j;
1832
   reg [32:1] polynom;
1833
   integer i;
1834
   always @ (qi)
1835
   begin
1836
        case (length)
1837
         2: polynom = 32'b11;                               // 0x3
1838
         3: polynom = 32'b110;                              // 0x6
1839
         4: polynom = 32'b1100;                             // 0xC
1840
         5: polynom = 32'b10100;                            // 0x14
1841
         6: polynom = 32'b110000;                           // 0x30
1842
         7: polynom = 32'b1100000;                          // 0x60
1843
         8: polynom = 32'b10111000;                         // 0xb8
1844
         9: polynom = 32'b100010000;                        // 0x110
1845
        10: polynom = 32'b1001000000;                       // 0x240
1846
        11: polynom = 32'b10100000000;                      // 0x500
1847
        12: polynom = 32'b100000101001;                     // 0x829
1848
        13: polynom = 32'b1000000001100;                    // 0x100C
1849
        14: polynom = 32'b10000000010101;                   // 0x2015
1850
        15: polynom = 32'b110000000000000;                  // 0x6000
1851
        16: polynom = 32'b1101000000001000;                 // 0xD008
1852
        17: polynom = 32'b10010000000000000;                // 0x12000
1853
        18: polynom = 32'b100000010000000000;               // 0x20400
1854
        19: polynom = 32'b1000000000000100011;              // 0x40023
1855
        20: polynom = 32'b10000010000000000000;             // 0x82000
1856
        21: polynom = 32'b101000000000000000000;            // 0x140000
1857
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1858
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1859
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1860
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1861
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1862
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1863
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1864
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1865
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1866
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1867
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1868
        default: polynom = 32'b0;
1869
        endcase
1870
        lfsr_fb = qi[length];
1871
        for (i=length-1; i>=1; i=i-1) begin
1872
            if (polynom[i])
1873
                lfsr_fb = lfsr_fb  ~^ qi[i];
1874
        end
1875
    end
1876
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1877
   always @ (qi)
1878
   begin
1879
        case (length)
1880
         2: polynom_rew = 32'b11;
1881
         3: polynom_rew = 32'b110;
1882
         4: polynom_rew = 32'b1100;
1883
         5: polynom_rew = 32'b10100;
1884
         6: polynom_rew = 32'b110000;
1885
         7: polynom_rew = 32'b1100000;
1886
         8: polynom_rew = 32'b10111000;
1887
         9: polynom_rew = 32'b100010000;
1888
        10: polynom_rew = 32'b1001000000;
1889
        11: polynom_rew = 32'b10100000000;
1890
        12: polynom_rew = 32'b100000101001;
1891
        13: polynom_rew = 32'b1000000001100;
1892
        14: polynom_rew = 32'b10000000010101;
1893
        15: polynom_rew = 32'b110000000000000;
1894
        16: polynom_rew = 32'b1101000000001000;
1895
        17: polynom_rew = 32'b10010000000000000;
1896
        18: polynom_rew = 32'b100000010000000000;
1897
        19: polynom_rew = 32'b1000000000000100011;
1898
        20: polynom_rew = 32'b10000010000000000000;
1899
        21: polynom_rew = 32'b101000000000000000000;
1900
        22: polynom_rew = 32'b1100000000000000000000;
1901
        23: polynom_rew = 32'b10000100000000000000000;
1902
        24: polynom_rew = 32'b111000010000000000000000;
1903
        25: polynom_rew = 32'b1001000000000000000000000;
1904
        26: polynom_rew = 32'b10000000000000000000100011;
1905
        27: polynom_rew = 32'b100000000000000000000010011;
1906
        28: polynom_rew = 32'b1100100000000000000000000000;
1907
        29: polynom_rew = 32'b10100000000000000000000000000;
1908
        30: polynom_rew = 32'b100000000000000000000000101001;
1909
        31: polynom_rew = 32'b1001000000000000000000000000000;
1910
        32: polynom_rew = 32'b10000000001000000000000000000011;
1911
        default: polynom_rew = 32'b0;
1912
        endcase
1913
        // rotate left
1914
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
1915
        lfsr_fb_rew = qi[length];
1916
        for (i=length-1; i>=1; i=i-1) begin
1917
            if (polynom_rew[i])
1918
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
1919
        end
1920
    end
1921
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
1922
   assign q_next = rew ? q_next_rew : q_next_fw;
1923
   always @ (posedge clk or posedge rst)
1924
     if (rst)
1925
       qi <= {length{1'b0}};
1926
     else
1927
     if (cke)
1928
       qi <= q_next;
1929
    always @ (posedge clk or posedge rst)
1930
    if (rst)
1931
        level1 <= 1'b0;
1932
    else
1933
    if (cke)
1934 29 unneback
    if (clear)
1935
        level1 <= 1'b0;
1936
    else if (q_next == level1_value)
1937 6 unneback
        level1 <= 1'b1;
1938
    else if (qi == level1_value & rew)
1939
        level1 <= 1'b0;
1940
endmodule
1941
//////////////////////////////////////////////////////////////////////
1942
////                                                              ////
1943
////  Versatile counter                                           ////
1944
////                                                              ////
1945
////  Description                                                 ////
1946
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1947
////  counter                                                     ////
1948
////                                                              ////
1949
////  To Do:                                                      ////
1950
////   - add LFSR with more taps                                  ////
1951
////                                                              ////
1952
////  Author(s):                                                  ////
1953
////      - Michael Unneback, unneback@opencores.org              ////
1954
////        ORSoC AB                                              ////
1955
////                                                              ////
1956
//////////////////////////////////////////////////////////////////////
1957
////                                                              ////
1958
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1959
////                                                              ////
1960
//// This source file may be used and distributed without         ////
1961
//// restriction provided that this copyright statement is not    ////
1962
//// removed from the file and that any derivative work contains  ////
1963
//// the original copyright notice and the associated disclaimer. ////
1964
////                                                              ////
1965
//// This source file is free software; you can redistribute it   ////
1966
//// and/or modify it under the terms of the GNU Lesser General   ////
1967
//// Public License as published by the Free Software Foundation; ////
1968
//// either version 2.1 of the License, or (at your option) any   ////
1969
//// later version.                                               ////
1970
////                                                              ////
1971
//// This source is distributed in the hope that it will be       ////
1972
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1973
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1974
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1975
//// details.                                                     ////
1976
////                                                              ////
1977
//// You should have received a copy of the GNU Lesser General    ////
1978
//// Public License along with this source; if not, download it   ////
1979
//// from http://www.opencores.org/lgpl.shtml                     ////
1980
////                                                              ////
1981
//////////////////////////////////////////////////////////////////////
1982
// GRAY counter
1983 18 unneback
module vl_cnt_gray ( q, rst, clk);
1984 6 unneback
   parameter length = 4;
1985
   output reg [length:1] q;
1986
   input rst;
1987
   input clk;
1988
   parameter clear_value = 0;
1989
   parameter set_value = 1;
1990
   parameter wrap_value = 8;
1991
   parameter level1_value = 15;
1992
   reg  [length:1] qi;
1993
   wire [length:1] q_next;
1994
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1995
   always @ (posedge clk or posedge rst)
1996
     if (rst)
1997
       qi <= {length{1'b0}};
1998
     else
1999
       qi <= q_next;
2000
   always @ (posedge clk or posedge rst)
2001
     if (rst)
2002
       q <= {length{1'b0}};
2003
     else
2004
         q <= (q_next>>1) ^ q_next;
2005
endmodule
2006
//////////////////////////////////////////////////////////////////////
2007
////                                                              ////
2008
////  Versatile counter                                           ////
2009
////                                                              ////
2010
////  Description                                                 ////
2011
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2012
////  counter                                                     ////
2013
////                                                              ////
2014
////  To Do:                                                      ////
2015
////   - add LFSR with more taps                                  ////
2016
////                                                              ////
2017
////  Author(s):                                                  ////
2018
////      - Michael Unneback, unneback@opencores.org              ////
2019
////        ORSoC AB                                              ////
2020
////                                                              ////
2021
//////////////////////////////////////////////////////////////////////
2022
////                                                              ////
2023
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2024
////                                                              ////
2025
//// This source file may be used and distributed without         ////
2026
//// restriction provided that this copyright statement is not    ////
2027
//// removed from the file and that any derivative work contains  ////
2028
//// the original copyright notice and the associated disclaimer. ////
2029
////                                                              ////
2030
//// This source file is free software; you can redistribute it   ////
2031
//// and/or modify it under the terms of the GNU Lesser General   ////
2032
//// Public License as published by the Free Software Foundation; ////
2033
//// either version 2.1 of the License, or (at your option) any   ////
2034
//// later version.                                               ////
2035
////                                                              ////
2036
//// This source is distributed in the hope that it will be       ////
2037
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2038
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2039
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2040
//// details.                                                     ////
2041
////                                                              ////
2042
//// You should have received a copy of the GNU Lesser General    ////
2043
//// Public License along with this source; if not, download it   ////
2044
//// from http://www.opencores.org/lgpl.shtml                     ////
2045
////                                                              ////
2046
//////////////////////////////////////////////////////////////////////
2047
// GRAY counter
2048 18 unneback
module vl_cnt_gray_ce ( cke, q, rst, clk);
2049 6 unneback
   parameter length = 4;
2050
   input cke;
2051
   output reg [length:1] q;
2052
   input rst;
2053
   input clk;
2054
   parameter clear_value = 0;
2055
   parameter set_value = 1;
2056
   parameter wrap_value = 8;
2057
   parameter level1_value = 15;
2058
   reg  [length:1] qi;
2059
   wire [length:1] q_next;
2060
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2061
   always @ (posedge clk or posedge rst)
2062
     if (rst)
2063
       qi <= {length{1'b0}};
2064
     else
2065
     if (cke)
2066
       qi <= q_next;
2067
   always @ (posedge clk or posedge rst)
2068
     if (rst)
2069
       q <= {length{1'b0}};
2070
     else
2071
       if (cke)
2072
         q <= (q_next>>1) ^ q_next;
2073
endmodule
2074
//////////////////////////////////////////////////////////////////////
2075
////                                                              ////
2076
////  Versatile counter                                           ////
2077
////                                                              ////
2078
////  Description                                                 ////
2079
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2080
////  counter                                                     ////
2081
////                                                              ////
2082
////  To Do:                                                      ////
2083
////   - add LFSR with more taps                                  ////
2084
////                                                              ////
2085
////  Author(s):                                                  ////
2086
////      - Michael Unneback, unneback@opencores.org              ////
2087
////        ORSoC AB                                              ////
2088
////                                                              ////
2089
//////////////////////////////////////////////////////////////////////
2090
////                                                              ////
2091
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2092
////                                                              ////
2093
//// This source file may be used and distributed without         ////
2094
//// restriction provided that this copyright statement is not    ////
2095
//// removed from the file and that any derivative work contains  ////
2096
//// the original copyright notice and the associated disclaimer. ////
2097
////                                                              ////
2098
//// This source file is free software; you can redistribute it   ////
2099
//// and/or modify it under the terms of the GNU Lesser General   ////
2100
//// Public License as published by the Free Software Foundation; ////
2101
//// either version 2.1 of the License, or (at your option) any   ////
2102
//// later version.                                               ////
2103
////                                                              ////
2104
//// This source is distributed in the hope that it will be       ////
2105
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2106
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2107
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2108
//// details.                                                     ////
2109
////                                                              ////
2110
//// You should have received a copy of the GNU Lesser General    ////
2111
//// Public License along with this source; if not, download it   ////
2112
//// from http://www.opencores.org/lgpl.shtml                     ////
2113
////                                                              ////
2114
//////////////////////////////////////////////////////////////////////
2115
// GRAY counter
2116 18 unneback
module vl_cnt_gray_ce_bin ( cke, q, q_bin, rst, clk);
2117 6 unneback
   parameter length = 4;
2118
   input cke;
2119
   output reg [length:1] q;
2120
   output [length:1] q_bin;
2121
   input rst;
2122
   input clk;
2123
   parameter clear_value = 0;
2124
   parameter set_value = 1;
2125
   parameter wrap_value = 8;
2126
   parameter level1_value = 15;
2127
   reg  [length:1] qi;
2128
   wire [length:1] q_next;
2129
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2130
   always @ (posedge clk or posedge rst)
2131
     if (rst)
2132
       qi <= {length{1'b0}};
2133
     else
2134
     if (cke)
2135
       qi <= q_next;
2136
   always @ (posedge clk or posedge rst)
2137
     if (rst)
2138
       q <= {length{1'b0}};
2139
     else
2140
       if (cke)
2141
         q <= (q_next>>1) ^ q_next;
2142
   assign q_bin = qi;
2143
endmodule
2144
//////////////////////////////////////////////////////////////////////
2145
////                                                              ////
2146
////  Versatile library, counters                                 ////
2147
////                                                              ////
2148
////  Description                                                 ////
2149
////  counters                                                    ////
2150
////                                                              ////
2151
////                                                              ////
2152
////  To Do:                                                      ////
2153
////   - add more counters                                        ////
2154
////                                                              ////
2155
////  Author(s):                                                  ////
2156
////      - Michael Unneback, unneback@opencores.org              ////
2157
////        ORSoC AB                                              ////
2158
////                                                              ////
2159
//////////////////////////////////////////////////////////////////////
2160
////                                                              ////
2161
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2162
////                                                              ////
2163
//// This source file may be used and distributed without         ////
2164
//// restriction provided that this copyright statement is not    ////
2165
//// removed from the file and that any derivative work contains  ////
2166
//// the original copyright notice and the associated disclaimer. ////
2167
////                                                              ////
2168
//// This source file is free software; you can redistribute it   ////
2169
//// and/or modify it under the terms of the GNU Lesser General   ////
2170
//// Public License as published by the Free Software Foundation; ////
2171
//// either version 2.1 of the License, or (at your option) any   ////
2172
//// later version.                                               ////
2173
////                                                              ////
2174
//// This source is distributed in the hope that it will be       ////
2175
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2176
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2177
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2178
//// details.                                                     ////
2179
////                                                              ////
2180
//// You should have received a copy of the GNU Lesser General    ////
2181
//// Public License along with this source; if not, download it   ////
2182
//// from http://www.opencores.org/lgpl.shtml                     ////
2183
////                                                              ////
2184
//////////////////////////////////////////////////////////////////////
2185 18 unneback
module vl_cnt_shreg_wrap ( q, rst, clk);
2186 6 unneback
   parameter length = 4;
2187
   output reg [0:length-1] q;
2188
   input rst;
2189
   input clk;
2190
    always @ (posedge clk or posedge rst)
2191
    if (rst)
2192
        q <= {1'b1,{length-1{1'b0}}};
2193
    else
2194
        q <= {q[length-1],q[0:length-2]};
2195
endmodule
2196 18 unneback
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
2197 6 unneback
   parameter length = 4;
2198
   input cke;
2199
   output reg [0:length-1] q;
2200
   input rst;
2201
   input clk;
2202
    always @ (posedge clk or posedge rst)
2203
    if (rst)
2204
        q <= {1'b1,{length-1{1'b0}}};
2205
    else
2206
        if (cke)
2207
            q <= {q[length-1],q[0:length-2]};
2208
endmodule
2209 18 unneback
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
2210 6 unneback
   parameter length = 4;
2211
   input cke, clear;
2212
   output reg [0:length-1] q;
2213
   input rst;
2214
   input clk;
2215
    always @ (posedge clk or posedge rst)
2216
    if (rst)
2217
        q <= {1'b1,{length-1{1'b0}}};
2218
    else
2219
        if (cke)
2220
            if (clear)
2221
                q <= {1'b1,{length-1{1'b0}}};
2222
            else
2223
                q <= q >> 1;
2224
endmodule
2225 18 unneback
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
2226 6 unneback
   parameter length = 4;
2227
   input cke, clear;
2228
   output reg [0:length-1] q;
2229
   input rst;
2230
   input clk;
2231
    always @ (posedge clk or posedge rst)
2232
    if (rst)
2233
        q <= {1'b1,{length-1{1'b0}}};
2234
    else
2235
        if (cke)
2236
            if (clear)
2237
                q <= {1'b1,{length-1{1'b0}}};
2238
            else
2239
            q <= {q[length-1],q[0:length-2]};
2240
endmodule
2241
//////////////////////////////////////////////////////////////////////
2242
////                                                              ////
2243
////  Versatile library, memories                                 ////
2244
////                                                              ////
2245
////  Description                                                 ////
2246
////  memories                                                    ////
2247
////                                                              ////
2248
////                                                              ////
2249
////  To Do:                                                      ////
2250
////   - add more memory types                                    ////
2251
////                                                              ////
2252
////  Author(s):                                                  ////
2253
////      - Michael Unneback, unneback@opencores.org              ////
2254
////        ORSoC AB                                              ////
2255
////                                                              ////
2256
//////////////////////////////////////////////////////////////////////
2257
////                                                              ////
2258
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2259
////                                                              ////
2260
//// This source file may be used and distributed without         ////
2261
//// restriction provided that this copyright statement is not    ////
2262
//// removed from the file and that any derivative work contains  ////
2263
//// the original copyright notice and the associated disclaimer. ////
2264
////                                                              ////
2265
//// This source file is free software; you can redistribute it   ////
2266
//// and/or modify it under the terms of the GNU Lesser General   ////
2267
//// Public License as published by the Free Software Foundation; ////
2268
//// either version 2.1 of the License, or (at your option) any   ////
2269
//// later version.                                               ////
2270
////                                                              ////
2271
//// This source is distributed in the hope that it will be       ////
2272
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2273
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2274
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2275
//// details.                                                     ////
2276
////                                                              ////
2277
//// You should have received a copy of the GNU Lesser General    ////
2278
//// Public License along with this source; if not, download it   ////
2279
//// from http://www.opencores.org/lgpl.shtml                     ////
2280
////                                                              ////
2281
//////////////////////////////////////////////////////////////////////
2282
/// ROM
2283 7 unneback
module vl_rom_init ( adr, q, clk);
2284
   parameter data_width = 32;
2285
   parameter addr_width = 8;
2286
   input [(addr_width-1):0]       adr;
2287
   output reg [(data_width-1):0] q;
2288
   input                         clk;
2289
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
2290
   parameter memory_file = "vl_rom.vmem";
2291
   initial
2292
     begin
2293
        $readmemh(memory_file, rom);
2294
     end
2295
   always @ (posedge clk)
2296
     q <= rom[adr];
2297
endmodule
2298 14 unneback
/*
2299 7 unneback
module vl_rom ( adr, q, clk);
2300 6 unneback
parameter data_width = 32;
2301
parameter addr_width = 4;
2302
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
2303
    {32'h18000000},
2304
    {32'hA8200000},
2305
    {32'hA8200000},
2306
    {32'hA8200000},
2307
    {32'h44003000},
2308
    {32'h15000000},
2309
    {32'h15000000},
2310
    {32'h15000000},
2311
    {32'h15000000},
2312
    {32'h15000000},
2313
    {32'h15000000},
2314
    {32'h15000000},
2315
    {32'h15000000},
2316
    {32'h15000000},
2317
    {32'h15000000},
2318
    {32'h15000000}};
2319 7 unneback
input [addr_width-1:0] adr;
2320 6 unneback
output reg [data_width-1:0] q;
2321
input clk;
2322
always @ (posedge clk)
2323 7 unneback
    q <= data[adr];
2324 6 unneback
endmodule
2325 14 unneback
*/
2326 6 unneback
// Single port RAM
2327
module vl_ram ( d, adr, we, q, clk);
2328
   parameter data_width = 32;
2329
   parameter addr_width = 8;
2330
   input [(data_width-1):0]      d;
2331
   input [(addr_width-1):0]       adr;
2332
   input                         we;
2333 7 unneback
   output reg [(data_width-1):0] q;
2334 6 unneback
   input                         clk;
2335
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
2336 7 unneback
   parameter init = 0;
2337
   parameter memory_file = "vl_ram.vmem";
2338
   generate if (init) begin : init_mem
2339
   initial
2340
     begin
2341
        $readmemh(memory_file, ram);
2342
     end
2343
   end
2344
   endgenerate
2345 6 unneback
   always @ (posedge clk)
2346
   begin
2347
   if (we)
2348
     ram[adr] <= d;
2349
   q <= ram[adr];
2350
   end
2351
endmodule
2352 7 unneback
module vl_ram_be ( d, adr, be, we, q, clk);
2353
   parameter data_width = 32;
2354
   parameter addr_width = 8;
2355
   input [(data_width-1):0]      d;
2356
   input [(addr_width-1):0]       adr;
2357
   input [(addr_width/4)-1:0]    be;
2358
   input                         we;
2359
   output reg [(data_width-1):0] q;
2360
   input                         clk;
2361
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
2362
   parameter init = 0;
2363
   parameter memory_file = "vl_ram.vmem";
2364
   generate if (init) begin : init_mem
2365
   initial
2366
     begin
2367
        $readmemh(memory_file, ram);
2368
     end
2369
   end
2370
   endgenerate
2371
   genvar i;
2372
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
2373
      always @ (posedge clk)
2374
      if (we & be[i])
2375
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
2376
   end
2377
   endgenerate
2378
   always @ (posedge clk)
2379
      q <= ram[adr];
2380
endmodule
2381 6 unneback
// Dual port RAM
2382
// ACTEL FPGA should not use logic to handle rw collision
2383 7 unneback
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
2384 6 unneback
   parameter data_width = 32;
2385
   parameter addr_width = 8;
2386
   input [(data_width-1):0]      d_a;
2387
   input [(addr_width-1):0]       adr_a;
2388
   input [(addr_width-1):0]       adr_b;
2389
   input                         we_a;
2390
   output [(data_width-1):0]      q_b;
2391
   input                         clk_a, clk_b;
2392
   reg [(addr_width-1):0]         adr_b_reg;
2393
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
2394 7 unneback
   parameter init = 0;
2395
   parameter memory_file = "vl_ram.vmem";
2396
   generate if (init) begin : init_mem
2397
   initial
2398
     begin
2399
        $readmemh(memory_file, ram);
2400
     end
2401
   end
2402
   endgenerate
2403 6 unneback
   always @ (posedge clk_a)
2404
   if (we_a)
2405
     ram[adr_a] <= d_a;
2406
   always @ (posedge clk_b)
2407
   adr_b_reg <= adr_b;
2408
   assign q_b = ram[adr_b_reg];
2409
endmodule
2410 7 unneback
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
2411 6 unneback
   parameter data_width = 32;
2412
   parameter addr_width = 8;
2413
   input [(data_width-1):0]      d_a;
2414
   input [(addr_width-1):0]       adr_a;
2415
   input [(addr_width-1):0]       adr_b;
2416
   input                         we_a;
2417
   output [(data_width-1):0]      q_b;
2418
   output reg [(data_width-1):0] q_a;
2419
   input                         clk_a, clk_b;
2420
   reg [(data_width-1):0]         q_b;
2421
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
2422 7 unneback
   parameter init = 0;
2423
   parameter memory_file = "vl_ram.vmem";
2424
   generate if (init) begin : init_mem
2425
   initial
2426
     begin
2427
        $readmemh(memory_file, ram);
2428
     end
2429
   end
2430
   endgenerate
2431 6 unneback
   always @ (posedge clk_a)
2432
     begin
2433
        q_a <= ram[adr_a];
2434
        if (we_a)
2435
             ram[adr_a] <= d_a;
2436
     end
2437
   always @ (posedge clk_b)
2438
          q_b <= ram[adr_b];
2439
endmodule
2440 7 unneback
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
2441 6 unneback
   parameter data_width = 32;
2442
   parameter addr_width = 8;
2443
   input [(data_width-1):0]      d_a;
2444
   input [(addr_width-1):0]       adr_a;
2445
   input [(addr_width-1):0]       adr_b;
2446
   input                         we_a;
2447
   output [(data_width-1):0]      q_b;
2448
   input [(data_width-1):0]       d_b;
2449
   output reg [(data_width-1):0] q_a;
2450
   input                         we_b;
2451
   input                         clk_a, clk_b;
2452
   reg [(data_width-1):0]         q_b;
2453
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
2454 7 unneback
   parameter init = 0;
2455
   parameter memory_file = "vl_ram.vmem";
2456
   generate if (init) begin : init_mem
2457
   initial
2458
     begin
2459
        $readmemh(memory_file, ram);
2460
     end
2461
   end
2462
   endgenerate
2463 6 unneback
   always @ (posedge clk_a)
2464
     begin
2465
        q_a <= ram[adr_a];
2466
        if (we_a)
2467
             ram[adr_a] <= d_a;
2468
     end
2469
   always @ (posedge clk_b)
2470
     begin
2471
        q_b <= ram[adr_b];
2472
        if (we_b)
2473
          ram[adr_b] <= d_b;
2474
     end
2475
endmodule
2476
// Content addresable memory, CAM
2477
// FIFO
2478 25 unneback
module vl_fifo_1r1w_fill_level_sync (
2479
    d, wr, fifo_full,
2480
    q, rd, fifo_empty,
2481
    fill_level,
2482
    clk, rst
2483
    );
2484
parameter data_width = 18;
2485
parameter addr_width = 4;
2486
// write side
2487
input  [data_width-1:0] d;
2488
input                   wr;
2489
output                  fifo_full;
2490
// read side
2491
output [data_width-1:0] q;
2492
input                   rd;
2493
output                  fifo_empty;
2494
// common
2495
output [addr_width:0]   fill_level;
2496
input rst, clk;
2497
wire [addr_width:1] wadr, radr;
2498
vl_cnt_bin_ce
2499
    # ( .length(addr_width))
2500
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
2501
vl_cnt_bin_ce
2502
    # (.length(addr_width))
2503
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
2504
vl_dpram_1r1w
2505
    # (.data_width(data_width), .addr_width(addr_width))
2506
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
2507 31 unneback
vl_cnt_bin_ce_rew_q_zq_l1
2508 27 unneback
    # (.length(addr_width+1), .level1_value(1<<addr_width))
2509 25 unneback
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
2510
endmodule
2511 27 unneback
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
2512
// RAM is supposed to be larger than the two FIFOs
2513
// LFSR counters used adr pointers
2514
module vl_fifo_2r2w_sync_simplex (
2515
    // a side
2516
    a_d, a_wr, a_fifo_full,
2517
    a_q, a_rd, a_fifo_empty,
2518
    a_fill_level,
2519
    // b side
2520
    b_d, b_wr, b_fifo_full,
2521
    b_q, b_rd, b_fifo_empty,
2522
    b_fill_level,
2523
    // common
2524
    clk, rst
2525
    );
2526
parameter data_width = 8;
2527
parameter addr_width = 5;
2528
parameter fifo_full_level = (1<<addr_width)-1;
2529
// a side
2530
input  [data_width-1:0] a_d;
2531
input                   a_wr;
2532
output                  a_fifo_full;
2533
output [data_width-1:0] a_q;
2534
input                   a_rd;
2535
output                  a_fifo_empty;
2536
output [addr_width-1:0] a_fill_level;
2537
// b side
2538
input  [data_width-1:0] b_d;
2539
input                   b_wr;
2540
output                  b_fifo_full;
2541
output [data_width-1:0] b_q;
2542
input                   b_rd;
2543
output                  b_fifo_empty;
2544
output [addr_width-1:0] b_fill_level;
2545
input                   clk;
2546
input                   rst;
2547
// adr_gen
2548
wire [addr_width:1] a_wadr, a_radr;
2549
wire [addr_width:1] b_wadr, b_radr;
2550
// dpram
2551
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
2552
vl_cnt_lfsr_ce
2553
    # ( .length(addr_width))
2554
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
2555
vl_cnt_lfsr_ce
2556
    # (.length(addr_width))
2557
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
2558
vl_cnt_lfsr_ce
2559
    # ( .length(addr_width))
2560
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
2561
vl_cnt_lfsr_ce
2562
    # (.length(addr_width))
2563
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
2564
// mux read or write adr to DPRAM
2565
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
2566
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
2567
vl_dpram_2r2w
2568
    # (.data_width(data_width), .addr_width(addr_width+1))
2569
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
2570
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
2571
vl_cnt_bin_ce_rew_zq_l1
2572 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
2573 27 unneback
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
2574
vl_cnt_bin_ce_rew_zq_l1
2575 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
2576 27 unneback
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
2577
endmodule
2578 6 unneback
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
2579 11 unneback
   parameter addr_width = 4;
2580
   parameter N = addr_width-1;
2581 6 unneback
   parameter Q1 = 2'b00;
2582
   parameter Q2 = 2'b01;
2583
   parameter Q3 = 2'b11;
2584
   parameter Q4 = 2'b10;
2585
   parameter going_empty = 1'b0;
2586
   parameter going_full  = 1'b1;
2587
   input [N:0]  wptr, rptr;
2588 14 unneback
   output       fifo_empty;
2589 6 unneback
   output       fifo_full;
2590
   input        wclk, rclk, rst;
2591
   wire direction;
2592
   reg  direction_set, direction_clr;
2593
   wire async_empty, async_full;
2594
   wire fifo_full2;
2595 14 unneback
   wire fifo_empty2;
2596 6 unneback
   // direction_set
2597
   always @ (wptr[N:N-1] or rptr[N:N-1])
2598
     case ({wptr[N:N-1],rptr[N:N-1]})
2599
       {Q1,Q2} : direction_set <= 1'b1;
2600
       {Q2,Q3} : direction_set <= 1'b1;
2601
       {Q3,Q4} : direction_set <= 1'b1;
2602
       {Q4,Q1} : direction_set <= 1'b1;
2603
       default : direction_set <= 1'b0;
2604
     endcase
2605
   // direction_clear
2606
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
2607
     if (rst)
2608
       direction_clr <= 1'b1;
2609
     else
2610
       case ({wptr[N:N-1],rptr[N:N-1]})
2611
         {Q2,Q1} : direction_clr <= 1'b1;
2612
         {Q3,Q2} : direction_clr