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1 6 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
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////  Versatile library, clock and reset                          ////
4
////                                                              ////
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////  Description                                                 ////
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////  Logic related to clock and reset                            ////
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////                                                              ////
8
////                                                              ////
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////  To Do:                                                      ////
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////   - add more different registers                             ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
14
////        ORSoC AB                                              ////
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////                                                              ////
16
//////////////////////////////////////////////////////////////////////
17
////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
19
////                                                              ////
20
//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
36
////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
// Global buffer
43
// usage:
44
// use to enable global buffers for high fan out signals such as clock and reset
45
`timescale 1 ns/100 ps
46
// Version: 8.4 8.4.0.33
47
module gbuf(GL,CLK);
48
output GL;
49
input  CLK;
50
    wire GND;
51
    GND GND_1_net(.Y(GND));
52
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
53
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
54
endmodule
55
`timescale 1 ns/1 ns
56
module vl_gbuf ( i, o);
57
input i;
58
output o;
59
`ifdef SIM_GBUF
60
assign o=i;
61
`else
62
gbuf gbuf_i0 ( .CLK(i), .GL(o));
63
`endif
64
endmodule
65
 //ACTEL
66
// sync reset
67 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
68 6 unneback
// output active high global reset sync with two DFFs 
69
`timescale 1 ns/100 ps
70
module vl_sync_rst ( rst_n_i, rst_o, clk);
71
input rst_n_i, clk;
72
output rst_o;
73 18 unneback
reg [1:0] tmp;
74 6 unneback
always @ (posedge clk or negedge rst_n_i)
75
if (!rst_n_i)
76 17 unneback
        tmp <= 2'b11;
77 6 unneback
else
78 33 unneback
        tmp <= {1'b0,tmp[1]};
79 17 unneback
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
80 6 unneback
endmodule
81
// vl_pll
82 32 unneback
///////////////////////////////////////////////////////////////////////////////
83 17 unneback
`timescale 1 ps/1 ps
84 6 unneback
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
85
parameter index = 0;
86
parameter number_of_clk = 1;
87 17 unneback
parameter period_time_0 = 20000;
88
parameter period_time_1 = 20000;
89
parameter period_time_2 = 20000;
90
parameter lock_delay = 2000000;
91 6 unneback
input clk_i, rst_n_i;
92
output lock;
93
output reg [0:number_of_clk-1] clk_o;
94
output [0:number_of_clk-1] rst_o;
95
`ifdef SIM_PLL
96
always
97
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
98
generate if (number_of_clk > 1)
99
always
100
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
101
endgenerate
102
generate if (number_of_clk > 2)
103
always
104
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
105
endgenerate
106
genvar i;
107
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
108
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
109
end
110
endgenerate
111
assign #lock_delay lock = rst_n_i;
112
endmodule
113
`else
114
generate if (number_of_clk==1 & index==0) begin
115
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
116
end
117
endgenerate // index==0
118
generate if (number_of_clk==1 & index==1) begin
119
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
120
end
121
endgenerate // index==1
122
generate if (number_of_clk==1 & index==2) begin
123
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
124
end
125
endgenerate // index==2
126
generate if (number_of_clk==1 & index==3) begin
127
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
128
end
129
endgenerate // index==0
130
generate if (number_of_clk==2 & index==0) begin
131
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
132
end
133
endgenerate // index==0
134
generate if (number_of_clk==2 & index==1) begin
135
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
136
end
137
endgenerate // index==1
138
generate if (number_of_clk==2 & index==2) begin
139
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
140
end
141
endgenerate // index==2
142
generate if (number_of_clk==2 & index==3) begin
143
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
144
end
145
endgenerate // index==0
146
generate if (number_of_clk==3 & index==0) begin
147
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
148
end
149
endgenerate // index==0
150
generate if (number_of_clk==3 & index==1) begin
151
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
152
end
153
endgenerate // index==1
154
generate if (number_of_clk==3 & index==2) begin
155
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
156
end
157
endgenerate // index==2
158
generate if (number_of_clk==3 & index==3) begin
159
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
160
end
161
endgenerate // index==0
162
genvar i;
163
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
164
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
165
end
166
endgenerate
167
endmodule
168
`endif
169 32 unneback
///////////////////////////////////////////////////////////////////////////////
170 6 unneback
 //actel
171
//////////////////////////////////////////////////////////////////////
172
////                                                              ////
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////  Versatile library, registers                                ////
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////                                                              ////
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////  Description                                                 ////
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////  Different type of registers                                 ////
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////                                                              ////
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////                                                              ////
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////  To Do:                                                      ////
180
////   - add more different registers                             ////
181
////                                                              ////
182
////  Author(s):                                                  ////
183
////      - Michael Unneback, unneback@opencores.org              ////
184
////        ORSoC AB                                              ////
185
////                                                              ////
186
//////////////////////////////////////////////////////////////////////
187
////                                                              ////
188
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
189
////                                                              ////
190
//// This source file may be used and distributed without         ////
191
//// restriction provided that this copyright statement is not    ////
192
//// removed from the file and that any derivative work contains  ////
193
//// the original copyright notice and the associated disclaimer. ////
194
////                                                              ////
195
//// This source file is free software; you can redistribute it   ////
196
//// and/or modify it under the terms of the GNU Lesser General   ////
197
//// Public License as published by the Free Software Foundation; ////
198
//// either version 2.1 of the License, or (at your option) any   ////
199
//// later version.                                               ////
200
////                                                              ////
201
//// This source is distributed in the hope that it will be       ////
202
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
203
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
204
//// PURPOSE.  See the GNU Lesser General Public License for more ////
205
//// details.                                                     ////
206
////                                                              ////
207
//// You should have received a copy of the GNU Lesser General    ////
208
//// Public License along with this source; if not, download it   ////
209
//// from http://www.opencores.org/lgpl.shtml                     ////
210
////                                                              ////
211
//////////////////////////////////////////////////////////////////////
212 18 unneback
module vl_dff ( d, q, clk, rst);
213 6 unneback
        parameter width = 1;
214
        parameter reset_value = 0;
215
        input [width-1:0] d;
216
        input clk, rst;
217
        output reg [width-1:0] q;
218
        always @ (posedge clk or posedge rst)
219
        if (rst)
220
                q <= reset_value;
221
        else
222
                q <= d;
223
endmodule
224 18 unneback
module vl_dff_array ( d, q, clk, rst);
225 6 unneback
        parameter width = 1;
226
        parameter depth = 2;
227
        parameter reset_value = 1'b0;
228
        input [width-1:0] d;
229
        input clk, rst;
230
        output [width-1:0] q;
231
        reg  [0:depth-1] q_tmp [width-1:0];
232
        integer i;
233
        always @ (posedge clk or posedge rst)
234
        if (rst) begin
235
            for (i=0;i<depth;i=i+1)
236
                q_tmp[i] <= {width{reset_value}};
237
        end else begin
238
            q_tmp[0] <= d;
239
            for (i=1;i<depth;i=i+1)
240
                q_tmp[i] <= q_tmp[i-1];
241
        end
242
    assign q = q_tmp[depth-1];
243
endmodule
244 18 unneback
module vl_dff_ce ( d, ce, q, clk, rst);
245 6 unneback
        parameter width = 1;
246
        parameter reset_value = 0;
247
        input [width-1:0] d;
248
        input ce, clk, rst;
249
        output reg [width-1:0] q;
250
        always @ (posedge clk or posedge rst)
251
        if (rst)
252
                q <= reset_value;
253
        else
254
                if (ce)
255
                        q <= d;
256
endmodule
257 18 unneback
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
258 8 unneback
        parameter width = 1;
259
        parameter reset_value = 0;
260
        input [width-1:0] d;
261 10 unneback
        input ce, clear, clk, rst;
262 8 unneback
        output reg [width-1:0] q;
263
        always @ (posedge clk or posedge rst)
264
        if (rst)
265
            q <= reset_value;
266
        else
267
            if (ce)
268
                if (clear)
269
                    q <= {width{1'b0}};
270
                else
271
                    q <= d;
272
endmodule
273 24 unneback
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
274
        parameter width = 1;
275
        parameter reset_value = 0;
276
        input [width-1:0] d;
277
        input ce, set, clk, rst;
278
        output reg [width-1:0] q;
279
        always @ (posedge clk or posedge rst)
280
        if (rst)
281
            q <= reset_value;
282
        else
283
            if (ce)
284
                if (set)
285
                    q <= {width{1'b1}};
286
                else
287
                    q <= d;
288
endmodule
289 29 unneback
module vl_spr ( sp, r, q, clk, rst);
290
        parameter width = 1;
291
        parameter reset_value = 0;
292
        input sp, r;
293
        output reg q;
294
        input clk, rst;
295
        always @ (posedge clk or posedge rst)
296
        if (rst)
297
            q <= reset_value;
298
        else
299
            if (sp)
300
                q <= 1'b1;
301
            else if (r)
302
                q <= 1'b0;
303
endmodule
304
module vl_srp ( s, rp, q, clk, rst);
305
        parameter width = 1;
306
        parameter reset_value = 0;
307
        input s, rp;
308
        output reg q;
309
        input clk, rst;
310
        always @ (posedge clk or posedge rst)
311
        if (rst)
312
            q <= reset_value;
313
        else
314
            if (rp)
315
                q <= 1'b0;
316
            else if (s)
317
                q <= 1'b1;
318
endmodule
319 18 unneback
module vl_dff_sr ( aclr, aset, clock, data, q);
320 6 unneback
    input         aclr;
321
    input         aset;
322
    input         clock;
323
    input         data;
324
    output reg    q;
325
   always @ (posedge clock or posedge aclr or posedge aset)
326
     if (aclr)
327
       q <= 1'b0;
328
     else if (aset)
329
       q <= 1'b1;
330
     else
331
       q <= data;
332
endmodule
333
// LATCH
334
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
335
module latch ( d, le, q, clk);
336
input d, le;
337
output q;
338
input clk;/*
339
   always @ (posedge direction_set or posedge direction_clr)
340
     if (direction_clr)
341
       direction <= going_empty;
342
     else
343
       direction <= going_full;*/
344
endmodule
345 18 unneback
module vl_shreg ( d, q, clk, rst);
346 17 unneback
parameter depth = 10;
347
input d;
348
output q;
349
input clk, rst;
350
reg [1:depth] dffs;
351
always @ (posedge clk or posedge rst)
352
if (rst)
353
    dffs <= {depth{1'b0}};
354
else
355
    dffs <= {d,dffs[1:depth-1]};
356
assign q = dffs[depth];
357
endmodule
358 18 unneback
module vl_shreg_ce ( d, ce, q, clk, rst);
359 17 unneback
parameter depth = 10;
360
input d, ce;
361
output q;
362
input clk, rst;
363
reg [1:depth] dffs;
364
always @ (posedge clk or posedge rst)
365
if (rst)
366
    dffs <= {depth{1'b0}};
367
else
368
    if (ce)
369
        dffs <= {d,dffs[1:depth-1]};
370
assign q = dffs[depth];
371
endmodule
372 18 unneback
module vl_delay ( d, q, clk, rst);
373 15 unneback
parameter depth = 10;
374
input d;
375
output q;
376
input clk, rst;
377
reg [1:depth] dffs;
378
always @ (posedge clk or posedge rst)
379
if (rst)
380
    dffs <= {depth{1'b0}};
381
else
382
    dffs <= {d,dffs[1:depth-1]};
383
assign q = dffs[depth];
384
endmodule
385 18 unneback
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
386 17 unneback
parameter depth = 10;
387
input d;
388
output q, emptyflag;
389
input clk, rst;
390
reg [1:depth] dffs;
391
always @ (posedge clk or posedge rst)
392
if (rst)
393
    dffs <= {depth{1'b0}};
394
else
395
    dffs <= {d,dffs[1:depth-1]};
396
assign q = dffs[depth];
397
assign emptyflag = !(|dffs);
398
endmodule
399 6 unneback
//////////////////////////////////////////////////////////////////////
400
////                                                              ////
401 18 unneback
////  Logic functions                                             ////
402
////                                                              ////
403
////  Description                                                 ////
404
////  Logic functions such as multiplexers                        ////
405
////                                                              ////
406
////                                                              ////
407
////  To Do:                                                      ////
408
////   -                                                          ////
409
////                                                              ////
410
////  Author(s):                                                  ////
411
////      - Michael Unneback, unneback@opencores.org              ////
412
////        ORSoC AB                                              ////
413
////                                                              ////
414
//////////////////////////////////////////////////////////////////////
415
////                                                              ////
416
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
417
////                                                              ////
418
//// This source file may be used and distributed without         ////
419
//// restriction provided that this copyright statement is not    ////
420
//// removed from the file and that any derivative work contains  ////
421
//// the original copyright notice and the associated disclaimer. ////
422
////                                                              ////
423
//// This source file is free software; you can redistribute it   ////
424
//// and/or modify it under the terms of the GNU Lesser General   ////
425
//// Public License as published by the Free Software Foundation; ////
426
//// either version 2.1 of the License, or (at your option) any   ////
427
//// later version.                                               ////
428
////                                                              ////
429
//// This source is distributed in the hope that it will be       ////
430
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
431
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
432
//// PURPOSE.  See the GNU Lesser General Public License for more ////
433
//// details.                                                     ////
434
////                                                              ////
435
//// You should have received a copy of the GNU Lesser General    ////
436
//// Public License along with this source; if not, download it   ////
437
//// from http://www.opencores.org/lgpl.shtml                     ////
438
////                                                              ////
439
//////////////////////////////////////////////////////////////////////
440 36 unneback
module vl_mux_andor ( a, sel, dout);
441
parameter width = 32;
442
parameter nr_of_ports = 4;
443
input [nr_of_ports*width-1:0] a;
444
input [nr_of_ports-1:0] sel;
445
output reg [width-1:0] dout;
446 38 unneback
integer i,j;
447 36 unneback
always @ (a, sel)
448
begin
449
    dout = a[width-1:0] & {width{sel[0]}};
450
    for (i=nr_of_ports-2;i<nr_of_ports;i=i+1)
451 38 unneback
        for (j=0;j<32;j=j+1)
452
            dout[j] = (a[(i-1)*width + j] & sel[i]) | dout[j];
453 36 unneback
end
454
endmodule
455 34 unneback
module vl_mux2_andor ( a1, a0, sel, dout);
456
parameter width = 32;
457 35 unneback
localparam nr_of_ports = 2;
458 34 unneback
input [width-1:0] a1, a0;
459
input [nr_of_ports-1:0] sel;
460
output [width-1:0] dout;
461 36 unneback
vl_mux_andor
462 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
463 36 unneback
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
464 34 unneback
endmodule
465
module vl_mux3_andor ( a2, a1, a0, sel, dout);
466
parameter width = 32;
467 35 unneback
localparam nr_of_ports = 3;
468 34 unneback
input [width-1:0] a2, a1, a0;
469
input [nr_of_ports-1:0] sel;
470
output [width-1:0] dout;
471 36 unneback
vl_mux_andor
472 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
473 36 unneback
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
474 34 unneback
endmodule
475 18 unneback
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
476
parameter width = 32;
477 35 unneback
localparam nr_of_ports = 4;
478 18 unneback
input [width-1:0] a3, a2, a1, a0;
479
input [nr_of_ports-1:0] sel;
480 22 unneback
output [width-1:0] dout;
481 36 unneback
vl_mux_andor
482 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
483 36 unneback
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
484 18 unneback
endmodule
485
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
486
parameter width = 32;
487 35 unneback
localparam nr_of_ports = 5;
488 18 unneback
input [width-1:0] a4, a3, a2, a1, a0;
489
input [nr_of_ports-1:0] sel;
490 22 unneback
output [width-1:0] dout;
491 36 unneback
vl_mux_andor
492 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
493 36 unneback
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
494 18 unneback
endmodule
495
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
496
parameter width = 32;
497 35 unneback
localparam nr_of_ports = 6;
498 18 unneback
input [width-1:0] a5, a4, a3, a2, a1, a0;
499
input [nr_of_ports-1:0] sel;
500 22 unneback
output [width-1:0] dout;
501 36 unneback
vl_mux_andor
502 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
503 36 unneback
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
504 18 unneback
endmodule
505
//////////////////////////////////////////////////////////////////////
506
////                                                              ////
507 6 unneback
////  Versatile counter                                           ////
508
////                                                              ////
509
////  Description                                                 ////
510
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
511
////  counter                                                     ////
512
////                                                              ////
513
////  To Do:                                                      ////
514
////   - add LFSR with more taps                                  ////
515
////                                                              ////
516
////  Author(s):                                                  ////
517
////      - Michael Unneback, unneback@opencores.org              ////
518
////        ORSoC AB                                              ////
519
////                                                              ////
520
//////////////////////////////////////////////////////////////////////
521
////                                                              ////
522
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
523
////                                                              ////
524
//// This source file may be used and distributed without         ////
525
//// restriction provided that this copyright statement is not    ////
526
//// removed from the file and that any derivative work contains  ////
527
//// the original copyright notice and the associated disclaimer. ////
528
////                                                              ////
529
//// This source file is free software; you can redistribute it   ////
530
//// and/or modify it under the terms of the GNU Lesser General   ////
531
//// Public License as published by the Free Software Foundation; ////
532
//// either version 2.1 of the License, or (at your option) any   ////
533
//// later version.                                               ////
534
////                                                              ////
535
//// This source is distributed in the hope that it will be       ////
536
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
537
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
538
//// PURPOSE.  See the GNU Lesser General Public License for more ////
539
//// details.                                                     ////
540
////                                                              ////
541
//// You should have received a copy of the GNU Lesser General    ////
542
//// Public License along with this source; if not, download it   ////
543
//// from http://www.opencores.org/lgpl.shtml                     ////
544
////                                                              ////
545
//////////////////////////////////////////////////////////////////////
546
// binary counter
547 22 unneback
module vl_cnt_bin ( q, rst, clk);
548
   parameter length = 4;
549
   output [length:1] q;
550
   input rst;
551
   input clk;
552
   parameter clear_value = 0;
553
   parameter set_value = 1;
554
   parameter wrap_value = 0;
555
   parameter level1_value = 15;
556
   reg  [length:1] qi;
557
   wire [length:1] q_next;
558
   assign q_next = qi + {{length-1{1'b0}},1'b1};
559
   always @ (posedge clk or posedge rst)
560
     if (rst)
561
       qi <= {length{1'b0}};
562
     else
563
       qi <= q_next;
564
   assign q = qi;
565
endmodule
566
//////////////////////////////////////////////////////////////////////
567
////                                                              ////
568
////  Versatile counter                                           ////
569
////                                                              ////
570
////  Description                                                 ////
571
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
572
////  counter                                                     ////
573
////                                                              ////
574
////  To Do:                                                      ////
575
////   - add LFSR with more taps                                  ////
576
////                                                              ////
577
////  Author(s):                                                  ////
578
////      - Michael Unneback, unneback@opencores.org              ////
579
////        ORSoC AB                                              ////
580
////                                                              ////
581
//////////////////////////////////////////////////////////////////////
582
////                                                              ////
583
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
584
////                                                              ////
585
//// This source file may be used and distributed without         ////
586
//// restriction provided that this copyright statement is not    ////
587
//// removed from the file and that any derivative work contains  ////
588
//// the original copyright notice and the associated disclaimer. ////
589
////                                                              ////
590
//// This source file is free software; you can redistribute it   ////
591
//// and/or modify it under the terms of the GNU Lesser General   ////
592
//// Public License as published by the Free Software Foundation; ////
593
//// either version 2.1 of the License, or (at your option) any   ////
594
//// later version.                                               ////
595
////                                                              ////
596
//// This source is distributed in the hope that it will be       ////
597
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
598
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
599
//// PURPOSE.  See the GNU Lesser General Public License for more ////
600
//// details.                                                     ////
601
////                                                              ////
602
//// You should have received a copy of the GNU Lesser General    ////
603
//// Public License along with this source; if not, download it   ////
604
//// from http://www.opencores.org/lgpl.shtml                     ////
605
////                                                              ////
606
//////////////////////////////////////////////////////////////////////
607
// binary counter
608
module vl_cnt_bin_clear ( clear, q, rst, clk);
609
   parameter length = 4;
610
   input clear;
611
   output [length:1] q;
612
   input rst;
613
   input clk;
614
   parameter clear_value = 0;
615
   parameter set_value = 1;
616
   parameter wrap_value = 0;
617
   parameter level1_value = 15;
618
   reg  [length:1] qi;
619
   wire [length:1] q_next;
620
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
621
   always @ (posedge clk or posedge rst)
622
     if (rst)
623
       qi <= {length{1'b0}};
624
     else
625
       qi <= q_next;
626
   assign q = qi;
627
endmodule
628
//////////////////////////////////////////////////////////////////////
629
////                                                              ////
630
////  Versatile counter                                           ////
631
////                                                              ////
632
////  Description                                                 ////
633
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
634
////  counter                                                     ////
635
////                                                              ////
636
////  To Do:                                                      ////
637
////   - add LFSR with more taps                                  ////
638
////                                                              ////
639
////  Author(s):                                                  ////
640
////      - Michael Unneback, unneback@opencores.org              ////
641
////        ORSoC AB                                              ////
642
////                                                              ////
643
//////////////////////////////////////////////////////////////////////
644
////                                                              ////
645
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
646
////                                                              ////
647
//// This source file may be used and distributed without         ////
648
//// restriction provided that this copyright statement is not    ////
649
//// removed from the file and that any derivative work contains  ////
650
//// the original copyright notice and the associated disclaimer. ////
651
////                                                              ////
652
//// This source file is free software; you can redistribute it   ////
653
//// and/or modify it under the terms of the GNU Lesser General   ////
654
//// Public License as published by the Free Software Foundation; ////
655
//// either version 2.1 of the License, or (at your option) any   ////
656
//// later version.                                               ////
657
////                                                              ////
658
//// This source is distributed in the hope that it will be       ////
659
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
660
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
661
//// PURPOSE.  See the GNU Lesser General Public License for more ////
662
//// details.                                                     ////
663
////                                                              ////
664
//// You should have received a copy of the GNU Lesser General    ////
665
//// Public License along with this source; if not, download it   ////
666
//// from http://www.opencores.org/lgpl.shtml                     ////
667
////                                                              ////
668
//////////////////////////////////////////////////////////////////////
669
// binary counter
670 18 unneback
module vl_cnt_bin_ce ( cke, q, rst, clk);
671 6 unneback
   parameter length = 4;
672
   input cke;
673
   output [length:1] q;
674
   input rst;
675
   input clk;
676
   parameter clear_value = 0;
677
   parameter set_value = 1;
678
   parameter wrap_value = 0;
679
   parameter level1_value = 15;
680
   reg  [length:1] qi;
681
   wire [length:1] q_next;
682
   assign q_next = qi + {{length-1{1'b0}},1'b1};
683
   always @ (posedge clk or posedge rst)
684
     if (rst)
685
       qi <= {length{1'b0}};
686
     else
687
     if (cke)
688
       qi <= q_next;
689
   assign q = qi;
690
endmodule
691
//////////////////////////////////////////////////////////////////////
692
////                                                              ////
693
////  Versatile counter                                           ////
694
////                                                              ////
695
////  Description                                                 ////
696
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
697
////  counter                                                     ////
698
////                                                              ////
699
////  To Do:                                                      ////
700
////   - add LFSR with more taps                                  ////
701
////                                                              ////
702
////  Author(s):                                                  ////
703
////      - Michael Unneback, unneback@opencores.org              ////
704
////        ORSoC AB                                              ////
705
////                                                              ////
706
//////////////////////////////////////////////////////////////////////
707
////                                                              ////
708
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
709
////                                                              ////
710
//// This source file may be used and distributed without         ////
711
//// restriction provided that this copyright statement is not    ////
712
//// removed from the file and that any derivative work contains  ////
713
//// the original copyright notice and the associated disclaimer. ////
714
////                                                              ////
715
//// This source file is free software; you can redistribute it   ////
716
//// and/or modify it under the terms of the GNU Lesser General   ////
717
//// Public License as published by the Free Software Foundation; ////
718
//// either version 2.1 of the License, or (at your option) any   ////
719
//// later version.                                               ////
720
////                                                              ////
721
//// This source is distributed in the hope that it will be       ////
722
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
723
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
724
//// PURPOSE.  See the GNU Lesser General Public License for more ////
725
//// details.                                                     ////
726
////                                                              ////
727
//// You should have received a copy of the GNU Lesser General    ////
728
//// Public License along with this source; if not, download it   ////
729
//// from http://www.opencores.org/lgpl.shtml                     ////
730
////                                                              ////
731
//////////////////////////////////////////////////////////////////////
732
// binary counter
733 18 unneback
module vl_cnt_bin_ce_clear ( clear, cke, q, rst, clk);
734 6 unneback
   parameter length = 4;
735
   input clear;
736
   input cke;
737
   output [length:1] q;
738
   input rst;
739
   input clk;
740
   parameter clear_value = 0;
741
   parameter set_value = 1;
742
   parameter wrap_value = 0;
743
   parameter level1_value = 15;
744
   reg  [length:1] qi;
745
   wire [length:1] q_next;
746
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
747
   always @ (posedge clk or posedge rst)
748
     if (rst)
749
       qi <= {length{1'b0}};
750
     else
751
     if (cke)
752
       qi <= q_next;
753
   assign q = qi;
754
endmodule
755
//////////////////////////////////////////////////////////////////////
756
////                                                              ////
757
////  Versatile counter                                           ////
758
////                                                              ////
759
////  Description                                                 ////
760
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
761
////  counter                                                     ////
762
////                                                              ////
763
////  To Do:                                                      ////
764
////   - add LFSR with more taps                                  ////
765
////                                                              ////
766
////  Author(s):                                                  ////
767
////      - Michael Unneback, unneback@opencores.org              ////
768
////        ORSoC AB                                              ////
769
////                                                              ////
770
//////////////////////////////////////////////////////////////////////
771
////                                                              ////
772
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
773
////                                                              ////
774
//// This source file may be used and distributed without         ////
775
//// restriction provided that this copyright statement is not    ////
776
//// removed from the file and that any derivative work contains  ////
777
//// the original copyright notice and the associated disclaimer. ////
778
////                                                              ////
779
//// This source file is free software; you can redistribute it   ////
780
//// and/or modify it under the terms of the GNU Lesser General   ////
781
//// Public License as published by the Free Software Foundation; ////
782
//// either version 2.1 of the License, or (at your option) any   ////
783
//// later version.                                               ////
784
////                                                              ////
785
//// This source is distributed in the hope that it will be       ////
786
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
787
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
788
//// PURPOSE.  See the GNU Lesser General Public License for more ////
789
//// details.                                                     ////
790
////                                                              ////
791
//// You should have received a copy of the GNU Lesser General    ////
792
//// Public License along with this source; if not, download it   ////
793
//// from http://www.opencores.org/lgpl.shtml                     ////
794
////                                                              ////
795
//////////////////////////////////////////////////////////////////////
796
// binary counter
797 29 unneback
module vl_cnt_bin_ce_clear_l1_l2 ( clear, cke, q, level1, level2, rst, clk);
798
   parameter length = 4;
799
   input clear;
800
   input cke;
801
   output [length:1] q;
802
   output reg level1;
803
   output reg level2;
804
   input rst;
805
   input clk;
806
   parameter clear_value = 0;
807
   parameter set_value = 1;
808 30 unneback
   parameter wrap_value = 15;
809
   parameter level1_value = 8;
810
   parameter level2_value = 15;
811 29 unneback
   wire rew;
812 30 unneback
   assign rew = 1'b0;
813 29 unneback
   reg  [length:1] qi;
814
   wire [length:1] q_next;
815
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
816
   always @ (posedge clk or posedge rst)
817
     if (rst)
818
       qi <= {length{1'b0}};
819
     else
820
     if (cke)
821
       qi <= q_next;
822
   assign q = qi;
823
    always @ (posedge clk or posedge rst)
824
    if (rst)
825
        level1 <= 1'b0;
826
    else
827
    if (cke)
828
    if (clear)
829
        level1 <= 1'b0;
830
    else if (q_next == level1_value)
831
        level1 <= 1'b1;
832
    else if (qi == level1_value & rew)
833
        level1 <= 1'b0;
834
    always @ (posedge clk or posedge rst)
835
    if (rst)
836
        level2 <= 1'b0;
837
    else
838
    if (cke)
839
    if (clear)
840
        level2 <= 1'b0;
841
    else if (q_next == level2_value)
842
        level2 <= 1'b1;
843
    else if (qi == level2_value & rew)
844
        level2 <= 1'b0;
845
endmodule
846
//////////////////////////////////////////////////////////////////////
847
////                                                              ////
848
////  Versatile counter                                           ////
849
////                                                              ////
850
////  Description                                                 ////
851
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
852
////  counter                                                     ////
853
////                                                              ////
854
////  To Do:                                                      ////
855
////   - add LFSR with more taps                                  ////
856
////                                                              ////
857
////  Author(s):                                                  ////
858
////      - Michael Unneback, unneback@opencores.org              ////
859
////        ORSoC AB                                              ////
860
////                                                              ////
861
//////////////////////////////////////////////////////////////////////
862
////                                                              ////
863
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
864
////                                                              ////
865
//// This source file may be used and distributed without         ////
866
//// restriction provided that this copyright statement is not    ////
867
//// removed from the file and that any derivative work contains  ////
868
//// the original copyright notice and the associated disclaimer. ////
869
////                                                              ////
870
//// This source file is free software; you can redistribute it   ////
871
//// and/or modify it under the terms of the GNU Lesser General   ////
872
//// Public License as published by the Free Software Foundation; ////
873
//// either version 2.1 of the License, or (at your option) any   ////
874
//// later version.                                               ////
875
////                                                              ////
876
//// This source is distributed in the hope that it will be       ////
877
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
878
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
879
//// PURPOSE.  See the GNU Lesser General Public License for more ////
880
//// details.                                                     ////
881
////                                                              ////
882
//// You should have received a copy of the GNU Lesser General    ////
883
//// Public License along with this source; if not, download it   ////
884
//// from http://www.opencores.org/lgpl.shtml                     ////
885
////                                                              ////
886
//////////////////////////////////////////////////////////////////////
887
// binary counter
888 18 unneback
module vl_cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk);
889 6 unneback
   parameter length = 4;
890
   input clear;
891
   input set;
892
   input cke;
893
   input rew;
894
   output [length:1] q;
895
   input rst;
896
   input clk;
897
   parameter clear_value = 0;
898
   parameter set_value = 1;
899
   parameter wrap_value = 0;
900
   parameter level1_value = 15;
901
   reg  [length:1] qi;
902
   wire  [length:1] q_next, q_next_fw, q_next_rew;
903
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
904
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
905
   assign q_next = rew ? q_next_rew : q_next_fw;
906
   always @ (posedge clk or posedge rst)
907
     if (rst)
908
       qi <= {length{1'b0}};
909
     else
910
     if (cke)
911
       qi <= q_next;
912
   assign q = qi;
913
endmodule
914
//////////////////////////////////////////////////////////////////////
915
////                                                              ////
916
////  Versatile counter                                           ////
917
////                                                              ////
918
////  Description                                                 ////
919
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
920
////  counter                                                     ////
921
////                                                              ////
922
////  To Do:                                                      ////
923
////   - add LFSR with more taps                                  ////
924
////                                                              ////
925
////  Author(s):                                                  ////
926
////      - Michael Unneback, unneback@opencores.org              ////
927
////        ORSoC AB                                              ////
928
////                                                              ////
929
//////////////////////////////////////////////////////////////////////
930
////                                                              ////
931
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
932
////                                                              ////
933
//// This source file may be used and distributed without         ////
934
//// restriction provided that this copyright statement is not    ////
935
//// removed from the file and that any derivative work contains  ////
936
//// the original copyright notice and the associated disclaimer. ////
937
////                                                              ////
938
//// This source file is free software; you can redistribute it   ////
939
//// and/or modify it under the terms of the GNU Lesser General   ////
940
//// Public License as published by the Free Software Foundation; ////
941
//// either version 2.1 of the License, or (at your option) any   ////
942
//// later version.                                               ////
943
////                                                              ////
944
//// This source is distributed in the hope that it will be       ////
945
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
946
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
947
//// PURPOSE.  See the GNU Lesser General Public License for more ////
948
//// details.                                                     ////
949
////                                                              ////
950
//// You should have received a copy of the GNU Lesser General    ////
951
//// Public License along with this source; if not, download it   ////
952
//// from http://www.opencores.org/lgpl.shtml                     ////
953
////                                                              ////
954
//////////////////////////////////////////////////////////////////////
955
// binary counter
956 18 unneback
module vl_cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk);
957 6 unneback
   parameter length = 4;
958
   input cke;
959
   input rew;
960
   output reg level1;
961
   input rst;
962
   input clk;
963
   parameter clear_value = 0;
964
   parameter set_value = 1;
965
   parameter wrap_value = 1;
966
   parameter level1_value = 15;
967 29 unneback
   wire clear;
968 30 unneback
   assign clear = 1'b0;
969 6 unneback
   reg  [length:1] qi;
970
   wire  [length:1] q_next, q_next_fw, q_next_rew;
971
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
972
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
973
   assign q_next = rew ? q_next_rew : q_next_fw;
974
   always @ (posedge clk or posedge rst)
975
     if (rst)
976
       qi <= {length{1'b0}};
977
     else
978
     if (cke)
979
       qi <= q_next;
980
    always @ (posedge clk or posedge rst)
981
    if (rst)
982
        level1 <= 1'b0;
983
    else
984
    if (cke)
985 29 unneback
    if (clear)
986
        level1 <= 1'b0;
987
    else if (q_next == level1_value)
988 6 unneback
        level1 <= 1'b1;
989
    else if (qi == level1_value & rew)
990
        level1 <= 1'b0;
991
endmodule
992
//////////////////////////////////////////////////////////////////////
993
////                                                              ////
994
////  Versatile counter                                           ////
995
////                                                              ////
996
////  Description                                                 ////
997
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
998
////  counter                                                     ////
999
////                                                              ////
1000
////  To Do:                                                      ////
1001
////   - add LFSR with more taps                                  ////
1002
////                                                              ////
1003
////  Author(s):                                                  ////
1004
////      - Michael Unneback, unneback@opencores.org              ////
1005
////        ORSoC AB                                              ////
1006
////                                                              ////
1007
//////////////////////////////////////////////////////////////////////
1008
////                                                              ////
1009
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1010
////                                                              ////
1011
//// This source file may be used and distributed without         ////
1012
//// restriction provided that this copyright statement is not    ////
1013
//// removed from the file and that any derivative work contains  ////
1014
//// the original copyright notice and the associated disclaimer. ////
1015
////                                                              ////
1016
//// This source file is free software; you can redistribute it   ////
1017
//// and/or modify it under the terms of the GNU Lesser General   ////
1018
//// Public License as published by the Free Software Foundation; ////
1019
//// either version 2.1 of the License, or (at your option) any   ////
1020
//// later version.                                               ////
1021
////                                                              ////
1022
//// This source is distributed in the hope that it will be       ////
1023
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1024
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1025
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1026
//// details.                                                     ////
1027
////                                                              ////
1028
//// You should have received a copy of the GNU Lesser General    ////
1029
//// Public License along with this source; if not, download it   ////
1030
//// from http://www.opencores.org/lgpl.shtml                     ////
1031
////                                                              ////
1032
//////////////////////////////////////////////////////////////////////
1033 25 unneback
// binary counter
1034
module vl_cnt_bin_ce_rew_zq_l1 ( cke, rew, zq, level1, rst, clk);
1035
   parameter length = 4;
1036
   input cke;
1037
   input rew;
1038
   output reg zq;
1039
   output reg level1;
1040
   input rst;
1041
   input clk;
1042
   parameter clear_value = 0;
1043
   parameter set_value = 1;
1044
   parameter wrap_value = 1;
1045
   parameter level1_value = 15;
1046 29 unneback
   wire clear;
1047 30 unneback
   assign clear = 1'b0;
1048 25 unneback
   reg  [length:1] qi;
1049
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1050
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1051
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1052
   assign q_next = rew ? q_next_rew : q_next_fw;
1053
   always @ (posedge clk or posedge rst)
1054
     if (rst)
1055
       qi <= {length{1'b0}};
1056
     else
1057
     if (cke)
1058
       qi <= q_next;
1059
   always @ (posedge clk or posedge rst)
1060
     if (rst)
1061
       zq <= 1'b1;
1062
     else
1063
     if (cke)
1064
       zq <= q_next == {length{1'b0}};
1065
    always @ (posedge clk or posedge rst)
1066
    if (rst)
1067
        level1 <= 1'b0;
1068
    else
1069
    if (cke)
1070 29 unneback
    if (clear)
1071
        level1 <= 1'b0;
1072
    else if (q_next == level1_value)
1073 25 unneback
        level1 <= 1'b1;
1074
    else if (qi == level1_value & rew)
1075
        level1 <= 1'b0;
1076
endmodule
1077
//////////////////////////////////////////////////////////////////////
1078
////                                                              ////
1079
////  Versatile counter                                           ////
1080
////                                                              ////
1081
////  Description                                                 ////
1082
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1083
////  counter                                                     ////
1084
////                                                              ////
1085
////  To Do:                                                      ////
1086
////   - add LFSR with more taps                                  ////
1087
////                                                              ////
1088
////  Author(s):                                                  ////
1089
////      - Michael Unneback, unneback@opencores.org              ////
1090
////        ORSoC AB                                              ////
1091
////                                                              ////
1092
//////////////////////////////////////////////////////////////////////
1093
////                                                              ////
1094
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1095
////                                                              ////
1096
//// This source file may be used and distributed without         ////
1097
//// restriction provided that this copyright statement is not    ////
1098
//// removed from the file and that any derivative work contains  ////
1099
//// the original copyright notice and the associated disclaimer. ////
1100
////                                                              ////
1101
//// This source file is free software; you can redistribute it   ////
1102
//// and/or modify it under the terms of the GNU Lesser General   ////
1103
//// Public License as published by the Free Software Foundation; ////
1104
//// either version 2.1 of the License, or (at your option) any   ////
1105
//// later version.                                               ////
1106
////                                                              ////
1107
//// This source is distributed in the hope that it will be       ////
1108
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1109
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1110
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1111
//// details.                                                     ////
1112
////                                                              ////
1113
//// You should have received a copy of the GNU Lesser General    ////
1114
//// Public License along with this source; if not, download it   ////
1115
//// from http://www.opencores.org/lgpl.shtml                     ////
1116
////                                                              ////
1117
//////////////////////////////////////////////////////////////////////
1118
// binary counter
1119
module vl_cnt_bin_ce_rew_q_zq_l1 ( cke, rew, q, zq, level1, rst, clk);
1120
   parameter length = 4;
1121
   input cke;
1122
   input rew;
1123
   output [length:1] q;
1124
   output reg zq;
1125
   output reg level1;
1126
   input rst;
1127
   input clk;
1128
   parameter clear_value = 0;
1129
   parameter set_value = 1;
1130
   parameter wrap_value = 1;
1131
   parameter level1_value = 15;
1132 29 unneback
   wire clear;
1133 30 unneback
   assign clear = 1'b0;
1134 25 unneback
   reg  [length:1] qi;
1135
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1136
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1137
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1138
   assign q_next = rew ? q_next_rew : q_next_fw;
1139
   always @ (posedge clk or posedge rst)
1140
     if (rst)
1141
       qi <= {length{1'b0}};
1142
     else
1143
     if (cke)
1144
       qi <= q_next;
1145
   assign q = qi;
1146
   always @ (posedge clk or posedge rst)
1147
     if (rst)
1148
       zq <= 1'b1;
1149
     else
1150
     if (cke)
1151
       zq <= q_next == {length{1'b0}};
1152
    always @ (posedge clk or posedge rst)
1153
    if (rst)
1154
        level1 <= 1'b0;
1155
    else
1156
    if (cke)
1157 29 unneback
    if (clear)
1158
        level1 <= 1'b0;
1159
    else if (q_next == level1_value)
1160 25 unneback
        level1 <= 1'b1;
1161
    else if (qi == level1_value & rew)
1162
        level1 <= 1'b0;
1163
endmodule
1164
//////////////////////////////////////////////////////////////////////
1165
////                                                              ////
1166
////  Versatile counter                                           ////
1167
////                                                              ////
1168
////  Description                                                 ////
1169
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1170
////  counter                                                     ////
1171
////                                                              ////
1172
////  To Do:                                                      ////
1173
////   - add LFSR with more taps                                  ////
1174
////                                                              ////
1175
////  Author(s):                                                  ////
1176
////      - Michael Unneback, unneback@opencores.org              ////
1177
////        ORSoC AB                                              ////
1178
////                                                              ////
1179
//////////////////////////////////////////////////////////////////////
1180
////                                                              ////
1181
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1182
////                                                              ////
1183
//// This source file may be used and distributed without         ////
1184
//// restriction provided that this copyright statement is not    ////
1185
//// removed from the file and that any derivative work contains  ////
1186
//// the original copyright notice and the associated disclaimer. ////
1187
////                                                              ////
1188
//// This source file is free software; you can redistribute it   ////
1189
//// and/or modify it under the terms of the GNU Lesser General   ////
1190
//// Public License as published by the Free Software Foundation; ////
1191
//// either version 2.1 of the License, or (at your option) any   ////
1192
//// later version.                                               ////
1193
////                                                              ////
1194
//// This source is distributed in the hope that it will be       ////
1195
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1196
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1197
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1198
//// details.                                                     ////
1199
////                                                              ////
1200
//// You should have received a copy of the GNU Lesser General    ////
1201
//// Public License along with this source; if not, download it   ////
1202
//// from http://www.opencores.org/lgpl.shtml                     ////
1203
////                                                              ////
1204
//////////////////////////////////////////////////////////////////////
1205 6 unneback
// LFSR counter
1206 18 unneback
module vl_cnt_lfsr_zq ( zq, rst, clk);
1207 6 unneback
   parameter length = 4;
1208
   output reg zq;
1209
   input rst;
1210
   input clk;
1211
   parameter clear_value = 0;
1212
   parameter set_value = 1;
1213
   parameter wrap_value = 8;
1214
   parameter level1_value = 15;
1215
   reg  [length:1] qi;
1216
   reg lfsr_fb;
1217
   wire [length:1] q_next;
1218
   reg [32:1] polynom;
1219
   integer i;
1220
   always @ (qi)
1221
   begin
1222
        case (length)
1223
         2: polynom = 32'b11;                               // 0x3
1224
         3: polynom = 32'b110;                              // 0x6
1225
         4: polynom = 32'b1100;                             // 0xC
1226
         5: polynom = 32'b10100;                            // 0x14
1227
         6: polynom = 32'b110000;                           // 0x30
1228
         7: polynom = 32'b1100000;                          // 0x60
1229
         8: polynom = 32'b10111000;                         // 0xb8
1230
         9: polynom = 32'b100010000;                        // 0x110
1231
        10: polynom = 32'b1001000000;                       // 0x240
1232
        11: polynom = 32'b10100000000;                      // 0x500
1233
        12: polynom = 32'b100000101001;                     // 0x829
1234
        13: polynom = 32'b1000000001100;                    // 0x100C
1235
        14: polynom = 32'b10000000010101;                   // 0x2015
1236
        15: polynom = 32'b110000000000000;                  // 0x6000
1237
        16: polynom = 32'b1101000000001000;                 // 0xD008
1238
        17: polynom = 32'b10010000000000000;                // 0x12000
1239
        18: polynom = 32'b100000010000000000;               // 0x20400
1240
        19: polynom = 32'b1000000000000100011;              // 0x40023
1241 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
1242 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
1243
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1244
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1245
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1246
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1247
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1248
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1249
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1250
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1251
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1252
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1253
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1254
        default: polynom = 32'b0;
1255
        endcase
1256
        lfsr_fb = qi[length];
1257
        for (i=length-1; i>=1; i=i-1) begin
1258
            if (polynom[i])
1259
                lfsr_fb = lfsr_fb  ~^ qi[i];
1260
        end
1261
    end
1262
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1263
   always @ (posedge clk or posedge rst)
1264
     if (rst)
1265
       qi <= {length{1'b0}};
1266
     else
1267
       qi <= q_next;
1268
   always @ (posedge clk or posedge rst)
1269
     if (rst)
1270
       zq <= 1'b1;
1271
     else
1272
       zq <= q_next == {length{1'b0}};
1273
endmodule
1274
//////////////////////////////////////////////////////////////////////
1275
////                                                              ////
1276
////  Versatile counter                                           ////
1277
////                                                              ////
1278
////  Description                                                 ////
1279
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1280
////  counter                                                     ////
1281
////                                                              ////
1282
////  To Do:                                                      ////
1283
////   - add LFSR with more taps                                  ////
1284
////                                                              ////
1285
////  Author(s):                                                  ////
1286
////      - Michael Unneback, unneback@opencores.org              ////
1287
////        ORSoC AB                                              ////
1288
////                                                              ////
1289
//////////////////////////////////////////////////////////////////////
1290
////                                                              ////
1291
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1292
////                                                              ////
1293
//// This source file may be used and distributed without         ////
1294
//// restriction provided that this copyright statement is not    ////
1295
//// removed from the file and that any derivative work contains  ////
1296
//// the original copyright notice and the associated disclaimer. ////
1297
////                                                              ////
1298
//// This source file is free software; you can redistribute it   ////
1299
//// and/or modify it under the terms of the GNU Lesser General   ////
1300
//// Public License as published by the Free Software Foundation; ////
1301
//// either version 2.1 of the License, or (at your option) any   ////
1302
//// later version.                                               ////
1303
////                                                              ////
1304
//// This source is distributed in the hope that it will be       ////
1305
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1306
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1307
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1308
//// details.                                                     ////
1309
////                                                              ////
1310
//// You should have received a copy of the GNU Lesser General    ////
1311
//// Public License along with this source; if not, download it   ////
1312
//// from http://www.opencores.org/lgpl.shtml                     ////
1313
////                                                              ////
1314
//////////////////////////////////////////////////////////////////////
1315
// LFSR counter
1316 18 unneback
module vl_cnt_lfsr_ce_zq ( cke, zq, rst, clk);
1317 6 unneback
   parameter length = 4;
1318
   input cke;
1319
   output reg zq;
1320
   input rst;
1321
   input clk;
1322
   parameter clear_value = 0;
1323
   parameter set_value = 1;
1324
   parameter wrap_value = 8;
1325
   parameter level1_value = 15;
1326
   reg  [length:1] qi;
1327
   reg lfsr_fb;
1328
   wire [length:1] q_next;
1329
   reg [32:1] polynom;
1330
   integer i;
1331
   always @ (qi)
1332
   begin
1333
        case (length)
1334
         2: polynom = 32'b11;                               // 0x3
1335
         3: polynom = 32'b110;                              // 0x6
1336
         4: polynom = 32'b1100;                             // 0xC
1337
         5: polynom = 32'b10100;                            // 0x14
1338
         6: polynom = 32'b110000;                           // 0x30
1339
         7: polynom = 32'b1100000;                          // 0x60
1340
         8: polynom = 32'b10111000;                         // 0xb8
1341
         9: polynom = 32'b100010000;                        // 0x110
1342
        10: polynom = 32'b1001000000;                       // 0x240
1343
        11: polynom = 32'b10100000000;                      // 0x500
1344
        12: polynom = 32'b100000101001;                     // 0x829
1345
        13: polynom = 32'b1000000001100;                    // 0x100C
1346
        14: polynom = 32'b10000000010101;                   // 0x2015
1347
        15: polynom = 32'b110000000000000;                  // 0x6000
1348
        16: polynom = 32'b1101000000001000;                 // 0xD008
1349
        17: polynom = 32'b10010000000000000;                // 0x12000
1350
        18: polynom = 32'b100000010000000000;               // 0x20400
1351
        19: polynom = 32'b1000000000000100011;              // 0x40023
1352 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
1353 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
1354
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1355
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1356
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1357
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1358
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1359
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1360
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1361
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1362
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1363
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1364
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1365
        default: polynom = 32'b0;
1366
        endcase
1367
        lfsr_fb = qi[length];
1368
        for (i=length-1; i>=1; i=i-1) begin
1369
            if (polynom[i])
1370
                lfsr_fb = lfsr_fb  ~^ qi[i];
1371
        end
1372
    end
1373
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1374
   always @ (posedge clk or posedge rst)
1375
     if (rst)
1376
       qi <= {length{1'b0}};
1377
     else
1378
     if (cke)
1379
       qi <= q_next;
1380
   always @ (posedge clk or posedge rst)
1381
     if (rst)
1382
       zq <= 1'b1;
1383
     else
1384
     if (cke)
1385
       zq <= q_next == {length{1'b0}};
1386
endmodule
1387
//////////////////////////////////////////////////////////////////////
1388
////                                                              ////
1389
////  Versatile counter                                           ////
1390
////                                                              ////
1391
////  Description                                                 ////
1392
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1393
////  counter                                                     ////
1394
////                                                              ////
1395
////  To Do:                                                      ////
1396
////   - add LFSR with more taps                                  ////
1397
////                                                              ////
1398
////  Author(s):                                                  ////
1399
////      - Michael Unneback, unneback@opencores.org              ////
1400
////        ORSoC AB                                              ////
1401
////                                                              ////
1402
//////////////////////////////////////////////////////////////////////
1403
////                                                              ////
1404
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1405
////                                                              ////
1406
//// This source file may be used and distributed without         ////
1407
//// restriction provided that this copyright statement is not    ////
1408
//// removed from the file and that any derivative work contains  ////
1409
//// the original copyright notice and the associated disclaimer. ////
1410
////                                                              ////
1411
//// This source file is free software; you can redistribute it   ////
1412
//// and/or modify it under the terms of the GNU Lesser General   ////
1413
//// Public License as published by the Free Software Foundation; ////
1414
//// either version 2.1 of the License, or (at your option) any   ////
1415
//// later version.                                               ////
1416
////                                                              ////
1417
//// This source is distributed in the hope that it will be       ////
1418
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1419
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1420
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1421
//// details.                                                     ////
1422
////                                                              ////
1423
//// You should have received a copy of the GNU Lesser General    ////
1424
//// Public License along with this source; if not, download it   ////
1425
//// from http://www.opencores.org/lgpl.shtml                     ////
1426
////                                                              ////
1427
//////////////////////////////////////////////////////////////////////
1428
// LFSR counter
1429 27 unneback
module vl_cnt_lfsr_ce_q ( cke, q, rst, clk);
1430
   parameter length = 4;
1431
   input cke;
1432
   output [length:1] q;
1433
   input rst;
1434
   input clk;
1435
   parameter clear_value = 0;
1436
   parameter set_value = 1;
1437
   parameter wrap_value = 8;
1438
   parameter level1_value = 15;
1439
   reg  [length:1] qi;
1440
   reg lfsr_fb;
1441
   wire [length:1] q_next;
1442
   reg [32:1] polynom;
1443
   integer i;
1444
   always @ (qi)
1445
   begin
1446
        case (length)
1447
         2: polynom = 32'b11;                               // 0x3
1448
         3: polynom = 32'b110;                              // 0x6
1449
         4: polynom = 32'b1100;                             // 0xC
1450
         5: polynom = 32'b10100;                            // 0x14
1451
         6: polynom = 32'b110000;                           // 0x30
1452
         7: polynom = 32'b1100000;                          // 0x60
1453
         8: polynom = 32'b10111000;                         // 0xb8
1454
         9: polynom = 32'b100010000;                        // 0x110
1455
        10: polynom = 32'b1001000000;                       // 0x240
1456
        11: polynom = 32'b10100000000;                      // 0x500
1457
        12: polynom = 32'b100000101001;                     // 0x829
1458
        13: polynom = 32'b1000000001100;                    // 0x100C
1459
        14: polynom = 32'b10000000010101;                   // 0x2015
1460
        15: polynom = 32'b110000000000000;                  // 0x6000
1461
        16: polynom = 32'b1101000000001000;                 // 0xD008
1462
        17: polynom = 32'b10010000000000000;                // 0x12000
1463
        18: polynom = 32'b100000010000000000;               // 0x20400
1464
        19: polynom = 32'b1000000000000100011;              // 0x40023
1465 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
1466 27 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
1467
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1468
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1469
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1470
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1471
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1472
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1473
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1474
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1475
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1476
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1477
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1478
        default: polynom = 32'b0;
1479
        endcase
1480
        lfsr_fb = qi[length];
1481
        for (i=length-1; i>=1; i=i-1) begin
1482
            if (polynom[i])
1483
                lfsr_fb = lfsr_fb  ~^ qi[i];
1484
        end
1485
    end
1486
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1487
   always @ (posedge clk or posedge rst)
1488
     if (rst)
1489
       qi <= {length{1'b0}};
1490
     else
1491
     if (cke)
1492
       qi <= q_next;
1493
   assign q = qi;
1494
endmodule
1495
//////////////////////////////////////////////////////////////////////
1496
////                                                              ////
1497
////  Versatile counter                                           ////
1498
////                                                              ////
1499
////  Description                                                 ////
1500
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1501
////  counter                                                     ////
1502
////                                                              ////
1503
////  To Do:                                                      ////
1504
////   - add LFSR with more taps                                  ////
1505
////                                                              ////
1506
////  Author(s):                                                  ////
1507
////      - Michael Unneback, unneback@opencores.org              ////
1508
////        ORSoC AB                                              ////
1509
////                                                              ////
1510
//////////////////////////////////////////////////////////////////////
1511
////                                                              ////
1512
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1513
////                                                              ////
1514
//// This source file may be used and distributed without         ////
1515
//// restriction provided that this copyright statement is not    ////
1516
//// removed from the file and that any derivative work contains  ////
1517
//// the original copyright notice and the associated disclaimer. ////
1518
////                                                              ////
1519
//// This source file is free software; you can redistribute it   ////
1520
//// and/or modify it under the terms of the GNU Lesser General   ////
1521
//// Public License as published by the Free Software Foundation; ////
1522
//// either version 2.1 of the License, or (at your option) any   ////
1523
//// later version.                                               ////
1524
////                                                              ////
1525
//// This source is distributed in the hope that it will be       ////
1526
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1527
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1528
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1529
//// details.                                                     ////
1530
////                                                              ////
1531
//// You should have received a copy of the GNU Lesser General    ////
1532
//// Public License along with this source; if not, download it   ////
1533
//// from http://www.opencores.org/lgpl.shtml                     ////
1534
////                                                              ////
1535
//////////////////////////////////////////////////////////////////////
1536
// LFSR counter
1537
module vl_cnt_lfsr_ce_clear_q ( clear, cke, q, rst, clk);
1538
   parameter length = 4;
1539
   input clear;
1540
   input cke;
1541
   output [length:1] q;
1542
   input rst;
1543
   input clk;
1544
   parameter clear_value = 0;
1545
   parameter set_value = 1;
1546
   parameter wrap_value = 8;
1547
   parameter level1_value = 15;
1548
   reg  [length:1] qi;
1549
   reg lfsr_fb;
1550
   wire [length:1] q_next;
1551
   reg [32:1] polynom;
1552
   integer i;
1553
   always @ (qi)
1554
   begin
1555
        case (length)
1556
         2: polynom = 32'b11;                               // 0x3
1557
         3: polynom = 32'b110;                              // 0x6
1558
         4: polynom = 32'b1100;                             // 0xC
1559
         5: polynom = 32'b10100;                            // 0x14
1560
         6: polynom = 32'b110000;                           // 0x30
1561
         7: polynom = 32'b1100000;                          // 0x60
1562
         8: polynom = 32'b10111000;                         // 0xb8
1563
         9: polynom = 32'b100010000;                        // 0x110
1564
        10: polynom = 32'b1001000000;                       // 0x240
1565
        11: polynom = 32'b10100000000;                      // 0x500
1566
        12: polynom = 32'b100000101001;                     // 0x829
1567
        13: polynom = 32'b1000000001100;                    // 0x100C
1568
        14: polynom = 32'b10000000010101;                   // 0x2015
1569
        15: polynom = 32'b110000000000000;                  // 0x6000
1570
        16: polynom = 32'b1101000000001000;                 // 0xD008
1571
        17: polynom = 32'b10010000000000000;                // 0x12000
1572
        18: polynom = 32'b100000010000000000;               // 0x20400
1573
        19: polynom = 32'b1000000000000100011;              // 0x40023
1574 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
1575 27 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
1576
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1577
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1578
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1579
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1580
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1581
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1582
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1583
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1584
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1585
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1586
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1587
        default: polynom = 32'b0;
1588
        endcase
1589
        lfsr_fb = qi[length];
1590
        for (i=length-1; i>=1; i=i-1) begin
1591
            if (polynom[i])
1592
                lfsr_fb = lfsr_fb  ~^ qi[i];
1593
        end
1594
    end
1595
   assign q_next =  clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1596
   always @ (posedge clk or posedge rst)
1597
     if (rst)
1598
       qi <= {length{1'b0}};
1599
     else
1600
     if (cke)
1601
       qi <= q_next;
1602
   assign q = qi;
1603
endmodule
1604
//////////////////////////////////////////////////////////////////////
1605
////                                                              ////
1606
////  Versatile counter                                           ////
1607
////                                                              ////
1608
////  Description                                                 ////
1609
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1610
////  counter                                                     ////
1611
////                                                              ////
1612
////  To Do:                                                      ////
1613
////   - add LFSR with more taps                                  ////
1614
////                                                              ////
1615
////  Author(s):                                                  ////
1616
////      - Michael Unneback, unneback@opencores.org              ////
1617
////        ORSoC AB                                              ////
1618
////                                                              ////
1619
//////////////////////////////////////////////////////////////////////
1620
////                                                              ////
1621
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1622
////                                                              ////
1623
//// This source file may be used and distributed without         ////
1624
//// restriction provided that this copyright statement is not    ////
1625
//// removed from the file and that any derivative work contains  ////
1626
//// the original copyright notice and the associated disclaimer. ////
1627
////                                                              ////
1628
//// This source file is free software; you can redistribute it   ////
1629
//// and/or modify it under the terms of the GNU Lesser General   ////
1630
//// Public License as published by the Free Software Foundation; ////
1631
//// either version 2.1 of the License, or (at your option) any   ////
1632
//// later version.                                               ////
1633
////                                                              ////
1634
//// This source is distributed in the hope that it will be       ////
1635
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1636
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1637
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1638
//// details.                                                     ////
1639
////                                                              ////
1640
//// You should have received a copy of the GNU Lesser General    ////
1641
//// Public License along with this source; if not, download it   ////
1642
//// from http://www.opencores.org/lgpl.shtml                     ////
1643
////                                                              ////
1644
//////////////////////////////////////////////////////////////////////
1645
// LFSR counter
1646 22 unneback
module vl_cnt_lfsr_ce_q_zq ( cke, q, zq, rst, clk);
1647
   parameter length = 4;
1648
   input cke;
1649
   output [length:1] q;
1650
   output reg zq;
1651
   input rst;
1652
   input clk;
1653
   parameter clear_value = 0;
1654
   parameter set_value = 1;
1655
   parameter wrap_value = 8;
1656
   parameter level1_value = 15;
1657
   reg  [length:1] qi;
1658
   reg lfsr_fb;
1659
   wire [length:1] q_next;
1660
   reg [32:1] polynom;
1661
   integer i;
1662
   always @ (qi)
1663
   begin
1664
        case (length)
1665
         2: polynom = 32'b11;                               // 0x3
1666
         3: polynom = 32'b110;                              // 0x6
1667
         4: polynom = 32'b1100;                             // 0xC
1668
         5: polynom = 32'b10100;                            // 0x14
1669
         6: polynom = 32'b110000;                           // 0x30
1670
         7: polynom = 32'b1100000;                          // 0x60
1671
         8: polynom = 32'b10111000;                         // 0xb8
1672
         9: polynom = 32'b100010000;                        // 0x110
1673
        10: polynom = 32'b1001000000;                       // 0x240
1674
        11: polynom = 32'b10100000000;                      // 0x500
1675
        12: polynom = 32'b100000101001;                     // 0x829
1676
        13: polynom = 32'b1000000001100;                    // 0x100C
1677
        14: polynom = 32'b10000000010101;                   // 0x2015
1678
        15: polynom = 32'b110000000000000;                  // 0x6000
1679
        16: polynom = 32'b1101000000001000;                 // 0xD008
1680
        17: polynom = 32'b10010000000000000;                // 0x12000
1681
        18: polynom = 32'b100000010000000000;               // 0x20400
1682
        19: polynom = 32'b1000000000000100011;              // 0x40023
1683 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
1684 22 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
1685
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1686
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1687
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1688
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1689
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1690
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1691
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1692
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1693
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1694
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1695
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1696
        default: polynom = 32'b0;
1697
        endcase
1698
        lfsr_fb = qi[length];
1699
        for (i=length-1; i>=1; i=i-1) begin
1700
            if (polynom[i])
1701
                lfsr_fb = lfsr_fb  ~^ qi[i];
1702
        end
1703
    end
1704
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1705
   always @ (posedge clk or posedge rst)
1706
     if (rst)
1707
       qi <= {length{1'b0}};
1708
     else
1709
     if (cke)
1710
       qi <= q_next;
1711
   assign q = qi;
1712
   always @ (posedge clk or posedge rst)
1713
     if (rst)
1714
       zq <= 1'b1;
1715
     else
1716
     if (cke)
1717
       zq <= q_next == {length{1'b0}};
1718
endmodule
1719
//////////////////////////////////////////////////////////////////////
1720
////                                                              ////
1721
////  Versatile counter                                           ////
1722
////                                                              ////
1723
////  Description                                                 ////
1724
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1725
////  counter                                                     ////
1726
////                                                              ////
1727
////  To Do:                                                      ////
1728
////   - add LFSR with more taps                                  ////
1729
////                                                              ////
1730
////  Author(s):                                                  ////
1731
////      - Michael Unneback, unneback@opencores.org              ////
1732
////        ORSoC AB                                              ////
1733
////                                                              ////
1734
//////////////////////////////////////////////////////////////////////
1735
////                                                              ////
1736
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1737
////                                                              ////
1738
//// This source file may be used and distributed without         ////
1739
//// restriction provided that this copyright statement is not    ////
1740
//// removed from the file and that any derivative work contains  ////
1741
//// the original copyright notice and the associated disclaimer. ////
1742
////                                                              ////
1743
//// This source file is free software; you can redistribute it   ////
1744
//// and/or modify it under the terms of the GNU Lesser General   ////
1745
//// Public License as published by the Free Software Foundation; ////
1746
//// either version 2.1 of the License, or (at your option) any   ////
1747
//// later version.                                               ////
1748
////                                                              ////
1749
//// This source is distributed in the hope that it will be       ////
1750
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1751
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1752
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1753
//// details.                                                     ////
1754
////                                                              ////
1755
//// You should have received a copy of the GNU Lesser General    ////
1756
//// Public License along with this source; if not, download it   ////
1757
//// from http://www.opencores.org/lgpl.shtml                     ////
1758
////                                                              ////
1759
//////////////////////////////////////////////////////////////////////
1760
// LFSR counter
1761 18 unneback
module vl_cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk);
1762 6 unneback
   parameter length = 4;
1763
   input cke;
1764
   input rew;
1765
   output reg level1;
1766
   input rst;
1767
   input clk;
1768
   parameter clear_value = 0;
1769
   parameter set_value = 1;
1770
   parameter wrap_value = 8;
1771
   parameter level1_value = 15;
1772 29 unneback
   wire clear;
1773 30 unneback
   assign clear = 1'b0;
1774 6 unneback
   reg  [length:1] qi;
1775
   reg lfsr_fb, lfsr_fb_rew;
1776
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1777
   reg [32:1] polynom_rew;
1778
   integer j;
1779
   reg [32:1] polynom;
1780
   integer i;
1781
   always @ (qi)
1782
   begin
1783
        case (length)
1784
         2: polynom = 32'b11;                               // 0x3
1785
         3: polynom = 32'b110;                              // 0x6
1786
         4: polynom = 32'b1100;                             // 0xC
1787
         5: polynom = 32'b10100;                            // 0x14
1788
         6: polynom = 32'b110000;                           // 0x30
1789
         7: polynom = 32'b1100000;                          // 0x60
1790
         8: polynom = 32'b10111000;                         // 0xb8
1791
         9: polynom = 32'b100010000;                        // 0x110
1792
        10: polynom = 32'b1001000000;                       // 0x240
1793
        11: polynom = 32'b10100000000;                      // 0x500
1794
        12: polynom = 32'b100000101001;                     // 0x829
1795
        13: polynom = 32'b1000000001100;                    // 0x100C
1796
        14: polynom = 32'b10000000010101;                   // 0x2015
1797
        15: polynom = 32'b110000000000000;                  // 0x6000
1798
        16: polynom = 32'b1101000000001000;                 // 0xD008
1799
        17: polynom = 32'b10010000000000000;                // 0x12000
1800
        18: polynom = 32'b100000010000000000;               // 0x20400
1801
        19: polynom = 32'b1000000000000100011;              // 0x40023
1802 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
1803 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
1804
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1805
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1806
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1807
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1808
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1809
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1810
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1811
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1812
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1813
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1814
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1815
        default: polynom = 32'b0;
1816
        endcase
1817
        lfsr_fb = qi[length];
1818
        for (i=length-1; i>=1; i=i-1) begin
1819
            if (polynom[i])
1820
                lfsr_fb = lfsr_fb  ~^ qi[i];
1821
        end
1822
    end
1823
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1824
   always @ (qi)
1825
   begin
1826
        case (length)
1827
         2: polynom_rew = 32'b11;
1828
         3: polynom_rew = 32'b110;
1829
         4: polynom_rew = 32'b1100;
1830
         5: polynom_rew = 32'b10100;
1831
         6: polynom_rew = 32'b110000;
1832
         7: polynom_rew = 32'b1100000;
1833
         8: polynom_rew = 32'b10111000;
1834
         9: polynom_rew = 32'b100010000;
1835
        10: polynom_rew = 32'b1001000000;
1836
        11: polynom_rew = 32'b10100000000;
1837
        12: polynom_rew = 32'b100000101001;
1838
        13: polynom_rew = 32'b1000000001100;
1839
        14: polynom_rew = 32'b10000000010101;
1840
        15: polynom_rew = 32'b110000000000000;
1841
        16: polynom_rew = 32'b1101000000001000;
1842
        17: polynom_rew = 32'b10010000000000000;
1843
        18: polynom_rew = 32'b100000010000000000;
1844
        19: polynom_rew = 32'b1000000000000100011;
1845
        20: polynom_rew = 32'b10000010000000000000;
1846
        21: polynom_rew = 32'b101000000000000000000;
1847
        22: polynom_rew = 32'b1100000000000000000000;
1848
        23: polynom_rew = 32'b10000100000000000000000;
1849
        24: polynom_rew = 32'b111000010000000000000000;
1850
        25: polynom_rew = 32'b1001000000000000000000000;
1851
        26: polynom_rew = 32'b10000000000000000000100011;
1852
        27: polynom_rew = 32'b100000000000000000000010011;
1853
        28: polynom_rew = 32'b1100100000000000000000000000;
1854
        29: polynom_rew = 32'b10100000000000000000000000000;
1855
        30: polynom_rew = 32'b100000000000000000000000101001;
1856
        31: polynom_rew = 32'b1001000000000000000000000000000;
1857
        32: polynom_rew = 32'b10000000001000000000000000000011;
1858
        default: polynom_rew = 32'b0;
1859
        endcase
1860
        // rotate left
1861
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
1862
        lfsr_fb_rew = qi[length];
1863
        for (i=length-1; i>=1; i=i-1) begin
1864
            if (polynom_rew[i])
1865
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
1866
        end
1867
    end
1868
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
1869
   assign q_next = rew ? q_next_rew : q_next_fw;
1870
   always @ (posedge clk or posedge rst)
1871
     if (rst)
1872
       qi <= {length{1'b0}};
1873
     else
1874
     if (cke)
1875
       qi <= q_next;
1876
    always @ (posedge clk or posedge rst)
1877
    if (rst)
1878
        level1 <= 1'b0;
1879
    else
1880
    if (cke)
1881 29 unneback
    if (clear)
1882
        level1 <= 1'b0;
1883
    else if (q_next == level1_value)
1884 6 unneback
        level1 <= 1'b1;
1885
    else if (qi == level1_value & rew)
1886
        level1 <= 1'b0;
1887
endmodule
1888
//////////////////////////////////////////////////////////////////////
1889
////                                                              ////
1890
////  Versatile counter                                           ////
1891
////                                                              ////
1892
////  Description                                                 ////
1893
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1894
////  counter                                                     ////
1895
////                                                              ////
1896
////  To Do:                                                      ////
1897
////   - add LFSR with more taps                                  ////
1898
////                                                              ////
1899
////  Author(s):                                                  ////
1900
////      - Michael Unneback, unneback@opencores.org              ////
1901
////        ORSoC AB                                              ////
1902
////                                                              ////
1903
//////////////////////////////////////////////////////////////////////
1904
////                                                              ////
1905
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1906
////                                                              ////
1907
//// This source file may be used and distributed without         ////
1908
//// restriction provided that this copyright statement is not    ////
1909
//// removed from the file and that any derivative work contains  ////
1910
//// the original copyright notice and the associated disclaimer. ////
1911
////                                                              ////
1912
//// This source file is free software; you can redistribute it   ////
1913
//// and/or modify it under the terms of the GNU Lesser General   ////
1914
//// Public License as published by the Free Software Foundation; ////
1915
//// either version 2.1 of the License, or (at your option) any   ////
1916
//// later version.                                               ////
1917
////                                                              ////
1918
//// This source is distributed in the hope that it will be       ////
1919
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1920
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1921
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1922
//// details.                                                     ////
1923
////                                                              ////
1924
//// You should have received a copy of the GNU Lesser General    ////
1925
//// Public License along with this source; if not, download it   ////
1926
//// from http://www.opencores.org/lgpl.shtml                     ////
1927
////                                                              ////
1928
//////////////////////////////////////////////////////////////////////
1929
// GRAY counter
1930 18 unneback
module vl_cnt_gray ( q, rst, clk);
1931 6 unneback
   parameter length = 4;
1932
   output reg [length:1] q;
1933
   input rst;
1934
   input clk;
1935
   parameter clear_value = 0;
1936
   parameter set_value = 1;
1937
   parameter wrap_value = 8;
1938
   parameter level1_value = 15;
1939
   reg  [length:1] qi;
1940
   wire [length:1] q_next;
1941
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1942
   always @ (posedge clk or posedge rst)
1943
     if (rst)
1944
       qi <= {length{1'b0}};
1945
     else
1946
       qi <= q_next;
1947
   always @ (posedge clk or posedge rst)
1948
     if (rst)
1949
       q <= {length{1'b0}};
1950
     else
1951
         q <= (q_next>>1) ^ q_next;
1952
endmodule
1953
//////////////////////////////////////////////////////////////////////
1954
////                                                              ////
1955
////  Versatile counter                                           ////
1956
////                                                              ////
1957
////  Description                                                 ////
1958
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1959
////  counter                                                     ////
1960
////                                                              ////
1961
////  To Do:                                                      ////
1962
////   - add LFSR with more taps                                  ////
1963
////                                                              ////
1964
////  Author(s):                                                  ////
1965
////      - Michael Unneback, unneback@opencores.org              ////
1966
////        ORSoC AB                                              ////
1967
////                                                              ////
1968
//////////////////////////////////////////////////////////////////////
1969
////                                                              ////
1970
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1971
////                                                              ////
1972
//// This source file may be used and distributed without         ////
1973
//// restriction provided that this copyright statement is not    ////
1974
//// removed from the file and that any derivative work contains  ////
1975
//// the original copyright notice and the associated disclaimer. ////
1976
////                                                              ////
1977
//// This source file is free software; you can redistribute it   ////
1978
//// and/or modify it under the terms of the GNU Lesser General   ////
1979
//// Public License as published by the Free Software Foundation; ////
1980
//// either version 2.1 of the License, or (at your option) any   ////
1981
//// later version.                                               ////
1982
////                                                              ////
1983
//// This source is distributed in the hope that it will be       ////
1984
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1985
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1986
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1987
//// details.                                                     ////
1988
////                                                              ////
1989
//// You should have received a copy of the GNU Lesser General    ////
1990
//// Public License along with this source; if not, download it   ////
1991
//// from http://www.opencores.org/lgpl.shtml                     ////
1992
////                                                              ////
1993
//////////////////////////////////////////////////////////////////////
1994
// GRAY counter
1995 18 unneback
module vl_cnt_gray_ce ( cke, q, rst, clk);
1996 6 unneback
   parameter length = 4;
1997
   input cke;
1998
   output reg [length:1] q;
1999
   input rst;
2000
   input clk;
2001
   parameter clear_value = 0;
2002
   parameter set_value = 1;
2003
   parameter wrap_value = 8;
2004
   parameter level1_value = 15;
2005
   reg  [length:1] qi;
2006
   wire [length:1] q_next;
2007
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2008
   always @ (posedge clk or posedge rst)
2009
     if (rst)
2010
       qi <= {length{1'b0}};
2011
     else
2012
     if (cke)
2013
       qi <= q_next;
2014
   always @ (posedge clk or posedge rst)
2015
     if (rst)
2016
       q <= {length{1'b0}};
2017
     else
2018
       if (cke)
2019
         q <= (q_next>>1) ^ q_next;
2020
endmodule
2021
//////////////////////////////////////////////////////////////////////
2022
////                                                              ////
2023
////  Versatile counter                                           ////
2024
////                                                              ////
2025
////  Description                                                 ////
2026
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2027
////  counter                                                     ////
2028
////                                                              ////
2029
////  To Do:                                                      ////
2030
////   - add LFSR with more taps                                  ////
2031
////                                                              ////
2032
////  Author(s):                                                  ////
2033
////      - Michael Unneback, unneback@opencores.org              ////
2034
////        ORSoC AB                                              ////
2035
////                                                              ////
2036
//////////////////////////////////////////////////////////////////////
2037
////                                                              ////
2038
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2039
////                                                              ////
2040
//// This source file may be used and distributed without         ////
2041
//// restriction provided that this copyright statement is not    ////
2042
//// removed from the file and that any derivative work contains  ////
2043
//// the original copyright notice and the associated disclaimer. ////
2044
////                                                              ////
2045
//// This source file is free software; you can redistribute it   ////
2046
//// and/or modify it under the terms of the GNU Lesser General   ////
2047
//// Public License as published by the Free Software Foundation; ////
2048
//// either version 2.1 of the License, or (at your option) any   ////
2049
//// later version.                                               ////
2050
////                                                              ////
2051
//// This source is distributed in the hope that it will be       ////
2052
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2053
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2054
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2055
//// details.                                                     ////
2056
////                                                              ////
2057
//// You should have received a copy of the GNU Lesser General    ////
2058
//// Public License along with this source; if not, download it   ////
2059
//// from http://www.opencores.org/lgpl.shtml                     ////
2060
////                                                              ////
2061
//////////////////////////////////////////////////////////////////////
2062
// GRAY counter
2063 18 unneback
module vl_cnt_gray_ce_bin ( cke, q, q_bin, rst, clk);
2064 6 unneback
   parameter length = 4;
2065
   input cke;
2066
   output reg [length:1] q;
2067
   output [length:1] q_bin;
2068
   input rst;
2069
   input clk;
2070
   parameter clear_value = 0;
2071
   parameter set_value = 1;
2072
   parameter wrap_value = 8;
2073
   parameter level1_value = 15;
2074
   reg  [length:1] qi;
2075
   wire [length:1] q_next;
2076
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2077
   always @ (posedge clk or posedge rst)
2078
     if (rst)
2079
       qi <= {length{1'b0}};
2080
     else
2081
     if (cke)
2082
       qi <= q_next;
2083
   always @ (posedge clk or posedge rst)
2084
     if (rst)
2085
       q <= {length{1'b0}};
2086
     else
2087
       if (cke)
2088
         q <= (q_next>>1) ^ q_next;
2089
   assign q_bin = qi;
2090
endmodule
2091
//////////////////////////////////////////////////////////////////////
2092
////                                                              ////
2093
////  Versatile library, counters                                 ////
2094
////                                                              ////
2095
////  Description                                                 ////
2096
////  counters                                                    ////
2097
////                                                              ////
2098
////                                                              ////
2099
////  To Do:                                                      ////
2100
////   - add more counters                                        ////
2101
////                                                              ////
2102
////  Author(s):                                                  ////
2103
////      - Michael Unneback, unneback@opencores.org              ////
2104
////        ORSoC AB                                              ////
2105
////                                                              ////
2106
//////////////////////////////////////////////////////////////////////
2107
////                                                              ////
2108
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2109
////                                                              ////
2110
//// This source file may be used and distributed without         ////
2111
//// restriction provided that this copyright statement is not    ////
2112
//// removed from the file and that any derivative work contains  ////
2113
//// the original copyright notice and the associated disclaimer. ////
2114
////                                                              ////
2115
//// This source file is free software; you can redistribute it   ////
2116
//// and/or modify it under the terms of the GNU Lesser General   ////
2117
//// Public License as published by the Free Software Foundation; ////
2118
//// either version 2.1 of the License, or (at your option) any   ////
2119
//// later version.                                               ////
2120
////                                                              ////
2121
//// This source is distributed in the hope that it will be       ////
2122
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2123
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2124
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2125
//// details.                                                     ////
2126
////                                                              ////
2127
//// You should have received a copy of the GNU Lesser General    ////
2128
//// Public License along with this source; if not, download it   ////
2129
//// from http://www.opencores.org/lgpl.shtml                     ////
2130
////                                                              ////
2131
//////////////////////////////////////////////////////////////////////
2132 18 unneback
module vl_cnt_shreg_wrap ( q, rst, clk);
2133 6 unneback
   parameter length = 4;
2134
   output reg [0:length-1] q;
2135
   input rst;
2136
   input clk;
2137
    always @ (posedge clk or posedge rst)
2138
    if (rst)
2139
        q <= {1'b1,{length-1{1'b0}}};
2140
    else
2141
        q <= {q[length-1],q[0:length-2]};
2142
endmodule
2143 18 unneback
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
2144 6 unneback
   parameter length = 4;
2145
   input cke;
2146
   output reg [0:length-1] q;
2147
   input rst;
2148
   input clk;
2149
    always @ (posedge clk or posedge rst)
2150
    if (rst)
2151
        q <= {1'b1,{length-1{1'b0}}};
2152
    else
2153
        if (cke)
2154
            q <= {q[length-1],q[0:length-2]};
2155
endmodule
2156 18 unneback
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
2157 6 unneback
   parameter length = 4;
2158
   input cke, clear;
2159
   output reg [0:length-1] q;
2160
   input rst;
2161
   input clk;
2162
    always @ (posedge clk or posedge rst)
2163
    if (rst)
2164
        q <= {1'b1,{length-1{1'b0}}};
2165
    else
2166
        if (cke)
2167
            if (clear)
2168
                q <= {1'b1,{length-1{1'b0}}};
2169
            else
2170
                q <= q >> 1;
2171
endmodule
2172 18 unneback
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
2173 6 unneback
   parameter length = 4;
2174
   input cke, clear;
2175
   output reg [0:length-1] q;
2176
   input rst;
2177
   input clk;
2178
    always @ (posedge clk or posedge rst)
2179
    if (rst)
2180
        q <= {1'b1,{length-1{1'b0}}};
2181
    else
2182
        if (cke)
2183
            if (clear)
2184
                q <= {1'b1,{length-1{1'b0}}};
2185
            else
2186
            q <= {q[length-1],q[0:length-2]};
2187
endmodule
2188
//////////////////////////////////////////////////////////////////////
2189
////                                                              ////
2190
////  Versatile library, memories                                 ////
2191
////                                                              ////
2192
////  Description                                                 ////
2193
////  memories                                                    ////
2194
////                                                              ////
2195
////                                                              ////
2196
////  To Do:                                                      ////
2197
////   - add more memory types                                    ////
2198
////                                                              ////
2199
////  Author(s):                                                  ////
2200
////      - Michael Unneback, unneback@opencores.org              ////
2201
////        ORSoC AB                                              ////
2202
////                                                              ////
2203
//////////////////////////////////////////////////////////////////////
2204
////                                                              ////
2205
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2206
////                                                              ////
2207
//// This source file may be used and distributed without         ////
2208
//// restriction provided that this copyright statement is not    ////
2209
//// removed from the file and that any derivative work contains  ////
2210
//// the original copyright notice and the associated disclaimer. ////
2211
////                                                              ////
2212
//// This source file is free software; you can redistribute it   ////
2213
//// and/or modify it under the terms of the GNU Lesser General   ////
2214
//// Public License as published by the Free Software Foundation; ////
2215
//// either version 2.1 of the License, or (at your option) any   ////
2216
//// later version.                                               ////
2217
////                                                              ////
2218
//// This source is distributed in the hope that it will be       ////
2219
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2220
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2221
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2222
//// details.                                                     ////
2223
////                                                              ////
2224
//// You should have received a copy of the GNU Lesser General    ////
2225
//// Public License along with this source; if not, download it   ////
2226
//// from http://www.opencores.org/lgpl.shtml                     ////
2227
////                                                              ////
2228
//////////////////////////////////////////////////////////////////////
2229
/// ROM
2230 7 unneback
module vl_rom_init ( adr, q, clk);
2231
   parameter data_width = 32;
2232
   parameter addr_width = 8;
2233
   input [(addr_width-1):0]       adr;
2234
   output reg [(data_width-1):0] q;
2235
   input                         clk;
2236
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
2237
   parameter memory_file = "vl_rom.vmem";
2238
   initial
2239
     begin
2240
        $readmemh(memory_file, rom);
2241
     end
2242
   always @ (posedge clk)
2243
     q <= rom[adr];
2244
endmodule
2245 14 unneback
/*
2246 7 unneback
module vl_rom ( adr, q, clk);
2247 6 unneback
parameter data_width = 32;
2248
parameter addr_width = 4;
2249
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
2250
    {32'h18000000},
2251
    {32'hA8200000},
2252
    {32'hA8200000},
2253
    {32'hA8200000},
2254
    {32'h44003000},
2255
    {32'h15000000},
2256
    {32'h15000000},
2257
    {32'h15000000},
2258
    {32'h15000000},
2259
    {32'h15000000},
2260
    {32'h15000000},
2261
    {32'h15000000},
2262
    {32'h15000000},
2263
    {32'h15000000},
2264
    {32'h15000000},
2265
    {32'h15000000}};
2266 7 unneback
input [addr_width-1:0] adr;
2267 6 unneback
output reg [data_width-1:0] q;
2268
input clk;
2269
always @ (posedge clk)
2270 7 unneback
    q <= data[adr];
2271 6 unneback
endmodule
2272 14 unneback
*/
2273 6 unneback
// Single port RAM
2274
module vl_ram ( d, adr, we, q, clk);
2275
   parameter data_width = 32;
2276
   parameter addr_width = 8;
2277
   input [(data_width-1):0]      d;
2278
   input [(addr_width-1):0]       adr;
2279
   input                         we;
2280 7 unneback
   output reg [(data_width-1):0] q;
2281 6 unneback
   input                         clk;
2282
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
2283 7 unneback
   parameter init = 0;
2284
   parameter memory_file = "vl_ram.vmem";
2285
   generate if (init) begin : init_mem
2286
   initial
2287
     begin
2288
        $readmemh(memory_file, ram);
2289
     end
2290
   end
2291
   endgenerate
2292 6 unneback
   always @ (posedge clk)
2293
   begin
2294
   if (we)
2295
     ram[adr] <= d;
2296
   q <= ram[adr];
2297
   end
2298
endmodule
2299 7 unneback
module vl_ram_be ( d, adr, be, we, q, clk);
2300
   parameter data_width = 32;
2301
   parameter addr_width = 8;
2302
   input [(data_width-1):0]      d;
2303
   input [(addr_width-1):0]       adr;
2304
   input [(addr_width/4)-1:0]    be;
2305
   input                         we;
2306
   output reg [(data_width-1):0] q;
2307
   input                         clk;
2308
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
2309
   parameter init = 0;
2310
   parameter memory_file = "vl_ram.vmem";
2311
   generate if (init) begin : init_mem
2312
   initial
2313
     begin
2314
        $readmemh(memory_file, ram);
2315
     end
2316
   end
2317
   endgenerate
2318
   genvar i;
2319
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
2320
      always @ (posedge clk)
2321
      if (we & be[i])
2322
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
2323
   end
2324
   endgenerate
2325
   always @ (posedge clk)
2326
      q <= ram[adr];
2327
endmodule
2328 6 unneback
// Dual port RAM
2329
// ACTEL FPGA should not use logic to handle rw collision
2330 7 unneback
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
2331 6 unneback
   parameter data_width = 32;
2332
   parameter addr_width = 8;
2333
   input [(data_width-1):0]      d_a;
2334
   input [(addr_width-1):0]       adr_a;
2335
   input [(addr_width-1):0]       adr_b;
2336
   input                         we_a;
2337
   output [(data_width-1):0]      q_b;
2338
   input                         clk_a, clk_b;
2339
   reg [(addr_width-1):0]         adr_b_reg;
2340
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
2341 7 unneback
   parameter init = 0;
2342
   parameter memory_file = "vl_ram.vmem";
2343
   generate if (init) begin : init_mem
2344
   initial
2345
     begin
2346
        $readmemh(memory_file, ram);
2347
     end
2348
   end
2349
   endgenerate
2350 6 unneback
   always @ (posedge clk_a)
2351
   if (we_a)
2352
     ram[adr_a] <= d_a;
2353
   always @ (posedge clk_b)
2354
   adr_b_reg <= adr_b;
2355
   assign q_b = ram[adr_b_reg];
2356
endmodule
2357 7 unneback
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
2358 6 unneback
   parameter data_width = 32;
2359
   parameter addr_width = 8;
2360
   input [(data_width-1):0]      d_a;
2361
   input [(addr_width-1):0]       adr_a;
2362
   input [(addr_width-1):0]       adr_b;
2363
   input                         we_a;
2364
   output [(data_width-1):0]      q_b;
2365
   output reg [(data_width-1):0] q_a;
2366
   input                         clk_a, clk_b;
2367
   reg [(data_width-1):0]         q_b;
2368
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
2369 7 unneback
   parameter init = 0;
2370
   parameter memory_file = "vl_ram.vmem";
2371
   generate if (init) begin : init_mem
2372
   initial
2373
     begin
2374
        $readmemh(memory_file, ram);
2375
     end
2376
   end
2377
   endgenerate
2378 6 unneback
   always @ (posedge clk_a)
2379
     begin
2380
        q_a <= ram[adr_a];
2381
        if (we_a)
2382
             ram[adr_a] <= d_a;
2383
     end
2384
   always @ (posedge clk_b)
2385
          q_b <= ram[adr_b];
2386
endmodule
2387 7 unneback
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
2388 6 unneback
   parameter data_width = 32;
2389
   parameter addr_width = 8;
2390
   input [(data_width-1):0]      d_a;
2391
   input [(addr_width-1):0]       adr_a;
2392
   input [(addr_width-1):0]       adr_b;
2393
   input                         we_a;
2394
   output [(data_width-1):0]      q_b;
2395
   input [(data_width-1):0]       d_b;
2396
   output reg [(data_width-1):0] q_a;
2397
   input                         we_b;
2398
   input                         clk_a, clk_b;
2399
   reg [(data_width-1):0]         q_b;
2400
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
2401 7 unneback
   parameter init = 0;
2402
   parameter memory_file = "vl_ram.vmem";
2403
   generate if (init) begin : init_mem
2404
   initial
2405
     begin
2406
        $readmemh(memory_file, ram);
2407
     end
2408
   end
2409
   endgenerate
2410 6 unneback
   always @ (posedge clk_a)
2411
     begin
2412
        q_a <= ram[adr_a];
2413
        if (we_a)
2414
             ram[adr_a] <= d_a;
2415
     end
2416
   always @ (posedge clk_b)
2417
     begin
2418
        q_b <= ram[adr_b];
2419
        if (we_b)
2420
          ram[adr_b] <= d_b;
2421
     end
2422
endmodule
2423
// Content addresable memory, CAM
2424
// FIFO
2425 25 unneback
module vl_fifo_1r1w_fill_level_sync (
2426
    d, wr, fifo_full,
2427
    q, rd, fifo_empty,
2428
    fill_level,
2429
    clk, rst
2430
    );
2431
parameter data_width = 18;
2432
parameter addr_width = 4;
2433
// write side
2434
input  [data_width-1:0] d;
2435
input                   wr;
2436
output                  fifo_full;
2437
// read side
2438
output [data_width-1:0] q;
2439
input                   rd;
2440
output                  fifo_empty;
2441
// common
2442
output [addr_width:0]   fill_level;
2443
input rst, clk;
2444
wire [addr_width:1] wadr, radr;
2445
vl_cnt_bin_ce
2446
    # ( .length(addr_width))
2447
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
2448
vl_cnt_bin_ce
2449
    # (.length(addr_width))
2450
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
2451
vl_dpram_1r1w
2452
    # (.data_width(data_width), .addr_width(addr_width))
2453
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
2454 31 unneback
vl_cnt_bin_ce_rew_q_zq_l1
2455 27 unneback
    # (.length(addr_width+1), .level1_value(1<<addr_width))
2456 25 unneback
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
2457
endmodule
2458 27 unneback
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
2459
// RAM is supposed to be larger than the two FIFOs
2460
// LFSR counters used adr pointers
2461
module vl_fifo_2r2w_sync_simplex (
2462
    // a side
2463
    a_d, a_wr, a_fifo_full,
2464
    a_q, a_rd, a_fifo_empty,
2465
    a_fill_level,
2466
    // b side
2467
    b_d, b_wr, b_fifo_full,
2468
    b_q, b_rd, b_fifo_empty,
2469
    b_fill_level,
2470
    // common
2471
    clk, rst
2472
    );
2473
parameter data_width = 8;
2474
parameter addr_width = 5;
2475
parameter fifo_full_level = (1<<addr_width)-1;
2476
// a side
2477
input  [data_width-1:0] a_d;
2478
input                   a_wr;
2479
output                  a_fifo_full;
2480
output [data_width-1:0] a_q;
2481
input                   a_rd;
2482
output                  a_fifo_empty;
2483
output [addr_width-1:0] a_fill_level;
2484
// b side
2485
input  [data_width-1:0] b_d;
2486
input                   b_wr;
2487
output                  b_fifo_full;
2488
output [data_width-1:0] b_q;
2489
input                   b_rd;
2490
output                  b_fifo_empty;
2491
output [addr_width-1:0] b_fill_level;
2492
input                   clk;
2493
input                   rst;
2494
// adr_gen
2495
wire [addr_width:1] a_wadr, a_radr;
2496
wire [addr_width:1] b_wadr, b_radr;
2497
// dpram
2498
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
2499
vl_cnt_lfsr_ce
2500
    # ( .length(addr_width))
2501
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
2502
vl_cnt_lfsr_ce
2503
    # (.length(addr_width))
2504
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
2505
vl_cnt_lfsr_ce
2506
    # ( .length(addr_width))
2507
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
2508
vl_cnt_lfsr_ce
2509
    # (.length(addr_width))
2510
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
2511
// mux read or write adr to DPRAM
2512
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
2513
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
2514
vl_dpram_2r2w
2515
    # (.data_width(data_width), .addr_width(addr_width+1))
2516
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
2517
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
2518
vl_cnt_bin_ce_rew_zq_l1
2519 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
2520 27 unneback
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
2521
vl_cnt_bin_ce_rew_zq_l1
2522 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
2523 27 unneback
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
2524
endmodule
2525 6 unneback
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
2526 11 unneback
   parameter addr_width = 4;
2527
   parameter N = addr_width-1;
2528 6 unneback
   parameter Q1 = 2'b00;
2529
   parameter Q2 = 2'b01;
2530
   parameter Q3 = 2'b11;
2531
   parameter Q4 = 2'b10;
2532
   parameter going_empty = 1'b0;
2533
   parameter going_full  = 1'b1;
2534
   input [N:0]  wptr, rptr;
2535 14 unneback
   output       fifo_empty;
2536 6 unneback
   output       fifo_full;
2537
   input        wclk, rclk, rst;
2538
   wire direction;
2539
   reg  direction_set, direction_clr;
2540
   wire async_empty, async_full;
2541
   wire fifo_full2;
2542 14 unneback
   wire fifo_empty2;
2543 6 unneback
   // direction_set
2544
   always @ (wptr[N:N-1] or rptr[N:N-1])
2545
     case ({wptr[N:N-1],rptr[N:N-1]})
2546
       {Q1,Q2} : direction_set <= 1'b1;
2547
       {Q2,Q3} : direction_set <= 1'b1;
2548
       {Q3,Q4} : direction_set <= 1'b1;
2549
       {Q4,Q1} : direction_set <= 1'b1;
2550
       default : direction_set <= 1'b0;
2551
     endcase
2552
   // direction_clear
2553
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
2554
     if (rst)
2555
       direction_clr <= 1'b1;
2556
     else
2557
       case ({wptr[N:N-1],rptr[N:N-1]})
2558
         {Q2,Q1} : direction_clr <= 1'b1;
2559
         {Q3,Q2} : direction_clr <= 1'b1;
2560
         {Q4,Q3} : direction_clr <= 1'b1;
2561
         {Q1,Q4} : direction_clr <= 1'b1;
2562
         default : direction_clr <= 1'b0;
2563
       endcase
2564 18 unneback
    vl_dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
2565 6 unneback
   assign async_empty = (wptr == rptr) && (direction==going_empty);
2566
   assign async_full  = (wptr == rptr) && (direction==going_full);
2567 18 unneback
    vl_dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
2568
    vl_dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk)<