OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Blame information for rev 44

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 6 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  Versatile library, clock and reset                          ////
4
////                                                              ////
5
////  Description                                                 ////
6
////  Logic related to clock and reset                            ////
7
////                                                              ////
8
////                                                              ////
9
////  To Do:                                                      ////
10
////   - add more different registers                             ////
11
////                                                              ////
12
////  Author(s):                                                  ////
13
////      - Michael Unneback, unneback@opencores.org              ////
14
////        ORSoC AB                                              ////
15
////                                                              ////
16
//////////////////////////////////////////////////////////////////////
17
////                                                              ////
18
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
19
////                                                              ////
20
//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
36
////                                                              ////
37
//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
// Global buffer
43
// usage:
44
// use to enable global buffers for high fan out signals such as clock and reset
45
`timescale 1 ns/100 ps
46
// Version: 8.4 8.4.0.33
47
module gbuf(GL,CLK);
48
output GL;
49
input  CLK;
50
    wire GND;
51
    GND GND_1_net(.Y(GND));
52
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
53
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
54
endmodule
55
`timescale 1 ns/1 ns
56
module vl_gbuf ( i, o);
57
input i;
58
output o;
59
`ifdef SIM_GBUF
60
assign o=i;
61
`else
62
gbuf gbuf_i0 ( .CLK(i), .GL(o));
63
`endif
64
endmodule
65
 //ACTEL
66
// sync reset
67 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
68 6 unneback
// output active high global reset sync with two DFFs 
69
`timescale 1 ns/100 ps
70
module vl_sync_rst ( rst_n_i, rst_o, clk);
71
input rst_n_i, clk;
72
output rst_o;
73 18 unneback
reg [1:0] tmp;
74 6 unneback
always @ (posedge clk or negedge rst_n_i)
75
if (!rst_n_i)
76 17 unneback
        tmp <= 2'b11;
77 6 unneback
else
78 33 unneback
        tmp <= {1'b0,tmp[1]};
79 17 unneback
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
80 6 unneback
endmodule
81
// vl_pll
82 32 unneback
///////////////////////////////////////////////////////////////////////////////
83 17 unneback
`timescale 1 ps/1 ps
84 6 unneback
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
85
parameter index = 0;
86
parameter number_of_clk = 1;
87 17 unneback
parameter period_time_0 = 20000;
88
parameter period_time_1 = 20000;
89
parameter period_time_2 = 20000;
90
parameter lock_delay = 2000000;
91 6 unneback
input clk_i, rst_n_i;
92
output lock;
93
output reg [0:number_of_clk-1] clk_o;
94
output [0:number_of_clk-1] rst_o;
95
`ifdef SIM_PLL
96
always
97
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
98
generate if (number_of_clk > 1)
99
always
100
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
101
endgenerate
102
generate if (number_of_clk > 2)
103
always
104
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
105
endgenerate
106
genvar i;
107
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
108
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
109
end
110
endgenerate
111
assign #lock_delay lock = rst_n_i;
112
endmodule
113
`else
114
generate if (number_of_clk==1 & index==0) begin
115
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
116
end
117
endgenerate // index==0
118
generate if (number_of_clk==1 & index==1) begin
119
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
120
end
121
endgenerate // index==1
122
generate if (number_of_clk==1 & index==2) begin
123
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
124
end
125
endgenerate // index==2
126
generate if (number_of_clk==1 & index==3) begin
127
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
128
end
129
endgenerate // index==0
130
generate if (number_of_clk==2 & index==0) begin
131
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
132
end
133
endgenerate // index==0
134
generate if (number_of_clk==2 & index==1) begin
135
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
136
end
137
endgenerate // index==1
138
generate if (number_of_clk==2 & index==2) begin
139
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
140
end
141
endgenerate // index==2
142
generate if (number_of_clk==2 & index==3) begin
143
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
144
end
145
endgenerate // index==0
146
generate if (number_of_clk==3 & index==0) begin
147
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
148
end
149
endgenerate // index==0
150
generate if (number_of_clk==3 & index==1) begin
151
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
152
end
153
endgenerate // index==1
154
generate if (number_of_clk==3 & index==2) begin
155
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
156
end
157
endgenerate // index==2
158
generate if (number_of_clk==3 & index==3) begin
159
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
160
end
161
endgenerate // index==0
162
genvar i;
163
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
164 40 unneback
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
165 6 unneback
end
166
endgenerate
167
endmodule
168
`endif
169 32 unneback
///////////////////////////////////////////////////////////////////////////////
170 6 unneback
 //actel
171
//////////////////////////////////////////////////////////////////////
172
////                                                              ////
173
////  Versatile library, registers                                ////
174
////                                                              ////
175
////  Description                                                 ////
176
////  Different type of registers                                 ////
177
////                                                              ////
178
////                                                              ////
179
////  To Do:                                                      ////
180
////   - add more different registers                             ////
181
////                                                              ////
182
////  Author(s):                                                  ////
183
////      - Michael Unneback, unneback@opencores.org              ////
184
////        ORSoC AB                                              ////
185
////                                                              ////
186
//////////////////////////////////////////////////////////////////////
187
////                                                              ////
188
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
189
////                                                              ////
190
//// This source file may be used and distributed without         ////
191
//// restriction provided that this copyright statement is not    ////
192
//// removed from the file and that any derivative work contains  ////
193
//// the original copyright notice and the associated disclaimer. ////
194
////                                                              ////
195
//// This source file is free software; you can redistribute it   ////
196
//// and/or modify it under the terms of the GNU Lesser General   ////
197
//// Public License as published by the Free Software Foundation; ////
198
//// either version 2.1 of the License, or (at your option) any   ////
199
//// later version.                                               ////
200
////                                                              ////
201
//// This source is distributed in the hope that it will be       ////
202
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
203
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
204
//// PURPOSE.  See the GNU Lesser General Public License for more ////
205
//// details.                                                     ////
206
////                                                              ////
207
//// You should have received a copy of the GNU Lesser General    ////
208
//// Public License along with this source; if not, download it   ////
209
//// from http://www.opencores.org/lgpl.shtml                     ////
210
////                                                              ////
211
//////////////////////////////////////////////////////////////////////
212 18 unneback
module vl_dff ( d, q, clk, rst);
213 6 unneback
        parameter width = 1;
214
        parameter reset_value = 0;
215
        input [width-1:0] d;
216
        input clk, rst;
217
        output reg [width-1:0] q;
218
        always @ (posedge clk or posedge rst)
219
        if (rst)
220
                q <= reset_value;
221
        else
222
                q <= d;
223
endmodule
224 18 unneback
module vl_dff_array ( d, q, clk, rst);
225 6 unneback
        parameter width = 1;
226
        parameter depth = 2;
227
        parameter reset_value = 1'b0;
228
        input [width-1:0] d;
229
        input clk, rst;
230
        output [width-1:0] q;
231
        reg  [0:depth-1] q_tmp [width-1:0];
232
        integer i;
233
        always @ (posedge clk or posedge rst)
234
        if (rst) begin
235
            for (i=0;i<depth;i=i+1)
236
                q_tmp[i] <= {width{reset_value}};
237
        end else begin
238
            q_tmp[0] <= d;
239
            for (i=1;i<depth;i=i+1)
240
                q_tmp[i] <= q_tmp[i-1];
241
        end
242
    assign q = q_tmp[depth-1];
243
endmodule
244 18 unneback
module vl_dff_ce ( d, ce, q, clk, rst);
245 6 unneback
        parameter width = 1;
246
        parameter reset_value = 0;
247
        input [width-1:0] d;
248
        input ce, clk, rst;
249
        output reg [width-1:0] q;
250
        always @ (posedge clk or posedge rst)
251
        if (rst)
252
                q <= reset_value;
253
        else
254
                if (ce)
255
                        q <= d;
256
endmodule
257 18 unneback
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
258 8 unneback
        parameter width = 1;
259
        parameter reset_value = 0;
260
        input [width-1:0] d;
261 10 unneback
        input ce, clear, clk, rst;
262 8 unneback
        output reg [width-1:0] q;
263
        always @ (posedge clk or posedge rst)
264
        if (rst)
265
            q <= reset_value;
266
        else
267
            if (ce)
268
                if (clear)
269
                    q <= {width{1'b0}};
270
                else
271
                    q <= d;
272
endmodule
273 24 unneback
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
274
        parameter width = 1;
275
        parameter reset_value = 0;
276
        input [width-1:0] d;
277
        input ce, set, clk, rst;
278
        output reg [width-1:0] q;
279
        always @ (posedge clk or posedge rst)
280
        if (rst)
281
            q <= reset_value;
282
        else
283
            if (ce)
284
                if (set)
285
                    q <= {width{1'b1}};
286
                else
287
                    q <= d;
288
endmodule
289 29 unneback
module vl_spr ( sp, r, q, clk, rst);
290
        parameter width = 1;
291
        parameter reset_value = 0;
292
        input sp, r;
293
        output reg q;
294
        input clk, rst;
295
        always @ (posedge clk or posedge rst)
296
        if (rst)
297
            q <= reset_value;
298
        else
299
            if (sp)
300
                q <= 1'b1;
301
            else if (r)
302
                q <= 1'b0;
303
endmodule
304
module vl_srp ( s, rp, q, clk, rst);
305
        parameter width = 1;
306
        parameter reset_value = 0;
307
        input s, rp;
308
        output reg q;
309
        input clk, rst;
310
        always @ (posedge clk or posedge rst)
311
        if (rst)
312
            q <= reset_value;
313
        else
314
            if (rp)
315
                q <= 1'b0;
316
            else if (s)
317
                q <= 1'b1;
318
endmodule
319 18 unneback
module vl_dff_sr ( aclr, aset, clock, data, q);
320 6 unneback
    input         aclr;
321
    input         aset;
322
    input         clock;
323
    input         data;
324
    output reg    q;
325
   always @ (posedge clock or posedge aclr or posedge aset)
326
     if (aclr)
327
       q <= 1'b0;
328
     else if (aset)
329
       q <= 1'b1;
330
     else
331
       q <= data;
332
endmodule
333
// LATCH
334
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
335 40 unneback
module vl_latch ( d, le, q, clk);
336 6 unneback
input d, le;
337
output q;
338
input clk;/*
339
   always @ (posedge direction_set or posedge direction_clr)
340
     if (direction_clr)
341
       direction <= going_empty;
342
     else
343
       direction <= going_full;*/
344
endmodule
345 18 unneback
module vl_shreg ( d, q, clk, rst);
346 17 unneback
parameter depth = 10;
347
input d;
348
output q;
349
input clk, rst;
350
reg [1:depth] dffs;
351
always @ (posedge clk or posedge rst)
352
if (rst)
353
    dffs <= {depth{1'b0}};
354
else
355
    dffs <= {d,dffs[1:depth-1]};
356
assign q = dffs[depth];
357
endmodule
358 18 unneback
module vl_shreg_ce ( d, ce, q, clk, rst);
359 17 unneback
parameter depth = 10;
360
input d, ce;
361
output q;
362
input clk, rst;
363
reg [1:depth] dffs;
364
always @ (posedge clk or posedge rst)
365
if (rst)
366
    dffs <= {depth{1'b0}};
367
else
368
    if (ce)
369
        dffs <= {d,dffs[1:depth-1]};
370
assign q = dffs[depth];
371
endmodule
372 18 unneback
module vl_delay ( d, q, clk, rst);
373 15 unneback
parameter depth = 10;
374
input d;
375
output q;
376
input clk, rst;
377
reg [1:depth] dffs;
378
always @ (posedge clk or posedge rst)
379
if (rst)
380
    dffs <= {depth{1'b0}};
381
else
382
    dffs <= {d,dffs[1:depth-1]};
383
assign q = dffs[depth];
384
endmodule
385 18 unneback
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
386 17 unneback
parameter depth = 10;
387
input d;
388
output q, emptyflag;
389
input clk, rst;
390
reg [1:depth] dffs;
391
always @ (posedge clk or posedge rst)
392
if (rst)
393
    dffs <= {depth{1'b0}};
394
else
395
    dffs <= {d,dffs[1:depth-1]};
396
assign q = dffs[depth];
397
assign emptyflag = !(|dffs);
398
endmodule
399 6 unneback
//////////////////////////////////////////////////////////////////////
400
////                                                              ////
401 18 unneback
////  Logic functions                                             ////
402
////                                                              ////
403
////  Description                                                 ////
404
////  Logic functions such as multiplexers                        ////
405
////                                                              ////
406
////                                                              ////
407
////  To Do:                                                      ////
408
////   -                                                          ////
409
////                                                              ////
410
////  Author(s):                                                  ////
411
////      - Michael Unneback, unneback@opencores.org              ////
412
////        ORSoC AB                                              ////
413
////                                                              ////
414
//////////////////////////////////////////////////////////////////////
415
////                                                              ////
416
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
417
////                                                              ////
418
//// This source file may be used and distributed without         ////
419
//// restriction provided that this copyright statement is not    ////
420
//// removed from the file and that any derivative work contains  ////
421
//// the original copyright notice and the associated disclaimer. ////
422
////                                                              ////
423
//// This source file is free software; you can redistribute it   ////
424
//// and/or modify it under the terms of the GNU Lesser General   ////
425
//// Public License as published by the Free Software Foundation; ////
426
//// either version 2.1 of the License, or (at your option) any   ////
427
//// later version.                                               ////
428
////                                                              ////
429
//// This source is distributed in the hope that it will be       ////
430
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
431
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
432
//// PURPOSE.  See the GNU Lesser General Public License for more ////
433
//// details.                                                     ////
434
////                                                              ////
435
//// You should have received a copy of the GNU Lesser General    ////
436
//// Public License along with this source; if not, download it   ////
437
//// from http://www.opencores.org/lgpl.shtml                     ////
438
////                                                              ////
439
//////////////////////////////////////////////////////////////////////
440 36 unneback
module vl_mux_andor ( a, sel, dout);
441
parameter width = 32;
442
parameter nr_of_ports = 4;
443
input [nr_of_ports*width-1:0] a;
444
input [nr_of_ports-1:0] sel;
445
output reg [width-1:0] dout;
446 38 unneback
integer i,j;
447 36 unneback
always @ (a, sel)
448
begin
449
    dout = a[width-1:0] & {width{sel[0]}};
450 42 unneback
    for (i=1;i<nr_of_ports;i=i+1)
451
        for (j=0;j<width;j=j+1)
452
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
453 36 unneback
end
454
endmodule
455 34 unneback
module vl_mux2_andor ( a1, a0, sel, dout);
456
parameter width = 32;
457 35 unneback
localparam nr_of_ports = 2;
458 34 unneback
input [width-1:0] a1, a0;
459
input [nr_of_ports-1:0] sel;
460
output [width-1:0] dout;
461 36 unneback
vl_mux_andor
462 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
463 36 unneback
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
464 34 unneback
endmodule
465
module vl_mux3_andor ( a2, a1, a0, sel, dout);
466
parameter width = 32;
467 35 unneback
localparam nr_of_ports = 3;
468 34 unneback
input [width-1:0] a2, a1, a0;
469
input [nr_of_ports-1:0] sel;
470
output [width-1:0] dout;
471 36 unneback
vl_mux_andor
472 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
473 36 unneback
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
474 34 unneback
endmodule
475 18 unneback
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
476
parameter width = 32;
477 35 unneback
localparam nr_of_ports = 4;
478 18 unneback
input [width-1:0] a3, a2, a1, a0;
479
input [nr_of_ports-1:0] sel;
480 22 unneback
output [width-1:0] dout;
481 36 unneback
vl_mux_andor
482 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
483 36 unneback
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
484 18 unneback
endmodule
485
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
486
parameter width = 32;
487 35 unneback
localparam nr_of_ports = 5;
488 18 unneback
input [width-1:0] a4, a3, a2, a1, a0;
489
input [nr_of_ports-1:0] sel;
490 22 unneback
output [width-1:0] dout;
491 36 unneback
vl_mux_andor
492 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
493 36 unneback
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
494 18 unneback
endmodule
495
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
496
parameter width = 32;
497 35 unneback
localparam nr_of_ports = 6;
498 18 unneback
input [width-1:0] a5, a4, a3, a2, a1, a0;
499
input [nr_of_ports-1:0] sel;
500 22 unneback
output [width-1:0] dout;
501 36 unneback
vl_mux_andor
502 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
503 36 unneback
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
504 18 unneback
endmodule
505 43 unneback
module vl_parity_generate (data, parity);
506
parameter word_size = 32;
507
parameter chunk_size = 8;
508
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
509
input [word_size-1:0] data;
510
output reg [word_size/chunk_size-1:0] parity;
511
integer i,j;
512
always @ (data)
513
for (i=0;i<word_size/chunk_size;i=i+1) begin
514
    parity[i] = parity_type;
515
    for (j=0;j<chunk_size;j=j+1) begin
516
        parity[i] = data[i+j] ^ parity[i];
517
    end
518
end
519
endmodule
520
module vl_parity_check( data, parity, parity_error);
521
parameter word_size = 32;
522
parameter chunk_size = 8;
523
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
524
input [word_size-1:0] data;
525
input [word_size/chunk_size-1:0] parity;
526
output parity_error;
527 44 unneback
reg [word_size/chunk_size-1:0] error_flag;
528 43 unneback
integer i,j;
529
always @ (data or parity)
530
for (i=0;i<word_size/chunk_size;i=i+1) begin
531
    error_flag[i] = parity[i] ^ parity_type;
532
    for (j=0;j<chunk_size;j=j+1) begin
533
        error_flag[i] = data[i+j] ^ error_flag[i];
534
    end
535
end
536
assign parity_error = |error_flag;
537
endmodule
538 18 unneback
//////////////////////////////////////////////////////////////////////
539
////                                                              ////
540 44 unneback
////  IO functions                                                ////
541
////                                                              ////
542
////  Description                                                 ////
543
////  IO functions such as IOB flip-flops                         ////
544
////                                                              ////
545
////                                                              ////
546
////  To Do:                                                      ////
547
////   -                                                          ////
548
////                                                              ////
549
////  Author(s):                                                  ////
550
////      - Michael Unneback, unneback@opencores.org              ////
551
////        ORSoC AB                                              ////
552
////                                                              ////
553
//////////////////////////////////////////////////////////////////////
554
////                                                              ////
555
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
556
////                                                              ////
557
//// This source file may be used and distributed without         ////
558
//// restriction provided that this copyright statement is not    ////
559
//// removed from the file and that any derivative work contains  ////
560
//// the original copyright notice and the associated disclaimer. ////
561
////                                                              ////
562
//// This source file is free software; you can redistribute it   ////
563
//// and/or modify it under the terms of the GNU Lesser General   ////
564
//// Public License as published by the Free Software Foundation; ////
565
//// either version 2.1 of the License, or (at your option) any   ////
566
//// later version.                                               ////
567
////                                                              ////
568
//// This source is distributed in the hope that it will be       ////
569
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
570
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
571
//// PURPOSE.  See the GNU Lesser General Public License for more ////
572
//// details.                                                     ////
573
////                                                              ////
574
//// You should have received a copy of the GNU Lesser General    ////
575
//// Public License along with this source; if not, download it   ////
576
//// from http://www.opencores.org/lgpl.shtml                     ////
577
////                                                              ////
578
//////////////////////////////////////////////////////////////////////
579
module vl_o_dff (d_i, o_pad, clk, rst);
580
parameter width = 1;
581
input [width-1:0]  d_i;
582
output [width-1:0] o_pad;
583
input clk, rst;
584
wire [width-1:0] d_i_int /*synthesis syn_keep = 1*/;
585
assign d_i_int = d_i;
586
genvar i;
587
for (i=0;i<width;i=i+1) begin
588
    always @ (posedge clk or posedge rst)
589
    if (rst)
590
        o_pad[i] <= 1'b0;
591
    else
592
        o_pad[i] <= d_i_int[i];
593
end
594
endgenerate
595
endmodule
596
module vl_io_dff_oe ( d_i, d_o, oe, io_pad, clk, rst);
597
parameter width = 1;
598
input  [width-1:0] d_o;
599
output reg [width-1:0] d_i;
600
input oe;
601
inout [width-1:0] io_pad;
602
input clk, rst;
603
wire [width-1:0] oe_d /*synthesis syn_keep = 1*/;
604
reg [width-1:0] oe_q;
605
reg [width-1:0] d_o_q;
606
assign oe_d = {width{oe}};
607
genvar i;
608
generate
609
for (i=0;i<width;i=i+1) begin
610
    always @ (posedge clk or posedge rst)
611
    if (rst)
612
        oe_q[i] <= 1'b0;
613
    else
614
        oe_q[i] <= oe_d[i];
615
    always @ (posedge clk or posedge rst)
616
    if (rst)
617
        d_o_q[i] <= 1'b0;
618
    else
619
        d_o_q[i] <= d_o[i];
620
    always @ (posedge clk or posedge rst)
621
    if (rst)
622
        d_i[i] <= 1'b0;
623
    else
624
        d_i[i] <= io_pad[i];
625
    assign io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
626
end
627
endgenerate
628
endmodule
629
//////////////////////////////////////////////////////////////////////
630
////                                                              ////
631 6 unneback
////  Versatile counter                                           ////
632
////                                                              ////
633
////  Description                                                 ////
634
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
635
////  counter                                                     ////
636
////                                                              ////
637
////  To Do:                                                      ////
638
////   - add LFSR with more taps                                  ////
639
////                                                              ////
640
////  Author(s):                                                  ////
641
////      - Michael Unneback, unneback@opencores.org              ////
642
////        ORSoC AB                                              ////
643
////                                                              ////
644
//////////////////////////////////////////////////////////////////////
645
////                                                              ////
646
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
647
////                                                              ////
648
//// This source file may be used and distributed without         ////
649
//// restriction provided that this copyright statement is not    ////
650
//// removed from the file and that any derivative work contains  ////
651
//// the original copyright notice and the associated disclaimer. ////
652
////                                                              ////
653
//// This source file is free software; you can redistribute it   ////
654
//// and/or modify it under the terms of the GNU Lesser General   ////
655
//// Public License as published by the Free Software Foundation; ////
656
//// either version 2.1 of the License, or (at your option) any   ////
657
//// later version.                                               ////
658
////                                                              ////
659
//// This source is distributed in the hope that it will be       ////
660
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
661
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
662
//// PURPOSE.  See the GNU Lesser General Public License for more ////
663
//// details.                                                     ////
664
////                                                              ////
665
//// You should have received a copy of the GNU Lesser General    ////
666
//// Public License along with this source; if not, download it   ////
667
//// from http://www.opencores.org/lgpl.shtml                     ////
668
////                                                              ////
669
//////////////////////////////////////////////////////////////////////
670
// binary counter
671 40 unneback
module vl_cnt_bin_ce (
672
 cke, q, rst, clk);
673 22 unneback
   parameter length = 4;
674 6 unneback
   input cke;
675
   output [length:1] q;
676
   input rst;
677
   input clk;
678
   parameter clear_value = 0;
679
   parameter set_value = 1;
680
   parameter wrap_value = 0;
681
   parameter level1_value = 15;
682
   reg  [length:1] qi;
683
   wire [length:1] q_next;
684
   assign q_next = qi + {{length-1{1'b0}},1'b1};
685
   always @ (posedge clk or posedge rst)
686
     if (rst)
687
       qi <= {length{1'b0}};
688
     else
689
     if (cke)
690
       qi <= q_next;
691
   assign q = qi;
692
endmodule
693
//////////////////////////////////////////////////////////////////////
694
////                                                              ////
695
////  Versatile counter                                           ////
696
////                                                              ////
697
////  Description                                                 ////
698
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
699
////  counter                                                     ////
700
////                                                              ////
701
////  To Do:                                                      ////
702
////   - add LFSR with more taps                                  ////
703
////                                                              ////
704
////  Author(s):                                                  ////
705
////      - Michael Unneback, unneback@opencores.org              ////
706
////        ORSoC AB                                              ////
707
////                                                              ////
708
//////////////////////////////////////////////////////////////////////
709
////                                                              ////
710
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
711
////                                                              ////
712
//// This source file may be used and distributed without         ////
713
//// restriction provided that this copyright statement is not    ////
714
//// removed from the file and that any derivative work contains  ////
715
//// the original copyright notice and the associated disclaimer. ////
716
////                                                              ////
717
//// This source file is free software; you can redistribute it   ////
718
//// and/or modify it under the terms of the GNU Lesser General   ////
719
//// Public License as published by the Free Software Foundation; ////
720
//// either version 2.1 of the License, or (at your option) any   ////
721
//// later version.                                               ////
722
////                                                              ////
723
//// This source is distributed in the hope that it will be       ////
724
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
725
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
726
//// PURPOSE.  See the GNU Lesser General Public License for more ////
727
//// details.                                                     ////
728
////                                                              ////
729
//// You should have received a copy of the GNU Lesser General    ////
730
//// Public License along with this source; if not, download it   ////
731
//// from http://www.opencores.org/lgpl.shtml                     ////
732
////                                                              ////
733
//////////////////////////////////////////////////////////////////////
734
// binary counter
735 40 unneback
module vl_cnt_bin_ce_rew_zq_l1 (
736
 cke, rew, zq, level1, rst, clk);
737 6 unneback
   parameter length = 4;
738
   input cke;
739
   input rew;
740 25 unneback
   output reg zq;
741
   output reg level1;
742
   input rst;
743
   input clk;
744
   parameter clear_value = 0;
745
   parameter set_value = 1;
746
   parameter wrap_value = 1;
747
   parameter level1_value = 15;
748 29 unneback
   wire clear;
749 30 unneback
   assign clear = 1'b0;
750 25 unneback
   reg  [length:1] qi;
751
   wire  [length:1] q_next, q_next_fw, q_next_rew;
752
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
753
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
754
   assign q_next = rew ? q_next_rew : q_next_fw;
755
   always @ (posedge clk or posedge rst)
756
     if (rst)
757
       qi <= {length{1'b0}};
758
     else
759
     if (cke)
760
       qi <= q_next;
761
   always @ (posedge clk or posedge rst)
762
     if (rst)
763
       zq <= 1'b1;
764
     else
765
     if (cke)
766
       zq <= q_next == {length{1'b0}};
767
    always @ (posedge clk or posedge rst)
768
    if (rst)
769
        level1 <= 1'b0;
770
    else
771
    if (cke)
772 29 unneback
    if (clear)
773
        level1 <= 1'b0;
774
    else if (q_next == level1_value)
775 25 unneback
        level1 <= 1'b1;
776
    else if (qi == level1_value & rew)
777
        level1 <= 1'b0;
778
endmodule
779
//////////////////////////////////////////////////////////////////////
780
////                                                              ////
781
////  Versatile counter                                           ////
782
////                                                              ////
783
////  Description                                                 ////
784
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
785
////  counter                                                     ////
786
////                                                              ////
787
////  To Do:                                                      ////
788
////   - add LFSR with more taps                                  ////
789
////                                                              ////
790
////  Author(s):                                                  ////
791
////      - Michael Unneback, unneback@opencores.org              ////
792
////        ORSoC AB                                              ////
793
////                                                              ////
794
//////////////////////////////////////////////////////////////////////
795
////                                                              ////
796
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
797
////                                                              ////
798
//// This source file may be used and distributed without         ////
799
//// restriction provided that this copyright statement is not    ////
800
//// removed from the file and that any derivative work contains  ////
801
//// the original copyright notice and the associated disclaimer. ////
802
////                                                              ////
803
//// This source file is free software; you can redistribute it   ////
804
//// and/or modify it under the terms of the GNU Lesser General   ////
805
//// Public License as published by the Free Software Foundation; ////
806
//// either version 2.1 of the License, or (at your option) any   ////
807
//// later version.                                               ////
808
////                                                              ////
809
//// This source is distributed in the hope that it will be       ////
810
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
811
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
812
//// PURPOSE.  See the GNU Lesser General Public License for more ////
813
//// details.                                                     ////
814
////                                                              ////
815
//// You should have received a copy of the GNU Lesser General    ////
816
//// Public License along with this source; if not, download it   ////
817
//// from http://www.opencores.org/lgpl.shtml                     ////
818
////                                                              ////
819
//////////////////////////////////////////////////////////////////////
820
// binary counter
821 40 unneback
module vl_cnt_bin_ce_rew_q_zq_l1 (
822
 cke, rew, q, zq, level1, rst, clk);
823 25 unneback
   parameter length = 4;
824
   input cke;
825
   input rew;
826
   output [length:1] q;
827
   output reg zq;
828
   output reg level1;
829
   input rst;
830
   input clk;
831
   parameter clear_value = 0;
832
   parameter set_value = 1;
833
   parameter wrap_value = 1;
834
   parameter level1_value = 15;
835 29 unneback
   wire clear;
836 30 unneback
   assign clear = 1'b0;
837 25 unneback
   reg  [length:1] qi;
838
   wire  [length:1] q_next, q_next_fw, q_next_rew;
839
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
840
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
841
   assign q_next = rew ? q_next_rew : q_next_fw;
842
   always @ (posedge clk or posedge rst)
843
     if (rst)
844
       qi <= {length{1'b0}};
845
     else
846
     if (cke)
847
       qi <= q_next;
848
   assign q = qi;
849
   always @ (posedge clk or posedge rst)
850
     if (rst)
851
       zq <= 1'b1;
852
     else
853
     if (cke)
854
       zq <= q_next == {length{1'b0}};
855
    always @ (posedge clk or posedge rst)
856
    if (rst)
857
        level1 <= 1'b0;
858
    else
859
    if (cke)
860 29 unneback
    if (clear)
861
        level1 <= 1'b0;
862
    else if (q_next == level1_value)
863 25 unneback
        level1 <= 1'b1;
864
    else if (qi == level1_value & rew)
865
        level1 <= 1'b0;
866
endmodule
867
//////////////////////////////////////////////////////////////////////
868
////                                                              ////
869
////  Versatile counter                                           ////
870
////                                                              ////
871
////  Description                                                 ////
872
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
873
////  counter                                                     ////
874
////                                                              ////
875
////  To Do:                                                      ////
876
////   - add LFSR with more taps                                  ////
877
////                                                              ////
878
////  Author(s):                                                  ////
879
////      - Michael Unneback, unneback@opencores.org              ////
880
////        ORSoC AB                                              ////
881
////                                                              ////
882
//////////////////////////////////////////////////////////////////////
883
////                                                              ////
884
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
885
////                                                              ////
886
//// This source file may be used and distributed without         ////
887
//// restriction provided that this copyright statement is not    ////
888
//// removed from the file and that any derivative work contains  ////
889
//// the original copyright notice and the associated disclaimer. ////
890
////                                                              ////
891
//// This source file is free software; you can redistribute it   ////
892
//// and/or modify it under the terms of the GNU Lesser General   ////
893
//// Public License as published by the Free Software Foundation; ////
894
//// either version 2.1 of the License, or (at your option) any   ////
895
//// later version.                                               ////
896
////                                                              ////
897
//// This source is distributed in the hope that it will be       ////
898
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
899
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
900
//// PURPOSE.  See the GNU Lesser General Public License for more ////
901
//// details.                                                     ////
902
////                                                              ////
903
//// You should have received a copy of the GNU Lesser General    ////
904
//// Public License along with this source; if not, download it   ////
905
//// from http://www.opencores.org/lgpl.shtml                     ////
906
////                                                              ////
907
//////////////////////////////////////////////////////////////////////
908 6 unneback
// GRAY counter
909 40 unneback
module vl_cnt_gray_ce_bin (
910
 cke, q, q_bin, rst, clk);
911 6 unneback
   parameter length = 4;
912
   input cke;
913
   output reg [length:1] q;
914
   output [length:1] q_bin;
915
   input rst;
916
   input clk;
917
   parameter clear_value = 0;
918
   parameter set_value = 1;
919
   parameter wrap_value = 8;
920
   parameter level1_value = 15;
921
   reg  [length:1] qi;
922
   wire [length:1] q_next;
923
   assign q_next = qi + {{length-1{1'b0}},1'b1};
924
   always @ (posedge clk or posedge rst)
925
     if (rst)
926
       qi <= {length{1'b0}};
927
     else
928
     if (cke)
929
       qi <= q_next;
930
   always @ (posedge clk or posedge rst)
931
     if (rst)
932
       q <= {length{1'b0}};
933
     else
934
       if (cke)
935
         q <= (q_next>>1) ^ q_next;
936
   assign q_bin = qi;
937
endmodule
938
//////////////////////////////////////////////////////////////////////
939
////                                                              ////
940
////  Versatile library, counters                                 ////
941
////                                                              ////
942
////  Description                                                 ////
943
////  counters                                                    ////
944
////                                                              ////
945
////                                                              ////
946
////  To Do:                                                      ////
947
////   - add more counters                                        ////
948
////                                                              ////
949
////  Author(s):                                                  ////
950
////      - Michael Unneback, unneback@opencores.org              ////
951
////        ORSoC AB                                              ////
952
////                                                              ////
953
//////////////////////////////////////////////////////////////////////
954
////                                                              ////
955
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
956
////                                                              ////
957
//// This source file may be used and distributed without         ////
958
//// restriction provided that this copyright statement is not    ////
959
//// removed from the file and that any derivative work contains  ////
960
//// the original copyright notice and the associated disclaimer. ////
961
////                                                              ////
962
//// This source file is free software; you can redistribute it   ////
963
//// and/or modify it under the terms of the GNU Lesser General   ////
964
//// Public License as published by the Free Software Foundation; ////
965
//// either version 2.1 of the License, or (at your option) any   ////
966
//// later version.                                               ////
967
////                                                              ////
968
//// This source is distributed in the hope that it will be       ////
969
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
970
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
971
//// PURPOSE.  See the GNU Lesser General Public License for more ////
972
//// details.                                                     ////
973
////                                                              ////
974
//// You should have received a copy of the GNU Lesser General    ////
975
//// Public License along with this source; if not, download it   ////
976
//// from http://www.opencores.org/lgpl.shtml                     ////
977
////                                                              ////
978
//////////////////////////////////////////////////////////////////////
979 18 unneback
module vl_cnt_shreg_wrap ( q, rst, clk);
980 6 unneback
   parameter length = 4;
981
   output reg [0:length-1] q;
982
   input rst;
983
   input clk;
984
    always @ (posedge clk or posedge rst)
985
    if (rst)
986
        q <= {1'b1,{length-1{1'b0}}};
987
    else
988
        q <= {q[length-1],q[0:length-2]};
989
endmodule
990 18 unneback
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
991 6 unneback
   parameter length = 4;
992
   input cke;
993
   output reg [0:length-1] q;
994
   input rst;
995
   input clk;
996
    always @ (posedge clk or posedge rst)
997
    if (rst)
998
        q <= {1'b1,{length-1{1'b0}}};
999
    else
1000
        if (cke)
1001
            q <= {q[length-1],q[0:length-2]};
1002
endmodule
1003 18 unneback
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
1004 6 unneback
   parameter length = 4;
1005
   input cke, clear;
1006
   output reg [0:length-1] q;
1007
   input rst;
1008
   input clk;
1009
    always @ (posedge clk or posedge rst)
1010
    if (rst)
1011
        q <= {1'b1,{length-1{1'b0}}};
1012
    else
1013
        if (cke)
1014
            if (clear)
1015
                q <= {1'b1,{length-1{1'b0}}};
1016
            else
1017
                q <= q >> 1;
1018
endmodule
1019 18 unneback
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
1020 6 unneback
   parameter length = 4;
1021
   input cke, clear;
1022
   output reg [0:length-1] q;
1023
   input rst;
1024
   input clk;
1025
    always @ (posedge clk or posedge rst)
1026
    if (rst)
1027
        q <= {1'b1,{length-1{1'b0}}};
1028
    else
1029
        if (cke)
1030
            if (clear)
1031
                q <= {1'b1,{length-1{1'b0}}};
1032
            else
1033
            q <= {q[length-1],q[0:length-2]};
1034
endmodule
1035
//////////////////////////////////////////////////////////////////////
1036
////                                                              ////
1037
////  Versatile library, memories                                 ////
1038
////                                                              ////
1039
////  Description                                                 ////
1040
////  memories                                                    ////
1041
////                                                              ////
1042
////                                                              ////
1043
////  To Do:                                                      ////
1044
////   - add more memory types                                    ////
1045
////                                                              ////
1046
////  Author(s):                                                  ////
1047
////      - Michael Unneback, unneback@opencores.org              ////
1048
////        ORSoC AB                                              ////
1049
////                                                              ////
1050
//////////////////////////////////////////////////////////////////////
1051
////                                                              ////
1052
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1053
////                                                              ////
1054
//// This source file may be used and distributed without         ////
1055
//// restriction provided that this copyright statement is not    ////
1056
//// removed from the file and that any derivative work contains  ////
1057
//// the original copyright notice and the associated disclaimer. ////
1058
////                                                              ////
1059
//// This source file is free software; you can redistribute it   ////
1060
//// and/or modify it under the terms of the GNU Lesser General   ////
1061
//// Public License as published by the Free Software Foundation; ////
1062
//// either version 2.1 of the License, or (at your option) any   ////
1063
//// later version.                                               ////
1064
////                                                              ////
1065
//// This source is distributed in the hope that it will be       ////
1066
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1067
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1068
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1069
//// details.                                                     ////
1070
////                                                              ////
1071
//// You should have received a copy of the GNU Lesser General    ////
1072
//// Public License along with this source; if not, download it   ////
1073
//// from http://www.opencores.org/lgpl.shtml                     ////
1074
////                                                              ////
1075
//////////////////////////////////////////////////////////////////////
1076
/// ROM
1077 7 unneback
module vl_rom_init ( adr, q, clk);
1078
   parameter data_width = 32;
1079
   parameter addr_width = 8;
1080
   input [(addr_width-1):0]       adr;
1081
   output reg [(data_width-1):0] q;
1082
   input                         clk;
1083
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
1084
   parameter memory_file = "vl_rom.vmem";
1085
   initial
1086
     begin
1087
        $readmemh(memory_file, rom);
1088
     end
1089
   always @ (posedge clk)
1090
     q <= rom[adr];
1091
endmodule
1092 14 unneback
/*
1093 7 unneback
module vl_rom ( adr, q, clk);
1094 6 unneback
parameter data_width = 32;
1095
parameter addr_width = 4;
1096
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
1097
    {32'h18000000},
1098
    {32'hA8200000},
1099
    {32'hA8200000},
1100
    {32'hA8200000},
1101
    {32'h44003000},
1102
    {32'h15000000},
1103
    {32'h15000000},
1104
    {32'h15000000},
1105
    {32'h15000000},
1106
    {32'h15000000},
1107
    {32'h15000000},
1108
    {32'h15000000},
1109
    {32'h15000000},
1110
    {32'h15000000},
1111
    {32'h15000000},
1112
    {32'h15000000}};
1113 7 unneback
input [addr_width-1:0] adr;
1114 6 unneback
output reg [data_width-1:0] q;
1115
input clk;
1116
always @ (posedge clk)
1117 7 unneback
    q <= data[adr];
1118 6 unneback
endmodule
1119 14 unneback
*/
1120 6 unneback
// Single port RAM
1121
module vl_ram ( d, adr, we, q, clk);
1122
   parameter data_width = 32;
1123
   parameter addr_width = 8;
1124
   input [(data_width-1):0]      d;
1125
   input [(addr_width-1):0]       adr;
1126
   input                         we;
1127 7 unneback
   output reg [(data_width-1):0] q;
1128 6 unneback
   input                         clk;
1129
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
1130 7 unneback
   parameter init = 0;
1131
   parameter memory_file = "vl_ram.vmem";
1132
   generate if (init) begin : init_mem
1133
   initial
1134
     begin
1135
        $readmemh(memory_file, ram);
1136
     end
1137
   end
1138
   endgenerate
1139 6 unneback
   always @ (posedge clk)
1140
   begin
1141
   if (we)
1142
     ram[adr] <= d;
1143
   q <= ram[adr];
1144
   end
1145
endmodule
1146 7 unneback
module vl_ram_be ( d, adr, be, we, q, clk);
1147
   parameter data_width = 32;
1148
   parameter addr_width = 8;
1149
   input [(data_width-1):0]      d;
1150
   input [(addr_width-1):0]       adr;
1151
   input [(addr_width/4)-1:0]    be;
1152
   input                         we;
1153
   output reg [(data_width-1):0] q;
1154
   input                         clk;
1155
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
1156
   parameter init = 0;
1157
   parameter memory_file = "vl_ram.vmem";
1158
   generate if (init) begin : init_mem
1159
   initial
1160
     begin
1161
        $readmemh(memory_file, ram);
1162
     end
1163
   end
1164
   endgenerate
1165
   genvar i;
1166
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
1167
      always @ (posedge clk)
1168
      if (we & be[i])
1169
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
1170
   end
1171
   endgenerate
1172
   always @ (posedge clk)
1173
      q <= ram[adr];
1174
endmodule
1175 6 unneback
// Dual port RAM
1176
// ACTEL FPGA should not use logic to handle rw collision
1177 7 unneback
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1178 6 unneback
   parameter data_width = 32;
1179
   parameter addr_width = 8;
1180
   input [(data_width-1):0]      d_a;
1181
   input [(addr_width-1):0]       adr_a;
1182
   input [(addr_width-1):0]       adr_b;
1183
   input                         we_a;
1184
   output [(data_width-1):0]      q_b;
1185
   input                         clk_a, clk_b;
1186
   reg [(addr_width-1):0]         adr_b_reg;
1187
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
1188 7 unneback
   parameter init = 0;
1189
   parameter memory_file = "vl_ram.vmem";
1190
   generate if (init) begin : init_mem
1191
   initial
1192
     begin
1193
        $readmemh(memory_file, ram);
1194
     end
1195
   end
1196
   endgenerate
1197 6 unneback
   always @ (posedge clk_a)
1198
   if (we_a)
1199
     ram[adr_a] <= d_a;
1200
   always @ (posedge clk_b)
1201
   adr_b_reg <= adr_b;
1202
   assign q_b = ram[adr_b_reg];
1203
endmodule
1204 7 unneback
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1205 6 unneback
   parameter data_width = 32;
1206
   parameter addr_width = 8;
1207
   input [(data_width-1):0]      d_a;
1208
   input [(addr_width-1):0]       adr_a;
1209
   input [(addr_width-1):0]       adr_b;
1210
   input                         we_a;
1211
   output [(data_width-1):0]      q_b;
1212
   output reg [(data_width-1):0] q_a;
1213
   input                         clk_a, clk_b;
1214
   reg [(data_width-1):0]         q_b;
1215
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
1216 7 unneback
   parameter init = 0;
1217
   parameter memory_file = "vl_ram.vmem";
1218
   generate if (init) begin : init_mem
1219
   initial
1220
     begin
1221
        $readmemh(memory_file, ram);
1222
     end
1223
   end
1224
   endgenerate
1225 6 unneback
   always @ (posedge clk_a)
1226
     begin
1227
        q_a <= ram[adr_a];
1228
        if (we_a)
1229
             ram[adr_a] <= d_a;
1230
     end
1231
   always @ (posedge clk_b)
1232
          q_b <= ram[adr_b];
1233
endmodule
1234 7 unneback
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
1235 6 unneback
   parameter data_width = 32;
1236
   parameter addr_width = 8;
1237
   input [(data_width-1):0]      d_a;
1238
   input [(addr_width-1):0]       adr_a;
1239
   input [(addr_width-1):0]       adr_b;
1240
   input                         we_a;
1241
   output [(data_width-1):0]      q_b;
1242
   input [(data_width-1):0]       d_b;
1243
   output reg [(data_width-1):0] q_a;
1244
   input                         we_b;
1245
   input                         clk_a, clk_b;
1246
   reg [(data_width-1):0]         q_b;
1247
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
1248 7 unneback
   parameter init = 0;
1249
   parameter memory_file = "vl_ram.vmem";
1250
   generate if (init) begin : init_mem
1251
   initial
1252
     begin
1253
        $readmemh(memory_file, ram);
1254
     end
1255
   end
1256
   endgenerate
1257 6 unneback
   always @ (posedge clk_a)
1258
     begin
1259
        q_a <= ram[adr_a];
1260
        if (we_a)
1261
             ram[adr_a] <= d_a;
1262
     end
1263
   always @ (posedge clk_b)
1264
     begin
1265
        q_b <= ram[adr_b];
1266
        if (we_b)
1267
          ram[adr_b] <= d_b;
1268
     end
1269
endmodule
1270
// Content addresable memory, CAM
1271
// FIFO
1272 25 unneback
module vl_fifo_1r1w_fill_level_sync (
1273
    d, wr, fifo_full,
1274
    q, rd, fifo_empty,
1275
    fill_level,
1276
    clk, rst
1277
    );
1278
parameter data_width = 18;
1279
parameter addr_width = 4;
1280
// write side
1281
input  [data_width-1:0] d;
1282
input                   wr;
1283
output                  fifo_full;
1284
// read side
1285
output [data_width-1:0] q;
1286
input                   rd;
1287
output                  fifo_empty;
1288
// common
1289
output [addr_width:0]   fill_level;
1290
input rst, clk;
1291
wire [addr_width:1] wadr, radr;
1292
vl_cnt_bin_ce
1293
    # ( .length(addr_width))
1294
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
1295
vl_cnt_bin_ce
1296
    # (.length(addr_width))
1297
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
1298
vl_dpram_1r1w
1299
    # (.data_width(data_width), .addr_width(addr_width))
1300
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
1301 31 unneback
vl_cnt_bin_ce_rew_q_zq_l1
1302 27 unneback
    # (.length(addr_width+1), .level1_value(1<<addr_width))
1303 25 unneback
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
1304
endmodule
1305 27 unneback
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
1306
// RAM is supposed to be larger than the two FIFOs
1307
// LFSR counters used adr pointers
1308
module vl_fifo_2r2w_sync_simplex (
1309
    // a side
1310
    a_d, a_wr, a_fifo_full,
1311
    a_q, a_rd, a_fifo_empty,
1312
    a_fill_level,
1313
    // b side
1314
    b_d, b_wr, b_fifo_full,
1315
    b_q, b_rd, b_fifo_empty,
1316
    b_fill_level,
1317
    // common
1318
    clk, rst
1319
    );
1320
parameter data_width = 8;
1321
parameter addr_width = 5;
1322
parameter fifo_full_level = (1<<addr_width)-1;
1323
// a side
1324
input  [data_width-1:0] a_d;
1325
input                   a_wr;
1326
output                  a_fifo_full;
1327
output [data_width-1:0] a_q;
1328
input                   a_rd;
1329
output                  a_fifo_empty;
1330
output [addr_width-1:0] a_fill_level;
1331
// b side
1332
input  [data_width-1:0] b_d;
1333
input                   b_wr;
1334
output                  b_fifo_full;
1335
output [data_width-1:0] b_q;
1336
input                   b_rd;
1337
output                  b_fifo_empty;
1338
output [addr_width-1:0] b_fill_level;
1339
input                   clk;
1340
input                   rst;
1341
// adr_gen
1342
wire [addr_width:1] a_wadr, a_radr;
1343
wire [addr_width:1] b_wadr, b_radr;
1344
// dpram
1345
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
1346
vl_cnt_lfsr_ce
1347
    # ( .length(addr_width))
1348
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
1349
vl_cnt_lfsr_ce
1350
    # (.length(addr_width))
1351
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
1352
vl_cnt_lfsr_ce
1353
    # ( .length(addr_width))
1354
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
1355
vl_cnt_lfsr_ce
1356
    # (.length(addr_width))
1357
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
1358
// mux read or write adr to DPRAM
1359
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
1360
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
1361
vl_dpram_2r2w
1362
    # (.data_width(data_width), .addr_width(addr_width+1))
1363
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
1364
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
1365
vl_cnt_bin_ce_rew_zq_l1
1366 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
1367 27 unneback
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
1368
vl_cnt_bin_ce_rew_zq_l1
1369 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
1370 27 unneback
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
1371
endmodule
1372 6 unneback
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
1373 11 unneback
   parameter addr_width = 4;
1374
   parameter N = addr_width-1;
1375 6 unneback
   parameter Q1 = 2'b00;
1376
   parameter Q2 = 2'b01;
1377
   parameter Q3 = 2'b11;
1378
   parameter Q4 = 2'b10;
1379
   parameter going_empty = 1'b0;
1380
   parameter going_full  = 1'b1;
1381
   input [N:0]  wptr, rptr;
1382 14 unneback
   output       fifo_empty;
1383 6 unneback
   output       fifo_full;
1384
   input        wclk, rclk, rst;
1385
   wire direction;
1386
   reg  direction_set, direction_clr;
1387
   wire async_empty, async_full;
1388
   wire fifo_full2;
1389 14 unneback
   wire fifo_empty2;
1390 6 unneback
   // direction_set
1391
   always @ (wptr[N:N-1] or rptr[N:N-1])
1392
     case ({wptr[N:N-1],rptr[N:N-1]})
1393
       {Q1,Q2} : direction_set <= 1'b1;
1394
       {Q2,Q3} : direction_set <= 1'b1;
1395
       {Q3,Q4} : direction_set <= 1'b1;
1396
       {Q4,Q1} : direction_set <= 1'b1;
1397
       default : direction_set <= 1'b0;
1398
     endcase
1399
   // direction_clear
1400
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
1401
     if (rst)
1402
       direction_clr <= 1'b1;
1403
     else
1404
       case ({wptr[N:N-1],rptr[N:N-1]})
1405
         {Q2,Q1} : direction_clr <= 1'b1;
1406
         {Q3,Q2} : direction_clr <= 1'b1;
1407
         {Q4,Q3} : direction_clr <= 1'b1;
1408
         {Q1,Q4} : direction_clr <= 1'b1;
1409
         default : direction_clr <= 1'b0;
1410
       endcase
1411 18 unneback
    vl_dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
1412 6 unneback
   assign async_empty = (wptr == rptr) && (direction==going_empty);
1413
   assign async_full  = (wptr == rptr) && (direction==going_full);
1414 18 unneback
    vl_dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
1415
    vl_dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
1416 6 unneback
/*
1417
   always @ (posedge wclk or posedge rst or posedge async_full)
1418
     if (rst)
1419
       {fifo_full, fifo_full2} <= 2'b00;
1420
     else if (async_full)
1421
       {fifo_full, fifo_full2} <= 2'b11;
1422
     else
1423
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
1424
*/
1425 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
1426 6 unneback
     if (async_empty)
1427
       {fifo_empty, fifo_empty2} <= 2'b11;
1428
     else
1429 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
1430 18 unneback
    vl_dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
1431
    vl_dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
1432 27 unneback
endmodule // async_compb
1433 6 unneback
module vl_fifo_1r1w_async (
1434
    d, wr, fifo_full, wr_clk, wr_rst,
1435
    q, rd, fifo_empty, rd_clk, rd_rst
1436
    );
1437
parameter data_width = 18;
1438
parameter addr_width = 4;
1439
// write side
1440
input  [data_width-1:0] d;
1441
input                   wr;
1442
output                  fifo_full;
1443
input                   wr_clk;
1444
input                   wr_rst;
1445
// read side
1446
output [data_width-1:0] q;
1447
input                   rd;
1448
output                  fifo_empty;
1449
input                   rd_clk;
1450
input                   rd_rst;
1451
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
1452 18 unneback
vl_cnt_gray_ce_bin
1453 6 unneback
    # ( .length(addr_width))
1454
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
1455 18 unneback
vl_cnt_gray_ce_bin
1456 6 unneback
    # (.length(addr_width))
1457 23 unneback
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
1458 7 unneback
vl_dpram_1r1w
1459 6 unneback
    # (.data_width(data_width), .addr_width(addr_width))
1460
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
1461
vl_fifo_cmp_async
1462
    # (.addr_width(addr_width))
1463
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
1464
endmodule
1465 8 unneback
module vl_fifo_2r2w_async (
1466 6 unneback
    // a side
1467
    a_d, a_wr, a_fifo_full,
1468
    a_q, a_rd, a_fifo_empty,
1469
    a_clk, a_rst,
1470
    // b side
1471
    b_d, b_wr, b_fifo_full,
1472
    b_q, b_rd, b_fifo_empty,
1473
    b_clk, b_rst
1474
    );
1475
parameter data_width = 18;
1476
parameter addr_width = 4;
1477
// a side
1478
input  [data_width-1:0] a_d;
1479
input                   a_wr;
1480
output                  a_fifo_full;
1481
output [data_width-1:0] a_q;
1482
input                   a_rd;
1483
output                  a_fifo_empty;
1484
input                   a_clk;
1485
input                   a_rst;
1486
// b side
1487
input  [data_width-1:0] b_d;
1488
input                   b_wr;
1489
output                  b_fifo_full;
1490
output [data_width-1:0] b_q;
1491
input                   b_rd;
1492
output                  b_fifo_empty;
1493
input                   b_clk;
1494
input                   b_rst;
1495
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
1496
vl_fifo_1r1w_async_a (
1497
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
1498
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
1499
    );
1500
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
1501
vl_fifo_1r1w_async_b (
1502
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
1503
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
1504
    );
1505
endmodule
1506 8 unneback
module vl_fifo_2r2w_async_simplex (
1507 6 unneback
    // a side
1508
    a_d, a_wr, a_fifo_full,
1509
    a_q, a_rd, a_fifo_empty,
1510
    a_clk, a_rst,
1511
    // b side
1512
    b_d, b_wr, b_fifo_full,
1513
    b_q, b_rd, b_fifo_empty,
1514
    b_clk, b_rst
1515
    );
1516
parameter data_width = 18;
1517
parameter addr_width = 4;
1518
// a side
1519
input  [data_width-1:0] a_d;
1520
input                   a_wr;
1521
output                  a_fifo_full;
1522
output [data_width-1:0] a_q;
1523
input                   a_rd;
1524
output                  a_fifo_empty;
1525
input                   a_clk;
1526
input                   a_rst;
1527
// b side
1528
input  [data_width-1:0] b_d;
1529
input                   b_wr;
1530
output                  b_fifo_full;
1531
output [data_width-1:0] b_q;
1532
input                   b_rd;
1533
output                  b_fifo_empty;
1534
input                   b_clk;
1535
input                   b_rst;
1536
// adr_gen
1537
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
1538
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
1539
// dpram
1540
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
1541 18 unneback
vl_cnt_gray_ce_bin
1542 6 unneback
    # ( .length(addr_width))
1543
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
1544 18 unneback
vl_cnt_gray_ce_bin
1545 6 unneback
    # (.length(addr_width))
1546
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
1547 18 unneback
vl_cnt_gray_ce_bin
1548 6 unneback
    # ( .length(addr_width))
1549
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
1550 18 unneback
vl_cnt_gray_ce_bin
1551 6 unneback
    # (.length(addr_width))
1552
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
1553
// mux read or write adr to DPRAM
1554
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
1555
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
1556 11 unneback
vl_dpram_2r2w
1557 6 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
1558
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
1559
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
1560 11 unneback
vl_fifo_cmp_async
1561 6 unneback
    # (.addr_width(addr_width))
1562
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
1563 11 unneback
vl_fifo_cmp_async
1564 6 unneback
    # (.addr_width(addr_width))
1565
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
1566
endmodule
1567 12 unneback
//////////////////////////////////////////////////////////////////////
1568
////                                                              ////
1569
////  Versatile library, wishbone stuff                           ////
1570
////                                                              ////
1571
////  Description                                                 ////
1572
////  Wishbone compliant modules                                  ////
1573
////                                                              ////
1574
////                                                              ////
1575
////  To Do:                                                      ////
1576
////   -                                                          ////
1577
////                                                              ////
1578
////  Author(s):                                                  ////
1579
////      - Michael Unneback, unneback@opencores.org              ////
1580
////        ORSoC AB                                              ////
1581
////                                                              ////
1582
//////////////////////////////////////////////////////////////////////
1583
////                                                              ////
1584
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1585
////                                                              ////
1586
//// This source file may be used and distributed without         ////
1587
//// restriction provided that this copyright statement is not    ////
1588
//// removed from the file and that any derivative work contains  ////
1589
//// the original copyright notice and the associated disclaimer. ////
1590
////                                                              ////
1591
//// This source file is free software; you can redistribute it   ////
1592
//// and/or modify it under the terms of the GNU Lesser General   ////
1593
//// Public License as published by the Free Software Foundation; ////
1594
//// either version 2.1 of the License, or (at your option) any   ////
1595
//// later version.                                               ////
1596
////                                                              ////
1597
//// This source is distributed in the hope that it will be       ////
1598
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1599
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1600
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1601
//// details.                                                     ////
1602
////                                                              ////
1603
//// You should have received a copy of the GNU Lesser General    ////
1604
//// Public License along with this source; if not, download it   ////
1605
//// from http://www.opencores.org/lgpl.shtml                     ////
1606
////                                                              ////
1607
//////////////////////////////////////////////////////////////////////
1608
// async wb3 - wb3 bridge
1609
`timescale 1ns/1ns
1610 18 unneback
module vl_wb3wb3_bridge (
1611 12 unneback
        // wishbone slave side
1612
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
1613
        // wishbone master side
1614
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
1615
input [31:0] wbs_dat_i;
1616
input [31:2] wbs_adr_i;
1617
input [3:0]  wbs_sel_i;
1618
input [1:0]  wbs_bte_i;
1619
input [2:0]  wbs_cti_i;
1620
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
1621
output [31:0] wbs_dat_o;
1622 14 unneback
output wbs_ack_o;
1623 12 unneback
input wbs_clk, wbs_rst;
1624
output [31:0] wbm_dat_o;
1625
output reg [31:2] wbm_adr_o;
1626
output [3:0]  wbm_sel_o;
1627
output reg [1:0]  wbm_bte_o;
1628
output reg [2:0]  wbm_cti_o;
1629 14 unneback
output reg wbm_we_o;
1630
output wbm_cyc_o;
1631 12 unneback
output wbm_stb_o;
1632
input [31:0]  wbm_dat_i;
1633
input wbm_ack_i;
1634
input wbm_clk, wbm_rst;
1635
parameter addr_width = 4;
1636
// bte
1637
parameter linear       = 2'b00;
1638
parameter wrap4        = 2'b01;
1639
parameter wrap8        = 2'b10;
1640
parameter wrap16       = 2'b11;
1641
// cti
1642
parameter classic      = 3'b000;
1643
parameter incburst     = 3'b010;
1644
parameter endofburst   = 3'b111;
1645
parameter wbs_adr  = 1'b0;
1646
parameter wbs_data = 1'b1;
1647 33 unneback
parameter wbm_adr0      = 2'b00;
1648
parameter wbm_adr1      = 2'b01;
1649
parameter wbm_data      = 2'b10;
1650
parameter wbm_data_wait = 2'b11;
1651 12 unneback
reg [1:0] wbs_bte_reg;
1652
reg wbs;
1653
wire wbs_eoc_alert, wbm_eoc_alert;
1654
reg wbs_eoc, wbm_eoc;
1655
reg [1:0] wbm;
1656 14 unneback
wire [1:16] wbs_count, wbm_count;
1657 12 unneback
wire [35:0] a_d, a_q, b_d, b_q;
1658
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
1659
reg a_rd_reg;
1660
wire b_rd_adr, b_rd_data;
1661 14 unneback
wire b_rd_data_reg;
1662
wire [35:0] temp;
1663 12 unneback
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
1664
always @ (posedge wbs_clk or posedge wbs_rst)
1665
if (wbs_rst)
1666
        wbs_eoc <= 1'b0;
1667
else
1668
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
1669
                wbs_eoc <= wbs_bte_i==linear;
1670
        else if (wbs_eoc_alert & (a_rd | a_wr))
1671
                wbs_eoc <= 1'b1;
1672 18 unneback
vl_cnt_shreg_ce_clear # ( .length(16))
1673 12 unneback
    cnt0 (
1674
        .cke(wbs_ack_o),
1675
        .clear(wbs_eoc),
1676
        .q(wbs_count),
1677
        .rst(wbs_rst),
1678
        .clk(wbs_clk));
1679
always @ (posedge wbs_clk or posedge wbs_rst)
1680
if (wbs_rst)
1681
        wbs <= wbs_adr;
1682
else
1683
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & !a_fifo_full)
1684
                wbs <= wbs_data;
1685
        else if (wbs_eoc & wbs_ack_o)
1686
                wbs <= wbs_adr;
1687
// wbs FIFO
1688
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,wbs_bte_i,wbs_cti_i} : {wbs_dat_i,wbs_sel_i};
1689
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & !a_fifo_full :
1690
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
1691
              1'b0;
1692
assign a_rd = !a_fifo_empty;
1693
always @ (posedge wbs_clk or posedge wbs_rst)
1694
if (wbs_rst)
1695
        a_rd_reg <= 1'b0;
1696
else
1697
        a_rd_reg <= a_rd;
1698
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
1699
assign wbs_dat_o = a_q[35:4];
1700
always @ (posedge wbs_clk or posedge wbs_rst)
1701
if (wbs_rst)
1702 13 unneback
        wbs_bte_reg <= 2'b00;
1703 12 unneback
else
1704 13 unneback
        wbs_bte_reg <= wbs_bte_i;
1705 12 unneback
// wbm FIFO
1706
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
1707
always @ (posedge wbm_clk or posedge wbm_rst)
1708
if (wbm_rst)
1709
        wbm_eoc <= 1'b0;
1710
else
1711
        if (wbm==wbm_adr0 & !b_fifo_empty)
1712
                wbm_eoc <= b_q[4:3] == linear;
1713
        else if (wbm_eoc_alert & wbm_ack_i)
1714
                wbm_eoc <= 1'b1;
1715
always @ (posedge wbm_clk or posedge wbm_rst)
1716
if (wbm_rst)
1717
        wbm <= wbm_adr0;
1718
else
1719 33 unneback
/*
1720 12 unneback
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
1721
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
1722
        (wbm==wbm_adr1 & !wbm_we_o) |
1723
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
1724
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
1725 33 unneback
*/
1726
    case (wbm)
1727
    wbm_adr0:
1728
        if (!b_fifo_empty)
1729
            wbm <= wbm_adr1;
1730
    wbm_adr1:
1731
        if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
1732
            wbm <= wbm_data;
1733
    wbm_data:
1734
        if (wbm_ack_i & wbm_eoc)
1735
            wbm <= wbm_adr0;
1736
        else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
1737
            wbm <= wbm_data_wait;
1738
    wbm_data_wait:
1739
        if (!b_fifo_empty)
1740
            wbm <= wbm_data;
1741
    endcase
1742 12 unneback
assign b_d = {wbm_dat_i,4'b1111};
1743
assign b_wr = !wbm_we_o & wbm_ack_i;
1744
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
1745
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
1746
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
1747 33 unneback
                   (wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
1748 12 unneback
                   1'b0;
1749
assign b_rd = b_rd_adr | b_rd_data;
1750 18 unneback
vl_dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
1751
vl_dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
1752 12 unneback
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
1753 18 unneback
vl_cnt_shreg_ce_clear # ( .length(16))
1754 12 unneback
    cnt1 (
1755
        .cke(wbm_ack_i),
1756
        .clear(wbm_eoc),
1757
        .q(wbm_count),
1758
        .rst(wbm_rst),
1759
        .clk(wbm_clk));
1760 33 unneback
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
1761
assign wbm_stb_o = (wbm==wbm_data);
1762 12 unneback
always @ (posedge wbm_clk or posedge wbm_rst)
1763
if (wbm_rst)
1764
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
1765
else begin
1766
        if (wbm==wbm_adr0 & !b_fifo_empty)
1767
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
1768
        else if (wbm_eoc_alert & wbm_ack_i)
1769
                wbm_cti_o <= endofburst;
1770
end
1771
//async_fifo_dw_simplex_top
1772
vl_fifo_2r2w_async_simplex
1773
# ( .data_width(36), .addr_width(addr_width))
1774
fifo (
1775
    // a side
1776
    .a_d(a_d),
1777
    .a_wr(a_wr),
1778
    .a_fifo_full(a_fifo_full),
1779
    .a_q(a_q),
1780
    .a_rd(a_rd),
1781
    .a_fifo_empty(a_fifo_empty),
1782
    .a_clk(wbs_clk),
1783
    .a_rst(wbs_rst),
1784
    // b side
1785
    .b_d(b_d),
1786
    .b_wr(b_wr),
1787
    .b_fifo_full(b_fifo_full),
1788
    .b_q(b_q),
1789
    .b_rd(b_rd),
1790
    .b_fifo_empty(b_fifo_empty),
1791
    .b_clk(wbm_clk),
1792
    .b_rst(wbm_rst)
1793
    );
1794
endmodule
1795 39 unneback
module vl_wb3_arbiter_type1 (
1796
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
1797
    wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
1798
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
1799
    wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
1800
    wb_clk, wb_rst
1801
);
1802
parameter nr_of_ports = 3;
1803
parameter adr_size = 26;
1804
parameter adr_lo   = 2;
1805
parameter dat_size = 32;
1806
parameter sel_size = dat_size/8;
1807
localparam aw = (adr_size - adr_lo) * nr_of_ports;
1808
localparam dw = dat_size * nr_of_ports;
1809
localparam sw = sel_size * nr_of_ports;
1810
localparam cw = 3 * nr_of_ports;
1811
localparam bw = 2 * nr_of_ports;
1812
input  [dw-1:0] wbm_dat_o;
1813
input  [aw-1:0] wbm_adr_o;
1814
input  [sw-1:0] wbm_sel_o;
1815
input  [cw-1:0] wbm_cti_o;
1816
input  [bw-1:0] wbm_bte_o;
1817
input  [nr_of_ports-1:0] wbm_we_o, wbm_stb_o, wbm_cyc_o;
1818
output [dw-1:0] wbm_dat_i;
1819
output [nr_of_ports-1:0] wbm_ack_i, wbm_err_i, wbm_rty_i;
1820
output [dat_size-1:0] wbs_dat_i;
1821
output [adr_size-1:adr_lo] wbs_adr_i;
1822
output [sel_size-1:0] wbs_sel_i;
1823
output [2:0] wbs_cti_i;
1824
output [1:0] wbs_bte_i;
1825
output wbs_we_i, wbs_stb_i, wbs_cyc_i;
1826
input  [dat_size-1:0] wbs_dat_o;
1827
input  wbs_ack_o, wbs_err_o, wbs_rty_o;
1828
input wb_clk, wb_rst;
1829 44 unneback
reg  [nr_of_ports-1:0] select;
1830 39 unneback
wire [nr_of_ports-1:0] state;
1831
wire [nr_of_ports-1:0] eoc; // end-of-cycle
1832
wire [nr_of_ports-1:0] sel;
1833
wire idle;
1834
genvar i;
1835
assign idle = !(|state);
1836
generate
1837
if (nr_of_ports == 2) begin
1838
    wire [2:0] wbm1_cti_o, wbm0_cti_o;
1839
    assign {wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
1840 44 unneback
    //assign select = (idle) ? {wbm_cyc_o[1],!wbm_cyc_o[1] & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
1841
    always @ (idle or wbm_cyc_o)
1842
    if (idle)
1843
        casex (wbm_cyc_o)
1844
        2'b1x : select = 2'b10;
1845
        2'b01 : select = 2'b01;
1846
        default : select = {nr_of_ports{1'b0}};
1847
        endcase
1848
    else
1849
        select = {nr_of_ports{1'b0}};
1850 39 unneback
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
1851
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
1852
end
1853
endgenerate
1854
generate
1855
if (nr_of_ports == 3) begin
1856
    wire [2:0] wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
1857
    assign {wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
1858 44 unneback
    always @ (idle or wbm_cyc_o)
1859
    if (idle)
1860
        casex (wbm_cyc_o)
1861
        3'b1xx : select = 3'b100;
1862
        3'b01x : select = 3'b010;
1863
        3'b001 : select = 3'b001;
1864
        default : select = {nr_of_ports{1'b0}};
1865
        endcase
1866
    else
1867
        select = {nr_of_ports{1'b0}};
1868
//    assign select = (idle) ? {wbm_cyc_o[2],!wbm_cyc_o[2] & wbm_cyc_o[1],wbm_cyc_o[2:1]==2'b00 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
1869 39 unneback
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
1870
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
1871
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
1872
end
1873
endgenerate
1874
generate
1875 44 unneback
if (nr_of_ports == 4) begin
1876
    wire [2:0] wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
1877
    assign {wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
1878
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
1879
    always @ (idle or wbm_cyc_o)
1880
    if (idle)
1881
        casex (wbm_cyc_o)
1882
        4'b1xxx : select = 4'b1000;
1883
        4'b01xx : select = 4'b0100;
1884
        4'b001x : select = 4'b0010;
1885
        4'b0001 : select = 4'b0001;
1886
        default : select = {nr_of_ports{1'b0}};
1887
        endcase
1888
    else
1889
        select = {nr_of_ports{1'b0}};
1890
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
1891
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
1892
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
1893
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
1894
end
1895
endgenerate
1896
generate
1897
if (nr_of_ports == 5) begin
1898
    wire [2:0] wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
1899
    assign {wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
1900
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
1901
    always @ (idle or wbm_cyc_o)
1902
    if (idle)
1903
        casex (wbm_cyc_o)
1904
        5'b1xxxx : select = 5'b10000;
1905
        5'b01xxx : select = 5'b01000;
1906
        5'b001xx : select = 5'b00100;
1907
        5'b0001x : select = 5'b00010;
1908
        5'b00001 : select = 5'b00001;
1909
        default : select = {nr_of_ports{1'b0}};
1910
        endcase
1911
    else
1912
        select = {nr_of_ports{1'b0}};
1913
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
1914
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
1915
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
1916
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
1917
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
1918
end
1919
endgenerate
1920
generate
1921 39 unneback
for (i=0;i<nr_of_ports;i=i+1) begin
1922
    vl_spr sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));
1923
end
1924
endgenerate
1925
    assign sel = select | state;
1926
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i));
1927
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(adr_size-adr_lo)) mux1 ( .a(wbm_adr_o), .sel(sel), .dout(wbs_adr_i));
1928
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(sel_size)) mux2 ( .a(wbm_sel_o), .sel(sel), .dout(wbs_sel_i));
1929
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(3)) mux3 ( .a(wbm_cti_o), .sel(sel), .dout(wbs_cti_i));
1930
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(2)) mux4 ( .a(wbm_bte_o), .sel(sel), .dout(wbs_bte_i));
1931
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(1)) mux5 ( .a(wbm_we_o), .sel(sel), .dout(wbs_we_i));
1932
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(1)) mux6 ( .a(wbm_stb_o), .sel(sel), .dout(wbs_stb_i));
1933
    assign wbs_cyc_i = |sel;
1934
    assign wbm_dat_i = {nr_of_ports{wbs_dat_o}};
1935
    assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
1936
    assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
1937
    assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
1938
endmodule
1939 17 unneback
// WB ROM
1940 18 unneback
module vl_wb_boot_rom (
1941 17 unneback
    wb_adr_i, wb_stb_i, wb_cyc_i,
1942 18 unneback
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
1943
    parameter adr_hi = 31;
1944
    parameter adr_lo = 28;
1945
    parameter adr_sel = 4'hf;
1946
    parameter addr_width = 5;
1947 33 unneback
/*
1948 17 unneback
`ifndef BOOT_ROM
1949
`define BOOT_ROM "boot_rom.v"
1950
`endif
1951 33 unneback
*/
1952 18 unneback
    input [adr_hi:2]    wb_adr_i;
1953
    input               wb_stb_i;
1954
    input               wb_cyc_i;
1955
    output [31:0]        wb_dat_o;
1956
    output              wb_ack_o;
1957
    output              hit_o;
1958
    input               wb_clk;
1959
    input               wb_rst;
1960
    wire hit;
1961
    reg [31:0] wb_dat;
1962
    reg wb_ack;
1963
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
1964 17 unneback
always @ (posedge wb_clk or posedge wb_rst)
1965
    if (wb_rst)
1966 18 unneback
        wb_dat <= 32'h15000000;
1967 17 unneback
    else
1968 18 unneback
         case (wb_adr_i[addr_width-1:2])
1969 33 unneback
`ifdef BOOT_ROM
1970 17 unneback
`include `BOOT_ROM
1971 33 unneback
`endif
1972 17 unneback
           /*
1973
            // Zero r0 and jump to 0x00000100
1974 18 unneback
 
1975
            1 : wb_dat <= 32'hA8200000;
1976
            2 : wb_dat <= 32'hA8C00100;
1977
            3 : wb_dat <= 32'h44003000;
1978
            4 : wb_dat <= 32'h15000000;
1979 17 unneback
            */
1980
           default:
1981 18 unneback
             wb_dat <= 32'h00000000;
1982 17 unneback
         endcase // case (wb_adr_i)
1983
always @ (posedge wb_clk or posedge wb_rst)
1984
    if (wb_rst)
1985 18 unneback
        wb_ack <= 1'b0;
1986 17 unneback
    else
1987 18 unneback
        wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
1988
assign hit_o = hit;
1989
assign wb_dat_o = wb_dat & {32{wb_ack}};
1990
assign wb_ack_o = wb_ack;
1991 17 unneback
endmodule
1992 32 unneback
module vl_wb_dpram (
1993
        // wishbone slave side a
1994
        wbsa_dat_i, wbsa_adr_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o,
1995
        wbsa_clk, wbsa_rst,
1996
        // wishbone slave side a
1997
        wbsb_dat_i, wbsb_adr_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o,
1998
        wbsb_clk, wbsb_rst);
1999
parameter data_width = 32;
2000
parameter addr_width = 8;
2001
parameter dat_o_mask_a = 1;
2002
parameter dat_o_mask_b = 1;
2003
input [31:0] wbsa_dat_i;
2004
input [addr_width-1:2] wbsa_adr_i;
2005
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
2006
output [31:0] wbsa_dat_o;
2007
output wbsa_ack_o;
2008
input wbsa_clk, wbsa_rst;
2009
input [31:0] wbsb_dat_i;
2010
input [addr_width-1:2] wbsb_adr_i;
2011
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
2012
output [31:0] wbsb_dat_o;
2013
output wbsb_ack_o;
2014
input wbsb_clk, wbsb_rst;
2015
wire wbsa_dat_tmp, wbsb_dat_tmp;
2016
vl_dpram_2r2w # (
2017 33 unneback
    .data_width(data_width), .addr_width(addr_width) )
2018 32 unneback
dpram0(
2019
    .d_a(wbsa_dat_i),
2020
    .q_a(wbsa_dat_tmp),
2021
    .adr_a(wbsa_adr_i),
2022
    .we_a(wbsa_we_i),
2023
    .clk_a(wbsa_clk),
2024
    .d_b(wbsb_dat_i),
2025
    .q_b(wbsb_dat_tmp),
2026
    .adr_b(wbsb_adr_i),
2027
    .we_b(wbsb_we_i),
2028
    .clk_b(wbsb_clk) );
2029 33 unneback
generate if (dat_o_mask_a==1)
2030 32 unneback
    assign wbsa_dat_o = wbsa_dat_tmp & {data_width{wbsa_ack_o}};
2031
endgenerate
2032 33 unneback
generate if (dat_o_mask_a==0)
2033 32 unneback
    assign wbsa_dat_o = wbsa_dat_tmp;
2034
endgenerate
2035 33 unneback
generate if (dat_o_mask_b==1)
2036 32 unneback
    assign wbsb_dat_o = wbsb_dat_tmp & {data_width{wbsb_ack_o}};
2037
endgenerate
2038 33 unneback
generate if (dat_o_mask_b==0)
2039 32 unneback
    assign wbsb_dat_o = wbsb_dat_tmp;
2040
endgenerate
2041
vl_spr ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
2042
vl_spr ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
2043
endmodule
2044 18 unneback
//////////////////////////////////////////////////////////////////////
2045
////                                                              ////
2046
////  Arithmetic functions                                        ////
2047
////                                                              ////
2048
////  Description                                                 ////
2049
////  Arithmetic functions for ALU and DSP                        ////
2050
////                                                              ////
2051
////                                                              ////
2052
////  To Do:                                                      ////
2053
////   -                                                          ////
2054
////                                                              ////
2055
////  Author(s):                                                  ////
2056
////      - Michael Unneback, unneback@opencores.org              ////
2057
////        ORSoC AB                                              ////
2058
////                                                              ////
2059
//////////////////////////////////////////////////////////////////////
2060
////                                                              ////
2061
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2062
////                                                              ////
2063
//// This source file may be used and distributed without         ////
2064
//// restriction provided that this copyright statement is not    ////
2065
//// removed from the file and that any derivative work contains  ////
2066
//// the original copyright notice and the associated disclaimer. ////
2067
////                                                              ////
2068
//// This source file is free software; you can redistribute it   ////
2069
//// and/or modify it under the terms of the GNU Lesser General   ////
2070
//// Public License as published by the Free Software Foundation; ////
2071
//// either version 2.1 of the License, or (at your option) any   ////
2072
//// later version.                                               ////
2073
////                                                              ////
2074
//// This source is distributed in the hope that it will be       ////
2075
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2076
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2077
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2078
//// details.                                                     ////
2079
////                                                              ////
2080
//// You should have received a copy of the GNU Lesser General    ////
2081
//// Public License along with this source; if not, download it   ////
2082
//// from http://www.opencores.org/lgpl.shtml                     ////
2083
////                                                              ////
2084
//////////////////////////////////////////////////////////////////////
2085
// signed multiplication
2086
module vl_mults (a,b,p);
2087
parameter operand_a_width = 18;
2088
parameter operand_b_width = 18;
2089
parameter result_hi = 35;
2090
parameter result_lo = 0;
2091
input [operand_a_width-1:0] a;
2092
input [operand_b_width-1:0] b;
2093
output [result_hi:result_lo] p;
2094
wire signed [operand_a_width-1:0] ai;
2095
wire signed [operand_b_width-1:0] bi;
2096
wire signed [operand_a_width+operand_b_width-1:0] result;
2097
    assign ai = a;
2098
    assign bi = b;
2099
    assign result = ai * bi;
2100
    assign p = result[result_hi:result_lo];
2101
endmodule
2102
module vl_mults18x18 (a,b,p);
2103
input [17:0] a,b;
2104
output [35:0] p;
2105
vl_mult
2106
    # (.operand_a_width(18), .operand_b_width(18))
2107
    mult0 (.a(a), .b(b), .p(p));
2108
endmodule
2109
// unsigned multiplication
2110
module vl_mult (a,b,p);
2111
parameter operand_a_width = 18;
2112
parameter operand_b_width = 18;
2113
parameter result_hi = 35;
2114
parameter result_lo = 0;
2115
input [operand_a_width-1:0] a;
2116
input [operand_b_width-1:0] b;
2117
output [result_hi:result_hi] p;
2118
wire [operand_a_width+operand_b_width-1:0] result;
2119
    assign result = a * b;
2120
    assign p = result[result_hi:result_lo];
2121
endmodule
2122
// shift unit
2123
// supporting the following shift functions
2124
//   SLL
2125
//   SRL
2126
//   SRA
2127
module vl_shift_unit_32( din, s, dout, opcode);
2128
input [31:0] din; // data in operand
2129
input [4:0] s; // shift operand
2130
input [1:0] opcode;
2131
output [31:0] dout;
2132
parameter opcode_sll = 2'b00;
2133
//parameter opcode_srl = 2'b01;
2134
parameter opcode_sra = 2'b10;
2135
//parameter opcode_ror = 2'b11;
2136
wire sll, sra;
2137
assign sll = opcode == opcode_sll;
2138
assign sra = opcode == opcode_sra;
2139
wire [15:1] s1;
2140
wire [3:0] sign;
2141
wire [7:0] tmp [0:3];
2142
// first stage is multiplier based
2143
// shift operand as fractional 8.7
2144
assign s1[15] = sll & s[2:0]==3'd7;
2145
assign s1[14] = sll & s[2:0]==3'd6;
2146
assign s1[13] = sll & s[2:0]==3'd5;
2147
assign s1[12] = sll & s[2:0]==3'd4;
2148
assign s1[11] = sll & s[2:0]==3'd3;
2149
assign s1[10] = sll & s[2:0]==3'd2;
2150
assign s1[ 9] = sll & s[2:0]==3'd1;
2151
assign s1[ 8] = s[2:0]==3'd0;
2152
assign s1[ 7] = !sll & s[2:0]==3'd1;
2153
assign s1[ 6] = !sll & s[2:0]==3'd2;
2154
assign s1[ 5] = !sll & s[2:0]==3'd3;
2155
assign s1[ 4] = !sll & s[2:0]==3'd4;
2156
assign s1[ 3] = !sll & s[2:0]==3'd5;
2157
assign s1[ 2] = !sll & s[2:0]==3'd6;
2158
assign s1[ 1] = !sll & s[2:0]==3'd7;
2159
assign sign[3] = din[31] & sra;
2160
assign sign[2] = sign[3] & (&din[31:24]);
2161
assign sign[1] = sign[2] & (&din[23:16]);
2162
assign sign[0] = sign[1] & (&din[15:8]);
2163
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte3 ( .a({sign[3], {8{sign[3]}},din[31:24], din[23:16]}), .b({1'b0,s1}), .p(tmp[3]));
2164
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte2 ( .a({sign[2], din[31:24]  ,din[23:16],  din[15:8]}), .b({1'b0,s1}), .p(tmp[2]));
2165
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte1 ( .a({sign[1], din[23:16]  ,din[15:8],   din[7:0]}), .b({1'b0,s1}), .p(tmp[1]));
2166
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte0 ( .a({sign[0], din[15:8]   ,din[7:0],    8'h00}),      .b({1'b0,s1}), .p(tmp[0]));
2167
// second stage is multiplexer based
2168
// shift on byte level
2169
// mux byte 3
2170
assign dout[31:24] = (s[4:3]==2'b00) ? tmp[3] :
2171
                     (sll & s[4:3]==2'b01) ? tmp[2] :
2172
                     (sll & s[4:3]==2'b10) ? tmp[1] :
2173
                     (sll & s[4:3]==2'b11) ? tmp[0] :
2174
                     {8{sign[3]}};
2175
// mux byte 2
2176
assign dout[23:16] = (s[4:3]==2'b00) ? tmp[2] :
2177
                     (sll & s[4:3]==2'b01) ? tmp[1] :
2178
                     (sll & s[4:3]==2'b10) ? tmp[0] :
2179
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
2180
                     (s[4:3]==2'b01) ? tmp[3] :
2181
                     {8{sign[3]}};
2182
// mux byte 1
2183
assign dout[15:8]  = (s[4:3]==2'b00) ? tmp[1] :
2184
                     (sll & s[4:3]==2'b01) ? tmp[0] :
2185
                     (sll & s[4:3]==2'b10) ? {8{1'b0}} :
2186
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
2187
                     (s[4:3]==2'b01) ? tmp[2] :
2188
                     (s[4:3]==2'b10) ? tmp[3] :
2189
                     {8{sign[3]}};
2190
// mux byte 0
2191
assign dout[7:0]   = (s[4:3]==2'b00) ? tmp[0] :
2192
                     (sll) ?  {8{1'b0}}:
2193
                     (s[4:3]==2'b01) ? tmp[1] :
2194
                     (s[4:3]==2'b10) ? tmp[2] :
2195
                     tmp[3];
2196
endmodule
2197
// logic unit
2198
// supporting the following logic functions
2199
//    a and b
2200
//    a or  b
2201
//    a xor b
2202
//    not b
2203
module vl_logic_unit( a, b, result, opcode);
2204
parameter width = 32;
2205
parameter opcode_and = 2'b00;
2206
parameter opcode_or  = 2'b01;
2207
parameter opcode_xor = 2'b10;
2208
input [width-1:0] a,b;
2209
output [width-1:0] result;
2210
input [1:0] opcode;
2211
assign result = (opcode==opcode_and) ? a & b :
2212
                (opcode==opcode_or)  ? a | b :
2213
                (opcode==opcode_xor) ? a ^ b :
2214
                b;
2215
endmodule
2216
module vl_arith_unit ( a, b, c_in, add_sub, sign, result, c_out, z, ovfl);
2217
parameter width = 32;
2218
parameter opcode_add = 1'b0;
2219
parameter opcode_sub = 1'b1;
2220
input [width-1:0] a,b;
2221
input c_in, add_sub, sign;
2222
output [width-1:0] result;
2223
output c_out, z, ovfl;
2224
assign {c_out,result} = {(a[width-1] & sign),a} + ({a[width-1] & sign,b} ^ {(width+1){(add_sub==opcode_sub)}}) + {{(width-1){1'b0}},(c_in | (add_sub==opcode_sub))};
2225
assign z = (result=={width{1'b0}});
2226
assign ovfl = ( a[width-1] &  b[width-1] & ~result[width-1]) |
2227
               (~a[width-1] & ~b[width-1] &  result[width-1]);
2228
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2021 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.