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1 6 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  Versatile library, clock and reset                          ////
4
////                                                              ////
5
////  Description                                                 ////
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////  Logic related to clock and reset                            ////
7
////                                                              ////
8
////                                                              ////
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////  To Do:                                                      ////
10
////   - add more different registers                             ////
11
////                                                              ////
12
////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
14
////        ORSoC AB                                              ////
15
////                                                              ////
16
//////////////////////////////////////////////////////////////////////
17
////                                                              ////
18
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
19
////                                                              ////
20
//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
36
////                                                              ////
37
//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42 48 unneback
`timescale 1 ns/100 ps
43 6 unneback
// Global buffer
44
// usage:
45
// use to enable global buffers for high fan out signals such as clock and reset
46
// Version: 8.4 8.4.0.33
47
module gbuf(GL,CLK);
48
output GL;
49
input  CLK;
50
    wire GND;
51
    GND GND_1_net(.Y(GND));
52
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
53
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
54
endmodule
55
`timescale 1 ns/1 ns
56
module vl_gbuf ( i, o);
57
input i;
58
output o;
59
`ifdef SIM_GBUF
60
assign o=i;
61
`else
62
gbuf gbuf_i0 ( .CLK(i), .GL(o));
63
`endif
64
endmodule
65
 //ACTEL
66
// sync reset
67 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
68 6 unneback
// output active high global reset sync with two DFFs 
69
`timescale 1 ns/100 ps
70
module vl_sync_rst ( rst_n_i, rst_o, clk);
71
input rst_n_i, clk;
72
output rst_o;
73 18 unneback
reg [1:0] tmp;
74 6 unneback
always @ (posedge clk or negedge rst_n_i)
75
if (!rst_n_i)
76 17 unneback
        tmp <= 2'b11;
77 6 unneback
else
78 33 unneback
        tmp <= {1'b0,tmp[1]};
79 17 unneback
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
80 6 unneback
endmodule
81
// vl_pll
82 32 unneback
///////////////////////////////////////////////////////////////////////////////
83 17 unneback
`timescale 1 ps/1 ps
84 6 unneback
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
85
parameter index = 0;
86
parameter number_of_clk = 1;
87 17 unneback
parameter period_time_0 = 20000;
88
parameter period_time_1 = 20000;
89
parameter period_time_2 = 20000;
90
parameter lock_delay = 2000000;
91 6 unneback
input clk_i, rst_n_i;
92
output lock;
93
output reg [0:number_of_clk-1] clk_o;
94
output [0:number_of_clk-1] rst_o;
95
`ifdef SIM_PLL
96
always
97
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
98
generate if (number_of_clk > 1)
99
always
100
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
101
endgenerate
102
generate if (number_of_clk > 2)
103
always
104
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
105
endgenerate
106
genvar i;
107
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
108
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
109
end
110
endgenerate
111
assign #lock_delay lock = rst_n_i;
112
endmodule
113
`else
114
generate if (number_of_clk==1 & index==0) begin
115
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
116
end
117
endgenerate // index==0
118
generate if (number_of_clk==1 & index==1) begin
119
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
120
end
121
endgenerate // index==1
122
generate if (number_of_clk==1 & index==2) begin
123
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
124
end
125
endgenerate // index==2
126
generate if (number_of_clk==1 & index==3) begin
127
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
128
end
129
endgenerate // index==0
130
generate if (number_of_clk==2 & index==0) begin
131
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
132
end
133
endgenerate // index==0
134
generate if (number_of_clk==2 & index==1) begin
135
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
136
end
137
endgenerate // index==1
138
generate if (number_of_clk==2 & index==2) begin
139
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
140
end
141
endgenerate // index==2
142
generate if (number_of_clk==2 & index==3) begin
143
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
144
end
145
endgenerate // index==0
146
generate if (number_of_clk==3 & index==0) begin
147
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
148
end
149
endgenerate // index==0
150
generate if (number_of_clk==3 & index==1) begin
151
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
152
end
153
endgenerate // index==1
154
generate if (number_of_clk==3 & index==2) begin
155
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
156
end
157
endgenerate // index==2
158
generate if (number_of_clk==3 & index==3) begin
159
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
160
end
161
endgenerate // index==0
162
genvar i;
163
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
164 40 unneback
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
165 6 unneback
end
166
endgenerate
167
endmodule
168
`endif
169 32 unneback
///////////////////////////////////////////////////////////////////////////////
170 6 unneback
 //actel
171
//////////////////////////////////////////////////////////////////////
172
////                                                              ////
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////  Versatile library, registers                                ////
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////                                                              ////
175
////  Description                                                 ////
176
////  Different type of registers                                 ////
177
////                                                              ////
178
////                                                              ////
179
////  To Do:                                                      ////
180
////   - add more different registers                             ////
181
////                                                              ////
182
////  Author(s):                                                  ////
183
////      - Michael Unneback, unneback@opencores.org              ////
184
////        ORSoC AB                                              ////
185
////                                                              ////
186
//////////////////////////////////////////////////////////////////////
187
////                                                              ////
188
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
189
////                                                              ////
190
//// This source file may be used and distributed without         ////
191
//// restriction provided that this copyright statement is not    ////
192
//// removed from the file and that any derivative work contains  ////
193
//// the original copyright notice and the associated disclaimer. ////
194
////                                                              ////
195
//// This source file is free software; you can redistribute it   ////
196
//// and/or modify it under the terms of the GNU Lesser General   ////
197
//// Public License as published by the Free Software Foundation; ////
198
//// either version 2.1 of the License, or (at your option) any   ////
199
//// later version.                                               ////
200
////                                                              ////
201
//// This source is distributed in the hope that it will be       ////
202
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
203
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
204
//// PURPOSE.  See the GNU Lesser General Public License for more ////
205
//// details.                                                     ////
206
////                                                              ////
207
//// You should have received a copy of the GNU Lesser General    ////
208
//// Public License along with this source; if not, download it   ////
209
//// from http://www.opencores.org/lgpl.shtml                     ////
210
////                                                              ////
211
//////////////////////////////////////////////////////////////////////
212 18 unneback
module vl_dff ( d, q, clk, rst);
213 6 unneback
        parameter width = 1;
214
        parameter reset_value = 0;
215
        input [width-1:0] d;
216
        input clk, rst;
217
        output reg [width-1:0] q;
218
        always @ (posedge clk or posedge rst)
219
        if (rst)
220
                q <= reset_value;
221
        else
222
                q <= d;
223
endmodule
224 18 unneback
module vl_dff_array ( d, q, clk, rst);
225 6 unneback
        parameter width = 1;
226
        parameter depth = 2;
227
        parameter reset_value = 1'b0;
228
        input [width-1:0] d;
229
        input clk, rst;
230
        output [width-1:0] q;
231
        reg  [0:depth-1] q_tmp [width-1:0];
232
        integer i;
233
        always @ (posedge clk or posedge rst)
234
        if (rst) begin
235
            for (i=0;i<depth;i=i+1)
236
                q_tmp[i] <= {width{reset_value}};
237
        end else begin
238
            q_tmp[0] <= d;
239
            for (i=1;i<depth;i=i+1)
240
                q_tmp[i] <= q_tmp[i-1];
241
        end
242
    assign q = q_tmp[depth-1];
243
endmodule
244 18 unneback
module vl_dff_ce ( d, ce, q, clk, rst);
245 6 unneback
        parameter width = 1;
246
        parameter reset_value = 0;
247
        input [width-1:0] d;
248
        input ce, clk, rst;
249
        output reg [width-1:0] q;
250
        always @ (posedge clk or posedge rst)
251
        if (rst)
252
                q <= reset_value;
253
        else
254
                if (ce)
255
                        q <= d;
256
endmodule
257 18 unneback
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
258 8 unneback
        parameter width = 1;
259
        parameter reset_value = 0;
260
        input [width-1:0] d;
261 10 unneback
        input ce, clear, clk, rst;
262 8 unneback
        output reg [width-1:0] q;
263
        always @ (posedge clk or posedge rst)
264
        if (rst)
265
            q <= reset_value;
266
        else
267
            if (ce)
268
                if (clear)
269
                    q <= {width{1'b0}};
270
                else
271
                    q <= d;
272
endmodule
273 24 unneback
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
274
        parameter width = 1;
275
        parameter reset_value = 0;
276
        input [width-1:0] d;
277
        input ce, set, clk, rst;
278
        output reg [width-1:0] q;
279
        always @ (posedge clk or posedge rst)
280
        if (rst)
281
            q <= reset_value;
282
        else
283
            if (ce)
284
                if (set)
285
                    q <= {width{1'b1}};
286
                else
287
                    q <= d;
288
endmodule
289 29 unneback
module vl_spr ( sp, r, q, clk, rst);
290
        parameter width = 1;
291
        parameter reset_value = 0;
292
        input sp, r;
293
        output reg q;
294
        input clk, rst;
295
        always @ (posedge clk or posedge rst)
296
        if (rst)
297
            q <= reset_value;
298
        else
299
            if (sp)
300
                q <= 1'b1;
301
            else if (r)
302
                q <= 1'b0;
303
endmodule
304
module vl_srp ( s, rp, q, clk, rst);
305
        parameter width = 1;
306
        parameter reset_value = 0;
307
        input s, rp;
308
        output reg q;
309
        input clk, rst;
310
        always @ (posedge clk or posedge rst)
311
        if (rst)
312
            q <= reset_value;
313
        else
314
            if (rp)
315
                q <= 1'b0;
316
            else if (s)
317
                q <= 1'b1;
318
endmodule
319 18 unneback
module vl_dff_sr ( aclr, aset, clock, data, q);
320 6 unneback
    input         aclr;
321
    input         aset;
322
    input         clock;
323
    input         data;
324
    output reg    q;
325
   always @ (posedge clock or posedge aclr or posedge aset)
326
     if (aclr)
327
       q <= 1'b0;
328
     else if (aset)
329
       q <= 1'b1;
330
     else
331
       q <= data;
332
endmodule
333
// LATCH
334
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
335 40 unneback
module vl_latch ( d, le, q, clk);
336 6 unneback
input d, le;
337 48 unneback
input clk;
338
always @ (le or d)
339
if le
340
    d <= q;
341 6 unneback
endmodule
342 18 unneback
module vl_shreg ( d, q, clk, rst);
343 17 unneback
parameter depth = 10;
344
input d;
345
output q;
346
input clk, rst;
347
reg [1:depth] dffs;
348
always @ (posedge clk or posedge rst)
349
if (rst)
350
    dffs <= {depth{1'b0}};
351
else
352
    dffs <= {d,dffs[1:depth-1]};
353
assign q = dffs[depth];
354
endmodule
355 18 unneback
module vl_shreg_ce ( d, ce, q, clk, rst);
356 17 unneback
parameter depth = 10;
357
input d, ce;
358
output q;
359
input clk, rst;
360
reg [1:depth] dffs;
361
always @ (posedge clk or posedge rst)
362
if (rst)
363
    dffs <= {depth{1'b0}};
364
else
365
    if (ce)
366
        dffs <= {d,dffs[1:depth-1]};
367
assign q = dffs[depth];
368
endmodule
369 18 unneback
module vl_delay ( d, q, clk, rst);
370 15 unneback
parameter depth = 10;
371
input d;
372
output q;
373
input clk, rst;
374
reg [1:depth] dffs;
375
always @ (posedge clk or posedge rst)
376
if (rst)
377
    dffs <= {depth{1'b0}};
378
else
379
    dffs <= {d,dffs[1:depth-1]};
380
assign q = dffs[depth];
381
endmodule
382 18 unneback
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
383 17 unneback
parameter depth = 10;
384
input d;
385
output q, emptyflag;
386
input clk, rst;
387
reg [1:depth] dffs;
388
always @ (posedge clk or posedge rst)
389
if (rst)
390
    dffs <= {depth{1'b0}};
391
else
392
    dffs <= {d,dffs[1:depth-1]};
393
assign q = dffs[depth];
394
assign emptyflag = !(|dffs);
395
endmodule
396 6 unneback
//////////////////////////////////////////////////////////////////////
397
////                                                              ////
398 18 unneback
////  Logic functions                                             ////
399
////                                                              ////
400
////  Description                                                 ////
401
////  Logic functions such as multiplexers                        ////
402
////                                                              ////
403
////                                                              ////
404
////  To Do:                                                      ////
405
////   -                                                          ////
406
////                                                              ////
407
////  Author(s):                                                  ////
408
////      - Michael Unneback, unneback@opencores.org              ////
409
////        ORSoC AB                                              ////
410
////                                                              ////
411
//////////////////////////////////////////////////////////////////////
412
////                                                              ////
413
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
414
////                                                              ////
415
//// This source file may be used and distributed without         ////
416
//// restriction provided that this copyright statement is not    ////
417
//// removed from the file and that any derivative work contains  ////
418
//// the original copyright notice and the associated disclaimer. ////
419
////                                                              ////
420
//// This source file is free software; you can redistribute it   ////
421
//// and/or modify it under the terms of the GNU Lesser General   ////
422
//// Public License as published by the Free Software Foundation; ////
423
//// either version 2.1 of the License, or (at your option) any   ////
424
//// later version.                                               ////
425
////                                                              ////
426
//// This source is distributed in the hope that it will be       ////
427
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
428
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
429
//// PURPOSE.  See the GNU Lesser General Public License for more ////
430
//// details.                                                     ////
431
////                                                              ////
432
//// You should have received a copy of the GNU Lesser General    ////
433
//// Public License along with this source; if not, download it   ////
434
//// from http://www.opencores.org/lgpl.shtml                     ////
435
////                                                              ////
436
//////////////////////////////////////////////////////////////////////
437 36 unneback
module vl_mux_andor ( a, sel, dout);
438
parameter width = 32;
439
parameter nr_of_ports = 4;
440
input [nr_of_ports*width-1:0] a;
441
input [nr_of_ports-1:0] sel;
442
output reg [width-1:0] dout;
443 38 unneback
integer i,j;
444 36 unneback
always @ (a, sel)
445
begin
446
    dout = a[width-1:0] & {width{sel[0]}};
447 42 unneback
    for (i=1;i<nr_of_ports;i=i+1)
448
        for (j=0;j<width;j=j+1)
449
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
450 36 unneback
end
451
endmodule
452 34 unneback
module vl_mux2_andor ( a1, a0, sel, dout);
453
parameter width = 32;
454 35 unneback
localparam nr_of_ports = 2;
455 34 unneback
input [width-1:0] a1, a0;
456
input [nr_of_ports-1:0] sel;
457
output [width-1:0] dout;
458 36 unneback
vl_mux_andor
459 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
460 36 unneback
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
461 34 unneback
endmodule
462
module vl_mux3_andor ( a2, a1, a0, sel, dout);
463
parameter width = 32;
464 35 unneback
localparam nr_of_ports = 3;
465 34 unneback
input [width-1:0] a2, a1, a0;
466
input [nr_of_ports-1:0] sel;
467
output [width-1:0] dout;
468 36 unneback
vl_mux_andor
469 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
470 36 unneback
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
471 34 unneback
endmodule
472 18 unneback
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
473
parameter width = 32;
474 35 unneback
localparam nr_of_ports = 4;
475 18 unneback
input [width-1:0] a3, a2, a1, a0;
476
input [nr_of_ports-1:0] sel;
477 22 unneback
output [width-1:0] dout;
478 36 unneback
vl_mux_andor
479 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
480 36 unneback
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
481 18 unneback
endmodule
482
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
483
parameter width = 32;
484 35 unneback
localparam nr_of_ports = 5;
485 18 unneback
input [width-1:0] a4, a3, a2, a1, a0;
486
input [nr_of_ports-1:0] sel;
487 22 unneback
output [width-1:0] dout;
488 36 unneback
vl_mux_andor
489 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
490 36 unneback
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
491 18 unneback
endmodule
492
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
493
parameter width = 32;
494 35 unneback
localparam nr_of_ports = 6;
495 18 unneback
input [width-1:0] a5, a4, a3, a2, a1, a0;
496
input [nr_of_ports-1:0] sel;
497 22 unneback
output [width-1:0] dout;
498 36 unneback
vl_mux_andor
499 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
500 36 unneback
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
501 18 unneback
endmodule
502 43 unneback
module vl_parity_generate (data, parity);
503
parameter word_size = 32;
504
parameter chunk_size = 8;
505
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
506
input [word_size-1:0] data;
507
output reg [word_size/chunk_size-1:0] parity;
508
integer i,j;
509
always @ (data)
510
for (i=0;i<word_size/chunk_size;i=i+1) begin
511
    parity[i] = parity_type;
512
    for (j=0;j<chunk_size;j=j+1) begin
513 46 unneback
        parity[i] = data[i*chunk_size+j] ^ parity[i];
514 43 unneback
    end
515
end
516
endmodule
517
module vl_parity_check( data, parity, parity_error);
518
parameter word_size = 32;
519
parameter chunk_size = 8;
520
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
521
input [word_size-1:0] data;
522
input [word_size/chunk_size-1:0] parity;
523
output parity_error;
524 44 unneback
reg [word_size/chunk_size-1:0] error_flag;
525 43 unneback
integer i,j;
526
always @ (data or parity)
527
for (i=0;i<word_size/chunk_size;i=i+1) begin
528
    error_flag[i] = parity[i] ^ parity_type;
529
    for (j=0;j<chunk_size;j=j+1) begin
530 46 unneback
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
531 43 unneback
    end
532
end
533
assign parity_error = |error_flag;
534
endmodule
535 18 unneback
//////////////////////////////////////////////////////////////////////
536
////                                                              ////
537 44 unneback
////  IO functions                                                ////
538
////                                                              ////
539
////  Description                                                 ////
540
////  IO functions such as IOB flip-flops                         ////
541
////                                                              ////
542
////                                                              ////
543
////  To Do:                                                      ////
544
////   -                                                          ////
545
////                                                              ////
546
////  Author(s):                                                  ////
547
////      - Michael Unneback, unneback@opencores.org              ////
548
////        ORSoC AB                                              ////
549
////                                                              ////
550
//////////////////////////////////////////////////////////////////////
551
////                                                              ////
552
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
553
////                                                              ////
554
//// This source file may be used and distributed without         ////
555
//// restriction provided that this copyright statement is not    ////
556
//// removed from the file and that any derivative work contains  ////
557
//// the original copyright notice and the associated disclaimer. ////
558
////                                                              ////
559
//// This source file is free software; you can redistribute it   ////
560
//// and/or modify it under the terms of the GNU Lesser General   ////
561
//// Public License as published by the Free Software Foundation; ////
562
//// either version 2.1 of the License, or (at your option) any   ////
563
//// later version.                                               ////
564
////                                                              ////
565
//// This source is distributed in the hope that it will be       ////
566
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
567
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
568
//// PURPOSE.  See the GNU Lesser General Public License for more ////
569
//// details.                                                     ////
570
////                                                              ////
571
//// You should have received a copy of the GNU Lesser General    ////
572
//// Public License along with this source; if not, download it   ////
573
//// from http://www.opencores.org/lgpl.shtml                     ////
574
////                                                              ////
575
//////////////////////////////////////////////////////////////////////
576 45 unneback
`timescale 1ns/1ns
577 44 unneback
module vl_o_dff (d_i, o_pad, clk, rst);
578
parameter width = 1;
579 45 unneback
parameter reset_value = {width{1'b0}};
580
input  [width-1:0]  d_i;
581 44 unneback
output [width-1:0] o_pad;
582
input clk, rst;
583
wire [width-1:0] d_i_int /*synthesis syn_keep = 1*/;
584 45 unneback
reg  [width-1:0] o_pad_int;
585 44 unneback
assign d_i_int = d_i;
586
genvar i;
587 45 unneback
generate
588 44 unneback
for (i=0;i<width;i=i+1) begin
589
    always @ (posedge clk or posedge rst)
590
    if (rst)
591 45 unneback
        o_pad_int[i] <= reset_value[i];
592 44 unneback
    else
593 45 unneback
        o_pad_int[i] <= d_i_int[i];
594
    assign #1 o_pad[i] = o_pad_int[i];
595 44 unneback
end
596
endgenerate
597
endmodule
598 45 unneback
`timescale 1ns/1ns
599 44 unneback
module vl_io_dff_oe ( d_i, d_o, oe, io_pad, clk, rst);
600
parameter width = 1;
601
input  [width-1:0] d_o;
602
output reg [width-1:0] d_i;
603
input oe;
604
inout [width-1:0] io_pad;
605
input clk, rst;
606
wire [width-1:0] oe_d /*synthesis syn_keep = 1*/;
607
reg [width-1:0] oe_q;
608
reg [width-1:0] d_o_q;
609
assign oe_d = {width{oe}};
610
genvar i;
611
generate
612
for (i=0;i<width;i=i+1) begin
613
    always @ (posedge clk or posedge rst)
614
    if (rst)
615
        oe_q[i] <= 1'b0;
616
    else
617
        oe_q[i] <= oe_d[i];
618
    always @ (posedge clk or posedge rst)
619
    if (rst)
620
        d_o_q[i] <= 1'b0;
621
    else
622
        d_o_q[i] <= d_o[i];
623
    always @ (posedge clk or posedge rst)
624
    if (rst)
625
        d_i[i] <= 1'b0;
626
    else
627
        d_i[i] <= io_pad[i];
628 45 unneback
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
629 44 unneback
end
630
endgenerate
631
endmodule
632
//////////////////////////////////////////////////////////////////////
633
////                                                              ////
634 6 unneback
////  Versatile counter                                           ////
635
////                                                              ////
636
////  Description                                                 ////
637
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
638
////  counter                                                     ////
639
////                                                              ////
640
////  To Do:                                                      ////
641
////   - add LFSR with more taps                                  ////
642
////                                                              ////
643
////  Author(s):                                                  ////
644
////      - Michael Unneback, unneback@opencores.org              ////
645
////        ORSoC AB                                              ////
646
////                                                              ////
647
//////////////////////////////////////////////////////////////////////
648
////                                                              ////
649
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
650
////                                                              ////
651
//// This source file may be used and distributed without         ////
652
//// restriction provided that this copyright statement is not    ////
653
//// removed from the file and that any derivative work contains  ////
654
//// the original copyright notice and the associated disclaimer. ////
655
////                                                              ////
656
//// This source file is free software; you can redistribute it   ////
657
//// and/or modify it under the terms of the GNU Lesser General   ////
658
//// Public License as published by the Free Software Foundation; ////
659
//// either version 2.1 of the License, or (at your option) any   ////
660
//// later version.                                               ////
661
////                                                              ////
662
//// This source is distributed in the hope that it will be       ////
663
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
664
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
665
//// PURPOSE.  See the GNU Lesser General Public License for more ////
666
//// details.                                                     ////
667
////                                                              ////
668
//// You should have received a copy of the GNU Lesser General    ////
669
//// Public License along with this source; if not, download it   ////
670
//// from http://www.opencores.org/lgpl.shtml                     ////
671
////                                                              ////
672
//////////////////////////////////////////////////////////////////////
673
// binary counter
674 40 unneback
module vl_cnt_bin_ce (
675
 cke, q, rst, clk);
676 22 unneback
   parameter length = 4;
677 6 unneback
   input cke;
678
   output [length:1] q;
679
   input rst;
680
   input clk;
681
   parameter clear_value = 0;
682
   parameter set_value = 1;
683
   parameter wrap_value = 0;
684
   parameter level1_value = 15;
685
   reg  [length:1] qi;
686
   wire [length:1] q_next;
687
   assign q_next = qi + {{length-1{1'b0}},1'b1};
688
   always @ (posedge clk or posedge rst)
689
     if (rst)
690
       qi <= {length{1'b0}};
691
     else
692
     if (cke)
693
       qi <= q_next;
694
   assign q = qi;
695
endmodule
696
//////////////////////////////////////////////////////////////////////
697
////                                                              ////
698
////  Versatile counter                                           ////
699
////                                                              ////
700
////  Description                                                 ////
701
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
702
////  counter                                                     ////
703
////                                                              ////
704
////  To Do:                                                      ////
705
////   - add LFSR with more taps                                  ////
706
////                                                              ////
707
////  Author(s):                                                  ////
708
////      - Michael Unneback, unneback@opencores.org              ////
709
////        ORSoC AB                                              ////
710
////                                                              ////
711
//////////////////////////////////////////////////////////////////////
712
////                                                              ////
713
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
714
////                                                              ////
715
//// This source file may be used and distributed without         ////
716
//// restriction provided that this copyright statement is not    ////
717
//// removed from the file and that any derivative work contains  ////
718
//// the original copyright notice and the associated disclaimer. ////
719
////                                                              ////
720
//// This source file is free software; you can redistribute it   ////
721
//// and/or modify it under the terms of the GNU Lesser General   ////
722
//// Public License as published by the Free Software Foundation; ////
723
//// either version 2.1 of the License, or (at your option) any   ////
724
//// later version.                                               ////
725
////                                                              ////
726
//// This source is distributed in the hope that it will be       ////
727
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
728
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
729
//// PURPOSE.  See the GNU Lesser General Public License for more ////
730
//// details.                                                     ////
731
////                                                              ////
732
//// You should have received a copy of the GNU Lesser General    ////
733
//// Public License along with this source; if not, download it   ////
734
//// from http://www.opencores.org/lgpl.shtml                     ////
735
////                                                              ////
736
//////////////////////////////////////////////////////////////////////
737
// binary counter
738 40 unneback
module vl_cnt_bin_ce_rew_zq_l1 (
739
 cke, rew, zq, level1, rst, clk);
740 6 unneback
   parameter length = 4;
741
   input cke;
742
   input rew;
743 25 unneback
   output reg zq;
744
   output reg level1;
745
   input rst;
746
   input clk;
747
   parameter clear_value = 0;
748
   parameter set_value = 1;
749
   parameter wrap_value = 1;
750
   parameter level1_value = 15;
751 29 unneback
   wire clear;
752 30 unneback
   assign clear = 1'b0;
753 25 unneback
   reg  [length:1] qi;
754
   wire  [length:1] q_next, q_next_fw, q_next_rew;
755
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
756
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
757
   assign q_next = rew ? q_next_rew : q_next_fw;
758
   always @ (posedge clk or posedge rst)
759
     if (rst)
760
       qi <= {length{1'b0}};
761
     else
762
     if (cke)
763
       qi <= q_next;
764
   always @ (posedge clk or posedge rst)
765
     if (rst)
766
       zq <= 1'b1;
767
     else
768
     if (cke)
769
       zq <= q_next == {length{1'b0}};
770
    always @ (posedge clk or posedge rst)
771
    if (rst)
772
        level1 <= 1'b0;
773
    else
774
    if (cke)
775 29 unneback
    if (clear)
776
        level1 <= 1'b0;
777
    else if (q_next == level1_value)
778 25 unneback
        level1 <= 1'b1;
779
    else if (qi == level1_value & rew)
780
        level1 <= 1'b0;
781
endmodule
782
//////////////////////////////////////////////////////////////////////
783
////                                                              ////
784
////  Versatile counter                                           ////
785
////                                                              ////
786
////  Description                                                 ////
787
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
788
////  counter                                                     ////
789
////                                                              ////
790
////  To Do:                                                      ////
791
////   - add LFSR with more taps                                  ////
792
////                                                              ////
793
////  Author(s):                                                  ////
794
////      - Michael Unneback, unneback@opencores.org              ////
795
////        ORSoC AB                                              ////
796
////                                                              ////
797
//////////////////////////////////////////////////////////////////////
798
////                                                              ////
799
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
800
////                                                              ////
801
//// This source file may be used and distributed without         ////
802
//// restriction provided that this copyright statement is not    ////
803
//// removed from the file and that any derivative work contains  ////
804
//// the original copyright notice and the associated disclaimer. ////
805
////                                                              ////
806
//// This source file is free software; you can redistribute it   ////
807
//// and/or modify it under the terms of the GNU Lesser General   ////
808
//// Public License as published by the Free Software Foundation; ////
809
//// either version 2.1 of the License, or (at your option) any   ////
810
//// later version.                                               ////
811
////                                                              ////
812
//// This source is distributed in the hope that it will be       ////
813
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
814
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
815
//// PURPOSE.  See the GNU Lesser General Public License for more ////
816
//// details.                                                     ////
817
////                                                              ////
818
//// You should have received a copy of the GNU Lesser General    ////
819
//// Public License along with this source; if not, download it   ////
820
//// from http://www.opencores.org/lgpl.shtml                     ////
821
////                                                              ////
822
//////////////////////////////////////////////////////////////////////
823
// binary counter
824 40 unneback
module vl_cnt_bin_ce_rew_q_zq_l1 (
825
 cke, rew, q, zq, level1, rst, clk);
826 25 unneback
   parameter length = 4;
827
   input cke;
828
   input rew;
829
   output [length:1] q;
830
   output reg zq;
831
   output reg level1;
832
   input rst;
833
   input clk;
834
   parameter clear_value = 0;
835
   parameter set_value = 1;
836
   parameter wrap_value = 1;
837
   parameter level1_value = 15;
838 29 unneback
   wire clear;
839 30 unneback
   assign clear = 1'b0;
840 25 unneback
   reg  [length:1] qi;
841
   wire  [length:1] q_next, q_next_fw, q_next_rew;
842
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
843
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
844
   assign q_next = rew ? q_next_rew : q_next_fw;
845
   always @ (posedge clk or posedge rst)
846
     if (rst)
847
       qi <= {length{1'b0}};
848
     else
849
     if (cke)
850
       qi <= q_next;
851
   assign q = qi;
852
   always @ (posedge clk or posedge rst)
853
     if (rst)
854
       zq <= 1'b1;
855
     else
856
     if (cke)
857
       zq <= q_next == {length{1'b0}};
858
    always @ (posedge clk or posedge rst)
859
    if (rst)
860
        level1 <= 1'b0;
861
    else
862
    if (cke)
863 29 unneback
    if (clear)
864
        level1 <= 1'b0;
865
    else if (q_next == level1_value)
866 25 unneback
        level1 <= 1'b1;
867
    else if (qi == level1_value & rew)
868
        level1 <= 1'b0;
869
endmodule
870
//////////////////////////////////////////////////////////////////////
871
////                                                              ////
872
////  Versatile counter                                           ////
873
////                                                              ////
874
////  Description                                                 ////
875
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
876
////  counter                                                     ////
877
////                                                              ////
878
////  To Do:                                                      ////
879
////   - add LFSR with more taps                                  ////
880
////                                                              ////
881
////  Author(s):                                                  ////
882
////      - Michael Unneback, unneback@opencores.org              ////
883
////        ORSoC AB                                              ////
884
////                                                              ////
885
//////////////////////////////////////////////////////////////////////
886
////                                                              ////
887
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
888
////                                                              ////
889
//// This source file may be used and distributed without         ////
890
//// restriction provided that this copyright statement is not    ////
891
//// removed from the file and that any derivative work contains  ////
892
//// the original copyright notice and the associated disclaimer. ////
893
////                                                              ////
894
//// This source file is free software; you can redistribute it   ////
895
//// and/or modify it under the terms of the GNU Lesser General   ////
896
//// Public License as published by the Free Software Foundation; ////
897
//// either version 2.1 of the License, or (at your option) any   ////
898
//// later version.                                               ////
899
////                                                              ////
900
//// This source is distributed in the hope that it will be       ////
901
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
902
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
903
//// PURPOSE.  See the GNU Lesser General Public License for more ////
904
//// details.                                                     ////
905
////                                                              ////
906
//// You should have received a copy of the GNU Lesser General    ////
907
//// Public License along with this source; if not, download it   ////
908
//// from http://www.opencores.org/lgpl.shtml                     ////
909
////                                                              ////
910
//////////////////////////////////////////////////////////////////////
911 6 unneback
// GRAY counter
912 40 unneback
module vl_cnt_gray_ce_bin (
913
 cke, q, q_bin, rst, clk);
914 6 unneback
   parameter length = 4;
915
   input cke;
916
   output reg [length:1] q;
917
   output [length:1] q_bin;
918
   input rst;
919
   input clk;
920
   parameter clear_value = 0;
921
   parameter set_value = 1;
922
   parameter wrap_value = 8;
923
   parameter level1_value = 15;
924
   reg  [length:1] qi;
925
   wire [length:1] q_next;
926
   assign q_next = qi + {{length-1{1'b0}},1'b1};
927
   always @ (posedge clk or posedge rst)
928
     if (rst)
929
       qi <= {length{1'b0}};
930
     else
931
     if (cke)
932
       qi <= q_next;
933
   always @ (posedge clk or posedge rst)
934
     if (rst)
935
       q <= {length{1'b0}};
936
     else
937
       if (cke)
938
         q <= (q_next>>1) ^ q_next;
939
   assign q_bin = qi;
940
endmodule
941
//////////////////////////////////////////////////////////////////////
942
////                                                              ////
943
////  Versatile library, counters                                 ////
944
////                                                              ////
945
////  Description                                                 ////
946
////  counters                                                    ////
947
////                                                              ////
948
////                                                              ////
949
////  To Do:                                                      ////
950
////   - add more counters                                        ////
951
////                                                              ////
952
////  Author(s):                                                  ////
953
////      - Michael Unneback, unneback@opencores.org              ////
954
////        ORSoC AB                                              ////
955
////                                                              ////
956
//////////////////////////////////////////////////////////////////////
957
////                                                              ////
958
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
959
////                                                              ////
960
//// This source file may be used and distributed without         ////
961
//// restriction provided that this copyright statement is not    ////
962
//// removed from the file and that any derivative work contains  ////
963
//// the original copyright notice and the associated disclaimer. ////
964
////                                                              ////
965
//// This source file is free software; you can redistribute it   ////
966
//// and/or modify it under the terms of the GNU Lesser General   ////
967
//// Public License as published by the Free Software Foundation; ////
968
//// either version 2.1 of the License, or (at your option) any   ////
969
//// later version.                                               ////
970
////                                                              ////
971
//// This source is distributed in the hope that it will be       ////
972
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
973
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
974
//// PURPOSE.  See the GNU Lesser General Public License for more ////
975
//// details.                                                     ////
976
////                                                              ////
977
//// You should have received a copy of the GNU Lesser General    ////
978
//// Public License along with this source; if not, download it   ////
979
//// from http://www.opencores.org/lgpl.shtml                     ////
980
////                                                              ////
981
//////////////////////////////////////////////////////////////////////
982 18 unneback
module vl_cnt_shreg_wrap ( q, rst, clk);
983 6 unneback
   parameter length = 4;
984
   output reg [0:length-1] q;
985
   input rst;
986
   input clk;
987
    always @ (posedge clk or posedge rst)
988
    if (rst)
989
        q <= {1'b1,{length-1{1'b0}}};
990
    else
991
        q <= {q[length-1],q[0:length-2]};
992
endmodule
993 18 unneback
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
994 6 unneback
   parameter length = 4;
995
   input cke;
996
   output reg [0:length-1] q;
997
   input rst;
998
   input clk;
999
    always @ (posedge clk or posedge rst)
1000
    if (rst)
1001
        q <= {1'b1,{length-1{1'b0}}};
1002
    else
1003
        if (cke)
1004
            q <= {q[length-1],q[0:length-2]};
1005
endmodule
1006 18 unneback
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
1007 6 unneback
   parameter length = 4;
1008
   input cke, clear;
1009
   output reg [0:length-1] q;
1010
   input rst;
1011
   input clk;
1012
    always @ (posedge clk or posedge rst)
1013
    if (rst)
1014
        q <= {1'b1,{length-1{1'b0}}};
1015
    else
1016
        if (cke)
1017
            if (clear)
1018
                q <= {1'b1,{length-1{1'b0}}};
1019
            else
1020
                q <= q >> 1;
1021
endmodule
1022 18 unneback
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
1023 6 unneback
   parameter length = 4;
1024
   input cke, clear;
1025
   output reg [0:length-1] q;
1026
   input rst;
1027
   input clk;
1028
    always @ (posedge clk or posedge rst)
1029
    if (rst)
1030
        q <= {1'b1,{length-1{1'b0}}};
1031
    else
1032
        if (cke)
1033
            if (clear)
1034
                q <= {1'b1,{length-1{1'b0}}};
1035
            else
1036
            q <= {q[length-1],q[0:length-2]};
1037
endmodule
1038
//////////////////////////////////////////////////////////////////////
1039
////                                                              ////
1040
////  Versatile library, memories                                 ////
1041
////                                                              ////
1042
////  Description                                                 ////
1043
////  memories                                                    ////
1044
////                                                              ////
1045
////                                                              ////
1046
////  To Do:                                                      ////
1047
////   - add more memory types                                    ////
1048
////                                                              ////
1049
////  Author(s):                                                  ////
1050
////      - Michael Unneback, unneback@opencores.org              ////
1051
////        ORSoC AB                                              ////
1052
////                                                              ////
1053
//////////////////////////////////////////////////////////////////////
1054
////                                                              ////
1055
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1056
////                                                              ////
1057
//// This source file may be used and distributed without         ////
1058
//// restriction provided that this copyright statement is not    ////
1059
//// removed from the file and that any derivative work contains  ////
1060
//// the original copyright notice and the associated disclaimer. ////
1061
////                                                              ////
1062
//// This source file is free software; you can redistribute it   ////
1063
//// and/or modify it under the terms of the GNU Lesser General   ////
1064
//// Public License as published by the Free Software Foundation; ////
1065
//// either version 2.1 of the License, or (at your option) any   ////
1066
//// later version.                                               ////
1067
////                                                              ////
1068
//// This source is distributed in the hope that it will be       ////
1069
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1070
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1071
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1072
//// details.                                                     ////
1073
////                                                              ////
1074
//// You should have received a copy of the GNU Lesser General    ////
1075
//// Public License along with this source; if not, download it   ////
1076
//// from http://www.opencores.org/lgpl.shtml                     ////
1077
////                                                              ////
1078
//////////////////////////////////////////////////////////////////////
1079
/// ROM
1080 7 unneback
module vl_rom_init ( adr, q, clk);
1081
   parameter data_width = 32;
1082
   parameter addr_width = 8;
1083
   input [(addr_width-1):0]       adr;
1084
   output reg [(data_width-1):0] q;
1085
   input                         clk;
1086
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
1087
   parameter memory_file = "vl_rom.vmem";
1088
   initial
1089
     begin
1090
        $readmemh(memory_file, rom);
1091
     end
1092
   always @ (posedge clk)
1093
     q <= rom[adr];
1094
endmodule
1095 6 unneback
// Single port RAM
1096
module vl_ram ( d, adr, we, q, clk);
1097
   parameter data_width = 32;
1098
   parameter addr_width = 8;
1099
   input [(data_width-1):0]      d;
1100
   input [(addr_width-1):0]       adr;
1101
   input                         we;
1102 7 unneback
   output reg [(data_width-1):0] q;
1103 6 unneback
   input                         clk;
1104
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
1105 7 unneback
   parameter init = 0;
1106
   parameter memory_file = "vl_ram.vmem";
1107
   generate if (init) begin : init_mem
1108
   initial
1109
     begin
1110
        $readmemh(memory_file, ram);
1111
     end
1112
   end
1113
   endgenerate
1114 6 unneback
   always @ (posedge clk)
1115
   begin
1116
   if (we)
1117
     ram[adr] <= d;
1118
   q <= ram[adr];
1119
   end
1120
endmodule
1121 7 unneback
module vl_ram_be ( d, adr, be, we, q, clk);
1122
   parameter data_width = 32;
1123
   parameter addr_width = 8;
1124
   input [(data_width-1):0]      d;
1125
   input [(addr_width-1):0]       adr;
1126
   input [(addr_width/4)-1:0]    be;
1127
   input                         we;
1128
   output reg [(data_width-1):0] q;
1129
   input                         clk;
1130
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
1131
   parameter init = 0;
1132
   parameter memory_file = "vl_ram.vmem";
1133
   generate if (init) begin : init_mem
1134
   initial
1135
     begin
1136
        $readmemh(memory_file, ram);
1137
     end
1138
   end
1139
   endgenerate
1140
   genvar i;
1141
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
1142
      always @ (posedge clk)
1143
      if (we & be[i])
1144
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
1145
   end
1146
   endgenerate
1147
   always @ (posedge clk)
1148
      q <= ram[adr];
1149
endmodule
1150 48 unneback
        // ACTEL FPGA should not use logic to handle rw collision
1151 7 unneback
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1152 6 unneback
   parameter data_width = 32;
1153
   parameter addr_width = 8;
1154
   input [(data_width-1):0]      d_a;
1155
   input [(addr_width-1):0]       adr_a;
1156
   input [(addr_width-1):0]       adr_b;
1157
   input                         we_a;
1158
   output [(data_width-1):0]      q_b;
1159
   input                         clk_a, clk_b;
1160
   reg [(addr_width-1):0]         adr_b_reg;
1161
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
1162 7 unneback
   parameter init = 0;
1163
   parameter memory_file = "vl_ram.vmem";
1164
   generate if (init) begin : init_mem
1165
   initial
1166
     begin
1167
        $readmemh(memory_file, ram);
1168
     end
1169
   end
1170
   endgenerate
1171 6 unneback
   always @ (posedge clk_a)
1172
   if (we_a)
1173
     ram[adr_a] <= d_a;
1174
   always @ (posedge clk_b)
1175
   adr_b_reg <= adr_b;
1176
   assign q_b = ram[adr_b_reg];
1177
endmodule
1178 7 unneback
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1179 6 unneback
   parameter data_width = 32;
1180
   parameter addr_width = 8;
1181
   input [(data_width-1):0]      d_a;
1182
   input [(addr_width-1):0]       adr_a;
1183
   input [(addr_width-1):0]       adr_b;
1184
   input                         we_a;
1185
   output [(data_width-1):0]      q_b;
1186
   output reg [(data_width-1):0] q_a;
1187
   input                         clk_a, clk_b;
1188
   reg [(data_width-1):0]         q_b;
1189
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
1190 7 unneback
   parameter init = 0;
1191
   parameter memory_file = "vl_ram.vmem";
1192
   generate if (init) begin : init_mem
1193
   initial
1194
     begin
1195
        $readmemh(memory_file, ram);
1196
     end
1197
   end
1198
   endgenerate
1199 6 unneback
   always @ (posedge clk_a)
1200
     begin
1201
        q_a <= ram[adr_a];
1202
        if (we_a)
1203
             ram[adr_a] <= d_a;
1204
     end
1205
   always @ (posedge clk_b)
1206
          q_b <= ram[adr_b];
1207
endmodule
1208 7 unneback
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
1209 6 unneback
   parameter data_width = 32;
1210
   parameter addr_width = 8;
1211
   input [(data_width-1):0]      d_a;
1212
   input [(addr_width-1):0]       adr_a;
1213
   input [(addr_width-1):0]       adr_b;
1214
   input                         we_a;
1215
   output [(data_width-1):0]      q_b;
1216
   input [(data_width-1):0]       d_b;
1217
   output reg [(data_width-1):0] q_a;
1218
   input                         we_b;
1219
   input                         clk_a, clk_b;
1220
   reg [(data_width-1):0]         q_b;
1221
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
1222 7 unneback
   parameter init = 0;
1223
   parameter memory_file = "vl_ram.vmem";
1224
   generate if (init) begin : init_mem
1225
   initial
1226
     begin
1227
        $readmemh(memory_file, ram);
1228
     end
1229
   end
1230
   endgenerate
1231 6 unneback
   always @ (posedge clk_a)
1232
     begin
1233
        q_a <= ram[adr_a];
1234
        if (we_a)
1235
             ram[adr_a] <= d_a;
1236
     end
1237
   always @ (posedge clk_b)
1238
     begin
1239
        q_b <= ram[adr_b];
1240
        if (we_b)
1241
          ram[adr_b] <= d_b;
1242
     end
1243
endmodule
1244
// Content addresable memory, CAM
1245
// FIFO
1246 25 unneback
module vl_fifo_1r1w_fill_level_sync (
1247
    d, wr, fifo_full,
1248
    q, rd, fifo_empty,
1249
    fill_level,
1250
    clk, rst
1251
    );
1252
parameter data_width = 18;
1253
parameter addr_width = 4;
1254
// write side
1255
input  [data_width-1:0] d;
1256
input                   wr;
1257
output                  fifo_full;
1258
// read side
1259
output [data_width-1:0] q;
1260
input                   rd;
1261
output                  fifo_empty;
1262
// common
1263
output [addr_width:0]   fill_level;
1264
input rst, clk;
1265
wire [addr_width:1] wadr, radr;
1266
vl_cnt_bin_ce
1267
    # ( .length(addr_width))
1268
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
1269
vl_cnt_bin_ce
1270
    # (.length(addr_width))
1271
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
1272
vl_dpram_1r1w
1273
    # (.data_width(data_width), .addr_width(addr_width))
1274
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
1275 31 unneback
vl_cnt_bin_ce_rew_q_zq_l1
1276 27 unneback
    # (.length(addr_width+1), .level1_value(1<<addr_width))
1277 25 unneback
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
1278
endmodule
1279 27 unneback
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
1280
// RAM is supposed to be larger than the two FIFOs
1281
// LFSR counters used adr pointers
1282
module vl_fifo_2r2w_sync_simplex (
1283
    // a side
1284
    a_d, a_wr, a_fifo_full,
1285
    a_q, a_rd, a_fifo_empty,
1286
    a_fill_level,
1287
    // b side
1288
    b_d, b_wr, b_fifo_full,
1289
    b_q, b_rd, b_fifo_empty,
1290
    b_fill_level,
1291
    // common
1292
    clk, rst
1293
    );
1294
parameter data_width = 8;
1295
parameter addr_width = 5;
1296
parameter fifo_full_level = (1<<addr_width)-1;
1297
// a side
1298
input  [data_width-1:0] a_d;
1299
input                   a_wr;
1300
output                  a_fifo_full;
1301
output [data_width-1:0] a_q;
1302
input                   a_rd;
1303
output                  a_fifo_empty;
1304
output [addr_width-1:0] a_fill_level;
1305
// b side
1306
input  [data_width-1:0] b_d;
1307
input                   b_wr;
1308
output                  b_fifo_full;
1309
output [data_width-1:0] b_q;
1310
input                   b_rd;
1311
output                  b_fifo_empty;
1312
output [addr_width-1:0] b_fill_level;
1313
input                   clk;
1314
input                   rst;
1315
// adr_gen
1316
wire [addr_width:1] a_wadr, a_radr;
1317
wire [addr_width:1] b_wadr, b_radr;
1318
// dpram
1319
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
1320
vl_cnt_lfsr_ce
1321
    # ( .length(addr_width))
1322
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
1323
vl_cnt_lfsr_ce
1324
    # (.length(addr_width))
1325
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
1326
vl_cnt_lfsr_ce
1327
    # ( .length(addr_width))
1328
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
1329
vl_cnt_lfsr_ce
1330
    # (.length(addr_width))
1331
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
1332
// mux read or write adr to DPRAM
1333
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
1334
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
1335
vl_dpram_2r2w
1336
    # (.data_width(data_width), .addr_width(addr_width+1))
1337
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
1338
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
1339
vl_cnt_bin_ce_rew_zq_l1
1340 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
1341 27 unneback
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
1342
vl_cnt_bin_ce_rew_zq_l1
1343 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
1344 27 unneback
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
1345
endmodule
1346 6 unneback
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
1347 11 unneback
   parameter addr_width = 4;
1348
   parameter N = addr_width-1;
1349 6 unneback
   parameter Q1 = 2'b00;
1350
   parameter Q2 = 2'b01;
1351
   parameter Q3 = 2'b11;
1352
   parameter Q4 = 2'b10;
1353
   parameter going_empty = 1'b0;
1354
   parameter going_full  = 1'b1;
1355
   input [N:0]  wptr, rptr;
1356 14 unneback
   output       fifo_empty;
1357 6 unneback
   output       fifo_full;
1358
   input        wclk, rclk, rst;
1359
   wire direction;
1360
   reg  direction_set, direction_clr;
1361
   wire async_empty, async_full;
1362
   wire fifo_full2;
1363 14 unneback
   wire fifo_empty2;
1364 6 unneback
   // direction_set
1365
   always @ (wptr[N:N-1] or rptr[N:N-1])
1366
     case ({wptr[N:N-1],rptr[N:N-1]})
1367
       {Q1,Q2} : direction_set <= 1'b1;
1368
       {Q2,Q3} : direction_set <= 1'b1;
1369
       {Q3,Q4} : direction_set <= 1'b1;
1370
       {Q4,Q1} : direction_set <= 1'b1;
1371
       default : direction_set <= 1'b0;
1372
     endcase
1373
   // direction_clear
1374
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
1375
     if (rst)
1376
       direction_clr <= 1'b1;
1377
     else
1378
       case ({wptr[N:N-1],rptr[N:N-1]})
1379
         {Q2,Q1} : direction_clr <= 1'b1;
1380
         {Q3,Q2} : direction_clr <= 1'b1;
1381
         {Q4,Q3} : direction_clr <= 1'b1;
1382
         {Q1,Q4} : direction_clr <= 1'b1;
1383
         default : direction_clr <= 1'b0;
1384
       endcase
1385 18 unneback
    vl_dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
1386 6 unneback
   assign async_empty = (wptr == rptr) && (direction==going_empty);
1387
   assign async_full  = (wptr == rptr) && (direction==going_full);
1388 18 unneback
    vl_dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
1389
    vl_dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
1390 6 unneback
/*
1391
   always @ (posedge wclk or posedge rst or posedge async_full)
1392
     if (rst)
1393
       {fifo_full, fifo_full2} <= 2'b00;
1394
     else if (async_full)
1395
       {fifo_full, fifo_full2} <= 2'b11;
1396
     else
1397
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
1398
*/
1399 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
1400 6 unneback
     if (async_empty)
1401
       {fifo_empty, fifo_empty2} <= 2'b11;
1402
     else
1403 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
1404 18 unneback
    vl_dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
1405
    vl_dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
1406 27 unneback
endmodule // async_compb
1407 6 unneback
module vl_fifo_1r1w_async (
1408
    d, wr, fifo_full, wr_clk, wr_rst,
1409
    q, rd, fifo_empty, rd_clk, rd_rst
1410
    );
1411
parameter data_width = 18;
1412
parameter addr_width = 4;
1413
// write side
1414
input  [data_width-1:0] d;
1415
input                   wr;
1416
output                  fifo_full;
1417
input                   wr_clk;
1418
input                   wr_rst;
1419
// read side
1420
output [data_width-1:0] q;
1421
input                   rd;
1422
output                  fifo_empty;
1423
input                   rd_clk;
1424
input                   rd_rst;
1425
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
1426 18 unneback
vl_cnt_gray_ce_bin
1427 6 unneback
    # ( .length(addr_width))
1428
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
1429 18 unneback
vl_cnt_gray_ce_bin
1430 6 unneback
    # (.length(addr_width))
1431 23 unneback
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
1432 7 unneback
vl_dpram_1r1w
1433 6 unneback
    # (.data_width(data_width), .addr_width(addr_width))
1434
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
1435
vl_fifo_cmp_async
1436
    # (.addr_width(addr_width))
1437
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
1438
endmodule
1439 8 unneback
module vl_fifo_2r2w_async (
1440 6 unneback
    // a side
1441
    a_d, a_wr, a_fifo_full,
1442
    a_q, a_rd, a_fifo_empty,
1443
    a_clk, a_rst,
1444
    // b side
1445
    b_d, b_wr, b_fifo_full,
1446
    b_q, b_rd, b_fifo_empty,
1447
    b_clk, b_rst
1448
    );
1449
parameter data_width = 18;
1450
parameter addr_width = 4;
1451
// a side
1452
input  [data_width-1:0] a_d;
1453
input                   a_wr;
1454
output                  a_fifo_full;
1455
output [data_width-1:0] a_q;
1456
input                   a_rd;
1457
output                  a_fifo_empty;
1458
input                   a_clk;
1459
input                   a_rst;
1460
// b side
1461
input  [data_width-1:0] b_d;
1462
input                   b_wr;
1463
output                  b_fifo_full;
1464
output [data_width-1:0] b_q;
1465
input                   b_rd;
1466
output                  b_fifo_empty;
1467
input                   b_clk;
1468
input                   b_rst;
1469
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
1470
vl_fifo_1r1w_async_a (
1471
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
1472
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
1473
    );
1474
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
1475
vl_fifo_1r1w_async_b (
1476
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
1477
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
1478
    );
1479
endmodule
1480 8 unneback
module vl_fifo_2r2w_async_simplex (
1481 6 unneback
    // a side
1482
    a_d, a_wr, a_fifo_full,
1483
    a_q, a_rd, a_fifo_empty,
1484
    a_clk, a_rst,
1485
    // b side
1486
    b_d, b_wr, b_fifo_full,
1487
    b_q, b_rd, b_fifo_empty,
1488
    b_clk, b_rst
1489
    );
1490
parameter data_width = 18;
1491
parameter addr_width = 4;
1492
// a side
1493
input  [data_width-1:0] a_d;
1494
input                   a_wr;
1495
output                  a_fifo_full;
1496
output [data_width-1:0] a_q;
1497
input                   a_rd;
1498
output                  a_fifo_empty;
1499
input                   a_clk;
1500
input                   a_rst;
1501
// b side
1502
input  [data_width-1:0] b_d;
1503
input                   b_wr;
1504
output                  b_fifo_full;
1505
output [data_width-1:0] b_q;
1506
input                   b_rd;
1507
output                  b_fifo_empty;
1508
input                   b_clk;
1509
input                   b_rst;
1510
// adr_gen
1511
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
1512
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
1513
// dpram
1514
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
1515 18 unneback
vl_cnt_gray_ce_bin
1516 6 unneback
    # ( .length(addr_width))
1517
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
1518 18 unneback
vl_cnt_gray_ce_bin
1519 6 unneback
    # (.length(addr_width))
1520
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
1521 18 unneback
vl_cnt_gray_ce_bin
1522 6 unneback
    # ( .length(addr_width))
1523
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
1524 18 unneback
vl_cnt_gray_ce_bin
1525 6 unneback
    # (.length(addr_width))
1526
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
1527
// mux read or write adr to DPRAM
1528
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
1529
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
1530 11 unneback
vl_dpram_2r2w
1531 6 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
1532
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
1533
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
1534 11 unneback
vl_fifo_cmp_async
1535 6 unneback
    # (.addr_width(addr_width))
1536
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
1537 11 unneback
vl_fifo_cmp_async
1538 6 unneback
    # (.addr_width(addr_width))
1539
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
1540
endmodule
1541 48 unneback
module vl_reg_file (
1542
    a1, a2, a3, wd3, we3, rd1, rd2, clk
1543
);
1544
parameter data_width = 32;
1545
parameter addr_width = 5;
1546
input [addr_width-1:0] a1, a2, a3;
1547
input [data_width-1:0] wd3;
1548
input we3;
1549
output [data_width-1:0] rd1, rd2;
1550
input clk;
1551
reg [data_width-1:0] wd3_reg;
1552
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
1553
reg we3_reg;
1554
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
1555
reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
1556
always @ (posedge clk or posedge rst)
1557
if (rst)
1558
    {wd3_reg, a3_reg, we3_reg} <= {(data_width+addr_width+1){1'b0}};
1559
else
1560
    {wd3_reg, a3_reg, we3_reg} <= {wd3,a3,wd3};
1561
    always @ (negedge clk)
1562
    if (we3_reg)
1563
        ram1[a3_reg] <= wd3;
1564
    always @ (posedge clk)
1565
        a1_reg <= a1;
1566
    assign rd1 = ram1[a1_reg];
1567
    always @ (negedge clk)
1568
    if (we3_reg)
1569
        ram2[a3_reg] <= wd3;
1570
    always @ (posedge clk)
1571
        a2_reg <= a2;
1572
    assign rd2 = ram2[a2_reg];
1573
endmodule
1574 12 unneback
//////////////////////////////////////////////////////////////////////
1575
////                                                              ////
1576
////  Versatile library, wishbone stuff                           ////
1577
////                                                              ////
1578
////  Description                                                 ////
1579
////  Wishbone compliant modules                                  ////
1580
////                                                              ////
1581
////                                                              ////
1582
////  To Do:                                                      ////
1583
////   -                                                          ////
1584
////                                                              ////
1585
////  Author(s):                                                  ////
1586
////      - Michael Unneback, unneback@opencores.org              ////
1587
////        ORSoC AB                                              ////
1588
////                                                              ////
1589
//////////////////////////////////////////////////////////////////////
1590
////                                                              ////
1591
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1592
////                                                              ////
1593
//// This source file may be used and distributed without         ////
1594
//// restriction provided that this copyright statement is not    ////
1595
//// removed from the file and that any derivative work contains  ////
1596
//// the original copyright notice and the associated disclaimer. ////
1597
////                                                              ////
1598
//// This source file is free software; you can redistribute it   ////
1599
//// and/or modify it under the terms of the GNU Lesser General   ////
1600
//// Public License as published by the Free Software Foundation; ////
1601
//// either version 2.1 of the License, or (at your option) any   ////
1602
//// later version.                                               ////
1603
////                                                              ////
1604
//// This source is distributed in the hope that it will be       ////
1605
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1606
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1607
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1608
//// details.                                                     ////
1609
////                                                              ////
1610
//// You should have received a copy of the GNU Lesser General    ////
1611
//// Public License along with this source; if not, download it   ////
1612
//// from http://www.opencores.org/lgpl.shtml                     ////
1613
////                                                              ////
1614
//////////////////////////////////////////////////////////////////////
1615
// async wb3 - wb3 bridge
1616
`timescale 1ns/1ns
1617 18 unneback
module vl_wb3wb3_bridge (
1618 12 unneback
        // wishbone slave side
1619
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
1620
        // wishbone master side
1621
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
1622
input [31:0] wbs_dat_i;
1623
input [31:2] wbs_adr_i;
1624
input [3:0]  wbs_sel_i;
1625
input [1:0]  wbs_bte_i;
1626
input [2:0]  wbs_cti_i;
1627
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
1628
output [31:0] wbs_dat_o;
1629 14 unneback
output wbs_ack_o;
1630 12 unneback
input wbs_clk, wbs_rst;
1631
output [31:0] wbm_dat_o;
1632
output reg [31:2] wbm_adr_o;
1633
output [3:0]  wbm_sel_o;
1634
output reg [1:0]  wbm_bte_o;
1635
output reg [2:0]  wbm_cti_o;
1636 14 unneback
output reg wbm_we_o;
1637
output wbm_cyc_o;
1638 12 unneback
output wbm_stb_o;
1639
input [31:0]  wbm_dat_i;
1640
input wbm_ack_i;
1641
input wbm_clk, wbm_rst;
1642
parameter addr_width = 4;
1643
// bte
1644
parameter linear       = 2'b00;
1645
parameter wrap4        = 2'b01;
1646
parameter wrap8        = 2'b10;
1647
parameter wrap16       = 2'b11;
1648
// cti
1649
parameter classic      = 3'b000;
1650
parameter incburst     = 3'b010;
1651
parameter endofburst   = 3'b111;
1652
parameter wbs_adr  = 1'b0;
1653
parameter wbs_data = 1'b1;
1654 33 unneback
parameter wbm_adr0      = 2'b00;
1655
parameter wbm_adr1      = 2'b01;
1656
parameter wbm_data      = 2'b10;
1657
parameter wbm_data_wait = 2'b11;
1658 12 unneback
reg [1:0] wbs_bte_reg;
1659
reg wbs;
1660
wire wbs_eoc_alert, wbm_eoc_alert;
1661
reg wbs_eoc, wbm_eoc;
1662
reg [1:0] wbm;
1663 14 unneback
wire [1:16] wbs_count, wbm_count;
1664 12 unneback
wire [35:0] a_d, a_q, b_d, b_q;
1665
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
1666
reg a_rd_reg;
1667
wire b_rd_adr, b_rd_data;
1668 14 unneback
wire b_rd_data_reg;
1669
wire [35:0] temp;
1670 12 unneback
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
1671
always @ (posedge wbs_clk or posedge wbs_rst)
1672
if (wbs_rst)
1673
        wbs_eoc <= 1'b0;
1674
else
1675
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
1676
                wbs_eoc <= wbs_bte_i==linear;
1677
        else if (wbs_eoc_alert & (a_rd | a_wr))
1678
                wbs_eoc <= 1'b1;
1679 18 unneback
vl_cnt_shreg_ce_clear # ( .length(16))
1680 12 unneback
    cnt0 (
1681
        .cke(wbs_ack_o),
1682
        .clear(wbs_eoc),
1683
        .q(wbs_count),
1684
        .rst(wbs_rst),
1685
        .clk(wbs_clk));
1686
always @ (posedge wbs_clk or posedge wbs_rst)
1687
if (wbs_rst)
1688
        wbs <= wbs_adr;
1689
else
1690
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & !a_fifo_full)
1691
                wbs <= wbs_data;
1692
        else if (wbs_eoc & wbs_ack_o)
1693
                wbs <= wbs_adr;
1694
// wbs FIFO
1695
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,wbs_bte_i,wbs_cti_i} : {wbs_dat_i,wbs_sel_i};
1696
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & !a_fifo_full :
1697
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
1698
              1'b0;
1699
assign a_rd = !a_fifo_empty;
1700
always @ (posedge wbs_clk or posedge wbs_rst)
1701
if (wbs_rst)
1702
        a_rd_reg <= 1'b0;
1703
else
1704
        a_rd_reg <= a_rd;
1705
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
1706
assign wbs_dat_o = a_q[35:4];
1707
always @ (posedge wbs_clk or posedge wbs_rst)
1708
if (wbs_rst)
1709 13 unneback
        wbs_bte_reg <= 2'b00;
1710 12 unneback
else
1711 13 unneback
        wbs_bte_reg <= wbs_bte_i;
1712 12 unneback
// wbm FIFO
1713
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
1714
always @ (posedge wbm_clk or posedge wbm_rst)
1715
if (wbm_rst)
1716
        wbm_eoc <= 1'b0;
1717
else
1718
        if (wbm==wbm_adr0 & !b_fifo_empty)
1719
                wbm_eoc <= b_q[4:3] == linear;
1720
        else if (wbm_eoc_alert & wbm_ack_i)
1721
                wbm_eoc <= 1'b1;
1722
always @ (posedge wbm_clk or posedge wbm_rst)
1723
if (wbm_rst)
1724
        wbm <= wbm_adr0;
1725
else
1726 33 unneback
/*
1727 12 unneback
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
1728
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
1729
        (wbm==wbm_adr1 & !wbm_we_o) |
1730
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
1731
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
1732 33 unneback
*/
1733
    case (wbm)
1734
    wbm_adr0:
1735
        if (!b_fifo_empty)
1736
            wbm <= wbm_adr1;
1737
    wbm_adr1:
1738
        if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
1739
            wbm <= wbm_data;
1740
    wbm_data:
1741
        if (wbm_ack_i & wbm_eoc)
1742
            wbm <= wbm_adr0;
1743
        else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
1744
            wbm <= wbm_data_wait;
1745
    wbm_data_wait:
1746
        if (!b_fifo_empty)
1747
            wbm <= wbm_data;
1748
    endcase
1749 12 unneback
assign b_d = {wbm_dat_i,4'b1111};
1750
assign b_wr = !wbm_we_o & wbm_ack_i;
1751
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
1752
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
1753
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
1754 33 unneback
                   (wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
1755 12 unneback
                   1'b0;
1756
assign b_rd = b_rd_adr | b_rd_data;
1757 18 unneback
vl_dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
1758
vl_dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
1759 12 unneback
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
1760 18 unneback
vl_cnt_shreg_ce_clear # ( .length(16))
1761 12 unneback
    cnt1 (
1762
        .cke(wbm_ack_i),
1763
        .clear(wbm_eoc),
1764
        .q(wbm_count),
1765
        .rst(wbm_rst),
1766
        .clk(wbm_clk));
1767 33 unneback
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
1768
assign wbm_stb_o = (wbm==wbm_data);
1769 12 unneback
always @ (posedge wbm_clk or posedge wbm_rst)
1770
if (wbm_rst)
1771
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
1772
else begin
1773
        if (wbm==wbm_adr0 & !b_fifo_empty)
1774
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
1775
        else if (wbm_eoc_alert & wbm_ack_i)
1776
                wbm_cti_o <= endofburst;
1777
end
1778
//async_fifo_dw_simplex_top
1779
vl_fifo_2r2w_async_simplex
1780
# ( .data_width(36), .addr_width(addr_width))
1781
fifo (
1782
    // a side
1783
    .a_d(a_d),
1784
    .a_wr(a_wr),
1785
    .a_fifo_full(a_fifo_full),
1786
    .a_q(a_q),
1787
    .a_rd(a_rd),
1788
    .a_fifo_empty(a_fifo_empty),
1789
    .a_clk(wbs_clk),
1790
    .a_rst(wbs_rst),
1791
    // b side
1792
    .b_d(b_d),
1793
    .b_wr(b_wr),
1794
    .b_fifo_full(b_fifo_full),
1795
    .b_q(b_q),
1796
    .b_rd(b_rd),
1797
    .b_fifo_empty(b_fifo_empty),
1798
    .b_clk(wbm_clk),
1799
    .b_rst(wbm_rst)
1800
    );
1801
endmodule
1802 39 unneback
module vl_wb3_arbiter_type1 (
1803
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
1804
    wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
1805
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
1806
    wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
1807
    wb_clk, wb_rst
1808
);
1809
parameter nr_of_ports = 3;
1810
parameter adr_size = 26;
1811
parameter adr_lo   = 2;
1812
parameter dat_size = 32;
1813
parameter sel_size = dat_size/8;
1814
localparam aw = (adr_size - adr_lo) * nr_of_ports;
1815
localparam dw = dat_size * nr_of_ports;
1816
localparam sw = sel_size * nr_of_ports;
1817
localparam cw = 3 * nr_of_ports;
1818
localparam bw = 2 * nr_of_ports;
1819
input  [dw-1:0] wbm_dat_o;
1820
input  [aw-1:0] wbm_adr_o;
1821
input  [sw-1:0] wbm_sel_o;
1822
input  [cw-1:0] wbm_cti_o;
1823
input  [bw-1:0] wbm_bte_o;
1824
input  [nr_of_ports-1:0] wbm_we_o, wbm_stb_o, wbm_cyc_o;
1825
output [dw-1:0] wbm_dat_i;
1826
output [nr_of_ports-1:0] wbm_ack_i, wbm_err_i, wbm_rty_i;
1827
output [dat_size-1:0] wbs_dat_i;
1828
output [adr_size-1:adr_lo] wbs_adr_i;
1829
output [sel_size-1:0] wbs_sel_i;
1830
output [2:0] wbs_cti_i;
1831
output [1:0] wbs_bte_i;
1832
output wbs_we_i, wbs_stb_i, wbs_cyc_i;
1833
input  [dat_size-1:0] wbs_dat_o;
1834
input  wbs_ack_o, wbs_err_o, wbs_rty_o;
1835
input wb_clk, wb_rst;
1836 44 unneback
reg  [nr_of_ports-1:0] select;
1837 39 unneback
wire [nr_of_ports-1:0] state;
1838
wire [nr_of_ports-1:0] eoc; // end-of-cycle
1839
wire [nr_of_ports-1:0] sel;
1840
wire idle;
1841
genvar i;
1842
assign idle = !(|state);
1843
generate
1844
if (nr_of_ports == 2) begin
1845
    wire [2:0] wbm1_cti_o, wbm0_cti_o;
1846
    assign {wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
1847 44 unneback
    //assign select = (idle) ? {wbm_cyc_o[1],!wbm_cyc_o[1] & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
1848
    always @ (idle or wbm_cyc_o)
1849
    if (idle)
1850
        casex (wbm_cyc_o)
1851
        2'b1x : select = 2'b10;
1852
        2'b01 : select = 2'b01;
1853
        default : select = {nr_of_ports{1'b0}};
1854
        endcase
1855
    else
1856
        select = {nr_of_ports{1'b0}};
1857 39 unneback
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
1858
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
1859
end
1860
endgenerate
1861
generate
1862
if (nr_of_ports == 3) begin
1863
    wire [2:0] wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
1864
    assign {wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
1865 44 unneback
    always @ (idle or wbm_cyc_o)
1866
    if (idle)
1867
        casex (wbm_cyc_o)
1868
        3'b1xx : select = 3'b100;
1869
        3'b01x : select = 3'b010;
1870
        3'b001 : select = 3'b001;
1871
        default : select = {nr_of_ports{1'b0}};
1872
        endcase
1873
    else
1874
        select = {nr_of_ports{1'b0}};
1875
//    assign select = (idle) ? {wbm_cyc_o[2],!wbm_cyc_o[2] & wbm_cyc_o[1],wbm_cyc_o[2:1]==2'b00 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
1876 39 unneback
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
1877
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
1878
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
1879
end
1880
endgenerate
1881
generate
1882 44 unneback
if (nr_of_ports == 4) begin
1883
    wire [2:0] wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
1884
    assign {wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
1885
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
1886
    always @ (idle or wbm_cyc_o)
1887
    if (idle)
1888
        casex (wbm_cyc_o)
1889
        4'b1xxx : select = 4'b1000;
1890
        4'b01xx : select = 4'b0100;
1891
        4'b001x : select = 4'b0010;
1892
        4'b0001 : select = 4'b0001;
1893
        default : select = {nr_of_ports{1'b0}};
1894
        endcase
1895
    else
1896
        select = {nr_of_ports{1'b0}};
1897
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
1898
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
1899
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
1900
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
1901
end
1902
endgenerate
1903
generate
1904
if (nr_of_ports == 5) begin
1905
    wire [2:0] wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
1906
    assign {wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
1907
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
1908
    always @ (idle or wbm_cyc_o)
1909
    if (idle)
1910
        casex (wbm_cyc_o)
1911
        5'b1xxxx : select = 5'b10000;
1912
        5'b01xxx : select = 5'b01000;
1913
        5'b001xx : select = 5'b00100;
1914
        5'b0001x : select = 5'b00010;
1915
        5'b00001 : select = 5'b00001;
1916
        default : select = {nr_of_ports{1'b0}};
1917
        endcase
1918
    else
1919
        select = {nr_of_ports{1'b0}};
1920
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
1921
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
1922
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
1923
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
1924
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
1925
end
1926
endgenerate
1927
generate
1928 39 unneback
for (i=0;i<nr_of_ports;i=i+1) begin
1929
    vl_spr sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));
1930
end
1931
endgenerate
1932
    assign sel = select | state;
1933
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i));
1934
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(adr_size-adr_lo)) mux1 ( .a(wbm_adr_o), .sel(sel), .dout(wbs_adr_i));
1935
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(sel_size)) mux2 ( .a(wbm_sel_o), .sel(sel), .dout(wbs_sel_i));
1936
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(3)) mux3 ( .a(wbm_cti_o), .sel(sel), .dout(wbs_cti_i));
1937
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(2)) mux4 ( .a(wbm_bte_o), .sel(sel), .dout(wbs_bte_i));
1938
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(1)) mux5 ( .a(wbm_we_o), .sel(sel), .dout(wbs_we_i));
1939
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(1)) mux6 ( .a(wbm_stb_o), .sel(sel), .dout(wbs_stb_i));
1940
    assign wbs_cyc_i = |sel;
1941
    assign wbm_dat_i = {nr_of_ports{wbs_dat_o}};
1942
    assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
1943
    assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
1944
    assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
1945
endmodule
1946 17 unneback
// WB ROM
1947 48 unneback
module vl_wb_b4_rom (
1948
    wb_adr_i, wb_stb_i, wb_cyc_i,
1949
    wb_dat_o, stall_o, wb_ack_o, wb_clk, wb_rst);
1950
    parameter dat_width = 32;
1951
    parameter dat_default = 32'h15000000;
1952
    parameter adr_width = 32;
1953
/*
1954
`ifndef ROM
1955
`define ROM "rom.v"
1956
`endif
1957
*/
1958
    input [adr_width-1:2]   wb_adr_i;
1959
    input                   wb_stb_i;
1960
    input                   wb_cyc_i;
1961
    output [dat_width-1:0]  wb_dat_o;
1962
    reg [dat_width-1:0]     wb_dat_o;
1963
    output                  wb_ack_o;
1964
    reg                     wb_ack_o;
1965
    output                  stall_o;
1966
    input                   wb_clk;
1967
    input                   wb_rst;
1968
always @ (posedge wb_clk or posedge wb_rst)
1969
    if (wb_rst)
1970
        wb_dat_o <= {dat_width{1'b0}};
1971
    else
1972
         case (wb_adr_i[adr_width-1:2])
1973
`ifdef ROM
1974
`include `ROM
1975
`endif
1976
           default:
1977
             wb_dat_o <= dat_default;
1978
         endcase // case (wb_adr_i)
1979
always @ (posedge wb_clk or posedge wb_rst)
1980
    if (wb_rst)
1981
        wb_ack_o <= 1'b0;
1982
    else
1983
        wb_ack_o <= wb_stb_i & wb_cyc_i;
1984
assign stall_o = 1'b0;
1985
endmodule
1986
// WB ROM
1987 18 unneback
module vl_wb_boot_rom (
1988 17 unneback
    wb_adr_i, wb_stb_i, wb_cyc_i,
1989 18 unneback
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
1990
    parameter adr_hi = 31;
1991
    parameter adr_lo = 28;
1992
    parameter adr_sel = 4'hf;
1993
    parameter addr_width = 5;
1994 33 unneback
/*
1995 17 unneback
`ifndef BOOT_ROM
1996
`define BOOT_ROM "boot_rom.v"
1997
`endif
1998 33 unneback
*/
1999 18 unneback
    input [adr_hi:2]    wb_adr_i;
2000
    input               wb_stb_i;
2001
    input               wb_cyc_i;
2002
    output [31:0]        wb_dat_o;
2003
    output              wb_ack_o;
2004
    output              hit_o;
2005
    input               wb_clk;
2006
    input               wb_rst;
2007
    wire hit;
2008
    reg [31:0] wb_dat;
2009
    reg wb_ack;
2010
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
2011 17 unneback
always @ (posedge wb_clk or posedge wb_rst)
2012
    if (wb_rst)
2013 18 unneback
        wb_dat <= 32'h15000000;
2014 17 unneback
    else
2015 18 unneback
         case (wb_adr_i[addr_width-1:2])
2016 33 unneback
`ifdef BOOT_ROM
2017 17 unneback
`include `BOOT_ROM
2018 33 unneback
`endif
2019 17 unneback
           /*
2020
            // Zero r0 and jump to 0x00000100
2021 18 unneback
 
2022
            1 : wb_dat <= 32'hA8200000;
2023
            2 : wb_dat <= 32'hA8C00100;
2024
            3 : wb_dat <= 32'h44003000;
2025
            4 : wb_dat <= 32'h15000000;
2026 17 unneback
            */
2027
           default:
2028 18 unneback
             wb_dat <= 32'h00000000;
2029 17 unneback
         endcase // case (wb_adr_i)
2030
always @ (posedge wb_clk or posedge wb_rst)
2031
    if (wb_rst)
2032 18 unneback
        wb_ack <= 1'b0;
2033 17 unneback
    else
2034 18 unneback
        wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
2035
assign hit_o = hit;
2036
assign wb_dat_o = wb_dat & {32{wb_ack}};
2037
assign wb_ack_o = wb_ack;
2038 17 unneback
endmodule
2039 32 unneback
module vl_wb_dpram (
2040
        // wishbone slave side a
2041
        wbsa_dat_i, wbsa_adr_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o,
2042
        wbsa_clk, wbsa_rst,
2043
        // wishbone slave side a
2044
        wbsb_dat_i, wbsb_adr_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o,
2045
        wbsb_clk, wbsb_rst);
2046
parameter data_width = 32;
2047
parameter addr_width = 8;
2048
parameter dat_o_mask_a = 1;
2049
parameter dat_o_mask_b = 1;
2050
input [31:0] wbsa_dat_i;
2051
input [addr_width-1:2] wbsa_adr_i;
2052
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
2053
output [31:0] wbsa_dat_o;
2054
output wbsa_ack_o;
2055
input wbsa_clk, wbsa_rst;
2056
input [31:0] wbsb_dat_i;
2057
input [addr_width-1:2] wbsb_adr_i;
2058
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
2059
output [31:0] wbsb_dat_o;
2060
output wbsb_ack_o;
2061
input wbsb_clk, wbsb_rst;
2062
wire wbsa_dat_tmp, wbsb_dat_tmp;
2063
vl_dpram_2r2w # (
2064 33 unneback
    .data_width(data_width), .addr_width(addr_width) )
2065 32 unneback
dpram0(
2066
    .d_a(wbsa_dat_i),
2067
    .q_a(wbsa_dat_tmp),
2068
    .adr_a(wbsa_adr_i),
2069
    .we_a(wbsa_we_i),
2070
    .clk_a(wbsa_clk),
2071
    .d_b(wbsb_dat_i),
2072
    .q_b(wbsb_dat_tmp),
2073
    .adr_b(wbsb_adr_i),
2074
    .we_b(wbsb_we_i),
2075
    .clk_b(wbsb_clk) );
2076 33 unneback
generate if (dat_o_mask_a==1)
2077 32 unneback
    assign wbsa_dat_o = wbsa_dat_tmp & {data_width{wbsa_ack_o}};
2078
endgenerate
2079 33 unneback
generate if (dat_o_mask_a==0)
2080 32 unneback
    assign wbsa_dat_o = wbsa_dat_tmp;
2081
endgenerate
2082 33 unneback
generate if (dat_o_mask_b==1)
2083 32 unneback
    assign wbsb_dat_o = wbsb_dat_tmp & {data_width{wbsb_ack_o}};
2084
endgenerate
2085 33 unneback
generate if (dat_o_mask_b==0)
2086 32 unneback
    assign wbsb_dat_o = wbsb_dat_tmp;
2087
endgenerate
2088
vl_spr ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
2089
vl_spr ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
2090
endmodule
2091 18 unneback
//////////////////////////////////////////////////////////////////////
2092
////                                                              ////
2093
////  Arithmetic functions                                        ////
2094
////                                                              ////
2095
////  Description                                                 ////
2096
////  Arithmetic functions for ALU and DSP                        ////
2097
////                                                              ////
2098
////                                                              ////
2099
////  To Do:                                                      ////
2100
////   -                                                          ////
2101
////                                                              ////
2102
////  Author(s):                                                  ////
2103
////      - Michael Unneback, unneback@opencores.org              ////
2104
////        ORSoC AB                                              ////
2105
////                                                              ////
2106
//////////////////////////////////////////////////////////////////////
2107
////                                                              ////
2108
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2109
////                                                              ////
2110
//// This source file may be used and distributed without         ////
2111
//// restriction provided that this copyright statement is not    ////
2112
//// removed from the file and that any derivative work contains  ////
2113
//// the original copyright notice and the associated disclaimer. ////
2114
////                                                              ////
2115
//// This source file is free software; you can redistribute it   ////
2116
//// and/or modify it under the terms of the GNU Lesser General   ////
2117
//// Public License as published by the Free Software Foundation; ////
2118
//// either version 2.1 of the License, or (at your option) any   ////
2119
//// later version.                                               ////
2120
////                                                              ////
2121
//// This source is distributed in the hope that it will be       ////
2122
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2123
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2124
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2125
//// details.                                                     ////
2126
////                                                              ////
2127
//// You should have received a copy of the GNU Lesser General    ////
2128
//// Public License along with this source; if not, download it   ////
2129
//// from http://www.opencores.org/lgpl.shtml                     ////
2130
////                                                              ////
2131
//////////////////////////////////////////////////////////////////////
2132
// signed multiplication
2133
module vl_mults (a,b,p);
2134
parameter operand_a_width = 18;
2135
parameter operand_b_width = 18;
2136
parameter result_hi = 35;
2137
parameter result_lo = 0;
2138
input [operand_a_width-1:0] a;
2139
input [operand_b_width-1:0] b;
2140
output [result_hi:result_lo] p;
2141
wire signed [operand_a_width-1:0] ai;
2142
wire signed [operand_b_width-1:0] bi;
2143
wire signed [operand_a_width+operand_b_width-1:0] result;
2144
    assign ai = a;
2145
    assign bi = b;
2146
    assign result = ai * bi;
2147
    assign p = result[result_hi:result_lo];
2148
endmodule
2149
module vl_mults18x18 (a,b,p);
2150
input [17:0] a,b;
2151
output [35:0] p;
2152
vl_mult
2153
    # (.operand_a_width(18), .operand_b_width(18))
2154
    mult0 (.a(a), .b(b), .p(p));
2155
endmodule
2156
// unsigned multiplication
2157
module vl_mult (a,b,p);
2158
parameter operand_a_width = 18;
2159
parameter operand_b_width = 18;
2160
parameter result_hi = 35;
2161
parameter result_lo = 0;
2162
input [operand_a_width-1:0] a;
2163
input [operand_b_width-1:0] b;
2164
output [result_hi:result_hi] p;
2165
wire [operand_a_width+operand_b_width-1:0] result;
2166
    assign result = a * b;
2167
    assign p = result[result_hi:result_lo];
2168
endmodule
2169
// shift unit
2170
// supporting the following shift functions
2171
//   SLL
2172
//   SRL
2173
//   SRA
2174
module vl_shift_unit_32( din, s, dout, opcode);
2175
input [31:0] din; // data in operand
2176
input [4:0] s; // shift operand
2177
input [1:0] opcode;
2178
output [31:0] dout;
2179
parameter opcode_sll = 2'b00;
2180
//parameter opcode_srl = 2'b01;
2181
parameter opcode_sra = 2'b10;
2182
//parameter opcode_ror = 2'b11;
2183
wire sll, sra;
2184
assign sll = opcode == opcode_sll;
2185
assign sra = opcode == opcode_sra;
2186
wire [15:1] s1;
2187
wire [3:0] sign;
2188
wire [7:0] tmp [0:3];
2189
// first stage is multiplier based
2190
// shift operand as fractional 8.7
2191
assign s1[15] = sll & s[2:0]==3'd7;
2192
assign s1[14] = sll & s[2:0]==3'd6;
2193
assign s1[13] = sll & s[2:0]==3'd5;
2194
assign s1[12] = sll & s[2:0]==3'd4;
2195
assign s1[11] = sll & s[2:0]==3'd3;
2196
assign s1[10] = sll & s[2:0]==3'd2;
2197
assign s1[ 9] = sll & s[2:0]==3'd1;
2198
assign s1[ 8] = s[2:0]==3'd0;
2199
assign s1[ 7] = !sll & s[2:0]==3'd1;
2200
assign s1[ 6] = !sll & s[2:0]==3'd2;
2201
assign s1[ 5] = !sll & s[2:0]==3'd3;
2202
assign s1[ 4] = !sll & s[2:0]==3'd4;
2203
assign s1[ 3] = !sll & s[2:0]==3'd5;
2204
assign s1[ 2] = !sll & s[2:0]==3'd6;
2205
assign s1[ 1] = !sll & s[2:0]==3'd7;
2206
assign sign[3] = din[31] & sra;
2207
assign sign[2] = sign[3] & (&din[31:24]);
2208
assign sign[1] = sign[2] & (&din[23:16]);
2209
assign sign[0] = sign[1] & (&din[15:8]);
2210
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte3 ( .a({sign[3], {8{sign[3]}},din[31:24], din[23:16]}), .b({1'b0,s1}), .p(tmp[3]));
2211
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte2 ( .a({sign[2], din[31:24]  ,din[23:16],  din[15:8]}), .b({1'b0,s1}), .p(tmp[2]));
2212
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte1 ( .a({sign[1], din[23:16]  ,din[15:8],   din[7:0]}), .b({1'b0,s1}), .p(tmp[1]));
2213
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte0 ( .a({sign[0], din[15:8]   ,din[7:0],    8'h00}),      .b({1'b0,s1}), .p(tmp[0]));
2214
// second stage is multiplexer based
2215
// shift on byte level
2216
// mux byte 3
2217
assign dout[31:24] = (s[4:3]==2'b00) ? tmp[3] :
2218
                     (sll & s[4:3]==2'b01) ? tmp[2] :
2219
                     (sll & s[4:3]==2'b10) ? tmp[1] :
2220
                     (sll & s[4:3]==2'b11) ? tmp[0] :
2221
                     {8{sign[3]}};
2222
// mux byte 2
2223
assign dout[23:16] = (s[4:3]==2'b00) ? tmp[2] :
2224
                     (sll & s[4:3]==2'b01) ? tmp[1] :
2225
                     (sll & s[4:3]==2'b10) ? tmp[0] :
2226
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
2227
                     (s[4:3]==2'b01) ? tmp[3] :
2228
                     {8{sign[3]}};
2229
// mux byte 1
2230
assign dout[15:8]  = (s[4:3]==2'b00) ? tmp[1] :
2231
                     (sll & s[4:3]==2'b01) ? tmp[0] :
2232
                     (sll & s[4:3]==2'b10) ? {8{1'b0}} :
2233
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
2234
                     (s[4:3]==2'b01) ? tmp[2] :
2235
                     (s[4:3]==2'b10) ? tmp[3] :
2236
                     {8{sign[3]}};
2237
// mux byte 0
2238
assign dout[7:0]   = (s[4:3]==2'b00) ? tmp[0] :
2239
                     (sll) ?  {8{1'b0}}:
2240
                     (s[4:3]==2'b01) ? tmp[1] :
2241
                     (s[4:3]==2'b10) ? tmp[2] :
2242
                     tmp[3];
2243
endmodule
2244
// logic unit
2245
// supporting the following logic functions
2246
//    a and b
2247
//    a or  b
2248
//    a xor b
2249
//    not b
2250
module vl_logic_unit( a, b, result, opcode);
2251
parameter width = 32;
2252
parameter opcode_and = 2'b00;
2253
parameter opcode_or  = 2'b01;
2254
parameter opcode_xor = 2'b10;
2255
input [width-1:0] a,b;
2256
output [width-1:0] result;
2257
input [1:0] opcode;
2258
assign result = (opcode==opcode_and) ? a & b :
2259
                (opcode==opcode_or)  ? a | b :
2260
                (opcode==opcode_xor) ? a ^ b :
2261
                b;
2262
endmodule

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